Chameleon

Chameleon Commit Details

Date:2011-05-25 17:38:33 (12 years 10 months ago)
Author:Kabyl
Commit:877
Parents: 876
Message:Make sure to use PCI device 00:0.0 when reading info from the memory controller, white-space cleanups in dram_controllers.c
Changes:
M/trunk/i386/libsaio/dram_controllers.c
M/trunk/i386/libsaio/pci_setup.c

File differences

trunk/i386/libsaio/dram_controllers.c
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␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
␉unsigned long did, vid;␊
␉int i;␊
␉␊
␊
␉// Nehalem supports Scrubbing␊
␉// First, locate the PCI bus where the MCH is located␊
␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
␉{␊
␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊
␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊
␉␉vid &= 0xFFFF;␊
␉␉did &= 0xFF00;␊
␉␉␊
␉{␊
␉␉case 0: mch_fsb = 1066; break;␊
␉␉case 1: mch_fsb = 533; break;␊
␉ default: ␊
␉␉default: ␊
␉␉case 2: mch_fsb = 800; break;␊
␉␉case 3: mch_fsb = 667; break;␉␉␊
␉␉case 4: mch_fsb = 1333; break;␊
␊
␉{ 0x8086, 0x1A30, "i845",␉NULL, NULL, NULL },␊
␉␊
␉{ 0x8086, 0x2970, "i946PL/GZ",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
␉{ 0x8086, 0x2990, "Q963/Q965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
␉{ 0x8086, 0x2970, "i946PL/GZ",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
␉{ 0x8086, 0x2990, "Q963/Q965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
␊
␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965, get_timings_im965 },␉␊
␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␊
␉{ 0x8086, 0x29B0, "Q35",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x29C0, "P35/G33",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x29D0, "Q33",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x29E0, "X38/X48",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␉␉␊
␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x2E30, "G41",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
␉␊
␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3400, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉ get_timings_nhm },␊
␉{ 0x8086, 0x3401, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3402, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3403, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3404, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3405, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3406, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3407, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉␊
␉{ 0x8086, 0x29B0, "Q35",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29C0, "P35/G33",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29D0, "Q33",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29E0, "X38/X48",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E30, "G41",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␊
␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3400, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3401, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3402, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3403, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3404, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3405, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3406, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3407, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
};␊
␊
static const char *memory_channel_types[] =␊
void scan_dram_controller(pci_dt_t *dram_dev)␊
{␊
␉int i;␊
␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)␊
␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)␊
␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) ␊
␉␉␉␉&& (dram_controllers[i].device == dram_dev->device_id))␊
␉␉{␊
␉␉␉␉␉␉memory_channel_types[Platform.RAM.Channels]␊
␉␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
␉␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
␉␉␉␉ );␊
␉␉␉␉␉);␊
␉␉␉/* getc();␊
␉␉␉ */␉␉␉␊
␉␉}␉␊
trunk/i386/libsaio/pci_setup.c
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␉␉switch (current->class_id)␊
␉␉{␊
␉␉␉case PCI_CLASS_BRIDGE_HOST:␊
␉␉␉␉␉dram_controller_dev = current;␊
␉␉␉␉␉if (current->dev.addr == PCIADDR(0, 0, 0))␊
␉␉␉␉␉␉dram_controller_dev = current;␊
␉␉␉␉break;␊
␉␉␉␉␊
␉␉␉case PCI_CLASS_NETWORK_ETHERNET: ␊

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