Chameleon

Chameleon Commit Details

Date:2011-05-25 23:10:55 (8 years 2 months ago)
Author:MacMan
Commit:878
Parents: 877
Message:Merge branch 'master' into Chimera Conflicts: CHANGES Makefile doc/BootHelp.txt i386/boot2/boot.c i386/boot2/boot.h i386/libsaio/SMBIOS.h i386/libsaio/acpi_patcher.c i386/libsaio/ati.c i386/libsaio/cpu.h i386/libsaio/platform.h i386/libsaio/smbios.c i386/libsaio/smbios_getters.c i386/libsaio/spd.c i386/modules/Resolution/Resolution.c
Changes:
D/branches/Chimera/i386/libsaio/SMBIOS.h
M/branches/Chimera/i386/libsa/libsa.h
M/branches/Chimera/i386/libsaio/dram_controllers.c
M/branches/Chimera/i386/libsaio/smbios_getters.c
M/branches/Chimera/version
M/branches/Chimera/i386/boot2/boot.h
M/branches/Chimera/i386/libsaio/pci_setup.c
M/branches/Chimera/CHANGES
M/branches/Chimera/i386/libsaio/smbios.c
M/branches/Chimera/i386/modules/Resolution/Resolution.c
M/branches/Chimera/i386/libsaio/ati.c
M/branches/Chimera/i386/libsa/string.c
M/branches/Chimera/revision
M/branches/Chimera/i386/libsaio/spd.c

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branches/Chimera/version
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branches/Chimera/i386/libsaio/SMBIOS.h
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/*
* Copyright (c) 1998-2009 Apple Computer, Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
*
* The contents of this file constitute Original Code as defined in and
* are subject to the Apple Public Source License Version 1.1 (the
* "License"). You may not use this file except in compliance with the
* License. Please obtain a copy of the License at
* http://www.apple.com/publicsource and read it before using this file.
*
* This Original Code and all software distributed under the License are
* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
* License for the specific language governing rights and limitations
* under the License.
*
* @APPLE_LICENSE_HEADER_END@
*/
#ifndef __LIBSAIO_SMBIOS_H
#define __LIBSAIO_SMBIOS_H
//
// Based on System Management BIOS Reference Specification v2.5
//
typedef uint8_t SMBString;
typedef uint8_t SMBByte;
typedef uint16_t SMBWord;
typedef uint32_t SMBDWord;
typedef uint64_t SMBQWord;
typedef struct DMIEntryPoint {
SMBByte anchor[5];
SMBByte checksum;
SMBWord tableLength;
SMBDWord tableAddress;
SMBWord structureCount;
SMBByte bcdRevision;
} __attribute__((packed)) DMIEntryPoint;
typedef struct SMBEntryPoint {
SMBByte anchor[4];
SMBByte checksum;
SMBByte entryPointLength;
SMBByte majorVersion;
SMBByte minorVersion;
SMBWord maxStructureSize;
SMBByte entryPointRevision;
SMBByte formattedArea[5];
DMIEntryPoint dmi;
} __attribute__((packed)) SMBEntryPoint;
//
// Header common to all SMBIOS structures
//
typedef struct SMBStructHeader {
SMBByte type;
SMBByte length;
SMBWord handle;
} __attribute__((packed)) SMBStructHeader;
#define SMB_STRUCT_HEADER SMBStructHeader header;
typedef struct SMBAnchor
{
const SMBStructHeader *header;
const uint8_t *next;
const uint8_t *end;
} SMBAnchor;
#define SMB_ANCHOR_IS_VALID(x)\
((x) && ((x)->header) && ((x)->next) && ((x)->end))
#define SMB_ANCHOR_RESET(x)\
bzero(x, sizeof(typedef struct SMBAnchor));
//
// SMBIOS structure types.
//
enum {
kSMBTypeBIOSInformation = 0,
kSMBTypeSystemInformation = 1,
kSMBTypeBaseBoard= 2,
kSMBTypeSystemEnclosure = 3,
kSMBTypeProcessorInformation = 4,
kSMBTypeMemoryModule = 6,
kSMBTypeCacheInformation = 7,
kSMBTypeSystemSlot = 9,
kSMBTypePhysicalMemoryArray = 16,
kSMBTypeMemoryDevice = 17,
kSMBType32BitMemoryErrorInfo = 18,
kSMBType64BitMemoryErrorInfo = 33,
kSMBTypeEndOfTable = 127,
/* Apple Specific Structures */
kSMBTypeFirmwareVolume = 128,
kSMBTypeMemorySPD = 130,
kSMBTypeOemProcessorType = 131,
kSMBTypeOemProcessorBusSpeed = 132
};
//
// BIOS Information (Type 0)
//
typedef struct SMBBIOSInformation {
SMB_STRUCT_HEADER // Type 0
SMBString vendor; // BIOS vendor name
SMBString version; // BIOS version
SMBWord startSegment; // BIOS segment start
SMBString releaseDate; // BIOS release date
SMBByte romSize; // (n); 64K * (n+1) bytes
SMBQWord characteristics; // supported BIOS functions
} __attribute__((packed)) SMBBIOSInformation;
//
// System Information (Type 1)
//
typedef struct SMBSystemInformation {
// 2.0+ spec (8 bytes)
SMB_STRUCT_HEADER // Type 1
SMBString manufacturer;
SMBString productName;
SMBString version;
SMBString serialNumber;
// 2.1+ spec (25 bytes)
SMBByte uuid[16]; // can be all 0 or all 1's
SMBByte wakeupReason; // reason for system wakeup
// 2.4+ spec (27 bytes)
SMBString skuNumber;
SMBString family;
} __attribute__((packed)) SMBSystemInformation;
//
// Base Board (Type 2)
//
typedef struct SMBBaseBoard {
SMB_STRUCT_HEADER // Type 2
SMBStringmanufacturer;
SMBStringproduct;
SMBStringversion;
SMBStringserialNumber;
SMBStringassetTagNumber;
SMBBytefeatureFlags;
SMBStringlocationInChassis;
SMBWordchassisHandle;
SMBByteboardType;
SMBBytenumberOfContainedHandles;
// 0 - 255 contained handles go here but we do not include
// them in our structure. Be careful to use numberOfContainedHandles
// times sizeof(SMBWord) when computing the actual record size,
// if you need it.
} __attribute__((packed)) SMBBaseBoard;
// Values for boardType in Type 2 records
enum {
kSMBBaseBoardUnknown= 0x01,
kSMBBaseBoardOther= 0x02,
kSMBBaseBoardServerBlade= 0x03,
kSMBBaseBoardConnectivitySwitch= 0x04,
kSMBBaseBoardSystemMgmtModule= 0x05,
kSMBBaseBoardProcessorModule= 0x06,
kSMBBaseBoardIOModule= 0x07,
kSMBBaseBoardMemoryModule= 0x08,
kSMBBaseBoardDaughter= 0x09,
kSMBBaseBoardMotherboard= 0x0A,
kSMBBaseBoardProcessorMemoryModule= 0x0B,
kSMBBaseBoardProcessorIOModule= 0x0C,
kSMBBaseBoardInterconnect= 0x0D,
};
//
// System Enclosure (Type 3)
//
typedef struct SMBSystemEnclosure {
SMB_STRUCT_HEADER // Type 3
SMBString manufacturer;
SMBByte type;
SMBString version;
SMBString serialNumber;
SMBString assetTagNumber;
SMBByte bootupState;
SMBByte powerSupplyState;
SMBByte thermalState;
SMBByte securityStatus;
SMBDWord oemDefined;
} __attribute__((packed)) SMBSystemEnclosure;
//
// Processor Information (Type 4)
//
typedef struct SMBProcessorInformation {
// 2.0+ spec (26 bytes)
SMB_STRUCT_HEADER // Type 4
SMBString socketDesignation;
SMBByte processorType; // CPU = 3
SMBByte processorFamily; // processor family enum
SMBString manufacturer;
SMBQWord processorID; // based on CPUID
SMBString processorVersion;
SMBByte voltage; // bit7 cleared indicate legacy mode
SMBWord externalClock; // external clock in MHz
SMBWord maximumClock; // max internal clock in MHz
SMBWord currentClock; // current internal clock in MHz
SMBByte status;
SMBByte processorUpgrade; // processor upgrade enum
// 2.1+ spec (32 bytes)
SMBWord L1CacheHandle;
SMBWord L2CacheHandle;
SMBWord L3CacheHandle;
// 2.3+ spec (35 bytes)
SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
} __attribute__((packed)) SMBProcessorInformation;
#define kSMBProcessorInformationMinSize 26
//
// Memory Module Information (Type 6)
// Obsoleted since SMBIOS version 2.1
//
typedef struct SMBMemoryModule {
SMB_STRUCT_HEADER // Type 6
SMBString socketDesignation;
SMBByte bankConnections;
SMBByte currentSpeed;
SMBWord currentMemoryType;
SMBByte installedSize;
SMBByte enabledSize;
SMBByte errorStatus;
} __attribute__((packed)) SMBMemoryModule;
#define kSMBMemoryModuleSizeNotDeterminable 0x7D
#define kSMBMemoryModuleSizeNotEnabled 0x7E
#define kSMBMemoryModuleSizeNotInstalled 0x7F
//
// Cache Information (Type 7)
//
typedef struct SMBCacheInformation {
SMB_STRUCT_HEADER // Type 7
SMBString socketDesignation;
SMBWord cacheConfiguration;
SMBWord maximumCacheSize;
SMBWord installedSize;
SMBWord supportedSRAMType;
SMBWord currentSRAMType;
SMBByte cacheSpeed;
SMBByte errorCorrectionType;
SMBByte systemCacheType;
SMBByte associativity;
} __attribute__((packed)) SMBCacheInformation;
typedef struct SMBSystemSlot {
// 2.0+ spec (12 bytes)
SMB_STRUCT_HEADER // Type 9
SMBString slotDesignation;
SMBByte slotType;
SMBByte slotDataBusWidth;
SMBByte currentUsage;
SMBByte slotLength;
SMBWord slotID;
SMBByte slotCharacteristics1;
// 2.1+ spec (13 bytes)
SMBByte slotCharacteristics2;
} __attribute__((packed)) SMBSystemSlot;
//
// Physical Memory Array (Type 16)
//
typedef struct SMBPhysicalMemoryArray {
// 2.1+ spec (15 bytes)
SMB_STRUCT_HEADER // Type 16
SMBByte physicalLocation; // physical location
SMBByte arrayUse; // the use for the memory array
SMBByte errorCorrection; // error correction/detection method
SMBDWord maximumCapacity; // maximum memory capacity in kilobytes
SMBWord errorHandle; // handle of a previously detected error
SMBWord numMemoryDevices; // number of memory slots or sockets
} __attribute__((packed)) SMBPhysicalMemoryArray;
// Memory Array - Use
enum {
kSMBMemoryArrayUseOther = 0x01,
kSMBMemoryArrayUseUnknown = 0x02,
kSMBMemoryArrayUseSystemMemory = 0x03,
kSMBMemoryArrayUseVideoMemory = 0x04,
kSMBMemoryArrayUseFlashMemory = 0x05,
kSMBMemoryArrayUseNonVolatileMemory = 0x06,
kSMBMemoryArrayUseCacheMemory = 0x07
};
// Memory Array - Error Correction Types
enum {
kSMBMemoryArrayErrorCorrectionTypeOther = 0x01,
kSMBMemoryArrayErrorCorrectionTypeUnknown = 0x02,
kSMBMemoryArrayErrorCorrectionTypeNone = 0x03,
kSMBMemoryArrayErrorCorrectionTypeParity = 0x04,
kSMBMemoryArrayErrorCorrectionTypeSingleBitECC = 0x05,
kSMBMemoryArrayErrorCorrectionTypeMultiBitECC = 0x06,
kSMBMemoryArrayErrorCorrectionTypeCRC = 0x07
};
//
// Memory Device (Type 17)
//
typedef struct SMBMemoryDevice {
// 2.1+ spec (21 bytes)
SMB_STRUCT_HEADER // Type 17
SMBWord arrayHandle; // handle of the parent memory array
SMBWord errorHandle; // handle of a previously detected error
SMBWord totalWidth; // total width in bits; including ECC bits
SMBWord dataWidth; // data width in bits
SMBWord memorySize; // bit15 is scale, 0 = MB, 1 = KB
SMBByte formFactor; // memory device form factor
SMBByte deviceSet; // parent set of identical memory devices
SMBString deviceLocator; // labeled socket; e.g. "SIMM 3"
SMBString bankLocator; // labeled bank; e.g. "Bank 0" or "A"
SMBByte memoryType; // type of memory
SMBWord memoryTypeDetail; // additional detail on memory type
// 2.3+ spec (27 bytes)
SMBWord memorySpeed; // speed of device in MHz (0 for unknown)
SMBString manufacturer;
SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
} __attribute__((packed)) SMBMemoryDevice;
//
// Firmware Volume Description (Apple Specific - Type 128)
//
enum {
FW_REGION_RESERVED = 0,
FW_REGION_RECOVERY = 1,
FW_REGION_MAIN = 2,
FW_REGION_NVRAM = 3,
FW_REGION_CONFIG = 4,
FW_REGION_DIAGVAULT = 5,
NUM_FLASHMAP_ENTRIES = 8
};
typedef struct FW_REGION_INFO
{
SMBDWord StartAddress;
SMBDWord EndAddress;
} __attribute__((packed)) FW_REGION_INFO;
typedef struct SMBFirmwareVolume {
SMB_STRUCT_HEADER // Type 128
SMBByte RegionCount;
SMBByte Reserved[3];
SMBDWord FirmwareFeatures;
SMBDWord FirmwareFeaturesMask;
SMBByte RegionType[ NUM_FLASHMAP_ENTRIES ];
FW_REGION_INFO FlashMap[ NUM_FLASHMAP_ENTRIES ];
} __attribute__((packed)) SMBFirmwareVolume;
//
// Memory SPD Data (Apple Specific - Type 130)
//
typedef struct SMBMemorySPD {
SMB_STRUCT_HEADER // Type 130
SMBWord Type17Handle;
SMBWord Offset;
SMBWord Size;
SMBWord Data[];
} __attribute__((packed)) SMBMemorySPD;
static const char *
SMBMemoryDeviceTypes[] =
{
"RAM", /* 00h Undefined */
"RAM", /* 01h Other */
"RAM", /* 02h Unknown */
"DRAM", /* 03h DRAM */
"EDRAM", /* 04h EDRAM */
"VRAM", /* 05h VRAM */
"SRAM", /* 06h SRAM */
"RAM", /* 07h RAM */
"ROM", /* 08h ROM */
"FLASH", /* 09h FLASH */
"EEPROM", /* 0Ah EEPROM */
"FEPROM", /* 0Bh FEPROM */
"EPROM", /* 0Ch EPROM */
"CDRAM", /* 0Dh CDRAM */
"3DRAM", /* 0Eh 3DRAM */
"SDRAM", /* 0Fh SDRAM */
"SGRAM", /* 10h SGRAM */
"RDRAM", /* 11h RDRAM */
"DDR SDRAM", /* 12h DDR */
"DDR2 SDRAM", /* 13h DDR2 */
"DDR2 FB-DIMM", /* 14h DDR2 FB-DIMM */
"RAM",/* 15h unused */
"RAM",/* 16h unused */
"RAM",/* 17h unused */
"DDR3",/* 18h DDR3, chosen in [5776134] */
};
static const int
kSMBMemoryDeviceTypeCount = sizeof(SMBMemoryDeviceTypes) /
sizeof(SMBMemoryDeviceTypes[0]);
//
// OEM Processor Type (Apple Specific - Type 131)
//
typedef struct SMBOemProcessorType {
SMB_STRUCT_HEADER
SMBWord ProcessorType;
} __attribute__((packed)) SMBOemProcessorType;
//
// OEM Processor Bus Speed (Apple Specific - Type 132)
//
typedef struct SMBOemProcessorBusSpeed {
SMB_STRUCT_HEADER
SMBWord ProcessorBusSpeed; // MT/s unit
} __attribute__((packed)) SMBOemProcessorBusSpeed;
//----------------------------------------------------------------------------------------------------------
/* From Foundation/Efi/Guid/Smbios/SmBios.h */
/* Modified to wrap Data4 array init with {} */
#define EFI_SMBIOS_TABLE_GUID {0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
#define SMBIOS_ORIGINAL0
#define SMBIOS_PATCHED1
extern void *getSmbios(int which);
extern void readSMBIOSInfo(SMBEntryPoint *eps);
extern void setupSMBIOSTable(void);
extern void decodeSMBIOSTable(SMBEntryPoint *eps);
#endif /* !__LIBSAIO_SMBIOS_H */
branches/Chimera/i386/libsaio/spd.c
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static struct smbus_controllers_t smbus_controllers[] = {
{0x8086, 0x269B, "ESB2", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x24C3, "ICH4", read_smb_intel },
{0x8086, 0x24D3, "ICH5", read_smb_intel },
{0x8086, 0x266A, "ICH6", read_smb_intel },
{0x8086, 0x27DA, "ICH7", read_smb_intel },
{0x8086, 0x283E, "ICH8", read_smb_intel },
{0x8086, 0x2930, "ICH9", read_smb_intel },
{0x8086, 0x3A30, "ICH10R", read_smb_intel },
{0x8086, 0x3A60, "ICH10B", read_smb_intel },
{0x8086, 0x3B30, "5 Series", read_smb_intel },
{0x8086, 0x1C22, "6 Series", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel }
{0x8086, 0x269B, "ESB2",read_smb_intel },
{0x8086, 0x25A4, "6300ESB",read_smb_intel },
{0x8086, 0x24C3, "ICH4",read_smb_intel },
{0x8086, 0x24D3, "ICH5",read_smb_intel },
{0x8086, 0x266A, "ICH6",read_smb_intel },
{0x8086, 0x27DA, "ICH7",read_smb_intel },
{0x8086, 0x283E, "ICH8",read_smb_intel },
{0x8086, 0x2930, "ICH9",read_smb_intel },
{0x8086, 0x3A30, "ICH10R",read_smb_intel },
{0x8086, 0x3A60, "ICH10B",read_smb_intel },
{0x8086, 0x3B30, "5 Series",read_smb_intel },
{0x8086, 0x1C22, "6 Series",read_smb_intel },
{0x8086, 0x5032, "EP80579",read_smb_intel }
};
branches/Chimera/i386/libsaio/dram_controllers.c
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static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);
vid &= 0xFFFF;
did &= 0xFF00;
{
case 0: mch_fsb = 1066; break;
case 1: mch_fsb = 533; break;
default:
default:
case 2: mch_fsb = 800; break;
case 3: mch_fsb = 667; break;
case 4: mch_fsb = 1333; break;
{ 0x8086, 0x1A30, "i845",NULL, NULL, NULL },
{ 0x8086, 0x2970, "i946PL/GZ",setup_p35, get_fsb_i965, get_timings_i965 },
{ 0x8086, 0x2990, "Q963/Q965",setup_p35, get_fsb_i965, get_timings_i965 },
{ 0x8086, 0x29A0, "P965/G965",setup_p35, get_fsb_i965, get_timings_i965 },
{ 0x8086, 0x2970, "i946PL/GZ",setup_p35, get_fsb_i965,get_timings_i965},
{ 0x8086, 0x2990, "Q963/Q965",setup_p35, get_fsb_i965,get_timings_i965},
{ 0x8086, 0x29A0, "P965/G965",setup_p35, get_fsb_i965,get_timings_i965},
{ 0x8086, 0x2A00, "GM965/GL960",setup_p35, get_fsb_im965, get_timings_im965 },
{ 0x8086, 0x2A10, "GME965/GLE960",setup_p35, get_fsb_im965, get_timings_im965 },
{ 0x8086, 0x2A40, "PM/GM45/47",setup_p35, get_fsb_im965, get_timings_im965 },
{ 0x8086, 0x2A00, "GM965/GL960",setup_p35, get_fsb_im965,get_timings_im965},
{ 0x8086, 0x2A10, "GME965/GLE960",setup_p35, get_fsb_im965,get_timings_im965},
{ 0x8086, 0x2A40, "PM/GM45/47",setup_p35, get_fsb_im965,get_timings_im965},
{ 0x8086, 0x29B0, "Q35",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x29C0, "P35/G33",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x29D0, "Q33",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x29E0, "X38/X48",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E00, "Eaglelake",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E10, "Q45/Q43",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E20, "P45/G45",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0x2E30, "G41",setup_p35, get_fsb_i965, get_timings_p35 },
{ 0x8086, 0xD131, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0xD132, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3400, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3401, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3402, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3403, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3404, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3405, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3406, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x3407, "NHM IMC",setup_nhm, get_fsb_nhm, get_timings_nhm },
{ 0x8086, 0x29B0, "Q35",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x29C0, "P35/G33",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x29D0, "Q33",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x29E0, "X38/X48",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x2E00, "Eaglelake",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x2E10, "Q45/Q43",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x2E20, "P45/G45",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x2E30, "G41",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0xD131, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0xD132, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3400, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3401, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3402, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3403, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3404, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3405, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3406, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
{ 0x8086, 0x3407, "NHM IMC",setup_nhm, get_fsb_nhm,get_timings_nhm},
};
static const char *memory_channel_types[] =
void scan_dram_controller(pci_dt_t *dram_dev)
{
int i;
for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)
for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)
if ((dram_controllers[i].vendor == dram_dev->vendor_id)
&& (dram_controllers[i].device == dram_dev->device_id))
{
memory_channel_types[Platform.RAM.Channels]
,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS
,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS
);
);
/* getc();
*/
}
branches/Chimera/i386/libsaio/ati.c
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{ 0x6718,0x0B001002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x31301682,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x67181002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6738,0x67381002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870",kDuckweed},
{ 0x6739,0x67391002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6739,0x21F81458,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6759,0xE193174B,CHIP_FAMILY_TURKS,"AMD Radeon HD 6570",kNull},
/* standard/default models */
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6900 Series",kNull},
/* Northen Islands */
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970 Series",kNull},
{ 0x6719,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6950 Series",kNull},
{ 0x6738,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870 Series",kDuckweed},
{ 0x6739,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850 Series",kDuckweed},
{ 0x673E,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6790 Series",kNull},
{ 0x6758,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6670 Series",kNull},
{ 0x6759,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6500 Series",kNull},
{ 0x6770,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6400 Series",kNull},
{ 0x6779,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6450 Series",kNull},
{ 0x0000,0x00000000,CHIP_FAMILY_UNKNOW,NULL,kNull}
};
branches/Chimera/i386/libsaio/pci_setup.c
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switch (current->class_id)
{
case PCI_CLASS_BRIDGE_HOST:
dram_controller_dev = current;
if (current->dev.addr == PCIADDR(0, 0, 0))
dram_controller_dev = current;
break;
case PCI_CLASS_NETWORK_ETHERNET:
branches/Chimera/i386/libsaio/smbios.c
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char**defaultValue;
} SMBValueSetter;
SMBValueSetter SMBSetters[] =
{
SMBValueSetter SMBSetters[] =
{
//-------------------------------------------------------------------------------------------------------------------------
// BIOSInformation
//-------------------------------------------------------------------------------------------------------------------------
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, product),kSMBBaseBoardProductKey,
NULL,&defaultBaseBoard.product},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, version),NULL,NULL,NULL},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, version),NULL,NULL,NULL},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, serialNumber),NULL,NULL,NULL},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, serialNumber),NULL,NULL,NULL},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, assetTagNumber),NULL,NULL,NULL},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, assetTagNumber),NULL,NULL,NULL},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, locationInChassis),NULL,NULL,NULL},
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, locationInChassis),NULL,NULL,NULL},
//-------------------------------------------------------------------------------------------------------------------------
defaultSystemInfo.productName= kDefaultiMacSandy;
defaultSystemInfo.family= kDefaultiMacFamily;
break;
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X7500
defaultBIOSInfo.version= kDefaultMacProNehalemBIOSVersion;
uint8_t *stringPtr = (uint8_t *)structHeader + structHeader->length;
if (!field)
return (char *)0;
return NULL;
for (field--; field != 0 && strlen((char *)stringPtr) > 0;
field--, stringPtr = (uint8_t *)((uint32_t)stringPtr + strlen((char *)stringPtr) + 1));
strSize = strlen(string);
// remove any spaces found at the end
while ((string[strSize - 1] == ' ') && strSize != 0)
while ((strSize != 0) && (string[strSize - 1] == ' '))
strSize--;
if (strSize == 0)
{
SMBOemProcessorBusSpeed *p = (SMBOemProcessorBusSpeed *)structPtr->new;
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
break;
default:
return;
}
}
}
p->header.type= kSMBTypeOemProcessorBusSpeed;
p->header.length= sizeof(SMBOemProcessorBusSpeed);
p->header.handle= handle++;
memcpy((void *)structPtr->new, structPtr->orig, structPtr->orig->length);
for (i = 0; i < numOfSetters; i++)
if (structPtr->orig->type == SMBSetters[i].type)
if ((structPtr->orig->type == SMBSetters[i].type) && (SMBSetters[i].fieldOffset < structPtr->orig->length))
{
setterFound = true;
setSMBValue(structPtr, i, (returnType *)((uint8_t *)structPtr->new + SMBSetters[i].fieldOffset));
tableLength += structSize;
if (structSize > maxStructSize)
if (structSize > maxStructSize)
maxStructSize = structSize;
structureCount++;
case kSMBTypeMemoryDevice:
Platform.DMI.CntMemorySlots++;
if (((SMBMemoryDevice *)structHeader)->memorySize != 0)
if (((SMBMemoryDevice *)structHeader)->memorySize != 0)
Platform.DMI.MemoryModules++;
if (((SMBMemoryDevice *)structHeader)->memorySpeed > 0)
if (((SMBMemoryDevice *)structHeader)->memorySpeed > 0)
Platform.RAM.DIMM[dimmnbr].Frequency = ((SMBMemoryDevice *)structHeader)->memorySpeed;
dimmnbr++;
break;
branches/Chimera/i386/libsaio/smbios_getters.c
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}
}
//return false;
value->string = NOT_AVAILABLE;
return true;
return false;
//value->string = NOT_AVAILABLE;
//return true;
}
bool getSMBMemoryDeviceSerialNumber(returnType *value)
}
}
//return false;
value->string = NOT_AVAILABLE;
return true;
return false;
//value->string = NOT_AVAILABLE;
//return true;
}
bool getSMBMemoryDevicePartNumber(returnType *value)
}
}
//return false;
value->string = NOT_AVAILABLE;
return true;
return false;
//value->string = NOT_AVAILABLE;
//return true;
}
branches/Chimera/i386/boot2/boot.h
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#define kSMBIOSdefaults"SMBIOSdefaults"/* smbios_patcher.c */
#define kDefaultPartition"Default Partition"/* sys.c */
#define kUSBBusFix"USBBusFix"/* usb.c */
#define kEHCIacquire"EHCIacquire"/* usb.c */
#define kUHCIreset"UHCIreset"/* usb.c */
#define kLegacyOff"USBLegacyOff"/* usb.c */
#define kEHCIhard"EHCIhard"/* usb.c */
#define kDefaultPartition"Default Partition"/* sys.c */
/*
* Flags to the booter or kernel
branches/Chimera/i386/modules/Resolution/Resolution.c
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*/
#include "915resolution.h"
#include "gui.h"
void Resolution_start()
{
UInt32 bp = 0;
UInt32 x, y;
patchVideoBios();
getResolution(&x, &y, &bp);
gui.screen.width = x;
gui.screen.height = y;
}
branches/Chimera/i386/libsa/libsa.h
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/*
* ctype stuff (aserebln)
*/
static inline int isupper(char c)
static inline int isupper(int c)
{
return (c >= 'A' && c <= 'Z');
}
static inline int islower(char c)
static inline int islower(int c)
{
return (c >= 'a' && c <= 'z');
}
static inline int isalpha(char c)
static inline int isalpha(int c)
{
return ((c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z'));
}
static inline int isascii(char c)
static inline int isascii(int c)
{
return ( (c >= 0x20) && (c < 0x7f) );
}
static inline int isspace(char c)
static inline int isspace(int c)
{
return (c == ' ' || c == '\t' || c == '\n' || c == '\12');
}
static inline int isdigit(char c)
static inline int isdigit(int c)
{
return (c >= '0' && c <= '9');
}
static inline int isxdigit(char c)
static inline int isxdigit(int c)
{
return ((c >= '0' && c <= '9') || (c >= 'A' && c <= 'F') || (c >= 'a' && c <= 'f'));
}
//Azi: TODO - add more ponctuation characters as needed; at least these two, i need for PartNo.
static inline int ispunct(char c)
static inline int ispunct(int c)
{
return (c == '.' || c == '-');
}
extern void * memset(void * dst, int c, size_t n);
extern void * memcpy(void * dst, const void * src, size_t len);
extern int memcmp(const void * p1, const void * p2, int len);
extern int memcmp(const void * p1, const void * p2, size_t len);
extern int strcmp(const char * s1, const char * s2);
extern int strncmp(const char * s1, const char * s2, size_t n);
extern char * strcpy(char * s1, const char * s2);
branches/Chimera/i386/libsa/string.c
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/* NOTE: Moved from ntfs.c */
int
memcmp(const void *p1, const void *p2, int len)
memcmp(const void *p1, const void *p2, size_t len)
{
while (len--) {
if (*(const char*)(p1++) != *(const char*)(p2++))
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- Added new ATi/AMD Graphics Card Enabler.
- Added new SMBIOS patcher.
- Added module system.
- Added the BOOT2_MAX_LENGTH constant in memory.h. This is now used in moot.c to relocate the correct number of bytes for boot2.
- Added new ATi/AMD Graphics Card Enabler.
- Added new SMBIOS patcher.
- Added module system.
- Added automatic P-States & C-States generation for native power management.
- Added Booter Log Dump Tool
- Added Booter message Logging (":/boot-log" ioreg property)

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Revision: 878