Chameleon

Chameleon Commit Details

Date:2011-06-06 17:39:13 (8 years 5 months ago)
Author:Azimutz
Commit:982
Parents: 981
Message:Modules folder up to date...
Changes:
D/branches/azimutz/Chazi/i386/modules/include/types.h
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.h
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/IntelGraphicsEnabler.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Cconfig
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ATiGraphicsEnabler.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/GraphicsEnabler.txt
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati_reg.h
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/Cconfig
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.h
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Cconfig
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Cconfig
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/AMDGraphicsEnabler.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/gma.c
A/branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/gma.h
M/branches/azimutz/Chazi/i386/modules/Makefile
M/branches/azimutz/Chazi/i386/modules/Resolution/include/edid.h
M/branches/azimutz/Chazi/i386/modules/Resolution/915resolution.c
M/branches/azimutz/Chazi/i386/modules/Resolution/915resolution.h
M/branches/azimutz/Chazi/i386/modules/uClibcxx/Makefile
M/branches/azimutz/Chazi/i386/modules/klibc/Makefile
M/branches/azimutz/Chazi/i386/modules/Cconfig
M/branches/azimutz/Chazi/i386/modules/Resolution/Makefile
M/branches/azimutz/Chazi/i386/modules/Resolution/edid.c

File differences

branches/azimutz/Chazi/i386/modules/uClibcxx/Makefile
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MODULE_NAME = uClibc++
MODULE_NAME = uClibcxx
MODULE_DESCRIPTION = This module provides a minimalistic c++ runtime library for use in other modules. This does not provide functionality by itself, instead it is used to allow for the c++ language to be used in other modules. Please note that rtti and exceptions has both been disabled.
MODULE_AUTHOR =
MODULE_VERSION = "0.2.2"
MODULE_COMPAT_VERSION = "0.2.2"
MODULE_START = _uClibcxx_start
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES = klibc
DIR = uClibc++
utility.o valarray.o vector.o support.o \
ios.o iostream.o istream.o ostream.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR) -Iinclude
ifneq "" "$(wildcard /bin/mkdirs)"
MKDIRS = /bin/mkdirs
else
MKDIRS = /bin/mkdir -p
endif
AS = as
LD = ld
# LIBS= -lc_static
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme: dylib
include ../MakeInc.dir
branches/azimutz/Chazi/i386/modules/Resolution/915resolution.c
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#ifndef _RESOLUTION_H_
#define _RESOLUTION_H_
#include "libsaio.h"
#include "edid.h"
//#include "libsaio.h"
//#include "edid.h" //included
#include "915resolution.h"
UInt32 x = 0, y = 0, bp = 0;
getResolution(&x, &y, &bp);
verbose("getResolution: %dx%dx%d\n", (int)x, (int)y, (int)bp);
if (x != 0 &&
y != 0 &&
bp != 0)
if((id & 0x0000FFFF) == 0x00008086) // Intel chipset
{
//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);
//getc();
//getchar();
type = CT_UNKNOWN_INTEL;
//type = CT_UNKNOWN;
int i = 0;
while (i < 512)
{ // we don't need to look through the whole bios, just the firs 512 bytes
{ // we don't need to look through the whole bios, just the first 512 bytes
if ((map->bios_ptr[i] == 'N')
&& (map->bios_ptr[i+1] == 'V')
&& (map->bios_ptr[i+2] == 'I')
char* edidInfo = readEDID();
if(!edidInfo) return 1;
mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];
//Slice
if(!fb_parse_edid((struct EDID *)edidInfo, mode))
{
free( edidInfo );
return 1;
}
/*mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];
mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];
mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];
mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);
mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);
*/
free( edidInfo );
if(!mode->h_active) return 1;
//for (i=0; i < map->mode_table_size; i++) {
//if (map->mode_table[0].mode == mode) {
switch(map->bios) {
case BT_INTEL:
return;
case BT_1:
{
vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);
branches/azimutz/Chazi/i386/modules/Resolution/include/edid.h
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* Created by Evan Lojewski on 12/1/09.
* Copyright 2009. All rights reserved.
*
* Slice 2010, based on Joblo works
*/
//#ifndef __EDID_H__
//#define __EDID_H__
#ifndef _EDID_H_
#define _EDID_H_
#include "libsaio.h"
#define EDID_BLOCK_SIZE128
#define EDID_V1_BLOCKS_TO_GO_OFFSET 126
//Slice - some more info about EDID
#define EDID_LENGTH0x80
#define EDID_HEADER0x00
#define EDID_HEADER_END0x07
#define ID_MANUFACTURER_NAME0x08
#define ID_MANUFACTURER_NAME_END0x09
#define ID_MODEL0x0a
#define ID_SERIAL_NUMBER0x0c
#define MANUFACTURE_WEEK0x10
#define MANUFACTURE_YEAR0x11
#define EDID_STRUCT_VERSION0x12
#define EDID_STRUCT_REVISION0x13
#define EDID_STRUCT_DISPLAY 0x14
#define DPMS_FLAGS0x18
#define ESTABLISHED_TIMING_10x23
#define ESTABLISHED_TIMING_20x24
#define MANUFACTURERS_TIMINGS0x25
/* standard timings supported */
#define STD_TIMING 8
#define STD_TIMING_DESCRIPTION_SIZE 2
#define STD_TIMING_DESCRIPTIONS_START 0x26
#define DETAILED_TIMING_DESCRIPTIONS_START0x36
#define DETAILED_TIMING_DESCRIPTION_SIZE18
#define NO_DETAILED_TIMING_DESCRIPTIONS4
#define DETAILED_TIMING_DESCRIPTION_10x36
#define DETAILED_TIMING_DESCRIPTION_20x48
#define DETAILED_TIMING_DESCRIPTION_30x5a
#define DETAILED_TIMING_DESCRIPTION_40x6c
#define DESCRIPTOR_DATA5
#define UPPER_NIBBLE( x ) \
(((128|64|32|16) & (x)) >> 4)
#define LOWER_NIBBLE( x ) \
((1|2|4|8) & (x))
#define COMBINE_HI_8LO( hi, lo ) \
( (((unsigned)hi) << 8) | (unsigned)lo )
#define COMBINE_HI_4LO( hi, lo ) \
( (((unsigned)hi) << 4) | (unsigned)lo )
#define PIXEL_CLOCK_LO (unsigned)block[ 0 ]
#define PIXEL_CLOCK_HI (unsigned)block[ 1 ]
#define PIXEL_CLOCK (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
#define H_ACTIVE_LO (unsigned)block[ 2 ]
#define H_BLANKING_LO (unsigned)block[ 3 ]
#define H_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 4 ] )
#define H_ACTIVE COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
#define H_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 4 ] )
#define H_BLANKING COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
#define V_ACTIVE_LO (unsigned)block[ 5 ]
#define V_BLANKING_LO (unsigned)block[ 6 ]
#define V_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 7 ] )
#define V_ACTIVE COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
#define V_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 7 ] )
#define V_BLANKING COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
#define H_SYNC_OFFSET_LO (unsigned)block[ 8 ]
#define H_SYNC_WIDTH_LO (unsigned)block[ 9 ]
#define V_SYNC_OFFSET_LO UPPER_NIBBLE( (unsigned)block[ 10 ] )
#define V_SYNC_WIDTH_LO LOWER_NIBBLE( (unsigned)block[ 10 ] )
#define V_SYNC_WIDTH_HI ((unsigned)block[ 11 ] & (1|2))
#define V_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (4|8)) >> 2)
#define H_SYNC_WIDTH_HI (((unsigned)block[ 11 ] & (16|32)) >> 4)
#define H_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (64|128)) >> 6)
#define V_SYNC_WIDTH COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
#define V_SYNC_OFFSET COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
#define H_SYNC_WIDTH COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
#define H_SYNC_OFFSET COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
#define H_SIZE_LO (unsigned)block[ 12 ]
#define V_SIZE_LO (unsigned)block[ 13 ]
#define H_SIZE_HI UPPER_NIBBLE( (unsigned)block[ 14 ] )
#define V_SIZE_HI LOWER_NIBBLE( (unsigned)block[ 14 ] )
#define H_SIZE COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
#define V_SIZE COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
#define H_BORDER (unsigned)block[ 15 ]
#define V_BORDER (unsigned)block[ 16 ]
#define FLAGS (unsigned)block[ 17 ]
#define INTERLACED (FLAGS&128)
#define SYNC_TYPE (FLAGS&3<<3)/* bits 4,3 */
#define SYNC_SEPARATE (3<<3)
#define HSYNC_POSITIVE (FLAGS & 4)
#define VSYNC_POSITIVE (FLAGS & 2)
#define V_MIN_RATE block[ 5 ]
#define V_MAX_RATE block[ 6 ]
#define H_MIN_RATE block[ 7 ]
#define H_MAX_RATE block[ 8 ]
#define MAX_PIXEL_CLOCK (((int)block[ 9 ]) * 10)
#define GTF_SUPPORTblock[10]
#define DPMS_ACTIVE_OFF(1 << 5)
#define DPMS_SUSPEND(1 << 6)
#define DPMS_STANDBY(1 << 7)
struct EDID
{
UInt8header[8];//0
UInt8vendorProduct[4];//8
UInt8serialNumber[4];//12
UInt8weekOfManufacture;//16
UInt8yearOfManufacture;//17
UInt8version;//18
UInt8revision;//19
UInt8displayParams[5];//20
UInt8colorCharacteristics[10];//25
UInt8establishedTimings[3];//35
UInt16standardTimings[8];//38
UInt8detailedTimings[72];//54
UInt8extension;//126
UInt8checksum;//127
};
typedef struct _edid_mode {
unsigned short pixel_clock;
unsigned short h_active;
unsigned short h_blanking;
unsigned short v_active;
unsigned short v_blanking;
unsigned short h_sync_offset;
unsigned short h_sync_width;
unsigned short v_sync_offset;
unsigned short v_sync_width;
} edid_mode;
char* readEDID();
void getResolution(UInt32* x, UInt32* y, UInt32* bp);
int fb_parse_edid(struct EDID *edid, edid_mode* var);
int getEDID( void * edidBlock, UInt8 block);
void getResolution(UInt32* x, UInt32* y, UInt32* bp);
#endif /* _EDID_H_ */
//#endif
branches/azimutz/Chazi/i386/modules/Resolution/edid.c
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*
* Created by Evan Lojewski on 12/1/09.
* Copyright 2009. All rights reserved.
*
*
*Slice 2010, based on Joblo works
*/
//#include "libsaio.h"
#include "edid.h"
#include "vbe.h"
#include "graphics.h"
#include "boot.h"
//----------------------------------------------------------------------------------
#define FBMON_FIX_HEADER 1
#define FBMON_FIX_INPUT 2
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
//----------------------------------------------------------------------------------
/*
struct broken_edid {
const char manufacturer[4];
UInt32 model;
UInt32 fix;
};
//----------------------------------------------------------------------------------
broken_edid brokendb[] = {
// DEC FR-PCXAV-YZ *
{ "DEC", 0x073a, FBMON_FIX_HEADER,},
// ViewSonic PF775a *
{ "VSC", 0x5a44, FBMON_FIX_INPUT,}
};
//----------------------------------------------------------------------------------
*/
const unsigned char edid_v1_header[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
//----------------------------------------------------------------------------------
int edid_compare(unsigned char *edid1, unsigned char *edid2)
{
int result = 0;
unsigned char *block = edid1 + ID_MANUFACTURER_NAME, manufacturer1[4], manufacturer2[4];;
manufacturer1[0] = ((block[0] & 0x7c) >> 2) + '@';
manufacturer1[1] = ((block[0] & 0x03) << 3) + ((block[1] & 0xe0) >> 5) + '@';
manufacturer1[2] = (block[1] & 0x1f) + '@';
manufacturer1[3] = 0;
block = edid2 + ID_MANUFACTURER_NAME;
manufacturer2[0] = ((block[0] & 0x7c) >> 2) + '@';
manufacturer2[1] = ((block[0] & 0x03) << 3) + ((block[1] & 0xe0) >> 5) + '@';
manufacturer2[2] = (block[1] & 0x1f) + '@';
manufacturer2[3] = 0;
int x;
for(x = 0; x < 4; x++)
{
if(manufacturer1[x] == manufacturer2[x])
result++;
}
return result;
}
int check_edid(unsigned char *edid)
{
unsigned char *block = edid + ID_MANUFACTURER_NAME, manufacturer[4];
//unsigned char *b;
UInt32 model;
//int i, fix = 0, ret = 0;
manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@';
manufacturer[1] = ((block[0] & 0x03) << 3) +
((block[1] & 0xe0) >> 5) + '@';
manufacturer[2] = (block[1] & 0x1f) + '@';
manufacturer[3] = 0;
model = block[2] + (block[3] << 8);
/*
for (i = 0; i < (int)ARRAY_SIZE(brokendb); i++) {
if (!strncmp((const char *)manufacturer, brokendb[i].manufacturer, 4) &&
brokendb[i].model == model) {
DEBG("ATIFB: The EDID Block of "
"Manufacturer: %s Model: 0x%08lx is known to "
"be broken,\n", manufacturer, model);
fix = brokendb[i].fix;
break;
}
}
switch (fix) {
case FBMON_FIX_HEADER:
for (i = 0; i < 8; i++) {
if (edid[i] != edid_v1_header[i])
ret = fix;
}
break;
case FBMON_FIX_INPUT:
b = edid + EDID_STRUCT_DISPLAY;
/// Only if display is GTF capable will
//the input type be reset to analog *
if (b[4] & 0x01 && b[0] & 0x80)
ret = fix;
break;
}
*/
return 0; //ret;
}
//----------------------------------------------------------------------------------
static void fix_edid(unsigned char *edid, int fix)
{
unsigned char *b;
switch (fix) {
case FBMON_FIX_HEADER:
msglog("EDID: trying a header reconstruct\n");
memcpy(edid, edid_v1_header, 8);
break;
case FBMON_FIX_INPUT:
msglog("EDID: trying to fix input type\n");
b = edid + EDID_STRUCT_DISPLAY;
b[0] &= ~0x80;
edid[127] += 0x80;
}
}
//----------------------------------------------------------------------------------
int edid_checksum(unsigned char *edid)
{
unsigned char i, csum = 0, all_null = 0;
int err = 0, fix = check_edid(edid);
if (fix)
fix_edid(edid, fix);
for (i = 0; i < EDID_LENGTH; i++) {
csum += edid[i];
all_null |= edid[i];
}
if (csum == 0x00 && all_null) {
/* checksum passed, everything's good */
err = 1;
}
return err;
}
//----------------------------------------------------------------------------------
static int edid_check_header(unsigned char *edid)
{
int i, err = 1, fix = check_edid(edid);
if (fix)
fix_edid(edid, fix);
for (i = 0; i < 8; i++) {
if (edid[i] != edid_v1_header[i])
err = 0;
}
return err;
}
//------------------------------------------------------------------------
bool verifyEDID(unsigned char *edid)
{
if (edid == NULL || !edid_checksum(edid) ||!edid_check_header(edid))
{
return false;
}
return true;
}
int edid_is_timing_block(unsigned char *block)
{
if ((block[0] != 0x00) || (block[1] != 0x00) ||
(block[2] != 0x00) || (block[4] != 0x00))
return 1;
else
return 0;
}
//----------------------------------------------------------------------------------
int fb_parse_edid(struct EDID *edid, edid_mode* var) //(struct EDID *edid, UInt32* x, UInt32* y)
{
int i;
unsigned char *block;
if(!verifyEDID((unsigned char *)edid)) return 1;
block = (unsigned char *)edid + DETAILED_TIMING_DESCRIPTIONS_START; //54
for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) {
if (edid_is_timing_block(block)) {
var->h_active = H_ACTIVE;
var->v_active = V_ACTIVE;
var->h_sync_offset = H_SYNC_OFFSET;
var->h_sync_width = H_SYNC_WIDTH;
var->h_blanking = H_BLANKING;
var->v_blanking = V_BLANKING;
var->pixel_clock = PIXEL_CLOCK;
var->h_sync_width = H_SYNC_WIDTH;
var->v_sync_width = V_SYNC_WIDTH;
/*
var->xres = var->xres_virtual = H_ACTIVE;
var->yres = var->yres_virtual = V_ACTIVE;
var->height = var->width = -1;
var->right_margin = H_SYNC_OFFSET;
var->left_margin = (H_ACTIVE + H_BLANKING) -
(H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
var->upper_margin = V_BLANKING - V_SYNC_OFFSET -
V_SYNC_WIDTH;
var->lower_margin = V_SYNC_OFFSET;
var->hsync_len = H_SYNC_WIDTH;
var->vsync_len = V_SYNC_WIDTH;
var->pixclock = PIXEL_CLOCK;
var->pixclock /= 1000;
var->pixclock = KHZ2PICOS(var->pixclock);
if (HSYNC_POSITIVE)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (VSYNC_POSITIVE)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
*/
return 1;
}
}
return 0;
}
void getResolution(UInt32* x, UInt32* y, UInt32* bp)
{
//int val;
static UInt32 xResolution, yResolution, bpResolution;
/*
if(getIntForKey(kScreenWidth, &val, &bootInfo->bootConfig))
{
xResolution = val;
}
if(getIntForKey(kScreenHeight, &val, &bootInfo->bootConfig))
{
yResolution = val;
}
*/
bpResolution = 32;// assume 32bits
bpResolution = 32;// assume 32bits
if(!xResolution || !yResolution || !bpResolution)
{
char* edidInfo = readEDID();
if(!edidInfo) return;
edid_mode mode;
// TODO: check *all* resolutions reported and either use the highest, or the native resolution (if there is a flag for that)
xResolution = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
yResolution = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
//xResolution = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
//yResolution = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
//Slice - done here
//printf("H Active = %d", edidInfo[56] | ((edidInfo[58] & 0xF0) << 4) );
//printf("V Active = %d", edidInfo[59] | ((edidInfo[61] & 0xF0) << 4) );
if(fb_parse_edid((struct EDID *)edidInfo, &mode) == 0)
{
xResolution = DEFAULT_SCREEN_WIDTH;
yResolution = DEFAULT_SCREEN_HEIGHT;
}
else {
xResolution = mode.h_active;
yResolution = mode.v_active;
}
/*
0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x32 0x0C
0x00 0xDF 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0x00
0x0C 0xDF 0x00 0x00 0x12 0x03 0x21 0x78 0xE9 0x99
0x53 0x28 0xFF 0xFF 0x32 0xDF 0x00 0x12 0x80 0x78
0xD5 0x53 0x26 0x00 0x01 0x01 0x01 0x01 0xFF 0x00
0xDF 0x00 0x03 0x78 0x99 0x28 0x00 0x01 0x01 0x01
0x01 0x21 0x84 0x20 0xFF 0x0C 0x00 0x03 0x0A 0x53
0x54 0x01 0x01 0x01 0xDE 0x84 0x56 0x00 0xA0 0x30
0xFF 0xDF 0x12 0x78 0x53 0x00 0x01 0x01 0x01 0x84
0x00 0x18 0x84 0x00 0x00 0x57 0xFF 0x00 0x80 0x99
0x54 0x01 0x01 0x21 0x20 0x00 0x50 0x00 0x00 0x35
0x57 0xFE 0x00 0x00 0x78 0x28 0x01 0x01 0x21 0x20
0x18 0x30 0x00 0x57 0x34 0xFE 0xAA 0x9A
*/
//msglog("H Active = %d ", edidInfo[56] | ((edidInfo[58] & 0xF0) << 4) );
//msglog("V Active = %d \n", edidInfo[59] | ((edidInfo[61] & 0xF0) << 4) );
free( edidInfo );
if(!xResolution) xResolution = DEFAULT_SCREEN_WIDTH;
if(!yResolution) yResolution = DEFAULT_SCREEN_HEIGHT;
//if(!xResolution) xResolution = DEFAULT_SCREEN_WIDTH;
//if(!yResolution) yResolution = DEFAULT_SCREEN_HEIGHT;
}
SInt16 status;
UInt16 blocks_left = 1;
//msglog("readEDID\n");
do
{
// TODO: This currently only retrieves the *last* block, make the block buffer expand as needed / calculated from the first block
status = getEDID(edidInfo, blocks_left);
//printf("Buffer location: 0x%X\n", SEG(buffer) << 16 | OFF(buffer));
/*
msglog("Buffer location: 0x%X status: %d\n", SEG(edidInfo) << 16 | OFF(edidInfo), status);
int j, i;
for (j = 0; j < 8; j++) {
for(i = 0; i < 16; i++) printf("0x%X ", ebiosInfo[((i+1) * (j + 1)) - 1]);
for(i = 0; i < 16; i++) msglog("0x%02X ", edidInfo[((i+1) * (j + 1)) - 1]);
msglog("\n");
}
printf("\n");
*/
if(status == 0)
{
//if( edidInfo[0] == 0x00 || edidInfo[0] == 0xFF)
if ( reported > blocks_left )
{
printf("EDID claims %d more blocks left\n", reported);
msglog("EDID claims %d more blocks left\n", reported);
}
if ( (last_reported <= reported && last_reported != -1)
//|| reported == MAGIC
)
{
printf("Last reported %d\n", last_reported);
printf( "EDID blocks left is wrong.\n"
msglog("Last reported %d\n", last_reported);
msglog( "EDID blocks left is wrong.\n"
"Your EDID is probably invalid.\n");
return 0;
}
}
else
{
printf("Invalid block %d\n", blocks_left);
printf("Header1 = %d", memcmp(edidInfo, header1, sizeof(header1)) );
printf("Header2 = %d", memcmp(edidInfo, header2, sizeof(header2)) );
msglog("Invalid block %d\n", blocks_left);
msglog("Header1 = %d", memcmp(edidInfo, header1, sizeof(header1)) );
msglog("Header2 = %d", memcmp(edidInfo, header2, sizeof(header2)) );
return 0;
}
}
bios( &bb );
return(bb.eax.r.h);
}
branches/azimutz/Chazi/i386/modules/Resolution/915resolution.h
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*/
#ifndef __RESOLUTION_H
#define __RESOLUTION_H
#include "shortatombios.h"
#include "edid.h"
#ifndef __RESOLUTION_H
#define __RESOLUTION_H
//Slice - moved to edid.h
/*
typedef struct _edid_mode {
unsigned short pixel_clock;
unsigned short h_active;
unsigned short v_sync_offset;
unsigned short v_sync_width;
} edid_mode;
*/
void patchVideoBios();
typedef enum {
BT_UNKNOWN, BT_1, BT_2, BT_3, BT_ATI_1, BT_ATI_2, BT_NVDA
BT_UNKNOWN, BT_1, BT_2, BT_3, BT_ATI_1, BT_ATI_2, BT_NVDA, BT_INTEL
} bios_type;
branches/azimutz/Chazi/i386/modules/Resolution/Makefile
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MODULE_NAME = Resolution
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = This module reads the edid information from the monitor attached to the main display. The module will also patch the vesa modes available in pre intel hd graphics cards to provide proper resolution while booting.
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
MODULE_OBJS = Resolution.o edid.o 915resolution.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
ifneq "" "$(wildcard /bin/mkdirs)"
MKDIRS = /bin/mkdirs
else
MKDIRS = /bin/mkdir -p
endif
AS = as
LD = ld
# LIBS= -lc_static
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme: dylib
include ../MakeInc.dir
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#ifndef _TYPES_H_
#define _TYPES_H_
typedef unsigned char UInt8;
typedef signed char SInt8;
typedef unsigned short UInt16;
typedef signed short SInt16;
typedef unsigned int UInt32;
typedef signed int SInt32;
typedef unsigned long long UInt64;
typedef signed long long SInt64;
#endif /* _TYPES_H_ */
branches/azimutz/Chazi/i386/modules/klibc/Makefile
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MODULE_NAME = klibc
MODULE_DESCRIPTION = This module provides a standard c library for modules to link to if the library provided by chameleon is insufficient. This is currently only used by the uClibc++ library.
MODULE_AUTHOR =
MODULE_VERSION = "1.5.20"
MODULE_COMPAT_VERSION = "1.5.20"
MODULE_START = _$(MODULE_NAME)_start
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = klibc
__lshrdi3.o __moddi3.o __modsi3.o __udivdi3.o \
__udivmoddi4.o __udivmodsi4.o __udivsi3.o \
__umoddi3.o __umodsi3.o \
strntoumax.o strntoimax.o atoi.o atol.o atoll.o \
strcasecmp.o strncasecmp.o strdup.o strlcat.o strndup.o strnlen.o \
strntoumax.o strntoimax.o atol.o atoll.o \
strcasecmp.o strncasecmp.o strlcat.o strndup.o strnlen.o \
strsep.o strtoimax.o strtok_r.o strtok.o strtol.o strtoll.o strtotimespec.o strtotimeval.o \
strtoul.o strtoull.o strtoumax.o strxspn.o strpbrk.o \
bsearch.o calloc.o \
qsort.o sha1hash.o onexit.o atexit.o exit.o \
snprintf.o vsnprintf.o sscanf.o vsscanf.o\
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
ifneq "" "$(wildcard /bin/mkdirs)"
MKDIRS = /bin/mkdirs
else
MKDIRS = /bin/mkdir -p
endif
AS = as
LD = ld
# LIBS= -lc_static
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme: dylib
include ../MakeInc.dir
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source "i386/modules/klibc/Cconfig"
source "i386/modules/uClibcxx/Cconfig"
source "i386/modules/HelloWorld/Cconfig"
source "i386/modules/GraphicsEnabler/AMDGraphicsEnabler/Cconfig"
source "i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Cconfig"
source "i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Cconfig"
source "i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Cconfig"
endmenu
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.h
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/*
*NVidia injector
*
*Copyright (C) 2009Jasmin Fazlic, iNDi
*
*NVidia injector is free software: you can redistribute it and/or modify
*it under the terms of the GNU General Public License as published by
*the Free Software Foundation, either version 3 of the License, or
*(at your option) any later version.
*
*NVidia driver and injector is distributed in the hope that it will be useful,
*but WITHOUT ANY WARRANTY; without even the implied warranty of
*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*GNU General Public License for more details.
*
*You should have received a copy of the GNU General Public License
*along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __LIBSAIO_NVIDIA_H
#define __LIBSAIO_NVIDIA_H
bool setup_nvidia_devprop(pci_dt_t *nvda_dev);
struct nv_chipsets_t {
unsigned device;
char *name;
};
#define DCB_MAX_NUM_ENTRIES 16
#define DCB_MAX_NUM_I2C_ENTRIES 16
#define DCB_LOC_ON_CHIP 0
struct bios {
uint16_tsignature;/* 0x55AA */
uint8_tsize;/* Size in multiples of 512 */
};
#define NV_PROM_OFFSET0x300000
#define NV_PROM_SIZE0x0000ffff
#define NV_PRAMIN_OFFSET0x00700000
#define NV_PRAMIN_SIZE0x00100000
#define NV04_PFB_FIFO_DATA0x0010020c
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK0xfff00000
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT20
#define NVC0_MEM_CTRLR_COUNT0x00121c74
#define NVC0_MEM_CTRLR_RAM_AMOUNT0x0010f20c
#define NV_PBUS_PCI_NV_200x00001850
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED(0 << 0)
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED(1 << 0)
#define REG8(reg)((volatile uint8_t *)regs)[(reg)]
#define REG16(reg)((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg)((volatile uint32_t *)regs)[(reg) >> 2]
#define NV_ARCH_030x03
#define NV_ARCH_040x04
#define NV_ARCH_100x10
#define NV_ARCH_200x20
#define NV_ARCH_300x30
#define NV_ARCH_400x40
#define NV_ARCH_500x50
#define NV_ARCH_C00xC0
#define CHIPSET_NV030x0010
#define CHIPSET_NV040x0020
#define CHIPSET_NV100x0100
#define CHIPSET_NV110x0110
#define CHIPSET_NV150x0150
#define CHIPSET_NV170x0170
#define CHIPSET_NV180x0180
#define CHIPSET_NFORCE0x01A0
#define CHIPSET_NFORCE20x01F0
#define CHIPSET_NV200x0200
#define CHIPSET_NV250x0250
#define CHIPSET_NV280x0280
#define CHIPSET_NV300x0300
#define CHIPSET_NV310x0310
#define CHIPSET_NV340x0320
#define CHIPSET_NV350x0330
#define CHIPSET_NV360x0340
#define CHIPSET_NV400x0040
#define CHIPSET_NV410x00C0
#define CHIPSET_NV430x0140
#define CHIPSET_NV440x0160
#define CHIPSET_NV44A0x0220
#define CHIPSET_NV450x0210
#define CHIPSET_NV500x0190
#define CHIPSET_NV840x0400
#define CHIPSET_MISC_BRIDGED0x00F0
#define CHIPSET_G700x0090
#define CHIPSET_G710x0290
#define CHIPSET_G720x01D0
#define CHIPSET_G730x0390
// integrated GeForces (6100, 6150)
#define CHIPSET_C510x0240
// variant of C51, seems based on a G70 design
#define CHIPSET_C5120x03D0
#define CHIPSET_G73_BRIDGED0x02E0
#endif /* !__LIBSAIO_NVIDIA_H */
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
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/*
*NVIDIAGraphicsEnabler Module
*Enables many nVidia cards to be used out of the box in OS X.
*This was converted from boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "nvidia.h"
#include "modules.h"
#define kGraphicsEnablerKey "GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void NVIDIAGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_NVIDIA))
{
verbose("NVIDIA VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_nvidia_devprop(current);
}
else
verbose("[%04x:%04x] :: %s, is not a NVIDIA VGA Controller.\n",
current->vendor_id, current->device_id, devicepath);
}
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Cconfig
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#
# Chameleon Modules
#
config NVIDIAGRAPHICSENABLER_MODULE
tristate "NVIDIAGraphicsEnabler Module"
default m
---help---
Say Y here if you want to enable the use of this module.
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Readme.txt
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Module:GraphicsEnabler
Description: the GraphicsEnabler nVidia code ported to a module.
If your card is supported and you find it missing
on this code, please file an issue at:
http://forge.voodooprojects.org/p/chameleon/issues/
Only cards known to work will be added.
Dependencies: none
Keys: GraphicsEnablerYes/No (enabled by default)
Disable GraphicsEnabler patch.
UseNvidiaROMYes/No (disabled by default)
Enable the use of a custom VBIOS ROM image.
VBIOSYes/No (disabled by default)
Adds "vbios" property to ioreg. ??? Azi: confirm
Adaptation of Meklort's work.
TODO: review "nv_chipsets_t NVKnownChipsets"
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.c
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/*
*NVidia injector
*
*Copyright (C) 2009Jasmin Fazlic, iNDi
*
*NVidia injector is free software: you can redistribute it and/or modify
*it under the terms of the GNU General Public License as published by
*the Free Software Foundation, either version 3 of the License, or
*(at your option) any later version.
*
*NVidia driver and injector is distributed in the hope that it will be useful,
*but WITHOUT ANY WARRANTY; without even the implied warranty of
*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*GNU General Public License for more details.
*
*You should have received a copy of the GNU General Public License
*along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "nvidia.h"
#ifndef DEBUG_NVIDIA
#define DEBUG_NVIDIA 0
#endif
#if DEBUG_NVIDIA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseNvidiaROM"UseNvidiaROM"
#define kVBIOS"VBIOS"
#define NVIDIA_ROM_SIZE0x10000
#define PATCH_ROM_SUCCESS1
#define PATCH_ROM_SUCCESS_HAS_LVDS2
#define PATCH_ROM_FAILED0
#define MAX_NUM_DCB_ENTRIES16
#define TYPE_GROUPED0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type", "display" };
const char *nvidia_device_type_1[]={ "@1,device_type", "display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name", "Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
// 0040 - 004F
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0043, "GeForce 6800 XE" },
{ 0x10DE0044, "GeForce 6800 XT" },
{ 0x10DE0045, "GeForce 6800 GT" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004D, "Quadro FX 3400" },
{ 0x10DE004E, "Quadro FX 4000" },
// 0050 - 005F
// 0060 - 006F
// 0070 - 007F
// 0080 - 008F
// 0090 - 009F
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0093, "GeForce 7800 GS" },
{ 0x10DE0095, "GeForce 7800 SLI" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
// 00A0 - 00AF
// 00B0 - 00BF
// 00C0 - 00CF
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00C3, "GeForce 6800 XT" },
{ 0x10DE00C8, "GeForce Go 6800" },
{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
// 00D0 - 00DF
// 00E0 - 00EF
// 00F0 - 00FF
{ 0x10DE00F1, "GeForce 6600 GT" },
{ 0x10DE00F2, "GeForce 6600" },
{ 0x10DE00F3, "GeForce 6200" },
{ 0x10DE00F4, "GeForce 6600 LE" },
{ 0x10DE00F5, "GeForce 7800 GS" },
{ 0x10DE00F6, "GeForce 6800 GS/XT" },
{ 0x10DE00F8, "Quadro FX 3400/4400" },
{ 0x10DE00F9, "GeForce 6800 Series GPU" },
// 0100 - 010F
// 0110 - 011F
// 0120 - 012F
// 0130 - 013F
// 0140 - 014F
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0143, "GeForce 6600 VE" },
{ 0x10DE0144, "GeForce Go 6600" },
{ 0x10DE0145, "GeForce 6610 XL" },
{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014A, "Quadro NVS 440" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
// 0150 - 015F
// 0160 - 016F
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0163, "GeForce 6200 LE" },
{ 0x10DE0164, "GeForce Go 6200" },
{ 0x10DE0165, "Quadro NVS 285" },
{ 0x10DE0166, "GeForce Go 6400" },
{ 0x10DE0167, "GeForce Go 6200" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
// 0170 - 017F
// 0180 - 018F
// 0190 - 019F
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE0197, "Tesla C870" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
// 01A0 - 01AF
// 01B0 - 01BF
// 01C0 - 01CF
// 01D0 - 01DF
{ 0x10DE01D0, "GeForce 7350 LE" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D2, "GeForce 7550 LE" },
{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01D9, "GeForce Go 7400 GS" },
{ 0x10DE01DA, "Quadro NVS 110M" },
{ 0x10DE01DB, "Quadro NVS 120M" },
{ 0x10DE01DC, "Quadro FX 350M" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
// 01E0 - 01EF
// 01F0 - 01FF
// 0200 - 020F
// 0210 - 021F
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
// 0220 - 022F
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
// 0230 - 023F
// 0240 - 024F
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },
{ 0x10DE0247, "GeForce Go 6100" },
// 0250 - 025F
// 0260 - 026F
// 0270 - 027F
// 0280 - 028F
// 0290 - 029F
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT/GTO" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0293, "GeForce 7950 GX2" },
{ 0x10DE0294, "GeForce 7950 GX2" },
{ 0x10DE0295, "GeForce 7950 GT" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029B, "Quadro FX 1500M" },
{ 0x10DE029C, "Quadro FX 5500" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
// 02A0 - 02AF
// 02B0 - 02BF
// 02C0 - 02CF
// 02D0 - 02DF
// 02E0 - 02EF
{ 0x10DE02E0, "GeForce 7600 GT" },
{ 0x10DE02E1, "GeForce 7600 GS" },
{ 0x10DE02E2, "GeForce 7300 GT" },
{ 0x10DE02E3, "GeForce 7900 GS" },
{ 0x10DE02E4, "GeForce 7950 GT" },
// 02F0 - 02FF
// 0300 - 030F
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
// 0310 - 031F
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
// 0320 - 032F
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
// 0330 - 033F
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0333, "GeForce FX 5950 Ultra" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
// 0340 - 034F
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0344, "GeForce FX 5700VE" },
{ 0x10DE0347, "GeForce FX Go5700" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
// 0350 - 035F
// 0360 - 036F
// 0370 - 037F
// 0380 - 038F
{ 0x10DE038B, "GeForce 7650 GS" },
// 0390 - 039F
{ 0x10DE0390, "GeForce 7650 GS" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE0394, "GeForce 7600 LE" },
{ 0x10DE0395, "GeForce 7300 GT" },
{ 0x10DE0397, "GeForce Go 7700" },
{ 0x10DE0398, "GeForce Go 7600" },
{ 0x10DE0399, "GeForce Go 7600 GT"},
{ 0x10DE039A, "Quadro NVS 300M" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
// 03A0 - 03AF
// 03B0 - 03BF
// 03C0 - 03CF
// 03D0 - 03DF
{ 0x10DE03D0, "GeForce 6150SE nForce 430" },
{ 0x10DE03D1, "GeForce 6100 nForce 405" },
{ 0x10DE03D2, "GeForce 6100 nForce 400" },
{ 0x10DE03D5, "GeForce 6100 nForce 420" },
{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },
// 03E0 - 03EF
// 03F0 - 03FF
// 0400 - 040F
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0406, "GeForce 8300 GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" },
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
// 0410 - 041F
{ 0x10DE0410, "GeForce GT 330" },
// 0420 - 042F
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE0423, "GeForce 8300 GS" },
{ 0x10DE0424, "GeForce 8400 GS" },
{ 0x10DE0425, "GeForce 8600M GS" },
{ 0x10DE0426, "GeForce 8400M GT" },
{ 0x10DE0427, "GeForce 8400M GS" },
{ 0x10DE0428, "GeForce 8400M G" },
{ 0x10DE0429, "Quadro NVS 140M" },
{ 0x10DE042A, "Quadro NVS 130M" },
{ 0x10DE042B, "Quadro NVS 135M" },
{ 0x10DE042C, "GeForce 9400 GT" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
// 0430 - 043F
// 0440 - 044F
// 0450 - 045F
// 0460 - 046F
// 0470 - 047F
// 0480 - 048F
// 0490 - 049F
// 04A0 - 04AF
// 04B0 - 04BF
// 04C0 - 04CF
// 04D0 - 04DF
// 04E0 - 04EF
// 04F0 - 04FF
// 0500 - 050F
// 0510 - 051F
// 0520 - 052F
// 0530 - 053F
{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053E, "GeForce 7025 / nForce 630a" },
// 0540 - 054F
// 0550 - 055F
// 0560 - 056F
// 0570 - 057F
// 0580 - 058F
// 0590 - 059F
// 05A0 - 05AF
// 05B0 - 05BF
// 05C0 - 05CF
// 05D0 - 05DF
// 05E0 - 05EF
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E3, "GeForce GTX 285" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05ED, "Quadroplex 2200 D2" },
// 05F0 - 05FF
{ 0x10DE05F8, "Quadroplex 2200 S4" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE05FF, "Quadro FX 3800" },
// 0600 - 060F
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0601, "GeForce 9800 GT" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0603, "GeForce GT 230" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE0607, "GeForce GTS 240" },
{ 0x10DE0608, "GeForce 9800M GTX" },
{ 0x10DE0609, "GeForce 8800M GTS" },
{ 0x10DE060A, "GeForce GTX 280M" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE060F, "GeForce GTX 285M" },
// 0610 - 061F
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0613, "GeForce 9800 GTX+" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE0619, "Quadro FX 4700 X2" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061B, "Quadro VX 200" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
// 0620 - 062F
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0626, "GeForce GT 130" },
{ 0x10DE0627, "GeForce GT 140" },
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE062D, "GeForce 9600 GT" },
{ 0x10DE062E, "GeForce 9600 GT" },
// 0630 - 063F
{ 0x10DE0631, "GeForce GTS 160M" },
{ 0x10DE0632, "GeForce GTS 150M" },
{ 0x10DE0635, "GeForce 9600 GSO" },
{ 0x10DE0637, "GeForce 9600 GT" },
{ 0x10DE0638, "Quadro FX 1800" },
{ 0x10DE063A, "Quadro FX 2700M" },
// 0640 - 064F
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE0643, "GeForce 9500 GT" },
{ 0x10DE0644, "GeForce 9500 GS" },
{ 0x10DE0645, "GeForce 9500 GS" },
{ 0x10DE0646, "GeForce GT 120" },
{ 0x10DE0647, "GeForce 9600M GT" },
{ 0x10DE0648, "GeForce 9600M GS" },
{ 0x10DE0649, "GeForce 9600M GT" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
// 0650 - 065F
{ 0x10DE0651, "GeForce G 110M" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0653, "GeForce GT 120M" },
{ 0x10DE0654, "GeForce GT 220M" },
{ 0x10DE0656, "GeForce 9650 S" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE065F, "GeForce G210" },
// 0660 - 066F
// 0670 - 067F
// 0680 - 068F
// 0690 - 069F
// 06A0 - 06AF
// 06B0 - 06BF
// 06C0 - 06CF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
// 06D0 - 06DF
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DD, "Quadro 4000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
// 06E0 - 06EF
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E2, "GeForce 8400" },
{ 0x10DE06E3, "GeForce 8400 SE" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E6, "GeForce G100" },
{ 0x10DE06E7, "GeForce 9300 SE" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
// 06F0 - 06FF
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FB, "Quadro FX 370M" },
{ 0x10DE06FD, "Quadro NVS 295" },
// 0700 - 070F
// 0710 - 071F
// 0720 - 072F
// 0730 - 073F
// 0740 - 074F
// 0750 - 075F
// 0760 - 076F
// 0770 - 077F
// 0780 - 078F
// 0790 - 079F
// 07A0 - 07AF
// 07B0 - 07BF
// 07C0 - 07CF
// 07D0 - 07DF
// 07E0 - 07EF
{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },
{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },
{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },
{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },
{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },
// 07F0 - 07FF
// 0800 - 080F
// 0810 - 081F
// 0820 - 082F
// 0830 - 083F
// 0840 - 084F
{ 0x10DE0844, "GeForce 9100M G" },
{ 0x10DE0845, "GeForce 8200M G" },
{ 0x10DE0846, "GeForce 9200" },
{ 0x10DE0847, "GeForce 9100" },
{ 0x10DE0848, "GeForce 8300" },
{ 0x10DE0849, "GeForce 8200" },
{ 0x10DE084A, "nForce 730a" },
{ 0x10DE084B, "GeForce 9200" },
{ 0x10DE084C, "nForce 980a/780a SLI" },
{ 0x10DE084D, "nForce 750a SLI" },
{ 0x10DE084F, "GeForce 8100 / nForce 720a" },
// 0850 - 085F
// 0860 - 086F
{ 0x10DE0860, "GeForce 9400" },
{ 0x10DE0861, "GeForce 9400" },
{ 0x10DE0862, "GeForce 9400M G" },
{ 0x10DE0863, "GeForce 9400M" },
{ 0x10DE0864, "GeForce 9300" },
{ 0x10DE0865, "ION" },
{ 0x10DE0866, "GeForce 9400M G" },
{ 0x10DE0867, "GeForce 9400" },
{ 0x10DE0868, "nForce 760i SLI" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE086C, "GeForce 9300 / nForce 730i" },
{ 0x10DE086D, "GeForce 9200" },
{ 0x10DE086E, "GeForce 9100M G" },
{ 0x10DE086F, "GeForce 8200M G" },
// 0870 - 087F
{ 0x10DE0870, "GeForce 9400M" },
{ 0x10DE0871, "GeForce 9200" },
{ 0x10DE0872, "GeForce G102M" },
{ 0x10DE0873, "GeForce G102M" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE0876, "ION" },
{ 0x10DE087A, "GeForce 9400" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE087F, "ION LE" },
// 0880 - 088F
// 0890 - 089F
// 08A0 - 08AF
// 08B0 - 08BF
// 08C0 - 08CF
// 08D0 - 08DF
// 08E0 - 08EF
// 08F0 - 08FF
// 0900 - 090F
// 0910 - 091F
// 0920 - 092F
// 0930 - 093F
// 0940 - 094F
// 0950 - 095F
// 0960 - 096F
// 0970 - 097F
// 0980 - 098F
// 0990 - 099F
// 09A0 - 09AF
// 09B0 - 09BF
// 09C0 - 09CF
// 09D0 - 09DF
// 09E0 - 09EF
// 09F0 - 09FF
// 0A00 - 0A0F
// 0A10 - 0A1F
// 0A20 - 0A2F
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A22, "GeForce 315" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A2B, "GeForce GT 330M" },
{ 0x10DE0A2C, "NVS 5100M" },
{ 0x10DE0A2D, "GeForce GT 320M" },
// 0A30 - 0A3F
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A35, "GeForce GT 325M" },
{ 0x10DE0A3C, "Quadro FX 880M" },
// 0A40 - 0A4F
// 0A50 - 0A5F
// 0A60 - 0A6F
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A64, "ION" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A67, "GeForce 315" },
{ 0x10DE0A68, "GeForce G105M" },
{ 0x10DE0A69, "GeForce G105M" },
{ 0x10DE0A6A, "NVS 2100M" },
{ 0x10DE0A6C, "NVS 3100M" },
{ 0x10DE0A6E, "GeForce 305M" },
{ 0x10DE0A6F, "ION" },
// 0A70 - 0A7F
{ 0x10DE0A70, "GeForce 310M" },
{ 0x10DE0A71, "GeForce 305M" },
{ 0x10DE0A72, "GeForce 310M" },
{ 0x10DE0A73, "GeForce 305M" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0A7C, "Quadro FX 380M" },
// 0A80 - 0A8F
// 0A90 - 0A9F
// 0AA0 - 0AAF
// 0AB0 - 0ABF
// 0AC0 - 0ACF
// 0AD0 - 0ADF
// 0AE0 - 0AEF
// 0AF0 - 0AFF
// 0B00 - 0B0F
// 0B10 - 0B1F
// 0B20 - 0B2F
// 0B30 - 0B3F
// 0B40 - 0B4F
// 0B50 - 0B5F
// 0B60 - 0B6F
// 0B70 - 0B7F
// 0B80 - 0B8F
// 0B90 - 0B9F
// 0BA0 - 0BAF
// 0BB0 - 0BBF
// 0BC0 - 0BCF
// 0BD0 - 0BDF
// 0BE0 - 0BEF
// 0BF0 - 0BFF
// 0C00 - 0C0F
// 0C10 - 0C1F
// 0C20 - 0C2F
// 0C30 - 0C3F
// 0C40 - 0C4F
// 0C50 - 0C5F
// 0C60 - 0C6F
// 0C70 - 0C7F
// 0C80 - 0C8F
// 0C90 - 0C9F
// 0CA0 - 0CAF
{ 0x10DE0CA0, "GeForce GT 330 " },
{ 0x10DE0CA2, "GeForce GT 320" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA4, "GeForce GT 340" },
{ 0x10DE0CA7, "GeForce GT 330" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CAC, "GeForce 315" },
{ 0x10DE0CAF, "GeForce GT 335M" },
// 0CB0 - 0CBF
{ 0x10DE0CB0, "GeForce GTS 350M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CBC, "Quadro FX 1800M" },
// 0CC0 - 0CCF
// 0CD0 - 0CDF
// 0CE0 - 0CEF
// 0CF0 - 0CFF
// 0D00 - 0D0F
// 0D10 - 0D1F
// 0D20 - 0D2F
// 0D30 - 0D3F
// 0D40 - 0D4F
// 0D50 - 0D5F
// 0D60 - 0D6F
// 0D70 - 0D7F
// 0D80 - 0D8F
// 0D90 - 0D9F
// 0DA0 - 0DAF
// 0DB0 - 0DBF
// 0DC0 - 0DCF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC4, "GeForce GTS 450" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
// 0DD0 - 0DDF
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
// 0DE0 - 0DEF
{ 0x10DE0DE0, "GeForce GT 440" },
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DE5, "GeForce GT 530" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
// 0DF0 - 0DFF
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF3, "GeForce GT 420M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E00 - 0E0F
// 0E10 - 0E1F
// 0E20 - 0E2F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
// 0E30 - 0E3F
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0E40 - 0E4F
// 0E50 - 0E5F
// 0E60 - 0E6F
// 0E70 - 0E7F
// 0E80 - 0E8F
// 0E90 - 0E9F
// 0EA0 - 0EAF
// 0EB0 - 0EBF
// 0EC0 - 0ECF
// 0ED0 - 0EDF
// 0EE0 - 0EEF
// 0EF0 - 0EFF
// 0F00 - 0F0F
// 0F10 - 0F1F
// 0F20 - 0F2F
// 0F30 - 0F3F
// 0F40 - 0F4F
// 0F50 - 0F5F
// 0F60 - 0F6F
// 0F70 - 0F7F
// 0F80 - 0F8F
// 0F90 - 0F9F
// 0FA0 - 0FAF
// 0FB0 - 0FBF
// 0FC0 - 0FCF
// 0FD0 - 0FDF
// 0FE0 - 0FEF
// 0FF0 - 0FFF
// 1000 - 100F
// 1010 - 101F
// 1020 - 102F
// 1030 - 103F
// 1040 - 104F
{ 0x10DE1040, "GeForce GT 520" },
// 1050 - 105F
{ 0x10DE1050, "GeForce GT 520M" },
// 1060 - 106F
// 1070 - 107F
// 1080 - 108F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "GeForce GTX 570" },
{ 0x10DE1082, "GeForce GTX 560 Ti" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1088, "GeForce GTX 590" },
// 1090 - 109F
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
// 10A0 - 10AF
// 10B0 - 10BF
// 10C0 - 10CF
{ 0x10DE10C3, "GeForce 8400 GS" },
// 1200 -
{ 0x10DE1200, "GeForce GTX 560 Ti" },
{ 0x10DE1244, "GeForce GTX 550 Ti" },
{ 0x10DE1245, "GeForce GTS 450" },
};
static uint16_t swap16(uint16_t x)
{
return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
}
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
#if 0
static uint32_t swap32(uint32_t x)
{
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_tread8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
static int patch_nvidia_rom(uint8_t *rom)
{
if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
return PATCH_ROM_FAILED;
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if (!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}
//else
//printf("dcb table at offset 0x%04x\n", dcbptr);
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if (dcbtable_version >= 0x20)
{
uint32_t sig;
if (dcbtable_version >= 0x30)
{
headerlength = dcbtable[1];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
}
else
{
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb)
{
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
}
else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */
{
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC"))
{
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
}
else
{
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if (numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i = 0;
struct dcbentry
{
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++)
{
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
continue;
if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == 3)
{
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if (has_lvds)
{
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
else
{
int x;
// we loop twice as we need to generate two channels
for (x = 0; x <= 1; x++)
{
for (i=0; i<num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if (i && entries[i].type == 0x2)
{
switch (x)
{
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if ((entries[i-1].type == 0x0))
{
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if ((entries[i - 1].type == 0x0))
{
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
}
}
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type != TYPE_GROUPED)
{
//printf("%d not grouped\n", i);
if (togroup)
{
*togroup |= ( 0x1 << entries[i].index);
}
entries[i].type = TYPE_GROUPED;
}
}
if (channel1 > channel2)
{
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
}
default_NVCAP[6] = channel1;
default_NVCAP[8] = channel2;
// patching HEADS
for (i = 0; i < num_outputs; i++)
{
if (channel1 & (1 << i))
{
*entries[i].heads = 1;
}
else if(channel2 & (1 << i))
{
*entries[i].heads = 2;
}
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id)
{
int i;
for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id)
{
return NVKnownChipsets[i].name;
}
}
return NVKnownChipsets[0].name;
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
int fd;
int size;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)
{
return 0;
}
size = file_size(fd);
if (size > bufsize)
{
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",
filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
char tmp[16];
if (!device)
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i = 0; i < len; i++)
{
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
}
buf[0] = *p++;
buf[1] = *p++;
bin[i] = (unsigned char) strtoul(buf, NULL, 16);
}
return 0;
}
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50)
{
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0)
{
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else // >= NV_ARCH_C0
{
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
// Workaround for GT 420/430 & 9600M GT
switch (nvda_dev->device_id)
{
case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430
case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420
case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT
default: break;
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t *rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,
(uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit)
{
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0)
{
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
}
else
{
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
}
else
{
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
}
else
{
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
else
{
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
else
{
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
//return false;
}
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952)
{
if (rom_pci_header->device_id != nvda_dev->device_id)
{
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
}
else
{
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for (i = 0; i < 0x180; i++)
{
if (rom[i] == 0x0D && rom[i+1] == 0x0A)
{
crlf_count++;
// second 0x0D0A was found, extract bios version
if (crlf_count == 2)
{
if (rom[i-1] == 0x20) i--; // strip last " "
{
for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)
{
// find start
if (rom[version_start] == 0x00)
{
version_start++;
// strip "Version "
if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)
{
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
}
break; //Azi: reminder
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2)
{
uint8_t new_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)
{
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit)
{
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/Makefile
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MODULE_NAME = NVIDIAGraphicsEnabler
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = to be added...
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = NVIDIAGraphicsEnabler
MODULE_OBJS = nvidia.o NVIDIAGraphicsEnabler.o
include ../../MakeInc.dir
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/gma.c
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/*
Original patch by Nawcom
http://forum.voodooprojects.org/index.php/topic,1029.msg4427.html#msg4427
*/
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "gma.h"
#ifndef DEBUG_GMA
#define DEBUG_GMA 0
#endif
#if DEBUG_GMA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
uint8_t GMAX3100_vals[22][4] = {
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x64,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x03,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x08,0x52,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x3B,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 }
};
uint8_t reg_TRUE[]= { 0x01 ,0x00 ,0x00 ,0x00 };
uint8_t reg_FALSE[] = { 0x00,0x00,0x00,0x00 };
static struct gma_gpu_t KnownGPUS[] = {
{ 0x00000000, "Unknown"},
{ 0x808627A2, "Mobile GMA950"},
{ 0x808627AE, "Mobile GMA950"},
{ 0x808627A6, "Mobile GMA950"},
{ 0x8086A011, "Mobile GMA3150"},
{ 0x8086A012, "Mobile GMA3150"},
//Azi: i can get QE/CI but no framebuffer... more testing needed.
{ 0x80862772, "Desktop GMA950"},
{ 0x80862776, "Desktop GMA950"},
{ 0x8086A001, "Mobile GMA3150"},
{ 0x8086A002, "Desktop GMA3150" },
{ 0x80862A02, "GMAX3100"},
{ 0x80862A03, "GMAX3100"},
{ 0x80862A12, "GMAX3100"},
{ 0x80862A13, "GMAX3100"},
{ 0x80862A42, "GMAX3100"},
{ 0x80862A43, "GMAX3100"},
};
char *get_gma_model(uint32_t id) {
int i = 0;
for (i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++)
{
if (KnownGPUS[i].device == id)
return KnownGPUS[i].name;
}
return KnownGPUS[0].name;
}
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
char*devicepath;
volatile uint8_t*regs;
uint32_tbar[7];
char*model;
uint8_t BuiltIn =0x00;
uint8_t ClassFix[4] ={ 0x00, 0x00, 0x03, 0x00 };
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id);
verbose("Intel %s [%04x:%04x] :: %s\n",
model, gma_dev->vendor_id, gma_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));
device = devprop_add_device(string, devicepath);
if (!device)
{
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getchar();
return false;
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
if ((model == (char *)"Mobile GMA950")
|| (model == (char *)"Mobile GMA3150"))
{
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if ((model == (char *)"Desktop GMA950")
|| (model == (char *)"Desktop GMA3150"))
{
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if (model == (char *)"GMAX3100")
{
devprop_add_value(device, "AAPL,HasPanel",GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported",GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected",GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control",GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences", GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity",GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences", GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify",GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth",GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither",GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink",GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height",GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace",GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter",GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent",GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency",GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat",GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType",GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe",GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat",GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh",GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch",GMAX3100_vals[21], 4);
devprop_add_value(device, "class-code",ClassFix, 4);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if (!stringdata)
{
printf("no stringdata press a key...\n");
getchar();
return false;
}
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/IntelGraphicsEnabler.c
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/*
*IntelGraphicsEnabler Module
*Enables a few Intel cards to be used out of the box in OS X.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "gma.h"
#include "modules.h"
#define kGraphicsEnablerKey "GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void IntelGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_INTEL))
{
verbose("Intel VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_gma_devprop(current);
}
else
verbose("[%04x:%04x] :: %s, is not a Intel VGA Controller.\n",
current->vendor_id, current->device_id, devicepath);
}
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Cconfig
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#
# Chameleon Modules
#
config INTELGRAPHICSENABLER_MODULE
tristate "IntelGraphicsEnabler Module"
default m
---help---
Say Y here if you want to enable the use of this module.
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/gma.h
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#ifndef __LIBSAIO_GMA_H
#define __LIBSAIO_GMA_H
bool setup_gma_devprop(pci_dt_t *gma_dev);
struct gma_gpu_t {
unsigned device;
char *name;
};
#define REG8(reg)((volatile uint8_t *)regs)[(reg)]
#define REG16(reg)((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg)((volatile uint32_t *)regs)[(reg) >> 2]
#endif /* !__LIBSAIO_GMA_H */
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Readme.txt
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Module:IntelGraphicsEnabler
Description: Enables a few Intel cards to be used out of the box,
mostly mobile ones.
Dependencies: none
Keys: GraphicsEnablerYes/No (enabled by default)
Disable GraphicsEnabler patch.
Adaptation of Meklort's work.
Original patch by Nawcom:
http://forum.voodooprojects.org/index.php/topic,1029.0.html
TODO: test my GMA desktop again (Azi)
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/IntelGraphicsEnabler/Makefile
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MODULE_NAME = IntelGraphicsEnabler
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = to be added...
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = IntelGraphicsEnabler
MODULE_OBJS = gma.o IntelGraphicsEnabler.o
include ../../MakeInc.dir
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.h
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#ifndef __LIBSAIO_ATI_H
#define __LIBSAIO_ATI_H
bool setup_ati_devprop(pci_dt_t *ati_dev);
struct ati_chipsets_t {
unsigned device;
char *name;
};
struct ati_data_key {
uint32_t size;
char *name;
uint8_t data[];
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val)
#endif /* !__LIBSAIO_ATI_H */
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ATiGraphicsEnabler.c
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/*
* ATIGraphicsEnabler Module ---
* Enables many ati "legacy ??" cards to be used out of the box in OS X.
* This was converted from ( < r784) boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "ati.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler" // change?
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void ATiGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
// AMD ?? i don't find any vga 1022 vendor!.. thou ATI isn't used anymore!
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI))
{
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
}
else
verbose("[%04x:%04x] :: %s, is not a AMD/ATI VGA Controller.\n",// amd ??
current->vendor_id, current->device_id, devicepath);
}
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Cconfig
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#
# Chameleon Modules
#
config ATIGRAPHICSENABLER_MODULE
tristate "ATiGraphicsEnabler Module"
default m
---help---
Say Y here if you want to enable the use of this module.
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Readme.txt
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Module:ATiGraphicsEnabler
Description: the GraphicsEnabler ATI code ( < r784) ported to a module.
Support for "legacy" cards...
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseAtiROM(disabled by default)
TODO:
- naming: ATi or AMD ??
- merge with AMDGraphicsEnabler ??
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/Makefile
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MODULE_NAME = ATiGraphicsEnabler
MODULE_AUTHOR = Chameleon
MODULE_DESCRIPTION = to be added...
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = $(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = ATiGraphicsEnabler
MODULE_OBJS = ati.o ATiGraphicsEnabler.o
include ../../MakeInc.dir
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/ATiGraphicsEnabler/ati.c
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#include "libsa.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "ati.h"
#ifndef DEBUG_ATI
#define DEBUG_ATI 0
#endif
#if DEBUG_ATI
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseAtiROMKey"UseAtiROM"
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *ati_compatible_0[]= { "@0,compatible", "ATY,%s" };
const char *ati_compatible_1[]= { "@1,compatible", "ATY,%s" };
const char *ati_device_type_0[]= { "@0,device_type", "display" };
const char *ati_device_type_1[]= { "@1,device_type", "display" };
const char *ati_device_type[]= { "device_type", "ATY,%sParent" };
const char *ati_name_0[]= { "@0,name", "ATY,%s" };
const char *ati_name_1[]= { "@1,name", "ATY,%s" };
const char *ati_name[]= { "name", "ATY,%sParent" };
const char *ati_efidisplay_0[]= { "@0,ATY,EFIDisplay", "TMDSB" };
struct ati_data_key ati_connector_type_0= { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1= { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_display_con_fl_type_0= { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };
const char *ati_display_type_0[]= { "@0,display-type", "LCD" };
const char *ati_display_type_1[]= { "@1,display-type", "NONE" };
struct ati_data_key ati_aux_power_conn= { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };
struct ati_data_key ati_backlight_ctrl= { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl01_coher= { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };
const char *ati_card_no[]= { "ATY,Card#", "109-B77101-00" };
const char *ati_copyright[]= { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };
const char *ati_efi_compile_d[]= { "ATY,EFICompileDate", "Jan 26 2009" };
struct ati_data_key ati_efi_disp_conf= { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };
struct ati_data_key ati_efi_drv_type= { 0x01, "ATY,EFIDriverType", {0x02} };
struct ati_data_key ati_efi_enbl_mode= { 0x01, "ATY,EFIEnabledMode", {0x01} };
struct ati_data_key ati_efi_init_stat= { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_efi_orientation= { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };
const char *ati_efi_version[]= { "ATY,EFIVersion", "01.00.318" };
const char *ati_efi_versionB[]= { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };
const char *ati_efi_versionE[]= { "ATY,EFIVersionE", "113-B7710A-318" };
struct ati_data_key ati_mclk= { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };
struct ati_data_key ati_mem_rev_id= { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };
struct ati_data_key ati_mem_vend_id= { 0x02, "ATY,MemVendorID", {0x02, 0x00} };
const char *ati_mrt[]= { "ATY,MRT", " " };
const char *ati_romno[]= { "ATY,Rom#", "113-B7710C-176" };
struct ati_data_key ati_sclk= { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };
struct ati_data_key ati_vendor_id= { 0x02, "ATY,VendorID", {0x02, 0x10} };
struct ati_data_key ati_platform_info= { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_mvad= { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };
struct ati_data_key ati_saved_config= { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
///non 48xx keys
const char *ati_efidisplay_0_n4[]= { "@0,ATY,EFIDisplay", "TMDSA" };
struct ati_data_key ati_connector_type_0_n4= { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1_n4= { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };
struct ati_data_key ati_aapl_emc_disp_list_n4= { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_fb_offset_n4= { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };
struct ati_data_key ati_hwgpio_n4= { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };
struct ati_data_key ati_iospace_offset_n4= { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };
struct ati_data_key ati_mclk_n4= { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };
struct ati_data_key ati_sclk_n4= { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };
struct ati_data_key ati_refclk_n4= { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };
struct ati_data_key ati_regspace_offset_n4= { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_0= { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_1= { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_swgpio_info_n4= { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };
struct ati_data_key ati_efi_orientation_n4= { 0x01, "ATY,EFIOrientation", {0x08} };
struct ati_data_key ati_mvad_n4= { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_saved_config_n4= { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct pcir_s {
uint32_t signature;
uint16_t vid;
uint16_t devid;
};
// Known cards as of 2008/08/26
static struct ati_chipsets_t ATIKnownChipsets[] = {
{ 0x00000000, "Unknown" } ,
//{ 0x10027181, "ATI Radeon 1300 Series"} ,
{ 0x10029589, "ATI Radeon 2600 Series"} ,
{ 0x10029588, "ATI Radeon 2600 Series"} ,
{ 0x100294C3, "ATI Radeon 2400 Series"} ,
{ 0x100294C4, "ATI Radeon 2400 Series"} ,
{ 0x100294C6, "ATI Radeon 2400 Series"} ,
{ 0x10029400, "ATI Radeon 2900 Series"} ,
{ 0x10029405, "ATI Radeon 2900GT Series"} ,
{ 0x10029581, "ATI Radeon 2600 Series"} ,
{ 0x10029583, "ATI Radeon 2600 Series"} ,
{ 0x10029586, "ATI Radeon 2600 Series"} ,
{ 0x10029587, "ATI Radeon 2600 Series"} ,
{ 0x100294C9, "ATI Radeon 2400 Series"} ,
{ 0x10029501, "ATI Radeon 3800 Series"} ,
{ 0x10029505, "ATI Radeon 3800 Series"} ,
{ 0x10029515, "ATI Radeon 3800 Series"} ,
{ 0x10029507, "ATI Radeon 3800 Series"} ,
{ 0x10029500, "ATI Radeon 3800 Series"} ,
{ 0x1002950F, "ATI Radeon 3800X2 Series"} ,
{ 0x100295C5, "ATI Radeon 3400 Series"} ,
{ 0x100295C7, "ATI Radeon 3400 Series"} ,
{ 0x100295C0, "ATI Radeon 3400 Series"} ,
{ 0x10029596, "ATI Radeon 3600 Series"} ,
{ 0x10029590, "ATI Radeon 3600 Series"} ,
{ 0x10029599, "ATI Radeon 3600 Series"} ,
{ 0x10029597, "ATI Radeon 3600 Series"} ,
{ 0x10029598, "ATI Radeon 3600 Series"} ,
{ 0x10029442, "ATI Radeon 4850 Series"} ,
{ 0x10029440, "ATI Radeon 4870 Series"} ,
{ 0x1002944C, "ATI Radeon 4830 Series"} ,
{ 0x10029460, "ATI Radeon 4890 Series"} ,
{ 0x10029462, "ATI Radeon 4890 Series"} ,
{ 0x10029441, "ATI Radeon 4870X2 Series"} ,
{ 0x10029443, "ATI Radeon 4850X2 Series"} ,
{ 0x10029444, "ATI Radeon 4800 Series"} ,
{ 0x10029446, "ATI Radeon 4800 Series"} ,
{ 0x1002944E, "ATI Radeon 4730 Series"} ,
{ 0x10029450, "ATI Radeon 4800 Series"} ,
{ 0x10029452, "ATI Radeon 4800 Series"} ,
{ 0x10029456, "ATI Radeon 4800 Series"} ,
{ 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x10029490, "ATI Radeon 4670 Series"} ,
{ 0x10029498, "ATI Radeon 4650 Series"} ,
{ 0x10029490, "ATI Radeon 4600 Series"} ,
{ 0x10029498, "ATI Radeon 4600 Series"} ,
{ 0x1002949E, "ATI Radeon 4600 Series"} ,
{ 0x10029480, "ATI Radeon 4600 Series"} ,
{ 0x10029488, "ATI Radeon 4600 Series"} ,
{ 0x10029540, "ATI Radeon 4500 Series"} ,
{ 0x10029541, "ATI Radeon 4500 Series"} ,
{ 0x1002954E, "ATI Radeon 4500 Series"} ,
{ 0x10029552, "ATI Radeon 4300 Mobility Series"} ,
{ 0x10029553, "ATI Radeon 4500 Mobility Series"} ,
{ 0x1002954F, "ATI Radeon 4300 Series"} ,
{ 0x100294B3, "ATI Radeon 4770 Series"} ,
{ 0x100294B5, "ATI Radeon 4770 Series"} ,
{ 0x100268B8, "ATI Radeon 5700 Series"} ,
{ 0x100268BE, "ATI Radeon 5700 Series"} ,
{ 0x10026898, "ATI Radeon 5800 Series"} ,
{ 0x10026899, "ATI Radeon 5800 Series"}
};
static struct ati_chipsets_t ATIKnownFramebuffers[] = {
{ 0x00000000, "Megalodon" },
//{ 0x10027181, "Caretta" },
{ 0x10029589, "Lamna"} ,
{ 0x10029588, "Lamna"} ,
{ 0x100294C3, "Iago"} ,
{ 0x100294C4, "Iago"} ,
{ 0x100294C6, "Iago"} ,
{ 0x10029400, "Franklin"} ,
{ 0x10029405, "Franklin"} ,
{ 0x10029581, "Hypoprion"} ,
{ 0x10029583, "Hypoprion"} ,
{ 0x10029586, "Hypoprion"} ,
{ 0x10029587, "Hypoprion"} ,
{ 0x100294C9, "Iago"} ,
{ 0x10029501, "Megalodon"} ,
{ 0x10029505, "Megalodon"} ,
{ 0x10029515, "Megalodon"} ,
{ 0x10029507, "Megalodon"} ,
{ 0x10029500, "Megalodon"} ,
{ 0x1002950F, "Triakis"} ,
{ 0x100295C5, "Iago"} ,
{ 0x100295C7, "Iago"} ,
{ 0x100295C0, "Iago"} ,
{ 0x10029596, "Megalodon"} ,
{ 0x10029590, "Megalodon"} ,
{ 0x10029599, "Megalodon"} ,
{ 0x10029597, "Megalodon"} ,
{ 0x10029598, "Megalodon"} ,
{ 0x10029442, "Motmot"} ,
{ 0x10029440, "Motmot"} ,
{ 0x1002944C, "Motmot"} ,
{ 0x10029460, "Motmot"} ,
{ 0x10029462, "Motmot"} ,
{ 0x10029441, "Motmot"} ,
{ 0x10029443, "Motmot"} ,
{ 0x10029444, "Motmot"} ,
{ 0x10029446, "Motmot"} ,
{ 0x1002944E, "Motmot"} ,
{ 0x10029450, "Motmot"} ,
{ 0x10029452, "Motmot"} ,
{ 0x10029456, "Motmot"} ,
{ 0x1002944A, "Motmot"} ,
{ 0x1002945A, "Motmot"} ,
{ 0x1002945B, "Motmot"} ,
{ 0x1002944B, "Motmot"} ,
{ 0x10029490, "Peregrine"} ,
{ 0x10029498, "Peregrine"} ,
{ 0x1002949E, "Peregrine"} ,
{ 0x10029480, "Peregrine"} ,
{ 0x10029488, "Peregrine"} ,
{ 0x10029540, "Peregrine"} ,
{ 0x10029541, "Peregrine"} ,
{ 0x1002954E, "Peregrine"} ,
{ 0x10029552, "Peregrine"} ,
{ 0x10029553, "Peregrine"} ,
{ 0x1002954F, "Peregrine"} ,
{ 0x100294B3, "Peregrine"},
{ 0x100294B5, "Peregrine"},
{ 0x100268B8, "Motmot"},
{ 0x100268BE, "Motmot"},
{ 0x10026898, "Motmot"},
{ 0x10026899, "Motmot"}
};
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
{
uint32_tbar[7];
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (mode) {
if (mode != 1) {
return 0xe00002c7;
}
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1600, 0x14030300);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x17a0, 0x21);
REG32W(0x1798, 0x21);
REG32W(0x1798, 0x21);
} else {
REG32W(0x1600, 0x14030302);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00080000);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x00080721);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x1604, 0x0400e9fc);
REG32W(0x161c, 0x00);
REG32W(0x1620, 0x9f);
REG32W(0x1618, 0x00040004);
REG32W(0x161c, 0x00);
REG32W(0x1604, 0xe9fc);
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
}
return 0;
}
static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_t*BIOSBase;
uint32_tcounter;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (volatile uint32_t *) (bar[2] & ~0x0f);
accessROM(ati_dev, 0);
REG32W(0xa8, 0);
REG32R(0xac);
REG32W(0xa8, 0);
REG32R(0xac);
BIOSBase = malloc(0x10000);
REG32W(0xa8, 0);
BIOSBase[0] = REG32R(0xac);
counter = 4;
do {
REG32W(0xa8, counter);
BIOSBase[counter/4] = REG32R(0xac);
counter +=4;
} while (counter != 0x10000);
accessROM((pci_dt_t *)regs, 1);
if (*(uint16_t *)BIOSBase != 0xAA55) {
printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
return 0;
}
return (uint8_t *)BIOSBase;
}
#define R5XX_CONFIG_MEMSIZE0x00F8 //Azi:---
#define R6XX_CONFIG_MEMSIZE0x5428
uint32_t getvramsizekb(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_tsize;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (ati_dev->device_id < 0x9400) {
size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
} else {
size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;
}
return size;
}
#define AVIVO_D1CRTC_CONTROL0x6080
#define AVIVO_CRTC_EN(1<<0)
#define AVIVO_D2CRTC_CONTROL0x6880
static bool radeon_card_posted(pci_dt_t *ati_dev)
{
// if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.
/*char *biosimage = 0xC0000;
if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)
{
option_rom_pci_header_t *rom_pci_header;
rom_pci_header = (option_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);
if (rom_pci_header->signature == 0x52494350)
{
if (rom_pci_header->device_id == ati_dev->device_id)
{
return true;
printf("Card was POSTed\n");
}
}
}
return false;
printf("Card was not POSTed\n");
*/
//fails yet
uint32_tbar[7];
uint32_tval;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);
regs = (uint32_t *) (bar[2] & ~0x0f);
val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);
if (val & AVIVO_CRTC_EN) {
return true;
} else {
return false;
}
}
static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static char *get_ati_model(uint32_t id)
{
int i;
for (i = 0; i < (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {
if (ATIKnownChipsets[i].device == id) {
return ATIKnownChipsets[i].name;
}
}
return ATIKnownChipsets[0].name;
}
static char *get_ati_fb(uint32_t id)
{
inti;
for (i = 0; i < (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {
if (ATIKnownFramebuffers[i].device == id) {
return ATIKnownFramebuffers[i].name;
}
}
return ATIKnownFramebuffers[0].name;
}
static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)
{
inti;
uint8_t*config_space;
if (!device || !ati_dev) {
return 0;
}
verbose("dumping pci config space, 256 bytes\n");
config_space = malloc(256);
for (i=0; i<=255; i++) {
config_space[i] = pci_config_read8( ati_dev->dev.addr, i);
}
devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);
free (config_space);
return 1;
}
static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)
{
if(!device)
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_device_type))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_1))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))
return 0;
return 1;
}
static int devprop_add_ati_template(struct DevPropDevice *device)
{
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))
return 0;
return 1;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
struct DevPropDevice*device;
char*devicepath;
char*model;
char*framebuffer;
char tmp[64];
uint8_t*rom = NULL;
uint32_t rom_size = 0;
option_rom_pci_header_t *rom_pci_header;
uint8_t*bios;
uint32_t bios_size;
uint32_t vram_size;
uint32_t boot_display;
uint8_t cmd;
bool doit;
bool toFree;
devicepath = get_pci_dev_path(ati_dev);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("old pci command - %x\n", cmd);
if (cmd == 0) {
pci_config_write8(ati_dev->dev.addr, 4, 6);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("new pci command - %x\n", cmd);
}
model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);
framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
if (!device) {
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getchar();
return false;
}
/* FIXME: for primary graphics card only */
if (radeon_card_posted(ati_dev)) {
boot_display = 1;
} else {
boot_display = 0;
}
verbose("boot display - %x\n", boot_display);
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if ((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') ||
(framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') ||
(framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)
devprop_add_ati_template_4xxx(device);
else {
devprop_add_ati_template(device);
vram_size = getvramsizekb(ati_dev) * 1024;
if ((vram_size > 0x80000000) || (vram_size == 0)) {
vram_size = 0x10000000;//vram reported wrong, defaulting to 256 mb
}
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);
ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;
ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF;
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0);
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);
devprop_add_iopciconfigspace(device, ati_dev);
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);
//fb setup
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);
devices_number++;
sprintf(tmp, ati_compatible_0[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_compatible_1[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_device_type[1], framebuffer);
devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name[1], framebuffer);
devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_0[1], framebuffer);
devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_1[1], framebuffer);
devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, "bt(0,0)/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);
if (getBoolForKey(kUseAtiROMKey, &doit, &bootInfo->bootConfig) && doit) {
verbose("looking for ati video bios file %s\n", tmp);
rom = malloc(0x20000);
rom_size = load_ati_bios_file(tmp, rom, 0x20000);
if (rom_size > 0) {
verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);
if (rom_size > 0x10000) {
rom_size = 0x10000; //we dont need rest anyway;
}
} else {
printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);
}
}
if (rom_size == 0) {
if (boot_display) {// no custom rom
bios = NULL;// try to dump from legacy space, otherwise can result in 100% fan speed
} else {
// readAtomBios result in bug on some cards (100% fan speed and black screen),
// not using it for posted card, reading from legacy space instead
bios = readAtomBIOS(ati_dev);
}
} else {
bios = rom;//going custom rom way
verbose("Using rom %s\n", tmp);
}
if (bios == NULL) {
bios = (uint8_t *)0x000C0000;
toFree = false;
verbose("Not going to use bios image file\n");
} else {
toFree = true;
}
if (bios[0] == 0x55 && bios[1] == 0xaa) {
verbose("Found bios image\n");
bios_size = bios[2] * 512;
rom_pci_header = (option_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);
if (rom_pci_header->signature == 0x52494350) {
if (rom_pci_header->device_id != ati_dev->device_id) {
verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device_id, ati_dev->device_id);
} else {
if (toFree)
{
verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);
} else {
verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);
}
devprop_add_value(device, "ATY,bin_image", bios, bios_size);
}
} else {
verbose("Wrong pci header signature %x\n", rom_pci_header->signature);
}
} else {
verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
}
if (toFree) {
free(bios);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/GraphicsEnabler.txt
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This is a port of the graphics enabler code into modules,
based on Meklort's previous port; for all purposes, this is
his work; i'm just trying to help ease the work load and
learn something while doing it.
Though the modules are in a working state and considered by me
as fit for testing (and use), this is still work in progress.
Please feedback directly to me by pm at:
http://forum.voodooprojects.org/
NOTICE: as of now, i'm considering this work as "LOW PRIORITY".
The folder will be kept synced with the trunk.
Work on the code will be done on a "free time" basis.
Any dev that wants to work directly on the folder is welcome;
i will take care of the "syncing with trunk" part.
The main reason for this is:
there are more important things to fix on the booter.
Azi
branches/azimutz/Chazi/i386/modules/GraphicsEnabler/AMDGraphicsEnabler/ati_reg.h
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