Chameleon

Chameleon Commit Details

Date:2011-06-08 20:11:48 (8 years 5 months ago)
Author:Azimutz
Commit:996
Parents: 995
Message:What a mess... synced with trunk (r994). Left some comment clean up for later.. need a beer.. or five!?
Changes:
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/bootstruct.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/dram_controllers.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/boot2/boot.h
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/bootstruct.h
M/branches/azimutz/trunkGraphicsEnablerModules/i386/modules/GraphicsEnabler/NVIDIAGraphicsEnabler/nvidia.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/load.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/biosfn.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/boot2/modules.h
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/acpi_patcher.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/memvendors.h
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsa/memory.h
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/spd.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/cpu.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/usb.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/smbios_getters.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/platform.h
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/disk.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/modules/Resolution/915resolution.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/pci_setup.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/smbios.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/cpu.h
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/hpet.c
M/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/console.c
M/branches/azimutz/trunkGraphicsEnablerModules/doc/BootHelp.txt

File differences

branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/console.c
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bool gVerboseMode;
bool gErrors;
/** Kabyl: BooterLog
Azi: Doubled available log size; this seems to fix some hangs and instant reboots caused by
booting with -f (ignore caches). 96kb are enough to hold full log, booting with -f; even so,
this depends on how much we "play" at the boot prompt and with what patches we're playing,
depending on how much they print to the log.
**/ //Azi: closing **/ alows colapse/expand... is this desirable?? colapsing an entire page
// will also colapse comments....
/*
* Azi: Doubled available log size; this seems to fix some hangs and instant reboots caused by
* booting with -f (ignore caches). 96kb are enough to hold full log, booting with -f; even so,
* this depends on how much we "play" at the boot prompt and with what patches we're playing,
* depending on how much they print to the log.
*
* Kabyl: BooterLog
*/
#define BOOTER_LOG_SIZE(128 * 1024)
#define SAFE_LOG_SIZE134
char *msgbuf = 0;
char *cursor = 0;
struct putc_info //Azi: same as below
struct putc_info
{
char * str;
char * last_str;
};
static int
sputc(int c, struct putc_info * pi) //Azi: exists on printf.c & gui.c
sputc(int c, struct putc_info * pi)
{
if (pi->last_str)
if (pi->str == pi->last_str)
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/bootstruct.c
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bootArgs = (boot_args *)AllocateKernelMemory(sizeof(boot_args));
bcopy(oldAddr, bootArgs, sizeof(boot_args));
}
else {
else
{
void *oldAddr = bootArgsPreLion;
bootArgsPreLion = (boot_args_pre_lion *)AllocateKernelMemory(sizeof(boot_args_pre_lion));
bcopy(oldAddr, bootArgsPreLion, sizeof(boot_args_pre_lion));
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/bootstruct.h
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/** <-- JavaDoc style (doxygen) //Azi
/*
* Copyright (c) 2002-2003 Apple Computer, Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
#include "bios.h"
#include "device_tree.h"
/*! <-- QT style (doxygen) //Azi
/*!
Kernel boot args global also used by booter for its own data.
*/
extern boot_args *bootArgs;
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/acpi_patcher.c
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#include "aml_generator.h"
#ifndef DEBUG_ACPI
#define DEBUG_ACPI 0
#define DEBUG_ACPI 1
#endif
#if DEBUG_ACPI==2
{
switch (Platform.CPU.Model)
{
case 0x0D: // ?
case CPU_MODEL_YONAH: // Yonah
case CPU_MODEL_MEROM: // Merom
case CPU_MODEL_PENRYN: // Penryn
case CPU_MODEL_ATOM: // Intel Atom (45nm)
case 0x0D:// ???
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
{
bool cpu_dynamic_fsb = false;
break;
}
case CPU_MODEL_FIELDS:
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:
case CPU_MODEL_NEHALEM:
case CPU_MODEL_NEHALEM_EX:
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
case CPU_MODEL_SANDY:
case CPU_MODEL_SANDY_XEON:
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_SANDY_XEON:// Intel Xeon E3
{
maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...
minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;
}
#if DEBUG_ACPI
printf("Press a key to continue... (DEBUG_ACPI)\n");
getc();
//getc();
getchar(); //getc(); Azi: getc stuff
#endif
return 1;
}
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/spd.c
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"DDR2 SDRAM", /* 08h SDRAM DDR 2 */
"",/* 09h Undefined */
"",/* 0Ah Undefined */
"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */
"DDR3 SDRAM"/* 0Bh SDRAM DDR 3 */
};
#define UNKNOWN_MEM_TYPE 2
static uint8_t spd_mem_to_smbios[] =
{
UNKNOWN_MEM_TYPE, /* 00h Undefined */
UNKNOWN_MEM_TYPE, /* 01h FPM */
UNKNOWN_MEM_TYPE, /* 02h EDO */
UNKNOWN_MEM_TYPE, /* 03h PIPELINE NIBBLE */
SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */
SMB_MEM_TYPE_ROM, /* 05h MULTIPLEXED ROM */
SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */
SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */
SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */
UNKNOWN_MEM_TYPE, /* 09h Undefined */
UNKNOWN_MEM_TYPE, /* 0Ah Undefined */
SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */
UNKNOWN_MEM_TYPE,/* 00h Undefined */
UNKNOWN_MEM_TYPE,/* 01h FPM */
UNKNOWN_MEM_TYPE,/* 02h EDO */
UNKNOWN_MEM_TYPE,/* 03h PIPELINE NIBBLE */
SMB_MEM_TYPE_SDRAM,/* 04h SDRAM */
SMB_MEM_TYPE_ROM,/* 05h MULTIPLEXED ROM */
SMB_MEM_TYPE_SGRAM,/* 06h SGRAM DDR */
SMB_MEM_TYPE_DDR,/* 07h SDRAM DDR */
SMB_MEM_TYPE_DDR2,/* 08h SDRAM DDR 2 */
UNKNOWN_MEM_TYPE,/* 09h Undefined */
UNKNOWN_MEM_TYPE,/* 0Ah Undefined */
SMB_MEM_TYPE_DDR3/* 0Bh SDRAM DDR 3 */
};
#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))
#if DEBUG_SPD
// prevously located on mem.c; temporarily on platform.c now
dumpPhysAddr("spd content: ", slot->spd, spd_size);
getchar();
dumpPhysAddr("spd content: ", slot->spd, spd_size); //Azi: reminder - can be removed/replaced??
getchar(); //getc(); Azi: getc stuff
#endif
}
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/memvendors.h
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} VenIdName;
VenIdName vendorMap[] = {
{ 0, 0x01, "AMD"},
{ 0, 0x01, "AMD"},
{ 0, 0x02, "AMI"},
{ 0, 0x83, "Fairchild"},
{ 0, 0x04, "Fujitsu"},
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{
// Set usb legacy off modification by Signal64
// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.
// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)
// NOTE2: This should be called after any getc()/getchar() call. (aka, after the Wait=y keyworkd is used)
// AKA: Make this run immediatly before the kernel is called
uint32_tcapaddr, opaddr;
uint8_teecp;
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/dram_controllers.c
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,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS
,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS
);
/* getc();
/* getc(); Azi: getc stuff
*/
}
}
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/load.c
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*
*/
//#define DEBUG 1
#include <mach-o/fat.h>
#include <mach-o/loader.h>
#include <mach/machine/thread_status.h>
printf("ncmds: %x\n", (unsigned)mH->ncmds);
printf("sizeofcmds: %x\n", (unsigned)mH->sizeofcmds);
printf("flags: %x\n", (unsigned)mH->flags);
getc();
getchar(); //getc(); Azi: getc stuff
#endif
ncmds = mH->ncmds;
fileaddr = (gBinaryAddress + segCmd->fileoff);
filesize = segCmd->filesize;
segname=segCmd->segname;
segname=segCmd->segname;
#ifdef DEBUG
printf("segname: %s, vmaddr: %x, vmsize: %x, fileoff: %x, filesize: %x, nsects: %d, flags: %x.\n",
segCmd->segname, (unsigned)vmaddr, (unsigned)vmsize, (unsigned)fileaddr, (unsigned)filesize,
(unsigned) segCmd->nsects, (unsigned)segCmd->flags);
getchar(); //getc(); Azi: getc stuff
#endif
}
else
{
fileaddr = (gBinaryAddress + segCmd->fileoff);
filesize = segCmd->filesize;
segname=segCmd->segname;
segname=segCmd->segname;
#ifdef DEBUG
printf("segname: %s, vmaddr: %x, vmsize: %x, fileoff: %x, filesize: %x, nsects: %d, flags: %x.\n",
segCmd->segname, (unsigned)vmaddr, (unsigned)vmsize, (unsigned)fileaddr, (unsigned)filesize,
(unsigned) segCmd->nsects, (unsigned)segCmd->flags);
getchar(); //getc(); Azi: getc stuff
#endif
}
if (vmsize == 0 || filesize == 0) {
return 0;
}
#if DEBUG
/*#if DEBUG
printf("segname: %s, vmaddr: %x, vmsize: %x, fileoff: %x, filesize: %x, nsects: %d, flags: %x.\n",
segCmd->segname, (unsigned)vmaddr, (unsigned)vmsize, (unsigned)fileaddr, (unsigned)filesize,
(unsigned) segCmd->nsects, (unsigned)segCmd->flags);
getc();
#endif
#endif*/
if (! ((vmaddr >= KERNEL_ADDR &&
(vmaddr + vmsize) <= (KERNEL_ADDR + KERNEL_LEN)) ||
#if DEBUG
printf("symoff: %x, nsyms: %x, stroff: %x, strsize: %x\n",
symTab->symoff, symTab->nsyms, symTab->stroff, symTab->strsize);
getc ();
getchar(); //getc(); Azi: getc stuff
#endif
symsSize = symTab->stroff - symTab->symoff;
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/cpu.c
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}
}
}
/* Mobile CPU ? */
if (rdmsr64(0x17) & (1<<28)) {
/* Mobile CPU */
if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {
p->CPU.Features |= CPU_FEATURE_MOBILE;
}
}
p->CPU.FSBFrequency = fsbFrequency;
p->CPU.CPUFrequency = cpuFrequency;
DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);
DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);
DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);
DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);
DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);
DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);
DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);
DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);
DBG("CPU: Features: 0x%08x\n", p->CPU.Features);
DBG("CPU: Brand String: %s\n",p->CPU.BrandString);
DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);
DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);
DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",p->CPU.MaxCoef, p->CPU.CurrCoef);
DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",p->CPU.MaxDiv, p->CPU.CurrDiv);
DBG("CPU: TSCFreq: %dMHz\n",p->CPU.TSCFrequency / 1000000);
DBG("CPU: FSBFreq: %dMHz\n",p->CPU.FSBFrequency / 1000000);
DBG("CPU: CPUFreq: %dMHz\n",p->CPU.CPUFrequency / 1000000);
DBG("CPU: NoCores/NoThreads: %d/%d\n",p->CPU.NoCores, p->CPU.NoThreads);
DBG("CPU: Features: 0x%08x\n",p->CPU.Features);
#if DEBUG_CPU
pause();
#endif
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/platform.h
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#define CPUID_816
#define CPUID_MAX7
#define CPU_MODEL_YONAH0x0E
#define CPU_MODEL_MEROM0x0F
#define CPU_MODEL_PENRYN0x17
#define CPU_MODEL_NEHALEM0x1A
#define CPU_MODEL_ATOM0x1C
#define CPU_MODEL_FIELDS0x1E/* Lynnfield, Clarksfield, Jasper */
#define CPU_MODEL_DALES0x1F/* Havendale, Auburndale */
#define CPU_MODEL_DALES_32NM0x25/* Clarkdale, Arrandale */
#define CPU_MODEL_SANDY0x2a/* Sandy bridge */
#define CPU_MODEL_WESTMERE0x2C/* Gulftown, Westmere-EP, Westmere-WS */
#define CPU_MODEL_SANDY_XEON0x2D
#define CPU_MODEL_NEHALEM_EX0x2E
#define CPU_MODEL_YONAH0x0E// Sossaman, Yonah
#define CPU_MODEL_MEROM0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
#define CPU_MODEL_PENRYN0x17// Wolfdale, Yorkfield, Harpertown, Penryn
#define CPU_MODEL_NEHALEM0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
#define CPU_MODEL_ATOM0x1C// Atom
#define CPU_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper Forest
#define CPU_MODEL_DALES0x1F// Havendale, Auburndale
#define CPU_MODEL_DALES_32NM0x25// Clarkdale, Arrandale
#define CPU_MODEL_SANDY0x2A// Sandy Bridge
#define CPU_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
#define CPU_MODEL_SANDY_XEON0x2D// Sandy Bridge Xeon
#define CPU_MODEL_NEHALEM_EX0x2E// Beckton
#define CPU_MODEL_WESTMERE_EX0x2F
/* CPU Features */
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/disk.c
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#define UFS_SUPPORT 0
#endif
//#define DEBUG 1
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
printf(" bvr: %d, dev: %d, part: %d, flags: %d, vis: %d\n", bvr, bvr->biosdev, bvr->part_no, bvr->flags, bvr->visible);
}
printf("count: %d\n", bvCount);
getc();
getchar(); //getc(); Azi: getc stuff
#endif
*count = bvCount;
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/pci_setup.c
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#include "bootstruct.h"
#include "pci.h"
#include "modules.h"
#include "modules.h"
extern void set_eth_builtin(pci_dt_t *eth_dev);
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/smbios.c
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{
switch (Platform.CPU.Model)
{
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
case 0x19:// Intel Core i5 650 @3.20 Ghz
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
defaultBIOSInfo.version= kDefaultiMacNehalemBIOSVersion;
defaultSystemInfo.productName= kDefaultiMacNehalem;
defaultSystemInfo.family= kDefaultiMacFamily;
break;
case CPU_MODEL_SANDY:
case CPU_MODEL_SANDY_XEON:
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_SANDY_XEON:// Intel Xeon E3
defaultBIOSInfo.version= kDefaultiMacSandyBIOSVersion;
defaultSystemInfo.productName= kDefaultiMacSandy;
defaultSystemInfo.family= kDefaultiMacFamily;
break;
case CPU_MODEL_NEHALEM:
case CPU_MODEL_NEHALEM_EX:
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
defaultBIOSInfo.version= kDefaultMacProNehalemBIOSVersion;
defaultSystemInfo.productName= kDefaultMacProNehalem;
defaultSystemInfo.family= kDefaultMacProFamily;
break;
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
defaultBIOSInfo.version= kDefaultMacProWestmereBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaulMacProWestmereBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultMacProWestmere;
{
switch (Platform.CPU.Model)
{
case 0x19:// Intel Core i5 650 @3.20 Ghz
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
break;
default:
for (i = 0; i < numOfSetters; i++)
if ((structPtr->orig->type == SMBSetters[i].type) && (SMBSetters[i].fieldOffset < structPtr->orig->length))
{
if (SMBSetters[i].fieldOffset > structPtr->orig->length)
continue;
setterFound = true;
setSMBValue(structPtr, i, (returnType *)((uint8_t *)structPtr->new + SMBSetters[i].fieldOffset));
}
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/cpu.h
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#define MSR_TURBO_RATIO_LIMIT0x1AD
#defineMSR_PLATFORM_INFO0xCE
#define MSR_CORE_THREAD_COUNT0x35// Undocumented
#define MSR_IA32_PLATFORM_ID0x17
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_STATUS0xC0010071
#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
// CPUID Values
#define CPUID_MODEL_YONAH14
#define CPUID_MODEL_MEROM15
#define CPUID_MODEL_PENRYN23
#define CPUID_MODEL_NEHALEM26
#define CPUID_MODEL_ATOM 28
#define CPUID_MODEL_FIELDS30/* Lynnfield, Clarksfield, Jasper */
#define CPUID_MODEL_DALES31/* Havendale, Auburndale */
#define CPUID_MODEL_NEHALEM_EX46
#define CPUID_MODEL_DALES_32NM37/* Clarkdale, Arrandale */
#define CPUID_MODEL_WESTMERE44/* Gulftown, Westmere-EP, Westmere-WS */
#define CPUID_MODEL_WESTMERE_EX47
#define CPUID_MODEL_YONAH14// Intel Mobile Core Solo, Duo
#define CPUID_MODEL_MEROM15// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
#define CPUID_MODEL_PENRYN23// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
#define CPUID_MODEL_NEHALEM26// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
#define CPUID_MODEL_ATOM28// Intel Atom (45nm)
#define CPUID_MODEL_FIELDS30// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
#define CPUID_MODEL_DALES31// Havendale, Auburndale
#define CPUID_MODEL_DALES_32NM37// Intel Core i3, i5 LGA1156 (32nm)
#define CPUID_MODEL_SANDY42// Intel Core i3, i5, i7 LGA1155 (32nm)
#define CPUID_MODEL_WESTMERE44// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
#define CPUID_MODEL_NEHALEM_EX46// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
#define CPUID_MODEL_WESTMERE_EX47// Intel Xeon E7
static inline uint64_t rdtsc64(void)
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/hpet.c
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#include "hpet.h"
#ifndef DEBUG_HPET
#define DEBUG_HPET 0
#define DEBUG_HPET 1
#endif
#if DEBUG_HPET
}
#if DEBUG_HPET
printf("Press [Enter] to continue...\n");
getc();
printf("Press [Enter] to continue...\n"); // replace by pause() function, console.c
getchar(); //getc(); Azi: getc stuff
#endif
}
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/biosfn.c
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2007-12-29 dfe
- Added ebiosEjectMedia
*/
//#define DEBUG 1
#include "bootstruct.h"
#include "libsaio.h"
#define MAX_DRIVES 8
static biosBuf_t bb;
// Some BIOSes will simply ignore the value of ECX on entry.
// Probably best to keep its value at 20 to avoid surprises.
//printf("Get memory map 0x%x, %d\n", rangeArray);getc();
//printf("Get memory map 0x%x, %d\n", rangeArray); getchar(); //getc(); Azi: getc stuff
if (maxRangeCount > (BIOS_LEN / sizeof(MemoryRange))) {
maxRangeCount = (BIOS_LEN / sizeof(MemoryRange));
}
#if DEBUG
{
int i;
printf("%d total ranges\n", count);getc();
printf("%d total ranges\n", count); getchar(); //getc(); Azi: getc stuff
for (i=0, range = rangeArray; i<count; i++, range++) {
printf("range: type %d, base 0x%x, length 0x%x\n",
range->type, (unsigned int)range->base, (unsigned int)range->length); getc();
range->type, (unsigned int)range->base, (unsigned int)range->length); getchar(); //getc(); Azi: getc stuff
}
}
#endif
printf("media_type: %x\n", pkt.media_type);
printf("drive_num: %x\n", pkt.drive_num);
printf("device_spec: %x\n", pkt.device_spec);
printf("press a key->\n");getc();
printf("press a key->\n"); getchar(); //getc(); Azi: getc stuff
#endif
/* Some BIOSes erroneously return cf = 1 */
print_drive_info(di);
printf("uses_ebios = 0x%x\n", dp->uses_ebios);
printf("result %d\n", ret);
printf("press a key->\n");getc();
printf("press a key->\n"); getchar(); //getc(); Azi: getc stuff
#endif
if (ret == 0) {
branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/smbios_getters.c
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{
switch (Platform.CPU.Model)
{
case 0x0D:// ?
case CPU_MODEL_YONAH:// Yonah0x0E
case CPU_MODEL_MEROM:// Merom0x0F
case CPU_MODEL_PENRYN:// Penryn0x17
case CPU_MODEL_ATOM:// Atom 45nm0x1C
case 0x0D:// ???
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
return false;
case 0x19:// Intel Core i5 650 @3.20 Ghz
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm)
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
case CPU_MODEL_WESTMERE_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
{
// thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
{
switch (Platform.CPU.Model)
{
case 0x0D:// ?
case CPU_MODEL_YONAH:// Yonah
case CPU_MODEL_MEROM:// Merom
case CPU_MODEL_PENRYN:// Penryn
case 0x0D:// ???
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
return true;
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
if (strstr(Platform.CPU.BrandString, "Xeon(R)"))
value->word = 0x0501;// Xeon
else
return true;
case CPU_MODEL_FIELDS:// Lynnfield, Clarksfield, Jasper
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
value->word = 0x601;// Core i5
value->word = 0x0601;// Core i5
else
value->word = 0x0701;// Core i7
value->word = 0x0701;// Core i7
return true;
case CPU_MODEL_DALES:// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)
case CPU_MODEL_DALES:
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
value->word = 0x601;// Core i5
value->word = 0x0601;// Core i5
else
value->word = 0x0701;// Core i7
value->word = 0x0701;// Core i7
return true;
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 sandy bridge
case CPU_MODEL_SANDY_XEON:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_SANDY_XEON:// Intel Xeon E3
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))
value->word = 0x901;// Core i3
value->word = 0x0901;// Core i3
else
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
value->word = 0x601;// Core i5
value->word = 0x0601;// Core i5
else
value->word = 0x0701;// Core i7
value->word = 0x0701;// Core i7
return true;
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)
case CPU_MODEL_WESTMERE_EX:// Intel Core i7 LGA1366 (45nm) 6 Core ???
value->word = 0x0501;// Core i7
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
value->word = 0x0501;// Core i7
return true;
case 0x19:// Intel Core i5 650 @3.20 Ghz
value->word = 0x601;// Core i5
case 0x19:// ??? Intel Core i5 650 @3.20 GHz
value->word = 0x0601;// Core i5
return true;
}
}
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#define kBootBannerKey"Boot Banner"
#define kWaitForKeypressKey"Wait"
//#define kUseAtiROM"UseAtiROM"/* ati.c */
//#define kAtiConfig"AtiConfig"/* ati.c */
//#define kATYbinimage"ATYbinimage"/* ati.c */
#define kWake"Wake"/* boot.c */
#define kForceWake"ForceWake"/* boot.c */
#define kWakeImage"WakeImage"/* boot.c */
#define kProductVersion"ProductVersion"/* boot.c */
#define karch"arch"/* boot.c */
#define kUseKernelCache"UseKernelCache"/* boot.c */
#define kDSDT"DSDT"/* acpi_patcher.c */
#define kDropSSDT"DropSSDT"/* acpi_patcher.c */
#define kRestartFix"RestartFix"/* acpi_patcher.c */
#define kEnableC3States"EnableC3State"/* acpi_patcher.c */
#define kEnableC4States"EnableC4State"/* acpi_patcher.c */
#define kWake"Wake"/* boot.c */
#define kForceWake"ForceWake"/* boot.c */
#define kWakeImage"WakeImage"/* boot.c */
#define kProductVersion"ProductVersion"/* boot.c */
#define karch"arch"/* boot.c */
#define kUseKernelCache"UseKernelCache"/* boot.c */
#define kbusratio"busratio"/* cpu.c */
#define kDeviceProperties"device-properties"/* device_inject.c */
#define kHidePartition"Hide Partition"/* disk.c */
#define kSystemID"SystemId"/* fake_efi.c */
#define kSystemType"SystemType"/* fake_efi.c */
//#define kUseNvidiaROM"UseNvidiaROM"/* nvidia.c */
//#define kUseAtiROM"UseAtiROM"/* ati.c */
//#define kAtiConfig"AtiConfig"/* ati.c */
//#define kATYbinimage"ATYbinimage"/* ati.c */
//#define kUseNvidiaROM"UseNvidiaROM"/* nvidia.c */
//#define kVBIOS"VBIOS"/* nvidia.c */
//#define kdcfg0 "display_0"/* nvidia.c */
//#define kdcfg1 "display_1"/* nvidia.c */
#define kPCIRootUID"PCIRootUID"/* pci_root.c */
#define kEthernetBuiltIn"EthernetBuiltIn"/* pci_setup.c */
//#define kGraphicsEnabler"GraphicsEnabler"/* pci_setup.c */
#define kGraphicsEnabler"GraphicsEnabler"/* pci_setup.c */
#define kForceHPET"ForceHPET"/* pci_setup.c */
#define kUseMemDetect"UseMemDetect" /* platform.c */
#define kMD0Image"md0"/* ramdisk.h */
#define kSMBIOSdefaults"SMBIOSdefaults"/* smbios_patcher.c */
#define kDefaultPartition"Default Partition"/* sys.c */
#define kUSBBusFix"USBBusFix"/* usb.c */
#define kEHCIacquire"EHCIacquire"/* usb.c */
#define kUHCIreset"UHCIreset"/* usb.c */
#define kLegacyOff"USBLegacyOff"/* usb.c */
#define kEHCIhard"EHCIhard"/* usb.c */
#define kDefaultPartition"Default Partition"/* sys.c */
#define kMD0Image"md0"/* ramdisk.h */
#define kbusratio"busratio"/* cpu.c */
/*
* Flags to the booter or kernel
*/
branches/azimutz/trunkGraphicsEnablerModules/i386/boot2/modules.h
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struct moduleHook_t* next;
} moduleHook_t;
typedef struct moduleList_t //Azi: modules or module? see modules/include/modules
typedef struct modulesList_t
{
const char*name;
const char* author;
const char* description;
UInt32version;
UInt32compat;
struct moduleList_t*next;
struct modulesList_t* next;
} moduleList_t;
branches/azimutz/trunkGraphicsEnablerModules/i386/modules/Resolution/915resolution.c
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if((id & 0x0000FFFF) == 0x00008086) // Intel chipset
{
//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);
//getchar();
//getc();
type = CT_UNKNOWN_INTEL;
//type = CT_UNKNOWN;
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278419
420
279421
422
280423
281424
282425
......
287430
288431
289432
433
434
290435
291436
292437
......
294439
295440
296441
297
442
443
298444
445
299446
300447
301448
449
302450
303451
304452
......
307455
308456
309457
458
459
460
461
462
463
464
465
466
467
310468
311469
312470
......
320478
321479
322480
481
482
323483
484
485
486
324487
325488
326489
327490
328491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
329518
330519
520
521
331522
332523
524
525
333526
334527
335528
336529
337530
338531
532
339533
340534
341535
536
342537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
343586
587
588
589
590
591
592
593
594
595
344596
345
597
598
346599
347600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
348629
630
349631
350632
351633
352634
635
636
637
638
353639
640
641
642
643
644
354645
355646
356647
648
357649
358650
651
652
653
654
655
656
657
658
659
660
661
662
359663
360664
361665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
362704
705
706
363707
364708
709
710
711
712
365713
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
387732
388733
389734
......
391736
392737
393738
739
394740
395741
396742
397743
398744
399745
746
747
400748
401749
750
402751
403752
753
404754
405755
406756
......
408758
409759
410760
411
412
761
762
763
413764
414765
415766
416767
417768
769
418770
419771
420772
421773
422
423
424
425
426
427
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
428813
429
430
814
815
431816
817
818
432819
433820
821
822
823
824
825
826
827
828
434829
435830
436831
......
441836
442837
443838
444
445839
446840
447
448841
449842
450843
......
454847
455848
456849
457
850
458851
459852
460853
......
462855
463856
464857
465
466858
467859
468860
469861
470
471862
472863
473864
......
480871
481872
482873
483
484
874
485875
486876
487
488
489
490
491
877
878
879
880
492881
493
494
495
882
883
884
496885
497
498
886
499887
500888
501
502
889
503890
504
891
505892
506
507893
508
509
510
894
511895
512896
513897
514
515
516
898
517899
518900
519901
520
521
522
902
523903
524904
525905
526906
527
528
529
907
530908
531909
532910
533
534
535
911
536912
537913
538914
539915
540
916
541917
542918
543
544
545
546
919
920
547921
548922
549923
550924
551925
552
553
926
554927
555928
556
557929
558930
559931
......
565937
566938
567939
940
568941
569942
570943
571944
572945
573
574
575
576
946
947
577948
578949
579950
580951
581952
582953
583
584954
585
586
587
588
589
955
956
957
590958
591
592959
593960
594961
595
596
597
962
963
598964
599965
600
601
602
603
604
966
967
968
605969
606970
607971
608972
609
610
611
612
973
974
613975
614976
615977
616978
617
618
619
979
620980
621981
622982
623983
624
625
984
626985
627986
628987
629988
630989
631
632990
633991
634992
635993
636
637
638
994
639995
640996
641997
642998
643
644
999
6451000
6461001
6471002
6481003
6491004
1005
6501006
6511007
6521008
......
6571013
6581014
6591015
660
661
662
663
664
1016
1017
6651018
666
667
1019
6681020
669
6701021
6711022
672
6731023
674
675
1024
6761025
6771026
6781027
......
6821031
6831032
6841033
685
686
687
688
1034
1035
6891036
690
6911037
692
6931038
694
6951039
1040
6961041
6971042
6981043
699
700
701
702
703
704
705
1044
1045
1046
1047
1048
7061049
7071050
7081051
......
7111054
7121055
7131056
714
715
716
717
718
1057
1058
1059
1060
7191061
7201062
721
7221063
723
724
725
726
727
1064
1065
7281066
7291067
7301068
7311069
732
7331070
7341071
7351072
7361073
7371074
738
739
740
1075
1076
1077
7411078
742
743
1079
1080
7441081
745
1082
7461083
747
1084
7481085
749
1086
7501087
751
1088
7521089
753
1090
7541091
755
1092
7561093
757
7581094
7591095
7601096
7611097
7621098
763
1099
7641100
7651101
7661102
7671103
7681104
7691105
770
1106
7711107
7721108
7731109
......
7771113
7781114
7791115
780
781
782
1116
7831117
7841118
7851119
......
7951129
7961130
7971131
798
799
1132
8001133
8011134
8021135
803
804
1136
8051137
8061138
8071139
8081140
809
810
1141
8111142
8121143
8131144
1145
1146
1147
1148
1149
1150
1151
1152
1153
8141154
8151155
8161156
8171157
8181158
8191159
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
8401181
8411182
8421183
8431184
8441185
8451186
846
1187
8471188
8481189
8491190
8501191
851
1192
8521193
8531194
8541195
855
1196
8561197
857
858
859
860
861
1198
1199
8621200
8631201
864
865
866
1202
8671203
8681204
869
870
871
1205
8721206
8731207
8741208
875
876
877
1209
8781210
8791211
880
1212
8811213
882
1214
8831215
8841216
8851217
8861218
8871219
888
889
1220
8901221
8911222
8921223
893
1224
8941225
8951226
8961227
8971228
898
899
1229
1230
9001231
901
902
1232
9031233
9041234
9051235
9061236
907
908
1237
9091238
9101239
911
912
913
1240
9141241
9151242
916
917
918
1243
9191244
9201245
921
922
923
1246
9241247
9251248
9261249
927
1250
9281251
9291252
9301253
9311254
932
1255
9331256
934
1257
9351258
936
937
938
939
1259
1260
9401261
9411262
942
943
944
1263
9451264
9461265
9471266
948
1267
9491268
9501269
9511270
9521271
953
1272
9541273
9551274
9561275
957
958
1276
1277
9591278
9601279
9611280
......
9631282
9641283
9651284
966
9671285
968
9691286
9701287
971
9721288
973
974
975
976
1289
1290
9771291
9781292
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
9981303
1304
1305
1306
9991307
10001308
1001
1309
10021310
10031311
10041312
10051313
10061314
1315
10071316
1008
1009
1010
1011
1012
1013
1014
1317
1318
1319
1320
10151321
10161322
10171323
10181324
1019
1020
1021
1022
1023
1024
1025
1026
1325
1326
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1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
10271369
10281370
10291371
......
10311373
10321374
10331375
1034
1035
1036
1376
1377
1378
1379
1380
10371381
10381382
1039
1383
10401384
10411385
10421386
1043
1387
10441388
10451389
/*
*NVidia injector
* NVidia injector
*
*Copyright (C) 2009Jasmin Fazlic, iNDi
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
*NVidia injector is free software: you can redistribute it and/or modify
*it under the terms of the GNU General Public License as published by
*the Free Software Foundation, either version 3 of the License, or
*(at your option) any later version.
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
*NVidia driver and injector is distributed in the hope that it will be useful,
*but WITHOUT ANY WARRANTY; without even the implied warranty of
*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*GNU General Public License for more details.
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*You should have received a copy of the GNU General Public License
*along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
* SOFTWARE.
*/
#include "libsa.h"
#include "saio_internal.h"
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#define kUseNvidiaROM"UseNvidiaROM"
#define kVBIOS"VBIOS"
#define kdcfg0"display_0"
#define kdcfg1"display_1"
#define NVIDIA_ROM_SIZE0x10000
#define PATCH_ROM_SUCCESS1
#define PATCH_ROM_SUCCESS_HAS_LVDS2
#define PATCH_ROM_FAILED0
#define MAX_NUM_DCB_ENTRIES16
#define TYPE_GROUPED0xff
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type", "display" };
const char *nvidia_device_type_1[]={ "@1,device_type", "display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name", "Slot-1" };
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
//const char *nvidia_display_cfg_0[] = { "@0,display-cfg
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static uint8_t default_dcfg_0[]={0xff, 0xff, 0xff, 0xff};
static uint8_t default_dcfg_1[]={0xff, 0xff, 0xff, 0xff};
#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )
#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
//Azi: REVIEW and style
{ 0x00000000, "Unknown" },
// 0040 - 004F
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004D, "Quadro FX 3400" },
{ 0x10DE004E, "Quadro FX 4000" },
// 0050 - 005F
// 0060 - 006F
// 0070 - 007F
// 0080 - 008F
// 0090 - 009F
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
// 00A0 - 00AF
// 00B0 - 00BF
// 00C0 - 00CF
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
// 00D0 - 00DF
// 00E0 - 00EF
// 00F0 - 00FF
{ 0x10DE00F1, "GeForce 6600 GT" },
{ 0x10DE00F2, "GeForce 6600" },
{ 0x10DE00F3, "GeForce 6200" },
{ 0x10DE00F4, "GeForce 6600 LE" },
{ 0x10DE00F5, "GeForce 7800 GS" },
{ 0x10DE00F6, "GeForce 6800 GS/XT" },
{ 0x10DE00F8, "Quadro FX 3400/4400" },
{ 0x10DE00F9, "GeForce 6800 Series GPU" },
// 0100 - 010F
// 0110 - 011F
// 0120 - 012F
// 0130 - 013F
// 0140 - 014F
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014A, "Quadro NVS 440" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
// 0150 - 015F
// 0160 - 016F
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
// 0170 - 017F
// 0180 - 018F
// 0190 - 019F
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE0197, "Tesla C870" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
// 01A0 - 01AF
// 01B0 - 01BF
// 01C0 - 01CF
// 01D0 - 01DF
{ 0x10DE01D0, "GeForce 7350 LE" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D2, "GeForce 7550 LE" },
{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
// 01E0 - 01EF
// 01F0 - 01FF
// 0200 - 020F
// 0210 - 021F
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
// 0220 - 022F
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
// 0230 - 023F
// 0240 - 024F
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },
{ 0x10DE0247, "GeForce Go 6100" },
// 0250 - 025F
// 0260 - 026F
// 0270 - 027F
// 0280 - 028F
// 0290 - 029F
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0291, "GeForce 7900 GT/GTO" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0293, "GeForce 7950 GX2" },
{ 0x10DE0294, "GeForce 7950 GX2" },
{ 0x10DE0295, "GeForce 7950 GT" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
// 02A0 - 02AF
// 02B0 - 02BF
// 02C0 - 02CF
// 02D0 - 02DF
// 02E0 - 02EF
{ 0x10DE02E0, "GeForce 7600 GT" },
{ 0x10DE02E1, "GeForce 7600 GS" },
{ 0x10DE02E2, "GeForce 7300 GT" },
{ 0x10DE02E3, "GeForce 7900 GS" },
{ 0x10DE02E4, "GeForce 7950 GT" },
// 02F0 - 02FF
// 0300 - 030F
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
// 0310 - 031F
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
// 0320 - 032F
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
// 0330 - 033F
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
// 0340 - 034F
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
// 0350 - 035F
// 0360 - 036F
// 0370 - 037F
// 0380 - 038F
{ 0x10DE038B, "GeForce 7650 GS" },
// 0390 - 039F
{ 0x10DE0390, "GeForce 7650 GS" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
// 03A0 - 03AF
// 03B0 - 03BF
// 03C0 - 03CF
// 03D0 - 03DF
{ 0x10DE03D0, "GeForce 6150SE nForce 430" },
{ 0x10DE03D1, "GeForce 6100 nForce 405" },
{ 0x10DE03D2, "GeForce 6100 nForce 400" },
{ 0x10DE03D5, "GeForce 6100 nForce 420" },
{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },
// 03E0 - 03EF
// 03F0 - 03FF
// 0400 - 040F
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0406, "GeForce 8300 GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
// 0410 - 041F
{ 0x10DE0410, "GeForce GT 330" },
// 0420 - 042F
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
// 0430 - 043F
// 0440 - 044F
// 0450 - 045F
// 0460 - 046F
// 0470 - 047F
// 0480 - 048F
// 0490 - 049F
// 04A0 - 04AF
// 04B0 - 04BF
// 04C0 - 04CF
// 04D0 - 04DF
// 04E0 - 04EF
// 04F0 - 04FF
// 0500 - 050F
// 0510 - 051F
// 0520 - 052F
// 0530 - 053F
{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053E, "GeForce 7025 / nForce 630a" },
// 0540 - 054F
// 0550 - 055F
// 0560 - 056F
// 0570 - 057F
// 0580 - 058F
// 0590 - 059F
// 05A0 - 05AF
// 05B0 - 05BF
// 05C0 - 05CF
// 05D0 - 05DF
// 05E0 - 05EF
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05ED, "Quadroplex 2200 D2" },
// 05F0 - 05FF
{ 0x10DE05F8, "Quadroplex 2200 S4" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE05FF, "Quadro FX 3800" },
// 0600 - 060F
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0601, "GeForce 9800 GT" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0603, "GeForce GT 230" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE060F, "GeForce GTX 285M" },
// 0610 - 061F
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE0619, "Quadro FX 4700 X2" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061B, "Quadro VX 200" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
// 0620 - 062F
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE062D, "GeForce 9600 GT" },
{ 0x10DE062E, "GeForce 9600 GT" },
// 0630 - 063F
{ 0x10DE0631, "GeForce GTS 160M" },
{ 0x10DE0632, "GeForce GTS 150M" },
{ 0x10DE0635, "GeForce 9600 GSO" },
{ 0x10DE0637, "GeForce 9600 GT" },
{ 0x10DE0638, "Quadro FX 1800" },
{ 0x10DE063A, "Quadro FX 2700M" },
// 0640 - 064F
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
// 0650 - 065F
{ 0x10DE0651, "GeForce G 110M" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0653, "GeForce GT 120M" },
{ 0x10DE0654, "GeForce GT 220M" },
{ 0x10DE0656, "GeForce 9650 S" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE065F, "GeForce G210" },
// 0660 - 066F
// 0670 - 067F
// 0680 - 068F
// 0690 - 069F
// 06A0 - 06AF
// 06B0 - 06BF
// 06C0 - 06CF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
// 06D0 - 06DF
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DD, "Quadro 4000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
// 06E0 - 06EF
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E2, "GeForce 8400" },
{ 0x10DE06E3, "GeForce 8400 SE" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E6, "GeForce G100" },
{ 0x10DE06E7, "GeForce 9300 SE" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
// 06F0 - 06FF
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FB, "Quadro FX 370M" },
{ 0x10DE06FD, "Quadro NVS 295" },
// 0700 - 070F
// 0710 - 071F
// 0720 - 072F
// 0730 - 073F
// 0740 - 074F
// 0750 - 075F
// 0760 - 076F
// 0770 - 077F
// 0780 - 078F
// 0790 - 079F
// 07A0 - 07AF
// 07B0 - 07BF
// 07C0 - 07CF
// 07D0 - 07DF
// 07E0 - 07EF
{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },
{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },
{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },
{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },
{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },
// 07F0 - 07FF
// 0800 - 080F
// 0810 - 081F
// 0820 - 082F
// 0830 - 083F
// 0840 - 084F
{ 0x10DE0844, "GeForce 9100M G" },
{ 0x10DE0845, "GeForce 8200M G" },
{ 0x10DE0846, "GeForce 9200" },
{ 0x10DE0847, "GeForce 9100" },
{ 0x10DE0848, "GeForce 8300" },
{ 0x10DE0849, "GeForce 8200" },
{ 0x10DE084A, "nForce 730a" },
{ 0x10DE084B, "GeForce 9200" },
{ 0x10DE084C, "nForce 980a/780a SLI" },
{ 0x10DE084D, "nForce 750a SLI" },
{ 0x10DE084F, "GeForce 8100 / nForce 720a" },
// 0850 - 085F
// 0860 - 086F
{ 0x10DE0860, "GeForce 9400" },
{ 0x10DE0861, "GeForce 9400" },
{ 0x10DE0862, "GeForce 9400M G" },
{ 0x10DE0863, "GeForce 9400M" },
{ 0x10DE0864, "GeForce 9300" },
{ 0x10DE0865, "ION" },
{ 0x10DE0866, "GeForce 9400M G" },
{ 0x10DE0867, "GeForce 9400" },
{ 0x10DE0868, "nForce 760i SLI" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE086C, "GeForce 9300 / nForce 730i" },
{ 0x10DE086D, "GeForce 9200" },
{ 0x10DE086E, "GeForce 9100M G" },
{ 0x10DE086F, "GeForce 8200M G" },
// 0870 - 087F
{ 0x10DE0870, "GeForce 9400M" },
{ 0x10DE0871, "GeForce 9200" },
{ 0x10DE0872, "GeForce G102M" },
{ 0x10DE0873, "GeForce G102M" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE0876, "ION" },
{ 0x10DE087A, "GeForce 9400" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE087F, "ION LE" },
// 0880 - 088F
// 0890 - 089F
// 08A0 - 08AF
// 08B0 - 08BF
// 08C0 - 08CF
// 08D0 - 08DF
// 08E0 - 08EF
// 08F0 - 08FF
// 0900 - 090F
// 0910 - 091F
// 0920 - 092F
// 0930 - 093F
// 0940 - 094F
// 0950 - 095F
// 0960 - 096F
// 0970 - 097F
// 0980 - 098F
// 0990 - 099F
// 09A0 - 09AF
// 09B0 - 09BF
// 09C0 - 09CF
// 09D0 - 09DF
// 09E0 - 09EF
// 09F0 - 09FF
// 0A00 - 0A0F
// 0A10 - 0A1F
// 0A20 - 0A2F
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A22, "GeForce 315" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A2B, "GeForce GT 330M" },
{ 0x10DE0A2C, "NVS 5100M" },
{ 0x10DE0A2D, "GeForce GT 320M" },
// 0A30 - 0A3F
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A35, "GeForce GT 325M" },
{ 0x10DE0A3C, "Quadro FX 880M" },
// 0A40 - 0A4F
// 0A50 - 0A5F
// 0A60 - 0A6F
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A64, "ION" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A67, "GeForce 315" },
{ 0x10DE0A68, "GeForce G105M" },
{ 0x10DE0A69, "GeForce G105M" },
{ 0x10DE0A6A, "NVS 2100M" },
{ 0x10DE0A6C, "NVS 3100M" },
{ 0x10DE0A6E, "GeForce 305M" },
{ 0x10DE0A6F, "ION" },
// 0A70 - 0A7F
{ 0x10DE0A70, "GeForce 310M" },
{ 0x10DE0A71, "GeForce 305M" },
{ 0x10DE0A72, "GeForce 310M" },
{ 0x10DE0A73, "GeForce 305M" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0A7C, "Quadro FX 380M" },
// 0A80 - 0A8F
// 0A90 - 0A9F
// 0AA0 - 0AAF
// 0AB0 - 0ABF
// 0AC0 - 0ACF
// 0AD0 - 0ADF
// 0AE0 - 0AEF
// 0AF0 - 0AFF
// 0B00 - 0B0F
// 0B10 - 0B1F
// 0B20 - 0B2F
// 0B30 - 0B3F
// 0B40 - 0B4F
// 0B50 - 0B5F
// 0B60 - 0B6F
// 0B70 - 0B7F
// 0B80 - 0B8F
// 0B90 - 0B9F
// 0BA0 - 0BAF
// 0BB0 - 0BBF
// 0BC0 - 0BCF
// 0BD0 - 0BDF
// 0BE0 - 0BEF
// 0BF0 - 0BFF
// 0C00 - 0C0F
// 0C10 - 0C1F
// 0C20 - 0C2F
// 0C30 - 0C3F
// 0C40 - 0C4F
// 0C50 - 0C5F
// 0C60 - 0C6F
// 0C70 - 0C7F
// 0C80 - 0C8F
// 0C90 - 0C9F
// 0CA0 - 0CAF
{ 0x10DE0CA0, "GeForce GT 330 " },
{ 0x10DE0CA2, "GeForce GT 320" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA4, "GeForce GT 340" },
{ 0x10DE0CA7, "GeForce GT 330" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CAC, "GeForce 315" },
{ 0x10DE0CAF, "GeForce GT 335M" },
// 0CB0 - 0CBF
{ 0x10DE0CB0, "GeForce GTS 350M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CA3, "GeForce GT240" },
// 06C0 - 06DFF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
// 0DC0 - 0DFF
{ 0x10DE0CBC, "Quadro FX 1800M" },
// 0CC0 - 0CCF
// 0CD0 - 0CDF
// 0CE0 - 0CEF
// 0CF0 - 0CFF
// 0D00 - 0D0F
// 0D10 - 0D1F
// 0D20 - 0D2F
// 0D30 - 0D3F
// 0D40 - 0D4F
// 0D50 - 0D5F
// 0D60 - 0D6F
// 0D70 - 0D7F
// 0D80 - 0D8F
// 0D90 - 0D9F
// 0DA0 - 0DAF
// 0DB0 - 0DBF
// 0DC0 - 0DCF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
// 0DD0 - 0DDF
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
// 0DE0 - 0DEF
{ 0x10DE0DE0, "GeForce GT 440" },
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DE5, "GeForce GT 530" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
// 0DF0 - 0DFF
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E20 - 0E3F
// 0E00 - 0E0F
// 0E10 - 0E1F
// 0E20 - 0E2F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
// 0E30 - 0E3F
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0EE0 - 0EFF: none yet
// 0F00 - 0F3F: none yet
// 1040 - 107F: none yet
// 1080 - 109F
// 0E40 - 0E4F
// 0E50 - 0E5F
// 0E60 - 0E6F
// 0E70 - 0E7F
// 0E80 - 0E8F
// 0E90 - 0E9F
// 0EA0 - 0EAF
// 0EB0 - 0EBF
// 0EC0 - 0ECF
// 0ED0 - 0EDF
// 0EE0 - 0EEF
// 0EF0 - 0EFF
// 0F00 - 0F0F
// 0F10 - 0F1F
// 0F20 - 0F2F
// 0F30 - 0F3F
// 0F40 - 0F4F
// 0F50 - 0F5F
// 0F60 - 0F6F
// 0F70 - 0F7F
// 0F80 - 0F8F
// 0F90 - 0F9F
// 0FA0 - 0FAF
// 0FB0 - 0FBF
// 0FC0 - 0FCF
// 0FD0 - 0FDF
// 0FE0 - 0FEF
// 0FF0 - 0FFF
// 1000 - 100F
// 1010 - 101F
// 1020 - 102F
// 1030 - 103F
// 1040 - 104F
{ 0x10DE1040, "GeForce GT 520" },
// 1050 - 105F
{ 0x10DE1050, "GeForce GT 520M" },
// 1060 - 106F
// 1070 - 107F
// 1080 - 108F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "D13U" },
{ 0x10DE1082, "D13U" },
{ 0x10DE1081, "GeForce GTX 570" },
{ 0x10DE1082, "GeForce GTX 560 Ti" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1088, "GeForce GTX 590" },
// 1090 - 109F
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
// 10A0 - 10AF
// 10B0 - 10BF
// 10C0 - 10CF
{ 0x10DE10C3, "GeForce 8400 GS" },
// 1200 -
{ 0x10DE1200, "GeForce GTX 560 Ti" },
{ 0x10DE1244, "GeForce GTX 550 Ti" },
{ 0x10DE1245, "GeForce GTS 450" },
};
static uint16_t swap16(uint16_t x)
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_tread8(uint8_t *ptr, uint16_t offset)
static uint8_t read8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if (!dcbptr) {
if(!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}
//else
//printf("dcb table at offset 0x%04x\n", dcbptr);
uint8_t *dcbtable = &rom[dcbptr];
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if (dcbtable_version >= 0x20)
{
if(dcbtable_version >= 0x20) {
uint32_t sig;
if (dcbtable_version >= 0x30)
{
if(dcbtable_version >= 0x30) {
headerlength = dcbtable[1];
numentries = dcbtable[2];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
}
else
{
} else {
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb)
{
if (sig != 0x4edcbdcb) {
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
}
else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */
{
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC"))
{
if (strcmp(sig, "DEV_REC")) {
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
}
else
{
} else {
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if (numentries >= MAX_NUM_DCB_ENTRIES)
if(numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i = 0;
struct dcbentry
{
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++)
{
for (i = 0; i < numentries; i++) {
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == 3)
{
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if (has_lvds)
{
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
else
{
} else {
//
int x;
// we loop twice as we need to generate two channels
for (x = 0; x <= 1; x++)
{
for (i=0; i<num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if (i && entries[i].type == 0x2)
{
switch (x)
{
if(i && entries[i].type == 0x2) {
switch (x) {
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if ((entries[i-1].type == 0x0))
{
if((entries[i-1].type == 0x0)) {
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if ((entries[i - 1].type == 0x0))
{
if((entries[i-1].type == 0x0)) {
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type != TYPE_GROUPED)
{
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
//printf("%d not grouped\n", i);
if (togroup)
{
if(togroup)
*togroup |= ( 0x1 << entries[i].index);
}
entries[i].type = TYPE_GROUPED;
}
}
if (channel1 > channel2)
{
if(channel1 > channel2) {
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
default_NVCAP[8] = channel2;
// patching HEADS
for (i = 0; i < num_outputs; i++)
{
if (channel1 & (1 << i))
{
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
*entries[i].heads = 1;
}
else if(channel2 & (1 << i))
{
*entries[i].heads = 2;
}
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id)
{
int i;
for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id)
{
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
return NVKnownChipsets[i].name;
}
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
int fd;
int size;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize)
{
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",
filename, bufsize);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
char tmp[16];
if (!device)
chartmp[16];
if(!device)
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
buf[2] = '\0';
p = (char *) hex;
for (i = 0; i < len; i++)
{
for (i=0; i<len; i++) {
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50)
{
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0)
{
else if (nvCardType < NV_ARCH_C0) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else // >= NV_ARCH_C0
{
else { // >= NV_ARCH_C0
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
// Workaround for GT 420/430 & 9600M GT
switch (nvda_dev->device_id)
{
case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430
case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420
case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT
default: break;
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t *rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,
(uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit)
{
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0)
{
if (nvBiosOveride > 0) {
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
}
else
{
} else {
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
}
else
{
} else {
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
if (rom[0] != 0x55 && rom[1] != 0xaa) {
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
}
else
{
} else {
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
else
{
} else {
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
else
{
} else {
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
//return false;
}
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952)
{
if (rom_pci_header->device_id != nvda_dev->device_id)
{
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device_id != nvda_dev->device_id) {
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
}
else
{
} else {
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for (i = 0; i < 0x180; i++)
{
if (rom[i] == 0x0D && rom[i+1] == 0x0A)
{
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
crlf_count++;
// second 0x0D0A was found, extract bios version
if (crlf_count == 2)
{
if (rom[i-1] == 0x20) i--; // strip last " "
{
for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)
{
// find start
if (rom[version_start] == 0x00)
{
version_start++;
// strip "Version "
if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)
{
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
// find start
if(rom[version_start] == 0x00) {
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
break; //Azi: reminder
break;
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2)
{
uint8_t new_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)
{
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
if (getValueForKey(kdcfg0, &value, &len, &bootInfo->bootConfig) && len == DCFG0_LEN * 2){
uint8_t new_dcfg0[DCFG0_LEN];
if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)
{
memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);
verbose("Using user supplied @0,display-cfg\n");
printf("@0,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);
}
}
if (getValueForKey(kdcfg1, &value, &len, &bootInfo->bootConfig) && len == DCFG1_LEN * 2){
uint8_t new_dcfg1[DCFG1_LEN];
if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)
{
memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);
verbose("Using user supplied @1,display-cfg\n");
printf("@1,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit)
{
devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);
devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/trunkGraphicsEnablerModules/i386/libsa/memory.h
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# define BASE_SEG BOOT2_SEG
#endif
#define STACK_SEG 0x1000// zef: old STACK_SEG 0x5000
#define STACK_SEG 0x1000 // zef: old STACK_SEG 0x5000
#define STACK_OFS 0xFFF0 // stack pointer
#define BOOT1U_SEG 0x1000
branches/azimutz/trunkGraphicsEnablerModules/doc/BootHelp.txt
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The boot: prompt waits for you to type advanced startup options.
If you don't type anything, the computer continues starting up normally. It
uses the kernel and configuration files on the startup device, which it also
uses as the root device.
uses as the root device.
Advanced startup options use the following syntax:
Example: mach_kernel rd=disk0s1 -v "Graphics Mode"="1920x1200x32"
If the computer won't start up properly, you may be able to start it up
using safe mode. Type -x to start up in safe mode, which ignores all
If the computer won't start up properly, you may be able to start it up
using safe mode. Type -x to start up in safe mode, which ignores all
cached driver files.
Special booter hotkeys:
F5 Rescans optical drive.
F10 Scans and displays all BIOS accessible drives.
Special booter commands:
?memory Displays information about the computer's memory.
?video Displays VESA video modes supported by the computer's BIOS.
Wait=Yes|No Prompt for a key press before starting the kernel.
"Quiet Boot"=Yes|No Use quiet boot mode (no messages or prompt).
Timeout=8 Number of seconds to pause at the boot: prompt.
"Instant Menu"=Yes Force displaying the partition selection menu.
"Instant Menu"=Yes Force displaying the partition selection menu.
"Default Partition" Sets the default boot partition,
=hd(x,y)|UUID|"Label" Specified as a disk/partition pair, an UUID, or a
=hd(x,y)|UUID|"Label" Specified as a disk/partition pair, an UUID, or a
label enclosed in quotes.
"Hide Partition" Remove unwanted partition(s) from the boot menu.
=partition Specified, possibly multiple times, as hd(x,y), an
[;partition2 ...] UUID or label enclosed in quotes.
"Rename Partition" Rename partition(s) for the boot menu.
=partition <alias> Where partition is hd(x,y), UUID or label enclosed
[;partition2 <alias2> in quotes. The alias can optionally be quoted too.
[;partition2 <alias2> in quotes. The alias can optionally be quoted too.
...]
GUI=No Disable the GUI (enabled by default).
"Boot Banner"=Yes|No Show boot banner in GUI mode (enabled by default).
"Legacy Logo"=Yes|No Use the legacy grey apple logo (disabled by default).
PciRoot=<value> Use an alternate value for PciRoot (default value 0).
UseKernelCache=Yes|No Default is No. Yes will load pre-linked kernel and will
ignore /E/E and /S/L/E/Extensions.mkext.
GraphicsEnabler=Yes|No Automatic device-properties generation for gfx cards.
UseAtiROM=Yes|No Use an alternate Ati ROM image
AtiConfig=<cardcfg> Use a different card config
UseAtiROM=Yes|No Use an alternate Ati ROM image
(path: /Extra/<vendorid>_<devid>_<subsysid>.rom)
UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image
UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image
(path: /Extra/<vendorid>_<devid>.rom)
VBIOS=Yes|No Inject VBIOS to device-properties.
VBIOS=Yes|No Inject NVIDIA VBIOS into device-properties.
display_0=<value> Inject alternate value of display-cfg into NVDA,Display-A@0 (HEX).
display_1=<value> Inject alternate value of display-cfg into NVDA,Display-B@1 (HEX).
AtiConfig=<cardcfg> Use a different card config (the list can be found in ati.c).
EthernetBuiltIn=Yes|No Automatic "built-in"=yes device-properties generation
for ethernet interfaces.
Wake=No Disable wake up after hibernation (default: enabled).
ForceWake=Yes Force using the sleepimage (disabled by default).
WakeImage=<file> Use an alternate sleepimage file.
WakeImage=<file> Use an alternate sleepimage file.
(default path is /private/var/vm/sleepimage).
DropSSDT=Yes Skip the SSDT tables while relocating the ACPI tables.
DSDT=<file> Use an alternate DSDT.aml file
DSDT=<file> Use an alternate DSDT.aml file
(default paths:
/DSDT.aml /Extra/DSDT.aml bt(0,0)/Extra/DSDT.aml).
GenerateCStates=Yes Enable auto generation of Processor (C-States) and/or
GeneratePStates=Yes Performance (P-States) power states.
GenerateCStates=Yes Enable auto generation of processor idle sleep states
(C-States).
GeneratePStates=Yes Enable auto generation of processor power performance
states (P-States).
EnableC2State=Yes Enable specific Processor power states, C2,
EnableC3State=Yes C3
EnableC4State=Yes and C4.
EnableC2State=Yes Enable specific Processor power state, C2.
EnableC3State=Yes Enable specific Processor power state, C3.
EnableC4State=Yes Enable specific Processor power state, C4.
SMBIOS=<file> Use an alternate SMBIOS.plist file
SMBIOS=<file> Use an alternate SMBIOS.plist file
(default paths:
/Extra/SMBIOS.plist bt(0,0)/Extra/SMBIOS.plist).
SMBIOSdefaults=No Don't use the Default values for SMBIOS overriding
if smbios.plist doesn't exist, factory
values are kept.
SMBIOSdefaults=No Don't use the Default values for SMBIOS overriding if
smbios.plist doesn't exist, factory values are kept.
"Scan Single Drive" Scan the drive only where the booter got loaded from.
=Yes|No Fix rescan pbs when using a DVD reader in AHCI mode.
=Yes|No Fix rescan pbs when using a DVD reader in AHCI mode.
Rescan=Yes Enable CD-ROM rescan mode.
"Rescan Prompt"=Yes Prompts for enable CD-ROM rescan mode.
SystemId=<UUID> Set manually the system id UUID,
SMUUID in smbios config (reserved field) isn't used.
SystemType=<n> Set the system type where n is between 0..6
(default =1 (Desktop)
(default =1 (Desktop)
md0=<file> Load raw img file into memory for use as XNU's md0
ramdisk. /Extra/Postboot.img is used otherwise.

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Revision: 996