Index: branches/azimutz/Chazi/i386/libsaio/acpi_patcher.c =================================================================== --- branches/azimutz/Chazi/i386/libsaio/acpi_patcher.c (revision 1027) +++ branches/azimutz/Chazi/i386/libsaio/acpi_patcher.c (revision 1028) @@ -421,10 +421,10 @@ switch (Platform.CPU.Model) { case 0x0D: // ? - Azi: pentium M - Slice - case CPU_MODEL_YONAH: // Yonah - case CPU_MODEL_MEROM: // Merom - case CPU_MODEL_PENRYN: // Penryn - case CPU_MODEL_ATOM: // Intel Atom (45nm) + case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo + case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx + case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx + case CPU_MODEL_ATOM: // Intel Atom (45nm) { bool cpu_dynamic_fsb = false; @@ -542,15 +542,15 @@ break; } - case CPU_MODEL_FIELDS: - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: - case CPU_MODEL_NEHALEM: - case CPU_MODEL_NEHALEM_EX: - case CPU_MODEL_WESTMERE: - case CPU_MODEL_WESTMERE_EX: - case CPU_MODEL_SANDY: - case CPU_MODEL_SANDY_XEON: + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 { maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff; Index: branches/azimutz/Chazi/i386/libsaio/memvendors.h =================================================================== --- branches/azimutz/Chazi/i386/libsaio/memvendors.h (revision 1027) +++ branches/azimutz/Chazi/i386/libsaio/memvendors.h (revision 1028) @@ -14,7 +14,7 @@ } VenIdName; VenIdName vendorMap[] = { - { 0, 0x01, "AMD"}, + { 0, 0x01, "AMD"}, { 0, 0x02, "AMI"}, { 0, 0x83, "Fairchild"}, { 0, 0x04, "Fujitsu"}, Index: branches/azimutz/Chazi/i386/libsaio/platform.h =================================================================== --- branches/azimutz/Chazi/i386/libsaio/platform.h (revision 1027) +++ branches/azimutz/Chazi/i386/libsaio/platform.h (revision 1028) @@ -30,18 +30,18 @@ #define CPUID_81 6 #define CPUID_MAX 7 -#define CPU_MODEL_YONAH 0x0E -#define CPU_MODEL_MEROM 0x0F -#define CPU_MODEL_PENRYN 0x17 -#define CPU_MODEL_NEHALEM 0x1A -#define CPU_MODEL_ATOM 0x1C -#define CPU_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper +#define CPU_MODEL_YONAH 0x0E // Sossaman, Yonah +#define CPU_MODEL_MEROM 0x0F // Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom +#define CPU_MODEL_PENRYN 0x17 // Wolfdale, Yorkfield, Harpertown, Penryn +#define CPU_MODEL_NEHALEM 0x1A // Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown +#define CPU_MODEL_ATOM 0x1C // Atom +#define CPU_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper Forest #define CPU_MODEL_DALES 0x1F // Havendale, Auburndale #define CPU_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale -#define CPU_MODEL_SANDY 0x2a // Sandy bridge +#define CPU_MODEL_SANDY 0x2A // Sandy Bridge #define CPU_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS -#define CPU_MODEL_SANDY_XEON 0x2D -#define CPU_MODEL_NEHALEM_EX 0x2E +#define CPU_MODEL_SANDY_XEON 0x2D // Sandy Bridge Xeon +#define CPU_MODEL_NEHALEM_EX 0x2E // Beckton #define CPU_MODEL_WESTMERE_EX 0x2F /* CPU Features */ Index: branches/azimutz/Chazi/i386/libsaio/smbios.c =================================================================== --- branches/azimutz/Chazi/i386/libsaio/smbios.c (revision 1027) +++ branches/azimutz/Chazi/i386/libsaio/smbios.c (revision 1028) @@ -340,33 +340,33 @@ { switch (Platform.CPU.Model) { - case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) - case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) - case 0x19: // Intel Core i5 650 @3.20 Ghz + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case 0x19: // ??? Intel Core i5 650 @3.20 GHz defaultBIOSInfo.version = kDefaultiMacNehalemBIOSVersion; defaultSystemInfo.productName = kDefaultiMacNehalem; defaultSystemInfo.family = kDefaultiMacFamily; defaultBaseBoard.product = kDefaultiMacNehalemBoardProduct; break; - case CPU_MODEL_SANDY: - case CPU_MODEL_SANDY_XEON: + case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 defaultBIOSInfo.version = kDefaultiMacSandyBIOSVersion; defaultSystemInfo.productName = kDefaultiMacSandy; defaultSystemInfo.family = kDefaultiMacFamily; defaultBaseBoard.product = kDefaultiMacSandyBoardProduct; // ?? break; - case CPU_MODEL_NEHALEM: - case CPU_MODEL_NEHALEM_EX: + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x defaultBIOSInfo.version = kDefaultMacProNehalemBIOSVersion; defaultSystemInfo.productName = kDefaultMacProNehalem; defaultSystemInfo.family = kDefaultMacProFamily; defaultBaseBoard.product = kDefaultMacProNehalemBoardProduct; break; - case CPU_MODEL_WESTMERE: - case CPU_MODEL_WESTMERE_EX: + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 defaultBIOSInfo.version = kDefaultMacProWestmereBIOSVersion; defaultBIOSInfo.releaseDate = kDefaulMacProWestmereBIOSReleaseDate; //*** defaultSystemInfo.productName = kDefaultMacProWestmere; @@ -561,14 +561,14 @@ { switch (Platform.CPU.Model) { - case 0x19: // Intel Core i5 650 @3.20 Ghz - case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) - case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) - case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) - case CPU_MODEL_NEHALEM_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? - case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core - case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + case 0x19: // ??? Intel Core i5 650 @3.20 GHz + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 break; default: return; Index: branches/azimutz/Chazi/i386/libsaio/smbios_getters.c =================================================================== --- branches/azimutz/Chazi/i386/libsaio/smbios_getters.c (revision 1027) +++ branches/azimutz/Chazi/i386/libsaio/smbios_getters.c (revision 1028) @@ -40,14 +40,14 @@ { switch (Platform.CPU.Model) { - case 0x0D: // ? + case 0x0D: // ??? case CPU_MODEL_YONAH: // Yonah 0x0E case CPU_MODEL_MEROM: // Merom 0x0F case CPU_MODEL_PENRYN: // Penryn 0x17 case CPU_MODEL_ATOM: // Atom 45nm 0x1C return false; - case 0x19: // Intel Core i5 650 @3.20 Ghz + case 0x19: // ??? Intel Core i5 650 @3.20 GHz case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? @@ -127,37 +127,37 @@ { switch (Platform.CPU.Model) { - case 0x0D: // ? - case CPU_MODEL_YONAH: // Yonah - case CPU_MODEL_MEROM: // Merom - case CPU_MODEL_PENRYN: // Penryn + case 0x0D: // ??? + case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo + case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx + case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx case CPU_MODEL_ATOM: // Intel Atom (45nm) return true; - case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) if (strstr(Platform.CPU.BrandString, "Xeon(R)")) value->word = 0x0501; // Xeon else value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_FIELDS: // Lynnfield, Clarksfield, Jasper + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) value->word = 0x601; // Core i5 else value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale) + case CPU_MODEL_DALES: // Havendale, Auburndale if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) value->word = 0x601; // Core i5 else value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 sandy bridge - case CPU_MODEL_SANDY_XEON: - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) value->word = 0x901; // Core i3 else @@ -167,12 +167,12 @@ value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS) - case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 value->word = 0x0501; // Core i7 return true; - case 0x19: // Intel Core i5 650 @3.20 Ghz + case 0x19: // ??? Intel Core i5 650 @3.20 GHz value->word = 0x601; // Core i5 return true; } Index: branches/azimutz/Chazi/i386/boot2/boot.c =================================================================== --- branches/azimutz/Chazi/i386/boot2/boot.c (revision 1027) +++ branches/azimutz/Chazi/i386/boot2/boot.c (revision 1028) @@ -567,7 +567,7 @@ getBoolForKey(kKPatcherKey, &patchKernel, &bootInfo->bootConfig); //Azi: avoiding having to use -f to ignore kernel cache //Azi: ignore kernel cache but still use kext cache (E/E.mkext & S/L/E.mkext). - explain... - getBoolForKey(kIgnoreKCKey, &ignoreKC, &bootInfo->bootConfig); // equivalent to UseKernelCache + getBoolForKey(kUseKCKey, &ignoreKC, &bootInfo->bootConfig); // equivalent to UseKernelCache if (ignoreKC) { verbose("KC: cache ignored by user.\n"); Index: branches/azimutz/Chazi/i386/boot2/boot.h =================================================================== --- branches/azimutz/Chazi/i386/boot2/boot.h (revision 1027) +++ branches/azimutz/Chazi/i386/boot2/boot.h (revision 1028) @@ -101,7 +101,7 @@ #define kKernelNameKey "Kernel" // options.c getValFK - kFlag*** bFlag ? #define kKernelCacheKey "Kernel Cache" // boot.c getValFK - kFlag #define kKernelFlagsKey "Kernel Flags" // options.c getValFK - kFlags*** -#define kIgnoreKCKey "ignoreKC" // boot.c getBoolFK - testing*** +#define kUseKCKey "UseKC" // boot.c getBoolFK - testing*** #define kKPatcherKey "PatchKernel" // kernel_patcher.c getBoolFK #define kAltExtensionsKey "kext" // drivers.c getValFK Index: branches/azimutz/Chazi/i386/boot2/modules.c =================================================================== --- branches/azimutz/Chazi/i386/boot2/modules.c (revision 1027) +++ branches/azimutz/Chazi/i386/boot2/modules.c (revision 1028) @@ -17,7 +17,7 @@ #if CONFIG_MODULE_DEBUG #define DBG(x...) printf(x); -#define DBGPAUSE() getc() // getchar() +#define DBGPAUSE() getc() // getchar() - ";" needed ? #else #define DBG(x...) #define DBGPAUSE() Index: branches/azimutz/Chazi/doc/BootHelp.txt =================================================================== --- branches/azimutz/Chazi/doc/BootHelp.txt (revision 1027) +++ branches/azimutz/Chazi/doc/BootHelp.txt (revision 1028) @@ -132,6 +132,14 @@ Use an alternate/backup "Kernel" cache file. Ex: "Kernel Cache"=bt(0,0)/kernelcache_i386.A701C40B + Note: damn long keys to type at the boot prompt!? :-/ UseKC would be enough!! + Doesn't anyone use the prompt anymore? Going to keep this here just + because i hope this file ends up on the trunk, but my Chazi will use + UseKC :P - update above*** + UseKernelCache=Yes + Yes will load the system prelinked kernel or the one specified by the user + with "Kernel Cache" arg, and ignore /E/E kexts/mkext and system kext cache. + - Devices/Other:??? UseMemDetect=No Property changes on: branches/azimutz/Chazi ___________________________________________________________________ Added: svn:mergeinfo Merged /trunk:r927,932,938,941,969