Index: branches/JrCs/i386/libsaio/freq_detect.c =================================================================== --- branches/JrCs/i386/libsaio/freq_detect.c (revision 14) +++ branches/JrCs/i386/libsaio/freq_detect.c (revision 15) @@ -1,291 +0,0 @@ -/* - * Copyright 2008 Islam Ahmed Zaid. All rights reserved. - */ - -#include "libsaio.h" -#include "freq_detect.h" - -// DFE: enable_PIT2 and disable_PIT2 come from older xnu - -/* - * Enable or disable timer 2. - * Port 0x61 controls timer 2: - * bit 0 gates the clock, - * bit 1 gates output to speaker. - */ -inline static void -enable_PIT2(void) -{ - /* Enable gate, disable speaker */ - __asm__ volatile( - " inb $0x61,%%al \n\t" - " and $0xFC,%%al \n\t" /* & ~0x03 */ - " or $1,%%al \n\t" - " outb %%al,$0x61 \n\t" - : : : "%al" ); -} - -inline static void -disable_PIT2(void) -{ - /* Disable gate and output to speaker */ - __asm__ volatile( - " inb $0x61,%%al \n\t" - " and $0xFC,%%al \n\t" /* & ~0x03 */ - " outb %%al,$0x61 \n\t" - : : : "%al" ); -} - -// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are -// roughly based on Linux code - -/* Set the 8254 channel 2 to mode 0 with the specified value. - In mode 0, the counter will initially set its gate low when the - timer expires. For this to be useful, you ought to set it high - before calling this function. The enable_PIT2 function does this. - */ -static inline void set_PIT2_mode0(uint16_t value) -{ - __asm__ volatile( - " movb $0xB0,%%al \n\t" - " outb %%al,$0x43 \n\t" - " movb %%dl,%%al \n\t" - " outb %%al,$0x42 \n\t" - " movb %%dh,%%al \n\t" - " outb %%al,$0x42" - : : "d"(value) /*: no clobber */ ); -} - -/* Returns the number of times the loop ran before the PIT2 signaled */ -static inline unsigned long poll_PIT2_gate(void) -{ - unsigned long count = 0; - unsigned char nmi_sc_val; - do { - ++count; - __asm__ volatile( - "inb $0x61,%0" - : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */); - } while( (nmi_sc_val & 0x20) == 0); - return count; -} - -/* - * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer - */ -uint64_t measure_tsc_frequency(void) -{ - uint64_t tscStart; - uint64_t tscEnd; - uint64_t tscDelta = 0xffffffffffffffffULL; - unsigned long pollCount; - uint64_t retval = 0; - int i; - - /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT - * counter 2. We run this loop 3 times to make sure the cache - * is hot and we take the minimum delta from all of the runs. - * That is to say that we're biased towards measuring the minimum - * number of TSC ticks that occur while waiting for the timer to - * expire. That theoretically helps avoid inconsistencies when - * running under a VM if the TSC is not virtualized and the host - * steals time. The TSC is normally virtualized for VMware. - */ - for(i = 0; i < 3; ++i) - { - enable_PIT2(); - set_PIT2_mode0(CALIBRATE_LATCH); - tscStart = rdtsc64(); - pollCount = poll_PIT2_gate(); - tscEnd = rdtsc64(); - /* The poll loop must have run at least a few times for accuracy */ - if(pollCount <= 1) - continue; - /* The TSC must increment at LEAST once every millisecond. We - * should have waited exactly 30 msec so the TSC delta should - * be >= 30. Anything less and the processor is way too slow. - */ - if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) - continue; - // tscDelta = min(tscDelta, (tscEnd - tscStart)) - if( (tscEnd - tscStart) < tscDelta ) - tscDelta = tscEnd - tscStart; - } - /* tscDelta is now the least number of TSC ticks the processor made in - * a timespan of 0.03 s (e.g. 30 milliseconds) - * Linux thus divides by 30 which gives the answer in kiloHertz because - * 1 / ms = kHz. But we're xnu and most of the rest of the code uses - * Hz so we need to convert our milliseconds to seconds. Since we're - * dividing by the milliseconds, we simply multiply by 1000. - */ - - /* Unlike linux, we're not limited to 32-bit, but we do need to take care - * that we're going to multiply by 1000 first so we do need at least some - * arithmetic headroom. For now, 32-bit should be enough. - * Also unlike Linux, our compiler can do 64-bit integer arithmetic. - */ - if(tscDelta > (1ULL<<32)) - retval = 0; - else - { - retval = tscDelta * 1000 / 30; - } - disable_PIT2(); - return retval; -} - -uint64_t tscFrequency = 0; -uint64_t fsbFrequency = 0; -uint64_t cpuFrequency = 0; - -/* - * Calculates the FSB and CPU frequencies using specific MSRs for each CPU - * - multi. is read from a specific MSR. In the case of Intel, there is: - * a max multi. (used to calculate the FSB freq.), - * and a current multi. (used to calculate the CPU freq.) - * - fsbFrequency = tscFrequency / multi - * - cpuFrequency = fsbFrequency * multi - */ - -void calculate_freq(void) -{ - uint32_t cpuid_reg[4], cpu_vendor; - uint8_t cpu_family, cpu_model, cpu_extfamily, cpu_extmodel; - uint64_t msr, flex_ratio; - uint8_t maxcoef, maxdiv, currcoef, currdiv; - - do_cpuid(0, cpuid_reg); - cpu_vendor = cpuid_reg[1]; - - do_cpuid(1, cpuid_reg); - cpu_model = bitfield(cpuid_reg[0], 7, 4); - cpu_family = bitfield(cpuid_reg[0], 11, 8); - cpu_extmodel = bitfield(cpuid_reg[0], 19, 16); - cpu_extfamily = bitfield(cpuid_reg[0], 27, 20); - - cpu_model += (cpu_extmodel << 4); - - DBG("\nCPU Model: %d - CPU Family: %d - CPU Ext. Family: %d\n", cpu_model, cpu_family, cpu_extfamily); - DBG("The booter will now attempt to read the CPU Multiplier (using RDMSR).\n"); - DBG("Press any key to continue..\n\n"); -#if DEBUG_FREQ - getc(); -#endif - - tscFrequency = measure_tsc_frequency(); - - DBG("CPU Multiplier: "); - - if((cpu_vendor == 0x756E6547 /* Intel */) && ((cpu_family == 0x06) || (cpu_family == 0x0f))) - { - if ((cpu_family == 0x06 && cpu_model >= 0x0c) || - (cpu_family == 0x0f && cpu_model >= 0x03)) - { - /* Nehalem CPU model */ - if (cpu_family == 0x06 && (cpu_model == 0x1a || cpu_model == 0x1e)) - { - msr = rdmsr64(MSR_PLATFORM_INFO); - currcoef = (msr >> 8) & 0xff; - msr = rdmsr64(MSR_FLEX_RATIO); - if ((msr >> 16) & 0x01) - { - flex_ratio = (msr >> 8) & 0xff; - if (currcoef > flex_ratio) - currcoef = flex_ratio; - } - - if (currcoef) - { - DBG("%d\n", currcoef); - fsbFrequency = (tscFrequency / currcoef); - } - cpuFrequency = tscFrequency; - } - else - { - msr = rdmsr64(IA32_PERF_STATUS); - currcoef = (msr >> 8) & 0x1f; - /* Non-integer bus ratio for the max-multi*/ - maxdiv = (msr >> 46) & 0x01; - /* Non-integer bus ratio for the current-multi (undocumented)*/ - currdiv = (msr >> 14) & 0x01; - - if ((cpu_family == 0x06 && cpu_model >= 0x0e) || - (cpu_family == 0x0f)) // This will always be model >= 3 - { - /* On these models, maxcoef defines TSC freq */ - maxcoef = (msr >> 40) & 0x1f; - } - else - { - /* On lower models, currcoef defines TSC freq */ - /* XXX */ - maxcoef = currcoef; - } - - if (maxcoef) - { - if (maxdiv) - fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1)); - else - fsbFrequency = (tscFrequency / maxcoef); - - if (currdiv) - cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2); - else - cpuFrequency = (fsbFrequency * currcoef); - DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : ""); - } - } - } - } - else if((cpu_vendor == 0x68747541 /* AMD */) && (cpu_family == 0x0f)) - { - if(cpu_extfamily == 0x00 /* K8 */) - { - msr = rdmsr64(K8_FIDVID_STATUS); - currcoef = (msr & 0x3f) / 2 + 4; - currdiv = (msr & 0x01) * 2; - } - else if(cpu_extfamily >= 0x01 /* K10+ */) - { - msr = rdmsr64(K10_COFVID_STATUS); - if(cpu_extfamily == 0x01 /* K10 */) - currcoef = (msr & 0x3f) + 0x10; - else /* K11+ */ - currcoef = (msr & 0x3f) + 0x08; - currdiv = (2 << ((msr >> 6) & 0x07)); - } - - if (currcoef) - { - if (currdiv) - { - fsbFrequency = ((tscFrequency * currdiv) / currcoef); - DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv); - } - else - { - fsbFrequency = (tscFrequency / currcoef); - DBG("%d\n", currcoef); - } - fsbFrequency = (tscFrequency / currcoef); - cpuFrequency = tscFrequency; - } - } - - if (!fsbFrequency) - { - fsbFrequency = (DEFAULT_FSB * 1000); - cpuFrequency = tscFrequency; - DBG("0 ! using the default value for FSB !\n"); - } - - DBG("TSC Frequency: %dMHz\n", tscFrequency / 1000000); - DBG("CPU Frequency: %dMHz\n", cpuFrequency / 1000000); - DBG("FSB Frequency: %dMHz\n", fsbFrequency / 1000000); - DBG("Press [Enter] to continue..\n"); -#if DEBUG_FREQ - while (getc() != 0x0d) ; -#endif -} Index: branches/JrCs/i386/libsaio/freq_detect.h =================================================================== --- branches/JrCs/i386/libsaio/freq_detect.h (revision 14) +++ branches/JrCs/i386/libsaio/freq_detect.h (revision 15) @@ -1,77 +0,0 @@ -/* - * Copyright 2008 Islam Ahmed Zaid. All rights reserved. - */ - -#ifndef __LIBSAIO_FREQ_DETECT_H -#define __LIBSAIO_FREQ_DETECT_H - -#include "libsaio.h" -#ifndef DEBUG_FREQ -#define DEBUG_FREQ 0 -#endif - -#if DEBUG_FREQ -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif - -/* Decimal powers: */ -#define kilo (1000ULL) -#define Mega (kilo * kilo) -#define Giga (kilo * Mega) -#define Tera (kilo * Giga) -#define Peta (kilo * Tera) - -#define bit(n) (1ULL << (n)) -#define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1)) -#define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l) - -#define IA32_PERF_STATUS 0x198 -#define MSR_FLEX_RATIO 0x194 -#define MSR_PLATFORM_INFO 0xCE -#define K8_FIDVID_STATUS 0xC0010042 -#define K10_COFVID_STATUS 0xC0010071 - -#define DEFAULT_FSB 100000 /* for now, hardcoding 100MHz for old CPUs */ - -// DFE: This constant comes from older xnu: -#define CLKNUM 1193182 /* formerly 1193167 */ - -// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM -#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ -#define CALIBRATE_LATCH \ - ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) - -extern uint64_t tscFrequency; -extern uint64_t fsbFrequency; -extern uint64_t cpuFrequency; - -void calculate_freq(void); - -static inline uint64_t rdtsc64(void) -{ - uint64_t ret; - __asm__ volatile("rdtsc" : "=A" (ret)); - return ret; -} - -static inline uint64_t rdmsr64(uint32_t msr) -{ - uint64_t ret; - __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr)); - return ret; -} - -static inline void do_cpuid(uint32_t selector, uint32_t *data) -{ - asm volatile ("cpuid" - : "=a" (data[0]), - "=b" (data[1]), - "=c" (data[2]), - "=d" (data[3]) - : "a" (selector) - ); -} - -#endif /* !__LIBSAIO_FREQ_DETECT_H */ Index: branches/JrCs/i386/libsaio/spd.c =================================================================== --- branches/JrCs/i386/libsaio/spd.c (revision 14) +++ branches/JrCs/i386/libsaio/spd.c (revision 15) @@ -18,6 +18,12 @@ #define DBG(x...) #endif +void scan_spd(PlatformInfo_t *p) +{ + /* NYI */ +} + +#if 0 // Old structures and functions static const char *spd_memory_types[] = { "RAM", /* 00h Undefined */ @@ -34,8 +40,8 @@ "DDR3 SDRAM", /* 0Bh SDRAM DDR 3 */ }; -#define rdtsc(low,high) \ -__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) +#define rdtsc(low,high) \ + __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) #define SMBHSTSTS 0 #define SMBHSTCNT 2 @@ -163,4 +169,4 @@ } } - +#endif Index: branches/JrCs/i386/libsaio/spd.h =================================================================== --- branches/JrCs/i386/libsaio/spd.h (revision 14) +++ branches/JrCs/i386/libsaio/spd.h (revision 15) @@ -6,6 +6,12 @@ #ifndef __LIBSAIO_SPD_H #define __LIBSAIO_SPD_H +#include "platform.h" + +extern void scan_spd(PlatformInfo_t *p); + +#if 0 // Old structures and functions + #include "libsaio.h" void scan_smbus_controller(pci_dt_t *smbus_dev); @@ -153,4 +159,6 @@ #define MODULE_BUFFERED 1 #define MODULE_REGISTERED 2 +#endif + #endif /* !__LIBSAIO_SPD_H */ Index: branches/JrCs/i386/libsaio/Makefile =================================================================== --- branches/JrCs/i386/libsaio/Makefile (revision 14) +++ branches/JrCs/i386/libsaio/Makefile (revision 15) @@ -4,6 +4,7 @@ UTILDIR = ../util LIBSADIR = ../libsa +BOOT2DIR = ../boot2 INSTALLDIR = $(DSTROOT)/System/Library/Frameworks/System.framework/Versions/B/PrivateHeaders/standalone #SYMROOT= @@ -18,7 +19,7 @@ DEFINES= CONFIG = hd -INC = -I. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) +INC = -I. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(BOOT2DIR) ifneq "" "$(wildcard /bin/mkdirs)" MKDIRS = /bin/mkdirs else @@ -37,10 +38,10 @@ ufs.o ufs_byteorder.o \ vbe.o nbp.o hfs.o hfs_compare.o \ xml.o ntfs.o msdos.o md5c.o device_tree.o \ - freq_detect.o platform.o dsdt_patcher.o \ + cpu.o platform.o dsdt_patcher.o \ smbios_patcher.o fake_efi.o ext2fs.o \ hpet.o spd.o usb.o pci_setup.o \ - device_inject.o nvidia.o ati.o + device_inject.o nvidia.o ati.o mem.o SAIO_EXTERN_OBJS = console.o Index: branches/JrCs/i386/libsaio/smbios_patcher.c =================================================================== --- branches/JrCs/i386/libsaio/smbios_patcher.c (revision 14) +++ branches/JrCs/i386/libsaio/smbios_patcher.c (revision 15) @@ -3,6 +3,7 @@ */ #include "libsaio.h" +#include "boot.h" #include "acpi.h" #include "bootstruct.h" #include "efi_tables.h" @@ -102,20 +103,20 @@ int i; char (*sm_defaults)[2][40]; - if (Platform.CPU.Mobile) - if (Platform.CPU.NoCores > 1) - { + if (platformCPUFeature(CPU_FEATURE_MOBILE)) { + if (Platform.CPU.NoCores > 1) { sm_defaults=sm_macbookpro_defaults; } else { sm_defaults=sm_macbook_defaults; } - else + } else { switch (Platform.CPU.NoCores) { case 1: sm_defaults=sm_macmini_defaults; break; case 2: sm_defaults=sm_imac_defaults; break; default: sm_defaults=sm_macpro_defaults; break; } + } for (i=0;sm_defaults[i][0][0];i++) if (!strcmp (sm_defaults[i][0],name)) @@ -156,32 +157,56 @@ static int sm_get_memtype (char *name, int table_num) { - if(Platform.RAM.Type) - return Platform.RAM.Type; - else + if (table_num < MAX_RAM_SLOTS && + Platform.RAM.DIMM[table_num].InUse && + Platform.RAM.DIMM[table_num].Type != 0) + { + return Platform.RAM.DIMM[table_num].Type; + } return SMB_MEM_TYPE_DDR2; } static int sm_get_memspeed (char *name, int table_num) { - if(Platform.RAM.Type) - return round2( Platform.RAM.Frequency / 500000, 2); - else + if (Platform.RAM.Frequency != 0) { + return Platform.RAM.Frequency/1000000; + } return 667; } static char *sm_get_memvendor (char *name, int table_num) { + if (table_num < MAX_RAM_SLOTS && + Platform.RAM.DIMM[table_num].InUse && + strlen(Platform.RAM.DIMM[table_num].Vendor) > 0) + { + DBG("Vendor[%d]='%s'\n", table_num, Platform.RAM.DIMM[table_num].Vendor); + return Platform.RAM.DIMM[table_num].Vendor; + } return "N/A"; } static char *sm_get_memserial (char *name, int table_num) { + if (table_num < MAX_RAM_SLOTS && + Platform.RAM.DIMM[table_num].InUse && + strlen(Platform.RAM.DIMM[table_num].SerialNo) > 0) + { + DBG("SerialNo[%d]='%s'\n", table_num, Platform.RAM.DIMM[table_num].SerialNo); + return Platform.RAM.DIMM[table_num].SerialNo; + } return "N/A"; } static char *sm_get_mempartno (char *name, int table_num) { + if (table_num < MAX_RAM_SLOTS && + Platform.RAM.DIMM[table_num].InUse && + strlen(Platform.RAM.DIMM[table_num].PartNo) > 0) + { + DBG("PartNo[%d]='%s'\n", table_num, Platform.RAM.DIMM[table_num].PartNo); + return Platform.RAM.DIMM[table_num].PartNo; + } return "N/A"; } @@ -227,7 +252,7 @@ {.type=132, .len=0x06, .numfunc=sm_one} }; -static inline struct SMBEntryPoint * getAddressOfSmbiosTable() +struct SMBEntryPoint * getAddressOfSmbiosTable() { /* First see if we can even find the damn SMBIOS table * The logic here is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking @@ -283,7 +308,11 @@ { smbiostables=(char *)origsmbios->dmi.tableAddress; origsmbiosnum=origsmbios->dmi.structureCount; + } else { + smbiostables = NULL; + origsmbiosnum = 0; } + // _SM_ ret->anchor[0]=0x5f; ret->anchor[1]=0x53; @@ -422,15 +451,17 @@ { smbiostables=(char *) origsmbios->dmi.tableAddress; origsmbiosnum=origsmbios->dmi.structureCount; + } else { + smbiostables = NULL; + origsmbiosnum = 0; } tablesptr=smbiostables; newtablesptr=(char *) newsmbios->dmi.tableAddress; if (smbiostables) for (i=0;i + * Released under version 2 of the Gnu Public License (GPLv2). + * + * mem.c - obtain system memory information + */ + +#include "libsaio.h" +#include "pci.h" +#include "platform.h" +#include "cpu.h" +#include "mem.h" + +#ifndef DEBUG_MEM +#define DEBUG_MEM 0 +#endif + +#if DEBUG_MEM +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +void scan_memory(PlatformInfo_t *p) +{ + /* NYI */ +} Index: branches/JrCs/i386/libsaio/mem.h =================================================================== --- branches/JrCs/i386/libsaio/mem.h (revision 0) +++ branches/JrCs/i386/libsaio/mem.h (revision 15) @@ -0,0 +1,16 @@ +/* + * Copyright 2010 AsereBLN. All rights reserved. + * Released under version 2 of the Gnu Public License (GPLv2). + * + * mem.h + */ + +#ifndef __LIBSAIO_MEM_H +#define __LIBSAIO_MEM_H + +#include "platform.h" + +extern void scan_memory(PlatformInfo_t *); + + +#endif /* __LIBSAIO_MEM_H */ Index: branches/JrCs/i386/libsaio/dsdt_patcher.c =================================================================== --- branches/JrCs/i386/libsaio/dsdt_patcher.c (revision 14) +++ branches/JrCs/i386/libsaio/dsdt_patcher.c (revision 15) @@ -3,6 +3,7 @@ */ #include "libsaio.h" +#include "boot.h" #include "bootstruct.h" #include "acpi.h" #include "efi_tables.h" @@ -240,12 +241,12 @@ // Correct the checksum of RSDT rsdt_mod->Length-=4*dropoffset; - DBG("RSDT Original checksum %d\n", rsdt_mod->Checksum); + DBG("RSDT: Original checksum %d, ", rsdt_mod->Checksum); rsdt_mod->Checksum=0; rsdt_mod->Checksum=256-checksum8(rsdt_mod,rsdt_mod->Length); - DBG("RSDT New checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod); + DBG("New checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod); } else { @@ -356,7 +357,7 @@ // Correct the checksum of RSDP - DBG("Original checksum %d\n", rsdp_mod->Checksum); + DBG("RSDP: Original checksum %d, ", rsdp_mod->Checksum); rsdp_mod->Checksum=0; rsdp_mod->Checksum=256-checksum8(rsdp_mod,20); @@ -365,7 +366,7 @@ if (version) { - DBG("Original extended checksum %d\n", rsdp_mod->ExtendedChecksum); + DBG("RSDP: Original extended checksum %d", rsdp_mod->ExtendedChecksum); rsdp_mod->ExtendedChecksum=0; rsdp_mod->ExtendedChecksum=256-checksum8(rsdp_mod,rsdp_mod->Length); @@ -387,6 +388,7 @@ } } #if DEBUG_DSDT + printf("Press a key to continue... (DEBUG_DSDT)\n"); getc(); #endif return 1; Index: branches/JrCs/i386/libsaio/platform.c =================================================================== --- branches/JrCs/i386/libsaio/platform.c (revision 14) +++ branches/JrCs/i386/libsaio/platform.c (revision 15) @@ -6,10 +6,10 @@ #include "libsaio.h" #include "bootstruct.h" #include "pci.h" -#include "freq_detect.h" -#include "nvidia.h" -#include "spd.h" #include "platform.h" +#include "cpu.h" +#include "mem.h" +#include "spd.h" #ifndef DEBUG_PLATFORM #define DEBUG_PLATFORM 0 @@ -23,71 +23,20 @@ PlatformInfo_t Platform; -void scan_cpu_amd() +bool platformCPUFeature(uint32_t feature) { - // AMD - - // TODO: Retrieve cpu brand string - // TODO: Retrieve cpu core count - // TODO: Retrieve cpu mobile info - + if (Platform.CPU.Features & feature) { + return true; + } else { + return false; + } } -void scan_cpu_intel() +void scan_platform(void) { - uint32_t cpuid_reg[4]; - - // Get Number of cores per package - /* - Initially set the EAX register to 4 and the ECX register to 0 prior to executing the CPUID instruction. - After executing the CPUID instruction, (EAX[31:26] + 1) contains the number of cores. - */ - cpuid_reg[2]=1; - do_cpuid(4, cpuid_reg); - do_cpuid(4, cpuid_reg); // FIXME: why does this only work the 2nd time ? - Platform.CPU.NoCores = bitfield(cpuid_reg[0], 31, 26) + 1; - - // Find Number of Concurrent Threads Processed (HyperThreading) - do_cpuid(1,cpuid_reg); - if(bitfield(cpuid_reg[1], 23, 16) > 1) - Platform.CPU.NoThreads=Platform.CPU.NoCores; - else - Platform.CPU.NoThreads=Platform.CPU.NoCores * 2; - - // Mobile CPU ? - if (rdmsr64(0x17) & (1<<28)) - Platform.CPU.Mobile = 1; - else - Platform.CPU.Mobile = 0; -} - -void scan_platform() -{ - uint32_t cpuid_reg[4]; - + memset(&Platform, 0, sizeof(Platform)); build_pci_dt(); - - calculate_freq(); - - // Copy the values from calculate_freq() - Platform.CPU.TSCFrequency = tscFrequency; - Platform.CPU.FSBFrequency = fsbFrequency; - Platform.CPU.CPUFrequency = cpuFrequency; - - do_cpuid(0, cpuid_reg); - Platform.CPU.Vendor = cpuid_reg[1]; - - do_cpuid(1, cpuid_reg); - Platform.CPU.Model = bitfield(cpuid_reg[0], 7, 4); - Platform.CPU.Family = bitfield(cpuid_reg[0], 11, 8); - Platform.CPU.ExtModel = bitfield(cpuid_reg[0], 19, 16); - Platform.CPU.ExtFamily = bitfield(cpuid_reg[0], 27, 20); - - // Get vendor specific cpu data - if((Platform.CPU.Vendor == 0x756E6547 /* Intel */) && ((Platform.CPU.Family == 0x06) || (Platform.CPU.Family == 0x0f))) - scan_cpu_intel(); - else if((Platform.CPU.Vendor == 0x68747541 /* AMD */) && (Platform.CPU.Family == 0x0f)) - scan_cpu_amd(); + scan_cpu(&Platform); + scan_memory(&Platform); + scan_spd(&Platform); } - - Index: branches/JrCs/i386/libsaio/cpu.c =================================================================== --- branches/JrCs/i386/libsaio/cpu.c (revision 0) +++ branches/JrCs/i386/libsaio/cpu.c (revision 15) @@ -0,0 +1,375 @@ +/* + * Copyright 2008 Islam Ahmed Zaid. All rights reserved. + * AsereBLN: 2009: cleanup and bugfix + */ + +#include "libsaio.h" +#include "platform.h" +#include "cpu.h" + +#ifndef DEBUG_CPU +#define DEBUG_CPU 0 +#endif + +#if DEBUG_CPU +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + + +static inline uint64_t rdtsc64(void) +{ + uint64_t ret; + __asm__ volatile("rdtsc" : "=A" (ret)); + return ret; +} + +static inline uint64_t rdmsr64(uint32_t msr) +{ + uint64_t ret; + __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr)); + return ret; +} + +static inline void do_cpuid(uint32_t selector, uint32_t *data) +{ + asm volatile ("cpuid" + : "=a" (data[0]), + "=b" (data[1]), + "=c" (data[2]), + "=d" (data[3]) + : "a" (selector)); +} + +static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data) +{ + asm volatile ("cpuid" + : "=a" (data[0]), + "=b" (data[1]), + "=c" (data[2]), + "=d" (data[3]) + : "a" (selector), "c" (selector2)); +} + +// DFE: enable_PIT2 and disable_PIT2 come from older xnu + +/* + * Enable or disable timer 2. + * Port 0x61 controls timer 2: + * bit 0 gates the clock, + * bit 1 gates output to speaker. + */ +static inline void enable_PIT2(void) +{ + /* Enable gate, disable speaker */ + __asm__ volatile( + " inb $0x61,%%al \n\t" + " and $0xFC,%%al \n\t" /* & ~0x03 */ + " or $1,%%al \n\t" + " outb %%al,$0x61 \n\t" + : : : "%al" ); +} + +static inline void disable_PIT2(void) +{ + /* Disable gate and output to speaker */ + __asm__ volatile( + " inb $0x61,%%al \n\t" + " and $0xFC,%%al \n\t" /* & ~0x03 */ + " outb %%al,$0x61 \n\t" + : : : "%al" ); +} + +// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are +// roughly based on Linux code + +/* Set the 8254 channel 2 to mode 0 with the specified value. + In mode 0, the counter will initially set its gate low when the + timer expires. For this to be useful, you ought to set it high + before calling this function. The enable_PIT2 function does this. + */ +static inline void set_PIT2_mode0(uint16_t value) +{ + __asm__ volatile( + " movb $0xB0,%%al \n\t" + " outb %%al,$0x43 \n\t" + " movb %%dl,%%al \n\t" + " outb %%al,$0x42 \n\t" + " movb %%dh,%%al \n\t" + " outb %%al,$0x42" + : : "d"(value) /*: no clobber */ ); +} + +/* Returns the number of times the loop ran before the PIT2 signaled */ +static inline unsigned long poll_PIT2_gate(void) +{ + unsigned long count = 0; + unsigned char nmi_sc_val; + do { + ++count; + __asm__ volatile( + "inb $0x61,%0" + : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */); + } while( (nmi_sc_val & 0x20) == 0); + return count; +} + +/* + * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer + */ +static uint64_t measure_tsc_frequency(void) +{ + uint64_t tscStart; + uint64_t tscEnd; + uint64_t tscDelta = 0xffffffffffffffffULL; + unsigned long pollCount; + uint64_t retval = 0; + int i; + + /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT + * counter 2. We run this loop 3 times to make sure the cache + * is hot and we take the minimum delta from all of the runs. + * That is to say that we're biased towards measuring the minimum + * number of TSC ticks that occur while waiting for the timer to + * expire. That theoretically helps avoid inconsistencies when + * running under a VM if the TSC is not virtualized and the host + * steals time. The TSC is normally virtualized for VMware. + */ + for(i = 0; i < 10; ++i) + { + enable_PIT2(); + set_PIT2_mode0(CALIBRATE_LATCH); + tscStart = rdtsc64(); + pollCount = poll_PIT2_gate(); + tscEnd = rdtsc64(); + /* The poll loop must have run at least a few times for accuracy */ + if(pollCount <= 1) + continue; + /* The TSC must increment at LEAST once every millisecond. We + * should have waited exactly 30 msec so the TSC delta should + * be >= 30. Anything less and the processor is way too slow. + */ + if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) + continue; + // tscDelta = min(tscDelta, (tscEnd - tscStart)) + if( (tscEnd - tscStart) < tscDelta ) + tscDelta = tscEnd - tscStart; + } + /* tscDelta is now the least number of TSC ticks the processor made in + * a timespan of 0.03 s (e.g. 30 milliseconds) + * Linux thus divides by 30 which gives the answer in kiloHertz because + * 1 / ms = kHz. But we're xnu and most of the rest of the code uses + * Hz so we need to convert our milliseconds to seconds. Since we're + * dividing by the milliseconds, we simply multiply by 1000. + */ + + /* Unlike linux, we're not limited to 32-bit, but we do need to take care + * that we're going to multiply by 1000 first so we do need at least some + * arithmetic headroom. For now, 32-bit should be enough. + * Also unlike Linux, our compiler can do 64-bit integer arithmetic. + */ + if(tscDelta > (1ULL<<32)) + retval = 0; + else + { + retval = tscDelta * 1000 / 30; + } + disable_PIT2(); + return retval; +} + +/* + * Calculates the FSB and CPU frequencies using specific MSRs for each CPU + * - multi. is read from a specific MSR. In the case of Intel, there is: + * a max multi. (used to calculate the FSB freq.), + * and a current multi. (used to calculate the CPU freq.) + * - fsbFrequency = tscFrequency / multi + * - cpuFrequency = fsbFrequency * multi + */ + +void scan_cpu(PlatformInfo_t *p) +{ + uint64_t tscFrequency, fsbFrequency, cpuFrequency; + uint64_t msr, flex_ratio; + uint8_t maxcoef, maxdiv, currcoef, currdiv; + + maxcoef = maxdiv = currcoef = currdiv = 0; + + /* get cpuid values */ + do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); + do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); + do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); + do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); + do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); + do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); + if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) { + do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]); + } +#if DEBUG_CPU + { + int i; + printf("CPUID Raw Values:\n"); + for (i=0; iCPU.CPUID[i][0], p->CPU.CPUID[i][1], + p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]); + } + } +#endif + p->CPU.Vendor = p->CPU.CPUID[CPUID_0][1]; + p->CPU.Model = bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); + p->CPU.Family = bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); + p->CPU.ExtModel = bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); + p->CPU.ExtFamily = bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20); + p->CPU.NoThreads = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16); + p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1; + + p->CPU.Model += (p->CPU.ExtModel << 4); + + /* setup features */ + if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_MMX; + } + if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE; + } + if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE2; + } + if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE3; + } + if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE41; + } + if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE42; + } + if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_EM64T; + } + //if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) { + if (p->CPU.NoThreads > p->CPU.NoCores) { + p->CPU.Features |= CPU_FEATURE_HTT; + } + + tscFrequency = measure_tsc_frequency(); + fsbFrequency = 0; + cpuFrequency = 0; + + if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) { + if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) { + /* Nehalem CPU model */ + if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e)) { + msr = rdmsr64(MSR_PLATFORM_INFO); + DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff); + currcoef = (msr >> 8) & 0xff; + msr = rdmsr64(MSR_FLEX_RATIO); + DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff); + if ((msr >> 16) & 0x01) { + flex_ratio = (msr >> 8) & 0xff; + if (currcoef > flex_ratio) { + currcoef = flex_ratio; + } + } + + if (currcoef) { + fsbFrequency = (tscFrequency / currcoef); + } + cpuFrequency = tscFrequency; + } else { + msr = rdmsr64(IA32_PERF_STATUS); + DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff); + currcoef = (msr >> 8) & 0x1f; + /* Non-integer bus ratio for the max-multi*/ + maxdiv = (msr >> 46) & 0x01; + /* Non-integer bus ratio for the current-multi (undocumented)*/ + currdiv = (msr >> 14) & 0x01; + + if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3 + { + /* On these models, maxcoef defines TSC freq */ + maxcoef = (msr >> 40) & 0x1f; + } else { + /* On lower models, currcoef defines TSC freq */ + /* XXX */ + maxcoef = currcoef; + } + + if (maxcoef) { + if (maxdiv) { + fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1)); + } else { + fsbFrequency = (tscFrequency / maxcoef); + } + if (currdiv) { + cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2); + } else { + cpuFrequency = (fsbFrequency * currcoef); + } + DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : ""); + } + } + } + /* Mobile CPU ? */ + if (rdmsr64(0x17) & (1<<28)) { + p->CPU.Features |= CPU_FEATURE_MOBILE; + } + } +#if 0 + else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) { + if(p->CPU.ExtFamily == 0x00 /* K8 */) { + msr = rdmsr64(K8_FIDVID_STATUS); + currcoef = (msr & 0x3f) / 2 + 4; + currdiv = (msr & 0x01) * 2; + } else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) { + msr = rdmsr64(K10_COFVID_STATUS); + if(p->CPU.ExtFamily == 0x01 /* K10 */) + currcoef = (msr & 0x3f) + 0x10; + else /* K11+ */ + currcoef = (msr & 0x3f) + 0x08; + currdiv = (2 << ((msr >> 6) & 0x07)); + } + + if (currcoef) { + if (currdiv) { + fsbFrequency = ((tscFrequency * currdiv) / currcoef); + DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv); + } else { + fsbFrequency = (tscFrequency / currcoef); + DBG("%d\n", currcoef); + } + fsbFrequency = (tscFrequency / currcoef); + cpuFrequency = tscFrequency; + } + } + + if (!fsbFrequency) { + fsbFrequency = (DEFAULT_FSB * 1000); + cpuFrequency = tscFrequency; + DBG("0 ! using the default value for FSB !\n"); + } +#endif + + p->CPU.MaxCoef = maxcoef; + p->CPU.MaxDiv = maxdiv; + p->CPU.CurrCoef = currcoef; + p->CPU.CurrDiv = currdiv; + p->CPU.TSCFrequency = tscFrequency; + p->CPU.FSBFrequency = fsbFrequency; + p->CPU.CPUFrequency = cpuFrequency; +#if DEBUG_CPU + DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel); + DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily); + DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef); + DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv); + DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000); + DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000); + DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000); + DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads); + DBG("CPU: Features: 0x%08x\n", p->CPU.Features); + printf("Press a key to continue... (DEBUG_CPU)\n"); + getc(); +#endif +} Index: branches/JrCs/i386/libsaio/platform.h =================================================================== --- branches/JrCs/i386/libsaio/platform.h (revision 14) +++ branches/JrCs/i386/libsaio/platform.h (revision 15) @@ -8,12 +8,30 @@ #include "libsaio.h" -#define bit(n) (1ULL << (n)) -#define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1)) -#define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l) +extern bool platformCPUFeature(uint32_t); +extern void scan_platform(void); -extern void scan_platform(); +/* CPUID index into cpuid_raw */ +#define CPUID_0 0 +#define CPUID_1 1 +#define CPUID_2 2 +#define CPUID_3 3 +#define CPUID_4 4 +#define CPUID_80 5 +#define CPUID_81 6 +#define CPUID_MAX 7 +/* CPU Features */ +#define CPU_FEATURE_MMX 0x00000001 // MMX Instruction Set +#define CPU_FEATURE_SSE 0x00000002 // SSE Instruction Set +#define CPU_FEATURE_SSE2 0x00000004 // SSE2 Instruction Set +#define CPU_FEATURE_SSE3 0x00000008 // SSE3 Instruction Set +#define CPU_FEATURE_SSE41 0x00000010 // SSE41 Instruction Set +#define CPU_FEATURE_SSE42 0x00000020 // SSE42 Instruction Set +#define CPU_FEATURE_EM64T 0x00000040 // 64Bit Support +#define CPU_FEATURE_HTT 0x00000080 // HyperThreading +#define CPU_FEATURE_MOBILE 0x00000100 // Mobile CPU + /* SMBIOS Memory Types */ #define SMB_MEM_TYPE_UNDEFINED 0 #define SMB_MEM_TYPE_OTHER 1 @@ -45,52 +63,45 @@ #define SMB_MEM_CHANNEL_TRIPLE 3 /* Maximum number of ram slots */ -#define MAX_RAM_SLOTS 16 +#define MAX_RAM_SLOTS 8 +/* Maximum number of SPD bytes */ +#define MAX_SPD_SIZE 256 + typedef struct _RamSlotInfo_t { - bool InUse; // Module Present - uint32_t ModuleSize; // Size of Module in MB - char *spd; // SPD Dump + bool InUse; + uint32_t ModuleSize; // Size of Module in MB + uint8_t Type; + char Vendor[64]; + char PartNo[64]; + char SerialNo[16]; + uint8_t spd[MAX_SPD_SIZE]; } RamSlotInfo_t; typedef struct _PlatformInfo_t { - bool Mobile; // Mobile Platform - bool x86_64; // 64 Bit Capable - struct PCI { - uint8_t NoDevices; // No of PCI devices - } PCI; struct CPU { - uint32_t Vendor; // Vendor - uint32_t Model; // Model - uint32_t ExtModel; // Extended Model - uint32_t Family; // Family - uint32_t ExtFamily; // Extended Family - uint8_t NoCores; // No Cores per Package - uint8_t NoThreads; // Threads per Package - uint8_t MaxCoef; // Max Multiplier + uint32_t Features; // CPU Features like MMX, SSE2, VT, MobileCPU + uint32_t Vendor; // Vendor + uint32_t Model; // Model + uint32_t ExtModel; // Extended Model + uint32_t Family; // Family + uint32_t ExtFamily; // Extended Family + uint32_t NoCores; // No Cores per Package + uint32_t NoThreads; // Threads per Package + uint8_t MaxCoef; // Max Multiplier uint8_t MaxDiv; uint8_t CurrCoef; // Current Multiplier uint8_t CurrDiv; - float MaxRatio; - float CurrRatio; - uint64_t TSCFrequency; // TSC Frequency Hz - uint64_t FSBFrequency; // FSB Frequency Hz - uint64_t CPUFrequency; // CPU Frequency Hz - bool Mobile; // Mobile CPU - uint32_t BrandString[16]; // 48 Byte Branding String + uint64_t TSCFrequency; // TSC Frequency Hz + uint64_t FSBFrequency; // FSB Frequency Hz + uint64_t CPUFrequency; // CPU Frequency Hz + uint32_t BrandString[16]; // 48 Byte Branding String + uint32_t CPUID[CPUID_MAX][4]; // CPUID 0..4, 80..81 Raw Values } CPU; struct RAM { - uint64_t Frequency; // Ram Frequency - uint32_t Divider; // Memory divider - float CAS; // CAS 1/2/2.5/3/4/5/6/7 - uint8_t TRC; - uint8_t TRP; - uint8_t RAS; - uint8_t Channels; // Channel Configuration Single,Dual or Triple - uint8_t NoSlots; // Maximum no of slots available - uint8_t Type; // Standard SMBIOS v2.5 Memory Type - char *BrandString; // Branding String Memory Controller - RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot + RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot + uint64_t Frequency; // Ram Frequency + //uint8_t Type; // Standard SMBIOS v2.5 Memory Type } RAM; } PlatformInfo_t; Index: branches/JrCs/i386/libsaio/cpu.h =================================================================== --- branches/JrCs/i386/libsaio/cpu.h (revision 0) +++ branches/JrCs/i386/libsaio/cpu.h (revision 15) @@ -0,0 +1,32 @@ +/* + * Copyright 2008 Islam Ahmed Zaid. All rights reserved. + * AsereBLN: 2009: cleanup and bugfix + */ + +#ifndef __LIBSAIO_CPU_H +#define __LIBSAIO_CPU_H + +#include "libsaio.h" + +extern void scan_cpu(PlatformInfo_t *); + +#define bit(n) (1UL << (n)) +#define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1)) +#define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l) + +#define IA32_PERF_STATUS 0x198 +#define MSR_FLEX_RATIO 0x194 +#define MSR_PLATFORM_INFO 0xCE +#define K8_FIDVID_STATUS 0xC0010042 +#define K10_COFVID_STATUS 0xC0010071 + +#define DEFAULT_FSB 100000 /* for now, hardcoding 100MHz for old CPUs */ + +// DFE: This constant comes from older xnu: +#define CLKNUM 1193182 /* formerly 1193167 */ + +// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM +#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ +#define CALIBRATE_LATCH ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) + +#endif /* !__LIBSAIO_CPU_H */ Index: branches/JrCs/i386/libsaio/fake_efi.c =================================================================== --- branches/JrCs/i386/libsaio/fake_efi.c (revision 14) +++ branches/JrCs/i386/libsaio/fake_efi.c (revision 15) @@ -3,19 +3,19 @@ */ #include "libsaio.h" +#include "boot.h" #include "bootstruct.h" /* for bootArgs */ #include "efi.h" #include "acpi.h" #include "fake_efi.h" #include "efi_tables.h" -#include "freq_detect.h" +#include "platform.h" #include "dsdt_patcher.h" #include "smbios_patcher.h" #include "device_inject.h" #include "pci.h" #include "sl.h" -extern struct SMBEntryPoint * getSmbios(); extern void setup_pci_devs(pci_dt_t *pci_dt); /* @@ -320,7 +320,6 @@ static char FIRMWARE_ABI_PROP[] = "firmware-abi"; static char FIRMWARE_VENDOR_PROP[] = "firmware-vendor"; static char FIRMWARE_ABI_PROP_VALUE[] = "EFI64"; -static char SYSTEM_ID_PROP[] = "system-id"; void setupEfiDeviceTree(void) @@ -366,18 +365,15 @@ * the value in the fsbFrequency global and not an malloc'd pointer * because the DT_AddProperty function does not copy its args. */ - if(fsbFrequency != 0) - DT__AddProperty(efiPlatformNode, FSB_Frequency_prop, sizeof(uint64_t), &fsbFrequency); + if(Platform.CPU.FSBFrequency != 0) + DT__AddProperty(efiPlatformNode, FSB_Frequency_prop, sizeof(uint64_t), &Platform.CPU.FSBFrequency); - // unable to determine UUID for host. Error: 35 fix - DT__AddProperty(efiPlatformNode, SYSTEM_ID_PROP, sizeof(SYSTEM_ID), (EFI_UINT32*)&SYSTEM_ID); - /* Export TSC and CPU frequencies for use by the kernel or KEXTs */ - if(tscFrequency != 0) - DT__AddProperty(efiPlatformNode, TSC_Frequency_prop, sizeof(uint64_t), &tscFrequency); - if(cpuFrequency != 0) - DT__AddProperty(efiPlatformNode, CPU_Frequency_prop, sizeof(uint64_t), &cpuFrequency); + if(Platform.CPU.TSCFrequency != 0) + DT__AddProperty(efiPlatformNode, TSC_Frequency_prop, sizeof(uint64_t), &Platform.CPU.TSCFrequency); + if(Platform.CPU.CPUFrequency != 0) + DT__AddProperty(efiPlatformNode, CPU_Frequency_prop, sizeof(uint64_t), &Platform.CPU.CPUFrequency); /* Fill /efi/device-properties node. */