Index: branches/ErmaC/i386/libsaio/gma.c =================================================================== --- branches/ErmaC/i386/libsaio/gma.c (revision 1567) +++ branches/ErmaC/i386/libsaio/gma.c (revision 1568) @@ -1,300 +0,0 @@ -/* - Original patch by Nawcom - http://forum.voodooprojects.org/index.php/topic,1029.0.html -*/ - -#include "libsa.h" -#include "saio_internal.h" -#include "bootstruct.h" -#include "pci.h" -#include "platform.h" -#include "device_inject.h" -#include "gma.h" - -#ifndef DEBUG_GMA -#define DEBUG_GMA 0 -#endif - -#if DEBUG_GMA -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif - - -uint8_t GMAX3100_vals[22][4] = { - { 0x01,0x00,0x00,0x00 }, - { 0x01,0x00,0x00,0x00 }, - { 0x01,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x08 }, - { 0x64,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x08 }, - { 0x01,0x00,0x00,0x00 }, - { 0x20,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x01,0x00,0x00,0x00 }, - { 0x20,0x03,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x08,0x52,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x01,0x00,0x00,0x00 }, - { 0x01,0x00,0x00,0x00 }, - { 0x3B,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 } -}; - -uint8_t HD2000_vals[16][4] = { - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x14,0x00,0x00,0x00 }, - { 0xfa,0x00,0x00,0x00 }, - { 0x2c,0x01,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x14,0x00,0x00,0x00 }, - { 0xf4,0x01,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x01,0x00,0x00,0x00 }, -}; - -uint8_t HD3000_vals[16][4] = { - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x14,0x00,0x00,0x00 }, - { 0xfa,0x00,0x00,0x00 }, - { 0x2c,0x01,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x14,0x00,0x00,0x00 }, - { 0xf4,0x01,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x00,0x00,0x00,0x00 }, - { 0x01,0x00,0x00,0x00 }, -}; - -uint8_t HD2000_tbl_info[18] = { - 0x30,0x44,0x02,0x02,0x02,0x02,0x00,0x00,0x00, - 0x00,0x01,0x02,0x02,0x02,0x00,0x01,0x02,0x02 -}; -uint8_t HD2000_os_info[20] = { - 0x30,0x49,0x01,0x11,0x11,0x11,0x08,0x00,0x00,0x01, - 0xf0,0x1f,0x01,0x00,0x00,0x00,0x10,0x07,0x00,0x00 -}; - -// The following values came from a Sandy Bridge MacBook Air -uint8_t HD3000_tbl_info[18] = { - 0x30,0x44,0x02,0x02,0x02,0x02,0x00,0x00,0x00, - 0x00,0x02,0x02,0x02,0x02,0x01,0x01,0x01,0x01 -}; - -// The following values came from a Sandy Bridge MacBook Air -uint8_t HD3000_os_info[20] = { - 0x30,0x49,0x01,0x12,0x12,0x12,0x08,0x00,0x00,0x01, - 0xf0,0x1f,0x01,0x00,0x00,0x00,0x10,0x07,0x00,0x00 -}; - - -uint8_t reg_TRUE[] = { 0x01, 0x00, 0x00, 0x00 }; -uint8_t reg_FALSE[] = { 0x00, 0x00, 0x00, 0x00 }; - -static struct gma_gpu_t KnownGPUS[] = { - { 0x00000000, "Unknown" }, - { 0x808627A2, "Mobile GMA950" }, - { 0x808627AE, "Mobile GMA950" }, - { 0x808627A6, "Mobile GMA950" }, - { 0x8086A011, "Mobile GMA3150" }, - { 0x8086A012, "Mobile GMA3150" }, - { 0x80862772, "Desktop GMA950" }, - { 0x80862776, "Desktop GMA950" }, -// { 0x8086A001, "Desktop GMA3150" }, - { 0x8086A001, "Mobile GMA3150" }, - { 0x8086A002, "Desktop GMA3150" }, - { 0x80862A02, "GMAX3100" }, - { 0x80862A03, "GMAX3100" }, - { 0x80862A12, "GMAX3100" }, - { 0x80862A13, "GMAX3100" }, - { 0x80862A42, "GMAX3100" }, - { 0x80862A43, "GMAX3100" }, - { 0x80860102, "Intel HD Graphics 2000" }, - { 0x80860106, "Intel HD Graphics 2000 Mobile" }, - { 0x80860112, "Intel HD Graphics 3000" }, - { 0x80860116, "Intel HD Graphics 3000 Mobile" }, - { 0x80860122, "Intel HD Graphics 3000" }, - { 0x80860126, "Intel HD Graphics 3000 Mobile" }, -}; - -char *get_gma_model(uint32_t id) { - int i = 0; - - for (i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++) - { - if (KnownGPUS[i].device == id) - return KnownGPUS[i].name; - } - return KnownGPUS[0].name; -} - -bool setup_gma_devprop(pci_dt_t *gma_dev) -{ - char *devicepath; - volatile uint8_t *regs; - uint32_t bar[7]; - char *model; - uint8_t BuiltIn = 0x00; - uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 }; - unsigned int device_id; - - devicepath = get_pci_dev_path(gma_dev); - - bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10); - regs = (uint8_t *) (bar[0] & ~0x0f); - - model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id); - device_id = gma_dev->device_id; - - verbose("Intel %s [%04x:%04x] :: %s\n", - model, gma_dev->vendor_id, gma_dev->device_id, devicepath); - - if (!string) - string = devprop_create_string(); - - struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice)); - device = devprop_add_device(string, devicepath); - - if (!device) - { - printf("Failed initializing dev-prop string dev-entry.\n"); - pause(); - return false; - } - - devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1)); - devprop_add_value(device, "device_type", (uint8_t*)"display", 8); - - if ((model == (char *)"Mobile GMA950") - || (model == (char *)"Mobile GMA3150")) - { - devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4); - devprop_add_value(device, "built-in", &BuiltIn, 1); - devprop_add_value(device, "class-code", ClassFix, 4); - } - else if ((model == (char *)"Desktop GMA950") - || (model == (char *)"Desktop GMA3150")) - { - BuiltIn = 0x01; - devprop_add_value(device, "built-in", &BuiltIn, 1); - devprop_add_value(device, "class-code", ClassFix, 4); - } - else if (model == (char *)"GMAX3100") - { - devprop_add_value(device, "AAPL,HasPanel", GMAX3100_vals[0], 4); - devprop_add_value(device, "AAPL,SelfRefreshSupported", GMAX3100_vals[1], 4); - devprop_add_value(device, "AAPL,aux-power-connected", GMAX3100_vals[2], 4); - devprop_add_value(device, "AAPL,backlight-control", GMAX3100_vals[3], 4); - devprop_add_value(device, "AAPL00,blackscreen-preferences", GMAX3100_vals[4], 4); - devprop_add_value(device, "AAPL01,BacklightIntensity", GMAX3100_vals[5], 4); - devprop_add_value(device, "AAPL01,blackscreen-preferences", GMAX3100_vals[6], 4); - devprop_add_value(device, "AAPL01,DataJustify", GMAX3100_vals[7], 4); - devprop_add_value(device, "AAPL01,Depth", GMAX3100_vals[8], 4); - devprop_add_value(device, "AAPL01,Dither", GMAX3100_vals[9], 4); - devprop_add_value(device, "AAPL01,DualLink", GMAX3100_vals[10], 4); - devprop_add_value(device, "AAPL01,Height", GMAX3100_vals[11], 4); - devprop_add_value(device, "AAPL01,Interlace", GMAX3100_vals[12], 4); - devprop_add_value(device, "AAPL01,Inverter", GMAX3100_vals[13], 4); - devprop_add_value(device, "AAPL01,InverterCurrent", GMAX3100_vals[14], 4); - devprop_add_value(device, "AAPL01,InverterCurrency", GMAX3100_vals[15], 4); - devprop_add_value(device, "AAPL01,LinkFormat", GMAX3100_vals[16], 4); - devprop_add_value(device, "AAPL01,LinkType", GMAX3100_vals[17], 4); - devprop_add_value(device, "AAPL01,Pipe", GMAX3100_vals[18], 4); - devprop_add_value(device, "AAPL01,PixelFormat", GMAX3100_vals[19], 4); - devprop_add_value(device, "AAPL01,Refresh", GMAX3100_vals[20], 4); - devprop_add_value(device, "AAPL01,Stretch", GMAX3100_vals[21], 4); - devprop_add_value(device, "class-code", ClassFix, 4); - } - else if (model == (char *)"Intel HD Graphics 2000 Mobile") - { - devprop_add_value(device, "class-code", ClassFix, 4); - devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); - devprop_add_value(device, "AAPL00,PixelFormat", HD2000_vals[0], 4); - devprop_add_value(device, "AAPL00,T1", HD2000_vals[1], 4); - devprop_add_value(device, "AAPL00,T2", HD2000_vals[2], 4); - devprop_add_value(device, "AAPL00,T3", HD2000_vals[3], 4); - devprop_add_value(device, "AAPL00,T4", HD2000_vals[4], 4); - devprop_add_value(device, "AAPL00,T5", HD2000_vals[5], 4); - devprop_add_value(device, "AAPL00,T6", HD2000_vals[6], 4); - devprop_add_value(device, "AAPL00,T7", HD2000_vals[7], 4); - devprop_add_value(device, "AAPL00,LinkType", HD2000_vals[8], 4); - devprop_add_value(device, "AAPL00,LinkFormat", HD2000_vals[9], 4); - devprop_add_value(device, "AAPL00,DualLink", HD2000_vals[10], 4); - devprop_add_value(device, "AAPL00,Dither", HD2000_vals[11], 4); - devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4); - devprop_add_value(device, "graphic-options", HD2000_vals[13], 4); - devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18); - devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20); - } - else if (model == (char *)"Intel HD Graphics 3000 Mobile") - { - devprop_add_value(device, "class-code", ClassFix, 4); - devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); - devprop_add_value(device, "AAPL00,PixelFormat", HD3000_vals[0], 4); - devprop_add_value(device, "AAPL00,T1", HD3000_vals[1], 4); - devprop_add_value(device, "AAPL00,T2", HD3000_vals[2], 4); - devprop_add_value(device, "AAPL00,T3", HD3000_vals[3], 4); - devprop_add_value(device, "AAPL00,T4", HD3000_vals[4], 4); - devprop_add_value(device, "AAPL00,T5", HD3000_vals[5], 4); - devprop_add_value(device, "AAPL00,T6", HD3000_vals[6], 4); - devprop_add_value(device, "AAPL00,T7", HD3000_vals[7], 4); - devprop_add_value(device, "AAPL00,LinkType", HD3000_vals[8], 4); - devprop_add_value(device, "AAPL00,LinkFormat", HD3000_vals[9], 4); - devprop_add_value(device, "AAPL00,DualLink", HD3000_vals[10], 4); - devprop_add_value(device, "AAPL00,Dither", HD3000_vals[11], 4); - devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4); - devprop_add_value(device, "graphic-options", HD3000_vals[13], 4); - devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18); - devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20); - } - else if (model == (char *)"Intel HD Graphics 2000") - { - devprop_add_value(device, "built-in", &BuiltIn, 1); - devprop_add_value(device, "class-code", ClassFix, 4); - devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id)); - devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); - devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18); - devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20); - } - else if (model == (char *)"Intel HD Graphics 3000") - { - devprop_add_value(device, "built-in", &BuiltIn, 1); - devprop_add_value(device, "class-code", ClassFix, 4); - device_id = 0x00000126; // Inject a valid mobile GPU device id instead of patching kexts - devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id)); - devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); - devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18); - devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20); - } - - stringdata = malloc(sizeof(uint8_t) * string->length); - if (!stringdata) - { - printf("No stringdata.\n"); - pause(); - return false; - } - - memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); - stringlength = string->length; - - return true; -} Index: branches/ErmaC/i386/libsaio/gma.h =================================================================== --- branches/ErmaC/i386/libsaio/gma.h (revision 1567) +++ branches/ErmaC/i386/libsaio/gma.h (revision 1568) @@ -1,16 +0,0 @@ -#ifndef __LIBSAIO_GMA_H -#define __LIBSAIO_GMA_H - -bool setup_gma_devprop(pci_dt_t *gma_dev); - -struct gma_gpu_t { - unsigned device; - char *name; -}; - -#define REG8(reg) ((volatile uint8_t *)regs)[(reg)] -#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1] -#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2] - - -#endif /* !__LIBSAIO_GMA_H */ Index: branches/ErmaC/i386/libsaio/nvidia.c =================================================================== --- branches/ErmaC/i386/libsaio/nvidia.c (revision 1567) +++ branches/ErmaC/i386/libsaio/nvidia.c (revision 1568) @@ -1,1501 +0,0 @@ -/* - * NVidia injector - * - * Copyright (C) 2009 Jasmin Fazlic, iNDi - * - * NVidia injector is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * NVidia driver and injector is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with NVidia injector. If not, see . - */ -/* - * Alternatively you can choose to comply with APSL - */ - - -/* - * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license: - * - * - * Copyright 2005-2006 Erik Waling - * Copyright 2006 Stephane Marchesin - * Copyright 2007-2009 Stuart Bennett - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "boot.h" -#include "bootstruct.h" -#include "pci.h" -#include "platform.h" -#include "device_inject.h" -#include "nvidia.h" - -#ifndef DEBUG_NVIDIA -#define DEBUG_NVIDIA 0 -#endif - -#if DEBUG_NVIDIA -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif - -#define NVIDIA_ROM_SIZE 0x10000 -#define PATCH_ROM_SUCCESS 1 -#define PATCH_ROM_SUCCESS_HAS_LVDS 2 -#define PATCH_ROM_FAILED 0 -#define MAX_NUM_DCB_ENTRIES 16 -#define TYPE_GROUPED 0xff - -extern uint32_t devices_number; - -const char *nvidia_compatible_0[] = { "@0,compatible", "NVDA,NVMac" }; -const char *nvidia_compatible_1[] = { "@1,compatible", "NVDA,NVMac" }; -const char *nvidia_device_type_0[] = { "@0,device_type", "display" }; -const char *nvidia_device_type_1[] = { "@1,device_type", "display" }; -const char *nvidia_device_type[] = { "device_type", "NVDA,Parent" }; -const char *nvidia_name_0[] = { "@0,name", "NVDA,Display-A" }; -const char *nvidia_name_1[] = { "@1,name", "NVDA,Display-B" }; -const char *nvidia_slot_name[] = { "AAPL,slot-name", "Slot-1" }; - -static uint8_t default_NVCAP[]= { - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x00 -}; - -#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) ) - -static uint8_t default_dcfg_0[] = {0xff, 0xff, 0xff, 0xff}; -static uint8_t default_dcfg_1[] = {0xff, 0xff, 0xff, 0xff}; - -#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) ) -#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) ) - -static struct nv_chipsets_t NVKnownChipsets[] = { - { 0x00000000, "Unknown" }, -// temporary placement - { 0x10DE0DF4, "GeForce GT 450M" }, //Azi + issue #99 - { 0x10DE1251, "GeForce GTX 560M" }, // Asus G74SX -//======================================== - // 0040 - 004F - { 0x10DE0040, "GeForce 6800 Ultra" }, - { 0x10DE0041, "GeForce 6800" }, - { 0x10DE0042, "GeForce 6800 LE" }, - { 0x10DE0043, "GeForce 6800 XE" }, - { 0x10DE0044, "GeForce 6800 XT" }, - { 0x10DE0045, "GeForce 6800 GT" }, - { 0x10DE0046, "GeForce 6800 GT" }, - { 0x10DE0047, "GeForce 6800 GS" }, - { 0x10DE0048, "GeForce 6800 XT" }, - { 0x10DE004D, "Quadro FX 3400" }, - { 0x10DE004E, "Quadro FX 4000" }, - // 0050 - 005F - // 0060 - 006F - // 0070 - 007F - // 0080 - 008F - // 0090 - 009F - { 0x10DE0090, "GeForce 7800 GTX" }, - { 0x10DE0091, "GeForce 7800 GTX" }, - { 0x10DE0092, "GeForce 7800 GT" }, - { 0x10DE0093, "GeForce 7800 GS" }, - { 0x10DE0095, "GeForce 7800 SLI" }, - { 0x10DE0098, "GeForce Go 7800" }, - { 0x10DE0099, "GeForce Go 7800 GTX" }, - { 0x10DE009D, "Quadro FX 4500" }, - // 00A0 - 00AF - // 00B0 - 00BF - // 00C0 - 00CF - { 0x10DE00C0, "GeForce 6800 GS" }, - { 0x10DE00C1, "GeForce 6800" }, - { 0x10DE00C2, "GeForce 6800 LE" }, - { 0x10DE00C3, "GeForce 6800 XT" }, - { 0x10DE00C8, "GeForce Go 6800" }, - { 0x10DE00C9, "GeForce Go 6800 Ultra" }, - { 0x10DE00CC, "Quadro FX Go1400" }, - { 0x10DE00CD, "Quadro FX 3450/4000 SDI" }, - { 0x10DE00CE, "Quadro FX 1400" }, - // 00D0 - 00DF - // 00E0 - 00EF - // 00F0 - 00FF - { 0x10DE00F1, "GeForce 6600 GT" }, - { 0x10DE00F2, "GeForce 6600" }, - { 0x10DE00F3, "GeForce 6200" }, - { 0x10DE00F4, "GeForce 6600 LE" }, - { 0x10DE00F5, "GeForce 7800 GS" }, - { 0x10DE00F6, "GeForce 6800 GS/XT" }, - { 0x10DE00F8, "Quadro FX 3400/4400" }, - { 0x10DE00F9, "GeForce 6800 Series GPU" }, - // 0100 - 010F - // 0110 - 011F - // 0120 - 012F - // 0130 - 013F - // 0140 - 014F - { 0x10DE0140, "GeForce 6600 GT" }, - { 0x10DE0141, "GeForce 6600" }, - { 0x10DE0142, "GeForce 6600 LE" }, - { 0x10DE0143, "GeForce 6600 VE" }, - { 0x10DE0144, "GeForce Go 6600" }, - { 0x10DE0145, "GeForce 6610 XL" }, - { 0x10DE0146, "GeForce Go 6600 TE/6200 TE" }, - { 0x10DE0147, "GeForce 6700 XL" }, - { 0x10DE0148, "GeForce Go 6600" }, - { 0x10DE0149, "GeForce Go 6600 GT" }, - { 0x10DE014A, "Quadro NVS 440" }, - { 0x10DE014C, "Quadro FX 550" }, - { 0x10DE014D, "Quadro FX 550" }, - { 0x10DE014E, "Quadro FX 540" }, - { 0x10DE014F, "GeForce 6200" }, - // 0150 - 015F - // 0160 - 016F - { 0x10DE0160, "GeForce 6500" }, - { 0x10DE0161, "GeForce 6200 TurboCache(TM)" }, - { 0x10DE0162, "GeForce 6200SE TurboCache(TM)" }, - { 0x10DE0163, "GeForce 6200 LE" }, - { 0x10DE0164, "GeForce Go 6200" }, - { 0x10DE0165, "Quadro NVS 285" }, - { 0x10DE0166, "GeForce Go 6400" }, - { 0x10DE0167, "GeForce Go 6200" }, - { 0x10DE0168, "GeForce Go 6400" }, - { 0x10DE0169, "GeForce 6250" }, - { 0x10DE016A, "GeForce 7100 GS" }, - // 0170 - 017F - // 0180 - 018F - // 0190 - 019F - { 0x10DE0191, "GeForce 8800 GTX" }, - { 0x10DE0193, "GeForce 8800 GTS" }, - { 0x10DE0194, "GeForce 8800 Ultra" }, - { 0x10DE0197, "Tesla C870" }, - { 0x10DE019D, "Quadro FX 5600" }, - { 0x10DE019E, "Quadro FX 4600" }, - // 01A0 - 01AF - // 01B0 - 01BF - // 01C0 - 01CF - // 01D0 - 01DF - { 0x10DE01D0, "GeForce 7350 LE" }, - { 0x10DE01D1, "GeForce 7300 LE" }, - { 0x10DE01D2, "GeForce 7550 LE" }, - { 0x10DE01D3, "GeForce 7300 SE/7200 GS" }, - { 0x10DE01D6, "GeForce Go 7200" }, - { 0x10DE01D7, "GeForce Go 7300" }, - { 0x10DE01D8, "GeForce Go 7400" }, - { 0x10DE01D9, "GeForce Go 7400 GS" }, - { 0x10DE01DA, "Quadro NVS 110M" }, - { 0x10DE01DB, "Quadro NVS 120M" }, - { 0x10DE01DC, "Quadro FX 350M" }, - { 0x10DE01DD, "GeForce 7500 LE" }, - { 0x10DE01DE, "Quadro FX 350" }, - { 0x10DE01DF, "GeForce 7300 GS" }, - // 01E0 - 01EF - // 01F0 - 01FF - // 0200 - 020F - // 0210 - 021F - { 0x10DE0211, "GeForce 6800" }, - { 0x10DE0212, "GeForce 6800 LE" }, - { 0x10DE0215, "GeForce 6800 GT" }, - { 0x10DE0218, "GeForce 6800 XT" }, - // 0220 - 022F - { 0x10DE0221, "GeForce 6200" }, - { 0x10DE0222, "GeForce 6200 A-LE" }, - // 0230 - 023F - // 0240 - 024F - { 0x10DE0240, "GeForce 6150" }, - { 0x10DE0241, "GeForce 6150 LE" }, - { 0x10DE0242, "GeForce 6100" }, - { 0x10DE0244, "GeForce Go 6150" }, - { 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" }, - { 0x10DE0247, "GeForce Go 6100" }, - // 0250 - 025F - // 0260 - 026F - // 0270 - 027F - // 0280 - 028F - // 0290 - 029F - { 0x10DE0290, "GeForce 7900 GTX" }, - { 0x10DE0291, "GeForce 7900 GT/GTO" }, - { 0x10DE0292, "GeForce 7900 GS" }, - { 0x10DE0293, "GeForce 7950 GX2" }, - { 0x10DE0294, "GeForce 7950 GX2" }, - { 0x10DE0295, "GeForce 7950 GT" }, - { 0x10DE0298, "GeForce Go 7900 GS" }, - { 0x10DE0299, "GeForce Go 7900 GTX" }, - { 0x10DE029A, "Quadro FX 2500M" }, - { 0x10DE029B, "Quadro FX 1500M" }, - { 0x10DE029C, "Quadro FX 5500" }, - { 0x10DE029D, "Quadro FX 3500" }, - { 0x10DE029E, "Quadro FX 1500" }, - { 0x10DE029F, "Quadro FX 4500 X2" }, - // 02A0 - 02AF - // 02B0 - 02BF - // 02C0 - 02CF - // 02D0 - 02DF - // 02E0 - 02EF - { 0x10DE02E0, "GeForce 7600 GT" }, - { 0x10DE02E1, "GeForce 7600 GS" }, - { 0x10DE02E2, "GeForce 7300 GT" }, - { 0x10DE02E3, "GeForce 7900 GS" }, - { 0x10DE02E4, "GeForce 7950 GT" }, - // 02F0 - 02FF - // 0300 - 030F - { 0x10DE0301, "GeForce FX 5800 Ultra" }, - { 0x10DE0302, "GeForce FX 5800" }, - { 0x10DE0308, "Quadro FX 2000" }, - { 0x10DE0309, "Quadro FX 1000" }, - // 0310 - 031F - { 0x10DE0311, "GeForce FX 5600 Ultra" }, - { 0x10DE0312, "GeForce FX 5600" }, - { 0x10DE0314, "GeForce FX 5600XT" }, - { 0x10DE031A, "GeForce FX Go5600" }, - { 0x10DE031B, "GeForce FX Go5650" }, - { 0x10DE031C, "Quadro FX Go700" }, - // 0320 - 032F - { 0x10DE0324, "GeForce FX Go5200" }, - { 0x10DE0325, "GeForce FX Go5250" }, - { 0x10DE0326, "GeForce FX 5500" }, - { 0x10DE0328, "GeForce FX Go5200 32M/64M" }, - { 0x10DE032A, "Quadro NVS 55/280 PCI" }, - { 0x10DE032B, "Quadro FX 500/600 PCI" }, - { 0x10DE032C, "GeForce FX Go53xx Series" }, - { 0x10DE032D, "GeForce FX Go5100" }, - // 0330 - 033F - { 0x10DE0330, "GeForce FX 5900 Ultra" }, - { 0x10DE0331, "GeForce FX 5900" }, - { 0x10DE0332, "GeForce FX 5900XT" }, - { 0x10DE0333, "GeForce FX 5950 Ultra" }, - { 0x10DE0334, "GeForce FX 5900ZT" }, - { 0x10DE0338, "Quadro FX 3000" }, - { 0x10DE033F, "Quadro FX 700" }, - // 0340 - 034F - { 0x10DE0341, "GeForce FX 5700 Ultra" }, - { 0x10DE0342, "GeForce FX 5700" }, - { 0x10DE0343, "GeForce FX 5700LE" }, - { 0x10DE0344, "GeForce FX 5700VE" }, - { 0x10DE0347, "GeForce FX Go5700" }, - { 0x10DE0348, "GeForce FX Go5700" }, - { 0x10DE034C, "Quadro FX Go1000" }, - { 0x10DE034E, "Quadro FX 1100" }, - // 0350 - 035F - // 0360 - 036F - // 0370 - 037F - // 0380 - 038F - { 0x10DE038B, "GeForce 7650 GS" }, - // 0390 - 039F - { 0x10DE0390, "GeForce 7650 GS" }, - { 0x10DE0391, "GeForce 7600 GT" }, - { 0x10DE0392, "GeForce 7600 GS" }, - { 0x10DE0393, "GeForce 7300 GT" }, - { 0x10DE0394, "GeForce 7600 LE" }, - { 0x10DE0395, "GeForce 7300 GT" }, - { 0x10DE0397, "GeForce Go 7700" }, - { 0x10DE0398, "GeForce Go 7600" }, - { 0x10DE0399, "GeForce Go 7600 GT"}, - { 0x10DE039A, "Quadro NVS 300M" }, - { 0x10DE039B, "GeForce Go 7900 SE" }, - { 0x10DE039C, "Quadro FX 550M" }, - { 0x10DE039E, "Quadro FX 560" }, - // 03A0 - 03AF - // 03B0 - 03BF - // 03C0 - 03CF - // 03D0 - 03DF - { 0x10DE03D0, "GeForce 6150SE nForce 430" }, - { 0x10DE03D1, "GeForce 6100 nForce 405" }, - { 0x10DE03D2, "GeForce 6100 nForce 400" }, - { 0x10DE03D5, "GeForce 6100 nForce 420" }, - { 0x10DE03D6, "GeForce 7025 / nForce 630a" }, - // 03E0 - 03EF - // 03F0 - 03FF - // 0400 - 040F - { 0x10DE0400, "GeForce 8600 GTS" }, - { 0x10DE0401, "GeForce 8600 GT" }, - { 0x10DE0402, "GeForce 8600 GT" }, - { 0x10DE0403, "GeForce 8600 GS" }, - { 0x10DE0404, "GeForce 8400 GS" }, - { 0x10DE0405, "GeForce 9500M GS" }, - { 0x10DE0406, "GeForce 8300 GS" }, - { 0x10DE0407, "GeForce 8600M GT" }, - { 0x10DE0408, "GeForce 9650M GS" }, - { 0x10DE0409, "GeForce 8700M GT" }, - { 0x10DE040A, "Quadro FX 370" }, - { 0x10DE040B, "Quadro NVS 320M" }, - { 0x10DE040C, "Quadro FX 570M" }, - { 0x10DE040D, "Quadro FX 1600M" }, - { 0x10DE040E, "Quadro FX 570" }, - { 0x10DE040F, "Quadro FX 1700" }, - // 0410 - 041F - { 0x10DE0410, "GeForce GT 330" }, - // 0420 - 042F - { 0x10DE0420, "GeForce 8400 SE" }, - { 0x10DE0421, "GeForce 8500 GT" }, - { 0x10DE0422, "GeForce 8400 GS" }, - { 0x10DE0423, "GeForce 8300 GS" }, - { 0x10DE0424, "GeForce 8400 GS" }, - { 0x10DE0425, "GeForce 8600M GS" }, - { 0x10DE0426, "GeForce 8400M GT" }, - { 0x10DE0427, "GeForce 8400M GS" }, - { 0x10DE0428, "GeForce 8400M G" }, - { 0x10DE0429, "Quadro NVS 140M" }, - { 0x10DE042A, "Quadro NVS 130M" }, - { 0x10DE042B, "Quadro NVS 135M" }, - { 0x10DE042C, "GeForce 9400 GT" }, - { 0x10DE042D, "Quadro FX 360M" }, - { 0x10DE042E, "GeForce 9300M G" }, - { 0x10DE042F, "Quadro NVS 290" }, - // 0430 - 043F - // 0440 - 044F - // 0450 - 045F - // 0460 - 046F - // 0470 - 047F - // 0480 - 048F - // 0490 - 049F - // 04A0 - 04AF - // 04B0 - 04BF - // 04C0 - 04CF - // 04D0 - 04DF - // 04E0 - 04EF - // 04F0 - 04FF - // 0500 - 050F - // 0510 - 051F - // 0520 - 052F - // 0530 - 053F - { 0x10DE053A, "GeForce 7050 PV / nForce 630a" }, - { 0x10DE053B, "GeForce 7050 PV / nForce 630a" }, - { 0x10DE053E, "GeForce 7025 / nForce 630a" }, - // 0540 - 054F - // 0550 - 055F - // 0560 - 056F - // 0570 - 057F - // 0580 - 058F - // 0590 - 059F - // 05A0 - 05AF - // 05B0 - 05BF - // 05C0 - 05CF - // 05D0 - 05DF - // 05E0 - 05EF - { 0x10DE05E0, "GeForce GTX 295" }, - { 0x10DE05E1, "GeForce GTX 280" }, - { 0x10DE05E2, "GeForce GTX 260" }, - { 0x10DE05E3, "GeForce GTX 285" }, - { 0x10DE05E6, "GeForce GTX 275" }, - { 0x10DE05EA, "GeForce GTX 260" }, - { 0x10DE05EB, "GeForce GTX 295" }, - { 0x10DE05ED, "Quadroplex 2200 D2" }, - // 05F0 - 05FF - { 0x10DE05F8, "Quadroplex 2200 S4" }, - { 0x10DE05F9, "Quadro CX" }, - { 0x10DE05FD, "Quadro FX 5800" }, - { 0x10DE05FE, "Quadro FX 4800" }, - { 0x10DE05FF, "Quadro FX 3800" }, - // 0600 - 060F - { 0x10DE0600, "GeForce 8800 GTS 512" }, - { 0x10DE0601, "GeForce 9800 GT" }, - { 0x10DE0602, "GeForce 8800 GT" }, - { 0x10DE0603, "GeForce GT 230" }, - { 0x10DE0604, "GeForce 9800 GX2" }, - { 0x10DE0605, "GeForce 9800 GT" }, - { 0x10DE0606, "GeForce 8800 GS" }, - { 0x10DE0607, "GeForce GTS 240" }, - { 0x10DE0608, "GeForce 9800M GTX" }, - { 0x10DE0609, "GeForce 8800M GTS" }, - { 0x10DE060A, "GeForce GTX 280M" }, - { 0x10DE060B, "GeForce 9800M GT" }, - { 0x10DE060C, "GeForce 8800M GTX" }, - { 0x10DE060D, "GeForce 8800 GS" }, - { 0x10DE060F, "GeForce GTX 285M" }, - // 0610 - 061F - { 0x10DE0610, "GeForce 9600 GSO" }, - { 0x10DE0611, "GeForce 8800 GT" }, - { 0x10DE0612, "GeForce 9800 GTX" }, - { 0x10DE0613, "GeForce 9800 GTX+" }, - { 0x10DE0614, "GeForce 9800 GT" }, - { 0x10DE0615, "GeForce GTS 250" }, - { 0x10DE0617, "GeForce 9800M GTX" }, - { 0x10DE0618, "GeForce GTX 260M" }, - { 0x10DE0619, "Quadro FX 4700 X2" }, - { 0x10DE061A, "Quadro FX 3700" }, - { 0x10DE061B, "Quadro VX 200" }, - { 0x10DE061C, "Quadro FX 3600M" }, - { 0x10DE061D, "Quadro FX 2800M" }, - { 0x10DE061F, "Quadro FX 3800M" }, - // 0620 - 062F - { 0x10DE0622, "GeForce 9600 GT" }, - { 0x10DE0623, "GeForce 9600 GS" }, - { 0x10DE0625, "GeForce 9600 GSO 512"}, - { 0x10DE0626, "GeForce GT 130" }, - { 0x10DE0627, "GeForce GT 140" }, - { 0x10DE0628, "GeForce 9800M GTS" }, - { 0x10DE062A, "GeForce 9700M GTS" }, - { 0x10DE062C, "GeForce 9800M GTS" }, - { 0x10DE062D, "GeForce 9600 GT" }, - { 0x10DE062E, "GeForce 9600 GT" }, - // 0630 - 063F - { 0x10DE0631, "GeForce GTS 160M" }, - { 0x10DE0632, "GeForce GTS 150M" }, - { 0x10DE0635, "GeForce 9600 GSO" }, - { 0x10DE0637, "GeForce 9600 GT" }, - { 0x10DE0638, "Quadro FX 1800" }, - { 0x10DE063A, "Quadro FX 2700M" }, - // 0640 - 064F - { 0x10DE0640, "GeForce 9500 GT" }, - { 0x10DE0641, "GeForce 9400 GT" }, - { 0x10DE0642, "GeForce 8400 GS" }, - { 0x10DE0643, "GeForce 9500 GT" }, - { 0x10DE0644, "GeForce 9500 GS" }, - { 0x10DE0645, "GeForce 9500 GS" }, - { 0x10DE0646, "GeForce GT 120" }, - { 0x10DE0647, "GeForce 9600M GT" }, - { 0x10DE0648, "GeForce 9600M GS" }, - { 0x10DE0649, "GeForce 9600M GT" }, - { 0x10DE064A, "GeForce 9700M GT" }, - { 0x10DE064B, "GeForce 9500M G" }, - { 0x10DE064C, "GeForce 9650M GT" }, - // 0650 - 065F - { 0x10DE0651, "GeForce G 110M" }, - { 0x10DE0652, "GeForce GT 130M" }, - { 0x10DE0653, "GeForce GT 120M" }, - { 0x10DE0654, "GeForce GT 220M" }, - { 0x10DE0656, "GeForce 9650 S" }, - { 0x10DE0658, "Quadro FX 380" }, - { 0x10DE0659, "Quadro FX 580" }, - { 0x10DE065A, "Quadro FX 1700M" }, - { 0x10DE065B, "GeForce 9400 GT" }, - { 0x10DE065C, "Quadro FX 770M" }, - { 0x10DE065F, "GeForce G210" }, - // 0660 - 066F - // 0670 - 067F - // 0680 - 068F - // 0690 - 069F - // 06A0 - 06AF - // 06B0 - 06BF - // 06C0 - 06CF - { 0x10DE06C0, "GeForce GTX 480" }, - { 0x10DE06C3, "GeForce GTX D12U" }, - { 0x10DE06C4, "GeForce GTX 465" }, - { 0x10DE06CA, "GeForce GTX 480M" }, - { 0x10DE06CD, "GeForce GTX 470" }, - // 06D0 - 06DF - { 0x10DE06D1, "Tesla C2050" }, // TODO: sub-device id: 0x0771 - { 0x10DE06D1, "Tesla C2070" }, // TODO: sub-device id: 0x0772 - { 0x10DE06D2, "Tesla M2070" }, - { 0x10DE06D8, "Quadro 6000" }, - { 0x10DE06D9, "Quadro 5000" }, - { 0x10DE06DA, "Quadro 5000M" }, - { 0x10DE06DC, "Quadro 6000" }, - { 0x10DE06DD, "Quadro 4000" }, - { 0x10DE06DE, "Tesla M2050" }, // TODO: sub-device id: 0x0846 - { 0x10DE06DE, "Tesla M2070" }, // TODO: sub-device id: ? - { 0x10DE06DF, "Tesla M2070-Q" }, - // 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070 - // 06E0 - 06EF - { 0x10DE06E0, "GeForce 9300 GE" }, - { 0x10DE06E1, "GeForce 9300 GS" }, - { 0x10DE06E2, "GeForce 8400" }, - { 0x10DE06E3, "GeForce 8400 SE" }, - { 0x10DE06E4, "GeForce 8400 GS" }, - { 0x10DE06E5, "GeForce 9300M GS" }, - { 0x10DE06E6, "GeForce G100" }, - { 0x10DE06E7, "GeForce 9300 SE" }, - { 0x10DE06E8, "GeForce 9200M GS" }, - { 0x10DE06E9, "GeForce 9300M GS" }, - { 0x10DE06EA, "Quadro NVS 150M" }, - { 0x10DE06EB, "Quadro NVS 160M" }, - { 0x10DE06EC, "GeForce G 105M" }, - { 0x10DE06EF, "GeForce G 103M" }, - // 06F0 - 06FF - { 0x10DE06F8, "Quadro NVS 420" }, - { 0x10DE06F9, "Quadro FX 370 LP" }, - { 0x10DE06FA, "Quadro NVS 450" }, - { 0x10DE06FB, "Quadro FX 370M" }, - { 0x10DE06FD, "Quadro NVS 295" }, - // 0700 - 070F - // 0710 - 071F - // 0720 - 072F - // 0730 - 073F - // 0740 - 074F - // 0750 - 075F - // 0760 - 076F - // 0770 - 077F - // 0780 - 078F - // 0790 - 079F - // 07A0 - 07AF - // 07B0 - 07BF - // 07C0 - 07CF - // 07D0 - 07DF - // 07E0 - 07EF - { 0x10DE07E0, "GeForce 7150 / nForce 630i" }, - { 0x10DE07E1, "GeForce 7100 / nForce 630i" }, - { 0x10DE07E2, "GeForce 7050 / nForce 630i" }, - { 0x10DE07E3, "GeForce 7050 / nForce 610i" }, - { 0x10DE07E5, "GeForce 7050 / nForce 620i" }, - // 07F0 - 07FF - // 0800 - 080F - // 0810 - 081F - // 0820 - 082F - // 0830 - 083F - // 0840 - 084F - { 0x10DE0844, "GeForce 9100M G" }, - { 0x10DE0845, "GeForce 8200M G" }, - { 0x10DE0846, "GeForce 9200" }, - { 0x10DE0847, "GeForce 9100" }, - { 0x10DE0848, "GeForce 8300" }, - { 0x10DE0849, "GeForce 8200" }, - { 0x10DE084A, "nForce 730a" }, - { 0x10DE084B, "GeForce 9200" }, - { 0x10DE084C, "nForce 980a/780a SLI" }, - { 0x10DE084D, "nForce 750a SLI" }, - { 0x10DE084F, "GeForce 8100 / nForce 720a" }, - // 0850 - 085F - // 0860 - 086F - { 0x10DE0860, "GeForce 9400" }, - { 0x10DE0861, "GeForce 9400" }, - { 0x10DE0862, "GeForce 9400M G" }, - { 0x10DE0863, "GeForce 9400M" }, - { 0x10DE0864, "GeForce 9300" }, - { 0x10DE0865, "ION" }, - { 0x10DE0866, "GeForce 9400M G" }, - { 0x10DE0867, "GeForce 9400" }, - { 0x10DE0868, "nForce 760i SLI" }, - { 0x10DE086A, "GeForce 9400" }, - { 0x10DE086C, "GeForce 9300 / nForce 730i" }, - { 0x10DE086D, "GeForce 9200" }, - { 0x10DE086E, "GeForce 9100M G" }, - { 0x10DE086F, "GeForce 8200M G" }, - // 0870 - 087F - { 0x10DE0870, "GeForce 9400M" }, - { 0x10DE0871, "GeForce 9200" }, - { 0x10DE0872, "GeForce G102M" }, - { 0x10DE0873, "GeForce G102M" }, - { 0x10DE0874, "ION 9300M" }, - { 0x10DE0876, "ION" }, - { 0x10DE087A, "GeForce 9400" }, - { 0x10DE087D, "ION 9400M" }, - { 0x10DE087E, "ION LE" }, - { 0x10DE087F, "ION LE" }, - // 0880 - 088F - // 0890 - 089F - // 08A0 - 08AF - // 08B0 - 08BF - // 08C0 - 08CF - // 08D0 - 08DF - // 08E0 - 08EF - // 08F0 - 08FF - // 0900 - 090F - // 0910 - 091F - // 0920 - 092F - // 0930 - 093F - // 0940 - 094F - // 0950 - 095F - // 0960 - 096F - // 0970 - 097F - // 0980 - 098F - // 0990 - 099F - // 09A0 - 09AF - // 09B0 - 09BF - // 09C0 - 09CF - // 09D0 - 09DF - // 09E0 - 09EF - // 09F0 - 09FF - // 0A00 - 0A0F - // 0A10 - 0A1F - // 0A20 - 0A2F - { 0x10DE0A20, "GeForce GT220" }, - { 0x10DE0A22, "GeForce 315" }, - { 0x10DE0A23, "GeForce 210" }, - { 0x10DE0A28, "GeForce GT 230M" }, - { 0x10DE0A29, "GeForce GT 330M" }, - { 0x10DE0A2A, "GeForce GT 230M" }, - { 0x10DE0A2B, "GeForce GT 330M" }, - { 0x10DE0A2C, "NVS 5100M" }, - { 0x10DE0A2D, "GeForce GT 320M" }, - // 0A30 - 0A3F - { 0x10DE0A34, "GeForce GT 240M" }, - { 0x10DE0A35, "GeForce GT 325M" }, - { 0x10DE0A3C, "Quadro FX 880M" }, - // 0A40 - 0A4F - // 0A50 - 0A5F - // 0A60 - 0A6F - { 0x10DE0A60, "GeForce G210" }, - { 0x10DE0A62, "GeForce 205" }, - { 0x10DE0A63, "GeForce 310" }, - { 0x10DE0A64, "ION" }, - { 0x10DE0A65, "GeForce 210" }, - { 0x10DE0A66, "GeForce 310" }, - { 0x10DE0A67, "GeForce 315" }, - { 0x10DE0A68, "GeForce G105M" }, - { 0x10DE0A69, "GeForce G105M" }, - { 0x10DE0A6A, "NVS 2100M" }, - { 0x10DE0A6C, "NVS 3100M" }, - { 0x10DE0A6E, "GeForce 305M" }, - { 0x10DE0A6F, "ION" }, - // 0A70 - 0A7F - { 0x10DE0A70, "GeForce 310M" }, - { 0x10DE0A71, "GeForce 305M" }, - { 0x10DE0A72, "GeForce 310M" }, - { 0x10DE0A73, "GeForce 305M" }, - { 0x10DE0A74, "GeForce G210M" }, - { 0x10DE0A75, "GeForce G310M" }, - { 0x10DE0A78, "Quadro FX 380 LP" }, - { 0x10DE0A7C, "Quadro FX 380M" }, - // 0A80 - 0A8F - // 0A90 - 0A9F - // 0AA0 - 0AAF - // 0AB0 - 0ABF - // 0AC0 - 0ACF - // 0AD0 - 0ADF - // 0AE0 - 0AEF - // 0AF0 - 0AFF - // 0B00 - 0B0F - // 0B10 - 0B1F - // 0B20 - 0B2F - // 0B30 - 0B3F - // 0B40 - 0B4F - // 0B50 - 0B5F - // 0B60 - 0B6F - // 0B70 - 0B7F - // 0B80 - 0B8F - // 0B90 - 0B9F - // 0BA0 - 0BAF - // 0BB0 - 0BBF - // 0BC0 - 0BCF - // 0BD0 - 0BDF - // 0BE0 - 0BEF - // 0BF0 - 0BFF - // 0C00 - 0C0F - // 0C10 - 0C1F - // 0C20 - 0C2F - // 0C30 - 0C3F - // 0C40 - 0C4F - // 0C50 - 0C5F - // 0C60 - 0C6F - // 0C70 - 0C7F - // 0C80 - 0C8F - // 0C90 - 0C9F - // 0CA0 - 0CAF - { 0x10DE0CA0, "GeForce GT 330 " }, - { 0x10DE0CA2, "GeForce GT 320" }, - { 0x10DE0CA3, "GeForce GT 240" }, - { 0x10DE0CA4, "GeForce GT 340" }, - { 0x10DE0CA7, "GeForce GT 330" }, - { 0x10DE0CA8, "GeForce GTS 260M" }, - { 0x10DE0CA9, "GeForce GTS 250M" }, - { 0x10DE0CAC, "GeForce 315" }, - { 0x10DE0CAF, "GeForce GT 335M" }, - // 0CB0 - 0CBF - { 0x10DE0CB0, "GeForce GTS 350M" }, - { 0x10DE0CB1, "GeForce GTS 360M" }, - { 0x10DE0CBC, "Quadro FX 1800M" }, - // 0CC0 - 0CCF - // 0CD0 - 0CDF - // 0CE0 - 0CEF - // 0CF0 - 0CFF - // 0D00 - 0D0F - // 0D10 - 0D1F - // 0D20 - 0D2F - // 0D30 - 0D3F - // 0D40 - 0D4F - // 0D50 - 0D5F - // 0D60 - 0D6F - // 0D70 - 0D7F - // 0D80 - 0D8F - // 0D90 - 0D9F - // 0DA0 - 0DAF - // 0DB0 - 0DBF - // 0DC0 - 0DCF - { 0x10DE0DC0, "GeForce GT 440" }, - { 0x10DE0DC1, "D12-P1-35" }, - { 0x10DE0DC2, "D12-P1-35" }, - { 0x10DE0DC4, "GeForce GTS 450" }, - { 0x10DE0DC5, "GeForce GTS 450" }, - { 0x10DE0DC6, "GeForce GTS 450" }, - { 0x10DE0DCA, "GF10x" }, - // 0DD0 - 0DDF - { 0x10DE0DCD, "GeForce GT 555M" }, - { 0x10DE0DCE, "GeForce GT 555M" }, - { 0x10DE0DD1, "GeForce GTX 460M" }, - { 0x10DE0DD2, "GeForce GT 445M" }, - { 0x10DE0DD3, "GeForce GT 435M" }, - { 0x10DE0DD6, "GeForce GT 550M" }, - { 0x10DE0DD8, "Quadro 2000" }, - { 0x10DE0DDA, "Quadro 2000M" }, - { 0x10DE0DDE, "GF106-ES" }, - { 0x10DE0DDF, "GF106-INT" }, - // 0DE0 - 0DEF - { 0x10DE0DE0, "GeForce GT 440" }, - { 0x10DE0DE1, "GeForce GT 430" }, - { 0x10DE0DE2, "GeForce GT 420" }, - { 0x10DE0DE5, "GeForce GT 530" }, - { 0x10DE0DEB, "GeForce GT 555M" }, - { 0x10DE0DEC, "GeForce GT 525M" }, - { 0x10DE0DED, "GeForce GT 520M" }, - { 0x10DE0DEE, "GeForce GT 415M" }, - // 0DF0 - 0DFF - { 0x10DE0DF0, "GeForce GT 425M" }, - { 0x10DE0DF1, "GeForce GT 420M" }, - { 0x10DE0DF2, "GeForce GT 435M" }, - { 0x10DE0DF3, "GeForce GT 420M" }, - { 0x10DE0DF4, "GeForce GT 540M" }, - { 0x10DE0DF5, "GeForce GT 525M" }, - { 0x10DE0DF6, "GeForce GT 550M" }, - { 0x10DE0DF7, "GeForce GT 520M" }, - { 0x10DE0DF8, "Quadro 600" }, - { 0x10DE0DFA, "Quadro 1000M" }, - { 0x10DE0DFE, "GF108 ES" }, - { 0x10DE0DFF, "GF108 INT" }, - // 0E00 - 0E0F - // 0E10 - 0E1F - // 0E20 - 0E2F - { 0x10DE0E21, "D12U-25" }, - { 0x10DE0E22, "GeForce GTX 460" }, - { 0x10DE0E23, "GeForce GTX 460 SE" }, - { 0x10DE0E24, "GeForce GTX 460" }, - { 0x10DE0E25, "D12U-50" }, - // 0E30 - 0E3F - { 0x10DE0E30, "GeForce GTX 470M" }, - { 0x10DE0E31, "GeForce GTX 485M" }, - { 0x10DE0E38, "GF104GL" }, - { 0x10DE0E3A, "Quadro 3000M" }, - { 0x10DE0E3B, "Quadro 4000M" }, - { 0x10DE0E3E, "GF104-ES" }, - { 0x10DE0E3F, "GF104-INT" }, - // 0E40 - 0E4F - // 0E50 - 0E5F - // 0E60 - 0E6F - // 0E70 - 0E7F - // 0E80 - 0E8F - // 0E90 - 0E9F - // 0EA0 - 0EAF - // 0EB0 - 0EBF - // 0EC0 - 0ECF - // 0ED0 - 0EDF - // 0EE0 - 0EEF - // 0EF0 - 0EFF - // 0F00 - 0F0F - // 0F10 - 0F1F - // 0F20 - 0F2F - // 0F30 - 0F3F - // 0F40 - 0F4F - // 0F50 - 0F5F - // 0F60 - 0F6F - // 0F70 - 0F7F - // 0F80 - 0F8F - // 0F90 - 0F9F - // 0FA0 - 0FAF - // 0FB0 - 0FBF - // 0FC0 - 0FCF - // 0FD0 - 0FDF - // 0FE0 - 0FEF - // 0FF0 - 0FFF - // 1000 - 100F - // 1010 - 101F - // 1020 - 102F - // 1030 - 103F - // 1040 - 104F - { 0x10DE1040, "GeForce GT 520" }, - // 1050 - 105F - { 0x10DE1050, "GeForce GT 520M" }, - // 1060 - 106F - // 1070 - 107F - // 1080 - 108F - { 0x10DE1054, "GeForce GT 410M" }, - { 0x10DE1056, "NVS 4200M" }, - { 0x10DE1057, "NVS 4200M" }, - { 0x10DE107F, "NVIDIA GF119-ES" }, - { 0x10DE1080, "GeForce GTX 580" }, - { 0x10DE1081, "GeForce GTX 570" }, - { 0x10DE1082, "GeForce GTX 560 Ti" }, - { 0x10DE1083, "D13U" }, - { 0x10DE1086, "GeForce GTX 570" }, - { 0x10DE1088, "GeForce GTX 590" }, - // 1090 - 109F - { 0x10DE1098, "D13U" }, - { 0x10DE109A, "Quadro 5010M / N12E-Q5" }, - // 10A0 - 10AF - // 10B0 - 10BF - // 10C0 - 10CF - { 0x10DE10C3, "GeForce 8400 GS" }, - { 0x10DE10C5, "GeForce 405" }, - // 1200 - - { 0x10DE1200, "GeForce GTX 560 Ti" }, - { 0x10DE1201, "GeForce GTX 560" }, - { 0x10DE1244, "GeForce GTX 550 Ti" }, - { 0x10DE1245, "GeForce GTS 450" }, - { 0x10DE1251, "N12E-GS-A1" }, -}; - -static uint16_t swap16(uint16_t x) -{ - return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8)); -} - -static uint16_t read16(uint8_t *ptr, uint16_t offset) -{ - uint8_t ret[2]; - - ret[0] = ptr[offset+1]; - ret[1] = ptr[offset]; - - return *((uint16_t*)&ret); -} - -#if 0 -static uint32_t swap32(uint32_t x) -{ - return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24); -} - -static uint8_t read8(uint8_t *ptr, uint16_t offset) -{ - return ptr[offset]; -} - -static uint32_t read32(uint8_t *ptr, uint16_t offset) -{ - uint8_t ret[4]; - - ret[0] = ptr[offset+3]; - ret[1] = ptr[offset+2]; - ret[2] = ptr[offset+1]; - ret[3] = ptr[offset]; - - return *((uint32_t*)&ret); -} -#endif - -static int patch_nvidia_rom(uint8_t *rom) -{ - if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) { - printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]); - return PATCH_ROM_FAILED; - } - - uint16_t dcbptr = swap16(read16(rom, 0x36)); - - if (!dcbptr) { - printf("no dcb table found\n"); - return PATCH_ROM_FAILED; - } -// else -// printf("dcb table at offset 0x%04x\n", dcbptr); - - uint8_t *dcbtable = &rom[dcbptr]; - uint8_t dcbtable_version = dcbtable[0]; - uint8_t headerlength = 0; - uint8_t numentries = 0; - uint8_t recordlength = 0; - - if (dcbtable_version >= 0x20) - { - uint32_t sig; - - if (dcbtable_version >= 0x30) - { - headerlength = dcbtable[1]; - numentries = dcbtable[2]; - recordlength = dcbtable[3]; - - sig = *(uint32_t *)&dcbtable[6]; - } - else - { - sig = *(uint32_t *)&dcbtable[4]; - headerlength = 8; - } - - if (sig != 0x4edcbdcb) - { - printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48 - return PATCH_ROM_FAILED; - } - } - else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */ - { - char sig[8] = { 0 }; - - strncpy(sig, (char *)&dcbtable[-7], 7); - recordlength = 10; - - if (strcmp(sig, "DEV_REC")) - { - printf("Bad Display Configuration Block signature (%s)\n", sig); - return PATCH_ROM_FAILED; - } - } - else - { - printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version); - return PATCH_ROM_FAILED; - } - - if (numentries >= MAX_NUM_DCB_ENTRIES) - numentries = MAX_NUM_DCB_ENTRIES; - - uint8_t num_outputs = 0, i = 0; - - struct dcbentry - { - uint8_t type; - uint8_t index; - uint8_t *heads; - } entries[numentries]; - - for (i = 0; i < numentries; i++) - { - uint32_t connection; - connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i]; - - /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */ - if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ - continue; - if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ - continue; - if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */ - continue; - - entries[num_outputs].type = connection & 0xf; - entries[num_outputs].index = num_outputs; - entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]); - } - - int has_lvds = false; - uint8_t channel1 = 0, channel2 = 0; - - for (i = 0; i < num_outputs; i++) - { - if (entries[i].type == 3) - { - has_lvds = true; - //printf("found LVDS\n"); - channel1 |= ( 0x1 << entries[i].index); - entries[i].type = TYPE_GROUPED; - } - } - - // if we have a LVDS output, we group the rest to the second channel - if (has_lvds) - { - for (i = 0; i < num_outputs; i++) - { - if (entries[i].type == TYPE_GROUPED) - continue; - - channel2 |= ( 0x1 << entries[i].index); - entries[i].type = TYPE_GROUPED; - } - } - else - { - int x; - // we loop twice as we need to generate two channels - for (x = 0; x <= 1; x++) - { - for (i=0; i channel2) - { - uint8_t buff = channel1; - channel1 = channel2; - channel2 = buff; - } - - default_NVCAP[6] = channel1; - default_NVCAP[8] = channel2; - - // patching HEADS - for (i = 0; i < num_outputs; i++) - { - if (channel1 & (1 << i)) - { - *entries[i].heads = 1; - } - else if(channel2 & (1 << i)) - { - *entries[i].heads = 2; - } - } - return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS); -} - -static char *get_nvidia_model(uint32_t id) -{ - int i; - - for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) { - if (NVKnownChipsets[i].device == id) - { - return NVKnownChipsets[i].name; - } - } - return NVKnownChipsets[0].name; -} - -static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize) -{ - int fd; - int size; - - if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) - { - return 0; - } - - size = file_size(fd); - - if (size > bufsize) - { - printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", - filename, bufsize); - size = bufsize; - } - size = read(fd, (char *)buf, size); - close(fd); - - return size > 0 ? size : 0; -} - -static int devprop_add_nvidia_template(struct DevPropDevice *device) -{ - char tmp[16]; - - if (!device) - return 0; - - if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0)) - return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0)) - return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_name_0)) - return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1)) - return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1)) - return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_name_1)) - return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_device_type)) - return 0; - - // Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0! - // len = sprintf(tmp, "Slot-%x", devices_number); - sprintf(tmp, "Slot-%x",devices_number); - devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp)); - devices_number++; - - return 1; -} - -int hex2bin(const char *hex, uint8_t *bin, int len) -{ - char *p; - int i; - char buf[3]; - - if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) { - printf("[ERROR] bin2hex input error\n"); - return -1; - } - - buf[2] = '\0'; - p = (char *) hex; - - for (i = 0; i < len; i++) - { - if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) { - printf("[ERROR] bin2hex '%s' syntax error\n", hex); - return -2; - } - buf[0] = *p++; - buf[1] = *p++; - bin[i] = (unsigned char) strtoul(buf, NULL, 16); - } - return 0; -} - -unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev) -{ - unsigned long long vram_size = 0; - - if (nvCardType < NV_ARCH_50) - { - vram_size = REG32(NV04_PFB_FIFO_DATA); - vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; - } - else if (nvCardType < NV_ARCH_C0) - { - vram_size = REG32(NV04_PFB_FIFO_DATA); - vram_size |= (vram_size & 0xff) << 32; - vram_size &= 0xffffffff00ll; - } - else // >= NV_ARCH_C0 - { - vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20; - vram_size *= REG32(NVC0_MEM_CTRLR_COUNT); - } - - // Workaround for GT 420/430 & 9600M GT - switch (nvda_dev->device_id) - { - case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430 - case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420 - case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT - default: break; - } - - return vram_size; -} - -bool setup_nvidia_devprop(pci_dt_t *nvda_dev) -{ - struct DevPropDevice *device; - char *devicepath; - option_rom_pci_header_t *rom_pci_header; - volatile uint8_t *regs; - uint8_t *rom; - uint8_t *nvRom; - uint8_t nvCardType; - unsigned long long videoRam; - uint32_t nvBiosOveride; - uint32_t bar[7]; - uint32_t boot_display; - int nvPatch; - int len; - char biosVersion[32]; - char nvFilename[32]; - char kNVCAP[12]; - char *model; - const char *value; - bool doit; - - devicepath = get_pci_dev_path(nvda_dev); - bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 ); - regs = (uint8_t *) (bar[0] & ~0x0f); - - // get card type - nvCardType = (REG32(0) >> 20) & 0x1ff; - - // Amount of VRAM in kilobytes - videoRam = mem_detect(regs, nvCardType, nvda_dev); - model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id); - - verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", - model, (uint32_t)(videoRam / 1024 / 1024), - (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id, - devicepath); - - rom = malloc(NVIDIA_ROM_SIZE); - sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, - (uint16_t)nvda_dev->device_id); - - if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit) - { - verbose("Looking for nvidia video bios file %s\n", nvFilename); - nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE); - - if (nvBiosOveride > 0) - { - verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride); - DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride); - } - else - { - printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename); - return false; - } - } - else - { - // Otherwise read bios from card - nvBiosOveride = 0; - - // TODO: we should really check for the signature before copying the rom, i think. - - // PRAMIN first - nvRom = (uint8_t*)®s[NV_PRAMIN_OFFSET]; - bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE); - - // Valid Signature ? - if (rom[0] != 0x55 && rom[1] != 0xaa) - { - // PROM next - // Enable PROM access - (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED; - - nvRom = (uint8_t*)®s[NV_PROM_OFFSET]; - bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE); - - // disable PROM access - (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; - - // Valid Signature ? - if (rom[0] != 0x55 && rom[1] != 0xaa) - { - // 0xC0000 last - bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE); - - // Valid Signature ? - if (rom[0] != 0x55 && rom[1] != 0xaa) - { - printf("ERROR: Unable to locate nVidia Video BIOS\n"); - return false; - } - else - { - DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); - } - } - else - { - DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); - } - } - else - { - DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); - } - } - - if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) { - printf("ERROR: nVidia ROM Patching Failed!\n"); - //return false; - } - - rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]); - - // check for 'PCIR' sig - if (rom_pci_header->signature == 0x50434952) - { - if (rom_pci_header->device_id != nvda_dev->device_id) - { - // Get Model from the OpROM - model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id); - } - else - { - printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature); - } - } - - if (!string) { - string = devprop_create_string(); - } - device = devprop_add_device(string, devicepath); - - /* FIXME: for primary graphics card only */ - boot_display = 1; - devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4); - - if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) { - uint8_t built_in = 0x01; - devprop_add_value(device, "@0,built-in", &built_in, 1); - } - - // get bios version - const int MAX_BIOS_VERSION_LENGTH = 32; - char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH); - - memset(version_str, 0, MAX_BIOS_VERSION_LENGTH); - - int i, version_start; - int crlf_count = 0; - - // only search the first 384 bytes - for (i = 0; i < 0x180; i++) - { - if (rom[i] == 0x0D && rom[i+1] == 0x0A) - { - crlf_count++; - // second 0x0D0A was found, extract bios version - if (crlf_count == 2) - { - if (rom[i-1] == 0x20) i--; // strip last " " - - for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) - { - // find start - if (rom[version_start] == 0x00) - { - version_start++; - - // strip "Version " - if (strncmp((const char*)rom+version_start, "Version ", 8) == 0) - { - version_start += 8; - } - - strncpy(version_str, (const char*)rom+version_start, i-version_start); - break; - } - } - break; - } - } - } - - sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str); - sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id); - - if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2) - { - uint8_t new_NVCAP[NVCAP_LEN]; - - if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) - { - verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath); - memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN); - } - } - - if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2) - { - uint8_t new_dcfg0[DCFG0_LEN]; - - if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0) - { - memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN); - - verbose("Using user supplied @0,display-cfg\n"); - printf("@0,display-cfg: %02x%02x%02x%02x\n", - default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]); - } - } - - if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2) - { - uint8_t new_dcfg1[DCFG1_LEN]; - - if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0) - { - memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN); - - verbose("Using user supplied @1,display-cfg\n"); - printf("@1,display-cfg: %02x%02x%02x%02x\n", - default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]); - } - } - -#if DEBUG_NVCAP - printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n", - default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3], - default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7], - default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11], - default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15], - default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]); -#endif - - devprop_add_nvidia_template(device); - devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN); - devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4); - devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1); - devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1); - devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN); - devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN); - - //add HDMI Audio back to nvidia - //http://forge.voodooprojects.org/p/chameleon/issues/67/ -// uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00}; -// devprop_add_value(device, "@1,connector-type",connector_type_1, 4); - //end Nvidia HDMI Audio - - if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit) - { - devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512)); - } - - stringdata = malloc(sizeof(uint8_t) * string->length); - memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); - stringlength = string->length; - - return true; -} Index: branches/ErmaC/i386/libsaio/ati.c =================================================================== --- branches/ErmaC/i386/libsaio/ati.c (revision 1567) +++ branches/ErmaC/i386/libsaio/ati.c (revision 1568) @@ -1,1451 +0,0 @@ -/* - * ATI Graphics Card Enabler, part of the Chameleon Boot Loader Project - * - * Copyright 2010 by Islam M. Ahmed Zaid. All rights reserved. - * - */ - -#include "boot.h" -#include "bootstruct.h" -#include "pci.h" -#include "platform.h" -#include "device_inject.h" -#include "ati_reg.h" - -#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x6e - -#define Reg32(reg) (*(volatile uint32_t *)(card->mmio + reg)) -#define RegRead32(reg) (Reg32(reg)) -#define RegWrite32(reg, value) (Reg32(reg) = value) - -typedef enum { - kNul, - kStr, - kPtr, - kCst -} type_t; - -typedef enum { - CHIP_FAMILY_UNKNOW, - /* IGP */ - CHIP_FAMILY_RS600, - CHIP_FAMILY_RS690, - CHIP_FAMILY_RS740, - CHIP_FAMILY_RS780, - CHIP_FAMILY_RS880, - /* R600 */ - CHIP_FAMILY_R600, - CHIP_FAMILY_RV610, - CHIP_FAMILY_RV620, - CHIP_FAMILY_RV630, - CHIP_FAMILY_RV635, - CHIP_FAMILY_RV670, - /* R700 */ - CHIP_FAMILY_RV710, - CHIP_FAMILY_RV730, - CHIP_FAMILY_RV740, - CHIP_FAMILY_RV770, - /* Evergreen */ - CHIP_FAMILY_CEDAR, - CHIP_FAMILY_CYPRESS, - CHIP_FAMILY_HEMLOCK, - CHIP_FAMILY_JUNIPER, - CHIP_FAMILY_REDWOOD, - /* Northern Islands */ - CHIP_FAMILY_BARTS, - CHIP_FAMILY_CAICOS, - CHIP_FAMILY_CAYMAN, - CHIP_FAMILY_TURKS, - CHIP_FAMILY_LAST -} chip_family_t; - -static const char *chip_family_name[] = { - "UNKNOW", - /* IGP */ - "RS600", - "RS690", - "RS740", - "RS780", - "RS880", - /* R600 */ - "R600", - "RV610", - "RV620", - "RV630", - "RV635", - "RV670", - /* R700 */ - "RV710", - "RV730", - "RV740", - "RV770", - /* Evergreen */ - "Cedar", - "Cypress", - "Hemlock", - "Juniper", - "Redwood", - /* Northern Islands */ - "Barts", - "Caicos", - "Cayman", - "Turks", - "" -}; - -typedef struct { - const char *name; - uint8_t ports; -} card_config_t; - -static card_config_t card_configs[] = { - {NULL, 0}, - {"Alopias", 2}, - {"Alouatta", 4}, - {"Baboon", 3}, - {"Cardinal", 2}, - {"Caretta", 1}, - {"Colobus", 2}, - {"Douc", 2}, - {"Eulemur", 3}, - {"Flicker", 3}, - {"Galago", 2}, - {"Gliff", 3}, - {"Hoolock", 3}, - {"Hypoprion", 2}, - {"Iago", 2}, - {"Kakapo", 3}, - {"Kipunji", 4}, - {"Lamna", 2}, - {"Langur", 3}, - {"Megalodon", 3}, - {"Motmot", 2}, - {"Nomascus", 5}, - {"Orangutan", 2}, - {"Peregrine", 2}, - {"Quail", 3}, - {"Raven", 3}, - {"Shrike", 3}, - {"Sphyrna", 1}, - {"Triakis", 2}, - {"Uakari", 4}, - {"Vervet", 4}, - {"Zonalis", 6}, - {"Pithecia", 3}, - {"Bulrushes", 6}, - {"Cattail", 4}, - {"Hydrilla", 5}, - {"Duckweed", 4}, - {"Fanwort", 4}, - {"Elodea", 5}, - {"Kudzu", 2}, - {"Gibba", 5}, - {"Lotus", 3}, - {"Ipomoea", 3}, - {"Mangabey", 2}, - {"Muskgrass", 4}, - {"Juncus", 4} -}; - -typedef enum { - kNull, - kAlopias, - kAlouatta, - kBaboon, - kCardinal, - kCaretta, - kColobus, - kDouc, - kEulemur, - kFlicker, - kGalago, - kGliff, - kHoolock, - kHypoprion, - kIago, - kKakapo, - kKipunji, - kLamna, - kLangur, - kMegalodon, - kMotmot, - kNomascus, - kOrangutan, - kPeregrine, - kQuail, - kRaven, - kShrike, - kSphyrna, - kTriakis, - kUakari, - kVervet, - kZonalis, - kPithecia, - kBulrushes, - kCattail, - kHydrilla, - kDuckweed, - kFanwort, - kElodea, - kKudzu, - kGibba, - kLotus, - kIpomoea, - kMangabey, - kMuskgrass, - kJuncus, - kCfgEnd -} config_name_t; - -typedef struct { - uint16_t device_id; - uint32_t subsys_id; - chip_family_t chip_family; - const char *model_name; - config_name_t cfg_name; -} radeon_card_info_t; - -static radeon_card_info_t radeon_cards[] = { - - // Earlier cards are not supported - // - // Layout is device_id, subsys_id (subsystem id plus vendor id), chip_family_name, display name, frame buffer - // Cards are grouped by device id and vendor id then sorted by subsystem id to make it easier to add new cards - // - { 0x9400, 0x25521002, CHIP_FAMILY_R600, "ATI Radeon HD 2900 XT", kNull }, - { 0x9400, 0x30001002, CHIP_FAMILY_R600, "ATI Radeon HD 2900 PRO", kNull }, - - { 0x9440, 0x24401682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, - { 0x9440, 0x24411682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, - { 0x9440, 0x24441682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, - { 0x9440, 0x24451682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, - - { 0x9441, 0x24401682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870 X2", kMotmot }, - - { 0x9442, 0x080110B0, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, - - { 0x9442, 0x24701682, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, - { 0x9442, 0x24711682, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, - - { 0x9442, 0xE104174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, - - { 0x944A, 0x30001043, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944A, 0x30001458, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944A, 0x30001462, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944A, 0x30001545, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944A, 0x30001682, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944A, 0x3000174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944A, 0x30001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944A, 0x300017AF, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x944C, 0x24801682, CHIP_FAMILY_RV770, "ATI Radeon HD 4830", kMotmot }, - { 0x944C, 0x24811682, CHIP_FAMILY_RV770, "ATI Radeon HD 4830", kMotmot }, - - { 0x944E, 0x3260174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 Series", kMotmot }, - { 0x944E, 0x3261174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 series", kMotmot }, - - { 0x944E, 0x30001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4730 Series", kMotmot }, - { 0x944E, 0x30101787, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 Series", kMotmot }, - { 0x944E, 0x31001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4820", kMotmot }, - - { 0x9480, 0x3628103C, CHIP_FAMILY_RV730, "ATI Radeon HD 4650M", kGliff }, - - { 0x9480, 0x9035104D, CHIP_FAMILY_RV730, "ATI Radeon HD 4650M", kGliff }, - - { 0x9490, 0x4710174B, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull }, - - { 0x9490, 0x20031787, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kFlicker }, - { 0x9490, 0x30501787, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull }, - - { 0x9490, 0x300017AF, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull }, - - { 0x9498, 0x21CF1458, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kNull }, - - { 0x9498, 0x24511682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull }, - { 0x9498, 0x24521682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull }, - { 0x9498, 0x24541682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull }, - { 0x9498, 0x29331682, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kNull }, - { 0x9498, 0x29341682, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kNull }, - - { 0x9498, 0x30501787, CHIP_FAMILY_RV730, "ATI Radeon HD 4700", kNull }, - { 0x9498, 0x31001787, CHIP_FAMILY_RV730, "ATI Radeon HD 4720", kNull }, - - { 0x94B3, 0x0D001002, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, - - { 0x94B3, 0x29001682, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, - - { 0x94B3, 0x1170174B, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, - - { 0x94C1, 0x0D021002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, - { 0x94C1, 0x10021002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Pro", kNull }, - - { 0x94C1, 0x0D021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, - - { 0x94C1, 0x21741458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, - - { 0x94C1, 0x10331462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, - { 0x94C1, 0x10401462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, - { 0x94C1, 0x11101462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, - - { 0x94C3, 0x03421002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - - { 0x94C3, 0x30001025, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, - - { 0x94C3, 0x03021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - { 0x94C3, 0x04021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - - { 0x94C3, 0x216A1458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - { 0x94C3, 0x21721458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - { 0x94C3, 0x30001458, CHIP_FAMILY_RV610, "ATI Radeon HD 3410", kNull }, - - { 0x94C3, 0x10321462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - { 0x94C3, 0x10411462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, - { 0x94C3, 0x11041462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, - { 0x94C3, 0x11051462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, - { 0x94C3, 0x30001462, CHIP_FAMILY_RV610, "ATI Radeon HD 3410", kNull }, - - { 0x94C3, 0x2247148C, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 LE", kNull }, - { 0x94C3, 0x3000148C, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, - - { 0x94C3, 0x3000174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, - { 0x94C3, 0xE370174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - { 0x94C3, 0xE400174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, - - { 0x94C3, 0x203817AF, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, - - { 0x94C3, 0x22471787, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 LE", kNull }, - { 0x94C3, 0x30001787, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, - - { 0x94C3, 0x01011A93, CHIP_FAMILY_RV610, "Qimonda Radeon HD 2400 PRO", kNull }, - - { 0x9501, 0x25421002, CHIP_FAMILY_RV670, "ATI Radeon HD 3870", kNull }, - { 0x9501, 0x30001002, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, - - { 0x9501, 0x3000174B, CHIP_FAMILY_RV670, "Sapphire Radeon HD 3690", kNull }, - { 0x9501, 0x4750174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, - - { 0x9501, 0x30001787, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, - - { 0x9505, 0x25421002, CHIP_FAMILY_RV670, "ATI Radeon HD 3850", kNull }, - { 0x9505, 0x30001002, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, - - { 0x9505, 0x30011043, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, - - { 0x9505, 0x3000148C, CHIP_FAMILY_RV670, "ATI Radeon HD 3850", kNull }, - { 0x9505, 0x3001148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, - { 0x9505, 0x3002148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, - { 0x9505, 0x3003148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, - { 0x9505, 0x3004148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, - - { 0x9505, 0x3000174B, CHIP_FAMILY_RV670, "Sapphire Radeon HD 3690", kNull }, - { 0x9505, 0x3001174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, - { 0x9505, 0x3010174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, - { 0x9505, 0x4730174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, - - { 0x9505, 0x30001787, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, - { 0x9505, 0x301017AF, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, - - { 0x9540, 0x4590174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4590", kNull }, - - { 0x9540, 0x30501787, CHIP_FAMILY_RV710, "ATI Radeon HD 4590", kNull }, - - { 0x954F, 0x29201682, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull }, - { 0x954F, 0x29211682, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull }, - { 0x954F, 0x30901682, CHIP_FAMILY_RV710, "XFX Radeon HD 4570", kNull }, - - { 0x954F, 0x30501787, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull }, - { 0x954F, 0x31001787, CHIP_FAMILY_RV710, "ATI Radeon HD 4520", kNull }, - - { 0x954F, 0x3000174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4520", kNull }, - { 0x954F, 0x4450174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull }, - { 0x954F, 0x4570174B, CHIP_FAMILY_RV710, "Sapphire Radeon HD 4570", kNull }, - { 0x954F, 0xE990174B, CHIP_FAMILY_RV710, "Sapphire Radeon HD 4350", kNull }, - - { 0x954F, 0x301017AF, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull }, - - { 0x9552, 0x04341028, CHIP_FAMILY_RV710, "ATI Mobility Radeon 4330", kShrike }, - - { 0x9552, 0x308B103C, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4300 Series", kShrike }, - - { 0x9552, 0x3000148C, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, - - { 0x9552, 0x3000174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, - - { 0x9552, 0x30001787, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, - - { 0x9552, 0x300017AF, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, - - { 0x9553, 0x18751043, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4570", kShrike }, - { 0x9553, 0x1B321043, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4570", kShrike }, - - { 0x9581, 0x95811002, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, - - { 0x9581, 0x3000148C, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, - - { 0x9583, 0x3000148C, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, - - { 0x9588, 0x01021A93, CHIP_FAMILY_RV630, "Qimonda Radeon HD 2600 XT", kNull }, - - { 0x9589, 0x30001462, CHIP_FAMILY_RV630, "ATI Radeon HD 3610", kNull }, - - { 0x9589, 0x0E41174B, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, - - { 0x9589, 0x30001787, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, - - { 0x9589, 0x01001A93, CHIP_FAMILY_RV630, "Qimonda Radeon HD 2600 PRO", kNull }, - - { 0x9591, 0x2303148C, CHIP_FAMILY_RV635, "ATI Radeon HD 3600 Series", kNull }, - - { 0x9598, 0xB3831002, CHIP_FAMILY_RV635, "ATI All-in-Wonder HD", kNull }, - - { 0x9598, 0x30001043, CHIP_FAMILY_RV635, "HD3730", kNull }, - { 0x9598, 0x30011043, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, - - { 0x9598, 0x3000148C, CHIP_FAMILY_RV635, "ATI Radeon HD 3730", kNull }, - { 0x9598, 0x3001148C, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull }, - { 0x9598, 0x3031148C, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, - - { 0x9598, 0x30001545, CHIP_FAMILY_RV635, "VisionTek Radeon HD 2600 XT", kNull }, - { 0x9598, 0x30011545, CHIP_FAMILY_RV635, "VisionTek Radeon HD 2600 Pro", kNull }, - - { 0x9598, 0x3000174B, CHIP_FAMILY_RV635, "Sapphire Radeon HD 3730", kNull }, - { 0x9598, 0x3001174B, CHIP_FAMILY_RV635, "Sapphire Radeon HD 3750", kNull }, - { 0x9598, 0x4570174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, - { 0x9598, 0x4580174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull }, - { 0x9598, 0x4610174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4610", kNull }, - - { 0x9598, 0x300117AF, CHIP_FAMILY_RV635, "ATI Radeon HD 3750", kNull }, - { 0x9598, 0x301017AF, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, - { 0x9598, 0x301117AF, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull }, - - { 0x9598, 0x30501787, CHIP_FAMILY_RV635, "ATI Radeon HD 4610", kNull }, - - { 0x95C0, 0x3000148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull }, - - { 0x95C0, 0xE3901745, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull }, - - { 0x95C0, 0x3000174B, CHIP_FAMILY_RV620, "Sapphire Radeon HD 3550", kNull }, - { 0x95C0, 0x3002174B, CHIP_FAMILY_RV620, "ATI Radeon HD 3570", kNull }, - { 0x95C0, 0x3020174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, - - { 0x95C5, 0x3000148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3450", kNull }, - { 0x95C5, 0x3001148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull }, - { 0x95C5, 0x3002148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull }, - { 0x95C5, 0x3003148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, - { 0x95C5, 0x3032148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, - { 0x95C5, 0x3033148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull }, - - { 0x95C5, 0x3010174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, - { 0x95C5, 0x4250174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, - - { 0x95C5, 0x30501787, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, - - { 0x95C5, 0x301017AF, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull }, - - { 0x95C5, 0x01041A93, CHIP_FAMILY_RV620, "Qimonda Radeon HD 3450", kNull }, - { 0x95C5, 0x01051A93, CHIP_FAMILY_RV620, "Qimonda Radeon HD 3450", kNull }, - - /* Evergreen */ - { 0x6898, 0x0B001002, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kZonalis }, - - { 0x6898, 0x032E1043, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari }, - - { 0x6898, 0x00D0106B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kLangur }, - - { 0x6898, 0xE140174B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari }, - - { 0x6898, 0x29611682, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari }, - - { 0x6899, 0x21E41458, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, - - { 0x6899, 0xE140174B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, - - { 0x6899, 0x200A1787, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, - { 0x6899, 0x22901787, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, - - { 0x689C, 0x03521043, CHIP_FAMILY_HEMLOCK, "ASUS ARES", kUakari }, - { 0x689C, 0x039E1043, CHIP_FAMILY_HEMLOCK, "ASUS EAH5870 Series", kUakari }, - - { 0x689C, 0x30201682, CHIP_FAMILY_HEMLOCK, "ATI Radeon HD 5970", kUakari }, - - { 0x68A1, 0x144D103C, CHIP_FAMILY_CYPRESS, "ATI Mobility Radeon HD 5850", kNomascus }, - { 0x68A1, 0x1522103C, CHIP_FAMILY_CYPRESS, "ATI Mobility Radeon HD 5850", kHoolock }, - - { 0x68A8, 0x050E1025, CHIP_FAMILY_CYPRESS, "AMD Radeon HD 6850M", kUakari }, - - { 0x68B8, 0x00CF106B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kHoolock }, - - { 0x68B8, 0x29901682, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, - { 0x68B8, 0x29911682, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, - - { 0x68B8, 0x1482174B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, - { 0x68B8, 0xE147174B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, - - { 0x68B8, 0x21D71458, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, - - { 0x68B8, 0x200B1787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, - { 0x68B8, 0x22881787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, - - { 0x68BF, 0x220E1458, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 6750", kVervet }, - - { 0x68C0, 0x1594103C, CHIP_FAMILY_REDWOOD, "AMD Radeon HD 6570M", kNull }, - - { 0x68C0, 0x392717AA, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5730", kNull }, - - { 0x68C1, 0x033E1025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5650", kNull }, - { 0x68C1, 0x9071104D, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5650", kEulemur }, - - { 0x68C8, 0x2306103C, CHIP_FAMILY_REDWOOD, "ATI FirePro V4800 (FireGL)", kNull }, - - { 0x68D8, 0x03561043, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon }, - - { 0x68D8, 0x21D91458, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon }, - - { 0x68D8, 0x5690174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5690", kNull }, - { 0x68D8, 0x5730174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull }, - { 0x68D8, 0xE151174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon }, - - { 0x68D8, 0x30001787, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull }, - - { 0x68D8, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull }, - { 0x68D8, 0x301117AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5690", kNull }, - - { 0x68D9, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, - - { 0x68DA, 0x5630174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, - - { 0x68DA, 0x30001787, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, - - { 0x68DA, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, - - { 0x68E0, 0x04561028, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470M", kEulemur }, - - { 0x68E0, 0x1433103C, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470M", kEulemur }, - - { 0x68E1, 0x1426103C, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5430M", kEulemur }, - - { 0x68F9, 0x5470174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, - { 0x68F9, 0x5490174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull }, - { 0x68F9, 0x5530174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5530", kNull }, - - { 0x68F9, 0x20091787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur }, - { 0x68F9, 0x22911787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur }, - { 0x68F9, 0x30001787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, - { 0x68F9, 0x30011787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5530", kNull }, - { 0x68F9, 0x30021787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull }, - - { 0x68F9, 0x301117AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, - { 0x68F9, 0x301217AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull }, - { 0x68F9, 0x301317AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, - - /* Northen Islands */ - { 0x6718, 0x0B001002, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull }, - { 0x6718, 0x67181002, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull }, - - { 0x6718, 0x31301682, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull }, - - { 0x6738, 0x00D01002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - { 0x6738, 0x21FA1002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - { 0x6738, 0x67381002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - - { 0x6738, 0x21FA1458, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - - { 0x6738, 0x31031682, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - { 0x6738, 0x31041682, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - - { 0x6738, 0xE178174B, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - - { 0x6738, 0x20101787, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - { 0x6738, 0x23051787, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, - - { 0x6739, 0x67391002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed }, - - { 0x6739, 0x21F81458, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed }, - - { 0x6739, 0x24411462, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed }, - - { 0x6739, 0xE177174B, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed }, - - { 0x6740, 0x1657103C, CHIP_FAMILY_TURKS, "AMD Radeon HD 6770M", kNull }, - - { 0x6741, 0x050E1025, CHIP_FAMILY_TURKS, "AMD Radeon HD 6650M", kNull }, - { 0x6741, 0x05131025, CHIP_FAMILY_TURKS, "AMD Radeon HD 6650M", kNull }, - { 0x6741, 0x1646103C, CHIP_FAMILY_TURKS, "AMD Radeon HD 6750M", kNull }, - { 0x6741, 0x9080104D, CHIP_FAMILY_TURKS, "AMD Radeon HD 6630M", kNull }, - - { 0x6758, 0x67581002, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes }, - - { 0x6758, 0x22051458, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes }, - - { 0x6758, 0x31811682, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes }, - { 0x6758, 0x31831682, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes }, - - { 0x6758, 0xE1941746, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes }, - - { 0x6759, 0xE193174B, CHIP_FAMILY_TURKS, "AMD Radeon HD 6570", kNull }, - - { 0x6760, 0x04CC1028, CHIP_FAMILY_RV730, "AMD Radeon HD 6490M", kNull }, - { 0x6760, 0x1CB21043, CHIP_FAMILY_RV730, "AMD Radeon HD 6470M", kNull }, - - { 0x6760, 0x1656103C, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6490M", kNull }, // ErmaC no tested - - { 0x6779, 0x64501092, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450", kBulrushes }, - - { 0x6779, 0xE164174B, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450", kBulrushes }, - - /* standard/default models */ - { 0x9400, 0x00000000, CHIP_FAMILY_R600, "ATI Radeon HD 2900 XT", kNull }, - { 0x9405, 0x00000000, CHIP_FAMILY_R600, "ATI Radeon HD 2900 GT", kNull }, - - { 0x9440, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - { 0x9441, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4870 X2", kMotmot }, - { 0x9442, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - { 0x9443, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4850 X2", kMotmot }, - { 0x944C, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - { 0x944E, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4700 Series", kMotmot }, - - { 0x9450, 0x00000000, CHIP_FAMILY_RV770, "AMD FireStream 9270", kMotmot }, - { 0x9452, 0x00000000, CHIP_FAMILY_RV770, "AMD FireStream 9250", kMotmot }, - - { 0x9460, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - { 0x9462, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, - - { 0x9490, 0x00000000, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kFlicker }, - { 0x9498, 0x00000000, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kFlicker }, - - { 0x94B3, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, - { 0x94B4, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4700 Series", kFlicker }, - { 0x94B5, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, - - { 0x94C1, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago }, - { 0x94C3, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago }, - { 0x94C7, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2350", kIago }, - { 0x94CC, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago }, - - { 0x9501, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3800 Series", kMegalodon }, - { 0x9505, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3800 Series", kMegalodon }, - { 0x9507, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3830", kMegalodon }, - { 0x950F, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3870 X2", kMegalodon }, - - { 0x9513, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3850 X2", kMegalodon }, - { 0x9519, 0x00000000, CHIP_FAMILY_RV670, "AMD FireStream 9170", kMegalodon }, - - { 0x9540, 0x00000000, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull }, - { 0x954F, 0x00000000, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, - - { 0x9553, 0x00000000, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4500/5100 Series", kShrike }, - - { 0x9588, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 XT", kLamna }, - { 0x9589, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 PRO", kLamna }, - { 0x958A, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 X2 Series", kLamna }, - - { 0x9598, 0x00000000, CHIP_FAMILY_RV635, "ATI Radeon HD 3600 Series", kMegalodon }, - - { 0x95C0, 0x00000000, CHIP_FAMILY_RV620, "ATI Radeon HD 3400 Series", kIago }, - { 0x95C5, 0x00000000, CHIP_FAMILY_RV620, "ATI Radeon HD 3400 Series", kIago }, - - /* IGP */ - { 0x9610, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon HD 3200 Graphics", kNull }, - { 0x9611, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon 3100 Graphics", kNull }, - { 0x9614, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon HD 3300 Graphics", kNull }, - { 0x9616, 0x00000000, CHIP_FAMILY_RS780, "AMD 760G", kNull }, - - { 0x9710, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4200", kNull }, - { 0x9715, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4250", kNull }, - { 0x9714, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4290", kNull }, - - /* Evergreen */ - { 0x688D, 0x00000000, CHIP_FAMILY_CYPRESS, "AMD FireStream 9350", kUakari }, - - { 0x6898, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari }, - { 0x6899, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari }, - { 0x689C, 0x00000000, CHIP_FAMILY_HEMLOCK, "ATI Radeon HD 5900 Series", kUakari }, - { 0x689E, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari }, - - { 0x68B8, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5700 Series", kVervet }, - { 0x68B9, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5600 Series", kVervet }, - { 0x68BE, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5700 Series", kVervet }, - - { 0x68D8, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5600 Series", kBaboon }, - { 0x68D9, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5500 Series", kBaboon }, - { 0x68DA, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5500 Series", kBaboon }, - - { 0x68F9, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5400 Series", kNull }, - - /* Northen Islands */ - { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970 Series", kNull }, - { 0x6719, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950 Series", kNull }, - - { 0x6738, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870 Series", kDuckweed }, - { 0x6739, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850 Series", kDuckweed }, - { 0x673E, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6790 Series", kNull }, - - { 0x6740, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6700M Series", kNull }, - { 0x6741, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6600/6700M Series", kNull }, - - { 0x6758, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670 Series", kNull }, - { 0x6759, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6500 Series", kNull }, - - { 0x6760, 0x00000000, CHIP_FAMILY_RV730, "AMD Radeon HD 6470M", kNull }, - - { 0x6770, 0x00000000, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6400 Series", kNull }, - { 0x6779, 0x00000000, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450 Series", kNull }, - - { 0x0000, 0x00000000, CHIP_FAMILY_UNKNOW, NULL, kNull } -}; - -typedef struct { - struct DevPropDevice *device; - radeon_card_info_t *info; - pci_dt_t *pci_dev; - uint8_t *fb; - uint8_t *mmio; - uint8_t *io; - uint8_t *rom; - uint32_t rom_size; - uint32_t vram_size; - const char *cfg_name; - uint8_t ports; - uint32_t flags; - bool posted; -} card_t; -card_t *card; - -/* Flags */ -#define MKFLAG(n) (1 << n) -#define FLAGTRUE MKFLAG(0) -#define EVERGREEN MKFLAG(1) - -//static uint8_t atN = 0; - -typedef struct { - type_t type; - uint32_t size; - uint8_t *data; -} value_t; - -static value_t aty_name; -static value_t aty_nameparent; -//static value_t aty_model; - -#define DATVAL(x) {kPtr, sizeof(x), (uint8_t *)x} -#define STRVAL(x) {kStr, sizeof(x), (uint8_t *)x} -#define BYTVAL(x) {kCst, 1, (uint8_t *)x} -#define WRDVAL(x) {kCst, 2, (uint8_t *)x} -#define DWRVAL(x) {kCst, 4, (uint8_t *)x} -#define QWRVAL(x) {kCst, 8, (uint8_t *)x} -#define NULVAL {kNul, 0, (uint8_t *)NULL} - -bool get_bootdisplay_val(value_t *val); -bool get_vrammemory_val(value_t *val); -bool get_name_val(value_t *val); -bool get_nameparent_val(value_t *val); -bool get_model_val(value_t *val); -bool get_conntype_val(value_t *val); -bool get_vrammemsize_val(value_t *val); -bool get_binimage_val(value_t *val); -bool get_romrevision_val(value_t *val); -bool get_deviceid_val(value_t *val); -bool get_mclk_val(value_t *val); -bool get_sclk_val(value_t *val); -bool get_refclk_val(value_t *val); -bool get_platforminfo_val(value_t *val); -bool get_vramtotalsize_val(value_t *val); - -typedef struct { - uint32_t flags; - bool all_ports; - char *name; - bool (*get_value)(value_t *val); - value_t default_val; -} dev_prop_t; - -dev_prop_t ati_devprop_list[] = { - {FLAGTRUE, false, "@0,AAPL,boot-display", get_bootdisplay_val, NULVAL }, -// {FLAGTRUE, false, "@0,ATY,EFIDisplay", NULL, STRVAL("TMDSA") }, - -// {FLAGTRUE, true, "@0,AAPL,vram-memory", get_vrammemory_val, NULVAL }, -// {FLAGTRUE, true, "@0,compatible", get_name_val, NULVAL }, -// {FLAGTRUE, true, "@0,connector-type", get_conntype_val, NULVAL }, -// {FLAGTRUE, true, "@0,device_type", NULL, STRVAL("display") }, -// {FLAGTRUE, false, "@0,display-connect-flags", NULL, DWRVAL((uint32_t)0) }, -// {FLAGTRUE, true, "@0,display-type", NULL, STRVAL("NONE") }, - {FLAGTRUE, true, "@0,name", get_name_val, NULVAL }, -// {FLAGTRUE, true, "@0,VRAM,memsize", get_vrammemsize_val, NULVAL }, - -// {FLAGTRUE, false, "AAPL,aux-power-connected", NULL, DWRVAL((uint32_t)1) }, -// {FLAGTRUE, false, "AAPL,backlight-control", NULL, DWRVAL((uint32_t)0) }, - {FLAGTRUE, false, "ATY,bin_image", get_binimage_val, NULVAL }, - {FLAGTRUE, false, "ATY,Copyright", NULL, STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010") }, - {FLAGTRUE, false, "ATY,Card#", get_romrevision_val, NULVAL }, - {FLAGTRUE, false, "ATY,VendorID", NULL, WRDVAL((uint16_t)0x1002) }, - {FLAGTRUE, false, "ATY,DeviceID", get_deviceid_val, NULVAL }, - -// {FLAGTRUE, false, "ATY,MCLK", get_mclk_val, NULVAL }, -// {FLAGTRUE, false, "ATY,SCLK", get_sclk_val, NULVAL }, -// {FLAGTRUE, false, "ATY,RefCLK", get_refclk_val, DWRVAL((uint32_t)0x0a8c) }, - -// {FLAGTRUE, false, "ATY,PlatformInfo", get_platforminfo_val, NULVAL }, - - {FLAGTRUE, false, "name", get_nameparent_val, NULVAL }, - {FLAGTRUE, false, "device_type", get_nameparent_val, NULVAL }, - {FLAGTRUE, false, "model", get_model_val, STRVAL("ATI Radeon") }, -// {FLAGTRUE, false, "VRAM,totalsize", get_vramtotalsize_val, NULVAL }, - - {FLAGTRUE, false, NULL, NULL, NULVAL } -}; - -bool get_bootdisplay_val(value_t *val) -{ - static uint32_t v = 0; - - if (v) - return false; - - if (!card->posted) - return false; - - v = 1; - val->type = kCst; - val->size = 4; - val->data = (uint8_t *)&v; - - return true; -} - -bool get_vrammemory_val(value_t *val) -{ - return false; -} - -bool get_name_val(value_t *val) -{ - val->type = aty_name.type; - val->size = aty_name.size; - val->data = aty_name.data; - - return true; -} - -bool get_nameparent_val(value_t *val) -{ - val->type = aty_nameparent.type; - val->size = aty_nameparent.size; - val->data = aty_nameparent.data; - - return true; -} - -bool get_model_val(value_t *val) -{ - if (!card->info->model_name) - return false; - - val->type = kStr; - val->size = strlen(card->info->model_name) + 1; - val->data = (uint8_t *)card->info->model_name; - - return true; -} - -bool get_conntype_val(value_t *val) -{ -//Connector types: -//0x4 : DisplayPort -//0x400: DL DVI-I -//0x800: HDMI - - return false; -} - -bool get_vrammemsize_val(value_t *val) -{ - static int idx = -1; - static uint64_t memsize; - - idx++; - memsize = ((uint64_t)card->vram_size << 32); - if (idx == 0) - memsize = memsize | (uint64_t)card->vram_size; - - val->type = kCst; - val->size = 8; - val->data = (uint8_t *)&memsize; - - return true; -} - -bool get_binimage_val(value_t *val) -{ - if (!card->rom) - return false; - - val->type = kPtr; - val->size = card->rom_size; - val->data = card->rom; - - return true; -} - -bool get_romrevision_val(value_t *val) -{ - uint8_t *rev; - if (!card->rom) - return false; - - rev = card->rom + *(uint8_t *)(card->rom + OFFSET_TO_GET_ATOMBIOS_STRINGS_START); - - val->type = kPtr; - val->size = strlen((char *)rev); - val->data = malloc(val->size); - - if (!val->data) - return false; - - memcpy(val->data, rev, val->size); - - return true; -} - -bool get_deviceid_val(value_t *val) -{ - val->type = kCst; - val->size = 2; - val->data = (uint8_t *)&card->pci_dev->device_id; - - return true; -} - -bool get_mclk_val(value_t *val) -{ - return false; -} - -bool get_sclk_val(value_t *val) -{ - return false; -} - -bool get_refclk_val(value_t *val) -{ - return false; -} - -bool get_platforminfo_val(value_t *val) -{ - val->data = malloc(0x80); - if (!val->data) - return false; - - bzero(val->data, 0x80); - - val->type = kPtr; - val->size = 0x80; - val->data[0] = 1; - - return true; -} - -bool get_vramtotalsize_val(value_t *val) -{ - val->type = kCst; - val->size = 4; - val->data = (uint8_t *)&card->vram_size; - - return true; -} - -void free_val(value_t *val) -{ - if (val->type == kPtr) - free(val->data); - - bzero(val, sizeof(value_t)); -} - -void devprop_add_list(dev_prop_t devprop_list[]) -{ - value_t *val = malloc(sizeof(value_t)); - int i, pnum; - - for (i = 0; devprop_list[i].name != NULL; i++) - { - if ((devprop_list[i].flags == FLAGTRUE) || (devprop_list[i].flags | card->flags)) - { - if (devprop_list[i].get_value && devprop_list[i].get_value(val)) - { - devprop_add_value(card->device, devprop_list[i].name, val->data, val->size); - free_val(val); - - if (devprop_list[i].all_ports) - { - for (pnum = 1; pnum < card->ports; pnum++) - { - if (devprop_list[i].get_value(val)) - { - devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii - devprop_add_value(card->device, devprop_list[i].name, val->data, val->size); - free_val(val); - } - } - devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card - } - } - else - { - if (devprop_list[i].default_val.type != kNul) - { - devprop_add_value(card->device, devprop_list[i].name, - devprop_list[i].default_val.type == kCst ? - (uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, - devprop_list[i].default_val.size); - } - - if (devprop_list[i].all_ports) - { - for (pnum = 1; pnum < card->ports; pnum++) - { - if (devprop_list[i].default_val.type != kNul) - { - devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii - devprop_add_value(card->device, devprop_list[i].name, - devprop_list[i].default_val.type == kCst ? - (uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, - devprop_list[i].default_val.size); - } - } - devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card - } - } - } - } - - free(val); -} - -bool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev) -{ - option_rom_pci_header_t *rom_pci_header; - - if (rom_header->signature != 0xaa55) - return false; - - rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset); - - if (rom_pci_header->signature != 0x52494350) - return false; - - if (rom_pci_header->vendor_id != pci_dev->vendor_id || rom_pci_header->device_id != pci_dev->device_id) - return false; - - return true; -} - -bool load_vbios_file(const char *key, uint16_t vendor_id, uint16_t device_id, uint32_t subsys_id) -{ - int fd; - char file_name[24]; - bool do_load = false; - - getBoolForKey(key, &do_load, &bootInfo->chameleonConfig); - if (!do_load) - return false; - - sprintf(file_name, "/Extra/%04x_%04x_%08x.rom", vendor_id, device_id, subsys_id); - if ((fd = open_bvdev("bt(0,0)", file_name, 0)) < 0) - return false; - - card->rom_size = file_size(fd); - card->rom = malloc(card->rom_size); - if (!card->rom) - return false; - - read(fd, (char *)card->rom, card->rom_size); - - if (!validate_rom((option_rom_header_t *)card->rom, card->pci_dev)) - { - card->rom_size = 0; - card->rom = 0; - return false; - } - - card->rom_size = ((option_rom_header_t *)card->rom)->rom_size * 512; - - close(fd); - - return true; -} - -void get_vram_size(void) -{ - chip_family_t chip_family = card->info->chip_family; - - card->vram_size = 0; - - if (chip_family >= CHIP_FAMILY_CEDAR) - // size in MB on evergreen - // XXX watch for overflow!!! - card->vram_size = RegRead32(R600_CONFIG_MEMSIZE) * 1024 * 1024; - else - if (chip_family >= CHIP_FAMILY_R600) - card->vram_size = RegRead32(R600_CONFIG_MEMSIZE); -} - -bool read_vbios(bool from_pci) -{ - option_rom_header_t *rom_addr; - - if (from_pci) - { - rom_addr = (option_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff); - verbose(" @0x%x", rom_addr); - } - else - rom_addr = (option_rom_header_t *)0xc0000; - - if (!validate_rom(rom_addr, card->pci_dev)) - return false; - - card->rom_size = rom_addr->rom_size * 512; - if (!card->rom_size) - return false; - - card->rom = malloc(card->rom_size); - if (!card->rom) - return false; - - memcpy(card->rom, (void *)rom_addr, card->rom_size); - - return true; -} - -bool read_disabled_vbios(void) -{ - bool ret = false; - chip_family_t chip_family = card->info->chip_family; - - if (chip_family >= CHIP_FAMILY_RV770) - { - uint32_t viph_control = RegRead32(RADEON_VIPH_CONTROL); - uint32_t bus_cntl = RegRead32(RADEON_BUS_CNTL); - uint32_t d1vga_control = RegRead32(AVIVO_D1VGA_CONTROL); - uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL); - uint32_t vga_render_control = RegRead32(AVIVO_VGA_RENDER_CONTROL); - uint32_t rom_cntl = RegRead32(R600_ROM_CNTL); - uint32_t cg_spll_func_cntl = 0; - uint32_t cg_spll_status; - - // disable VIP - RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); - - // enable the rom - RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); - - // Disable VGA mode - RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); - RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); - RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); - - if (chip_family == CHIP_FAMILY_RV730) - { - cg_spll_func_cntl = RegRead32(R600_CG_SPLL_FUNC_CNTL); - - // enable bypass mode - RegWrite32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN)); - - // wait for SPLL_CHG_STATUS to change to 1 - cg_spll_status = 0; - while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) - cg_spll_status = RegRead32(R600_CG_SPLL_STATUS); - - RegWrite32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); - } - else - RegWrite32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); - - ret = read_vbios(true); - - // restore regs - if (chip_family == CHIP_FAMILY_RV730) - { - RegWrite32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); - - // wait for SPLL_CHG_STATUS to change to 1 - cg_spll_status = 0; - while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) - cg_spll_status = RegRead32(R600_CG_SPLL_STATUS); - } - RegWrite32(RADEON_VIPH_CONTROL, viph_control); - RegWrite32(RADEON_BUS_CNTL, bus_cntl); - RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control); - RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control); - RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); - RegWrite32(R600_ROM_CNTL, rom_cntl); - } - else - if (chip_family >= CHIP_FAMILY_R600) - { - uint32_t viph_control = RegRead32(RADEON_VIPH_CONTROL); - uint32_t bus_cntl = RegRead32(RADEON_BUS_CNTL); - uint32_t d1vga_control = RegRead32(AVIVO_D1VGA_CONTROL); - uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL); - uint32_t vga_render_control = RegRead32(AVIVO_VGA_RENDER_CONTROL); - uint32_t rom_cntl = RegRead32(R600_ROM_CNTL); - uint32_t general_pwrmgt = RegRead32(R600_GENERAL_PWRMGT); - uint32_t low_vid_lower_gpio_cntl = RegRead32(R600_LOW_VID_LOWER_GPIO_CNTL); - uint32_t medium_vid_lower_gpio_cntl = RegRead32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); - uint32_t high_vid_lower_gpio_cntl = RegRead32(R600_HIGH_VID_LOWER_GPIO_CNTL); - uint32_t ctxsw_vid_lower_gpio_cntl = RegRead32(R600_CTXSW_VID_LOWER_GPIO_CNTL); - uint32_t lower_gpio_enable = RegRead32(R600_LOWER_GPIO_ENABLE); - - // disable VIP - RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); - - // enable the rom - RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); - - // Disable VGA mode - RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); - RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); - RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); - RegWrite32(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | R600_SCK_OVERWRITE)); - RegWrite32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); - RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); - RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); - RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); - RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); - RegWrite32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); - - ret = read_vbios(true); - - // restore regs - RegWrite32(RADEON_VIPH_CONTROL, viph_control); - RegWrite32(RADEON_BUS_CNTL, bus_cntl); - RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control); - RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control); - RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); - RegWrite32(R600_ROM_CNTL, rom_cntl); - RegWrite32(R600_GENERAL_PWRMGT, general_pwrmgt); - RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); - RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); - RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); - RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); - RegWrite32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); - } - - return ret; -} - -bool radeon_card_posted(void) -{ - uint32_t reg; - - // first check CRTCs - reg = RegRead32(RADEON_CRTC_GEN_CNTL) | RegRead32(RADEON_CRTC2_GEN_CNTL); - if (reg & RADEON_CRTC_EN) - return true; - - // then check MEM_SIZE, in case something turned the crtcs off - reg = RegRead32(R600_CONFIG_MEMSIZE); - if (reg) - return true; - - return false; -} - -#if 0 -bool devprop_add_pci_config_space(void) -{ - int offset; - - uint8_t *config_space = malloc(0x100); - if (!config_space) - return false; - - for (offset = 0; offset < 0x100; offset += 4) - config_space[offset / 4] = pci_config_read32(card->pci_dev->dev.addr, offset); - - devprop_add_value(card->device, "ATY,PCIConfigSpace", config_space, 0x100); - free(config_space); - - return true; -} -#endif - -static bool init_card(pci_dt_t *pci_dev) -{ - bool add_vbios = true; - char name[24]; - char name_parent[24]; - int i; - int n_ports = 0; - - card = malloc(sizeof(card_t)); - if (!card) - return false; - bzero(card, sizeof(card_t)); - - card->pci_dev = pci_dev; - - for (i = 0; radeon_cards[i].device_id ; i++) - { - if (radeon_cards[i].device_id == pci_dev->device_id) - { - card->info = &radeon_cards[i]; - if ((radeon_cards[i].subsys_id == 0x00000000) || - (radeon_cards[i].subsys_id == pci_dev->subsys_id.subsys_id)) - break; - } - } - - if (!card->info->device_id || !card->info->cfg_name) - { - printf("Unsupported card!\n"); - return false; - } - - card->fb = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_0) & ~0x0f); - card->mmio = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f); - card->io = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03); - - verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n", - card->fb, card->mmio, card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS)); - - card->posted = radeon_card_posted(); - verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed"); - - get_vram_size(); - - getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->chameleonConfig); - - if (add_vbios) - { - if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id)) - { - verbose("reading VBIOS from %s", card->posted ? "legacy space" : "PCI ROM"); - if (card->posted) - read_vbios(false); - else - read_disabled_vbios(); - verbose("\n"); - } - } - -// card->ports = 2; // default - Azi: default is card_configs - - if (card->info->chip_family >= CHIP_FAMILY_CEDAR) - { - card->flags |= EVERGREEN; -// card->ports = 3; //Azi: use the AtiPorts key if needed - } - -// atN = 0; - - // Check AtiConfig key for a framebuffer name, - card->cfg_name = getStringForKey(kAtiConfig, &bootInfo->chameleonConfig); - // if none, - if (!card->cfg_name) - { - // use cfg_name on radeon_cards, to retrive the default name from card_configs, - card->cfg_name = card_configs[card->info->cfg_name].name; - // and leave ports alone! -// card->ports = card_configs[card->info->cfg_name].ports; - - // which means one of the fb's or kNull - verbose("Framebuffer set to device's default: %s\n", card->cfg_name); - } - else - { - // else, use the fb name returned by AtiConfig. - verbose("(AtiConfig) Framebuffer set to: %s\n", card->cfg_name); - } - - // Check AtiPorts key for nr of ports, - card->ports = getIntForKey(kAtiPorts, &n_ports, &bootInfo->chameleonConfig); - // if a value bigger than 0 ?? is found, (do we need >= 0 ?? that's null FB on card_configs) - if (n_ports > 0) - { - card->ports = n_ports; // use it. - verbose("(AtiPorts) Nr of ports set to: %d\n", card->ports); - } - else// if (card->cfg_name > 0) // do we want 0 ports if fb is kNull or mistyped ? - { - // else, match cfg_name with card_configs list and retrive default nr of ports. - for (i = 0; i < kCfgEnd; i++) - if (strcmp(card->cfg_name, card_configs[i].name) == 0) - card->ports = card_configs[i].ports; // default - - verbose("Nr of ports set to framebuffer's default: %d\n", card->ports); - } -// else -// card->ports = 2/1 ?; // set a min if 0 ports ? -// verbose("Nr of ports set to min: %d\n", card->ports); - - sprintf(name, "ATY,%s", card->cfg_name); - aty_name.type = kStr; - aty_name.size = strlen(name) + 1; - aty_name.data = (uint8_t *)name; - - sprintf(name_parent, "ATY,%sParent", card->cfg_name); - aty_nameparent.type = kStr; - aty_nameparent.size = strlen(name_parent) + 1; - aty_nameparent.data = (uint8_t *)name_parent; - - return true; -} - -bool setup_ati_devprop(pci_dt_t *ati_dev) -{ - char *devicepath; - - if (!init_card(ati_dev)) - return false; - - // ------------------------------------------------- - // Find a better way to do this (in device_inject.c) - if (!string) - string = devprop_create_string(); - - devicepath = get_pci_dev_path(ati_dev); - card->device = devprop_add_device(string, devicepath); - if (!card->device) - return false; - // ------------------------------------------------- - -#if 0 - uint64_t fb = (uint32_t)card->fb; - uint64_t mmio = (uint32_t)card->mmio; - uint64_t io = (uint32_t)card->io; - devprop_add_value(card->device, "ATY,FrameBufferOffset", &fb, 8); - devprop_add_value(card->device, "ATY,RegisterSpaceOffset", &mmio, 8); - devprop_add_value(card->device, "ATY,IOSpaceOffset", &io, 8); -#endif - - devprop_add_list(ati_devprop_list); - - // ------------------------------------------------- - // Find a better way to do this (in device_inject.c) - //Azi: XXX tried to fix a malloc error in vain; this is related to XCode 4 compilation! - stringdata = malloc(sizeof(uint8_t) * string->length); - memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); - stringlength = string->length; - // ------------------------------------------------- - - verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n", - chip_family_name[card->info->chip_family], card->info->model_name, - (uint32_t)(card->vram_size / (1024 * 1024)), card->cfg_name, - ati_dev->vendor_id, ati_dev->device_id, - ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id, - devicepath); - - free(card); - - return true; -} Index: branches/ErmaC/i386/libsaio/nvidia.h =================================================================== --- branches/ErmaC/i386/libsaio/nvidia.h (revision 1567) +++ branches/ErmaC/i386/libsaio/nvidia.h (revision 1568) @@ -1,135 +0,0 @@ -/* - * NVidia injector - * - * Copyright (C) 2009 Jasmin Fazlic, iNDi - * - * NVidia injector is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * NVidia driver and injector is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with NVidia injector. If not, see . - */ - /* - * Alternatively you can choose to comply with APSL - */ - -/* - * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license: - * - * - * Copyright 2005-2006 Erik Waling - * Copyright 2006 Stephane Marchesin - * Copyright 2007-2009 Stuart Bennett - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef __LIBSAIO_NVIDIA_H -#define __LIBSAIO_NVIDIA_H - -bool setup_nvidia_devprop(pci_dt_t *nvda_dev); - -struct nv_chipsets_t { - unsigned device; - char *name; -}; - -#define DCB_MAX_NUM_ENTRIES 16 -#define DCB_MAX_NUM_I2C_ENTRIES 16 - -#define DCB_LOC_ON_CHIP 0 - -struct bios { - uint16_t signature; /* 0x55AA */ - uint8_t size; /* Size in multiples of 512 */ -}; - -#define NV_PROM_OFFSET 0x300000 -#define NV_PROM_SIZE 0x0000ffff -#define NV_PRAMIN_OFFSET 0x00700000 -#define NV_PRAMIN_SIZE 0x00100000 -#define NV04_PFB_FIFO_DATA 0x0010020c -#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 -#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 -#define NVC0_MEM_CTRLR_COUNT 0x00121c74 -#define NVC0_MEM_CTRLR_RAM_AMOUNT 0x0010f20c - -#define NV_PBUS_PCI_NV_20 0x00001850 -#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) -#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) - -#define REG8(reg) ((volatile uint8_t *)regs)[(reg)] -#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1] -#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2] - -#define NV_ARCH_03 0x03 -#define NV_ARCH_04 0x04 -#define NV_ARCH_10 0x10 -#define NV_ARCH_20 0x20 -#define NV_ARCH_30 0x30 -#define NV_ARCH_40 0x40 -#define NV_ARCH_50 0x50 -#define NV_ARCH_C0 0xC0 - -#define CHIPSET_NV03 0x0010 -#define CHIPSET_NV04 0x0020 -#define CHIPSET_NV10 0x0100 -#define CHIPSET_NV11 0x0110 -#define CHIPSET_NV15 0x0150 -#define CHIPSET_NV17 0x0170 -#define CHIPSET_NV18 0x0180 -#define CHIPSET_NFORCE 0x01A0 -#define CHIPSET_NFORCE2 0x01F0 -#define CHIPSET_NV20 0x0200 -#define CHIPSET_NV25 0x0250 -#define CHIPSET_NV28 0x0280 -#define CHIPSET_NV30 0x0300 -#define CHIPSET_NV31 0x0310 -#define CHIPSET_NV34 0x0320 -#define CHIPSET_NV35 0x0330 -#define CHIPSET_NV36 0x0340 -#define CHIPSET_NV40 0x0040 -#define CHIPSET_NV41 0x00C0 -#define CHIPSET_NV43 0x0140 -#define CHIPSET_NV44 0x0160 -#define CHIPSET_NV44A 0x0220 -#define CHIPSET_NV45 0x0210 -#define CHIPSET_NV50 0x0190 -#define CHIPSET_NV84 0x0400 -#define CHIPSET_MISC_BRIDGED 0x00F0 -#define CHIPSET_G70 0x0090 -#define CHIPSET_G71 0x0290 -#define CHIPSET_G72 0x01D0 -#define CHIPSET_G73 0x0390 - -// integrated GeForces (6100, 6150) -#define CHIPSET_C51 0x0240 - -// variant of C51, seems based on a G70 design -#define CHIPSET_C512 0x03D0 -#define CHIPSET_G73_BRIDGED 0x02E0 - -#endif /* !__LIBSAIO_NVIDIA_H */ Index: branches/ErmaC/i386/libsaio/ati_reg.h =================================================================== --- branches/ErmaC/i386/libsaio/ati_reg.h (revision 1567) +++ branches/ErmaC/i386/libsaio/ati_reg.h (revision 1568) @@ -1,5672 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* - * Authors: - * Kevin E. Martin - * Rickard E. Faith - * Alan Hourihane - * - * References: - * - * !!!! FIXME !!!! - * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical - * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April - * 1999. - * - * !!!! FIXME !!!! - * RAGE 128 Software Development Manual (Technical Reference Manual P/N - * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. - * - */ - -/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h - * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT - * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ - -#ifndef _ATI_REG_H_ -#define _ATI_REG_H_ - -#define ATI_DATATYPE_VQ 0 -#define ATI_DATATYPE_CI4 1 -#define ATI_DATATYPE_CI8 2 -#define ATI_DATATYPE_ARGB1555 3 -#define ATI_DATATYPE_RGB565 4 -#define ATI_DATATYPE_RGB888 5 -#define ATI_DATATYPE_ARGB8888 6 -#define ATI_DATATYPE_RGB332 7 -#define ATI_DATATYPE_Y8 8 -#define ATI_DATATYPE_RGB8 9 -#define ATI_DATATYPE_CI16 10 -#define ATI_DATATYPE_VYUY_422 11 -#define ATI_DATATYPE_YVYU_422 12 -#define ATI_DATATYPE_AYUV_444 14 -#define ATI_DATATYPE_ARGB4444 15 - - /* Registers for 2D/Video/Overlay */ -#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ -#define RADEON_AGP_BASE 0x0170 -#define RADEON_AGP_CNTL 0x0174 -# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) -# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) -# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) -# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) -# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) -# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) -# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) -# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) -#define RADEON_STATUS_PCI_CONFIG 0x06 -# define RADEON_CAP_LIST 0x100000 -#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ -# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ -# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ -# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ -# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ -#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ -#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ -# define RADEON_AGP_ENABLE (1<<8) -#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ -#define RADEON_AGP_STATUS 0x0f5c /* PCI */ -# define RADEON_AGP_1X_MODE 0x01 -# define RADEON_AGP_2X_MODE 0x02 -# define RADEON_AGP_4X_MODE 0x04 -# define RADEON_AGP_FW_MODE 0x10 -# define RADEON_AGP_MODE_MASK 0x17 -# define RADEON_AGPv3_MODE 0x08 -# define RADEON_AGPv3_4X_MODE 0x01 -# define RADEON_AGPv3_8X_MODE 0x02 -#define RADEON_ATTRDR 0x03c1 /* VGA */ -#define RADEON_ATTRDW 0x03c0 /* VGA */ -#define RADEON_ATTRX 0x03c0 /* VGA */ -#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 -#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc - -#define RADEON_BASE_CODE 0x0f0b -#define RADEON_BIOS_0_SCRATCH 0x0010 -# define RADEON_FP_PANEL_SCALABLE (1 << 16) -# define RADEON_FP_PANEL_SCALE_EN (1 << 17) -# define RADEON_FP_CHIP_SCALE_EN (1 << 18) -# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) -# define RADEON_DISPLAY_ROT_MASK (3 << 28) -# define RADEON_DISPLAY_ROT_00 (0 << 28) -# define RADEON_DISPLAY_ROT_90 (1 << 28) -# define RADEON_DISPLAY_ROT_180 (2 << 28) -# define RADEON_DISPLAY_ROT_270 (3 << 28) -#define RADEON_BIOS_1_SCRATCH 0x0014 -#define RADEON_BIOS_2_SCRATCH 0x0018 -#define RADEON_BIOS_3_SCRATCH 0x001c -#define RADEON_BIOS_4_SCRATCH 0x0020 -# define RADEON_CRT1_ATTACHED_MASK (3 << 0) -# define RADEON_CRT1_ATTACHED_MONO (1 << 0) -# define RADEON_CRT1_ATTACHED_COLOR (2 << 0) -# define RADEON_LCD1_ATTACHED (1 << 2) -# define RADEON_DFP1_ATTACHED (1 << 3) -# define RADEON_TV1_ATTACHED_MASK (3 << 4) -# define RADEON_TV1_ATTACHED_COMP (1 << 4) -# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) -# define RADEON_CRT2_ATTACHED_MASK (3 << 8) -# define RADEON_CRT2_ATTACHED_MONO (1 << 8) -# define RADEON_CRT2_ATTACHED_COLOR (2 << 8) -# define RADEON_DFP2_ATTACHED (1 << 11) -#define RADEON_BIOS_5_SCRATCH 0x0024 -# define RADEON_LCD1_ON (1 << 0) -# define RADEON_CRT1_ON (1 << 1) -# define RADEON_TV1_ON (1 << 2) -# define RADEON_DFP1_ON (1 << 3) -# define RADEON_CRT2_ON (1 << 5) -# define RADEON_CV1_ON (1 << 6) -# define RADEON_DFP2_ON (1 << 7) -# define RADEON_LCD1_CRTC_MASK (1 << 8) -# define RADEON_LCD1_CRTC_SHIFT 8 -# define RADEON_CRT1_CRTC_MASK (1 << 9) -# define RADEON_CRT1_CRTC_SHIFT 9 -# define RADEON_TV1_CRTC_MASK (1 << 10) -# define RADEON_TV1_CRTC_SHIFT 10 -# define RADEON_DFP1_CRTC_MASK (1 << 11) -# define RADEON_DFP1_CRTC_SHIFT 11 -# define RADEON_CRT2_CRTC_MASK (1 << 12) -# define RADEON_CRT2_CRTC_SHIFT 12 -# define RADEON_CV1_CRTC_MASK (1 << 13) -# define RADEON_CV1_CRTC_SHIFT 13 -# define RADEON_DFP2_CRTC_MASK (1 << 14) -# define RADEON_DFP2_CRTC_SHIFT 14 -#define RADEON_BIOS_6_SCRATCH 0x0028 -# define RADEON_ACC_MODE_CHANGE (1 << 2) -# define RADEON_EXT_DESKTOP_MODE (1 << 3) -# define RADEON_LCD_DPMS_ON (1 << 20) -# define RADEON_CRT_DPMS_ON (1 << 21) -# define RADEON_TV_DPMS_ON (1 << 22) -# define RADEON_DFP_DPMS_ON (1 << 23) -# define RADEON_DPMS_MASK (3 << 24) -# define RADEON_DPMS_ON (0 << 24) -# define RADEON_DPMS_STANDBY (1 << 24) -# define RADEON_DPMS_SUSPEND (2 << 24) -# define RADEON_DPMS_OFF (3 << 24) -# define RADEON_SCREEN_BLANKING (1 << 26) -# define RADEON_DRIVER_CRITICAL (1 << 27) -# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) -#define RADEON_BIOS_7_SCRATCH 0x002c -# define RADEON_SYS_HOTKEY (1 << 10) -# define RADEON_DRV_LOADED (1 << 12) -#define RADEON_BIOS_ROM 0x0f30 /* PCI */ -#define RADEON_BIST 0x0f0f /* PCI */ -#define RADEON_BRUSH_DATA0 0x1480 -#define RADEON_BRUSH_DATA1 0x1484 -#define RADEON_BRUSH_DATA10 0x14a8 -#define RADEON_BRUSH_DATA11 0x14ac -#define RADEON_BRUSH_DATA12 0x14b0 -#define RADEON_BRUSH_DATA13 0x14b4 -#define RADEON_BRUSH_DATA14 0x14b8 -#define RADEON_BRUSH_DATA15 0x14bc -#define RADEON_BRUSH_DATA16 0x14c0 -#define RADEON_BRUSH_DATA17 0x14c4 -#define RADEON_BRUSH_DATA18 0x14c8 -#define RADEON_BRUSH_DATA19 0x14cc -#define RADEON_BRUSH_DATA2 0x1488 -#define RADEON_BRUSH_DATA20 0x14d0 -#define RADEON_BRUSH_DATA21 0x14d4 -#define RADEON_BRUSH_DATA22 0x14d8 -#define RADEON_BRUSH_DATA23 0x14dc -#define RADEON_BRUSH_DATA24 0x14e0 -#define RADEON_BRUSH_DATA25 0x14e4 -#define RADEON_BRUSH_DATA26 0x14e8 -#define RADEON_BRUSH_DATA27 0x14ec -#define RADEON_BRUSH_DATA28 0x14f0 -#define RADEON_BRUSH_DATA29 0x14f4 -#define RADEON_BRUSH_DATA3 0x148c -#define RADEON_BRUSH_DATA30 0x14f8 -#define RADEON_BRUSH_DATA31 0x14fc -#define RADEON_BRUSH_DATA32 0x1500 -#define RADEON_BRUSH_DATA33 0x1504 -#define RADEON_BRUSH_DATA34 0x1508 -#define RADEON_BRUSH_DATA35 0x150c -#define RADEON_BRUSH_DATA36 0x1510 -#define RADEON_BRUSH_DATA37 0x1514 -#define RADEON_BRUSH_DATA38 0x1518 -#define RADEON_BRUSH_DATA39 0x151c -#define RADEON_BRUSH_DATA4 0x1490 -#define RADEON_BRUSH_DATA40 0x1520 -#define RADEON_BRUSH_DATA41 0x1524 -#define RADEON_BRUSH_DATA42 0x1528 -#define RADEON_BRUSH_DATA43 0x152c -#define RADEON_BRUSH_DATA44 0x1530 -#define RADEON_BRUSH_DATA45 0x1534 -#define RADEON_BRUSH_DATA46 0x1538 -#define RADEON_BRUSH_DATA47 0x153c -#define RADEON_BRUSH_DATA48 0x1540 -#define RADEON_BRUSH_DATA49 0x1544 -#define RADEON_BRUSH_DATA5 0x1494 -#define RADEON_BRUSH_DATA50 0x1548 -#define RADEON_BRUSH_DATA51 0x154c -#define RADEON_BRUSH_DATA52 0x1550 -#define RADEON_BRUSH_DATA53 0x1554 -#define RADEON_BRUSH_DATA54 0x1558 -#define RADEON_BRUSH_DATA55 0x155c -#define RADEON_BRUSH_DATA56 0x1560 -#define RADEON_BRUSH_DATA57 0x1564 -#define RADEON_BRUSH_DATA58 0x1568 -#define RADEON_BRUSH_DATA59 0x156c -#define RADEON_BRUSH_DATA6 0x1498 -#define RADEON_BRUSH_DATA60 0x1570 -#define RADEON_BRUSH_DATA61 0x1574 -#define RADEON_BRUSH_DATA62 0x1578 -#define RADEON_BRUSH_DATA63 0x157c -#define RADEON_BRUSH_DATA7 0x149c -#define RADEON_BRUSH_DATA8 0x14a0 -#define RADEON_BRUSH_DATA9 0x14a4 -#define RADEON_BRUSH_SCALE 0x1470 -#define RADEON_BRUSH_Y_X 0x1474 -#define RADEON_BUS_CNTL 0x0030 -# define RADEON_BUS_MASTER_DIS (1 << 6) -# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) -# define RADEON_BUS_RD_DISCARD_EN (1 << 24) -# define RADEON_BUS_RD_ABORT_EN (1 << 25) -# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) -# define RADEON_BUS_WRT_BURST (1 << 29) -# define RADEON_BUS_READ_BURST (1 << 30) -#define RADEON_BUS_CNTL1 0x0034 -# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) - -#define RADEON_PCIE_INDEX 0x0030 -#define RADEON_PCIE_DATA 0x0034 -#define R600_PCIE_PORT_INDEX 0x0038 -#define R600_PCIE_PORT_DATA 0x003c -/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */ -#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */ -# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0 -# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7 -# define RADEON_PCIE_LC_LINK_WIDTH_X0 0 -# define RADEON_PCIE_LC_LINK_WIDTH_X1 1 -# define RADEON_PCIE_LC_LINK_WIDTH_X2 2 -# define RADEON_PCIE_LC_LINK_WIDTH_X4 3 -# define RADEON_PCIE_LC_LINK_WIDTH_X8 4 -# define RADEON_PCIE_LC_LINK_WIDTH_X12 5 -# define RADEON_PCIE_LC_LINK_WIDTH_X16 6 -# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 -# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 -# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) -# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) -# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) -# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) -# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10) -# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11) -#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c -#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c - -#define RADEON_CACHE_CNTL 0x1724 -#define RADEON_CACHE_LINE 0x0f0c /* PCI */ -#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ -#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ -#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ -# define RADEON_DONT_USE_XTALIN (1 << 4) -# define RADEON_SCLK_DYN_START_CNTL (1 << 15) -#define RADEON_CLOCK_CNTL_DATA 0x000c -#define RADEON_CLOCK_CNTL_INDEX 0x0008 -# define RADEON_PLL_WR_EN (1 << 7) -# define RADEON_PLL_DIV_SEL (3 << 8) -# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) -#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */ -# define RADEON_M_SPLL_REF_DIV_MASK 0xff -# define RADEON_M_SPLL_REF_DIV_SHIFT 0 -# define RADEON_MPLL_FB_DIV_MASK 0xff -# define RADEON_MPLL_FB_DIV_SHIFT 8 -# define RADEON_SPLL_FB_DIV_MASK 0xff -# define RADEON_SPLL_FB_DIV_SHIFT 16 -#define RADEON_SPLL_CNTL 0x000c /* PLL */ -# define RADEON_SPLL_SLEEP (1 << 0) -# define RADEON_SPLL_RESET (1 << 1) -# define RADEON_SPLL_PCP_MASK 0x7 -# define RADEON_SPLL_PCP_SHIFT 8 -# define RADEON_SPLL_PVG_MASK 0x7 -# define RADEON_SPLL_PVG_SHIFT 11 -# define RADEON_SPLL_PDC_MASK 0x3 -# define RADEON_SPLL_PDC_SHIFT 14 -#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */ -# define RADEON_ENGIN_DYNCLK_MODE (1 << 12) -# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) -# define RADEON_ACTIVE_HILO_LAT_SHIFT 13 -# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) -# define RADEON_MC_BUSY (1 << 16) -# define RADEON_DLL_READY (1 << 19) -# define RADEON_CG_NO1_DEBUG_0 (1 << 24) -# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) -# define RADEON_DYN_STOP_MODE_MASK (7 << 21) -# define RADEON_TVPLL_PWRMGT_OFF (1 << 30) -# define RADEON_TVCLK_TURNOFF (1 << 31) -#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ -# define RADEON_TCL_BYPASS_DISABLE (1 << 20) -#define RADEON_CLR_CMP_CLR_3D 0x1a24 -#define RADEON_CLR_CMP_CLR_DST 0x15c8 -#define RADEON_CLR_CMP_CLR_SRC 0x15c4 -#define RADEON_CLR_CMP_CNTL 0x15c0 -# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) -# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) -# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) -#define RADEON_CLR_CMP_MASK 0x15cc -# define RADEON_CLR_CMP_MSK 0xffffffff -#define RADEON_CLR_CMP_MASK_3D 0x1A28 -#define RADEON_COMMAND 0x0f04 /* PCI */ -#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c -#define RADEON_CONFIG_APER_0_BASE 0x0100 -#define RADEON_CONFIG_APER_1_BASE 0x0104 -#define RADEON_CONFIG_APER_SIZE 0x0108 -#define RADEON_CONFIG_BONDS 0x00e8 -#define RADEON_CONFIG_CNTL 0x00e0 -# define RADEON_CFG_ATI_REV_A11 (0 << 16) -# define RADEON_CFG_ATI_REV_A12 (1 << 16) -# define RADEON_CFG_ATI_REV_A13 (2 << 16) -# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) -#define RADEON_CONFIG_MEMSIZE 0x00f8 -#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 -#define RADEON_CONFIG_REG_1_BASE 0x010c -#define RADEON_CONFIG_REG_APER_SIZE 0x0110 -#define RADEON_CONFIG_XSTRAP 0x00e4 -#define RADEON_CONSTANT_COLOR_C 0x1d34 -# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff -# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff -# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 -#define RADEON_CRC_CMDFIFO_ADDR 0x0740 -#define RADEON_CRC_CMDFIFO_DOUT 0x0744 -#define RADEON_GRPH_BUFFER_CNTL 0x02f0 -# define RADEON_GRPH_START_REQ_MASK (0x7f) -# define RADEON_GRPH_START_REQ_SHIFT 0 -# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) -# define RADEON_GRPH_STOP_REQ_SHIFT 8 -# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) -# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 -# define RADEON_GRPH_CRITICAL_CNTL (1<<28) -# define RADEON_GRPH_BUFFER_SIZE (1<<29) -# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) -# define RADEON_GRPH_STOP_CNTL (1<<31) -#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 -# define RADEON_GRPH2_START_REQ_MASK (0x7f) -# define RADEON_GRPH2_START_REQ_SHIFT 0 -# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) -# define RADEON_GRPH2_STOP_REQ_SHIFT 8 -# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) -# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 -# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) -# define RADEON_GRPH2_BUFFER_SIZE (1<<29) -# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) -# define RADEON_GRPH2_STOP_CNTL (1<<31) -#define RADEON_CRTC_CRNT_FRAME 0x0214 -#define RADEON_CRTC_EXT_CNTL 0x0054 -# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) -# define RADEON_VGA_ATI_LINEAR (1 << 3) -# define RADEON_XCRT_CNT_EN (1 << 6) -# define RADEON_CRTC_HSYNC_DIS (1 << 8) -# define RADEON_CRTC_VSYNC_DIS (1 << 9) -# define RADEON_CRTC_DISPLAY_DIS (1 << 10) -# define RADEON_CRTC_SYNC_TRISTAT (1 << 11) -# define RADEON_CRTC_CRT_ON (1 << 15) -#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 -# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) -# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) -# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) -#define RADEON_CRTC_GEN_CNTL 0x0050 -# define RADEON_CRTC_DBL_SCAN_EN (1 << 0) -# define RADEON_CRTC_INTERLACE_EN (1 << 1) -# define RADEON_CRTC_CSYNC_EN (1 << 4) -# define RADEON_CRTC_ICON_EN (1 << 15) -# define RADEON_CRTC_CUR_EN (1 << 16) -# define RADEON_CRTC_CUR_MODE_MASK (7 << 20) -# define RADEON_CRTC_EXT_DISP_EN (1 << 24) -# define RADEON_CRTC_EN (1 << 25) -# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) -#define RADEON_CRTC2_GEN_CNTL 0x03f8 -# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) -# define RADEON_CRTC2_INTERLACE_EN (1 << 1) -# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) -# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) -# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) -# define RADEON_CRTC2_CRT2_ON (1 << 7) -# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 -# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) -# define RADEON_CRTC2_ICON_EN (1 << 15) -# define RADEON_CRTC2_CUR_EN (1 << 16) -# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) -# define RADEON_CRTC2_DISP_DIS (1 << 23) -# define RADEON_CRTC2_EN (1 << 25) -# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) -# define RADEON_CRTC2_CSYNC_EN (1 << 27) -# define RADEON_CRTC2_HSYNC_DIS (1 << 28) -# define RADEON_CRTC2_VSYNC_DIS (1 << 29) -#define RADEON_CRTC_MORE_CNTL 0x27c -# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) -# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) -# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) -#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 -# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0 -# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15) -# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16 -# define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30) -#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 -# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) -# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) -# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 -# define RADEON_CRTC_H_SYNC_WID (0x3f << 16) -# define RADEON_CRTC_H_SYNC_WID_SHIFT 16 -# define RADEON_CRTC_H_SYNC_POL (1 << 23) -#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 -# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) -# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) -# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 -# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) -# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 -# define RADEON_CRTC2_H_SYNC_POL (1 << 23) -#define RADEON_CRTC_H_TOTAL_DISP 0x0200 -# define RADEON_CRTC_H_TOTAL (0x03ff << 0) -# define RADEON_CRTC_H_TOTAL_SHIFT 0 -# define RADEON_CRTC_H_DISP (0x01ff << 16) -# define RADEON_CRTC_H_DISP_SHIFT 16 -#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 -# define RADEON_CRTC2_H_TOTAL (0x03ff << 0) -# define RADEON_CRTC2_H_TOTAL_SHIFT 0 -# define RADEON_CRTC2_H_DISP (0x01ff << 16) -# define RADEON_CRTC2_H_DISP_SHIFT 16 - -#define RADEON_CRTC_OFFSET_RIGHT 0x0220 -#define RADEON_CRTC_OFFSET 0x0224 -# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) -# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) - -#define RADEON_CRTC2_OFFSET 0x0324 -# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) -# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) -#define RADEON_CRTC_OFFSET_CNTL 0x0228 -# define RADEON_CRTC_TILE_LINE_SHIFT 0 -# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 -# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) -# define R300_CRTC_X_Y_MODE_EN (1 << 9) -# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) -# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) -# define R300_CRTC_MICRO_TILE_EN (1 << 13) -# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) -# define R300_CRTC_MACRO_TILE_EN (1 << 15) -# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) -# define RADEON_CRTC_TILE_EN (1 << 15) -# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) -# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) - -#define R300_CRTC_TILE_X0_Y0 0x0350 -#define R300_CRTC2_TILE_X0_Y0 0x0358 - -#define RADEON_CRTC2_OFFSET_CNTL 0x0328 -# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) -# define RADEON_CRTC2_TILE_EN (1 << 15) -#define RADEON_CRTC_PITCH 0x022c -# define RADEON_CRTC_PITCH__SHIFT 0 -# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 - -#define RADEON_CRTC2_PITCH 0x032c -#define RADEON_CRTC_STATUS 0x005c -# define RADEON_CRTC_VBLANK_SAVE (1 << 1) -# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) -#define RADEON_CRTC2_STATUS 0x03fc -# define RADEON_CRTC2_VBLANK_SAVE (1 << 1) -# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) -#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c -# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) -# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 -# define RADEON_CRTC_V_SYNC_WID (0x1f << 16) -# define RADEON_CRTC_V_SYNC_WID_SHIFT 16 -# define RADEON_CRTC_V_SYNC_POL (1 << 23) -#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c -# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) -# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 -# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) -# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 -# define RADEON_CRTC2_V_SYNC_POL (1 << 23) -#define RADEON_CRTC_V_TOTAL_DISP 0x0208 -# define RADEON_CRTC_V_TOTAL (0x07ff << 0) -# define RADEON_CRTC_V_TOTAL_SHIFT 0 -# define RADEON_CRTC_V_DISP (0x07ff << 16) -# define RADEON_CRTC_V_DISP_SHIFT 16 -#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 -# define RADEON_CRTC2_V_TOTAL (0x07ff << 0) -# define RADEON_CRTC2_V_TOTAL_SHIFT 0 -# define RADEON_CRTC2_V_DISP (0x07ff << 16) -# define RADEON_CRTC2_V_DISP_SHIFT 16 -#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 -# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) -#define RADEON_CRTC2_CRNT_FRAME 0x0314 -#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 -#define RADEON_CRTC2_STATUS 0x03fc -#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 -#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ -#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ -#define RADEON_CUR_CLR0 0x026c -#define RADEON_CUR_CLR1 0x0270 -#define RADEON_CUR_HORZ_VERT_OFF 0x0268 -#define RADEON_CUR_HORZ_VERT_POSN 0x0264 -#define RADEON_CUR_OFFSET 0x0260 -# define RADEON_CUR_LOCK (1 << 31) -#define RADEON_CUR2_CLR0 0x036c -#define RADEON_CUR2_CLR1 0x0370 -#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 -#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 -#define RADEON_CUR2_OFFSET 0x0360 -# define RADEON_CUR2_LOCK (1 << 31) - -#define RADEON_DAC_CNTL 0x0058 -# define RADEON_DAC_RANGE_CNTL (3 << 0) -# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) -# define RADEON_DAC_RANGE_CNTL_MASK 0x03 -# define RADEON_DAC_BLANKING (1 << 2) -# define RADEON_DAC_CMP_EN (1 << 3) -# define RADEON_DAC_CMP_OUTPUT (1 << 7) -# define RADEON_DAC_8BIT_EN (1 << 8) -# define RADEON_DAC_TVO_EN (1 << 10) -# define RADEON_DAC_VGA_ADR_EN (1 << 13) -# define RADEON_DAC_PDWN (1 << 15) -# define RADEON_DAC_MASK_ALL (0xff << 24) -#define RADEON_DAC_CNTL2 0x007c -# define RADEON_DAC2_TV_CLK_SEL (0 << 1) -# define RADEON_DAC2_DAC_CLK_SEL (1 << 0) -# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) -# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) -# define RADEON_DAC2_CMP_EN (1 << 7) -# define RADEON_DAC2_CMP_OUT_R (1 << 8) -# define RADEON_DAC2_CMP_OUT_G (1 << 9) -# define RADEON_DAC2_CMP_OUT_B (1 << 10) -# define RADEON_DAC2_CMP_OUTPUT (1 << 11) -#define RADEON_DAC_EXT_CNTL 0x0280 -# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) -# define RADEON_DAC2_FORCE_DATA_EN (1 << 1) -# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) -# define RADEON_DAC_FORCE_DATA_EN (1 << 5) -# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) -# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 -# define RADEON_DAC_FORCE_DATA_SHIFT 8 -#define RADEON_DAC_MACRO_CNTL 0x0d04 -# define RADEON_DAC_PDWN_R (1 << 16) -# define RADEON_DAC_PDWN_G (1 << 17) -# define RADEON_DAC_PDWN_B (1 << 18) -#define RADEON_TV_DAC_CNTL 0x088c -# define RADEON_TV_DAC_NBLANK (1 << 0) -# define RADEON_TV_DAC_NHOLD (1 << 1) -# define RADEON_TV_DAC_PEDESTAL (1 << 2) -# define RADEON_TV_MONITOR_DETECT_EN (1 << 4) -# define RADEON_TV_DAC_CMPOUT (1 << 5) -# define RADEON_TV_DAC_STD_MASK (3 << 8) -# define RADEON_TV_DAC_STD_PAL (0 << 8) -# define RADEON_TV_DAC_STD_NTSC (1 << 8) -# define RADEON_TV_DAC_STD_PS2 (2 << 8) -# define RADEON_TV_DAC_STD_RS343 (3 << 8) -# define RADEON_TV_DAC_BGSLEEP (1 << 6) -# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) -# define RADEON_TV_DAC_BGADJ_SHIFT 16 -# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) -# define RADEON_TV_DAC_DACADJ_SHIFT 20 -# define RADEON_TV_DAC_RDACPD (1 << 24) -# define RADEON_TV_DAC_GDACPD (1 << 25) -# define RADEON_TV_DAC_BDACPD (1 << 26) -# define RADEON_TV_DAC_RDACDET (1 << 29) -# define RADEON_TV_DAC_GDACDET (1 << 30) -# define RADEON_TV_DAC_BDACDET (1 << 31) -# define R420_TV_DAC_DACADJ_MASK (0x1f << 20) -# define R420_TV_DAC_RDACPD (1 << 25) -# define R420_TV_DAC_GDACPD (1 << 26) -# define R420_TV_DAC_BDACPD (1 << 27) -# define R420_TV_DAC_TVENABLE (1 << 28) -#define RADEON_DISP_HW_DEBUG 0x0d14 -# define RADEON_CRT2_DISP1_SEL (1 << 5) -#define RADEON_DISP_OUTPUT_CNTL 0x0d64 -# define RADEON_DISP_DAC_SOURCE_MASK 0x03 -# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c -# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 -# define RADEON_DISP_DAC_SOURCE_RMX 0x02 -# define RADEON_DISP_DAC_SOURCE_LTU 0x03 -# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 -# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) -# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 -# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) -# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) -# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) -# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) -# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) -# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) -# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) -# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ -# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ -#define RADEON_DISP_TV_OUT_CNTL 0x0d6c -# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) -# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) -#define RADEON_DAC_CRC_SIG 0x02cc -#define RADEON_DAC_DATA 0x03c9 /* VGA */ -#define RADEON_DAC_MASK 0x03c6 /* VGA */ -#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ -#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ -#define RADEON_DDA_CONFIG 0x02e0 -#define RADEON_DDA_ON_OFF 0x02e4 -#define RADEON_DEFAULT_OFFSET 0x16e0 -#define RADEON_DEFAULT_PITCH 0x16e4 -#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 -# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) -#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 -#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 -#define RADEON_DEVICE_ID 0x0f02 /* PCI */ -#define RADEON_DISP_MISC_CNTL 0x0d00 -# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) -#define RADEON_DISP_MERGE_CNTL 0x0d60 -# define RADEON_DISP_ALPHA_MODE_MASK 0x03 -# define RADEON_DISP_ALPHA_MODE_KEY 0 -# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 -# define RADEON_DISP_ALPHA_MODE_GLOBAL 2 -# define RADEON_DISP_RGB_OFFSET_EN (1 << 8) -# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) -# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) -# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) -#define RADEON_DISP2_MERGE_CNTL 0x0d68 -# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) -#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 -#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 -#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 -#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c -#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 -#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 -#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 -#define RADEON_DP_BRUSH_FRGD_CLR 0x147c -#define RADEON_DP_CNTL 0x16c0 -# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) -# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) -# define RADEON_DP_DST_TILE_LINEAR (0 << 3) -# define RADEON_DP_DST_TILE_MACRO (1 << 3) -# define RADEON_DP_DST_TILE_MICRO (2 << 3) -# define RADEON_DP_DST_TILE_BOTH (3 << 3) -#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 -# define RADEON_DST_Y_MAJOR (1 << 2) -# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) -# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) -#define RADEON_DP_DATATYPE 0x16c4 -# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) -#define RADEON_DP_GUI_MASTER_CNTL 0x146c -# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) -# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) -# define RADEON_GMC_SRC_CLIPPING (1 << 2) -# define RADEON_GMC_DST_CLIPPING (1 << 3) -# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) -# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) -# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) -# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) -# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) -# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) -# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) -# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) -# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) -# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) -# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) -# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) -# define RADEON_GMC_BRUSH_NONE (15 << 4) -# define RADEON_GMC_DST_8BPP_CI (2 << 8) -# define RADEON_GMC_DST_15BPP (3 << 8) -# define RADEON_GMC_DST_16BPP (4 << 8) -# define RADEON_GMC_DST_24BPP (5 << 8) -# define RADEON_GMC_DST_32BPP (6 << 8) -# define RADEON_GMC_DST_8BPP_RGB (7 << 8) -# define RADEON_GMC_DST_Y8 (8 << 8) -# define RADEON_GMC_DST_RGB8 (9 << 8) -# define RADEON_GMC_DST_VYUY (11 << 8) -# define RADEON_GMC_DST_YVYU (12 << 8) -# define RADEON_GMC_DST_AYUV444 (14 << 8) -# define RADEON_GMC_DST_ARGB4444 (15 << 8) -# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) -# define RADEON_GMC_DST_DATATYPE_SHIFT 8 -# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) -# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) -# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) -# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) -# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) -# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) -# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) -# define RADEON_GMC_CONVERSION_TEMP (1 << 15) -# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) -# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) -# define RADEON_GMC_ROP3_MASK (0xff << 16) -# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) -# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) -# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) -# define RADEON_GMC_3D_FCN_EN (1 << 27) -# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) -# define RADEON_GMC_WR_MSK_DIS (1 << 30) -# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) -# define RADEON_ROP3_ZERO 0x00000000 -# define RADEON_ROP3_DSa 0x00880000 -# define RADEON_ROP3_SDna 0x00440000 -# define RADEON_ROP3_S 0x00cc0000 -# define RADEON_ROP3_DSna 0x00220000 -# define RADEON_ROP3_D 0x00aa0000 -# define RADEON_ROP3_DSx 0x00660000 -# define RADEON_ROP3_DSo 0x00ee0000 -# define RADEON_ROP3_DSon 0x00110000 -# define RADEON_ROP3_DSxn 0x00990000 -# define RADEON_ROP3_Dn 0x00550000 -# define RADEON_ROP3_SDno 0x00dd0000 -# define RADEON_ROP3_Sn 0x00330000 -# define RADEON_ROP3_DSno 0x00bb0000 -# define RADEON_ROP3_DSan 0x00770000 -# define RADEON_ROP3_ONE 0x00ff0000 -# define RADEON_ROP3_DPa 0x00a00000 -# define RADEON_ROP3_PDna 0x00500000 -# define RADEON_ROP3_P 0x00f00000 -# define RADEON_ROP3_DPna 0x000a0000 -# define RADEON_ROP3_D 0x00aa0000 -# define RADEON_ROP3_DPx 0x005a0000 -# define RADEON_ROP3_DPo 0x00fa0000 -# define RADEON_ROP3_DPon 0x00050000 -# define RADEON_ROP3_PDxn 0x00a50000 -# define RADEON_ROP3_PDno 0x00f50000 -# define RADEON_ROP3_Pn 0x000f0000 -# define RADEON_ROP3_DPno 0x00af0000 -# define RADEON_ROP3_DPan 0x005f0000 -#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 -#define RADEON_DP_MIX 0x16c8 -#define RADEON_DP_SRC_BKGD_CLR 0x15dc -#define RADEON_DP_SRC_FRGD_CLR 0x15d8 -#define RADEON_DP_WRITE_MASK 0x16cc -#define RADEON_DST_BRES_DEC 0x1630 -#define RADEON_DST_BRES_ERR 0x1628 -#define RADEON_DST_BRES_INC 0x162c -#define RADEON_DST_BRES_LNTH 0x1634 -#define RADEON_DST_BRES_LNTH_SUB 0x1638 -#define RADEON_DST_HEIGHT 0x1410 -#define RADEON_DST_HEIGHT_WIDTH 0x143c -#define RADEON_DST_HEIGHT_WIDTH_8 0x158c -#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 -#define RADEON_DST_HEIGHT_Y 0x15a0 -#define RADEON_DST_LINE_START 0x1600 -#define RADEON_DST_LINE_END 0x1604 -#define RADEON_DST_LINE_PATCOUNT 0x1608 -# define RADEON_BRES_CNTL_SHIFT 8 -#define RADEON_DST_OFFSET 0x1404 -#define RADEON_DST_PITCH 0x1408 -#define RADEON_DST_PITCH_OFFSET 0x142c -#define RADEON_DST_PITCH_OFFSET_C 0x1c80 -# define RADEON_PITCH_SHIFT 21 -# define RADEON_DST_TILE_LINEAR (0 << 30) -# define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) -#define RADEON_DST_WIDTH 0x140c -#define RADEON_DST_WIDTH_HEIGHT 0x1598 -#define RADEON_DST_WIDTH_X 0x1588 -#define RADEON_DST_WIDTH_X_INCY 0x159c -#define RADEON_DST_X 0x141c -#define RADEON_DST_X_SUB 0x15a4 -#define RADEON_DST_X_Y 0x1594 -#define RADEON_DST_Y 0x1420 -#define RADEON_DST_Y_SUB 0x15a8 -#define RADEON_DST_Y_X 0x1438 - -#define RADEON_FCP_CNTL 0x0910 -# define RADEON_FCP0_SRC_PCICLK 0 -# define RADEON_FCP0_SRC_PCLK 1 -# define RADEON_FCP0_SRC_PCLKb 2 -# define RADEON_FCP0_SRC_HREF 3 -# define RADEON_FCP0_SRC_GND 4 -# define RADEON_FCP0_SRC_HREFb 5 -#define RADEON_FLUSH_1 0x1704 -#define RADEON_FLUSH_2 0x1708 -#define RADEON_FLUSH_3 0x170c -#define RADEON_FLUSH_4 0x1710 -#define RADEON_FLUSH_5 0x1714 -#define RADEON_FLUSH_6 0x1718 -#define RADEON_FLUSH_7 0x171c -#define RADEON_FOG_3D_TABLE_START 0x1810 -#define RADEON_FOG_3D_TABLE_END 0x1814 -#define RADEON_FOG_3D_TABLE_DENSITY 0x181c -#define RADEON_FOG_TABLE_INDEX 0x1a14 -#define RADEON_FOG_TABLE_DATA 0x1a18 -#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 -#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 -# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff -# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 -# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff -# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 -# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 -# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff -# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 -# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 -# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 -# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 -# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 -# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 -# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 -# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 -#define RADEON_FP_GEN_CNTL 0x0284 -# define RADEON_FP_FPON (1 << 0) -# define RADEON_FP_BLANK_EN (1 << 1) -# define RADEON_FP_TMDS_EN (1 << 2) -# define RADEON_FP_PANEL_FORMAT (1 << 3) -# define RADEON_FP_EN_TMDS (1 << 7) -# define RADEON_FP_DETECT_SENSE (1 << 8) -# define R200_FP_SOURCE_SEL_MASK (3 << 10) -# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) -# define R200_FP_SOURCE_SEL_RMX (2 << 10) -# define R200_FP_SOURCE_SEL_TRANS (3 << 10) -# define RADEON_FP_SEL_CRTC1 (0 << 13) -# define RADEON_FP_SEL_CRTC2 (1 << 13) -# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) -# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) -# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -# define RADEON_FP_DFP_SYNC_SEL (1 << 21) -# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) -# define RADEON_FP_CRT_SYNC_SEL (1 << 23) -# define RADEON_FP_USE_SHADOW_EN (1 << 24) -# define RADEON_FP_CRT_SYNC_ALT (1 << 26) -#define RADEON_FP2_GEN_CNTL 0x0288 -# define RADEON_FP2_BLANK_EN (1 << 1) -# define RADEON_FP2_ON (1 << 2) -# define RADEON_FP2_PANEL_FORMAT (1 << 3) -# define RADEON_FP2_DETECT_SENSE (1 << 8) -# define R200_FP2_SOURCE_SEL_MASK (3 << 10) -# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) -# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) -# define R200_FP2_SOURCE_SEL_RMX (2 << 10) -# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) -# define RADEON_FP2_SRC_SEL_MASK (3 << 13) -# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) -# define RADEON_FP2_FP_POL (1 << 16) -# define RADEON_FP2_LP_POL (1 << 17) -# define RADEON_FP2_SCK_POL (1 << 18) -# define RADEON_FP2_LCD_CNTL_MASK (7 << 19) -# define RADEON_FP2_PAD_FLOP_EN (1 << 22) -# define RADEON_FP2_CRC_EN (1 << 23) -# define RADEON_FP2_CRC_READ_EN (1 << 24) -# define RADEON_FP2_DVO_EN (1 << 25) -# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) -# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) -# define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) -# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) -#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 -#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 -#define RADEON_FP_HORZ_STRETCH 0x028c -#define RADEON_FP_HORZ2_STRETCH 0x038c -# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff -# define RADEON_HORZ_STRETCH_RATIO_MAX 4096 -# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) -# define RADEON_HORZ_PANEL_SHIFT 16 -# define RADEON_HORZ_STRETCH_PIXREP (0 << 25) -# define RADEON_HORZ_STRETCH_BLEND (1 << 26) -# define RADEON_HORZ_STRETCH_ENABLE (1 << 25) -# define RADEON_HORZ_AUTO_RATIO (1 << 27) -# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) -# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) -#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 -#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 -#define RADEON_FP_VERT_STRETCH 0x0290 -#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 -#define RADEON_FP_VERT2_STRETCH 0x0390 -# define RADEON_VERT_PANEL_SIZE (0xfff << 12) -# define RADEON_VERT_PANEL_SHIFT 12 -# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff -# define RADEON_VERT_STRETCH_RATIO_SHIFT 0 -# define RADEON_VERT_STRETCH_RATIO_MAX 4096 -# define RADEON_VERT_STRETCH_ENABLE (1 << 25) -# define RADEON_VERT_STRETCH_LINEREP (0 << 26) -# define RADEON_VERT_STRETCH_BLEND (1 << 26) -# define RADEON_VERT_AUTO_RATIO_EN (1 << 27) -# define RADEON_VERT_AUTO_RATIO_INC (1 << 31) -# define RADEON_VERT_STRETCH_RESERVED 0x71000000 -#define RS400_FP_2ND_GEN_CNTL 0x0384 -# define RS400_FP_2ND_ON (1 << 0) -# define RS400_FP_2ND_BLANK_EN (1 << 1) -# define RS400_TMDS_2ND_EN (1 << 2) -# define RS400_PANEL_FORMAT_2ND (1 << 3) -# define RS400_FP_2ND_EN_TMDS (1 << 7) -# define RS400_FP_2ND_DETECT_SENSE (1 << 8) -# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) -# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) -# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) -# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) -# define RS400_FP_2ND_DETECT_EN (1 << 12) -# define RS400_HPD_2ND_SEL (1 << 13) -#define RS400_FP2_2_GEN_CNTL 0x0388 -# define RS400_FP2_2_BLANK_EN (1 << 1) -# define RS400_FP2_2_ON (1 << 2) -# define RS400_FP2_2_PANEL_FORMAT (1 << 3) -# define RS400_FP2_2_DETECT_SENSE (1 << 8) -# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) -# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) -# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) -# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) -# define RS400_FP2_2_DVO2_EN (1 << 25) -#define RS400_TMDS2_CNTL 0x0394 -#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 -# define RS400_TMDS2_PLLEN (1 << 0) -# define RS400_TMDS2_PLLRST (1 << 1) - -#define RADEON_GEN_INT_CNTL 0x0040 -#define RADEON_GEN_INT_STATUS 0x0044 -# define RADEON_VSYNC_INT_AK (1 << 2) -# define RADEON_VSYNC_INT (1 << 2) -# define RADEON_VSYNC2_INT_AK (1 << 6) -# define RADEON_VSYNC2_INT (1 << 6) -#define RADEON_GENENB 0x03c3 /* VGA */ -#define RADEON_GENFC_RD 0x03ca /* VGA */ -#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ -#define RADEON_GENMO_RD 0x03cc /* VGA */ -#define RADEON_GENMO_WT 0x03c2 /* VGA */ -#define RADEON_GENS0 0x03c2 /* VGA */ -#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ -#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */ -#define RADEON_GPIO_MONIDB 0x006c -#define RADEON_GPIO_CRT2_DDC 0x006c -#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */ -#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */ -# define RADEON_GPIO_A_0 (1 << 0) -# define RADEON_GPIO_A_1 (1 << 1) -# define RADEON_GPIO_Y_0 (1 << 8) -# define RADEON_GPIO_Y_1 (1 << 9) -# define RADEON_GPIO_Y_SHIFT_0 8 -# define RADEON_GPIO_Y_SHIFT_1 9 -# define RADEON_GPIO_EN_0 (1 << 16) -# define RADEON_GPIO_EN_1 (1 << 17) -# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ -# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ -#define RADEON_GRPH8_DATA 0x03cf /* VGA */ -#define RADEON_GRPH8_IDX 0x03ce /* VGA */ -#define RADEON_GUI_SCRATCH_REG0 0x15e0 -#define RADEON_GUI_SCRATCH_REG1 0x15e4 -#define RADEON_GUI_SCRATCH_REG2 0x15e8 -#define RADEON_GUI_SCRATCH_REG3 0x15ec -#define RADEON_GUI_SCRATCH_REG4 0x15f0 -#define RADEON_GUI_SCRATCH_REG5 0x15f4 - -#define RADEON_HEADER 0x0f0e /* PCI */ -#define RADEON_HOST_DATA0 0x17c0 -#define RADEON_HOST_DATA1 0x17c4 -#define RADEON_HOST_DATA2 0x17c8 -#define RADEON_HOST_DATA3 0x17cc -#define RADEON_HOST_DATA4 0x17d0 -#define RADEON_HOST_DATA5 0x17d4 -#define RADEON_HOST_DATA6 0x17d8 -#define RADEON_HOST_DATA7 0x17dc -#define RADEON_HOST_DATA_LAST 0x17e0 -#define RADEON_HOST_PATH_CNTL 0x0130 -# define RADEON_HDP_SOFT_RESET (1 << 26) -# define RADEON_HDP_APER_CNTL (1 << 23) -#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ -# define RADEON_HTOT_CNTL_VGA_EN (1 << 28) -#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ - - /* Multimedia I2C bus */ -#define RADEON_I2C_CNTL_0 0x0090 -#define RADEON_I2C_DONE (1 << 0) -#define RADEON_I2C_NACK (1 << 1) -#define RADEON_I2C_HALT (1 << 2) -#define RADEON_I2C_SOFT_RST (1 << 5) -#define RADEON_I2C_DRIVE_EN (1 << 6) -#define RADEON_I2C_DRIVE_SEL (1 << 7) -#define RADEON_I2C_START (1 << 8) -#define RADEON_I2C_STOP (1 << 9) -#define RADEON_I2C_RECEIVE (1 << 10) -#define RADEON_I2C_ABORT (1 << 11) -#define RADEON_I2C_GO (1 << 12) -#define RADEON_I2C_CNTL_1 0x0094 -#define RADEON_I2C_SEL (1 << 16) -#define RADEON_I2C_EN (1 << 17) -#define RADEON_I2C_DATA 0x0098 - -#define RADEON_DVI_I2C_CNTL_0 0x02e0 -# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) -# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */ -# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */ -# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */ -#define RADEON_DVI_I2C_CNTL_1 0x02e4 -#define RADEON_DVI_I2C_DATA 0x02e8 - -#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ -#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ -#define RADEON_IO_BASE 0x0f14 /* PCI */ - -#define RADEON_LATENCY 0x0f0d /* PCI */ -#define RADEON_LEAD_BRES_DEC 0x1608 -#define RADEON_LEAD_BRES_LNTH 0x161c -#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 -#define RADEON_LVDS_GEN_CNTL 0x02d0 -# define RADEON_LVDS_ON (1 << 0) -# define RADEON_LVDS_DISPLAY_DIS (1 << 1) -# define RADEON_LVDS_PANEL_TYPE (1 << 2) -# define RADEON_LVDS_PANEL_FORMAT (1 << 3) -# define RADEON_LVDS_RST_FM (1 << 6) -# define RADEON_LVDS_EN (1 << 7) -# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 -# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) -# define RADEON_LVDS_BL_MOD_EN (1 << 16) -# define RADEON_LVDS_DIGON (1 << 18) -# define RADEON_LVDS_BLON (1 << 19) -# define RADEON_LVDS_SEL_CRTC2 (1 << 23) -#define RADEON_LVDS_PLL_CNTL 0x02d4 -# define RADEON_HSYNC_DELAY_SHIFT 28 -# define RADEON_HSYNC_DELAY_MASK (0xf << 28) -# define RADEON_LVDS_PLL_EN (1 << 16) -# define RADEON_LVDS_PLL_RESET (1 << 17) -# define R300_LVDS_SRC_SEL_MASK (3 << 18) -# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) -# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) -# define R300_LVDS_SRC_SEL_RMX (2 << 18) - -#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ -#define RADEON_MC_AGP_LOCATION 0x014c -#define RADEON_MC_FB_LOCATION 0x0148 -#define RADEON_DISPLAY_BASE_ADDR 0x23c -#define RADEON_DISPLAY2_BASE_ADDR 0x33c -#define RADEON_OV0_BASE_ADDR 0x43c -#define RADEON_NB_TOM 0x15c -#define R300_MC_INIT_MISC_LAT_TIMER 0x180 -# define R300_MC_DISP0R_INIT_LAT_SHIFT 8 -# define R300_MC_DISP0R_INIT_LAT_MASK 0xf -# define R300_MC_DISP1R_INIT_LAT_SHIFT 12 -# define R300_MC_DISP1R_INIT_LAT_MASK 0xf -#define RADEON_MCLK_CNTL 0x0012 /* PLL */ -# define RADEON_FORCEON_MCLKA (1 << 16) -# define RADEON_FORCEON_MCLKB (1 << 17) -# define RADEON_FORCEON_YCLKA (1 << 18) -# define RADEON_FORCEON_YCLKB (1 << 19) -# define RADEON_FORCEON_MC (1 << 20) -# define RADEON_FORCEON_AIC (1 << 21) -# define R300_DISABLE_MC_MCLKA (1 << 21) -# define R300_DISABLE_MC_MCLKB (1 << 21) -#define RADEON_MCLK_MISC 0x001f /* PLL */ -# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) -# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) -# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) -# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) -#define RADEON_LCD_GPIO_MASK 0x01a0 -#define RADEON_GPIOPAD_EN 0x01a0 -#define RADEON_LCD_GPIO_Y_REG 0x01a4 -#define RADEON_MDGPIO_A_REG 0x01ac -#define RADEON_MDGPIO_EN_REG 0x01b0 -#define RADEON_MDGPIO_MASK 0x0198 -#define RADEON_GPIOPAD_MASK 0x0198 -#define RADEON_GPIOPAD_A 0x019c -#define RADEON_MDGPIO_Y_REG 0x01b4 -#define RADEON_MEM_ADDR_CONFIG 0x0148 -#define RADEON_MEM_BASE 0x0f10 /* PCI */ -#define RADEON_MEM_CNTL 0x0140 -# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 -# define RADEON_MEM_USE_B_CH_ONLY (1 << 1) -# define RV100_HALF_MODE (1 << 3) -# define R300_MEM_NUM_CHANNELS_MASK 0x03 -# define R300_MEM_USE_CD_CH_ONLY (1 << 2) -#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ -#define RADEON_MEM_INIT_LAT_TIMER 0x0154 -#define RADEON_MEM_INTF_CNTL 0x014c -#define RADEON_MEM_SDRAM_MODE_REG 0x0158 -# define RADEON_SDRAM_MODE_MASK 0xffff0000 -# define RADEON_B3MEM_RESET_MASK 0x6fffffff -# define RADEON_MEM_CFG_TYPE_DDR (1 << 30) -#define RADEON_MEM_STR_CNTL 0x0150 -# define RADEON_MEM_PWRUP_COMPL_A (1 << 0) -# define RADEON_MEM_PWRUP_COMPL_B (1 << 1) -# define R300_MEM_PWRUP_COMPL_C (1 << 2) -# define R300_MEM_PWRUP_COMPL_D (1 << 3) -# define RADEON_MEM_PWRUP_COMPLETE 0x03 -# define R300_MEM_PWRUP_COMPLETE 0x0f -#define RADEON_MC_STATUS 0x0150 -# define RADEON_MC_IDLE (1 << 2) -# define R300_MC_IDLE (1 << 4) -#define RADEON_MEM_VGA_RP_SEL 0x003c -#define RADEON_MEM_VGA_WP_SEL 0x0038 -#define RADEON_MIN_GRANT 0x0f3e /* PCI */ -#define RADEON_MM_DATA 0x0004 -#define RADEON_MM_INDEX 0x0000 -#define RADEON_MPLL_CNTL 0x000e /* PLL */ -#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ -#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ -#define RADEON_SEPROM_CNTL1 0x01c0 -# define RADEON_SCK_PRESCALE_SHIFT 24 -# define RADEON_SCK_PRESCALE_MASK (0xff << 24) -#define R300_MC_IND_INDEX 0x01f8 -# define R300_MC_IND_ADDR_MASK 0x3f -# define R300_MC_IND_WR_EN (1 << 8) -#define R300_MC_IND_DATA 0x01fc -#define R300_MC_READ_CNTL_AB 0x017c -# define R300_MEM_RBS_POSITION_A_MASK 0x03 -#define R300_MC_READ_CNTL_CD_mcind 0x24 -# define R300_MEM_RBS_POSITION_C_MASK 0x03 - -#define RADEON_N_VIF_COUNT 0x0248 - -#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 -# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 -# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 -# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 -# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 -# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 -# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 - -#define RADEON_OV0_COLOUR_CNTL 0x04E0 -#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 -#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 -# define RADEON_EXCL_HORZ_START_MASK 0x000000ff -# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 -# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 -# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 -#define RADEON_OV0_EXCLUSIVE_VERT 0x040C -# define RADEON_EXCL_VERT_START_MASK 0x000003ff -# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 -#define RADEON_OV0_FILTER_CNTL 0x04A0 -# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 -# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 -# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 -# define RADEON_FILTER_HC_COEF_VERT_Y 0x4 -# define RADEON_FILTER_HC_COEF_VERT_UV 0x8 -# define RADEON_FILTER_HARDCODED_COEF 0xf -# define RADEON_FILTER_COEF_MASK 0xf - -#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 -#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 -#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 -#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC -#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 -#define RADEON_OV0_FLAG_CNTL 0x04DC -#define RADEON_OV0_GAMMA_000_00F 0x0d40 -#define RADEON_OV0_GAMMA_010_01F 0x0d44 -#define RADEON_OV0_GAMMA_020_03F 0x0d48 -#define RADEON_OV0_GAMMA_040_07F 0x0d4c -#define RADEON_OV0_GAMMA_080_0BF 0x0e00 -#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 -#define RADEON_OV0_GAMMA_100_13F 0x0e08 -#define RADEON_OV0_GAMMA_140_17F 0x0e0c -#define RADEON_OV0_GAMMA_180_1BF 0x0e10 -#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 -#define RADEON_OV0_GAMMA_200_23F 0x0e18 -#define RADEON_OV0_GAMMA_240_27F 0x0e1c -#define RADEON_OV0_GAMMA_280_2BF 0x0e20 -#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 -#define RADEON_OV0_GAMMA_300_33F 0x0e28 -#define RADEON_OV0_GAMMA_340_37F 0x0e2c -#define RADEON_OV0_GAMMA_380_3BF 0x0d50 -#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 -#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC -#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 -#define RADEON_OV0_H_INC 0x0480 -#define RADEON_OV0_KEY_CNTL 0x04F4 -# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L -# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L -# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L -# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L -# define RADEON_VIDEO_KEY_FN_NE 0x00000003L -# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L -# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L -# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L -# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L -# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L -# define RADEON_CMP_MIX_MASK 0x00000100L -# define RADEON_CMP_MIX_OR 0x00000000L -# define RADEON_CMP_MIX_AND 0x00000100L -#define RADEON_OV0_LIN_TRANS_A 0x0d20 -#define RADEON_OV0_LIN_TRANS_B 0x0d24 -#define RADEON_OV0_LIN_TRANS_C 0x0d28 -#define RADEON_OV0_LIN_TRANS_D 0x0d2c -#define RADEON_OV0_LIN_TRANS_E 0x0d30 -#define RADEON_OV0_LIN_TRANS_F 0x0d34 -#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 -# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL -# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L -#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 -#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 -# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L -# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L -#define RADEON_OV0_P1_X_START_END 0x0494 -#define RADEON_OV0_P2_X_START_END 0x0498 -#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 -# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL -# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L -#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C -#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C -#define RADEON_OV0_P3_X_START_END 0x049C -#define RADEON_OV0_REG_LOAD_CNTL 0x0410 -# define RADEON_REG_LD_CTL_LOCK 0x00000001L -# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L -# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L -# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L -# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L -#define RADEON_OV0_SCALE_CNTL 0x0420 -# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L -# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L -# define RADEON_SCALER_SIGNED_UV 0x00000010L -# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L -# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L -# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L -# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L -# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L -# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L -# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L -# define RADEON_SCALER_SOURCE_15BPP 0x00000300L -# define RADEON_SCALER_SOURCE_16BPP 0x00000400L -# define RADEON_SCALER_SOURCE_32BPP 0x00000600L -# define RADEON_SCALER_SOURCE_YUV9 0x00000900L -# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L -# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L -# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L -# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L -# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L -# define RADEON_SCALER_CRTC_SEL 0x00004000L -# define RADEON_SCALER_SMART_SWITCH 0x00008000L -# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L -# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L -# define RADEON_SCALER_DIS_LIMIT 0x08000000L -# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L -# define RADEON_SCALER_INT_EMU 0x20000000L -# define RADEON_SCALER_ENABLE 0x40000000L -# define RADEON_SCALER_SOFT_RESET 0x80000000L -#define RADEON_OV0_STEP_BY 0x0484 -#define RADEON_OV0_TEST 0x04F8 -#define RADEON_OV0_V_INC 0x0424 -#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 -# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L -#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 -# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L -#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 -# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L -#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C -#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 -#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 -#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 -#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 -#define RADEON_OV0_Y_X_START 0x0400 -#define RADEON_OV0_Y_X_END 0x0404 -#define RADEON_OV1_Y_X_START 0x0600 -#define RADEON_OV1_Y_X_END 0x0604 -#define RADEON_OVR_CLR 0x0230 -#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 -#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 - -/* first capture unit */ - -#define RADEON_CAP0_BUF0_OFFSET 0x0920 -#define RADEON_CAP0_BUF1_OFFSET 0x0924 -#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 -#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C - -#define RADEON_CAP0_BUF_PITCH 0x0930 -#define RADEON_CAP0_V_WINDOW 0x0934 -#define RADEON_CAP0_H_WINDOW 0x0938 -#define RADEON_CAP0_VBI0_OFFSET 0x093C -#define RADEON_CAP0_VBI1_OFFSET 0x0940 -#define RADEON_CAP0_VBI_V_WINDOW 0x0944 -#define RADEON_CAP0_VBI_H_WINDOW 0x0948 -#define RADEON_CAP0_PORT_MODE_CNTL 0x094C -#define RADEON_CAP0_TRIG_CNTL 0x0950 -#define RADEON_CAP0_DEBUG 0x0954 -#define RADEON_CAP0_CONFIG 0x0958 -# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 -# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 -# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 -# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 -# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 -# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 -# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 -# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 -# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 -# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 -# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 -# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 -# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 -# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 -# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 -# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 -# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 -# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 -# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 -# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 -# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 -# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 -# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 -# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 -# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 -# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 -# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 -# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 -# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 -# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 -# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 -# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 -# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 -#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C -#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 -#define RADEON_CAP0_ANC_H_WINDOW 0x0964 -#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 -#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C -#define RADEON_CAP0_BUF_STATUS 0x0970 -/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ -/* #define RADEON_CAP0_XSHARPNESS 0x097C */ -#define RADEON_CAP0_VBI2_OFFSET 0x0980 -#define RADEON_CAP0_VBI3_OFFSET 0x0984 -#define RADEON_CAP0_ANC2_OFFSET 0x0988 -#define RADEON_CAP0_ANC3_OFFSET 0x098C -#define RADEON_VID_BUFFER_CONTROL 0x0900 - -/* second capture unit */ - -#define RADEON_CAP1_BUF0_OFFSET 0x0990 -#define RADEON_CAP1_BUF1_OFFSET 0x0994 -#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 -#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C - -#define RADEON_CAP1_BUF_PITCH 0x09A0 -#define RADEON_CAP1_V_WINDOW 0x09A4 -#define RADEON_CAP1_H_WINDOW 0x09A8 -#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC -#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 -#define RADEON_CAP1_VBI_V_WINDOW 0x09B4 -#define RADEON_CAP1_VBI_H_WINDOW 0x09B8 -#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC -#define RADEON_CAP1_TRIG_CNTL 0x09C0 -#define RADEON_CAP1_DEBUG 0x09C4 -#define RADEON_CAP1_CONFIG 0x09C8 -#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC -#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 -#define RADEON_CAP1_ANC_H_WINDOW 0x09D4 -#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 -#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC -#define RADEON_CAP1_BUF_STATUS 0x09E0 -#define RADEON_CAP1_DWNSC_XRATIO 0x09E8 -#define RADEON_CAP1_XSHARPNESS 0x09EC - -/* misc multimedia registers */ - -#define RADEON_IDCT_RUNS 0x1F80 -#define RADEON_IDCT_LEVELS 0x1F84 -#define RADEON_IDCT_CONTROL 0x1FBC -#define RADEON_IDCT_AUTH_CONTROL 0x1F88 -#define RADEON_IDCT_AUTH 0x1F8C - -#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ -# define RADEON_P2PLL_RESET (1 << 0) -# define RADEON_P2PLL_SLEEP (1 << 1) -# define RADEON_P2PLL_PVG_MASK (7 << 11) -# define RADEON_P2PLL_PVG_SHIFT 11 -# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) -# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define RADEON_P2PLL_DIV_0 0x002c -# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff -# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 -#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ -# define RADEON_P2PLL_REF_DIV_MASK 0x03ff -# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ -# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) -# define R300_PPLL_REF_DIV_ACC_SHIFT 18 -#define RADEON_PALETTE_DATA 0x00b4 -#define RADEON_PALETTE_30_DATA 0x00b8 -#define RADEON_PALETTE_INDEX 0x00b0 -#define RADEON_PCI_GART_PAGE 0x017c -#define RADEON_PIXCLKS_CNTL 0x002d -# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 -# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 -# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 -# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 -# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 -# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) -# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) -# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) -# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -# define R300_DVOCLK_ALWAYS_ONb (1 << 10) -# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) -# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) -# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) -# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) -# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) -# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) -#define RADEON_PLANE_3D_MASK_C 0x1d44 -#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ -# define RADEON_PLL_MASK_READ_B (1 << 9) -#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ -#define RADEON_PMI_DATA 0x0f63 /* PCI */ -#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ -#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ -#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ -#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ -#define RADEON_PPLL_CNTL 0x0002 /* PLL */ -# define RADEON_PPLL_RESET (1 << 0) -# define RADEON_PPLL_SLEEP (1 << 1) -# define RADEON_PPLL_PVG_MASK (7 << 11) -# define RADEON_PPLL_PVG_SHIFT 11 -# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) -# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ -#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ -#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ -#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ -# define RADEON_PPLL_FB3_DIV_MASK 0x07ff -# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 -#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ -# define RADEON_PPLL_REF_DIV_MASK 0x03ff -# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ -#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ - -#define RADEON_RBBM_GUICNTL 0x172c -# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) -# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) -# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) -# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) -#define RADEON_RBBM_SOFT_RESET 0x00f0 -# define RADEON_SOFT_RESET_CP (1 << 0) -# define RADEON_SOFT_RESET_HI (1 << 1) -# define RADEON_SOFT_RESET_SE (1 << 2) -# define RADEON_SOFT_RESET_RE (1 << 3) -# define RADEON_SOFT_RESET_PP (1 << 4) -# define RADEON_SOFT_RESET_E2 (1 << 5) -# define RADEON_SOFT_RESET_RB (1 << 6) -# define RADEON_SOFT_RESET_HDP (1 << 7) -#define RADEON_RBBM_STATUS 0x0e40 -# define RADEON_RBBM_FIFOCNT_MASK 0x007f -# define RADEON_RBBM_ACTIVE (1 << 31) -#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c -# define RADEON_RB2D_DC_FLUSH (3 << 0) -# define RADEON_RB2D_DC_FREE (3 << 2) -# define RADEON_RB2D_DC_FLUSH_ALL 0xf -# define RADEON_RB2D_DC_BUSY (1 << 31) -#define RADEON_RB2D_DSTCACHE_MODE 0x3428 -#define RADEON_DSTCACHE_CTLSTAT 0x1714 - -#define RADEON_RB3D_ZCACHE_MODE 0x3250 -#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 -# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 -#define RADEON_RB3D_DSTCACHE_MODE 0x3258 -# define RADEON_RB3D_DC_CACHE_ENABLE (0) -# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) -# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) -# define RADEON_RB3D_DC_CACHE_DISABLE (3) -# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) -# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) -# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) -# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) -# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) -# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) -# define RADEON_RB3D_DC_FORCE_RMW (1 << 16) -# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) -# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) - -#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C -# define RADEON_RB3D_DC_FLUSH (3 << 0) -# define RADEON_RB3D_DC_FREE (3 << 2) -# define RADEON_RB3D_DC_FLUSH_ALL 0xf -# define RADEON_RB3D_DC_BUSY (1 << 31) - -#define RADEON_REG_BASE 0x0f18 /* PCI */ -#define RADEON_REGPROG_INF 0x0f09 /* PCI */ -#define RADEON_REVISION_ID 0x0f08 /* PCI */ - -#define RADEON_SC_BOTTOM 0x164c -#define RADEON_SC_BOTTOM_RIGHT 0x16f0 -#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c -#define RADEON_SC_LEFT 0x1640 -#define RADEON_SC_RIGHT 0x1644 -#define RADEON_SC_TOP 0x1648 -#define RADEON_SC_TOP_LEFT 0x16ec -#define RADEON_SC_TOP_LEFT_C 0x1c88 -# define RADEON_SC_SIGN_MASK_LO 0x8000 -# define RADEON_SC_SIGN_MASK_HI 0x80000000 -#define RADEON_SCLK_CNTL 0x000d /* PLL */ -# define RADEON_SCLK_SRC_SEL_MASK 0x0007 -# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 -# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 -# define RADEON_SCLK_FORCEON_MASK 0xffff8000 -# define RADEON_SCLK_FORCE_DISP2 (1<<15) -# define RADEON_SCLK_FORCE_CP (1<<16) -# define RADEON_SCLK_FORCE_HDP (1<<17) -# define RADEON_SCLK_FORCE_DISP1 (1<<18) -# define RADEON_SCLK_FORCE_TOP (1<<19) -# define RADEON_SCLK_FORCE_E2 (1<<20) -# define RADEON_SCLK_FORCE_SE (1<<21) -# define RADEON_SCLK_FORCE_IDCT (1<<22) -# define RADEON_SCLK_FORCE_VIP (1<<23) -# define RADEON_SCLK_FORCE_RE (1<<24) -# define RADEON_SCLK_FORCE_PB (1<<25) -# define RADEON_SCLK_FORCE_TAM (1<<26) -# define RADEON_SCLK_FORCE_TDM (1<<27) -# define RADEON_SCLK_FORCE_RB (1<<28) -# define RADEON_SCLK_FORCE_TV_SCLK (1<<29) -# define RADEON_SCLK_FORCE_SUBPIC (1<<30) -# define RADEON_SCLK_FORCE_OV0 (1<<31) -# define R300_SCLK_FORCE_VAP (1<<21) -# define R300_SCLK_FORCE_SR (1<<25) -# define R300_SCLK_FORCE_PX (1<<26) -# define R300_SCLK_FORCE_TX (1<<27) -# define R300_SCLK_FORCE_US (1<<28) -# define R300_SCLK_FORCE_SU (1<<30) -#define R300_SCLK_CNTL2 0x1e /* PLL */ -# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) -# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) -# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) -# define R300_SCLK_FORCE_TCL (1<<13) -# define R300_SCLK_FORCE_CBA (1<<14) -# define R300_SCLK_FORCE_GA (1<<15) -#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ -# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 -# define RADEON_SCLK_MORE_FORCEON 0x0700 -#define RADEON_SDRAM_MODE_REG 0x0158 -#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ -#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ -#define RADEON_SNAPSHOT_F_COUNT 0x0244 -#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 -#define RADEON_SNAPSHOT_VIF_COUNT 0x024c -#define RADEON_SRC_OFFSET 0x15ac -#define RADEON_SRC_PITCH 0x15b0 -#define RADEON_SRC_PITCH_OFFSET 0x1428 -#define RADEON_SRC_SC_BOTTOM 0x165c -#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 -#define RADEON_SRC_SC_RIGHT 0x1654 -#define RADEON_SRC_X 0x1414 -#define RADEON_SRC_X_Y 0x1590 -#define RADEON_SRC_Y 0x1418 -#define RADEON_SRC_Y_X 0x1434 -#define RADEON_STATUS 0x0f06 /* PCI */ -#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ -#define RADEON_SUB_CLASS 0x0f0a /* PCI */ -#define RADEON_SURFACE_CNTL 0x0b00 -# define RADEON_SURF_TRANSLATION_DIS (1 << 8) -# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) -# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) -# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) -# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) -#define RADEON_SURFACE0_INFO 0x0b0c -# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) -# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) -# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) -# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) -# define R200_SURF_TILE_NONE (0 << 16) -# define R200_SURF_TILE_COLOR_MACRO (1 << 16) -# define R200_SURF_TILE_COLOR_MICRO (2 << 16) -# define R200_SURF_TILE_COLOR_BOTH (3 << 16) -# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) -# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) -# define R300_SURF_TILE_NONE (0 << 16) -# define R300_SURF_TILE_COLOR_MACRO (1 << 16) -# define R300_SURF_TILE_DEPTH_32BPP (2 << 16) -# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) -# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) -# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) -# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) -#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 -#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 -#define RADEON_SURFACE1_INFO 0x0b1c -#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 -#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 -#define RADEON_SURFACE2_INFO 0x0b2c -#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 -#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 -#define RADEON_SURFACE3_INFO 0x0b3c -#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 -#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 -#define RADEON_SURFACE4_INFO 0x0b4c -#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 -#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 -#define RADEON_SURFACE5_INFO 0x0b5c -#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 -#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 -#define RADEON_SURFACE6_INFO 0x0b6c -#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 -#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 -#define RADEON_SURFACE7_INFO 0x0b7c -#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 -#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 -#define RADEON_SW_SEMAPHORE 0x013c - -#define RADEON_TEST_DEBUG_CNTL 0x0120 -#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 - -#define RADEON_TEST_DEBUG_MUX 0x0124 -#define RADEON_TEST_DEBUG_OUT 0x012c -#define RADEON_TMDS_PLL_CNTL 0x02a8 -#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 -# define RADEON_TMDS_TRANSMITTER_PLLEN 1 -# define RADEON_TMDS_TRANSMITTER_PLLRST 2 -#define RADEON_TRAIL_BRES_DEC 0x1614 -#define RADEON_TRAIL_BRES_ERR 0x160c -#define RADEON_TRAIL_BRES_INC 0x1610 -#define RADEON_TRAIL_X 0x1618 -#define RADEON_TRAIL_X_SUB 0x1620 - -#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ -# define RADEON_VCLK_SRC_SEL_MASK 0x03 -# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 -# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 -# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 -# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 -# define RADEON_PIXCLK_ALWAYS_ONb (1<<6) -# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) -# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) - -#define RADEON_VENDOR_ID 0x0f00 /* PCI */ -#define RADEON_VGA_DDA_CONFIG 0x02e8 -#define RADEON_VGA_DDA_ON_OFF 0x02ec -#define RADEON_VID_BUFFER_CONTROL 0x0900 -#define RADEON_VIDEOMUX_CNTL 0x0190 - - /* VIP bus */ -#define RADEON_VIPH_CH0_DATA 0x0c00 -#define RADEON_VIPH_CH1_DATA 0x0c04 -#define RADEON_VIPH_CH2_DATA 0x0c08 -#define RADEON_VIPH_CH3_DATA 0x0c0c -#define RADEON_VIPH_CH0_ADDR 0x0c10 -#define RADEON_VIPH_CH1_ADDR 0x0c14 -#define RADEON_VIPH_CH2_ADDR 0x0c18 -#define RADEON_VIPH_CH3_ADDR 0x0c1c -#define RADEON_VIPH_CH0_SBCNT 0x0c20 -#define RADEON_VIPH_CH1_SBCNT 0x0c24 -#define RADEON_VIPH_CH2_SBCNT 0x0c28 -#define RADEON_VIPH_CH3_SBCNT 0x0c2c -#define RADEON_VIPH_CH0_ABCNT 0x0c30 -#define RADEON_VIPH_CH1_ABCNT 0x0c34 -#define RADEON_VIPH_CH2_ABCNT 0x0c38 -#define RADEON_VIPH_CH3_ABCNT 0x0c3c -#define RADEON_VIPH_CONTROL 0x0c40 -# define RADEON_VIP_BUSY 0 -# define RADEON_VIP_IDLE 1 -# define RADEON_VIP_RESET 2 -# define RADEON_VIPH_EN (1 << 21) -#define RADEON_VIPH_DV_LAT 0x0c44 -#define RADEON_VIPH_BM_CHUNK 0x0c48 -#define RADEON_VIPH_DV_INT 0x0c4c -#define RADEON_VIPH_TIMEOUT_STAT 0x0c50 -#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 -#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 -#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 - -#define RADEON_VIPH_REG_DATA 0x0084 -#define RADEON_VIPH_REG_ADDR 0x0080 - - -#define RADEON_WAIT_UNTIL 0x1720 -# define RADEON_WAIT_CRTC_PFLIP (1 << 0) -# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) -# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) -# define RADEON_WAIT_CRTC_VLINE (1 << 3) -# define RADEON_WAIT_DMA_VID_IDLE (1 << 8) -# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) -# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ -# define RADEON_WAIT_OV0_FLIP (1 << 11) -# define RADEON_WAIT_AGP_FLUSH (1 << 13) -# define RADEON_WAIT_2D_IDLE (1 << 14) -# define RADEON_WAIT_3D_IDLE (1 << 15) -# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) -# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) -# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) -# define RADEON_CMDFIFO_ENTRIES_SHIFT 10 -# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f -# define RADEON_WAIT_VAP_IDLE (1 << 28) -# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) -# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) -# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) - -#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ -#define RADEON_XCLK_CNTL 0x000d /* PLL */ -#define RADEON_XDLL_CNTL 0x000c /* PLL */ -#define RADEON_XPLL_CNTL 0x000b /* PLL */ - - - - /* Registers for 3D/TCL */ -#define RADEON_PP_BORDER_COLOR_0 0x1d40 -#define RADEON_PP_BORDER_COLOR_1 0x1d44 -#define RADEON_PP_BORDER_COLOR_2 0x1d48 -#define RADEON_PP_CNTL 0x1c38 -# define RADEON_STIPPLE_ENABLE (1 << 0) -# define RADEON_SCISSOR_ENABLE (1 << 1) -# define RADEON_PATTERN_ENABLE (1 << 2) -# define RADEON_SHADOW_ENABLE (1 << 3) -# define RADEON_TEX_ENABLE_MASK (0xf << 4) -# define RADEON_TEX_0_ENABLE (1 << 4) -# define RADEON_TEX_1_ENABLE (1 << 5) -# define RADEON_TEX_2_ENABLE (1 << 6) -# define RADEON_TEX_3_ENABLE (1 << 7) -# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) -# define RADEON_TEX_BLEND_0_ENABLE (1 << 12) -# define RADEON_TEX_BLEND_1_ENABLE (1 << 13) -# define RADEON_TEX_BLEND_2_ENABLE (1 << 14) -# define RADEON_TEX_BLEND_3_ENABLE (1 << 15) -# define RADEON_PLANAR_YUV_ENABLE (1 << 20) -# define RADEON_SPECULAR_ENABLE (1 << 21) -# define RADEON_FOG_ENABLE (1 << 22) -# define RADEON_ALPHA_TEST_ENABLE (1 << 23) -# define RADEON_ANTI_ALIAS_NONE (0 << 24) -# define RADEON_ANTI_ALIAS_LINE (1 << 24) -# define RADEON_ANTI_ALIAS_POLY (2 << 24) -# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) -# define RADEON_BUMP_MAP_ENABLE (1 << 26) -# define RADEON_BUMPED_MAP_T0 (0 << 27) -# define RADEON_BUMPED_MAP_T1 (1 << 27) -# define RADEON_BUMPED_MAP_T2 (2 << 27) -# define RADEON_TEX_3D_ENABLE_0 (1 << 29) -# define RADEON_TEX_3D_ENABLE_1 (1 << 30) -# define RADEON_MC_ENABLE (1 << 31) -#define RADEON_PP_FOG_COLOR 0x1c18 -# define RADEON_FOG_COLOR_MASK 0x00ffffff -# define RADEON_FOG_VERTEX (0 << 24) -# define RADEON_FOG_TABLE (1 << 24) -# define RADEON_FOG_USE_DEPTH (0 << 25) -# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) -# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) -#define RADEON_PP_LUM_MATRIX 0x1d00 -#define RADEON_PP_MISC 0x1c14 -# define RADEON_REF_ALPHA_MASK 0x000000ff -# define RADEON_ALPHA_TEST_FAIL (0 << 8) -# define RADEON_ALPHA_TEST_LESS (1 << 8) -# define RADEON_ALPHA_TEST_LEQUAL (2 << 8) -# define RADEON_ALPHA_TEST_EQUAL (3 << 8) -# define RADEON_ALPHA_TEST_GEQUAL (4 << 8) -# define RADEON_ALPHA_TEST_GREATER (5 << 8) -# define RADEON_ALPHA_TEST_NEQUAL (6 << 8) -# define RADEON_ALPHA_TEST_PASS (7 << 8) -# define RADEON_ALPHA_TEST_OP_MASK (7 << 8) -# define RADEON_CHROMA_FUNC_FAIL (0 << 16) -# define RADEON_CHROMA_FUNC_PASS (1 << 16) -# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) -# define RADEON_CHROMA_FUNC_EQUAL (3 << 16) -# define RADEON_CHROMA_KEY_NEAREST (0 << 18) -# define RADEON_CHROMA_KEY_ZERO (1 << 18) -# define RADEON_SHADOW_ID_AUTO_INC (1 << 20) -# define RADEON_SHADOW_FUNC_EQUAL (0 << 21) -# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) -# define RADEON_SHADOW_PASS_1 (0 << 22) -# define RADEON_SHADOW_PASS_2 (1 << 22) -# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) -# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) -#define RADEON_PP_ROT_MATRIX_0 0x1d58 -#define RADEON_PP_ROT_MATRIX_1 0x1d5c -#define RADEON_PP_TXFILTER_0 0x1c54 -#define RADEON_PP_TXFILTER_1 0x1c6c -#define RADEON_PP_TXFILTER_2 0x1c84 -# define RADEON_MAG_FILTER_NEAREST (0 << 0) -# define RADEON_MAG_FILTER_LINEAR (1 << 0) -# define RADEON_MAG_FILTER_MASK (1 << 0) -# define RADEON_MIN_FILTER_NEAREST (0 << 1) -# define RADEON_MIN_FILTER_LINEAR (1 << 1) -# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) -# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) -# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) -# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) -# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) -# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) -# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) -# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) -# define RADEON_MIN_FILTER_MASK (15 << 1) -# define RADEON_MAX_ANISO_1_TO_1 (0 << 5) -# define RADEON_MAX_ANISO_2_TO_1 (1 << 5) -# define RADEON_MAX_ANISO_4_TO_1 (2 << 5) -# define RADEON_MAX_ANISO_8_TO_1 (3 << 5) -# define RADEON_MAX_ANISO_16_TO_1 (4 << 5) -# define RADEON_MAX_ANISO_MASK (7 << 5) -# define RADEON_LOD_BIAS_MASK (0xff << 8) -# define RADEON_LOD_BIAS_SHIFT 8 -# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) -# define RADEON_MAX_MIP_LEVEL_SHIFT 16 -# define RADEON_YUV_TO_RGB (1 << 20) -# define RADEON_YUV_TEMPERATURE_COOL (0 << 21) -# define RADEON_YUV_TEMPERATURE_HOT (1 << 21) -# define RADEON_YUV_TEMPERATURE_MASK (1 << 21) -# define RADEON_WRAPEN_S (1 << 22) -# define RADEON_CLAMP_S_WRAP (0 << 23) -# define RADEON_CLAMP_S_MIRROR (1 << 23) -# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) -# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) -# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) -# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) -# define RADEON_CLAMP_S_CLAMP_GL (6 << 23) -# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) -# define RADEON_CLAMP_S_MASK (7 << 23) -# define RADEON_WRAPEN_T (1 << 26) -# define RADEON_CLAMP_T_WRAP (0 << 27) -# define RADEON_CLAMP_T_MIRROR (1 << 27) -# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) -# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) -# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) -# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) -# define RADEON_CLAMP_T_CLAMP_GL (6 << 27) -# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) -# define RADEON_CLAMP_T_MASK (7 << 27) -# define RADEON_BORDER_MODE_OGL (0 << 31) -# define RADEON_BORDER_MODE_D3D (1 << 31) -#define RADEON_PP_TXFORMAT_0 0x1c58 -#define RADEON_PP_TXFORMAT_1 0x1c70 -#define RADEON_PP_TXFORMAT_2 0x1c88 -# define RADEON_TXFORMAT_I8 (0 << 0) -# define RADEON_TXFORMAT_AI88 (1 << 0) -# define RADEON_TXFORMAT_RGB332 (2 << 0) -# define RADEON_TXFORMAT_ARGB1555 (3 << 0) -# define RADEON_TXFORMAT_RGB565 (4 << 0) -# define RADEON_TXFORMAT_ARGB4444 (5 << 0) -# define RADEON_TXFORMAT_ARGB8888 (6 << 0) -# define RADEON_TXFORMAT_RGBA8888 (7 << 0) -# define RADEON_TXFORMAT_Y8 (8 << 0) -# define RADEON_TXFORMAT_VYUY422 (10 << 0) -# define RADEON_TXFORMAT_YVYU422 (11 << 0) -# define RADEON_TXFORMAT_DXT1 (12 << 0) -# define RADEON_TXFORMAT_DXT23 (14 << 0) -# define RADEON_TXFORMAT_DXT45 (15 << 0) -# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) -# define RADEON_TXFORMAT_FORMAT_SHIFT 0 -# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) -# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) -# define RADEON_TXFORMAT_NON_POWER2 (1 << 7) -# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) -# define RADEON_TXFORMAT_WIDTH_SHIFT 8 -# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) -# define RADEON_TXFORMAT_HEIGHT_SHIFT 12 -# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) -# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 -# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) -# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 -# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) -# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) -# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) -# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) -# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) -# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) -# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) -# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) -# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) -# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) -# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) -# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) -#define RADEON_PP_CUBIC_FACES_0 0x1d24 -#define RADEON_PP_CUBIC_FACES_1 0x1d28 -#define RADEON_PP_CUBIC_FACES_2 0x1d2c -# define RADEON_FACE_WIDTH_1_SHIFT 0 -# define RADEON_FACE_HEIGHT_1_SHIFT 4 -# define RADEON_FACE_WIDTH_1_MASK (0xf << 0) -# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) -# define RADEON_FACE_WIDTH_2_SHIFT 8 -# define RADEON_FACE_HEIGHT_2_SHIFT 12 -# define RADEON_FACE_WIDTH_2_MASK (0xf << 8) -# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) -# define RADEON_FACE_WIDTH_3_SHIFT 16 -# define RADEON_FACE_HEIGHT_3_SHIFT 20 -# define RADEON_FACE_WIDTH_3_MASK (0xf << 16) -# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) -# define RADEON_FACE_WIDTH_4_SHIFT 24 -# define RADEON_FACE_HEIGHT_4_SHIFT 28 -# define RADEON_FACE_WIDTH_4_MASK (0xf << 24) -# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) - -#define RADEON_PP_TXOFFSET_0 0x1c5c -#define RADEON_PP_TXOFFSET_1 0x1c74 -#define RADEON_PP_TXOFFSET_2 0x1c8c -# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) -# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) -# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) -# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) -# define RADEON_TXO_MACRO_LINEAR (0 << 2) -# define RADEON_TXO_MACRO_TILE (1 << 2) -# define RADEON_TXO_MICRO_LINEAR (0 << 3) -# define RADEON_TXO_MICRO_TILE_X2 (1 << 3) -# define RADEON_TXO_MICRO_TILE_OPT (2 << 3) -# define RADEON_TXO_OFFSET_MASK 0xffffffe0 -# define RADEON_TXO_OFFSET_SHIFT 5 - -#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ -#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 -#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 -#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc -#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 -#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 -#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 -#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 -#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c -#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 -#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 -#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 -#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c -#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 -#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 - -#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ -#define RADEON_PP_TEX_SIZE_1 0x1d0c -#define RADEON_PP_TEX_SIZE_2 0x1d14 -# define RADEON_TEX_USIZE_MASK (0x7ff << 0) -# define RADEON_TEX_USIZE_SHIFT 0 -# define RADEON_TEX_VSIZE_MASK (0x7ff << 16) -# define RADEON_TEX_VSIZE_SHIFT 16 -# define RADEON_SIGNED_RGB_MASK (1 << 30) -# define RADEON_SIGNED_RGB_SHIFT 30 -# define RADEON_SIGNED_ALPHA_MASK (1 << 31) -# define RADEON_SIGNED_ALPHA_SHIFT 31 -#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ -#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ -#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ -/* note: bits 13-5: 32 byte aligned stride of texture map */ - -#define RADEON_PP_TXCBLEND_0 0x1c60 -#define RADEON_PP_TXCBLEND_1 0x1c78 -#define RADEON_PP_TXCBLEND_2 0x1c90 -# define RADEON_COLOR_ARG_A_SHIFT 0 -# define RADEON_COLOR_ARG_A_MASK (0x1f << 0) -# define RADEON_COLOR_ARG_A_ZERO (0 << 0) -# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) -# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) -# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) -# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) -# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) -# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) -# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) -# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) -# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) -# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) -# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) -# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) -# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) -# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) -# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) -# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) -# define RADEON_COLOR_ARG_B_SHIFT 5 -# define RADEON_COLOR_ARG_B_MASK (0x1f << 5) -# define RADEON_COLOR_ARG_B_ZERO (0 << 5) -# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) -# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) -# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) -# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) -# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) -# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) -# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) -# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) -# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) -# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) -# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) -# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) -# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) -# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) -# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) -# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) -# define RADEON_COLOR_ARG_C_SHIFT 10 -# define RADEON_COLOR_ARG_C_MASK (0x1f << 10) -# define RADEON_COLOR_ARG_C_ZERO (0 << 10) -# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) -# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) -# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) -# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) -# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) -# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) -# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) -# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) -# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) -# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) -# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) -# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) -# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) -# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) -# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) -# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) -# define RADEON_COMP_ARG_A (1 << 15) -# define RADEON_COMP_ARG_A_SHIFT 15 -# define RADEON_COMP_ARG_B (1 << 16) -# define RADEON_COMP_ARG_B_SHIFT 16 -# define RADEON_COMP_ARG_C (1 << 17) -# define RADEON_COMP_ARG_C_SHIFT 17 -# define RADEON_BLEND_CTL_MASK (7 << 18) -# define RADEON_BLEND_CTL_ADD (0 << 18) -# define RADEON_BLEND_CTL_SUBTRACT (1 << 18) -# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) -# define RADEON_BLEND_CTL_BLEND (3 << 18) -# define RADEON_BLEND_CTL_DOT3 (4 << 18) -# define RADEON_SCALE_SHIFT 21 -# define RADEON_SCALE_MASK (3 << 21) -# define RADEON_SCALE_1X (0 << 21) -# define RADEON_SCALE_2X (1 << 21) -# define RADEON_SCALE_4X (2 << 21) -# define RADEON_CLAMP_TX (1 << 23) -# define RADEON_T0_EQ_TCUR (1 << 24) -# define RADEON_T1_EQ_TCUR (1 << 25) -# define RADEON_T2_EQ_TCUR (1 << 26) -# define RADEON_T3_EQ_TCUR (1 << 27) -# define RADEON_COLOR_ARG_MASK 0x1f -# define RADEON_COMP_ARG_SHIFT 15 -#define RADEON_PP_TXABLEND_0 0x1c64 -#define RADEON_PP_TXABLEND_1 0x1c7c -#define RADEON_PP_TXABLEND_2 0x1c94 -# define RADEON_ALPHA_ARG_A_SHIFT 0 -# define RADEON_ALPHA_ARG_A_MASK (0xf << 0) -# define RADEON_ALPHA_ARG_A_ZERO (0 << 0) -# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) -# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) -# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) -# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) -# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) -# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) -# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) -# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) -# define RADEON_ALPHA_ARG_B_SHIFT 4 -# define RADEON_ALPHA_ARG_B_MASK (0xf << 4) -# define RADEON_ALPHA_ARG_B_ZERO (0 << 4) -# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) -# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) -# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) -# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) -# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) -# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) -# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) -# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) -# define RADEON_ALPHA_ARG_C_SHIFT 8 -# define RADEON_ALPHA_ARG_C_MASK (0xf << 8) -# define RADEON_ALPHA_ARG_C_ZERO (0 << 8) -# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) -# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) -# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) -# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) -# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) -# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) -# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) -# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) -# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) -# define RADEON_ALPHA_ARG_MASK 0xf - -#define RADEON_PP_TFACTOR_0 0x1c68 -#define RADEON_PP_TFACTOR_1 0x1c80 -#define RADEON_PP_TFACTOR_2 0x1c98 - -#define RADEON_RB3D_BLENDCNTL 0x1c20 -# define RADEON_COMB_FCN_MASK (3 << 12) -# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) -# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) -# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) -# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) -# define RADEON_SRC_BLEND_GL_ZERO (32 << 16) -# define RADEON_SRC_BLEND_GL_ONE (33 << 16) -# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) -# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) -# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) -# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) -# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) -# define RADEON_SRC_BLEND_MASK (63 << 16) -# define RADEON_DST_BLEND_GL_ZERO (32 << 24) -# define RADEON_DST_BLEND_GL_ONE (33 << 24) -# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) -# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) -# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) -# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) -# define RADEON_DST_BLEND_MASK (63 << 24) -#define RADEON_RB3D_CNTL 0x1c3c -# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) -# define RADEON_PLANE_MASK_ENABLE (1 << 1) -# define RADEON_DITHER_ENABLE (1 << 2) -# define RADEON_ROUND_ENABLE (1 << 3) -# define RADEON_SCALE_DITHER_ENABLE (1 << 4) -# define RADEON_DITHER_INIT (1 << 5) -# define RADEON_ROP_ENABLE (1 << 6) -# define RADEON_STENCIL_ENABLE (1 << 7) -# define RADEON_Z_ENABLE (1 << 8) -# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) -# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) -# define RADEON_COLOR_FORMAT_RGB565 (4 << 10) -# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) -# define RADEON_COLOR_FORMAT_RGB332 (7 << 10) -# define RADEON_COLOR_FORMAT_Y8 (8 << 10) -# define RADEON_COLOR_FORMAT_RGB8 (9 << 10) -# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) -# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) -# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) -# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) -# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) -#define RADEON_RB3D_COLOROFFSET 0x1c40 -# define RADEON_COLOROFFSET_MASK 0xfffffff0 -#define RADEON_RB3D_COLORPITCH 0x1c48 -# define RADEON_COLORPITCH_MASK 0x000001ff8 -# define RADEON_COLOR_TILE_ENABLE (1 << 16) -# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) -# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) -# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) -# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) -#define RADEON_RB3D_DEPTHOFFSET 0x1c24 -#define RADEON_RB3D_DEPTHPITCH 0x1c28 -# define RADEON_DEPTHPITCH_MASK 0x00001ff8 -# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) -# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) -# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) -#define RADEON_RB3D_PLANEMASK 0x1d84 -#define RADEON_RB3D_ROPCNTL 0x1d80 -# define RADEON_ROP_MASK (15 << 8) -# define RADEON_ROP_CLEAR (0 << 8) -# define RADEON_ROP_NOR (1 << 8) -# define RADEON_ROP_AND_INVERTED (2 << 8) -# define RADEON_ROP_COPY_INVERTED (3 << 8) -# define RADEON_ROP_AND_REVERSE (4 << 8) -# define RADEON_ROP_INVERT (5 << 8) -# define RADEON_ROP_XOR (6 << 8) -# define RADEON_ROP_NAND (7 << 8) -# define RADEON_ROP_AND (8 << 8) -# define RADEON_ROP_EQUIV (9 << 8) -# define RADEON_ROP_NOOP (10 << 8) -# define RADEON_ROP_OR_INVERTED (11 << 8) -# define RADEON_ROP_COPY (12 << 8) -# define RADEON_ROP_OR_REVERSE (13 << 8) -# define RADEON_ROP_OR (14 << 8) -# define RADEON_ROP_SET (15 << 8) -#define RADEON_RB3D_STENCILREFMASK 0x1d7c -# define RADEON_STENCIL_REF_SHIFT 0 -# define RADEON_STENCIL_REF_MASK (0xff << 0) -# define RADEON_STENCIL_MASK_SHIFT 16 -# define RADEON_STENCIL_VALUE_MASK (0xff << 16) -# define RADEON_STENCIL_WRITEMASK_SHIFT 24 -# define RADEON_STENCIL_WRITE_MASK (0xff << 24) -#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c -# define RADEON_DEPTH_FORMAT_MASK (0xf << 0) -# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) -# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) -# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) -# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) -# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) -# define RADEON_Z_TEST_NEVER (0 << 4) -# define RADEON_Z_TEST_LESS (1 << 4) -# define RADEON_Z_TEST_LEQUAL (2 << 4) -# define RADEON_Z_TEST_EQUAL (3 << 4) -# define RADEON_Z_TEST_GEQUAL (4 << 4) -# define RADEON_Z_TEST_GREATER (5 << 4) -# define RADEON_Z_TEST_NEQUAL (6 << 4) -# define RADEON_Z_TEST_ALWAYS (7 << 4) -# define RADEON_Z_TEST_MASK (7 << 4) -# define RADEON_STENCIL_TEST_NEVER (0 << 12) -# define RADEON_STENCIL_TEST_LESS (1 << 12) -# define RADEON_STENCIL_TEST_LEQUAL (2 << 12) -# define RADEON_STENCIL_TEST_EQUAL (3 << 12) -# define RADEON_STENCIL_TEST_GEQUAL (4 << 12) -# define RADEON_STENCIL_TEST_GREATER (5 << 12) -# define RADEON_STENCIL_TEST_NEQUAL (6 << 12) -# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) -# define RADEON_STENCIL_TEST_MASK (0x7 << 12) -# define RADEON_STENCIL_FAIL_KEEP (0 << 16) -# define RADEON_STENCIL_FAIL_ZERO (1 << 16) -# define RADEON_STENCIL_FAIL_REPLACE (2 << 16) -# define RADEON_STENCIL_FAIL_INC (3 << 16) -# define RADEON_STENCIL_FAIL_DEC (4 << 16) -# define RADEON_STENCIL_FAIL_INVERT (5 << 16) -# define RADEON_STENCIL_FAIL_MASK (0x7 << 16) -# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) -# define RADEON_STENCIL_ZPASS_ZERO (1 << 20) -# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) -# define RADEON_STENCIL_ZPASS_INC (3 << 20) -# define RADEON_STENCIL_ZPASS_DEC (4 << 20) -# define RADEON_STENCIL_ZPASS_INVERT (5 << 20) -# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) -# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) -# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) -# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) -# define RADEON_STENCIL_ZFAIL_INC (3 << 24) -# define RADEON_STENCIL_ZFAIL_DEC (4 << 24) -# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) -# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) -# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) -# define RADEON_FORCE_Z_DIRTY (1 << 29) -# define RADEON_Z_WRITE_ENABLE (1 << 30) -#define RADEON_RE_LINE_PATTERN 0x1cd0 -# define RADEON_LINE_PATTERN_MASK 0x0000ffff -# define RADEON_LINE_REPEAT_COUNT_SHIFT 16 -# define RADEON_LINE_PATTERN_START_SHIFT 24 -# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) -# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) -# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) -#define RADEON_RE_LINE_STATE 0x1cd4 -# define RADEON_LINE_CURRENT_PTR_SHIFT 0 -# define RADEON_LINE_CURRENT_COUNT_SHIFT 8 -#define RADEON_RE_MISC 0x26c4 -# define RADEON_STIPPLE_COORD_MASK 0x1f -# define RADEON_STIPPLE_X_OFFSET_SHIFT 0 -# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) -# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 -# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) -# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) -# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) -#define RADEON_RE_SOLID_COLOR 0x1c1c -#define RADEON_RE_TOP_LEFT 0x26c0 -# define RADEON_RE_LEFT_SHIFT 0 -# define RADEON_RE_TOP_SHIFT 16 -#define RADEON_RE_WIDTH_HEIGHT 0x1c44 -# define RADEON_RE_WIDTH_SHIFT 0 -# define RADEON_RE_HEIGHT_SHIFT 16 - -#define RADEON_SE_CNTL 0x1c4c -# define RADEON_FFACE_CULL_CW (0 << 0) -# define RADEON_FFACE_CULL_CCW (1 << 0) -# define RADEON_FFACE_CULL_DIR_MASK (1 << 0) -# define RADEON_BFACE_CULL (0 << 1) -# define RADEON_BFACE_SOLID (3 << 1) -# define RADEON_FFACE_CULL (0 << 3) -# define RADEON_FFACE_SOLID (3 << 3) -# define RADEON_FFACE_CULL_MASK (3 << 3) -# define RADEON_BADVTX_CULL_DISABLE (1 << 5) -# define RADEON_FLAT_SHADE_VTX_0 (0 << 6) -# define RADEON_FLAT_SHADE_VTX_1 (1 << 6) -# define RADEON_FLAT_SHADE_VTX_2 (2 << 6) -# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) -# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) -# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) -# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) -# define RADEON_DIFFUSE_SHADE_MASK (3 << 8) -# define RADEON_ALPHA_SHADE_SOLID (0 << 10) -# define RADEON_ALPHA_SHADE_FLAT (1 << 10) -# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) -# define RADEON_ALPHA_SHADE_MASK (3 << 10) -# define RADEON_SPECULAR_SHADE_SOLID (0 << 12) -# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) -# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) -# define RADEON_SPECULAR_SHADE_MASK (3 << 12) -# define RADEON_FOG_SHADE_SOLID (0 << 14) -# define RADEON_FOG_SHADE_FLAT (1 << 14) -# define RADEON_FOG_SHADE_GOURAUD (2 << 14) -# define RADEON_FOG_SHADE_MASK (3 << 14) -# define RADEON_ZBIAS_ENABLE_POINT (1 << 16) -# define RADEON_ZBIAS_ENABLE_LINE (1 << 17) -# define RADEON_ZBIAS_ENABLE_TRI (1 << 18) -# define RADEON_WIDELINE_ENABLE (1 << 20) -# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) -# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) -# define RADEON_VTX_PIX_CENTER_D3D (0 << 27) -# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) -# define RADEON_ROUND_MODE_TRUNC (0 << 28) -# define RADEON_ROUND_MODE_ROUND (1 << 28) -# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) -# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) -# define RADEON_ROUND_PREC_16TH_PIX (0 << 30) -# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) -# define RADEON_ROUND_PREC_4TH_PIX (2 << 30) -# define RADEON_ROUND_PREC_HALF_PIX (3 << 30) -#define R200_RE_CNTL 0x1c50 -# define R200_STIPPLE_ENABLE 0x1 -# define R200_SCISSOR_ENABLE 0x2 -# define R200_PATTERN_ENABLE 0x4 -# define R200_PERSPECTIVE_ENABLE 0x8 -# define R200_POINT_SMOOTH 0x20 -# define R200_VTX_STQ0_D3D 0x00010000 -# define R200_VTX_STQ1_D3D 0x00040000 -# define R200_VTX_STQ2_D3D 0x00100000 -# define R200_VTX_STQ3_D3D 0x00400000 -# define R200_VTX_STQ4_D3D 0x01000000 -# define R200_VTX_STQ5_D3D 0x04000000 -#define R200_RE_SCISSOR_TL_0 0x1cd8 -#define R200_RE_SCISSOR_BR_0 0x1cdc -#define R200_RE_SCISSOR_TL_1 0x1ce0 -#define R200_RE_SCISSOR_BR_1 0x1ce4 -#define R200_RE_SCISSOR_TL_2 0x1ce8 -#define R200_RE_SCISSOR_BR_2 0x1cec -# define R200_SCISSOR_X_SHIFT 0 -# define R200_SCISSOR_Y_SHIFT 16 -#define RADEON_SE_CNTL_STATUS 0x2140 -# define RADEON_VC_NO_SWAP (0 << 0) -# define RADEON_VC_16BIT_SWAP (1 << 0) -# define RADEON_VC_32BIT_SWAP (2 << 0) -# define RADEON_VC_HALF_DWORD_SWAP (3 << 0) -# define RADEON_TCL_BYPASS (1 << 8) -#define RADEON_SE_COORD_FMT 0x1c50 -# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) -# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) -# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) -# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) -# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) -# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) -# define RADEON_VTX_W0_NORMALIZE (1 << 12) -# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) -# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) -# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) -# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) -# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) -# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) -# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) -#define RADEON_SE_LINE_WIDTH 0x1db8 -#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c -# define RADEON_LIGHTING_ENABLE (1 << 0) -# define RADEON_LIGHT_IN_MODELSPACE (1 << 1) -# define RADEON_LOCAL_VIEWER (1 << 2) -# define RADEON_NORMALIZE_NORMALS (1 << 3) -# define RADEON_RESCALE_NORMALS (1 << 4) -# define RADEON_SPECULAR_LIGHTS (1 << 5) -# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) -# define RADEON_LIGHT_ALPHA (1 << 7) -# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) -# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) -# define RADEON_LM_SOURCE_STATE_PREMULT 0 -# define RADEON_LM_SOURCE_STATE_MULT 1 -# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 -# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 -# define RADEON_EMISSIVE_SOURCE_SHIFT 16 -# define RADEON_AMBIENT_SOURCE_SHIFT 18 -# define RADEON_DIFFUSE_SOURCE_SHIFT 20 -# define RADEON_SPECULAR_SOURCE_SHIFT 22 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c -#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 -#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 -#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 -#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c -#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c -# define RADEON_MODELVIEW_0_SHIFT 0 -# define RADEON_MODELVIEW_1_SHIFT 4 -# define RADEON_MODELVIEW_2_SHIFT 8 -# define RADEON_MODELVIEW_3_SHIFT 12 -# define RADEON_IT_MODELVIEW_0_SHIFT 16 -# define RADEON_IT_MODELVIEW_1_SHIFT 20 -# define RADEON_IT_MODELVIEW_2_SHIFT 24 -# define RADEON_IT_MODELVIEW_3_SHIFT 28 -#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 -# define RADEON_MODELPROJECT_0_SHIFT 0 -# define RADEON_MODELPROJECT_1_SHIFT 4 -# define RADEON_MODELPROJECT_2_SHIFT 8 -# define RADEON_MODELPROJECT_3_SHIFT 12 -# define RADEON_TEXMAT_0_SHIFT 16 -# define RADEON_TEXMAT_1_SHIFT 20 -# define RADEON_TEXMAT_2_SHIFT 24 -# define RADEON_TEXMAT_3_SHIFT 28 - - -#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 -# define RADEON_TCL_VTX_W0 (1 << 0) -# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) -# define RADEON_TCL_VTX_FP_ALPHA (1 << 2) -# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) -# define RADEON_TCL_VTX_FP_SPEC (1 << 4) -# define RADEON_TCL_VTX_FP_FOG (1 << 5) -# define RADEON_TCL_VTX_PK_SPEC (1 << 6) -# define RADEON_TCL_VTX_ST0 (1 << 7) -# define RADEON_TCL_VTX_ST1 (1 << 8) -# define RADEON_TCL_VTX_Q1 (1 << 9) -# define RADEON_TCL_VTX_ST2 (1 << 10) -# define RADEON_TCL_VTX_Q2 (1 << 11) -# define RADEON_TCL_VTX_ST3 (1 << 12) -# define RADEON_TCL_VTX_Q3 (1 << 13) -# define RADEON_TCL_VTX_Q0 (1 << 14) -# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 -# define RADEON_TCL_VTX_NORM0 (1 << 18) -# define RADEON_TCL_VTX_XY1 (1 << 27) -# define RADEON_TCL_VTX_Z1 (1 << 28) -# define RADEON_TCL_VTX_W1 (1 << 29) -# define RADEON_TCL_VTX_NORM1 (1 << 30) -# define RADEON_TCL_VTX_Z0 (1 << 31) - -#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 -# define RADEON_TCL_COMPUTE_XYZW (1 << 0) -# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) -# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) -# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) -# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) -# define RADEON_TCL_TEX_INPUT_TEX_0 0 -# define RADEON_TCL_TEX_INPUT_TEX_1 1 -# define RADEON_TCL_TEX_INPUT_TEX_2 2 -# define RADEON_TCL_TEX_INPUT_TEX_3 3 -# define RADEON_TCL_TEX_COMPUTED_TEX_0 8 -# define RADEON_TCL_TEX_COMPUTED_TEX_1 9 -# define RADEON_TCL_TEX_COMPUTED_TEX_2 10 -# define RADEON_TCL_TEX_COMPUTED_TEX_3 11 -# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 -# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 -# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 -# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 - -#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 -# define RADEON_LIGHT_0_ENABLE (1 << 0) -# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) -# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) -# define RADEON_LIGHT_0_IS_LOCAL (1 << 3) -# define RADEON_LIGHT_0_IS_SPOT (1 << 4) -# define RADEON_LIGHT_0_DUAL_CONE (1 << 5) -# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) -# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) -# define RADEON_LIGHT_0_SHIFT 0 -# define RADEON_LIGHT_1_ENABLE (1 << 16) -# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) -# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) -# define RADEON_LIGHT_1_IS_LOCAL (1 << 19) -# define RADEON_LIGHT_1_IS_SPOT (1 << 20) -# define RADEON_LIGHT_1_DUAL_CONE (1 << 21) -# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) -# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) -# define RADEON_LIGHT_1_SHIFT 16 -#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 -# define RADEON_LIGHT_2_SHIFT 0 -# define RADEON_LIGHT_3_SHIFT 16 -#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 -# define RADEON_LIGHT_4_SHIFT 0 -# define RADEON_LIGHT_5_SHIFT 16 -#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c -# define RADEON_LIGHT_6_SHIFT 0 -# define RADEON_LIGHT_7_SHIFT 16 - -#define RADEON_SE_TCL_SHININESS 0x2250 - -#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 -# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) -# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) -# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) -# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) -# define RADEON_TEXMAT_0_ENABLE (1 << 4) -# define RADEON_TEXMAT_1_ENABLE (1 << 5) -# define RADEON_TEXMAT_2_ENABLE (1 << 6) -# define RADEON_TEXMAT_3_ENABLE (1 << 7) -# define RADEON_TEXGEN_INPUT_MASK 0xf -# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 -# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 -# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 -# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 -# define RADEON_TEXGEN_INPUT_OBJ 4 -# define RADEON_TEXGEN_INPUT_EYE 5 -# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 -# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 -# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 -# define RADEON_TEXGEN_0_INPUT_SHIFT 16 -# define RADEON_TEXGEN_1_INPUT_SHIFT 20 -# define RADEON_TEXGEN_2_INPUT_SHIFT 24 -# define RADEON_TEXGEN_3_INPUT_SHIFT 28 - -#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 -# define RADEON_UCP_IN_CLIP_SPACE (1 << 0) -# define RADEON_UCP_IN_MODEL_SPACE (1 << 1) -# define RADEON_UCP_ENABLE_0 (1 << 2) -# define RADEON_UCP_ENABLE_1 (1 << 3) -# define RADEON_UCP_ENABLE_2 (1 << 4) -# define RADEON_UCP_ENABLE_3 (1 << 5) -# define RADEON_UCP_ENABLE_4 (1 << 6) -# define RADEON_UCP_ENABLE_5 (1 << 7) -# define RADEON_TCL_FOG_MASK (3 << 8) -# define RADEON_TCL_FOG_DISABLE (0 << 8) -# define RADEON_TCL_FOG_EXP (1 << 8) -# define RADEON_TCL_FOG_EXP2 (2 << 8) -# define RADEON_TCL_FOG_LINEAR (3 << 8) -# define RADEON_RNG_BASED_FOG (1 << 10) -# define RADEON_LIGHT_TWOSIDE (1 << 11) -# define RADEON_BLEND_OP_COUNT_MASK (7 << 12) -# define RADEON_BLEND_OP_COUNT_SHIFT 12 -# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) -# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) -# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) -# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) -# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) -# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) -# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) -# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) -# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) -# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) -# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) -# define RADEON_CULL_FRONT_IS_CW (0 << 28) -# define RADEON_CULL_FRONT_IS_CCW (1 << 28) -# define RADEON_CULL_FRONT (1 << 29) -# define RADEON_CULL_BACK (1 << 30) -# define RADEON_FORCE_W_TO_ONE (1 << 31) - -#define RADEON_SE_VPORT_XSCALE 0x1d98 -#define RADEON_SE_VPORT_XOFFSET 0x1d9c -#define RADEON_SE_VPORT_YSCALE 0x1da0 -#define RADEON_SE_VPORT_YOFFSET 0x1da4 -#define RADEON_SE_VPORT_ZSCALE 0x1da8 -#define RADEON_SE_VPORT_ZOFFSET 0x1dac -#define RADEON_SE_ZBIAS_FACTOR 0x1db0 -#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 - -#define RADEON_SE_VTX_FMT 0x2080 -# define RADEON_SE_VTX_FMT_XY 0x00000000 -# define RADEON_SE_VTX_FMT_W0 0x00000001 -# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 -# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 -# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 -# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 -# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 -# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 -# define RADEON_SE_VTX_FMT_ST0 0x00000080 -# define RADEON_SE_VTX_FMT_ST1 0x00000100 -# define RADEON_SE_VTX_FMT_Q1 0x00000200 -# define RADEON_SE_VTX_FMT_ST2 0x00000400 -# define RADEON_SE_VTX_FMT_Q2 0x00000800 -# define RADEON_SE_VTX_FMT_ST3 0x00001000 -# define RADEON_SE_VTX_FMT_Q3 0x00002000 -# define RADEON_SE_VTX_FMT_Q0 0x00004000 -# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 -# define RADEON_SE_VTX_FMT_N0 0x00040000 -# define RADEON_SE_VTX_FMT_XY1 0x08000000 -# define RADEON_SE_VTX_FMT_Z1 0x10000000 -# define RADEON_SE_VTX_FMT_W1 0x20000000 -# define RADEON_SE_VTX_FMT_N1 0x40000000 -# define RADEON_SE_VTX_FMT_Z 0x80000000 - -#define RADEON_SE_VF_CNTL 0x2084 -# define RADEON_VF_PRIM_TYPE_POINT_LIST 1 -# define RADEON_VF_PRIM_TYPE_LINE_LIST 2 -# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 -# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 -# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 -# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 -# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 -# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 -# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 -# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 -# define RADEON_VF_PRIM_TYPE_POLYGON 15 -# define RADEON_VF_PRIM_WALK_STATE (0<<4) -# define RADEON_VF_PRIM_WALK_INDEX (1<<4) -# define RADEON_VF_PRIM_WALK_LIST (2<<4) -# define RADEON_VF_PRIM_WALK_DATA (3<<4) -# define RADEON_VF_COLOR_ORDER_RGBA (1<<6) -# define RADEON_VF_RADEON_MODE (1<<8) -# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) -# define RADEON_VF_PROG_STREAM_ENA (1<<10) -# define RADEON_VF_INDEX_SIZE_SHIFT 11 -# define RADEON_VF_NUM_VERTICES_SHIFT 16 - -#define RADEON_SE_PORT_DATA0 0x2000 - -#define R200_SE_VAP_CNTL 0x2080 -# define R200_VAP_TCL_ENABLE 0x00000001 -# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 -# define R200_VAP_FORCE_W_TO_ONE 0x00010000 -# define R200_VAP_D3D_TEX_DEFAULT 0x00020000 -# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 -# define R200_VAP_VF_MAX_VTX_NUM (9 << 18) -# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 -#define R200_VF_MAX_VTX_INDX 0x210c -#define R200_VF_MIN_VTX_INDX 0x2110 -#define R200_SE_VTE_CNTL 0x20b0 -# define R200_VPORT_X_SCALE_ENA 0x00000001 -# define R200_VPORT_X_OFFSET_ENA 0x00000002 -# define R200_VPORT_Y_SCALE_ENA 0x00000004 -# define R200_VPORT_Y_OFFSET_ENA 0x00000008 -# define R200_VPORT_Z_SCALE_ENA 0x00000010 -# define R200_VPORT_Z_OFFSET_ENA 0x00000020 -# define R200_VTX_XY_FMT 0x00000100 -# define R200_VTX_Z_FMT 0x00000200 -# define R200_VTX_W0_FMT 0x00000400 -# define R200_VTX_W0_NORMALIZE 0x00000800 -# define R200_VTX_ST_DENORMALIZED 0x00001000 -#define R200_SE_VAP_CNTL_STATUS 0x2140 -# define R200_VC_NO_SWAP (0 << 0) -# define R200_VC_16BIT_SWAP (1 << 0) -# define R200_VC_32BIT_SWAP (2 << 0) -#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 -# define R200_EXCLUSIVE_SCISSOR_0 0x01000000 -# define R200_EXCLUSIVE_SCISSOR_1 0x02000000 -# define R200_EXCLUSIVE_SCISSOR_2 0x04000000 -# define R200_SCISSOR_ENABLE_0 0x10000000 -# define R200_SCISSOR_ENABLE_1 0x20000000 -# define R200_SCISSOR_ENABLE_2 0x40000000 -#define R200_PP_TXFILTER_0 0x2c00 -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFILTER_5 0x2ca0 -# define R200_MAG_FILTER_NEAREST (0 << 0) -# define R200_MAG_FILTER_LINEAR (1 << 0) -# define R200_MAG_FILTER_MASK (1 << 0) -# define R200_MIN_FILTER_NEAREST (0 << 1) -# define R200_MIN_FILTER_LINEAR (1 << 1) -# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) -# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) -# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) -# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) -# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) -# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) -# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) -# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) -# define R200_MIN_FILTER_MASK (15 << 1) -# define R200_MAX_ANISO_1_TO_1 (0 << 5) -# define R200_MAX_ANISO_2_TO_1 (1 << 5) -# define R200_MAX_ANISO_4_TO_1 (2 << 5) -# define R200_MAX_ANISO_8_TO_1 (3 << 5) -# define R200_MAX_ANISO_16_TO_1 (4 << 5) -# define R200_MAX_ANISO_MASK (7 << 5) -# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) -# define R200_MAX_MIP_LEVEL_SHIFT 16 -# define R200_YUV_TO_RGB (1 << 20) -# define R200_YUV_TEMPERATURE_COOL (0 << 21) -# define R200_YUV_TEMPERATURE_HOT (1 << 21) -# define R200_YUV_TEMPERATURE_MASK (1 << 21) -# define R200_WRAPEN_S (1 << 22) -# define R200_CLAMP_S_WRAP (0 << 23) -# define R200_CLAMP_S_MIRROR (1 << 23) -# define R200_CLAMP_S_CLAMP_LAST (2 << 23) -# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) -# define R200_CLAMP_S_CLAMP_BORDER (4 << 23) -# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) -# define R200_CLAMP_S_CLAMP_GL (6 << 23) -# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) -# define R200_CLAMP_S_MASK (7 << 23) -# define R200_WRAPEN_T (1 << 26) -# define R200_CLAMP_T_WRAP (0 << 27) -# define R200_CLAMP_T_MIRROR (1 << 27) -# define R200_CLAMP_T_CLAMP_LAST (2 << 27) -# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) -# define R200_CLAMP_T_CLAMP_BORDER (4 << 27) -# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) -# define R200_CLAMP_T_CLAMP_GL (6 << 27) -# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) -# define R200_CLAMP_T_MASK (7 << 27) -# define R200_KILL_LT_ZERO (1 << 30) -# define R200_BORDER_MODE_OGL (0 << 31) -# define R200_BORDER_MODE_D3D (1 << 31) -#define R200_PP_TXFORMAT_0 0x2c04 -#define R200_PP_TXFORMAT_1 0x2c24 -#define R200_PP_TXFORMAT_2 0x2c44 -#define R200_PP_TXFORMAT_3 0x2c64 -#define R200_PP_TXFORMAT_4 0x2c84 -#define R200_PP_TXFORMAT_5 0x2ca4 -# define R200_TXFORMAT_I8 (0 << 0) -# define R200_TXFORMAT_AI88 (1 << 0) -# define R200_TXFORMAT_RGB332 (2 << 0) -# define R200_TXFORMAT_ARGB1555 (3 << 0) -# define R200_TXFORMAT_RGB565 (4 << 0) -# define R200_TXFORMAT_ARGB4444 (5 << 0) -# define R200_TXFORMAT_ARGB8888 (6 << 0) -# define R200_TXFORMAT_RGBA8888 (7 << 0) -# define R200_TXFORMAT_Y8 (8 << 0) -# define R200_TXFORMAT_AVYU4444 (9 << 0) -# define R200_TXFORMAT_VYUY422 (10 << 0) -# define R200_TXFORMAT_YVYU422 (11 << 0) -# define R200_TXFORMAT_DXT1 (12 << 0) -# define R200_TXFORMAT_DXT23 (14 << 0) -# define R200_TXFORMAT_DXT45 (15 << 0) -# define R200_TXFORMAT_ABGR8888 (22 << 0) -# define R200_TXFORMAT_FORMAT_MASK (31 << 0) -# define R200_TXFORMAT_FORMAT_SHIFT 0 -# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) -# define R200_TXFORMAT_NON_POWER2 (1 << 7) -# define R200_TXFORMAT_WIDTH_MASK (15 << 8) -# define R200_TXFORMAT_WIDTH_SHIFT 8 -# define R200_TXFORMAT_HEIGHT_MASK (15 << 12) -# define R200_TXFORMAT_HEIGHT_SHIFT 12 -# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ -# define R200_TXFORMAT_F5_WIDTH_SHIFT 16 -# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) -# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 -# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) -# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) -# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 -# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) -# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) -# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) -#define R200_PP_TXFORMAT_X_0 0x2c08 -#define R200_PP_TXFORMAT_X_1 0x2c28 -#define R200_PP_TXFORMAT_X_2 0x2c48 -#define R200_PP_TXFORMAT_X_3 0x2c68 -#define R200_PP_TXFORMAT_X_4 0x2c88 -#define R200_PP_TXFORMAT_X_5 0x2ca8 - -#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ -#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ -#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ -#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ -#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ -#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ - -#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ -#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ -#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ -#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ -#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ -#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ - -#define R200_PP_TXOFFSET_0 0x2d00 -# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) -# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) -# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) -# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) -# define R200_TXO_MACRO_LINEAR (0 << 2) -# define R200_TXO_MACRO_TILE (1 << 2) -# define R200_TXO_MICRO_LINEAR (0 << 3) -# define R200_TXO_MICRO_TILE (1 << 3) -# define R200_TXO_OFFSET_MASK 0xffffffe0 -# define R200_TXO_OFFSET_SHIFT 5 -#define R200_PP_TXOFFSET_1 0x2d18 -#define R200_PP_TXOFFSET_2 0x2d30 -#define R200_PP_TXOFFSET_3 0x2d48 -#define R200_PP_TXOFFSET_4 0x2d60 -#define R200_PP_TXOFFSET_5 0x2d78 - -#define R200_PP_TFACTOR_0 0x2ee0 -#define R200_PP_TFACTOR_1 0x2ee4 -#define R200_PP_TFACTOR_2 0x2ee8 -#define R200_PP_TFACTOR_3 0x2eec -#define R200_PP_TFACTOR_4 0x2ef0 -#define R200_PP_TFACTOR_5 0x2ef4 - -#define R200_PP_TXCBLEND_0 0x2f00 -# define R200_TXC_ARG_A_ZERO (0) -# define R200_TXC_ARG_A_CURRENT_COLOR (2) -# define R200_TXC_ARG_A_CURRENT_ALPHA (3) -# define R200_TXC_ARG_A_DIFFUSE_COLOR (4) -# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) -# define R200_TXC_ARG_A_SPECULAR_COLOR (6) -# define R200_TXC_ARG_A_SPECULAR_ALPHA (7) -# define R200_TXC_ARG_A_TFACTOR_COLOR (8) -# define R200_TXC_ARG_A_TFACTOR_ALPHA (9) -# define R200_TXC_ARG_A_R0_COLOR (10) -# define R200_TXC_ARG_A_R0_ALPHA (11) -# define R200_TXC_ARG_A_R1_COLOR (12) -# define R200_TXC_ARG_A_R1_ALPHA (13) -# define R200_TXC_ARG_A_R2_COLOR (14) -# define R200_TXC_ARG_A_R2_ALPHA (15) -# define R200_TXC_ARG_A_R3_COLOR (16) -# define R200_TXC_ARG_A_R3_ALPHA (17) -# define R200_TXC_ARG_A_R4_COLOR (18) -# define R200_TXC_ARG_A_R4_ALPHA (19) -# define R200_TXC_ARG_A_R5_COLOR (20) -# define R200_TXC_ARG_A_R5_ALPHA (21) -# define R200_TXC_ARG_A_TFACTOR1_COLOR (26) -# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) -# define R200_TXC_ARG_A_MASK (31 << 0) -# define R200_TXC_ARG_A_SHIFT 0 -# define R200_TXC_ARG_B_ZERO (0 << 5) -# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) -# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) -# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) -# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) -# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) -# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) -# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) -# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) -# define R200_TXC_ARG_B_R0_COLOR (10 << 5) -# define R200_TXC_ARG_B_R0_ALPHA (11 << 5) -# define R200_TXC_ARG_B_R1_COLOR (12 << 5) -# define R200_TXC_ARG_B_R1_ALPHA (13 << 5) -# define R200_TXC_ARG_B_R2_COLOR (14 << 5) -# define R200_TXC_ARG_B_R2_ALPHA (15 << 5) -# define R200_TXC_ARG_B_R3_COLOR (16 << 5) -# define R200_TXC_ARG_B_R3_ALPHA (17 << 5) -# define R200_TXC_ARG_B_R4_COLOR (18 << 5) -# define R200_TXC_ARG_B_R4_ALPHA (19 << 5) -# define R200_TXC_ARG_B_R5_COLOR (20 << 5) -# define R200_TXC_ARG_B_R5_ALPHA (21 << 5) -# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) -# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) -# define R200_TXC_ARG_B_MASK (31 << 5) -# define R200_TXC_ARG_B_SHIFT 5 -# define R200_TXC_ARG_C_ZERO (0 << 10) -# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) -# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) -# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) -# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) -# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) -# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) -# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) -# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) -# define R200_TXC_ARG_C_R0_COLOR (10 << 10) -# define R200_TXC_ARG_C_R0_ALPHA (11 << 10) -# define R200_TXC_ARG_C_R1_COLOR (12 << 10) -# define R200_TXC_ARG_C_R1_ALPHA (13 << 10) -# define R200_TXC_ARG_C_R2_COLOR (14 << 10) -# define R200_TXC_ARG_C_R2_ALPHA (15 << 10) -# define R200_TXC_ARG_C_R3_COLOR (16 << 10) -# define R200_TXC_ARG_C_R3_ALPHA (17 << 10) -# define R200_TXC_ARG_C_R4_COLOR (18 << 10) -# define R200_TXC_ARG_C_R4_ALPHA (19 << 10) -# define R200_TXC_ARG_C_R5_COLOR (20 << 10) -# define R200_TXC_ARG_C_R5_ALPHA (21 << 10) -# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) -# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) -# define R200_TXC_ARG_C_MASK (31 << 10) -# define R200_TXC_ARG_C_SHIFT 10 -# define R200_TXC_COMP_ARG_A (1 << 16) -# define R200_TXC_COMP_ARG_A_SHIFT (16) -# define R200_TXC_BIAS_ARG_A (1 << 17) -# define R200_TXC_SCALE_ARG_A (1 << 18) -# define R200_TXC_NEG_ARG_A (1 << 19) -# define R200_TXC_COMP_ARG_B (1 << 20) -# define R200_TXC_COMP_ARG_B_SHIFT (20) -# define R200_TXC_BIAS_ARG_B (1 << 21) -# define R200_TXC_SCALE_ARG_B (1 << 22) -# define R200_TXC_NEG_ARG_B (1 << 23) -# define R200_TXC_COMP_ARG_C (1 << 24) -# define R200_TXC_COMP_ARG_C_SHIFT (24) -# define R200_TXC_BIAS_ARG_C (1 << 25) -# define R200_TXC_SCALE_ARG_C (1 << 26) -# define R200_TXC_NEG_ARG_C (1 << 27) -# define R200_TXC_OP_MADD (0 << 28) -# define R200_TXC_OP_CND0 (2 << 28) -# define R200_TXC_OP_LERP (3 << 28) -# define R200_TXC_OP_DOT3 (4 << 28) -# define R200_TXC_OP_DOT4 (5 << 28) -# define R200_TXC_OP_CONDITIONAL (6 << 28) -# define R200_TXC_OP_DOT2_ADD (7 << 28) -# define R200_TXC_OP_MASK (7 << 28) -#define R200_PP_TXCBLEND2_0 0x2f04 -# define R200_TXC_TFACTOR_SEL_SHIFT 0 -# define R200_TXC_TFACTOR_SEL_MASK 0x7 -# define R200_TXC_TFACTOR1_SEL_SHIFT 4 -# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) -# define R200_TXC_SCALE_SHIFT 8 -# define R200_TXC_SCALE_MASK (7 << 8) -# define R200_TXC_SCALE_1X (0 << 8) -# define R200_TXC_SCALE_2X (1 << 8) -# define R200_TXC_SCALE_4X (2 << 8) -# define R200_TXC_SCALE_8X (3 << 8) -# define R200_TXC_SCALE_INV2 (5 << 8) -# define R200_TXC_SCALE_INV4 (6 << 8) -# define R200_TXC_SCALE_INV8 (7 << 8) -# define R200_TXC_CLAMP_SHIFT 12 -# define R200_TXC_CLAMP_MASK (3 << 12) -# define R200_TXC_CLAMP_WRAP (0 << 12) -# define R200_TXC_CLAMP_0_1 (1 << 12) -# define R200_TXC_CLAMP_8_8 (2 << 12) -# define R200_TXC_OUTPUT_REG_MASK (7 << 16) -# define R200_TXC_OUTPUT_REG_NONE (0 << 16) -# define R200_TXC_OUTPUT_REG_R0 (1 << 16) -# define R200_TXC_OUTPUT_REG_R1 (2 << 16) -# define R200_TXC_OUTPUT_REG_R2 (3 << 16) -# define R200_TXC_OUTPUT_REG_R3 (4 << 16) -# define R200_TXC_OUTPUT_REG_R4 (5 << 16) -# define R200_TXC_OUTPUT_REG_R5 (6 << 16) -# define R200_TXC_OUTPUT_MASK_MASK (7 << 20) -# define R200_TXC_OUTPUT_MASK_RGB (0 << 20) -# define R200_TXC_OUTPUT_MASK_RG (1 << 20) -# define R200_TXC_OUTPUT_MASK_RB (2 << 20) -# define R200_TXC_OUTPUT_MASK_R (3 << 20) -# define R200_TXC_OUTPUT_MASK_GB (4 << 20) -# define R200_TXC_OUTPUT_MASK_G (5 << 20) -# define R200_TXC_OUTPUT_MASK_B (6 << 20) -# define R200_TXC_OUTPUT_MASK_NONE (7 << 20) -# define R200_TXC_REPL_NORMAL 0 -# define R200_TXC_REPL_RED 1 -# define R200_TXC_REPL_GREEN 2 -# define R200_TXC_REPL_BLUE 3 -# define R200_TXC_REPL_ARG_A_SHIFT 26 -# define R200_TXC_REPL_ARG_A_MASK (3 << 26) -# define R200_TXC_REPL_ARG_B_SHIFT 28 -# define R200_TXC_REPL_ARG_B_MASK (3 << 28) -# define R200_TXC_REPL_ARG_C_SHIFT 30 -# define R200_TXC_REPL_ARG_C_MASK (3 << 30) -#define R200_PP_TXABLEND_0 0x2f08 -# define R200_TXA_ARG_A_ZERO (0) -# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ -# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ -# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) -# define R200_TXA_ARG_A_DIFFUSE_BLUE (5) -# define R200_TXA_ARG_A_SPECULAR_ALPHA (6) -# define R200_TXA_ARG_A_SPECULAR_BLUE (7) -# define R200_TXA_ARG_A_TFACTOR_ALPHA (8) -# define R200_TXA_ARG_A_TFACTOR_BLUE (9) -# define R200_TXA_ARG_A_R0_ALPHA (10) -# define R200_TXA_ARG_A_R0_BLUE (11) -# define R200_TXA_ARG_A_R1_ALPHA (12) -# define R200_TXA_ARG_A_R1_BLUE (13) -# define R200_TXA_ARG_A_R2_ALPHA (14) -# define R200_TXA_ARG_A_R2_BLUE (15) -# define R200_TXA_ARG_A_R3_ALPHA (16) -# define R200_TXA_ARG_A_R3_BLUE (17) -# define R200_TXA_ARG_A_R4_ALPHA (18) -# define R200_TXA_ARG_A_R4_BLUE (19) -# define R200_TXA_ARG_A_R5_ALPHA (20) -# define R200_TXA_ARG_A_R5_BLUE (21) -# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) -# define R200_TXA_ARG_A_TFACTOR1_BLUE (27) -# define R200_TXA_ARG_A_MASK (31 << 0) -# define R200_TXA_ARG_A_SHIFT 0 -# define R200_TXA_ARG_B_ZERO (0 << 5) -# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ -# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ -# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) -# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) -# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) -# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) -# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) -# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) -# define R200_TXA_ARG_B_R0_ALPHA (10 << 5) -# define R200_TXA_ARG_B_R0_BLUE (11 << 5) -# define R200_TXA_ARG_B_R1_ALPHA (12 << 5) -# define R200_TXA_ARG_B_R1_BLUE (13 << 5) -# define R200_TXA_ARG_B_R2_ALPHA (14 << 5) -# define R200_TXA_ARG_B_R2_BLUE (15 << 5) -# define R200_TXA_ARG_B_R3_ALPHA (16 << 5) -# define R200_TXA_ARG_B_R3_BLUE (17 << 5) -# define R200_TXA_ARG_B_R4_ALPHA (18 << 5) -# define R200_TXA_ARG_B_R4_BLUE (19 << 5) -# define R200_TXA_ARG_B_R5_ALPHA (20 << 5) -# define R200_TXA_ARG_B_R5_BLUE (21 << 5) -# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) -# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) -# define R200_TXA_ARG_B_MASK (31 << 5) -# define R200_TXA_ARG_B_SHIFT 5 -# define R200_TXA_ARG_C_ZERO (0 << 10) -# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ -# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ -# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) -# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) -# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) -# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) -# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) -# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) -# define R200_TXA_ARG_C_R0_ALPHA (10 << 10) -# define R200_TXA_ARG_C_R0_BLUE (11 << 10) -# define R200_TXA_ARG_C_R1_ALPHA (12 << 10) -# define R200_TXA_ARG_C_R1_BLUE (13 << 10) -# define R200_TXA_ARG_C_R2_ALPHA (14 << 10) -# define R200_TXA_ARG_C_R2_BLUE (15 << 10) -# define R200_TXA_ARG_C_R3_ALPHA (16 << 10) -# define R200_TXA_ARG_C_R3_BLUE (17 << 10) -# define R200_TXA_ARG_C_R4_ALPHA (18 << 10) -# define R200_TXA_ARG_C_R4_BLUE (19 << 10) -# define R200_TXA_ARG_C_R5_ALPHA (20 << 10) -# define R200_TXA_ARG_C_R5_BLUE (21 << 10) -# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) -# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) -# define R200_TXA_ARG_C_MASK (31 << 10) -# define R200_TXA_ARG_C_SHIFT 10 -# define R200_TXA_COMP_ARG_A (1 << 16) -# define R200_TXA_COMP_ARG_A_SHIFT (16) -# define R200_TXA_BIAS_ARG_A (1 << 17) -# define R200_TXA_SCALE_ARG_A (1 << 18) -# define R200_TXA_NEG_ARG_A (1 << 19) -# define R200_TXA_COMP_ARG_B (1 << 20) -# define R200_TXA_COMP_ARG_B_SHIFT (20) -# define R200_TXA_BIAS_ARG_B (1 << 21) -# define R200_TXA_SCALE_ARG_B (1 << 22) -# define R200_TXA_NEG_ARG_B (1 << 23) -# define R200_TXA_COMP_ARG_C (1 << 24) -# define R200_TXA_COMP_ARG_C_SHIFT (24) -# define R200_TXA_BIAS_ARG_C (1 << 25) -# define R200_TXA_SCALE_ARG_C (1 << 26) -# define R200_TXA_NEG_ARG_C (1 << 27) -# define R200_TXA_OP_MADD (0 << 28) -# define R200_TXA_OP_CND0 (2 << 28) -# define R200_TXA_OP_LERP (3 << 28) -# define R200_TXA_OP_CONDITIONAL (6 << 28) -# define R200_TXA_OP_MASK (7 << 28) -#define R200_PP_TXABLEND2_0 0x2f0c -# define R200_TXA_TFACTOR_SEL_SHIFT 0 -# define R200_TXA_TFACTOR_SEL_MASK 0x7 -# define R200_TXA_TFACTOR1_SEL_SHIFT 4 -# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) -# define R200_TXA_SCALE_SHIFT 8 -# define R200_TXA_SCALE_MASK (7 << 8) -# define R200_TXA_SCALE_1X (0 << 8) -# define R200_TXA_SCALE_2X (1 << 8) -# define R200_TXA_SCALE_4X (2 << 8) -# define R200_TXA_SCALE_8X (3 << 8) -# define R200_TXA_SCALE_INV2 (5 << 8) -# define R200_TXA_SCALE_INV4 (6 << 8) -# define R200_TXA_SCALE_INV8 (7 << 8) -# define R200_TXA_CLAMP_SHIFT 12 -# define R200_TXA_CLAMP_MASK (3 << 12) -# define R200_TXA_CLAMP_WRAP (0 << 12) -# define R200_TXA_CLAMP_0_1 (1 << 12) -# define R200_TXA_CLAMP_8_8 (2 << 12) -# define R200_TXA_OUTPUT_REG_MASK (7 << 16) -# define R200_TXA_OUTPUT_REG_NONE (0 << 16) -# define R200_TXA_OUTPUT_REG_R0 (1 << 16) -# define R200_TXA_OUTPUT_REG_R1 (2 << 16) -# define R200_TXA_OUTPUT_REG_R2 (3 << 16) -# define R200_TXA_OUTPUT_REG_R3 (4 << 16) -# define R200_TXA_OUTPUT_REG_R4 (5 << 16) -# define R200_TXA_OUTPUT_REG_R5 (6 << 16) -# define R200_TXA_DOT_ALPHA (1 << 20) -# define R200_TXA_REPL_NORMAL 0 -# define R200_TXA_REPL_RED 1 -# define R200_TXA_REPL_GREEN 2 -# define R200_TXA_REPL_ARG_A_SHIFT 26 -# define R200_TXA_REPL_ARG_A_MASK (3 << 26) -# define R200_TXA_REPL_ARG_B_SHIFT 28 -# define R200_TXA_REPL_ARG_B_MASK (3 << 28) -# define R200_TXA_REPL_ARG_C_SHIFT 30 -# define R200_TXA_REPL_ARG_C_MASK (3 << 30) -#define R200_PP_TXCBLEND_1 0x2f10 -#define R200_PP_TXCBLEND2_1 0x2f14 -#define R200_PP_TXABLEND_1 0x2f18 -#define R200_PP_TXABLEND2_1 0x2f1c -#define R200_PP_TXCBLEND_2 0x2f20 -#define R200_PP_TXCBLEND2_2 0x2f24 -#define R200_PP_TXABLEND_2 0x2f28 -#define R200_PP_TXABLEND2_2 0x2f2c -#define R200_PP_TXCBLEND_3 0x2f30 -#define R200_PP_TXCBLEND2_3 0x2f34 -#define R200_PP_TXABLEND_3 0x2f38 -#define R200_PP_TXABLEND2_3 0x2f3c - -#define R200_SE_VTX_FMT_0 0x2088 -# define R200_VTX_XY 0 /* always have xy */ -# define R200_VTX_Z0 (1<<0) -# define R200_VTX_W0 (1<<1) -# define R200_VTX_WEIGHT_COUNT_SHIFT (2) -# define R200_VTX_PV_MATRIX_SEL (1<<5) -# define R200_VTX_N0 (1<<6) -# define R200_VTX_POINT_SIZE (1<<7) -# define R200_VTX_DISCRETE_FOG (1<<8) -# define R200_VTX_SHININESS_0 (1<<9) -# define R200_VTX_SHININESS_1 (1<<10) -# define R200_VTX_COLOR_NOT_PRESENT 0 -# define R200_VTX_PK_RGBA 1 -# define R200_VTX_FP_RGB 2 -# define R200_VTX_FP_RGBA 3 -# define R200_VTX_COLOR_MASK 3 -# define R200_VTX_COLOR_0_SHIFT 11 -# define R200_VTX_COLOR_1_SHIFT 13 -# define R200_VTX_COLOR_2_SHIFT 15 -# define R200_VTX_COLOR_3_SHIFT 17 -# define R200_VTX_COLOR_4_SHIFT 19 -# define R200_VTX_COLOR_5_SHIFT 21 -# define R200_VTX_COLOR_6_SHIFT 23 -# define R200_VTX_COLOR_7_SHIFT 25 -# define R200_VTX_XY1 (1<<28) -# define R200_VTX_Z1 (1<<29) -# define R200_VTX_W1 (1<<30) -# define R200_VTX_N1 (1<<31) -#define R200_SE_VTX_FMT_1 0x208c -# define R200_VTX_TEX0_COMP_CNT_SHIFT 0 -# define R200_VTX_TEX1_COMP_CNT_SHIFT 3 -# define R200_VTX_TEX2_COMP_CNT_SHIFT 6 -# define R200_VTX_TEX3_COMP_CNT_SHIFT 9 -# define R200_VTX_TEX4_COMP_CNT_SHIFT 12 -# define R200_VTX_TEX5_COMP_CNT_SHIFT 15 - -#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 -#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 -#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 -# define R200_OUTPUT_XYZW (1<<0) -# define R200_OUTPUT_COLOR_0 (1<<8) -# define R200_OUTPUT_COLOR_1 (1<<9) -# define R200_OUTPUT_TEX_0 (1<<16) -# define R200_OUTPUT_TEX_1 (1<<17) -# define R200_OUTPUT_TEX_2 (1<<18) -# define R200_OUTPUT_TEX_3 (1<<19) -# define R200_OUTPUT_TEX_4 (1<<20) -# define R200_OUTPUT_TEX_5 (1<<21) -# define R200_OUTPUT_TEX_MASK (0x3f<<16) -# define R200_OUTPUT_DISCRETE_FOG (1<<24) -# define R200_OUTPUT_PT_SIZE (1<<25) -# define R200_FORCE_INORDER_PROC (1<<31) -#define R200_PP_CNTL_X 0x2cc4 -#define R200_PP_TXMULTI_CTL_0 0x2c1c -#define R200_SE_VTX_STATE_CNTL 0x2180 -# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) - - /* Registers for CP and Microcode Engine */ -#define RADEON_CP_ME_RAM_ADDR 0x07d4 -#define RADEON_CP_ME_RAM_RADDR 0x07d8 -#define RADEON_CP_ME_RAM_DATAH 0x07dc -#define RADEON_CP_ME_RAM_DATAL 0x07e0 - -#define RADEON_CP_RB_BASE 0x0700 -#define RADEON_CP_RB_CNTL 0x0704 -#define RADEON_CP_RB_RPTR_ADDR 0x070c -#define RADEON_CP_RB_RPTR 0x0710 -#define RADEON_CP_RB_WPTR 0x0714 - -#define RADEON_CP_IB_BASE 0x0738 -#define RADEON_CP_IB_BUFSZ 0x073c - -#define RADEON_CP_CSQ_CNTL 0x0740 -# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) -# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) -# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) -# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) -# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) -# define RADEON_CSQ_PRIBM_INDBM (4 << 28) -# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) -#define RADEON_CP_CSQ_STAT 0x07f8 -# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) -# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) -# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) -# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) -#define RADEON_CP_CSQ_ADDR 0x07f0 -#define RADEON_CP_CSQ_DATA 0x07f4 -#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 -#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 - -#define RADEON_CP_RB_WPTR_DELAY 0x0718 -# define RADEON_PRE_WRITE_TIMER_SHIFT 0 -# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 - -#define RADEON_AIC_CNTL 0x01d0 -# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) -#define RADEON_AIC_LO_ADDR 0x01dc - - - - /* Constants */ -#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 -#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 - - - - /* CP packet types */ -#define RADEON_CP_PACKET0 0x00000000 -#define RADEON_CP_PACKET1 0x40000000 -#define RADEON_CP_PACKET2 0x80000000 -#define RADEON_CP_PACKET3 0xC0000000 -# define RADEON_CP_PACKET_MASK 0xC0000000 -# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 -# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) -# define RADEON_CP_PACKET0_REG_MASK 0x000007ff -# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff -# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 - -#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 - -#define RADEON_CP_PACKET3_NOP 0xC0001000 -#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 -#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 -#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 -#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 -#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 -#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 -#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 -#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 -#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 -#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 -#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 -#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 -#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 -#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 -#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 -#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 -#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 -#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 -#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 -#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 -#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 - - -#define RADEON_CP_VC_FRMT_XY 0x00000000 -#define RADEON_CP_VC_FRMT_W0 0x00000001 -#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 -#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 -#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 -#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 -#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 -#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 -#define RADEON_CP_VC_FRMT_ST0 0x00000080 -#define RADEON_CP_VC_FRMT_ST1 0x00000100 -#define RADEON_CP_VC_FRMT_Q1 0x00000200 -#define RADEON_CP_VC_FRMT_ST2 0x00000400 -#define RADEON_CP_VC_FRMT_Q2 0x00000800 -#define RADEON_CP_VC_FRMT_ST3 0x00001000 -#define RADEON_CP_VC_FRMT_Q3 0x00002000 -#define RADEON_CP_VC_FRMT_Q0 0x00004000 -#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 -#define RADEON_CP_VC_FRMT_N0 0x00040000 -#define RADEON_CP_VC_FRMT_XY1 0x08000000 -#define RADEON_CP_VC_FRMT_Z1 0x10000000 -#define RADEON_CP_VC_FRMT_W1 0x20000000 -#define RADEON_CP_VC_FRMT_N1 0x40000000 -#define RADEON_CP_VC_FRMT_Z 0x80000000 - -#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a -#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d -#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 -#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 -#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 -#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 -#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 -#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 -#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 -#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 -#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 -#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 -#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 - -#define RADEON_VS_MATRIX_0_ADDR 0 -#define RADEON_VS_MATRIX_1_ADDR 4 -#define RADEON_VS_MATRIX_2_ADDR 8 -#define RADEON_VS_MATRIX_3_ADDR 12 -#define RADEON_VS_MATRIX_4_ADDR 16 -#define RADEON_VS_MATRIX_5_ADDR 20 -#define RADEON_VS_MATRIX_6_ADDR 24 -#define RADEON_VS_MATRIX_7_ADDR 28 -#define RADEON_VS_MATRIX_8_ADDR 32 -#define RADEON_VS_MATRIX_9_ADDR 36 -#define RADEON_VS_MATRIX_10_ADDR 40 -#define RADEON_VS_MATRIX_11_ADDR 44 -#define RADEON_VS_MATRIX_12_ADDR 48 -#define RADEON_VS_MATRIX_13_ADDR 52 -#define RADEON_VS_MATRIX_14_ADDR 56 -#define RADEON_VS_MATRIX_15_ADDR 60 -#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 -#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 -#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 -#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 -#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 -#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 -#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 -#define RADEON_VS_UCP_ADDR 116 -#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 -#define RADEON_VS_FOG_PARAM_ADDR 123 -#define RADEON_VS_EYE_VECTOR_ADDR 124 - -#define RADEON_SS_LIGHT_DCD_ADDR 0 -#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 -#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 -#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 -#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 -#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 -#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 -#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 -#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 -#define RADEON_SS_SHININESS 60 - -#define RADEON_TV_MASTER_CNTL 0x0800 -# define RADEON_TV_ASYNC_RST (1 << 0) -# define RADEON_CRT_ASYNC_RST (1 << 1) -# define RADEON_RESTART_PHASE_FIX (1 << 3) -# define RADEON_TV_FIFO_ASYNC_RST (1 << 4) -# define RADEON_VIN_ASYNC_RST (1 << 5) -# define RADEON_AUD_ASYNC_RST (1 << 6) -# define RADEON_DVS_ASYNC_RST (1 << 7) -# define RADEON_CRT_FIFO_CE_EN (1 << 9) -# define RADEON_TV_FIFO_CE_EN (1 << 10) -# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) -# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) -# define RADEON_TV_ON (1 << 31) -#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 -# define RADEON_Y_RED_EN (1 << 0) -# define RADEON_C_GRN_EN (1 << 1) -# define RADEON_CMP_BLU_EN (1 << 2) -# define RADEON_DAC_DITHER_EN (1 << 3) -# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) -# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) -# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) -# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 -#define RADEON_TV_RGB_CNTL 0x0804 -# define RADEON_SWITCH_TO_BLUE (1 << 4) -# define RADEON_RGB_DITHER_EN (1 << 5) -# define RADEON_RGB_SRC_SEL_MASK (3 << 8) -# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) -# define RADEON_RGB_SRC_SEL_RMX (1 << 8) -# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) -# define RADEON_RGB_CONVERT_BY_PASS (1 << 10) -# define RADEON_UVRAM_READ_MARGIN_SHIFT 16 -# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 -# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) -# define RADEON_TVOUT_SCALE_EN (1 << 26) -# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) -#define RADEON_TV_SYNC_CNTL 0x0808 -# define RADEON_SYNC_OE (1 << 0) -# define RADEON_SYNC_OUT (1 << 1) -# define RADEON_SYNC_IN (1 << 2) -# define RADEON_SYNC_PUB (1 << 3) -# define RADEON_SYNC_PD (1 << 4) -# define RADEON_TV_SYNC_IO_DRIVE (1 << 5) -#define RADEON_TV_HTOTAL 0x080c -#define RADEON_TV_HDISP 0x0810 -#define RADEON_TV_HSTART 0x0818 -#define RADEON_TV_HCOUNT 0x081C -#define RADEON_TV_VTOTAL 0x0820 -#define RADEON_TV_VDISP 0x0824 -#define RADEON_TV_VCOUNT 0x0828 -#define RADEON_TV_FTOTAL 0x082c -#define RADEON_TV_FCOUNT 0x0830 -#define RADEON_TV_FRESTART 0x0834 -#define RADEON_TV_HRESTART 0x0838 -#define RADEON_TV_VRESTART 0x083c -#define RADEON_TV_HOST_READ_DATA 0x0840 -#define RADEON_TV_HOST_WRITE_DATA 0x0844 -#define RADEON_TV_HOST_RD_WT_CNTL 0x0848 -# define RADEON_HOST_FIFO_RD (1 << 12) -# define RADEON_HOST_FIFO_RD_ACK (1 << 13) -# define RADEON_HOST_FIFO_WT (1 << 14) -# define RADEON_HOST_FIFO_WT_ACK (1 << 15) -#define RADEON_TV_VSCALER_CNTL1 0x084c -# define RADEON_UV_INC_MASK 0xffff -# define RADEON_UV_INC_SHIFT 0 -# define RADEON_Y_W_EN (1 << 24) -# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ -# define RADEON_Y_DEL_W_SIG_SHIFT 26 -#define RADEON_TV_TIMING_CNTL 0x0850 -# define RADEON_H_INC_MASK 0xfff -# define RADEON_H_INC_SHIFT 0 -# define RADEON_REQ_Y_FIRST (1 << 19) -# define RADEON_FORCE_BURST_ALWAYS (1 << 21) -# define RADEON_UV_POST_SCALE_BYPASS (1 << 23) -# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 -#define RADEON_TV_VSCALER_CNTL2 0x0854 -# define RADEON_DITHER_MODE (1 << 0) -# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) -# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) -# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) -#define RADEON_TV_Y_FALL_CNTL 0x0858 -# define RADEON_Y_FALL_PING_PONG (1 << 16) -# define RADEON_Y_COEF_EN (1 << 17) -#define RADEON_TV_Y_RISE_CNTL 0x085c -# define RADEON_Y_RISE_PING_PONG (1 << 16) -#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 -#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 -# define RADEON_YUPSAMP_EN (1 << 0) -# define RADEON_UVUPSAMP_EN (1 << 2) -#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 -# define RADEON_Y_GAIN_LIMIT_SHIFT 0 -# define RADEON_UV_GAIN_LIMIT_SHIFT 16 -#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c -# define RADEON_Y_GAIN_SHIFT 0 -# define RADEON_UV_GAIN_SHIFT 16 -#define RADEON_TV_MODULATOR_CNTL1 0x0870 -# define RADEON_YFLT_EN (1 << 2) -# define RADEON_UVFLT_EN (1 << 3) -# define RADEON_ALT_PHASE_EN (1 << 6) -# define RADEON_SYNC_TIP_LEVEL (1 << 7) -# define RADEON_BLANK_LEVEL_SHIFT 8 -# define RADEON_SET_UP_LEVEL_SHIFT 16 -# define RADEON_SLEW_RATE_LIMIT (1 << 23) -# define RADEON_CY_FILT_BLEND_SHIFT 28 -#define RADEON_TV_MODULATOR_CNTL2 0x0874 -# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff -# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff -# define RADEON_TV_V_BURST_LEVEL_SHIFT 16 -#define RADEON_TV_CRC_CNTL 0x0890 -#define RADEON_TV_UV_ADR 0x08ac -# define RADEON_MAX_UV_ADR_MASK 0x000000ff -# define RADEON_MAX_UV_ADR_SHIFT 0 -# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 -# define RADEON_TABLE1_BOT_ADR_SHIFT 8 -# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 -# define RADEON_TABLE3_TOP_ADR_SHIFT 16 -# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 -# define RADEON_HCODE_TABLE_SEL_SHIFT 25 -# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 -# define RADEON_VCODE_TABLE_SEL_SHIFT 27 -# define RADEON_TV_MAX_FIFO_ADDR 0x1a7 -# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff -#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ -#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ -# define RADEON_TV_M0LO_MASK 0xff -# define RADEON_TV_M0HI_MASK 0x7 -# define RADEON_TV_M0HI_SHIFT 18 -# define RADEON_TV_N0LO_MASK 0x1ff -# define RADEON_TV_N0LO_SHIFT 8 -# define RADEON_TV_N0HI_MASK 0x3 -# define RADEON_TV_N0HI_SHIFT 21 -# define RADEON_TV_P_MASK 0xf -# define RADEON_TV_P_SHIFT 24 -# define RADEON_TV_SLIP_EN (1 << 23) -# define RADEON_TV_DTO_EN (1 << 28) -#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ -# define RADEON_TVPLL_RESET (1 << 1) -# define RADEON_TVPLL_SLEEP (1 << 3) -# define RADEON_TVPLL_REFCLK_SEL (1 << 4) -# define RADEON_TVPCP_SHIFT 8 -# define RADEON_TVPCP_MASK (7 << 8) -# define RADEON_TVPVG_SHIFT 11 -# define RADEON_TVPVG_MASK (7 << 11) -# define RADEON_TVPDC_SHIFT 14 -# define RADEON_TVPDC_MASK (3 << 14) -# define RADEON_TVPLL_TEST_DIS (1 << 31) -# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) - -#define RS400_DISP2_REQ_CNTL1 0xe30 -# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 -# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 -# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 -# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff -#define RS400_DISP2_REQ_CNTL2 0xe34 -# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 -# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff -# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 -# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff -#define RS400_DMIF_MEM_CNTL1 0xe38 -# define RS400_DISP2_START_ADR_SHIFT 0 -# define RS400_DISP2_START_ADR_MASK 0x3ff -# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 -# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff -# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 -# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff -#define RS400_DISP1_REQ_CNTL1 0xe3c -# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 -# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 -# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 -# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff - -#define RS690_MC_INDEX 0x78 -# define RS690_MC_INDEX_MASK 0x1ff -# define RS690_MC_INDEX_WR_EN (1 << 9) -# define RS690_MC_INDEX_WR_ACK 0x7f -#define RS690_MC_DATA 0x7c - -#define RS690_MC_FB_LOCATION 0x100 -#define RS690_MC_AGP_LOCATION 0x101 -#define RS690_MC_AGP_BASE 0x102 -#define RS690_MC_AGP_BASE_2 0x103 -#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 -#define RS690_MC_STATUS 0x90 -#define RS690_MC_STATUS_IDLE (1 << 0) - -#define RS600_MC_INDEX 0x70 -# define RS600_MC_ADDR_MASK 0xffff -# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) -# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) -# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) -# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) -# define RS600_MC_IND_AIC_RBS (1 << 20) -# define RS600_MC_IND_CITF_ARB0 (1 << 21) -# define RS600_MC_IND_CITF_ARB1 (1 << 22) -# define RS600_MC_IND_WR_EN (1 << 23) -#define RS600_MC_DATA 0x74 - -#define RS600_MC_STATUS 0x0 -# define RS600_MC_IDLE (1 << 1) -#define RS600_MC_FB_LOCATION 0x4 -#define RS600_MC_AGP_LOCATION 0x5 -#define RS600_AGP_BASE 0x6 -#define RS600_AGP_BASE2 0x7 - -#define AVIVO_MC_INDEX 0x0070 -#define R520_MC_STATUS 0x00 -# define R520_MC_STATUS_IDLE (1 << 1) -#define RV515_MC_STATUS 0x08 -# define RV515_MC_STATUS_IDLE (1 << 4) -#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 -#define AVIVO_MC_DATA 0x0074 - -#define RV515_MC_FB_LOCATION 0x1 -#define RV515_MC_AGP_LOCATION 0x2 -#define RV515_MC_AGP_BASE 0x3 -#define RV515_MC_AGP_BASE_2 0x4 -#define RV515_MC_CNTL 0x5 -# define RV515_MEM_NUM_CHANNELS_MASK 0x3 -#define R520_MC_FB_LOCATION 0x4 -#define R520_MC_AGP_LOCATION 0x5 -#define R520_MC_AGP_BASE 0x6 -#define R520_MC_AGP_BASE_2 0x7 -#define R520_MC_CNTL0 0x8 -# define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) -# define R520_MEM_NUM_CHANNELS_SHIFT 24 -# define R520_MC_CHANNEL_SIZE (1 << 23) - -#define RS780_MC_INDEX 0x28f8 -# define RS780_MC_INDEX_MASK 0x1ff -# define RS780_MC_INDEX_WR_EN (1 << 9) -#define RS780_MC_DATA 0x28fc - -#define R600_RAMCFG 0x2408 -# define R600_CHANSIZE (1 << 7) -# define R600_CHANSIZE_OVERRIDE (1 << 10) - -#define R600_SRBM_STATUS 0x0e50 - -#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ -# define AVIVO_CP_FORCEON (1 << 0) -#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ -# define AVIVO_E2_FORCEON (1 << 0) -#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ -# define AVIVO_IDCT_FORCEON (1 << 0) - -#define AVIVO_HDP_FB_LOCATION 0x134 - -#define AVIVO_VGA_RENDER_CONTROL 0x0300 -# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) -#define AVIVO_D1VGA_CONTROL 0x0330 -# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) -# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) -# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) -# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) -# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) -# define AVIVO_DVGA_CONTROL_ROTATE (1<<24) -#define AVIVO_D2VGA_CONTROL 0x0338 - -#define AVIVO_VGA25_PPLL_REF_DIV_SRC 0x0360 -#define AVIVO_VGA25_PPLL_REF_DIV 0x0364 -#define AVIVO_VGA28_PPLL_REF_DIV_SRC 0x0368 -#define AVIVO_VGA28_PPLL_REF_DIV 0x036c -#define AVIVO_VGA41_PPLL_REF_DIV_SRC 0x0370 -#define AVIVO_VGA41_PPLL_REF_DIV 0x0374 -#define AVIVO_VGA25_PPLL_FB_DIV 0x0378 -#define AVIVO_VGA28_PPLL_FB_DIV 0x037c -#define AVIVO_VGA41_PPLL_FB_DIV 0x0380 -#define AVIVO_VGA25_PPLL_POST_DIV_SRC 0x0384 -#define AVIVO_VGA25_PPLL_POST_DIV 0x0388 -#define AVIVO_VGA28_PPLL_POST_DIV_SRC 0x038c -#define AVIVO_VGA28_PPLL_POST_DIV 0x0390 -#define AVIVO_VGA41_PPLL_POST_DIV_SRC 0x0394 -#define AVIVO_VGA41_PPLL_POST_DIV 0x0398 -#define AVIVO_VGA25_PPLL_CNTL 0x039c -#define AVIVO_VGA28_PPLL_CNTL 0x03a0 -#define AVIVO_VGA41_PPLL_CNTL 0x03a4 - -#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 -#define AVIVO_EXT1_PPLL_REF_DIV 0x404 -#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 -#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c - -#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 -#define AVIVO_EXT2_PPLL_REF_DIV 0x414 -#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 -#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c - -#define AVIVO_EXT1_PPLL_FB_DIV 0x430 -#define AVIVO_EXT2_PPLL_FB_DIV 0x434 - -#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 -#define AVIVO_EXT1_PPLL_POST_DIV 0x43c - -#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 -#define AVIVO_EXT2_PPLL_POST_DIV 0x444 - -#define AVIVO_EXT1_PPLL_CNTL 0x448 -#define AVIVO_EXT2_PPLL_CNTL 0x44c - -#define AVIVO_P1PLL_CNTL 0x450 -#define AVIVO_P2PLL_CNTL 0x454 -#define AVIVO_P1PLL_INT_SS_CNTL 0x458 -#define AVIVO_P2PLL_INT_SS_CNTL 0x45c -#define AVIVO_P1PLL_TMDSA_CNTL 0x460 -#define AVIVO_P2PLL_LVTMA_CNTL 0x464 - -#define AVIVO_PCLK_CRTC1_CNTL 0x480 -#define AVIVO_PCLK_CRTC2_CNTL 0x484 - -#define AVIVO_D1CRTC_H_TOTAL 0x6000 -#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 -#define AVIVO_D1CRTC_H_SYNC_A 0x6008 -#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c -#define AVIVO_D1CRTC_H_SYNC_B 0x6010 -#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 - -#define AVIVO_D1CRTC_V_TOTAL 0x6020 -#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 -#define AVIVO_D1CRTC_V_SYNC_A 0x6028 -#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c -#define AVIVO_D1CRTC_V_SYNC_B 0x6030 -#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 - -#define AVIVO_D1CRTC_CONTROL 0x6080 -# define AVIVO_CRTC_EN (1<<0) -#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 -#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 -#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c -#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 - -/* master controls */ -#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 -#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc - -#define AVIVO_D1GRPH_ENABLE 0x6100 -#define AVIVO_D1GRPH_CONTROL 0x6104 -# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) -# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) -# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) -# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) - -# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) - -# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) - -# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) -# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) -# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) -# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) - - -# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) - -# define AVIVO_D1GRPH_SWAP_RB (1<<16) -# define AVIVO_D1GRPH_TILED (1<<20) -# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) - -#define AVIVO_D1GRPH_LUT_SEL 0x6108 - -#define R600_D1GRPH_SWAP_CONTROL 0x610C -# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) - -/* the *_HIGH surface regs are backwards; the D1 regs are in the D2 - * block and vice versa. This applies to GRPH, CUR, etc. - */ - -#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 -#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 -#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 -#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 -#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c -#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c -#define AVIVO_D1GRPH_PITCH 0x6120 -#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 -#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 -#define AVIVO_D1GRPH_X_START 0x612c -#define AVIVO_D1GRPH_Y_START 0x6130 -#define AVIVO_D1GRPH_X_END 0x6134 -#define AVIVO_D1GRPH_Y_END 0x6138 -#define AVIVO_D1GRPH_UPDATE 0x6144 -# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) -#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 - -#define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380 - -#define AVIVO_D1CUR_CONTROL 0x6400 -# define AVIVO_D1CURSOR_EN (1<<0) -# define AVIVO_D1CURSOR_MODE_SHIFT 8 -# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) -# define AVIVO_D1CURSOR_MODE_24BPP (0x2) -#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 -#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c -#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c -#define AVIVO_D1CUR_SIZE 0x6410 -#define AVIVO_D1CUR_POSITION 0x6414 -#define AVIVO_D1CUR_HOT_SPOT 0x6418 -#define AVIVO_D1CUR_UPDATE 0x6424 -# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) - -#define AVIVO_DC_LUT_RW_SELECT 0x6480 -#define AVIVO_DC_LUT_RW_MODE 0x6484 -#define AVIVO_DC_LUT_RW_INDEX 0x6488 -#define AVIVO_DC_LUT_SEQ_COLOR 0x648c -#define AVIVO_DC_LUT_PWL_DATA 0x6490 -#define AVIVO_DC_LUT_30_COLOR 0x6494 -#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 -#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c -#define AVIVO_DC_LUT_AUTOFILL 0x64a0 - -#define AVIVO_DC_LUTA_CONTROL 0x64c0 -#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 -#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 -#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc -#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 -#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 -#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 - -#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 -# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 -# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 -# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) -# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 -# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff -#define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548 -# define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff -# define AVIVO_DxMODE_PRIORITY_OFF (1 << 16) -# define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20) -# define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24) -#define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c -#define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48 -#define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c -#define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58 -# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf -# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 -# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf -# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 - -#define AVIVO_D1MODE_DATA_FORMAT 0x6528 -# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) -#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c -#define AVIVO_D1MODE_VLINE_START_END 0x6538 -# define AVIVO_D1MODE_VLINE_START_SHIFT 0 -# define AVIVO_D1MODE_VLINE_END_SHIFT 16 -# define AVIVO_D1MODE_VLINE_INV (1 << 31) -#define AVIVO_D1MODE_VLINE_STATUS 0x653c -# define AVIVO_D1MODE_VLINE_STAT (1 << 12) -#define AVIVO_D1MODE_VIEWPORT_START 0x6580 -#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 -#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 -#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c - -#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 -#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 -#define AVIVO_D1SCL_UPDATE 0x65cc -# define AVIVO_D1SCL_UPDATE_LOCK (1<<16) - -/* second crtc */ -#define AVIVO_D2CRTC_H_TOTAL 0x6800 -#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 -#define AVIVO_D2CRTC_H_SYNC_A 0x6808 -#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c -#define AVIVO_D2CRTC_H_SYNC_B 0x6810 -#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 - -#define AVIVO_D2CRTC_V_TOTAL 0x6820 -#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 -#define AVIVO_D2CRTC_V_SYNC_A 0x6828 -#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c -#define AVIVO_D2CRTC_V_SYNC_B 0x6830 -#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 - -#define AVIVO_D2CRTC_CONTROL 0x6880 -#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 -#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 -#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c -#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 - -#define AVIVO_D2GRPH_ENABLE 0x6900 -#define AVIVO_D2GRPH_CONTROL 0x6904 -#define AVIVO_D2GRPH_LUT_SEL 0x6908 -#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 -#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 -#define AVIVO_D2GRPH_PITCH 0x6920 -#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 -#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 -#define AVIVO_D2GRPH_X_START 0x692c -#define AVIVO_D2GRPH_Y_START 0x6930 -#define AVIVO_D2GRPH_X_END 0x6934 -#define AVIVO_D2GRPH_Y_END 0x6938 -#define AVIVO_D2GRPH_UPDATE 0x6944 -#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 - -#define AVIVO_D2CUR_CONTROL 0x6c00 -#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 -#define AVIVO_D2CUR_SIZE 0x6c10 -#define AVIVO_D2CUR_POSITION 0x6c14 - -#define RS690_DCP_CONTROL 0x6c9c - -#define AVIVO_D2MODE_DATA_FORMAT 0x6d28 -#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c -#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 -#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 -#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 -#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c - -#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 -#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 -#define AVIVO_D2SCL_UPDATE 0x6dcc - -#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 - -#define AVIVO_DACA_ENABLE 0x7800 -# define AVIVO_DAC_ENABLE (1 << 0) -#define AVIVO_DACA_SOURCE_SELECT 0x7804 -# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) -# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) -# define AVIVO_DAC_SOURCE_TV (2 << 0) - -#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) -#define AVIVO_DACA_POWERDOWN 0x7850 -# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) -# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) -# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) -# define AVIVO_DACA_POWERDOWN_RED (1 << 24) - -#define AVIVO_DACB_ENABLE 0x7a00 -#define AVIVO_DACB_SOURCE_SELECT 0x7a04 -#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) -#define AVIVO_DACB_POWERDOWN 0x7a50 -# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) -# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) -# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) -# define AVIVO_DACB_POWERDOWN_RED - -#define AVIVO_TMDSA_CNTL 0x7880 -# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) -# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) -# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) -# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) -# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) -# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) -# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) -#define AVIVO_TMDSA_SOURCE_SELECT 0x7884 -/* 78a8 appears to be some kind of (reasonably tolerant) clock? - * 78d0 definitely hits the transmitter, definitely clock. */ -/* MYSTERY1 This appears to control dithering? */ -#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) -#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 -# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) -# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) -# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) -# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) -#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 -# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) -# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) -#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 -#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) - -#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) - -#define AVIVO_LVTMA_CNTL 0x7a80 -# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) -# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) -# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) -# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) -# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) -# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) -# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) -#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 -#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 -#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) - - - -#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 -# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) -# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) -# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) -# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) - -#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 -# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) -# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) -#define R500_LVTMA_CLOCK_ENABLE 0x7b00 -#define R600_LVTMA_CLOCK_ENABLE 0x7b04 - -#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 -#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) - -#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 -#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) - -#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 -#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 -# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) -# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) -# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) -# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) -# define AVIVO_LVTMA_SYNCEN (1 << 8) -# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) -# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) -# define AVIVO_LVTMA_DIGON (1 << 16) -# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) -# define AVIVO_LVTMA_DIGON_POL (1 << 18) -# define AVIVO_LVTMA_BLON (1 << 24) -# define AVIVO_LVTMA_BLON_OVRD (1 << 25) -# define AVIVO_LVTMA_BLON_POL (1 << 26) - -#define R500_LVTMA_PWRSEQ_STATE 0x7af4 -#define R600_LVTMA_PWRSEQ_STATE 0x7af8 -# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) -# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) -# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) -# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) -# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) -# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) - -#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 -# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) -# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 -# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 - -#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 - -#define AVIVO_GPIO_0 0x7e30 -#define AVIVO_GPIO_1 0x7e40 -#define AVIVO_GPIO_2 0x7e50 -#define AVIVO_GPIO_3 0x7e60 - -#define AVIVO_DC_GPIO_HPD_MASK 0x7e90 -#define AVIVO_DC_GPIO_HPD_A 0x7e94 -#define AVIVO_DC_GPIO_HPD_EN 0x7e98 -#define AVIVO_DC_GPIO_HPD_Y 0x7e9c - -#define AVIVO_I2C_STATUS 0x7d30 -# define AVIVO_I2C_STATUS_DONE (1 << 0) -# define AVIVO_I2C_STATUS_NACK (1 << 1) -# define AVIVO_I2C_STATUS_HALT (1 << 2) -# define AVIVO_I2C_STATUS_GO (1 << 3) -# define AVIVO_I2C_STATUS_MASK 0x7 -/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe - * DONE? */ -# define AVIVO_I2C_STATUS_CMD_RESET 0x7 -# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) -#define AVIVO_I2C_STOP 0x7d34 -#define AVIVO_I2C_START_CNTL 0x7d38 -# define AVIVO_I2C_START (1 << 8) -# define AVIVO_I2C_CONNECTOR0 (0 << 16) -# define AVIVO_I2C_CONNECTOR1 (1 << 16) -#define R520_I2C_START (1<<0) -#define R520_I2C_STOP (1<<1) -#define R520_I2C_RX (1<<2) -#define R520_I2C_EN (1<<8) -#define R520_I2C_DDC1 (0<<16) -#define R520_I2C_DDC2 (1<<16) -#define R520_I2C_DDC3 (2<<16) -#define R520_I2C_DDC_MASK (3<<16) -#define AVIVO_I2C_CONTROL2 0x7d3c -# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 -# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) -#define AVIVO_I2C_CONTROL3 0x7d40 -/* Reading is done 4 bytes at a time: read the bottom 8 bits from - * 7d44, four times in a row. - * Writing is a little more complex. First write DATA with - * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic - * magic number, zz is, I think, the slave address, and yy is the byte - * you want to write. */ -#define AVIVO_I2C_DATA 0x7d44 -#define R520_I2C_ADDR_COUNT_MASK (0x7) -#define R520_I2C_DATA_COUNT_SHIFT (8) -#define R520_I2C_DATA_COUNT_MASK (0xF00) -#define AVIVO_I2C_CNTL 0x7d50 -# define AVIVO_I2C_EN (1 << 0) -# define AVIVO_I2C_RESET (1 << 8) - -#define R600_GENERAL_PWRMGT 0x618 -# define R600_OPEN_DRAIN_PADS (1 << 11) - -#define R600_LOWER_GPIO_ENABLE 0x710 -#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 -#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c -#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 -#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 - -#define R600_MC_VM_FB_LOCATION 0x2180 -#define R600_MC_VM_AGP_TOP 0x2184 -#define R600_MC_VM_AGP_BOT 0x2188 -#define R600_MC_VM_AGP_BASE 0x218c -#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 -#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 -#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 - -#define R700_MC_VM_FB_LOCATION 0x2024 -#define R700_MC_VM_AGP_TOP 0x2028 -#define R700_MC_VM_AGP_BOT 0x202c -#define R700_MC_VM_AGP_BASE 0x2030 - -#define R600_HDP_NONSURFACE_BASE 0x2c04 - -#define R600_BUS_CNTL 0x5420 -#define R600_CONFIG_CNTL 0x5424 -#define R600_CONFIG_MEMSIZE 0x5428 -#define R600_CONFIG_F0_BASE 0x542C -#define R600_CONFIG_APER_SIZE 0x5430 - -#define R600_ROM_CNTL 0x1600 -# define R600_SCK_OVERWRITE (1 << 1) -# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 -# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) - -#define R600_CG_SPLL_FUNC_CNTL 0x600 -# define R600_SPLL_BYPASS_EN (1 << 3) -#define R600_CG_SPLL_STATUS 0x60c -# define R600_SPLL_CHG_STATUS (1 << 1) - -#define R600_BIOS_0_SCRATCH 0x1724 -#define R600_BIOS_1_SCRATCH 0x1728 -#define R600_BIOS_2_SCRATCH 0x172c -#define R600_BIOS_3_SCRATCH 0x1730 -#define R600_BIOS_4_SCRATCH 0x1734 -#define R600_BIOS_5_SCRATCH 0x1738 -#define R600_BIOS_6_SCRATCH 0x173c -#define R600_BIOS_7_SCRATCH 0x1740 - -/* evergreen */ -#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 -#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 -#define EVERGREEN_D3VGA_CONTROL 0x3e0 -#define EVERGREEN_D4VGA_CONTROL 0x3e4 -#define EVERGREEN_D5VGA_CONTROL 0x3e8 -#define EVERGREEN_D6VGA_CONTROL 0x3ec - -#define EVERGREEN_P1PLL_SS_CNTL 0x414 -#define EVERGREEN_P2PLL_SS_CNTL 0x454 -# define EVERGREEN_PxPLL_SS_EN (1 << 12) -/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ -#define EVERGREEN_GRPH_ENABLE 0x6800 -#define EVERGREEN_GRPH_CONTROL 0x6804 -# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) -# define EVERGREEN_GRPH_DEPTH_8BPP 0 -# define EVERGREEN_GRPH_DEPTH_16BPP 1 -# define EVERGREEN_GRPH_DEPTH_32BPP 2 -# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) -/* 8 BPP */ -# define EVERGREEN_GRPH_FORMAT_INDEXED 0 -/* 16 BPP */ -# define EVERGREEN_GRPH_FORMAT_ARGB1555 0 -# define EVERGREEN_GRPH_FORMAT_ARGB565 1 -# define EVERGREEN_GRPH_FORMAT_ARGB4444 2 -# define EVERGREEN_GRPH_FORMAT_AI88 3 -# define EVERGREEN_GRPH_FORMAT_MONO16 4 -# define EVERGREEN_GRPH_FORMAT_BGRA5551 5 -/* 32 BPP */ -# define EVERGREEN_GRPH_FORMAT_ARGB8888 0 -# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 -# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 -# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 -# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 -# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 -# define EVERGREEN_GRPH_FORMAT_RGB111110 6 -# define EVERGREEN_GRPH_FORMAT_BGR101111 7 -#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c -# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) -# define EVERGREEN_GRPH_ENDIAN_NONE 0 -# define EVERGREEN_GRPH_ENDIAN_8IN16 1 -# define EVERGREEN_GRPH_ENDIAN_8IN32 2 -# define EVERGREEN_GRPH_ENDIAN_8IN64 3 -# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) -# define EVERGREEN_GRPH_RED_SEL_R 0 -# define EVERGREEN_GRPH_RED_SEL_G 1 -# define EVERGREEN_GRPH_RED_SEL_B 2 -# define EVERGREEN_GRPH_RED_SEL_A 3 -# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) -# define EVERGREEN_GRPH_GREEN_SEL_G 0 -# define EVERGREEN_GRPH_GREEN_SEL_B 1 -# define EVERGREEN_GRPH_GREEN_SEL_A 2 -# define EVERGREEN_GRPH_GREEN_SEL_R 3 -# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) -# define EVERGREEN_GRPH_BLUE_SEL_B 0 -# define EVERGREEN_GRPH_BLUE_SEL_A 1 -# define EVERGREEN_GRPH_BLUE_SEL_R 2 -# define EVERGREEN_GRPH_BLUE_SEL_G 3 -# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) -# define EVERGREEN_GRPH_ALPHA_SEL_A 0 -# define EVERGREEN_GRPH_ALPHA_SEL_R 1 -# define EVERGREEN_GRPH_ALPHA_SEL_G 2 -# define EVERGREEN_GRPH_ALPHA_SEL_B 3 -#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 -#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 -# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) -# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 -#define EVERGREEN_GRPH_PITCH 0x6818 -#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c -#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 -#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 -#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 -#define EVERGREEN_GRPH_X_START 0x682c -#define EVERGREEN_GRPH_Y_START 0x6830 -#define EVERGREEN_GRPH_X_END 0x6834 -#define EVERGREEN_GRPH_Y_END 0x6838 - -/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ -#define EVERGREEN_CUR_CONTROL 0x6998 -# define EVERGREEN_CURSOR_EN (1 << 0) -# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) -# define EVERGREEN_CURSOR_MONO 0 -# define EVERGREEN_CURSOR_24_1 1 -# define EVERGREEN_CURSOR_24_8_PRE_MULT 2 -# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 -# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) -# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) -# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) -# define EVERGREEN_CURSOR_URGENT_ALWAYS 0 -# define EVERGREEN_CURSOR_URGENT_1_8 1 -# define EVERGREEN_CURSOR_URGENT_1_4 2 -# define EVERGREEN_CURSOR_URGENT_3_8 3 -# define EVERGREEN_CURSOR_URGENT_1_2 4 -#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c -# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 -#define EVERGREEN_CUR_SIZE 0x69a0 -#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 -#define EVERGREEN_CUR_POSITION 0x69a8 -#define EVERGREEN_CUR_HOT_SPOT 0x69ac -#define EVERGREEN_CUR_COLOR1 0x69b0 -#define EVERGREEN_CUR_COLOR2 0x69b4 -#define EVERGREEN_CUR_UPDATE 0x69b8 -# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) -# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) -# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) -# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) - -/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ -#define EVERGREEN_DC_LUT_RW_MODE 0x69e0 -#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 -#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 -#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec -#define EVERGREEN_DC_LUT_30_COLOR 0x69f0 -#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 -#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 -#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc -#define EVERGREEN_DC_LUT_CONTROL 0x6a00 -#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 -#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 -#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c -#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 -#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 -#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 - -#define EVERGREEN_DATA_FORMAT 0x6b00 -# define EVERGREEN_INTERLEAVE_EN (1 << 0) -#define EVERGREEN_DESKTOP_HEIGHT 0x6b04 - -#define EVERGREEN_VIEWPORT_START 0x6d70 -#define EVERGREEN_VIEWPORT_SIZE 0x6d74 - -/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ -#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) -#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) -#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) -#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) -#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) -#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) - -/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ -#define EVERGREEN_CRTC_CONTROL 0x6e70 -# define EVERGREEN_CRTC_MASTER_EN (1 << 0) -#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 - -#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 -#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 -#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 -#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc - -#define R300_GB_TILE_CONFIG 0x4018 -# define R300_ENABLE_TILING (1 << 0) -# define R300_PIPE_COUNT_RV350 (0 << 1) -# define R300_PIPE_COUNT_R300 (3 << 1) -# define R300_PIPE_COUNT_R420_3P (6 << 1) -# define R300_PIPE_COUNT_R420 (7 << 1) -# define R300_TILE_SIZE_8 (0 << 4) -# define R300_TILE_SIZE_16 (1 << 4) -# define R300_TILE_SIZE_32 (2 << 4) -# define R300_SUBPIXEL_1_12 (0 << 16) -# define R300_SUBPIXEL_1_16 (1 << 16) -#define R300_GB_SELECT 0x401c -#define R300_GB_ENABLE 0x4008 -#define R300_GB_AA_CONFIG 0x4020 -#define R400_GB_PIPE_SELECT 0x402c -#define R300_GB_MSPOS0 0x4010 -# define R300_MS_X0_SHIFT 0 -# define R300_MS_Y0_SHIFT 4 -# define R300_MS_X1_SHIFT 8 -# define R300_MS_Y1_SHIFT 12 -# define R300_MS_X2_SHIFT 16 -# define R300_MS_Y2_SHIFT 20 -# define R300_MSBD0_Y_SHIFT 24 -# define R300_MSBD0_X_SHIFT 28 -#define R300_GB_MSPOS1 0x4014 -# define R300_MS_X3_SHIFT 0 -# define R300_MS_Y3_SHIFT 4 -# define R300_MS_X4_SHIFT 8 -# define R300_MS_Y4_SHIFT 12 -# define R300_MS_X5_SHIFT 16 -# define R300_MS_Y5_SHIFT 20 -# define R300_MSBD1_SHIFT 24 - -#define R300_GA_ENHANCE 0x4274 -# define R300_GA_DEADLOCK_CNTL (1 << 0) -# define R300_GA_FASTSYNC_CNTL (1 << 1) - -#define R300_GA_POLY_MODE 0x4288 -# define R300_FRONT_PTYPE_POINT (0 << 4) -# define R300_FRONT_PTYPE_LINE (1 << 4) -# define R300_FRONT_PTYPE_TRIANGE (2 << 4) -# define R300_BACK_PTYPE_POINT (0 << 7) -# define R300_BACK_PTYPE_LINE (1 << 7) -# define R300_BACK_PTYPE_TRIANGE (2 << 7) -#define R300_GA_ROUND_MODE 0x428c -# define R300_GEOMETRY_ROUND_TRUNC (0 << 0) -# define R300_GEOMETRY_ROUND_NEAREST (1 << 0) -# define R300_COLOR_ROUND_TRUNC (0 << 2) -# define R300_COLOR_ROUND_NEAREST (1 << 2) -#define R300_GA_COLOR_CONTROL 0x4278 -# define R300_RGB0_SHADING_SOLID (0 << 0) -# define R300_RGB0_SHADING_FLAT (1 << 0) -# define R300_RGB0_SHADING_GOURAUD (2 << 0) -# define R300_ALPHA0_SHADING_SOLID (0 << 2) -# define R300_ALPHA0_SHADING_FLAT (1 << 2) -# define R300_ALPHA0_SHADING_GOURAUD (2 << 2) -# define R300_RGB1_SHADING_SOLID (0 << 4) -# define R300_RGB1_SHADING_FLAT (1 << 4) -# define R300_RGB1_SHADING_GOURAUD (2 << 4) -# define R300_ALPHA1_SHADING_SOLID (0 << 6) -# define R300_ALPHA1_SHADING_FLAT (1 << 6) -# define R300_ALPHA1_SHADING_GOURAUD (2 << 6) -# define R300_RGB2_SHADING_SOLID (0 << 8) -# define R300_RGB2_SHADING_FLAT (1 << 8) -# define R300_RGB2_SHADING_GOURAUD (2 << 8) -# define R300_ALPHA2_SHADING_SOLID (0 << 10) -# define R300_ALPHA2_SHADING_FLAT (1 << 10) -# define R300_ALPHA2_SHADING_GOURAUD (2 << 10) -# define R300_RGB3_SHADING_SOLID (0 << 12) -# define R300_RGB3_SHADING_FLAT (1 << 12) -# define R300_RGB3_SHADING_GOURAUD (2 << 12) -# define R300_ALPHA3_SHADING_SOLID (0 << 14) -# define R300_ALPHA3_SHADING_FLAT (1 << 14) -# define R300_ALPHA3_SHADING_GOURAUD (2 << 14) -#define R300_GA_OFFSET 0x4290 - -#define R500_SU_REG_DEST 0x42c8 - -#define R300_VAP_CNTL_STATUS 0x2140 -# define R300_PVS_BYPASS (1 << 8) -#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 -#define R300_VAP_CNTL 0x2080 -# define R300_PVS_NUM_SLOTS_SHIFT 0 -# define R300_PVS_NUM_CNTLRS_SHIFT 4 -# define R300_PVS_NUM_FPUS_SHIFT 8 -# define R300_VF_MAX_VTX_NUM_SHIFT 18 -# define R300_GL_CLIP_SPACE_DEF (0 << 22) -# define R300_DX_CLIP_SPACE_DEF (1 << 22) -# define R500_TCL_STATE_OPTIMIZATION (1 << 23) -#define R300_VAP_VTE_CNTL 0x20B0 -# define R300_VPORT_X_SCALE_ENA (1 << 0) -# define R300_VPORT_X_OFFSET_ENA (1 << 1) -# define R300_VPORT_Y_SCALE_ENA (1 << 2) -# define R300_VPORT_Y_OFFSET_ENA (1 << 3) -# define R300_VPORT_Z_SCALE_ENA (1 << 4) -# define R300_VPORT_Z_OFFSET_ENA (1 << 5) -# define R300_VTX_XY_FMT (1 << 8) -# define R300_VTX_Z_FMT (1 << 9) -# define R300_VTX_W0_FMT (1 << 10) -#define R300_VAP_VTX_STATE_CNTL 0x2180 -#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC -#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 -# define R300_DATA_TYPE_0_SHIFT 0 -# define R300_DATA_TYPE_FLOAT_1 0 -# define R300_DATA_TYPE_FLOAT_2 1 -# define R300_DATA_TYPE_FLOAT_3 2 -# define R300_DATA_TYPE_FLOAT_4 3 -# define R300_DATA_TYPE_BYTE 4 -# define R300_DATA_TYPE_D3DCOLOR 5 -# define R300_DATA_TYPE_SHORT_2 6 -# define R300_DATA_TYPE_SHORT_4 7 -# define R300_DATA_TYPE_VECTOR_3_TTT 8 -# define R300_DATA_TYPE_VECTOR_3_EET 9 -# define R300_SKIP_DWORDS_0_SHIFT 4 -# define R300_DST_VEC_LOC_0_SHIFT 8 -# define R300_LAST_VEC_0 (1 << 13) -# define R300_SIGNED_0 (1 << 14) -# define R300_NORMALIZE_0 (1 << 15) -# define R300_DATA_TYPE_1_SHIFT 16 -# define R300_SKIP_DWORDS_1_SHIFT 20 -# define R300_DST_VEC_LOC_1_SHIFT 24 -# define R300_LAST_VEC_1 (1 << 29) -# define R300_SIGNED_1 (1 << 30) -# define R300_NORMALIZE_1 (1 << 31) -#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 -# define R300_DATA_TYPE_2_SHIFT 0 -# define R300_SKIP_DWORDS_2_SHIFT 4 -# define R300_DST_VEC_LOC_2_SHIFT 8 -# define R300_LAST_VEC_2 (1 << 13) -# define R300_SIGNED_2 (1 << 14) -# define R300_NORMALIZE_2 (1 << 15) -# define R300_DATA_TYPE_3_SHIFT 16 -# define R300_SKIP_DWORDS_3_SHIFT 20 -# define R300_DST_VEC_LOC_3_SHIFT 24 -# define R300_LAST_VEC_3 (1 << 29) -# define R300_SIGNED_3 (1 << 30) -# define R300_NORMALIZE_3 (1 << 31) -#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 -# define R300_SWIZZLE_SELECT_X_0_SHIFT 0 -# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 -# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 -# define R300_SWIZZLE_SELECT_W_0_SHIFT 9 -# define R300_SWIZZLE_SELECT_X 0 -# define R300_SWIZZLE_SELECT_Y 1 -# define R300_SWIZZLE_SELECT_Z 2 -# define R300_SWIZZLE_SELECT_W 3 -# define R300_SWIZZLE_SELECT_FP_ZERO 4 -# define R300_SWIZZLE_SELECT_FP_ONE 5 -# define R300_WRITE_ENA_0_SHIFT 12 -# define R300_WRITE_ENA_X 1 -# define R300_WRITE_ENA_Y 2 -# define R300_WRITE_ENA_Z 4 -# define R300_WRITE_ENA_W 8 -# define R300_SWIZZLE_SELECT_X_1_SHIFT 16 -# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 -# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 -# define R300_SWIZZLE_SELECT_W_1_SHIFT 25 -# define R300_WRITE_ENA_1_SHIFT 28 -#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 -# define R300_SWIZZLE_SELECT_X_2_SHIFT 0 -# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 -# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 -# define R300_SWIZZLE_SELECT_W_2_SHIFT 9 -# define R300_WRITE_ENA_2_SHIFT 12 -# define R300_SWIZZLE_SELECT_X_3_SHIFT 16 -# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 -# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 -# define R300_SWIZZLE_SELECT_W_3_SHIFT 25 -# define R300_WRITE_ENA_3_SHIFT 28 -#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 -# define R300_PVS_FIRST_INST_SHIFT 0 -# define R300_PVS_XYZW_VALID_INST_SHIFT 10 -# define R300_PVS_LAST_INST_SHIFT 20 -#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 -# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 -#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 -# define R300_PVS_CODE_START 0 -# define R300_PVS_CONST_START 512 -# define R500_PVS_CONST_START 1024 -# define R300_PVS_VECTOR_INST_INDEX(x) ((x) + R300_PVS_CODE_START) -# define R300_PVS_VECTOR_CONST_INDEX(x) ((x) + R300_PVS_CONST_START) -# define R500_PVS_VECTOR_CONST_INDEX(x) ((x) + R500_PVS_CONST_START) -#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 -/* PVS instructions */ -/* Opcode and dst instruction */ -#define R300_PVS_DST_OPCODE(x) ((x) << 0) -/* Vector ops */ -# define R300_VECTOR_NO_OP 0 -# define R300_VE_DOT_PRODUCT 1 -# define R300_VE_MULTIPLY 2 -# define R300_VE_ADD 3 -# define R300_VE_MULTIPLY_ADD 4 -# define R300_VE_DISTANCE_VECTOR 5 -# define R300_VE_FRACTION 6 -# define R300_VE_MAXIMUM 7 -# define R300_VE_MINIMUM 8 -# define R300_VE_SET_GREATER_THAN_EQUAL 9 -# define R300_VE_SET_LESS_THAN 10 -# define R300_VE_MULTIPLYX2_ADD 11 -# define R300_VE_MULTIPLY_CLAMP 12 -# define R300_VE_FLT2FIX_DX 13 -# define R300_VE_FLT2FIX_DX_RND 14 -/* R500 additions */ -# define R500_VE_PRED_SET_EQ_PUSH 15 -# define R500_VE_PRED_SET_GT_PUSH 16 -# define R500_VE_PRED_SET_GTE_PUSH 17 -# define R500_VE_PRED_SET_NEQ_PUSH 18 -# define R500_VE_COND_WRITE_EQ 19 -# define R500_VE_COND_WRITE_GT 20 -# define R500_VE_COND_WRITE_GTE 21 -# define R500_VE_COND_WRITE_NEQ 22 -# define R500_VE_COND_MUX_EQ 23 -# define R500_VE_COND_MUX_GT 24 -# define R500_VE_COND_MUX_GTE 25 -# define R500_VE_SET_GREATER_THAN 26 -# define R500_VE_SET_EQUAL 27 -# define R500_VE_SET_NOT_EQUAL 28 -/* Math ops */ -# define R300_MATH_NO_OP 0 -# define R300_ME_EXP_BASE2_DX 1 -# define R300_ME_LOG_BASE2_DX 2 -# define R300_ME_EXP_BASEE_FF 3 -# define R300_ME_LIGHT_COEFF_DX 4 -# define R300_ME_POWER_FUNC_FF 5 -# define R300_ME_RECIP_DX 6 -# define R300_ME_RECIP_FF 7 -# define R300_ME_RECIP_SQRT_DX 8 -# define R300_ME_RECIP_SQRT_FF 9 -# define R300_ME_MULTIPLY 10 -# define R300_ME_EXP_BASE2_FULL_DX 11 -# define R300_ME_LOG_BASE2_FULL_DX 12 -# define R300_ME_POWER_FUNC_FF_CLAMP_B 13 -# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 -# define R300_ME_POWER_FUNC_FF_CLAMP_01 15 -# define R300_ME_SIN 16 -# define R300_ME_COS 17 -/* R500 additions */ -# define R500_ME_LOG_BASE2_IEEE 18 -# define R500_ME_RECIP_IEEE 19 -# define R500_ME_RECIP_SQRT_IEEE 20 -# define R500_ME_PRED_SET_EQ 21 -# define R500_ME_PRED_SET_GT 22 -# define R500_ME_PRED_SET_GTE 23 -# define R500_ME_PRED_SET_NEQ 24 -# define R500_ME_PRED_SET_CLR 25 -# define R500_ME_PRED_SET_INV 26 -# define R500_ME_PRED_SET_POP 27 -# define R500_ME_PRED_SET_RESTORE 28 -/* macro */ -# define R300_PVS_MACRO_OP_2CLK_MADD 0 -# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 -#define R300_PVS_DST_MATH_INST (1 << 6) -#define R300_PVS_DST_MACRO_INST (1 << 7) -#define R300_PVS_DST_REG_TYPE(x) ((x) << 8) -# define R300_PVS_DST_REG_TEMPORARY 0 -# define R300_PVS_DST_REG_A0 1 -# define R300_PVS_DST_REG_OUT 2 -# define R500_PVS_DST_REG_OUT_REPL_X 3 -# define R300_PVS_DST_REG_ALT_TEMPORARY 4 -# define R300_PVS_DST_REG_INPUT 5 -#define R300_PVS_DST_ADDR_MODE_1 (1 << 12) -#define R300_PVS_DST_OFFSET(x) ((x) << 13) -#define R300_PVS_DST_WE_X (1 << 20) -#define R300_PVS_DST_WE_Y (1 << 21) -#define R300_PVS_DST_WE_Z (1 << 22) -#define R300_PVS_DST_WE_W (1 << 23) -#define R300_PVS_DST_VE_SAT (1 << 24) -#define R300_PVS_DST_ME_SAT (1 << 25) -#define R300_PVS_DST_PRED_ENABLE (1 << 26) -#define R300_PVS_DST_PRED_SENSE (1 << 27) -#define R300_PVS_DST_DUAL_MATH_OP (1 << 28) -#define R300_PVS_DST_ADDR_SEL(x) ((x) << 29) -#define R300_PVS_DST_ADDR_MODE_0 (1 << 31) -/* src operand instruction */ -#define R300_PVS_SRC_REG_TYPE(x) ((x) << 0) -# define R300_PVS_SRC_REG_TEMPORARY 0 -# define R300_PVS_SRC_REG_INPUT 1 -# define R300_PVS_SRC_REG_CONSTANT 2 -# define R300_PVS_SRC_REG_ALT_TEMPORARY 3 -#define R300_SPARE_0 (1 << 2) -#define R300_PVS_SRC_ABS_XYZW (1 << 3) -#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) -#define R300_PVS_SRC_OFFSET(x) ((x) << 5) -#define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13) -#define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16) -#define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19) -#define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22) -# define R300_PVS_SRC_SELECT_X 0 -# define R300_PVS_SRC_SELECT_Y 1 -# define R300_PVS_SRC_SELECT_Z 2 -# define R300_PVS_SRC_SELECT_W 3 -# define R300_PVS_SRC_SELECT_FORCE_0 4 -# define R300_PVS_SRC_SELECT_FORCE_1 5 -#define R300_PVS_SRC_NEG_X (1 << 25) -#define R300_PVS_SRC_NEG_Y (1 << 26) -#define R300_PVS_SRC_NEG_Z (1 << 27) -#define R300_PVS_SRC_NEG_W (1 << 28) -#define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29) -#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) - -#define R300_VAP_PVS_CONST_CNTL 0x22d4 -# define R300_PVS_CONST_BASE_OFFSET(x) ((x) << 0) -# define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16) - -#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc -#define R300_VAP_OUT_VTX_FMT_0 0x2090 -# define R300_VTX_POS_PRESENT (1 << 0) -# define R300_VTX_COLOR_0_PRESENT (1 << 1) -# define R300_VTX_COLOR_1_PRESENT (1 << 2) -# define R300_VTX_COLOR_2_PRESENT (1 << 3) -# define R300_VTX_COLOR_3_PRESENT (1 << 4) -# define R300_VTX_PT_SIZE_PRESENT (1 << 16) -#define R300_VAP_OUT_VTX_FMT_1 0x2094 -# define R300_TEX_0_COMP_CNT_SHIFT 0 -# define R300_TEX_1_COMP_CNT_SHIFT 3 -# define R300_TEX_2_COMP_CNT_SHIFT 6 -# define R300_TEX_3_COMP_CNT_SHIFT 9 -# define R300_TEX_4_COMP_CNT_SHIFT 12 -# define R300_TEX_5_COMP_CNT_SHIFT 15 -# define R300_TEX_6_COMP_CNT_SHIFT 18 -# define R300_TEX_7_COMP_CNT_SHIFT 21 -#define R300_VAP_VTX_SIZE 0x20b4 -#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 -#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 -#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 -#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c -#define R300_VAP_CLIP_CNTL 0x221c -# define R300_UCP_ENA_0 (1 << 0) -# define R300_UCP_ENA_1 (1 << 1) -# define R300_UCP_ENA_2 (1 << 2) -# define R300_UCP_ENA_3 (1 << 3) -# define R300_UCP_ENA_4 (1 << 4) -# define R300_UCP_ENA_5 (1 << 5) -# define R300_PS_UCP_MODE_SHIFT 14 -# define R300_CLIP_DISABLE (1 << 16) -# define R300_UCP_CULL_ONLY_ENA (1 << 17) -# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) -#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 - -#define R500_VAP_INDEX_OFFSET 0x208c - -#define R300_SU_TEX_WRAP 0x42a0 -#define R300_SU_POLY_OFFSET_ENABLE 0x42b4 -#define R300_SU_CULL_MODE 0x42b8 -# define R300_CULL_FRONT (1 << 0) -# define R300_CULL_BACK (1 << 1) -# define R300_FACE_POS (0 << 2) -# define R300_FACE_NEG (1 << 2) -#define R300_SU_DEPTH_SCALE 0x42c0 -#define R300_SU_DEPTH_OFFSET 0x42c4 - -#define R300_RS_COUNT 0x4300 -# define R300_RS_COUNT_IT_COUNT_SHIFT 0 -# define R300_RS_COUNT_IC_COUNT_SHIFT 7 -# define R300_RS_COUNT_HIRES_EN (1 << 18) - -#define R300_RS_IP_0 0x4310 -#define R300_RS_IP_1 0x4314 -# define R300_RS_TEX_PTR(x) ((x) << 0) -# define R300_RS_COL_PTR(x) ((x) << 6) -# define R300_RS_COL_FMT(x) ((x) << 9) -# define R300_RS_COL_FMT_RGBA 0 -# define R300_RS_COL_FMT_RGB0 2 -# define R300_RS_COL_FMT_RGB1 3 -# define R300_RS_COL_FMT_000A 4 -# define R300_RS_COL_FMT_0000 5 -# define R300_RS_COL_FMT_0001 6 -# define R300_RS_COL_FMT_111A 8 -# define R300_RS_COL_FMT_1110 9 -# define R300_RS_COL_FMT_1111 10 -# define R300_RS_SEL_S(x) ((x) << 13) -# define R300_RS_SEL_T(x) ((x) << 16) -# define R300_RS_SEL_R(x) ((x) << 19) -# define R300_RS_SEL_Q(x) ((x) << 22) -# define R300_RS_SEL_C0 0 -# define R300_RS_SEL_C1 1 -# define R300_RS_SEL_C2 2 -# define R300_RS_SEL_C3 3 -# define R300_RS_SEL_K0 4 -# define R300_RS_SEL_K1 5 -#define R300_RS_INST_COUNT 0x4304 -# define R300_INST_COUNT_RS(x) ((x) << 0) -# define R300_RS_W_EN (1 << 4) -# define R300_TX_OFFSET_RS(x) ((x) << 5) -#define R300_RS_INST_0 0x4330 -#define R300_RS_INST_1 0x4334 -# define R300_INST_TEX_ID(x) ((x) << 0) -# define R300_RS_INST_TEX_CN_WRITE (1 << 3) -# define R300_INST_TEX_ADDR(x) ((x) << 6) - -#define R300_TX_INVALTAGS 0x4100 -#define R300_TX_FILTER0_0 0x4400 -#define R300_TX_FILTER0_1 0x4404 -#define R300_TX_FILTER0_2 0x4408 -# define R300_TX_CLAMP_S(x) ((x) << 0) -# define R300_TX_CLAMP_T(x) ((x) << 3) -# define R300_TX_CLAMP_R(x) ((x) << 6) -# define R300_TX_CLAMP_WRAP 0 -# define R300_TX_CLAMP_MIRROR 1 -# define R300_TX_CLAMP_CLAMP_LAST 2 -# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 -# define R300_TX_CLAMP_CLAMP_BORDER 4 -# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 -# define R300_TX_CLAMP_CLAMP_GL 6 -# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 -# define R300_TX_MAG_FILTER_NEAREST (1 << 9) -# define R300_TX_MIN_FILTER_NEAREST (1 << 11) -# define R300_TX_MAG_FILTER_LINEAR (2 << 9) -# define R300_TX_MIN_FILTER_LINEAR (2 << 11) -# define R300_TX_ID_SHIFT 28 -#define R300_TX_FILTER1_0 0x4440 -#define R300_TX_FILTER1_1 0x4444 -#define R300_TX_FILTER1_2 0x4448 -#define R300_TX_FORMAT0_0 0x4480 -#define R300_TX_FORMAT0_1 0x4484 -#define R300_TX_FORMAT0_2 0x4488 -# define R300_TXWIDTH_SHIFT 0 -# define R300_TXHEIGHT_SHIFT 11 -# define R300_NUM_LEVELS_SHIFT 26 -# define R300_NUM_LEVELS_MASK 0x -# define R300_TXPROJECTED (1 << 30) -# define R300_TXPITCH_EN (1 << 31) -#define R300_TX_FORMAT1_0 0x44c0 -#define R300_TX_FORMAT1_1 0x44c4 -#define R300_TX_FORMAT1_2 0x44c8 -# define R300_TX_FORMAT_X8 0x0 -# define R300_TX_FORMAT_X16 0x1 -# define R300_TX_FORMAT_Y4X4 0x2 -# define R300_TX_FORMAT_Y8X8 0x3 -# define R300_TX_FORMAT_Y16X16 0x4 -# define R300_TX_FORMAT_Z3Y3X2 0x5 -# define R300_TX_FORMAT_Z5Y6X5 0x6 -# define R300_TX_FORMAT_Z6Y5X5 0x7 -# define R300_TX_FORMAT_Z11Y11X10 0x8 -# define R300_TX_FORMAT_Z10Y11X11 0x9 -# define R300_TX_FORMAT_W4Z4Y4X4 0xA -# define R300_TX_FORMAT_W1Z5Y5X5 0xB -# define R300_TX_FORMAT_W8Z8Y8X8 0xC -# define R300_TX_FORMAT_W2Z10Y10X10 0xD -# define R300_TX_FORMAT_W16Z16Y16X16 0xE -# define R300_TX_FORMAT_DXT1 0xF -# define R300_TX_FORMAT_DXT3 0x10 -# define R300_TX_FORMAT_DXT5 0x11 -# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ -# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ -# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ -# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ -# define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ -# define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ -# define R300_TX_FORMAT_X24_Y8 0x1e -# define R300_TX_FORMAT_X32 0x1e - /* Floating point formats */ - /* Note - hardware supports both 16 and 32 bit floating point */ -# define R300_TX_FORMAT_FL_I16 0x18 -# define R300_TX_FORMAT_FL_I16A16 0x19 -# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A -# define R300_TX_FORMAT_FL_I32 0x1B -# define R300_TX_FORMAT_FL_I32A32 0x1C -# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D - /* alpha modes, convenience mostly */ - /* if you have alpha, pick constant appropriate to the - number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ -# define R300_TX_FORMAT_ALPHA_1CH 0x000 -# define R300_TX_FORMAT_ALPHA_2CH 0x200 -# define R300_TX_FORMAT_ALPHA_4CH 0x600 -# define R300_TX_FORMAT_ALPHA_NONE 0xA00 - /* Swizzling */ - /* constants */ -# define R300_TX_FORMAT_X 0 -# define R300_TX_FORMAT_Y 1 -# define R300_TX_FORMAT_Z 2 -# define R300_TX_FORMAT_W 3 -# define R300_TX_FORMAT_ZERO 4 -# define R300_TX_FORMAT_ONE 5 - /* 2.0*Z, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_Z 6 - /* 2.0*W, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_W 7 - -# define R300_TX_FORMAT_B_SHIFT 18 -# define R300_TX_FORMAT_G_SHIFT 15 -# define R300_TX_FORMAT_R_SHIFT 12 -# define R300_TX_FORMAT_A_SHIFT 9 - - /* Convenience macro to take care of layout and swizzling */ -# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ - ((R300_TX_FORMAT_##B)<chameleonConfig); - getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->chameleonConfig); getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->chameleonConfig); while (current) { - devicepath = get_pci_dev_path(current); switch (current->class_id) { @@ -41,25 +35,7 @@ if (do_eth_devprop) set_eth_builtin(current); break; - - case PCI_CLASS_DISPLAY_VGA: - if (do_gfx_devprop) - switch (current->vendor_id) - { - case PCI_VENDOR_ID_ATI: - setup_ati_devprop(current); - break; - - case PCI_VENDOR_ID_INTEL: - setup_gma_devprop(current); - break; - - case PCI_VENDOR_ID_NVIDIA: - setup_nvidia_devprop(current); - break; - } - break; - + case PCI_CLASS_SERIAL_USB: notify_usb_dev(current); break; Index: branches/ErmaC/i386/boot2/boot.h =================================================================== --- branches/ErmaC/i386/boot2/boot.h (revision 1567) +++ branches/ErmaC/i386/boot2/boot.h (revision 1568) @@ -107,16 +107,6 @@ #define kPCIRootUID "PCIRootUID" /* pci_root.c */ -#define kUseAtiROM "UseAtiROM" /* ati.c */ -#define kAtiConfig "AtiConfig" /* ati.c */ -#define kAtiPorts "AtiPorts" /* ati.c */ -#define kATYbinimage "ATYbinimage" /* ati.c */ - -#define kUseNvidiaROM "UseNvidiaROM" /* nvidia.c */ -#define kVBIOS "VBIOS" /* nvidia.c */ -#define kDcfg0 "display_0" /* nvidia.c */ -#define kDcfg1 "display_1" /* nvidia.c */ - #define kEthernetBuiltIn "EthernetBuiltIn" /* pci_setup.c */ #define kGraphicsEnabler "GraphicsEnabler" /* pci_setup.c */ #define kForceHPET "ForceHPET" /* pci_setup.c */ Index: branches/ErmaC/i386/modules/GraphicsEnablerModules.txt =================================================================== --- branches/ErmaC/i386/modules/GraphicsEnablerModules.txt (revision 0) +++ branches/ErmaC/i386/modules/GraphicsEnablerModules.txt (revision 1568) @@ -0,0 +1,22 @@ +This is a port of the graphics enabler code into modules, +based on Meklort's previous port; for all purposes, this is +his work; i'm just trying to help ease the work load and +learn something while doing it. + +Though the modules are in a working state and considered by me +as fit for testing (and use), this is still work in progress. +Please feedback directly to me by pm at: +http://forum.voodooprojects.org/ + + +NOTICE: as of now, i'm considering this work as "LOW PRIORITY". +The folder will be kept synced with the trunk. +Work on the code will be done on a "free time" basis. +Any dev that wants to work directly on the folder is welcome; +i will take care of the "syncing with trunk" part. + +The main reason for this is: +there are more important things to fix on the booter. + + +Azi \ No newline at end of file Index: branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/nvidia.h =================================================================== --- branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/nvidia.h (revision 0) +++ branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/nvidia.h (revision 1568) @@ -0,0 +1,135 @@ +/* + * NVidia injector + * + * Copyright (C) 2009 Jasmin Fazlic, iNDi + * + * NVidia injector is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * NVidia driver and injector is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with NVidia injector. If not, see . + */ + /* + * Alternatively you can choose to comply with APSL + */ + +/* + * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license: + * + * + * Copyright 2005-2006 Erik Waling + * Copyright 2006 Stephane Marchesin + * Copyright 2007-2009 Stuart Bennett + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef __LIBSAIO_NVIDIA_H +#define __LIBSAIO_NVIDIA_H + +bool setup_nvidia_devprop(pci_dt_t *nvda_dev); + +struct nv_chipsets_t { + unsigned device; + char *name; +}; + +#define DCB_MAX_NUM_ENTRIES 16 +#define DCB_MAX_NUM_I2C_ENTRIES 16 + +#define DCB_LOC_ON_CHIP 0 + +struct bios { + uint16_t signature; /* 0x55AA */ + uint8_t size; /* Size in multiples of 512 */ +}; + +#define NV_PROM_OFFSET 0x300000 +#define NV_PROM_SIZE 0x0000ffff +#define NV_PRAMIN_OFFSET 0x00700000 +#define NV_PRAMIN_SIZE 0x00100000 +#define NV04_PFB_FIFO_DATA 0x0010020c +#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 +#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 +#define NVC0_MEM_CTRLR_COUNT 0x00121c74 +#define NVC0_MEM_CTRLR_RAM_AMOUNT 0x0010f20c + +#define NV_PBUS_PCI_NV_20 0x00001850 +#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) +#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) + +#define REG8(reg) ((volatile uint8_t *)regs)[(reg)] +#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1] +#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2] + +#define NV_ARCH_03 0x03 +#define NV_ARCH_04 0x04 +#define NV_ARCH_10 0x10 +#define NV_ARCH_20 0x20 +#define NV_ARCH_30 0x30 +#define NV_ARCH_40 0x40 +#define NV_ARCH_50 0x50 +#define NV_ARCH_C0 0xC0 + +#define CHIPSET_NV03 0x0010 +#define CHIPSET_NV04 0x0020 +#define CHIPSET_NV10 0x0100 +#define CHIPSET_NV11 0x0110 +#define CHIPSET_NV15 0x0150 +#define CHIPSET_NV17 0x0170 +#define CHIPSET_NV18 0x0180 +#define CHIPSET_NFORCE 0x01A0 +#define CHIPSET_NFORCE2 0x01F0 +#define CHIPSET_NV20 0x0200 +#define CHIPSET_NV25 0x0250 +#define CHIPSET_NV28 0x0280 +#define CHIPSET_NV30 0x0300 +#define CHIPSET_NV31 0x0310 +#define CHIPSET_NV34 0x0320 +#define CHIPSET_NV35 0x0330 +#define CHIPSET_NV36 0x0340 +#define CHIPSET_NV40 0x0040 +#define CHIPSET_NV41 0x00C0 +#define CHIPSET_NV43 0x0140 +#define CHIPSET_NV44 0x0160 +#define CHIPSET_NV44A 0x0220 +#define CHIPSET_NV45 0x0210 +#define CHIPSET_NV50 0x0190 +#define CHIPSET_NV84 0x0400 +#define CHIPSET_MISC_BRIDGED 0x00F0 +#define CHIPSET_G70 0x0090 +#define CHIPSET_G71 0x0290 +#define CHIPSET_G72 0x01D0 +#define CHIPSET_G73 0x0390 + +// integrated GeForces (6100, 6150) +#define CHIPSET_C51 0x0240 + +// variant of C51, seems based on a G70 design +#define CHIPSET_C512 0x03D0 +#define CHIPSET_G73_BRIDGED 0x02E0 + +#endif /* !__LIBSAIO_NVIDIA_H */ Index: branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c =================================================================== --- branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c (revision 0) +++ branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c (revision 1568) @@ -0,0 +1,45 @@ +/* + * NVIDIAGraphicsEnabler Module + * Enables many nVidia cards to be used out of the box in OS X. + * This was converted from boot2 code to a boot2 module. + * + */ + +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "nvidia.h" +#include "modules.h" + +#define kGraphicsEnablerKey "GraphicsEnabler" + +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4); + + +void NVIDIAGraphicsEnabler_start() +{ + register_hook_callback("PCIDevice", &GraphicsEnabler_hook); +} + + +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4) +{ + pci_dt_t* current = arg1; + + if (current->class_id != PCI_CLASS_DISPLAY_VGA) return; + + char *devicepath = get_pci_dev_path(current); + + bool do_gfx_devprop = true; + getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->chameleonConfig); + + if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_NVIDIA)) + { + verbose("NVIDIA VGA Controller [%04x:%04x] :: %s \n", + current->vendor_id, current->device_id, devicepath); + setup_nvidia_devprop(current); + } + else + verbose("[%04x:%04x] :: %s, is not a NVIDIA VGA Controller.\n", + current->vendor_id, current->device_id, devicepath); +} Index: branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Cconfig =================================================================== --- branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Cconfig (revision 0) +++ branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Cconfig (revision 1568) @@ -0,0 +1,10 @@ +# +# Chameleon Modules +# + +config NVIDIAGRAPHICSENABLER_MODULE + tristate "NVIDIAGraphicsEnabler Module" + default m + ---help--- + Say Y here if you want to enable the use of this module. + Index: branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Readme.txt =================================================================== --- branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Readme.txt (revision 0) +++ branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Readme.txt (revision 1568) @@ -0,0 +1,23 @@ +Module: GraphicsEnabler + +Description: the GraphicsEnabler nVidia code ported to a module. + If your card is supported and you find it missing + on this code, please file an issue at: + http://forge.voodooprojects.org/p/chameleon/issues/ + Only cards known to work will be added. + +Dependencies: none + +Keys: GraphicsEnabler Yes/No (enabled by default) + Disable GraphicsEnabler patch. + + UseNvidiaROM Yes/No (disabled by default) + Enable the use of a custom VBIOS ROM image. + + VBIOS Yes/No (disabled by default) + Adds "vbios" property to ioreg. ??? Azi: confirm + + +Adaptation of Meklort's work. + +TODO: review "nv_chipsets_t NVKnownChipsets" \ No newline at end of file Index: branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/nvidia.c =================================================================== --- branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/nvidia.c (revision 0) +++ branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/nvidia.c (revision 1568) @@ -0,0 +1,1508 @@ +/* + * NVidia injector + * + * Copyright (C) 2009 Jasmin Fazlic, iNDi + * + * NVidia injector is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * NVidia driver and injector is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with NVidia injector. If not, see . + */ +/* + * Alternatively you can choose to comply with APSL + */ + + +/* + * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license: + * + * + * Copyright 2005-2006 Erik Waling + * Copyright 2006 Stephane Marchesin + * Copyright 2007-2009 Stuart Bennett + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +//#include "boot.h" +#include "libsa.h" +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "device_inject.h" +#include "nvidia.h" + +#ifndef DEBUG_NVIDIA +#define DEBUG_NVIDIA 0 +#endif + +#if DEBUG_NVIDIA +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +#define kUseNvidiaROM "UseNvidiaROM" +#define kVBIOS "VBIOS" +#define kDcfg0 "display_0" +#define kDcfg1 "display_1" + +#define NVIDIA_ROM_SIZE 0x10000 +#define PATCH_ROM_SUCCESS 1 +#define PATCH_ROM_SUCCESS_HAS_LVDS 2 +#define PATCH_ROM_FAILED 0 +#define MAX_NUM_DCB_ENTRIES 16 +#define TYPE_GROUPED 0xff + +extern uint32_t devices_number; + +const char *nvidia_compatible_0[] = { "@0,compatible", "NVDA,NVMac" }; +const char *nvidia_compatible_1[] = { "@1,compatible", "NVDA,NVMac" }; +const char *nvidia_device_type_0[] = { "@0,device_type", "display" }; +const char *nvidia_device_type_1[] = { "@1,device_type", "display" }; +const char *nvidia_device_type[] = { "device_type", "NVDA,Parent" }; +const char *nvidia_name_0[] = { "@0,name", "NVDA,Display-A" }; +const char *nvidia_name_1[] = { "@1,name", "NVDA,Display-B" }; +const char *nvidia_slot_name[] = { "AAPL,slot-name", "Slot-1" }; + +static uint8_t default_NVCAP[]= { + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x00 +}; + +#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) ) + +static uint8_t default_dcfg_0[] = {0xff, 0xff, 0xff, 0xff}; +static uint8_t default_dcfg_1[] = {0xff, 0xff, 0xff, 0xff}; + +#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) ) +#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) ) + +static struct nv_chipsets_t NVKnownChipsets[] = { + { 0x00000000, "Unknown" }, +// temporary placement + { 0x10DE0DF4, "GeForce GT 450M" }, //Azi + issue #99 + { 0x10DE1251, "GeForce GTX 560M" }, // Asus G74SX +//======================================== + // 0040 - 004F + { 0x10DE0040, "GeForce 6800 Ultra" }, + { 0x10DE0041, "GeForce 6800" }, + { 0x10DE0042, "GeForce 6800 LE" }, + { 0x10DE0043, "GeForce 6800 XE" }, + { 0x10DE0044, "GeForce 6800 XT" }, + { 0x10DE0045, "GeForce 6800 GT" }, + { 0x10DE0046, "GeForce 6800 GT" }, + { 0x10DE0047, "GeForce 6800 GS" }, + { 0x10DE0048, "GeForce 6800 XT" }, + { 0x10DE004D, "Quadro FX 3400" }, + { 0x10DE004E, "Quadro FX 4000" }, + // 0050 - 005F + // 0060 - 006F + // 0070 - 007F + // 0080 - 008F + // 0090 - 009F + { 0x10DE0090, "GeForce 7800 GTX" }, + { 0x10DE0091, "GeForce 7800 GTX" }, + { 0x10DE0092, "GeForce 7800 GT" }, + { 0x10DE0093, "GeForce 7800 GS" }, + { 0x10DE0095, "GeForce 7800 SLI" }, + { 0x10DE0098, "GeForce Go 7800" }, + { 0x10DE0099, "GeForce Go 7800 GTX" }, + { 0x10DE009D, "Quadro FX 4500" }, + // 00A0 - 00AF + // 00B0 - 00BF + // 00C0 - 00CF + { 0x10DE00C0, "GeForce 6800 GS" }, + { 0x10DE00C1, "GeForce 6800" }, + { 0x10DE00C2, "GeForce 6800 LE" }, + { 0x10DE00C3, "GeForce 6800 XT" }, + { 0x10DE00C8, "GeForce Go 6800" }, + { 0x10DE00C9, "GeForce Go 6800 Ultra" }, + { 0x10DE00CC, "Quadro FX Go1400" }, + { 0x10DE00CD, "Quadro FX 3450/4000 SDI" }, + { 0x10DE00CE, "Quadro FX 1400" }, + // 00D0 - 00DF + // 00E0 - 00EF + // 00F0 - 00FF + { 0x10DE00F1, "GeForce 6600 GT" }, + { 0x10DE00F2, "GeForce 6600" }, + { 0x10DE00F3, "GeForce 6200" }, + { 0x10DE00F4, "GeForce 6600 LE" }, + { 0x10DE00F5, "GeForce 7800 GS" }, + { 0x10DE00F6, "GeForce 6800 GS/XT" }, + { 0x10DE00F8, "Quadro FX 3400/4400" }, + { 0x10DE00F9, "GeForce 6800 Series GPU" }, + // 0100 - 010F + // 0110 - 011F + // 0120 - 012F + // 0130 - 013F + // 0140 - 014F + { 0x10DE0140, "GeForce 6600 GT" }, + { 0x10DE0141, "GeForce 6600" }, + { 0x10DE0142, "GeForce 6600 LE" }, + { 0x10DE0143, "GeForce 6600 VE" }, + { 0x10DE0144, "GeForce Go 6600" }, + { 0x10DE0145, "GeForce 6610 XL" }, + { 0x10DE0146, "GeForce Go 6600 TE/6200 TE" }, + { 0x10DE0147, "GeForce 6700 XL" }, + { 0x10DE0148, "GeForce Go 6600" }, + { 0x10DE0149, "GeForce Go 6600 GT" }, + { 0x10DE014A, "Quadro NVS 440" }, + { 0x10DE014C, "Quadro FX 550" }, + { 0x10DE014D, "Quadro FX 550" }, + { 0x10DE014E, "Quadro FX 540" }, + { 0x10DE014F, "GeForce 6200" }, + // 0150 - 015F + // 0160 - 016F + { 0x10DE0160, "GeForce 6500" }, + { 0x10DE0161, "GeForce 6200 TurboCache(TM)" }, + { 0x10DE0162, "GeForce 6200SE TurboCache(TM)" }, + { 0x10DE0163, "GeForce 6200 LE" }, + { 0x10DE0164, "GeForce Go 6200" }, + { 0x10DE0165, "Quadro NVS 285" }, + { 0x10DE0166, "GeForce Go 6400" }, + { 0x10DE0167, "GeForce Go 6200" }, + { 0x10DE0168, "GeForce Go 6400" }, + { 0x10DE0169, "GeForce 6250" }, + { 0x10DE016A, "GeForce 7100 GS" }, + // 0170 - 017F + // 0180 - 018F + // 0190 - 019F + { 0x10DE0191, "GeForce 8800 GTX" }, + { 0x10DE0193, "GeForce 8800 GTS" }, + { 0x10DE0194, "GeForce 8800 Ultra" }, + { 0x10DE0197, "Tesla C870" }, + { 0x10DE019D, "Quadro FX 5600" }, + { 0x10DE019E, "Quadro FX 4600" }, + // 01A0 - 01AF + // 01B0 - 01BF + // 01C0 - 01CF + // 01D0 - 01DF + { 0x10DE01D0, "GeForce 7350 LE" }, + { 0x10DE01D1, "GeForce 7300 LE" }, + { 0x10DE01D2, "GeForce 7550 LE" }, + { 0x10DE01D3, "GeForce 7300 SE/7200 GS" }, + { 0x10DE01D6, "GeForce Go 7200" }, + { 0x10DE01D7, "GeForce Go 7300" }, + { 0x10DE01D8, "GeForce Go 7400" }, + { 0x10DE01D9, "GeForce Go 7400 GS" }, + { 0x10DE01DA, "Quadro NVS 110M" }, + { 0x10DE01DB, "Quadro NVS 120M" }, + { 0x10DE01DC, "Quadro FX 350M" }, + { 0x10DE01DD, "GeForce 7500 LE" }, + { 0x10DE01DE, "Quadro FX 350" }, + { 0x10DE01DF, "GeForce 7300 GS" }, + // 01E0 - 01EF + // 01F0 - 01FF + // 0200 - 020F + // 0210 - 021F + { 0x10DE0211, "GeForce 6800" }, + { 0x10DE0212, "GeForce 6800 LE" }, + { 0x10DE0215, "GeForce 6800 GT" }, + { 0x10DE0218, "GeForce 6800 XT" }, + // 0220 - 022F + { 0x10DE0221, "GeForce 6200" }, + { 0x10DE0222, "GeForce 6200 A-LE" }, + // 0230 - 023F + // 0240 - 024F + { 0x10DE0240, "GeForce 6150" }, + { 0x10DE0241, "GeForce 6150 LE" }, + { 0x10DE0242, "GeForce 6100" }, + { 0x10DE0244, "GeForce Go 6150" }, + { 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" }, + { 0x10DE0247, "GeForce Go 6100" }, + // 0250 - 025F + // 0260 - 026F + // 0270 - 027F + // 0280 - 028F + // 0290 - 029F + { 0x10DE0290, "GeForce 7900 GTX" }, + { 0x10DE0291, "GeForce 7900 GT/GTO" }, + { 0x10DE0292, "GeForce 7900 GS" }, + { 0x10DE0293, "GeForce 7950 GX2" }, + { 0x10DE0294, "GeForce 7950 GX2" }, + { 0x10DE0295, "GeForce 7950 GT" }, + { 0x10DE0298, "GeForce Go 7900 GS" }, + { 0x10DE0299, "GeForce Go 7900 GTX" }, + { 0x10DE029A, "Quadro FX 2500M" }, + { 0x10DE029B, "Quadro FX 1500M" }, + { 0x10DE029C, "Quadro FX 5500" }, + { 0x10DE029D, "Quadro FX 3500" }, + { 0x10DE029E, "Quadro FX 1500" }, + { 0x10DE029F, "Quadro FX 4500 X2" }, + // 02A0 - 02AF + // 02B0 - 02BF + // 02C0 - 02CF + // 02D0 - 02DF + // 02E0 - 02EF + { 0x10DE02E0, "GeForce 7600 GT" }, + { 0x10DE02E1, "GeForce 7600 GS" }, + { 0x10DE02E2, "GeForce 7300 GT" }, + { 0x10DE02E3, "GeForce 7900 GS" }, + { 0x10DE02E4, "GeForce 7950 GT" }, + // 02F0 - 02FF + // 0300 - 030F + { 0x10DE0301, "GeForce FX 5800 Ultra" }, + { 0x10DE0302, "GeForce FX 5800" }, + { 0x10DE0308, "Quadro FX 2000" }, + { 0x10DE0309, "Quadro FX 1000" }, + // 0310 - 031F + { 0x10DE0311, "GeForce FX 5600 Ultra" }, + { 0x10DE0312, "GeForce FX 5600" }, + { 0x10DE0314, "GeForce FX 5600XT" }, + { 0x10DE031A, "GeForce FX Go5600" }, + { 0x10DE031B, "GeForce FX Go5650" }, + { 0x10DE031C, "Quadro FX Go700" }, + // 0320 - 032F + { 0x10DE0324, "GeForce FX Go5200" }, + { 0x10DE0325, "GeForce FX Go5250" }, + { 0x10DE0326, "GeForce FX 5500" }, + { 0x10DE0328, "GeForce FX Go5200 32M/64M" }, + { 0x10DE032A, "Quadro NVS 55/280 PCI" }, + { 0x10DE032B, "Quadro FX 500/600 PCI" }, + { 0x10DE032C, "GeForce FX Go53xx Series" }, + { 0x10DE032D, "GeForce FX Go5100" }, + // 0330 - 033F + { 0x10DE0330, "GeForce FX 5900 Ultra" }, + { 0x10DE0331, "GeForce FX 5900" }, + { 0x10DE0332, "GeForce FX 5900XT" }, + { 0x10DE0333, "GeForce FX 5950 Ultra" }, + { 0x10DE0334, "GeForce FX 5900ZT" }, + { 0x10DE0338, "Quadro FX 3000" }, + { 0x10DE033F, "Quadro FX 700" }, + // 0340 - 034F + { 0x10DE0341, "GeForce FX 5700 Ultra" }, + { 0x10DE0342, "GeForce FX 5700" }, + { 0x10DE0343, "GeForce FX 5700LE" }, + { 0x10DE0344, "GeForce FX 5700VE" }, + { 0x10DE0347, "GeForce FX Go5700" }, + { 0x10DE0348, "GeForce FX Go5700" }, + { 0x10DE034C, "Quadro FX Go1000" }, + { 0x10DE034E, "Quadro FX 1100" }, + // 0350 - 035F + // 0360 - 036F + // 0370 - 037F + // 0380 - 038F + { 0x10DE038B, "GeForce 7650 GS" }, + // 0390 - 039F + { 0x10DE0390, "GeForce 7650 GS" }, + { 0x10DE0391, "GeForce 7600 GT" }, + { 0x10DE0392, "GeForce 7600 GS" }, + { 0x10DE0393, "GeForce 7300 GT" }, + { 0x10DE0394, "GeForce 7600 LE" }, + { 0x10DE0395, "GeForce 7300 GT" }, + { 0x10DE0397, "GeForce Go 7700" }, + { 0x10DE0398, "GeForce Go 7600" }, + { 0x10DE0399, "GeForce Go 7600 GT"}, + { 0x10DE039A, "Quadro NVS 300M" }, + { 0x10DE039B, "GeForce Go 7900 SE" }, + { 0x10DE039C, "Quadro FX 550M" }, + { 0x10DE039E, "Quadro FX 560" }, + // 03A0 - 03AF + // 03B0 - 03BF + // 03C0 - 03CF + // 03D0 - 03DF + { 0x10DE03D0, "GeForce 6150SE nForce 430" }, + { 0x10DE03D1, "GeForce 6100 nForce 405" }, + { 0x10DE03D2, "GeForce 6100 nForce 400" }, + { 0x10DE03D5, "GeForce 6100 nForce 420" }, + { 0x10DE03D6, "GeForce 7025 / nForce 630a" }, + // 03E0 - 03EF + // 03F0 - 03FF + // 0400 - 040F + { 0x10DE0400, "GeForce 8600 GTS" }, + { 0x10DE0401, "GeForce 8600 GT" }, + { 0x10DE0402, "GeForce 8600 GT" }, + { 0x10DE0403, "GeForce 8600 GS" }, + { 0x10DE0404, "GeForce 8400 GS" }, + { 0x10DE0405, "GeForce 9500M GS" }, + { 0x10DE0406, "GeForce 8300 GS" }, + { 0x10DE0407, "GeForce 8600M GT" }, + { 0x10DE0408, "GeForce 9650M GS" }, + { 0x10DE0409, "GeForce 8700M GT" }, + { 0x10DE040A, "Quadro FX 370" }, + { 0x10DE040B, "Quadro NVS 320M" }, + { 0x10DE040C, "Quadro FX 570M" }, + { 0x10DE040D, "Quadro FX 1600M" }, + { 0x10DE040E, "Quadro FX 570" }, + { 0x10DE040F, "Quadro FX 1700" }, + // 0410 - 041F + { 0x10DE0410, "GeForce GT 330" }, + // 0420 - 042F + { 0x10DE0420, "GeForce 8400 SE" }, + { 0x10DE0421, "GeForce 8500 GT" }, + { 0x10DE0422, "GeForce 8400 GS" }, + { 0x10DE0423, "GeForce 8300 GS" }, + { 0x10DE0424, "GeForce 8400 GS" }, + { 0x10DE0425, "GeForce 8600M GS" }, + { 0x10DE0426, "GeForce 8400M GT" }, + { 0x10DE0427, "GeForce 8400M GS" }, + { 0x10DE0428, "GeForce 8400M G" }, + { 0x10DE0429, "Quadro NVS 140M" }, + { 0x10DE042A, "Quadro NVS 130M" }, + { 0x10DE042B, "Quadro NVS 135M" }, + { 0x10DE042C, "GeForce 9400 GT" }, + { 0x10DE042D, "Quadro FX 360M" }, + { 0x10DE042E, "GeForce 9300M G" }, + { 0x10DE042F, "Quadro NVS 290" }, + // 0430 - 043F + // 0440 - 044F + // 0450 - 045F + // 0460 - 046F + // 0470 - 047F + // 0480 - 048F + // 0490 - 049F + // 04A0 - 04AF + // 04B0 - 04BF + // 04C0 - 04CF + // 04D0 - 04DF + // 04E0 - 04EF + // 04F0 - 04FF + // 0500 - 050F + // 0510 - 051F + // 0520 - 052F + // 0530 - 053F + { 0x10DE053A, "GeForce 7050 PV / nForce 630a" }, + { 0x10DE053B, "GeForce 7050 PV / nForce 630a" }, + { 0x10DE053E, "GeForce 7025 / nForce 630a" }, + // 0540 - 054F + // 0550 - 055F + // 0560 - 056F + // 0570 - 057F + // 0580 - 058F + // 0590 - 059F + // 05A0 - 05AF + // 05B0 - 05BF + // 05C0 - 05CF + // 05D0 - 05DF + // 05E0 - 05EF + { 0x10DE05E0, "GeForce GTX 295" }, + { 0x10DE05E1, "GeForce GTX 280" }, + { 0x10DE05E2, "GeForce GTX 260" }, + { 0x10DE05E3, "GeForce GTX 285" }, + { 0x10DE05E6, "GeForce GTX 275" }, + { 0x10DE05EA, "GeForce GTX 260" }, + { 0x10DE05EB, "GeForce GTX 295" }, + { 0x10DE05ED, "Quadroplex 2200 D2" }, + // 05F0 - 05FF + { 0x10DE05F8, "Quadroplex 2200 S4" }, + { 0x10DE05F9, "Quadro CX" }, + { 0x10DE05FD, "Quadro FX 5800" }, + { 0x10DE05FE, "Quadro FX 4800" }, + { 0x10DE05FF, "Quadro FX 3800" }, + // 0600 - 060F + { 0x10DE0600, "GeForce 8800 GTS 512" }, + { 0x10DE0601, "GeForce 9800 GT" }, + { 0x10DE0602, "GeForce 8800 GT" }, + { 0x10DE0603, "GeForce GT 230" }, + { 0x10DE0604, "GeForce 9800 GX2" }, + { 0x10DE0605, "GeForce 9800 GT" }, + { 0x10DE0606, "GeForce 8800 GS" }, + { 0x10DE0607, "GeForce GTS 240" }, + { 0x10DE0608, "GeForce 9800M GTX" }, + { 0x10DE0609, "GeForce 8800M GTS" }, + { 0x10DE060A, "GeForce GTX 280M" }, + { 0x10DE060B, "GeForce 9800M GT" }, + { 0x10DE060C, "GeForce 8800M GTX" }, + { 0x10DE060D, "GeForce 8800 GS" }, + { 0x10DE060F, "GeForce GTX 285M" }, + // 0610 - 061F + { 0x10DE0610, "GeForce 9600 GSO" }, + { 0x10DE0611, "GeForce 8800 GT" }, + { 0x10DE0612, "GeForce 9800 GTX" }, + { 0x10DE0613, "GeForce 9800 GTX+" }, + { 0x10DE0614, "GeForce 9800 GT" }, + { 0x10DE0615, "GeForce GTS 250" }, + { 0x10DE0617, "GeForce 9800M GTX" }, + { 0x10DE0618, "GeForce GTX 260M" }, + { 0x10DE0619, "Quadro FX 4700 X2" }, + { 0x10DE061A, "Quadro FX 3700" }, + { 0x10DE061B, "Quadro VX 200" }, + { 0x10DE061C, "Quadro FX 3600M" }, + { 0x10DE061D, "Quadro FX 2800M" }, + { 0x10DE061F, "Quadro FX 3800M" }, + // 0620 - 062F + { 0x10DE0622, "GeForce 9600 GT" }, + { 0x10DE0623, "GeForce 9600 GS" }, + { 0x10DE0625, "GeForce 9600 GSO 512"}, + { 0x10DE0626, "GeForce GT 130" }, + { 0x10DE0627, "GeForce GT 140" }, + { 0x10DE0628, "GeForce 9800M GTS" }, + { 0x10DE062A, "GeForce 9700M GTS" }, + { 0x10DE062C, "GeForce 9800M GTS" }, + { 0x10DE062D, "GeForce 9600 GT" }, + { 0x10DE062E, "GeForce 9600 GT" }, + // 0630 - 063F + { 0x10DE0631, "GeForce GTS 160M" }, + { 0x10DE0632, "GeForce GTS 150M" }, + { 0x10DE0635, "GeForce 9600 GSO" }, + { 0x10DE0637, "GeForce 9600 GT" }, + { 0x10DE0638, "Quadro FX 1800" }, + { 0x10DE063A, "Quadro FX 2700M" }, + // 0640 - 064F + { 0x10DE0640, "GeForce 9500 GT" }, + { 0x10DE0641, "GeForce 9400 GT" }, + { 0x10DE0642, "GeForce 8400 GS" }, + { 0x10DE0643, "GeForce 9500 GT" }, + { 0x10DE0644, "GeForce 9500 GS" }, + { 0x10DE0645, "GeForce 9500 GS" }, + { 0x10DE0646, "GeForce GT 120" }, + { 0x10DE0647, "GeForce 9600M GT" }, + { 0x10DE0648, "GeForce 9600M GS" }, + { 0x10DE0649, "GeForce 9600M GT" }, + { 0x10DE064A, "GeForce 9700M GT" }, + { 0x10DE064B, "GeForce 9500M G" }, + { 0x10DE064C, "GeForce 9650M GT" }, + // 0650 - 065F + { 0x10DE0651, "GeForce G 110M" }, + { 0x10DE0652, "GeForce GT 130M" }, + { 0x10DE0653, "GeForce GT 120M" }, + { 0x10DE0654, "GeForce GT 220M" }, + { 0x10DE0656, "GeForce 9650 S" }, + { 0x10DE0658, "Quadro FX 380" }, + { 0x10DE0659, "Quadro FX 580" }, + { 0x10DE065A, "Quadro FX 1700M" }, + { 0x10DE065B, "GeForce 9400 GT" }, + { 0x10DE065C, "Quadro FX 770M" }, + { 0x10DE065F, "GeForce G210" }, + // 0660 - 066F + // 0670 - 067F + // 0680 - 068F + // 0690 - 069F + // 06A0 - 06AF + // 06B0 - 06BF + // 06C0 - 06CF + { 0x10DE06C0, "GeForce GTX 480" }, + { 0x10DE06C3, "GeForce GTX D12U" }, + { 0x10DE06C4, "GeForce GTX 465" }, + { 0x10DE06CA, "GeForce GTX 480M" }, + { 0x10DE06CD, "GeForce GTX 470" }, + // 06D0 - 06DF + { 0x10DE06D1, "Tesla C2050" }, // TODO: sub-device id: 0x0771 + { 0x10DE06D1, "Tesla C2070" }, // TODO: sub-device id: 0x0772 + { 0x10DE06D2, "Tesla M2070" }, + { 0x10DE06D8, "Quadro 6000" }, + { 0x10DE06D9, "Quadro 5000" }, + { 0x10DE06DA, "Quadro 5000M" }, + { 0x10DE06DC, "Quadro 6000" }, + { 0x10DE06DD, "Quadro 4000" }, + { 0x10DE06DE, "Tesla M2050" }, // TODO: sub-device id: 0x0846 + { 0x10DE06DE, "Tesla M2070" }, // TODO: sub-device id: ? + { 0x10DE06DF, "Tesla M2070-Q" }, + // 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070 + // 06E0 - 06EF + { 0x10DE06E0, "GeForce 9300 GE" }, + { 0x10DE06E1, "GeForce 9300 GS" }, + { 0x10DE06E2, "GeForce 8400" }, + { 0x10DE06E3, "GeForce 8400 SE" }, + { 0x10DE06E4, "GeForce 8400 GS" }, + { 0x10DE06E5, "GeForce 9300M GS" }, + { 0x10DE06E6, "GeForce G100" }, + { 0x10DE06E7, "GeForce 9300 SE" }, + { 0x10DE06E8, "GeForce 9200M GS" }, + { 0x10DE06E9, "GeForce 9300M GS" }, + { 0x10DE06EA, "Quadro NVS 150M" }, + { 0x10DE06EB, "Quadro NVS 160M" }, + { 0x10DE06EC, "GeForce G 105M" }, + { 0x10DE06EF, "GeForce G 103M" }, + // 06F0 - 06FF + { 0x10DE06F8, "Quadro NVS 420" }, + { 0x10DE06F9, "Quadro FX 370 LP" }, + { 0x10DE06FA, "Quadro NVS 450" }, + { 0x10DE06FB, "Quadro FX 370M" }, + { 0x10DE06FD, "Quadro NVS 295" }, + // 0700 - 070F + // 0710 - 071F + // 0720 - 072F + // 0730 - 073F + // 0740 - 074F + // 0750 - 075F + // 0760 - 076F + // 0770 - 077F + // 0780 - 078F + // 0790 - 079F + // 07A0 - 07AF + // 07B0 - 07BF + // 07C0 - 07CF + // 07D0 - 07DF + // 07E0 - 07EF + { 0x10DE07E0, "GeForce 7150 / nForce 630i" }, + { 0x10DE07E1, "GeForce 7100 / nForce 630i" }, + { 0x10DE07E2, "GeForce 7050 / nForce 630i" }, + { 0x10DE07E3, "GeForce 7050 / nForce 610i" }, + { 0x10DE07E5, "GeForce 7050 / nForce 620i" }, + // 07F0 - 07FF + // 0800 - 080F + // 0810 - 081F + // 0820 - 082F + // 0830 - 083F + // 0840 - 084F + { 0x10DE0844, "GeForce 9100M G" }, + { 0x10DE0845, "GeForce 8200M G" }, + { 0x10DE0846, "GeForce 9200" }, + { 0x10DE0847, "GeForce 9100" }, + { 0x10DE0848, "GeForce 8300" }, + { 0x10DE0849, "GeForce 8200" }, + { 0x10DE084A, "nForce 730a" }, + { 0x10DE084B, "GeForce 9200" }, + { 0x10DE084C, "nForce 980a/780a SLI" }, + { 0x10DE084D, "nForce 750a SLI" }, + { 0x10DE084F, "GeForce 8100 / nForce 720a" }, + // 0850 - 085F + // 0860 - 086F + { 0x10DE0860, "GeForce 9400" }, + { 0x10DE0861, "GeForce 9400" }, + { 0x10DE0862, "GeForce 9400M G" }, + { 0x10DE0863, "GeForce 9400M" }, + { 0x10DE0864, "GeForce 9300" }, + { 0x10DE0865, "ION" }, + { 0x10DE0866, "GeForce 9400M G" }, + { 0x10DE0867, "GeForce 9400" }, + { 0x10DE0868, "nForce 760i SLI" }, + { 0x10DE086A, "GeForce 9400" }, + { 0x10DE086C, "GeForce 9300 / nForce 730i" }, + { 0x10DE086D, "GeForce 9200" }, + { 0x10DE086E, "GeForce 9100M G" }, + { 0x10DE086F, "GeForce 8200M G" }, + // 0870 - 087F + { 0x10DE0870, "GeForce 9400M" }, + { 0x10DE0871, "GeForce 9200" }, + { 0x10DE0872, "GeForce G102M" }, + { 0x10DE0873, "GeForce G102M" }, + { 0x10DE0874, "ION 9300M" }, + { 0x10DE0876, "ION" }, + { 0x10DE087A, "GeForce 9400" }, + { 0x10DE087D, "ION 9400M" }, + { 0x10DE087E, "ION LE" }, + { 0x10DE087F, "ION LE" }, + // 0880 - 088F + // 0890 - 089F + // 08A0 - 08AF + // 08B0 - 08BF + // 08C0 - 08CF + // 08D0 - 08DF + // 08E0 - 08EF + // 08F0 - 08FF + // 0900 - 090F + // 0910 - 091F + // 0920 - 092F + // 0930 - 093F + // 0940 - 094F + // 0950 - 095F + // 0960 - 096F + // 0970 - 097F + // 0980 - 098F + // 0990 - 099F + // 09A0 - 09AF + // 09B0 - 09BF + // 09C0 - 09CF + // 09D0 - 09DF + // 09E0 - 09EF + // 09F0 - 09FF + // 0A00 - 0A0F + // 0A10 - 0A1F + // 0A20 - 0A2F + { 0x10DE0A20, "GeForce GT220" }, + { 0x10DE0A22, "GeForce 315" }, + { 0x10DE0A23, "GeForce 210" }, + { 0x10DE0A28, "GeForce GT 230M" }, + { 0x10DE0A29, "GeForce GT 330M" }, + { 0x10DE0A2A, "GeForce GT 230M" }, + { 0x10DE0A2B, "GeForce GT 330M" }, + { 0x10DE0A2C, "NVS 5100M" }, + { 0x10DE0A2D, "GeForce GT 320M" }, + // 0A30 - 0A3F + { 0x10DE0A34, "GeForce GT 240M" }, + { 0x10DE0A35, "GeForce GT 325M" }, + { 0x10DE0A3C, "Quadro FX 880M" }, + // 0A40 - 0A4F + // 0A50 - 0A5F + // 0A60 - 0A6F + { 0x10DE0A60, "GeForce G210" }, + { 0x10DE0A62, "GeForce 205" }, + { 0x10DE0A63, "GeForce 310" }, + { 0x10DE0A64, "ION" }, + { 0x10DE0A65, "GeForce 210" }, + { 0x10DE0A66, "GeForce 310" }, + { 0x10DE0A67, "GeForce 315" }, + { 0x10DE0A68, "GeForce G105M" }, + { 0x10DE0A69, "GeForce G105M" }, + { 0x10DE0A6A, "NVS 2100M" }, + { 0x10DE0A6C, "NVS 3100M" }, + { 0x10DE0A6E, "GeForce 305M" }, + { 0x10DE0A6F, "ION" }, + // 0A70 - 0A7F + { 0x10DE0A70, "GeForce 310M" }, + { 0x10DE0A71, "GeForce 305M" }, + { 0x10DE0A72, "GeForce 310M" }, + { 0x10DE0A73, "GeForce 305M" }, + { 0x10DE0A74, "GeForce G210M" }, + { 0x10DE0A75, "GeForce G310M" }, + { 0x10DE0A78, "Quadro FX 380 LP" }, + { 0x10DE0A7C, "Quadro FX 380M" }, + // 0A80 - 0A8F + // 0A90 - 0A9F + // 0AA0 - 0AAF + // 0AB0 - 0ABF + // 0AC0 - 0ACF + // 0AD0 - 0ADF + // 0AE0 - 0AEF + // 0AF0 - 0AFF + // 0B00 - 0B0F + // 0B10 - 0B1F + // 0B20 - 0B2F + // 0B30 - 0B3F + // 0B40 - 0B4F + // 0B50 - 0B5F + // 0B60 - 0B6F + // 0B70 - 0B7F + // 0B80 - 0B8F + // 0B90 - 0B9F + // 0BA0 - 0BAF + // 0BB0 - 0BBF + // 0BC0 - 0BCF + // 0BD0 - 0BDF + // 0BE0 - 0BEF + // 0BF0 - 0BFF + // 0C00 - 0C0F + // 0C10 - 0C1F + // 0C20 - 0C2F + // 0C30 - 0C3F + // 0C40 - 0C4F + // 0C50 - 0C5F + // 0C60 - 0C6F + // 0C70 - 0C7F + // 0C80 - 0C8F + // 0C90 - 0C9F + // 0CA0 - 0CAF + { 0x10DE0CA0, "GeForce GT 330 " }, + { 0x10DE0CA2, "GeForce GT 320" }, + { 0x10DE0CA3, "GeForce GT 240" }, + { 0x10DE0CA4, "GeForce GT 340" }, + { 0x10DE0CA7, "GeForce GT 330" }, + { 0x10DE0CA8, "GeForce GTS 260M" }, + { 0x10DE0CA9, "GeForce GTS 250M" }, + { 0x10DE0CAC, "GeForce 315" }, + { 0x10DE0CAF, "GeForce GT 335M" }, + // 0CB0 - 0CBF + { 0x10DE0CB0, "GeForce GTS 350M" }, + { 0x10DE0CB1, "GeForce GTS 360M" }, + { 0x10DE0CBC, "Quadro FX 1800M" }, + // 0CC0 - 0CCF + // 0CD0 - 0CDF + // 0CE0 - 0CEF + // 0CF0 - 0CFF + // 0D00 - 0D0F + // 0D10 - 0D1F + // 0D20 - 0D2F + // 0D30 - 0D3F + // 0D40 - 0D4F + // 0D50 - 0D5F + // 0D60 - 0D6F + // 0D70 - 0D7F + // 0D80 - 0D8F + // 0D90 - 0D9F + // 0DA0 - 0DAF + // 0DB0 - 0DBF + // 0DC0 - 0DCF + { 0x10DE0DC0, "GeForce GT 440" }, + { 0x10DE0DC1, "D12-P1-35" }, + { 0x10DE0DC2, "D12-P1-35" }, + { 0x10DE0DC4, "GeForce GTS 450" }, + { 0x10DE0DC5, "GeForce GTS 450" }, + { 0x10DE0DC6, "GeForce GTS 450" }, + { 0x10DE0DCA, "GF10x" }, + // 0DD0 - 0DDF + { 0x10DE0DCD, "GeForce GT 555M" }, + { 0x10DE0DCE, "GeForce GT 555M" }, + { 0x10DE0DD1, "GeForce GTX 460M" }, + { 0x10DE0DD2, "GeForce GT 445M" }, + { 0x10DE0DD3, "GeForce GT 435M" }, + { 0x10DE0DD6, "GeForce GT 550M" }, + { 0x10DE0DD8, "Quadro 2000" }, + { 0x10DE0DDA, "Quadro 2000M" }, + { 0x10DE0DDE, "GF106-ES" }, + { 0x10DE0DDF, "GF106-INT" }, + // 0DE0 - 0DEF + { 0x10DE0DE0, "GeForce GT 440" }, + { 0x10DE0DE1, "GeForce GT 430" }, + { 0x10DE0DE2, "GeForce GT 420" }, + { 0x10DE0DE5, "GeForce GT 530" }, + { 0x10DE0DEB, "GeForce GT 555M" }, + { 0x10DE0DEC, "GeForce GT 525M" }, + { 0x10DE0DED, "GeForce GT 520M" }, + { 0x10DE0DEE, "GeForce GT 415M" }, + // 0DF0 - 0DFF + { 0x10DE0DF0, "GeForce GT 425M" }, + { 0x10DE0DF1, "GeForce GT 420M" }, + { 0x10DE0DF2, "GeForce GT 435M" }, + { 0x10DE0DF3, "GeForce GT 420M" }, + { 0x10DE0DF4, "GeForce GT 540M" }, + { 0x10DE0DF5, "GeForce GT 525M" }, + { 0x10DE0DF6, "GeForce GT 550M" }, + { 0x10DE0DF7, "GeForce GT 520M" }, + { 0x10DE0DF8, "Quadro 600" }, + { 0x10DE0DFA, "Quadro 1000M" }, + { 0x10DE0DFE, "GF108 ES" }, + { 0x10DE0DFF, "GF108 INT" }, + // 0E00 - 0E0F + // 0E10 - 0E1F + // 0E20 - 0E2F + { 0x10DE0E21, "D12U-25" }, + { 0x10DE0E22, "GeForce GTX 460" }, + { 0x10DE0E23, "GeForce GTX 460 SE" }, + { 0x10DE0E24, "GeForce GTX 460" }, + { 0x10DE0E25, "D12U-50" }, + // 0E30 - 0E3F + { 0x10DE0E30, "GeForce GTX 470M" }, + { 0x10DE0E31, "GeForce GTX 485M" }, + { 0x10DE0E38, "GF104GL" }, + { 0x10DE0E3A, "Quadro 3000M" }, + { 0x10DE0E3B, "Quadro 4000M" }, + { 0x10DE0E3E, "GF104-ES" }, + { 0x10DE0E3F, "GF104-INT" }, + // 0E40 - 0E4F + // 0E50 - 0E5F + // 0E60 - 0E6F + // 0E70 - 0E7F + // 0E80 - 0E8F + // 0E90 - 0E9F + // 0EA0 - 0EAF + // 0EB0 - 0EBF + // 0EC0 - 0ECF + // 0ED0 - 0EDF + // 0EE0 - 0EEF + // 0EF0 - 0EFF + // 0F00 - 0F0F + // 0F10 - 0F1F + // 0F20 - 0F2F + // 0F30 - 0F3F + // 0F40 - 0F4F + // 0F50 - 0F5F + // 0F60 - 0F6F + // 0F70 - 0F7F + // 0F80 - 0F8F + // 0F90 - 0F9F + // 0FA0 - 0FAF + // 0FB0 - 0FBF + // 0FC0 - 0FCF + // 0FD0 - 0FDF + // 0FE0 - 0FEF + // 0FF0 - 0FFF + // 1000 - 100F + // 1010 - 101F + // 1020 - 102F + // 1030 - 103F + // 1040 - 104F + { 0x10DE1040, "GeForce GT 520" }, + // 1050 - 105F + { 0x10DE1050, "GeForce GT 520M" }, + // 1060 - 106F + // 1070 - 107F + // 1080 - 108F + { 0x10DE1054, "GeForce GT 410M" }, + { 0x10DE1056, "NVS 4200M" }, + { 0x10DE1057, "NVS 4200M" }, + { 0x10DE107F, "NVIDIA GF119-ES" }, + { 0x10DE1080, "GeForce GTX 580" }, + { 0x10DE1081, "GeForce GTX 570" }, + { 0x10DE1082, "GeForce GTX 560 Ti" }, + { 0x10DE1083, "D13U" }, + { 0x10DE1086, "GeForce GTX 570" }, + { 0x10DE1088, "GeForce GTX 590" }, + // 1090 - 109F + { 0x10DE1098, "D13U" }, + { 0x10DE109A, "Quadro 5010M / N12E-Q5" }, + // 10A0 - 10AF + // 10B0 - 10BF + // 10C0 - 10CF + { 0x10DE10C3, "GeForce 8400 GS" }, + { 0x10DE10C5, "GeForce 405" }, + // 1200 - + { 0x10DE1200, "GeForce GTX 560 Ti" }, + { 0x10DE1201, "GeForce GTX 560" }, + { 0x10DE1244, "GeForce GTX 550 Ti" }, + { 0x10DE1245, "GeForce GTS 450" }, + { 0x10DE1251, "N12E-GS-A1" }, +}; + +static uint16_t swap16(uint16_t x) +{ + return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8)); +} + +static uint16_t read16(uint8_t *ptr, uint16_t offset) +{ + uint8_t ret[2]; + + ret[0] = ptr[offset+1]; + ret[1] = ptr[offset]; + + return *((uint16_t*)&ret); +} + +#if 0 +static uint32_t swap32(uint32_t x) +{ + return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24); +} + +static uint8_t read8(uint8_t *ptr, uint16_t offset) +{ + return ptr[offset]; +} + +static uint32_t read32(uint8_t *ptr, uint16_t offset) +{ + uint8_t ret[4]; + + ret[0] = ptr[offset+3]; + ret[1] = ptr[offset+2]; + ret[2] = ptr[offset+1]; + ret[3] = ptr[offset]; + + return *((uint32_t*)&ret); +} +#endif + +static int patch_nvidia_rom(uint8_t *rom) +{ + if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) { + printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]); + return PATCH_ROM_FAILED; + } + + uint16_t dcbptr = swap16(read16(rom, 0x36)); + + if (!dcbptr) { + printf("no dcb table found\n"); + return PATCH_ROM_FAILED; + } +// else +// printf("dcb table at offset 0x%04x\n", dcbptr); + + uint8_t *dcbtable = &rom[dcbptr]; + uint8_t dcbtable_version = dcbtable[0]; + uint8_t headerlength = 0; + uint8_t numentries = 0; + uint8_t recordlength = 0; + + if (dcbtable_version >= 0x20) + { + uint32_t sig; + + if (dcbtable_version >= 0x30) + { + headerlength = dcbtable[1]; + numentries = dcbtable[2]; + recordlength = dcbtable[3]; + + sig = *(uint32_t *)&dcbtable[6]; + } + else + { + sig = *(uint32_t *)&dcbtable[4]; + headerlength = 8; + } + + if (sig != 0x4edcbdcb) + { + printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48 + return PATCH_ROM_FAILED; + } + } + else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */ + { + char sig[8] = { 0 }; + + strncpy(sig, (char *)&dcbtable[-7], 7); + recordlength = 10; + + if (strcmp(sig, "DEV_REC")) + { + printf("Bad Display Configuration Block signature (%s)\n", sig); + return PATCH_ROM_FAILED; + } + } + else + { + printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version); + return PATCH_ROM_FAILED; + } + + if (numentries >= MAX_NUM_DCB_ENTRIES) + numentries = MAX_NUM_DCB_ENTRIES; + + uint8_t num_outputs = 0, i = 0; + + struct dcbentry + { + uint8_t type; + uint8_t index; + uint8_t *heads; + } entries[numentries]; + + for (i = 0; i < numentries; i++) + { + uint32_t connection; + connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i]; + + /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */ + if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ + continue; + if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ + continue; + if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */ + continue; + + entries[num_outputs].type = connection & 0xf; + entries[num_outputs].index = num_outputs; + entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]); + } + + int has_lvds = false; + uint8_t channel1 = 0, channel2 = 0; + + for (i = 0; i < num_outputs; i++) + { + if (entries[i].type == 3) + { + has_lvds = true; + //printf("found LVDS\n"); + channel1 |= ( 0x1 << entries[i].index); + entries[i].type = TYPE_GROUPED; + } + } + + // if we have a LVDS output, we group the rest to the second channel + if (has_lvds) + { + for (i = 0; i < num_outputs; i++) + { + if (entries[i].type == TYPE_GROUPED) + continue; + + channel2 |= ( 0x1 << entries[i].index); + entries[i].type = TYPE_GROUPED; + } + } + else + { + int x; + // we loop twice as we need to generate two channels + for (x = 0; x <= 1; x++) + { + for (i=0; i channel2) + { + uint8_t buff = channel1; + channel1 = channel2; + channel2 = buff; + } + + default_NVCAP[6] = channel1; + default_NVCAP[8] = channel2; + + // patching HEADS + for (i = 0; i < num_outputs; i++) + { + if (channel1 & (1 << i)) + { + *entries[i].heads = 1; + } + else if(channel2 & (1 << i)) + { + *entries[i].heads = 2; + } + } + return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS); +} + +static char *get_nvidia_model(uint32_t id) +{ + int i; + + for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) { + if (NVKnownChipsets[i].device == id) + { + return NVKnownChipsets[i].name; + } + } + return NVKnownChipsets[0].name; +} + +static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize) +{ + int fd; + int size; + + if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) + { + return 0; + } + + size = file_size(fd); + + if (size > bufsize) + { + printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", + filename, bufsize); + size = bufsize; + } + size = read(fd, (char *)buf, size); + close(fd); + + return size > 0 ? size : 0; +} + +static int devprop_add_nvidia_template(struct DevPropDevice *device) +{ + char tmp[16]; + + if (!device) + return 0; + + if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0)) + return 0; + if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0)) + return 0; + if (!DP_ADD_TEMP_VAL(device, nvidia_name_0)) + return 0; + if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1)) + return 0; + if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1)) + return 0; + if (!DP_ADD_TEMP_VAL(device, nvidia_name_1)) + return 0; + if (!DP_ADD_TEMP_VAL(device, nvidia_device_type)) + return 0; + + // Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0! + // len = sprintf(tmp, "Slot-%x", devices_number); + sprintf(tmp, "Slot-%x",devices_number); + devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp)); + devices_number++; + + return 1; +} + +int hex2bin(const char *hex, uint8_t *bin, int len) +{ + char *p; + int i; + char buf[3]; + + if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) { + printf("[ERROR] bin2hex input error\n"); + return -1; + } + + buf[2] = '\0'; + p = (char *) hex; + + for (i = 0; i < len; i++) + { + if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) { + printf("[ERROR] bin2hex '%s' syntax error\n", hex); + return -2; + } + buf[0] = *p++; + buf[1] = *p++; + bin[i] = (unsigned char) strtoul(buf, NULL, 16); + } + return 0; +} + +unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev) +{ + unsigned long long vram_size = 0; + + if (nvCardType < NV_ARCH_50) + { + vram_size = REG32(NV04_PFB_FIFO_DATA); + vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; + } + else if (nvCardType < NV_ARCH_C0) + { + vram_size = REG32(NV04_PFB_FIFO_DATA); + vram_size |= (vram_size & 0xff) << 32; + vram_size &= 0xffffffff00ll; + } + else // >= NV_ARCH_C0 + { + vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20; + vram_size *= REG32(NVC0_MEM_CTRLR_COUNT); + } + + // Workaround for GT 420/430 & 9600M GT + switch (nvda_dev->device_id) + { + case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430 + case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420 + case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT + default: break; + } + + return vram_size; +} + +bool setup_nvidia_devprop(pci_dt_t *nvda_dev) +{ + struct DevPropDevice *device; + char *devicepath; + option_rom_pci_header_t *rom_pci_header; + volatile uint8_t *regs; + uint8_t *rom; + uint8_t *nvRom; + uint8_t nvCardType; + unsigned long long videoRam; + uint32_t nvBiosOveride; + uint32_t bar[7]; + uint32_t boot_display; + int nvPatch; + int len; + char biosVersion[32]; + char nvFilename[32]; + char kNVCAP[12]; + char *model; + const char *value; + bool doit; + + devicepath = get_pci_dev_path(nvda_dev); + bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 ); + regs = (uint8_t *) (bar[0] & ~0x0f); + + // get card type + nvCardType = (REG32(0) >> 20) & 0x1ff; + + // Amount of VRAM in kilobytes + videoRam = mem_detect(regs, nvCardType, nvda_dev); + model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id); + + verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", + model, (uint32_t)(videoRam / 1024 / 1024), + (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id, + devicepath); + + rom = malloc(NVIDIA_ROM_SIZE); + sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, + (uint16_t)nvda_dev->device_id); + + if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit) + { + verbose("Looking for nvidia video bios file %s\n", nvFilename); + nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE); + + if (nvBiosOveride > 0) + { + verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride); + DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride); + } + else + { + printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename); + return false; + } + } + else + { + // Otherwise read bios from card + nvBiosOveride = 0; + + // TODO: we should really check for the signature before copying the rom, i think. + + // PRAMIN first + nvRom = (uint8_t*)®s[NV_PRAMIN_OFFSET]; + bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE); + + // Valid Signature ? + if (rom[0] != 0x55 && rom[1] != 0xaa) + { + // PROM next + // Enable PROM access + (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED; + + nvRom = (uint8_t*)®s[NV_PROM_OFFSET]; + bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE); + + // disable PROM access + (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; + + // Valid Signature ? + if (rom[0] != 0x55 && rom[1] != 0xaa) + { + // 0xC0000 last + bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE); + + // Valid Signature ? + if (rom[0] != 0x55 && rom[1] != 0xaa) + { + printf("ERROR: Unable to locate nVidia Video BIOS\n"); + return false; + } + else + { + DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + } + } + else + { + DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + } + } + else + { + DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + } + } + + if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) { + printf("ERROR: nVidia ROM Patching Failed!\n"); + //return false; + } + + rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]); + + // check for 'PCIR' sig + if (rom_pci_header->signature == 0x50434952) + { + if (rom_pci_header->device_id != nvda_dev->device_id) + { + // Get Model from the OpROM + model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id); + } + else + { + printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature); + } + } + + if (!string) { + string = devprop_create_string(); + } + device = devprop_add_device(string, devicepath); + + /* FIXME: for primary graphics card only */ + boot_display = 1; + devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4); + + if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) { + uint8_t built_in = 0x01; + devprop_add_value(device, "@0,built-in", &built_in, 1); + } + + // get bios version + const int MAX_BIOS_VERSION_LENGTH = 32; + char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH); + + memset(version_str, 0, MAX_BIOS_VERSION_LENGTH); + + int i, version_start; + int crlf_count = 0; + + // only search the first 384 bytes + for (i = 0; i < 0x180; i++) + { + if (rom[i] == 0x0D && rom[i+1] == 0x0A) + { + crlf_count++; + // second 0x0D0A was found, extract bios version + if (crlf_count == 2) + { + if (rom[i-1] == 0x20) i--; // strip last " " + + for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) + { + // find start + if (rom[version_start] == 0x00) + { + version_start++; + + // strip "Version " + if (strncmp((const char*)rom+version_start, "Version ", 8) == 0) + { + version_start += 8; + } + + strncpy(version_str, (const char*)rom+version_start, i-version_start); + break; + } + } + break; + } + } + } + + sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str); + sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id); + + if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2) + { + uint8_t new_NVCAP[NVCAP_LEN]; + + if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) + { + verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath); + memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN); + } + } + + if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2) + { + uint8_t new_dcfg0[DCFG0_LEN]; + + if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0) + { + memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN); + + verbose("Using user supplied @0,display-cfg\n"); + printf("@0,display-cfg: %02x%02x%02x%02x\n", + default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]); + } + } + + if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2) + { + uint8_t new_dcfg1[DCFG1_LEN]; + + if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0) + { + memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN); + + verbose("Using user supplied @1,display-cfg\n"); + printf("@1,display-cfg: %02x%02x%02x%02x\n", + default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]); + } + } + +#if DEBUG_NVCAP + printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n", + default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3], + default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7], + default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11], + default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15], + default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]); +#endif + + devprop_add_nvidia_template(device); + devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN); + devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4); + devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1); + devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1); + devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN); + devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN); + + //add HDMI Audio back to nvidia + //http://forge.voodooprojects.org/p/chameleon/issues/67/ +// uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00}; +// devprop_add_value(device, "@1,connector-type",connector_type_1, 4); + //end Nvidia HDMI Audio + + if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit) + { + devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512)); + } + + stringdata = malloc(sizeof(uint8_t) * string->length); + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + + return true; +} Index: branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Makefile =================================================================== --- branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Makefile (revision 0) +++ branches/ErmaC/i386/modules/NVIDIAGraphicsEnabler/Makefile (revision 1568) @@ -0,0 +1,13 @@ +MODULE_NAME = NVIDIAGraphicsEnabler +MODULE_AUTHOR = Chameleon +MODULE_DESCRIPTION = to be added... +MODULE_VERSION = "1.0.0" +MODULE_COMPAT_VERSION = "1.0.0" +MODULE_START = $(MODULE_NAME)_start +MODULE_DEPENDENCIES = + +DIR = NVIDIAGraphicsEnabler + +MODULE_OBJS = nvidia.o NVIDIAGraphicsEnabler.o + +include ../MakeInc.dir Index: branches/ErmaC/i386/modules/IntelGraphicsEnabler/gma.c =================================================================== --- branches/ErmaC/i386/modules/IntelGraphicsEnabler/gma.c (revision 0) +++ branches/ErmaC/i386/modules/IntelGraphicsEnabler/gma.c (revision 1568) @@ -0,0 +1,300 @@ +/* + Original patch by Nawcom + http://forum.voodooprojects.org/index.php/topic,1029.0.html +*/ + +#include "libsa.h" +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "device_inject.h" +#include "gma.h" + +#ifndef DEBUG_GMA +#define DEBUG_GMA 0 +#endif + +#if DEBUG_GMA +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + + +uint8_t GMAX3100_vals[22][4] = { + { 0x01,0x00,0x00,0x00 }, + { 0x01,0x00,0x00,0x00 }, + { 0x01,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x08 }, + { 0x64,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x08 }, + { 0x01,0x00,0x00,0x00 }, + { 0x20,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x01,0x00,0x00,0x00 }, + { 0x20,0x03,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x08,0x52,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x01,0x00,0x00,0x00 }, + { 0x01,0x00,0x00,0x00 }, + { 0x3B,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 } +}; + +uint8_t HD2000_vals[16][4] = { + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x14,0x00,0x00,0x00 }, + { 0xfa,0x00,0x00,0x00 }, + { 0x2c,0x01,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x14,0x00,0x00,0x00 }, + { 0xf4,0x01,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x01,0x00,0x00,0x00 }, +}; + +uint8_t HD3000_vals[16][4] = { + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x14,0x00,0x00,0x00 }, + { 0xfa,0x00,0x00,0x00 }, + { 0x2c,0x01,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x14,0x00,0x00,0x00 }, + { 0xf4,0x01,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00 }, + { 0x01,0x00,0x00,0x00 }, +}; + +uint8_t HD2000_tbl_info[18] = { + 0x30,0x44,0x02,0x02,0x02,0x02,0x00,0x00,0x00, + 0x00,0x01,0x02,0x02,0x02,0x00,0x01,0x02,0x02 +}; +uint8_t HD2000_os_info[20] = { + 0x30,0x49,0x01,0x11,0x11,0x11,0x08,0x00,0x00,0x01, + 0xf0,0x1f,0x01,0x00,0x00,0x00,0x10,0x07,0x00,0x00 +}; + +// The following values came from a Sandy Bridge MacBook Air +uint8_t HD3000_tbl_info[18] = { + 0x30,0x44,0x02,0x02,0x02,0x02,0x00,0x00,0x00, + 0x00,0x02,0x02,0x02,0x02,0x01,0x01,0x01,0x01 +}; + +// The following values came from a Sandy Bridge MacBook Air +uint8_t HD3000_os_info[20] = { + 0x30,0x49,0x01,0x12,0x12,0x12,0x08,0x00,0x00,0x01, + 0xf0,0x1f,0x01,0x00,0x00,0x00,0x10,0x07,0x00,0x00 +}; + + +uint8_t reg_TRUE[] = { 0x01, 0x00, 0x00, 0x00 }; +uint8_t reg_FALSE[] = { 0x00, 0x00, 0x00, 0x00 }; + +static struct gma_gpu_t KnownGPUS[] = { + { 0x00000000, "Unknown" }, + { 0x808627A2, "Mobile GMA950" }, + { 0x808627AE, "Mobile GMA950" }, + { 0x808627A6, "Mobile GMA950" }, + { 0x8086A011, "Mobile GMA3150" }, + { 0x8086A012, "Mobile GMA3150" }, + { 0x80862772, "Desktop GMA950" }, + { 0x80862776, "Desktop GMA950" }, +// { 0x8086A001, "Desktop GMA3150" }, + { 0x8086A001, "Mobile GMA3150" }, + { 0x8086A002, "Desktop GMA3150" }, + { 0x80862A02, "GMAX3100" }, + { 0x80862A03, "GMAX3100" }, + { 0x80862A12, "GMAX3100" }, + { 0x80862A13, "GMAX3100" }, + { 0x80862A42, "GMAX3100" }, + { 0x80862A43, "GMAX3100" }, + { 0x80860102, "Intel HD Graphics 2000" }, + { 0x80860106, "Intel HD Graphics 2000 Mobile" }, + { 0x80860112, "Intel HD Graphics 3000" }, + { 0x80860116, "Intel HD Graphics 3000 Mobile" }, + { 0x80860122, "Intel HD Graphics 3000" }, + { 0x80860126, "Intel HD Graphics 3000 Mobile" }, +}; + +char *get_gma_model(uint32_t id) { + int i = 0; + + for (i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++) + { + if (KnownGPUS[i].device == id) + return KnownGPUS[i].name; + } + return KnownGPUS[0].name; +} + +bool setup_gma_devprop(pci_dt_t *gma_dev) +{ + char *devicepath; + volatile uint8_t *regs; + uint32_t bar[7]; + char *model; + uint8_t BuiltIn = 0x00; + uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 }; + unsigned int device_id; + + devicepath = get_pci_dev_path(gma_dev); + + bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10); + regs = (uint8_t *) (bar[0] & ~0x0f); + + model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id); + device_id = gma_dev->device_id; + + verbose("Intel %s [%04x:%04x] :: %s\n", + model, gma_dev->vendor_id, gma_dev->device_id, devicepath); + + if (!string) + string = devprop_create_string(); + + struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice)); + device = devprop_add_device(string, devicepath); + + if (!device) + { + printf("Failed initializing dev-prop string dev-entry.\n"); + pause(); + return false; + } + + devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1)); + devprop_add_value(device, "device_type", (uint8_t*)"display", 8); + + if ((model == (char *)"Mobile GMA950") + || (model == (char *)"Mobile GMA3150")) + { + devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4); + devprop_add_value(device, "built-in", &BuiltIn, 1); + devprop_add_value(device, "class-code", ClassFix, 4); + } + else if ((model == (char *)"Desktop GMA950") + || (model == (char *)"Desktop GMA3150")) + { + BuiltIn = 0x01; + devprop_add_value(device, "built-in", &BuiltIn, 1); + devprop_add_value(device, "class-code", ClassFix, 4); + } + else if (model == (char *)"GMAX3100") + { + devprop_add_value(device, "AAPL,HasPanel", GMAX3100_vals[0], 4); + devprop_add_value(device, "AAPL,SelfRefreshSupported", GMAX3100_vals[1], 4); + devprop_add_value(device, "AAPL,aux-power-connected", GMAX3100_vals[2], 4); + devprop_add_value(device, "AAPL,backlight-control", GMAX3100_vals[3], 4); + devprop_add_value(device, "AAPL00,blackscreen-preferences", GMAX3100_vals[4], 4); + devprop_add_value(device, "AAPL01,BacklightIntensity", GMAX3100_vals[5], 4); + devprop_add_value(device, "AAPL01,blackscreen-preferences", GMAX3100_vals[6], 4); + devprop_add_value(device, "AAPL01,DataJustify", GMAX3100_vals[7], 4); + devprop_add_value(device, "AAPL01,Depth", GMAX3100_vals[8], 4); + devprop_add_value(device, "AAPL01,Dither", GMAX3100_vals[9], 4); + devprop_add_value(device, "AAPL01,DualLink", GMAX3100_vals[10], 4); + devprop_add_value(device, "AAPL01,Height", GMAX3100_vals[11], 4); + devprop_add_value(device, "AAPL01,Interlace", GMAX3100_vals[12], 4); + devprop_add_value(device, "AAPL01,Inverter", GMAX3100_vals[13], 4); + devprop_add_value(device, "AAPL01,InverterCurrent", GMAX3100_vals[14], 4); + devprop_add_value(device, "AAPL01,InverterCurrency", GMAX3100_vals[15], 4); + devprop_add_value(device, "AAPL01,LinkFormat", GMAX3100_vals[16], 4); + devprop_add_value(device, "AAPL01,LinkType", GMAX3100_vals[17], 4); + devprop_add_value(device, "AAPL01,Pipe", GMAX3100_vals[18], 4); + devprop_add_value(device, "AAPL01,PixelFormat", GMAX3100_vals[19], 4); + devprop_add_value(device, "AAPL01,Refresh", GMAX3100_vals[20], 4); + devprop_add_value(device, "AAPL01,Stretch", GMAX3100_vals[21], 4); + devprop_add_value(device, "class-code", ClassFix, 4); + } + else if (model == (char *)"Intel HD Graphics 2000 Mobile") + { + devprop_add_value(device, "class-code", ClassFix, 4); + devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); + devprop_add_value(device, "AAPL00,PixelFormat", HD2000_vals[0], 4); + devprop_add_value(device, "AAPL00,T1", HD2000_vals[1], 4); + devprop_add_value(device, "AAPL00,T2", HD2000_vals[2], 4); + devprop_add_value(device, "AAPL00,T3", HD2000_vals[3], 4); + devprop_add_value(device, "AAPL00,T4", HD2000_vals[4], 4); + devprop_add_value(device, "AAPL00,T5", HD2000_vals[5], 4); + devprop_add_value(device, "AAPL00,T6", HD2000_vals[6], 4); + devprop_add_value(device, "AAPL00,T7", HD2000_vals[7], 4); + devprop_add_value(device, "AAPL00,LinkType", HD2000_vals[8], 4); + devprop_add_value(device, "AAPL00,LinkFormat", HD2000_vals[9], 4); + devprop_add_value(device, "AAPL00,DualLink", HD2000_vals[10], 4); + devprop_add_value(device, "AAPL00,Dither", HD2000_vals[11], 4); + devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4); + devprop_add_value(device, "graphic-options", HD2000_vals[13], 4); + devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18); + devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20); + } + else if (model == (char *)"Intel HD Graphics 3000 Mobile") + { + devprop_add_value(device, "class-code", ClassFix, 4); + devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); + devprop_add_value(device, "AAPL00,PixelFormat", HD3000_vals[0], 4); + devprop_add_value(device, "AAPL00,T1", HD3000_vals[1], 4); + devprop_add_value(device, "AAPL00,T2", HD3000_vals[2], 4); + devprop_add_value(device, "AAPL00,T3", HD3000_vals[3], 4); + devprop_add_value(device, "AAPL00,T4", HD3000_vals[4], 4); + devprop_add_value(device, "AAPL00,T5", HD3000_vals[5], 4); + devprop_add_value(device, "AAPL00,T6", HD3000_vals[6], 4); + devprop_add_value(device, "AAPL00,T7", HD3000_vals[7], 4); + devprop_add_value(device, "AAPL00,LinkType", HD3000_vals[8], 4); + devprop_add_value(device, "AAPL00,LinkFormat", HD3000_vals[9], 4); + devprop_add_value(device, "AAPL00,DualLink", HD3000_vals[10], 4); + devprop_add_value(device, "AAPL00,Dither", HD3000_vals[11], 4); + devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4); + devprop_add_value(device, "graphic-options", HD3000_vals[13], 4); + devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18); + devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20); + } + else if (model == (char *)"Intel HD Graphics 2000") + { + devprop_add_value(device, "built-in", &BuiltIn, 1); + devprop_add_value(device, "class-code", ClassFix, 4); + devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id)); + devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); + devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18); + devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20); + } + else if (model == (char *)"Intel HD Graphics 3000") + { + devprop_add_value(device, "built-in", &BuiltIn, 1); + devprop_add_value(device, "class-code", ClassFix, 4); + device_id = 0x00000126; // Inject a valid mobile GPU device id instead of patching kexts + devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id)); + devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); + devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18); + devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20); + } + + stringdata = malloc(sizeof(uint8_t) * string->length); + if (!stringdata) + { + printf("No stringdata.\n"); + pause(); + return false; + } + + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + + return true; +} Index: branches/ErmaC/i386/modules/IntelGraphicsEnabler/IntelGraphicsEnabler.c =================================================================== --- branches/ErmaC/i386/modules/IntelGraphicsEnabler/IntelGraphicsEnabler.c (revision 0) +++ branches/ErmaC/i386/modules/IntelGraphicsEnabler/IntelGraphicsEnabler.c (revision 1568) @@ -0,0 +1,44 @@ +/* + * IntelGraphicsEnabler Module + * Enables a few Intel cards to be used out of the box in OS X. + * + */ + +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "gma.h" +#include "modules.h" + +#define kGraphicsEnablerKey "GraphicsEnabler" + +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4); + + +void IntelGraphicsEnabler_start() +{ + register_hook_callback("PCIDevice", &GraphicsEnabler_hook); +} + + +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4) +{ + pci_dt_t* current = arg1; + + if (current->class_id != PCI_CLASS_DISPLAY_VGA) return; + + char *devicepath = get_pci_dev_path(current); + + bool do_gfx_devprop = true; + getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->chameleonConfig); + + if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_INTEL)) + { + verbose("Intel VGA Controller [%04x:%04x] :: %s \n", + current->vendor_id, current->device_id, devicepath); + setup_gma_devprop(current); + } + else + verbose("[%04x:%04x] :: %s, is not a Intel VGA Controller.\n", + current->vendor_id, current->device_id, devicepath); +} Index: branches/ErmaC/i386/modules/IntelGraphicsEnabler/Cconfig =================================================================== --- branches/ErmaC/i386/modules/IntelGraphicsEnabler/Cconfig (revision 0) +++ branches/ErmaC/i386/modules/IntelGraphicsEnabler/Cconfig (revision 1568) @@ -0,0 +1,10 @@ +# +# Chameleon Modules +# + +config INTELGRAPHICSENABLER_MODULE + tristate "IntelGraphicsEnabler Module" + default m + ---help--- + Say Y here if you want to enable the use of this module. + Index: branches/ErmaC/i386/modules/IntelGraphicsEnabler/gma.h =================================================================== --- branches/ErmaC/i386/modules/IntelGraphicsEnabler/gma.h (revision 0) +++ branches/ErmaC/i386/modules/IntelGraphicsEnabler/gma.h (revision 1568) @@ -0,0 +1,16 @@ +#ifndef __LIBSAIO_GMA_H +#define __LIBSAIO_GMA_H + +bool setup_gma_devprop(pci_dt_t *gma_dev); + +struct gma_gpu_t { + unsigned device; + char *name; +}; + +#define REG8(reg) ((volatile uint8_t *)regs)[(reg)] +#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1] +#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2] + + +#endif /* !__LIBSAIO_GMA_H */ Index: branches/ErmaC/i386/modules/IntelGraphicsEnabler/Readme.txt =================================================================== --- branches/ErmaC/i386/modules/IntelGraphicsEnabler/Readme.txt (revision 0) +++ branches/ErmaC/i386/modules/IntelGraphicsEnabler/Readme.txt (revision 1568) @@ -0,0 +1,16 @@ +Module: IntelGraphicsEnabler + +Description: Enables a few Intel cards to be used out of the box, + mostly mobile ones. + +Dependencies: none + +Keys: GraphicsEnabler Yes/No (enabled by default) + Disable GraphicsEnabler patch. + + +Adaptation of Meklort's work. +Original patch by Nawcom: +http://forum.voodooprojects.org/index.php/topic,1029.0.html + +TODO: test my GMA desktop again (Azi) \ No newline at end of file Index: branches/ErmaC/i386/modules/IntelGraphicsEnabler/Makefile =================================================================== --- branches/ErmaC/i386/modules/IntelGraphicsEnabler/Makefile (revision 0) +++ branches/ErmaC/i386/modules/IntelGraphicsEnabler/Makefile (revision 1568) @@ -0,0 +1,13 @@ +MODULE_NAME = IntelGraphicsEnabler +MODULE_AUTHOR = Chameleon +MODULE_DESCRIPTION = to be added... +MODULE_VERSION = "1.0.0" +MODULE_COMPAT_VERSION = "1.0.0" +MODULE_START = $(MODULE_NAME)_start +MODULE_DEPENDENCIES = + +DIR = IntelGraphicsEnabler + +MODULE_OBJS = gma.o IntelGraphicsEnabler.o + +include ../MakeInc.dir Index: branches/ErmaC/i386/modules/ATiGraphicsEnabler/ati.h =================================================================== --- branches/ErmaC/i386/modules/ATiGraphicsEnabler/ati.h (revision 0) +++ branches/ErmaC/i386/modules/ATiGraphicsEnabler/ati.h (revision 1568) @@ -0,0 +1,46 @@ +/* + * ATI injector + * + * Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas + * + * ATI injector is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * ATI driver and injector is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with ATI injector. If not, see . + */ + /* + * Alternatively you can choose to comply with APSL + */ + + +#ifndef __LIBSAIO_ATI_H +#define __LIBSAIO_ATI_H + +bool setup_ati_devprop(pci_dt_t *ati_dev); + +struct ati_chipsets_t { + unsigned device; + char *name; +}; + +struct ati_data_key { + uint32_t size; + char *name; + uint8_t data[]; +}; + +#define REG8(reg) ((volatile uint8_t *)regs)[(reg)] +#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1] +#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2] +#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val) + + +#endif /* !__LIBSAIO_ATI_H */ Index: branches/ErmaC/i386/modules/ATiGraphicsEnabler/ATiGraphicsEnabler.c =================================================================== --- branches/ErmaC/i386/modules/ATiGraphicsEnabler/ATiGraphicsEnabler.c (revision 0) +++ branches/ErmaC/i386/modules/ATiGraphicsEnabler/ATiGraphicsEnabler.c (revision 1568) @@ -0,0 +1,47 @@ +/* + * ATIGraphicsEnabler Module --- + * Enables many ati "legacy ??" cards to be used out of the box in OS X. + * This was converted from ( < r784) boot2 code to a boot2 module. + * + */ + +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "ati.h" +#include "modules.h" + + +#define kGraphicsEnablerKey "GraphicsEnabler" // change? + +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4); + + +void ATiGraphicsEnabler_start() +{ + register_hook_callback("PCIDevice", &GraphicsEnabler_hook); +} + + +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4) +{ + pci_dt_t* current = arg1; + + if (current->class_id != PCI_CLASS_DISPLAY_VGA) return; + + char *devicepath = get_pci_dev_path(current); + + bool do_gfx_devprop = true; + getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->chameleonConfig); + + // AMD ?? i don't find any vga 1022 vendor!.. thou ATI isn't used anymore! + if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI)) + { + verbose("ATI VGA Controller [%04x:%04x] :: %s \n", + current->vendor_id, current->device_id, devicepath); + setup_ati_devprop(current); + } + else + verbose("[%04x:%04x] :: %s, is not a AMD/ATI VGA Controller.\n",// amd ?? + current->vendor_id, current->device_id, devicepath); +} Index: branches/ErmaC/i386/modules/ATiGraphicsEnabler/Cconfig =================================================================== --- branches/ErmaC/i386/modules/ATiGraphicsEnabler/Cconfig (revision 0) +++ branches/ErmaC/i386/modules/ATiGraphicsEnabler/Cconfig (revision 1568) @@ -0,0 +1,10 @@ +# +# Chameleon Modules +# + +config ATIGRAPHICSENABLER_MODULE + tristate "ATiGraphicsEnabler Module" + default m + ---help--- + Say Y here if you want to enable the use of this module. + Index: branches/ErmaC/i386/modules/ATiGraphicsEnabler/Readme.txt =================================================================== --- branches/ErmaC/i386/modules/ATiGraphicsEnabler/Readme.txt (revision 0) +++ branches/ErmaC/i386/modules/ATiGraphicsEnabler/Readme.txt (revision 1568) @@ -0,0 +1,16 @@ +Module: ATiGraphicsEnabler + +Description: the GraphicsEnabler ATI code ( < r784) ported to a module. +Support for "legacy" cards... +Based on Meklort's work. + +Dependencies: none + +Keys: GraphicsEnabler (enabled by default) + UseAtiROM (disabled by default) + + + +TODO: +- naming: ATi or AMD ?? +- merge with AMDGraphicsEnabler ?? \ No newline at end of file Index: branches/ErmaC/i386/modules/ATiGraphicsEnabler/Makefile =================================================================== --- branches/ErmaC/i386/modules/ATiGraphicsEnabler/Makefile (revision 0) +++ branches/ErmaC/i386/modules/ATiGraphicsEnabler/Makefile (revision 1568) @@ -0,0 +1,13 @@ +MODULE_NAME = ATiGraphicsEnabler +MODULE_AUTHOR = Chameleon +MODULE_DESCRIPTION = to be added... +MODULE_VERSION = "1.0.0" +MODULE_COMPAT_VERSION = "1.0.0" +MODULE_START = $(MODULE_NAME)_start +MODULE_DEPENDENCIES = + +DIR = ATiGraphicsEnabler + +MODULE_OBJS = ati.o ATiGraphicsEnabler.o + +include ../MakeInc.dir Index: branches/ErmaC/i386/modules/ATiGraphicsEnabler/ati.c =================================================================== --- branches/ErmaC/i386/modules/ATiGraphicsEnabler/ati.c (revision 0) +++ branches/ErmaC/i386/modules/ATiGraphicsEnabler/ati.c (revision 1568) @@ -0,0 +1,982 @@ +/* + * ATI injector + * + * Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas + * + * ATI injector is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * ATI driver and injector is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with ATI injector. If not, see . + */ +/* + * Alternatively you can choose to comply with APSL + */ + +#include "libsa.h" +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "device_inject.h" +#include "ati.h" + +#ifndef DEBUG_ATI +#define DEBUG_ATI 0 +#endif + +#if DEBUG_ATI +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +#define kUseAtiROMKey "UseAtiROM" +#define kAtiConfig "AtiConfig" + +#define MAX_NUM_DCB_ENTRIES 16 + +#define TYPE_GROUPED 0xff + +extern uint32_t devices_number; + +// ====================//==================== +// properties + +// "@" +const char *ati_name_0[] = { "@0,name", "ATY,%s" }; +const char *ati_name_1[] = { "@1,name", "ATY,%s" }; +const char *ati_device_type_0[] = { "@0,device_type", "display" }; +const char *ati_device_type_1[] = { "@1,device_type", "display" }; +const char *ati_compatible_0[] = { "@0,compatible", "ATY,%s" }; +const char *ati_compatible_1[] = { "@1,compatible", "ATY,%s" }; +const char *ati_efidisplay_0[] = { "@0,ATY,EFIDisplay", "TMDSB" }; +const char *ati_display_type_0[] = { "@0,display-type", "LCD" }; +const char *ati_display_type_1[] = { "@1,display-type", "NONE" }; + +// no "@" +const char *ati_name[] = { "name", "ATY,%sParent" }; +const char *ati_device_type[] = { "device_type", "ATY,%sParent" }; +const char *ati_card_no[] = { "ATY,Card#", "109-B77101-00" }; +const char *ati_copyright[] = { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" }; +const char *ati_efi_compile_d[] = { "ATY,EFICompileDate", "Jan 26 2009" }; +const char *ati_efi_version[] = { "ATY,EFIVersion", "01.00.318" }; +const char *ati_efi_versionB[] = { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" }; +const char *ati_efi_versionE[] = { "ATY,EFIVersionE", "113-B7710A-318" }; +const char *ati_mrt[] = { "ATY,MRT", " " }; +const char *ati_romno[] = { "ATY,Rom#", "113-B7710C-176" }; +// non 48xx key ??? +const char *ati_efidisplay_0_n4[] = { "@0,ATY,EFIDisplay", "TMDSA" }; + +// =====//===== + +// ati_data_key "@" +struct ati_data_key ati_connector_type_0 = { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} }; +struct ati_data_key ati_connector_type_1 = { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_display_con_fl_type_0 = { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} }; +// non 48xx keys ??? +struct ati_data_key ati_connector_type_0_n4 = { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_connector_type_1_n4 = { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} }; +struct ati_data_key ati_vram_memsize_0 = { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_vram_memsize_1 = { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }; + +// no "@" +struct ati_data_key ati_aux_power_conn = { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_backlight_ctrl = { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_aapl01_coher = { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_efi_disp_conf = { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} }; +struct ati_data_key ati_efi_drv_type = { 0x01, "ATY,EFIDriverType", {0x02} }; +struct ati_data_key ati_efi_enbl_mode = { 0x01, "ATY,EFIEnabledMode", {0x01} }; +struct ati_data_key ati_efi_init_stat = { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_efi_orientation = { 0x02, "ATY,EFIOrientation", {0x02, 0x00} }; +struct ati_data_key ati_mclk = { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} }; +struct ati_data_key ati_mem_rev_id = { 0x02, "ATY,MemRevisionID", {0x03, 0x00} }; +struct ati_data_key ati_mem_vend_id = { 0x02, "ATY,MemVendorID", {0x02, 0x00} }; +struct ati_data_key ati_sclk = { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} }; +struct ati_data_key ati_vendor_id = { 0x02, "ATY,VendorID", {0x02, 0x10} }; + +struct ati_data_key ati_platform_info = { 0x80, "ATY,PlatformInfo", + {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }; + +struct ati_data_key ati_mvad = { 0x40, "MVAD", + {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, + 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, + 0x92, 0x20, 0x00, 0x03} }; + +struct ati_data_key ati_saved_config = { 0x100, "saved-config", + {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, + 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, + 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }; +// non 48xx keys ??? +struct ati_data_key ati_fb_offset_n4 = { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_hwgpio_n4 = { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} }; +struct ati_data_key ati_iospace_offset_n4 = { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} }; +struct ati_data_key ati_mclk_n4 = { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} }; +struct ati_data_key ati_sclk_n4 = { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} }; +struct ati_data_key ati_refclk_n4 = { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} }; +struct ati_data_key ati_regspace_offset_n4 = { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} }; +struct ati_data_key ati_aapl_blackscr_prefs_0_n4 = { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_aapl_blackscr_prefs_1_n4 = { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} }; +struct ati_data_key ati_swgpio_info_n4 = { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} }; +struct ati_data_key ati_efi_orientation_n4 = { 0x01, "ATY,EFIOrientation", {0x08} }; + +struct ati_data_key ati_aapl_emc_disp_list_n4 = { 0x40, "AAPL,EMC-Display-List", + {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, + 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00} }; + +struct ati_data_key ati_mvad_n4 = { 0x100, "MVAD", + {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, + 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }; + +struct ati_data_key ati_saved_config_n4 = { 0x100, "saved-config", + {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, + 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }; + +// ====================//==================== + +/* ??? +struct pcir_s { + uint32_t signature; + uint16_t vid; + uint16_t devid; +};*/ + +static struct ati_chipsets_t ATIChipsets[] = { + { 0x00000000, "Unknown" }, +// ===================================================== + { 0x10027181, "ATI Radeon X1600 Series" }, // Azi + { 0x10027183, "ATI Radeon X1550 Series" }, // Beej + { 0x10027187, "ATI Radeon X1300 Series" }, // Mckibble + { 0x100271C5, "ATI Mobility Radeon X1600" }, // Darles, Derc - looks like it's a no go ?? + { 0x100271D4, "ATI Mobility FireGL V5250" }, // Downlord - ?? + + { 0x10027244, "ATI RADEON X1950 Series" }, // tlfrance +// ===================================================== + { 0x10029589, "ATI Radeon 2600 Series" }, + { 0x10029588, "ATI Radeon 2600 Series" }, + { 0x100294C3, "ATI Radeon 2400 Series" }, + { 0x100294C4, "ATI Radeon 2400 Series" }, + { 0x100294C6, "ATI Radeon 2400 Series" }, + { 0x10029400, "ATI Radeon 2900 Series" }, + { 0x10029405, "ATI Radeon 2900GT Series" }, + { 0x10029581, "ATI Radeon 2600 Series" }, + { 0x10029583, "ATI Radeon 2600 Series" }, + { 0x10029586, "ATI Radeon 2600 Series" }, + { 0x10029587, "ATI Radeon 2600 Series" }, + { 0x100294C9, "ATI Radeon 2400 Series" }, + { 0x10029501, "ATI Radeon 3800 Series" }, + { 0x10029505, "ATI Radeon 3800 Series" }, + { 0x10029515, "ATI Radeon 3800 Series" }, + { 0x10029507, "ATI Radeon 3800 Series" }, + { 0x10029500, "ATI Radeon 3800 Series" }, + { 0x1002950F, "ATI Radeon 3800X2 Series" }, + { 0x100295C5, "ATI Radeon 3400 Series" }, + { 0x100295C7, "ATI Radeon 3400 Series" }, + { 0x100295C0, "ATI Radeon 3400 Series" }, + { 0x10029596, "ATI Radeon 3600 Series" }, + { 0x10029590, "ATI Radeon 3600 Series" }, + { 0x10029599, "ATI Radeon 3600 Series" }, + { 0x10029597, "ATI Radeon 3600 Series" }, + { 0x10029598, "ATI Radeon 3600 Series" }, + { 0x10029442, "ATI Radeon 4850 Series" }, + { 0x10029440, "ATI Radeon 4870 Series" }, + { 0x1002944C, "ATI Radeon 4830 Series" }, + { 0x10029460, "ATI Radeon 4890 Series" }, + { 0x10029462, "ATI Radeon 4890 Series" }, + { 0x10029441, "ATI Radeon 4870X2 Series" }, + { 0x10029443, "ATI Radeon 4850X2 Series" }, + { 0x10029444, "ATI Radeon 4800 Series" }, + { 0x10029446, "ATI Radeon 4800 Series" }, + { 0x1002944E, "ATI Radeon 4730 Series" }, + { 0x10029450, "ATI Radeon 4800 Series" }, + { 0x10029452, "ATI Radeon 4800 Series" }, + { 0x10029456, "ATI Radeon 4800 Series" }, + { 0x1002944A, "ATI Radeon 4800 Mobility Series" }, + { 0x1002945A, "ATI Radeon 4800 Mobility Series" }, + { 0x1002945B, "ATI Radeon 4800 Mobility Series" }, + { 0x1002944B, "ATI Radeon 4800 Mobility Series" }, + { 0x10029490, "ATI Radeon 4670 Series" }, + { 0x10029498, "ATI Radeon 4650 Series" }, + { 0x10029490, "ATI Radeon 4600 Series" }, + { 0x10029498, "ATI Radeon 4600 Series" }, + { 0x1002949E, "ATI Radeon 4600 Series" }, + { 0x10029480, "ATI Radeon 4600 Series" }, + { 0x10029488, "ATI Radeon 4600 Series" }, + { 0x10029540, "ATI Radeon 4500 Series" }, + { 0x10029541, "ATI Radeon 4500 Series" }, + { 0x1002954E, "ATI Radeon 4500 Series" }, + { 0x10029552, "ATI Radeon 4300 Mobility Series" }, + { 0x10029553, "ATI Radeon 4500 Mobility Series" }, + { 0x1002954F, "ATI Radeon 4300 Series" }, + { 0x100294B3, "ATI Radeon 4770 Series" }, + { 0x100294B5, "ATI Radeon 4770 Series" }, + { 0x100268B8, "ATI Radeon 5700 Series" }, + { 0x100268BE, "ATI Radeon 5700 Series" }, + { 0x10026898, "ATI Radeon 5800 Series" }, + { 0x10026899, "ATI Radeon 5800 Series" } +}; + +// <= 10.6.7 +static struct ati_chipsets_t ATIFramebuffers_pre[] = { + { 0x00000000, "Megalodon" }, +// ============================= + { 0x10027181, "Megalodon" }, +/* { 0x10027183, "Caretta" }, + { 0x10027187, "Caretta" }, + { 0x100271C5, "Wormy" }, // ?? + { 0x100271D4, "Wormy" }, // ?? + + { 0x10027244, "Alopias" },*/ +// ============================= + { 0x10029589, "Lamna" }, + { 0x10029588, "Lamna" }, + { 0x100294C3, "Iago" }, + { 0x100294C4, "Iago" }, + { 0x100294C6, "Iago" }, + { 0x10029400, "Franklin" }, + { 0x10029405, "Franklin" }, + { 0x10029581, "Hypoprion" }, + { 0x10029583, "Hypoprion" }, + { 0x10029586, "Hypoprion" }, + { 0x10029587, "Hypoprion" }, + { 0x100294C9, "Iago" }, + { 0x10029501, "Megalodon" }, + { 0x10029505, "Megalodon" }, + { 0x10029515, "Megalodon" }, + { 0x10029507, "Megalodon" }, + { 0x10029500, "Megalodon" }, + { 0x1002950F, "Triakis" }, + { 0x100295C5, "Iago" }, + { 0x100295C7, "Iago" }, + { 0x100295C0, "Iago" }, + { 0x10029596, "Megalodon" }, + { 0x10029590, "Megalodon" }, + { 0x10029599, "Megalodon" }, + { 0x10029597, "Megalodon" }, + { 0x10029598, "Megalodon" }, + { 0x10029442, "Motmot" }, + { 0x10029440, "Motmot" }, + { 0x1002944C, "Motmot" }, + { 0x10029460, "Motmot" }, + { 0x10029462, "Motmot" }, + { 0x10029441, "Motmot" }, + { 0x10029443, "Motmot" }, + { 0x10029444, "Motmot" }, + { 0x10029446, "Motmot" }, + { 0x1002944E, "Motmot" }, + { 0x10029450, "Motmot" }, + { 0x10029452, "Motmot" }, + { 0x10029456, "Motmot" }, + { 0x1002944A, "Motmot" }, + { 0x1002945A, "Motmot" }, + { 0x1002945B, "Motmot" }, + { 0x1002944B, "Motmot" }, + { 0x10029490, "Peregrine" }, + { 0x10029498, "Peregrine" }, + { 0x1002949E, "Peregrine" }, + { 0x10029480, "Peregrine" }, + { 0x10029488, "Peregrine" }, + { 0x10029540, "Peregrine" }, + { 0x10029541, "Peregrine" }, + { 0x1002954E, "Peregrine" }, + { 0x10029552, "Peregrine" }, + { 0x10029553, "Peregrine" }, + { 0x1002954F, "Peregrine" }, + { 0x100294B3, "Peregrine" }, + { 0x100294B5, "Peregrine" }, + { 0x100268B8, "Motmot" }, + { 0x100268BE, "Motmot" }, + { 0x10026898, "Motmot" }, + { 0x10026899, "Motmot" } +}; + +// >= 10.6.8 +static struct ati_chipsets_t ATIFramebuffers_post[] = { + { 0x00000000, "Megalodon" }, +// ============================= + { 0x10027181, "Caretta" }, + { 0x10027183, "Caretta" }, + { 0x10027187, "Caretta" }, + { 0x100271C5, "Wormy" }, // ?? + { 0x100271D4, "Wormy" }, // ?? + + { 0x10027244, "Alopias" }, +// ============================= +/* { 0x10029589, "Lamna" }, + { 0x10029588, "Lamna" }, + { 0x100294C3, "Iago" }, + { 0x100294C4, "Iago" }, + { 0x100294C6, "Iago" }, + { 0x10029400, "Franklin" }, + { 0x10029405, "Franklin" }, + { 0x10029581, "Hypoprion" }, + { 0x10029583, "Hypoprion" }, + { 0x10029586, "Hypoprion" }, + { 0x10029587, "Hypoprion" }, + { 0x100294C9, "Iago" }, + { 0x10029501, "Megalodon" }, + { 0x10029505, "Megalodon" }, + { 0x10029515, "Megalodon" }, + { 0x10029507, "Megalodon" }, + { 0x10029500, "Megalodon" }, + { 0x1002950F, "Triakis" }, + { 0x100295C5, "Iago" }, + { 0x100295C7, "Iago" }, + { 0x100295C0, "Iago" }, + { 0x10029596, "Megalodon" }, + { 0x10029590, "Megalodon" }, + { 0x10029599, "Megalodon" }, + { 0x10029597, "Megalodon" }, + { 0x10029598, "Megalodon" }, + { 0x10029442, "Motmot" }, + { 0x10029440, "Motmot" }, + { 0x1002944C, "Motmot" }, + { 0x10029460, "Motmot" }, + { 0x10029462, "Motmot" }, + { 0x10029441, "Motmot" }, + { 0x10029443, "Motmot" }, + { 0x10029444, "Motmot" }, + { 0x10029446, "Motmot" }, + { 0x1002944E, "Motmot" }, + { 0x10029450, "Motmot" }, + { 0x10029452, "Motmot" }, + { 0x10029456, "Motmot" }, + { 0x1002944A, "Motmot" }, + { 0x1002945A, "Motmot" }, + { 0x1002945B, "Motmot" }, + { 0x1002944B, "Motmot" }, + { 0x10029490, "Peregrine" }, + { 0x10029498, "Peregrine" }, + { 0x1002949E, "Peregrine" },*/ + { 0x10029480, "Gliff" }//, Akbar +/* { 0x10029488, "Peregrine" }, + { 0x10029540, "Peregrine" }, + { 0x10029541, "Peregrine" }, + { 0x1002954E, "Peregrine" }, + { 0x10029552, "Peregrine" }, + { 0x10029553, "Peregrine" }, + { 0x1002954F, "Peregrine" }, + { 0x100294B3, "Peregrine" }, + { 0x100294B5, "Peregrine" }, + { 0x100268B8, "Motmot" }, + { 0x100268BE, "Motmot" }, + { 0x10026898, "Motmot" }, + { 0x10026899, "Motmot" }*/ +}; + +static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode) +{ + uint32_t bar[7]; + volatile uint32_t *regs; + + bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 ); + regs = (uint32_t *) (bar[2] & ~0x0f); + + if (mode) { + if (mode != 1) { + return 0xe00002c7; + } + REG32W(0x179c, 0x00080000); + REG32W(0x1798, 0x00080721); + REG32W(0x17a0, 0x00080621); + REG32W(0x1600, 0x14030300); + REG32W(0x1798, 0x21); + REG32W(0x17a0, 0x21); + REG32W(0x179c, 0x00); + REG32W(0x17a0, 0x21); + REG32W(0x1798, 0x21); + REG32W(0x1798, 0x21); + } else { + REG32W(0x1600, 0x14030302); + REG32W(0x1798, 0x21); + REG32W(0x17a0, 0x21); + REG32W(0x179c, 0x00080000); + REG32W(0x17a0, 0x00080621); + REG32W(0x1798, 0x00080721); + REG32W(0x1798, 0x21); + REG32W(0x17a0, 0x21); + REG32W(0x179c, 0x00); + REG32W(0x1604, 0x0400e9fc); + REG32W(0x161c, 0x00); + REG32W(0x1620, 0x9f); + REG32W(0x1618, 0x00040004); + REG32W(0x161c, 0x00); + REG32W(0x1604, 0xe9fc); + REG32W(0x179c, 0x00080000); + REG32W(0x1798, 0x00080721); + REG32W(0x17a0, 0x00080621); + REG32W(0x1798, 0x21); + REG32W(0x17a0, 0x21); + REG32W(0x179c, 0x00); + } + return 0; +} + +static uint8_t *readAtomBIOS(pci_dt_t *ati_dev) +{ + uint32_t bar[7]; + uint32_t *BIOSBase; + uint32_t counter; + volatile uint32_t *regs; + + bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 ); + regs = (volatile uint32_t *) (bar[2] & ~0x0f); + accessROM(ati_dev, 0); + REG32W(0xa8, 0); + REG32R(0xac); + REG32W(0xa8, 0); + REG32R(0xac); + + BIOSBase = malloc(0x10000); + REG32W(0xa8, 0); + BIOSBase[0] = REG32R(0xac); + counter = 4; + do { + REG32W(0xa8, counter); + BIOSBase[counter/4] = REG32R(0xac); + counter +=4; + } while (counter != 0x10000); + accessROM((pci_dt_t *)regs, 1); + + if (*(uint16_t *)BIOSBase != 0xAA55) { + printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase); + return 0; + } + return (uint8_t *)BIOSBase; +} + +#define R5XX_CONFIG_MEMSIZE 0x00F8 //Azi:--- +#define R6XX_CONFIG_MEMSIZE 0x5428 + +uint32_t getvramsizekb(pci_dt_t *ati_dev) +{ + uint32_t bar[7]; + uint32_t size; + volatile uint32_t *regs; + + bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 ); + regs = (uint32_t *) (bar[2] & ~0x0f); + if (ati_dev->device_id < 0x9400) { + size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10; + } else { + size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10; + } + return size; +} + +#define AVIVO_D1CRTC_CONTROL 0x6080 +#define AVIVO_CRTC_EN (1<<0) +#define AVIVO_D2CRTC_CONTROL 0x6880 + +static bool radeon_card_posted(pci_dt_t *ati_dev) +{ + // if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards. +/* char *biosimage = 0xC0000; + + if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa) + { + option_rom_pci_header_t *rom_pci_header; + rom_pci_header = (option_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256); + + if (rom_pci_header->signature == 0x52494350) + { + if (rom_pci_header->device_id == ati_dev->device_id) + { + return true; + printf("Card was POSTed\n"); + } + } + } + return false; + printf("Card was not POSTed\n"); + */ + //fails yet + uint32_t bar[7]; + uint32_t val; + volatile uint32_t *regs; + + bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18); + regs = (uint32_t *) (bar[2] & ~0x0f); + + val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL); + if (val & AVIVO_CRTC_EN) { + return true; + } else { + return false; + } +} + +static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize) +{ + int fd; + int size; + + if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) { + return 0; + } + size = file_size(fd); + if (size > bufsize) { + printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize); + size = bufsize; + } + size = read(fd, (char *)buf, size); + close(fd); + return size > 0 ? size : 0; +} + +static char *get_ati_model(uint32_t id) +{ + int i; + + for (i = 0; i < (sizeof(ATIChipsets) / sizeof(ATIChipsets[0])); i++) { + if (ATIChipsets[i].device == id) { + return ATIChipsets[i].name; + } + } + return ATIChipsets[0].name; +} + +static char *get_ati_fb(uint32_t id) +{ + int i; + + // limit patch to Snow & Lion explicitly!? + if ((gMacOSVersion[3] == '6') && (gMacOSVersion[5] >= '8')) + { + for (i = 0; i < (sizeof(ATIFramebuffers_post) / sizeof(ATIFramebuffers_post[0])); i++) + { + if (ATIFramebuffers_post[i].device == id) + { + verbose("Framebuffer ( >= 10.6.8): %s\n", ATIFramebuffers_post[i].name); + return ATIFramebuffers_post[i].name; + } + } + verbose("Framebuffer (default post): %s\n", ATIFramebuffers_post[0].name); + return ATIFramebuffers_post[0].name; + } + else + { + for (i = 0; i < (sizeof(ATIFramebuffers_pre) / sizeof(ATIFramebuffers_pre[0])); i++) + { + if (ATIFramebuffers_pre[i].device == id) + { + verbose("Framebuffer ( <= 10.6.7): %s\n", ATIFramebuffers_pre[i].name); + return ATIFramebuffers_pre[i].name; + } + } + verbose("Framebuffer (default): %s\n", ATIFramebuffers_pre[0].name); + return ATIFramebuffers_pre[0].name; + } +} + +static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev) +{ + int i; + uint8_t *config_space; + + if (!device || !ati_dev) { + return 0; + } + verbose("dumping pci config space, 256 bytes\n"); + config_space = malloc(256); + for (i=0; i<=255; i++) { + config_space[i] = pci_config_read8( ati_dev->dev.addr, i); + } + devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256); + free (config_space); + return 1; +} + +static int devprop_add_ati_template_4xxx(struct DevPropDevice *device) +{ + if(!device) + return 0; + +// if(!DP_ADD_TEMP_VAL(device, ati_compatible_0)) +// return 0; +// if(!DP_ADD_TEMP_VAL(device, ati_compatible_1)) +// return 0; + if(!DP_ADD_TEMP_VAL(device, ati_device_type_0)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_device_type_1)) + return 0; +// if(!DP_ADD_TEMP_VAL(device, ati_device_type)) +// return 0; +// if(!DP_ADD_TEMP_VAL(device, ati_name_0)) +// return 0; +// if(!DP_ADD_TEMP_VAL(device, ati_name_1)) +// return 0; +// if(!DP_ADD_TEMP_VAL(device, ati_name)) +// return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_display_type_0)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_display_type_1)) + return 0; +// if(!DP_ADD_TEMP_VAL(device, ati_slot_name)) +// return 0; + if(!DP_ADD_TEMP_VAL(device, ati_card_no)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_copyright)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_version)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_mrt)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_romno)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_name_1)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config)) + return 0; + return 1; +} + +static int devprop_add_ati_template(struct DevPropDevice *device) +{ + if(!device) + return 0; + + if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_device_type_0)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_device_type_1)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4)) + return 0; +// if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4)) +// return 0; + if(!DP_ADD_TEMP_VAL(device, ati_card_no)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_copyright)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_version)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_mrt)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_romno)) + return 0; + if(!DP_ADD_TEMP_VAL(device, ati_name_1)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4)) + return 0; + if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4)) + return 0; + return 1; +} + +bool setup_ati_devprop(pci_dt_t *ati_dev) +{ + struct DevPropDevice *device; + char *devicepath; + char *model; + const char *framebuffer; + char tmp[64]; + uint8_t *rom = NULL; + uint32_t rom_size = 0; + option_rom_pci_header_t *rom_pci_header; + uint8_t *bios; + uint32_t bios_size; + uint32_t vram_size; + uint32_t boot_display; + uint8_t cmd; + bool doit; + bool toFree; + + devicepath = get_pci_dev_path(ati_dev); + + cmd = pci_config_read8(ati_dev->dev.addr, 4); + verbose("old pci command - %x\n", cmd); + if (cmd == 0) { + pci_config_write8(ati_dev->dev.addr, 4, 6); + cmd = pci_config_read8(ati_dev->dev.addr, 4); + verbose("new pci command - %x\n", cmd); + } + + model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id); + framebuffer = getStringForKey(kAtiConfig, &bootInfo->bootConfig); + + if (framebuffer == 0) + { + framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id); + } + else + { + verbose("(AtiConfig) Framebuffer set to: %s\n", framebuffer); + } + + if (!string) { + string = devprop_create_string(); + } + device = devprop_add_device(string, devicepath); + if (!device) { + printf("Failed initializing dev-prop string dev-entry, press any key...\n"); + getchar(); + return false; + } + + /* FIXME: for primary graphics card only */ + if (radeon_card_posted(ati_dev)) { + boot_display = 1; + } else { + boot_display = 0; + } + verbose("boot display - %x\n", boot_display); + devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4); + + if ((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') || + (framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') || + (framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;) + devprop_add_ati_template_4xxx(device); + else { + devprop_add_ati_template(device); + vram_size = getvramsizekb(ati_dev) * 1024; + if ((vram_size > 0x80000000) || (vram_size == 0)) { + vram_size = 0x10000000; //vram reported wrong, defaulting to 256 mb + } + devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4); + ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway + ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF; + ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway + ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF; + DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0); + DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1); + devprop_add_iopciconfigspace(device, ati_dev); + } + devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1)); + devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2); + + //fb setup + sprintf(tmp, "Slot-%x",devices_number); + devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1); + devices_number++; + + sprintf(tmp, ati_compatible_0[1], framebuffer); + devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1); + + sprintf(tmp, ati_compatible_1[1], framebuffer); + devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1); + + sprintf(tmp, ati_device_type[1], framebuffer); + devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1); + + sprintf(tmp, ati_name[1], framebuffer); + devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1); + + sprintf(tmp, ati_name_0[1], framebuffer); + devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1); + + sprintf(tmp, ati_name_1[1], framebuffer); + devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1); + + sprintf(tmp, "bt(0,0)/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id); + if (getBoolForKey(kUseAtiROMKey, &doit, &bootInfo->chameleonConfig) && doit) { + verbose("looking for ati video bios file %s\n", tmp); + rom = malloc(0x20000); + rom_size = load_ati_bios_file(tmp, rom, 0x20000); + if (rom_size > 0) { + verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size); + if (rom_size > 0x10000) { + rom_size = 0x10000; //we dont need rest anyway; + } + } else { + printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp); + } + } + if (rom_size == 0) { + if (boot_display) { // no custom rom + bios = NULL; // try to dump from legacy space, otherwise can result in 100% fan speed + } else { + // readAtomBios result in bug on some cards (100% fan speed and black screen), + // not using it for posted card, reading from legacy space instead + bios = readAtomBIOS(ati_dev); + } + } else { + bios = rom; //going custom rom way + verbose("Using rom %s\n", tmp); + } + if (bios == NULL) { + bios = (uint8_t *)0x000C0000; + toFree = false; + verbose("Not going to use bios image file\n"); + } else { + toFree = true; + } + + if (bios[0] == 0x55 && bios[1] == 0xaa) { + verbose("Found bios image\n"); + bios_size = bios[2] * 512; + + rom_pci_header = (option_rom_pci_header_t*)(bios + bios[24] + bios[25]*256); + + if (rom_pci_header->signature == 0x52494350) { + if (rom_pci_header->device_id != ati_dev->device_id) { + verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device_id, ati_dev->device_id); + } else { + if (toFree) + { + verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size); + } else { + verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size); + } + devprop_add_value(device, "ATY,bin_image", bios, bios_size); + } + } else { + verbose("Wrong pci header signature %x\n", rom_pci_header->signature); + } + } else { + verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]); + } + if (toFree) { + free(bios); + } + stringdata = malloc(sizeof(uint8_t) * string->length); + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + + return true; +} Index: branches/ErmaC/i386/modules/Cconfig =================================================================== --- branches/ErmaC/i386/modules/Cconfig (revision 1567) +++ branches/ErmaC/i386/modules/Cconfig (revision 1568) @@ -8,4 +8,8 @@ source "i386/modules/uClibcxx/Cconfig" source "i386/modules/HelloWorld/Cconfig" source "i386/modules/Keylayout/Cconfig" +source "i386/modules/AMDGraphicsEnabler/Cconfig" +source "i386/modules/ATiGraphicsEnabler/Cconfig" +source "i386/modules/IntelGraphicsEnabler/Cconfig" +source "i386/modules/NVIDIAGraphicsEnabler/Cconfig" endmenu Index: branches/ErmaC/i386/modules/AMDGraphicsEnabler/ati_reg.h =================================================================== --- branches/ErmaC/i386/modules/AMDGraphicsEnabler/ati_reg.h (revision 0) +++ branches/ErmaC/i386/modules/AMDGraphicsEnabler/ati_reg.h (revision 1568) @@ -0,0 +1,5664 @@ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * !!!! FIXME !!!! + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + */ + +/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h + * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT + * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ + +#ifndef _ATI_REG_H_ +#define _ATI_REG_H_ + +#define ATI_DATATYPE_VQ 0 +#define ATI_DATATYPE_CI4 1 +#define ATI_DATATYPE_CI8 2 +#define ATI_DATATYPE_ARGB1555 3 +#define ATI_DATATYPE_RGB565 4 +#define ATI_DATATYPE_RGB888 5 +#define ATI_DATATYPE_ARGB8888 6 +#define ATI_DATATYPE_RGB332 7 +#define ATI_DATATYPE_Y8 8 +#define ATI_DATATYPE_RGB8 9 +#define ATI_DATATYPE_CI16 10 +#define ATI_DATATYPE_VYUY_422 11 +#define ATI_DATATYPE_YVYU_422 12 +#define ATI_DATATYPE_AYUV_444 14 +#define ATI_DATATYPE_ARGB4444 15 + +/* Registers for 2D/Video/Overlay */ +#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ +#define RADEON_AGP_BASE 0x0170 +#define RADEON_AGP_CNTL 0x0174 +#define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) +#define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) +#define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) +#define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) +#define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) +#define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) +#define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) +#define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) +#define RADEON_STATUS_PCI_CONFIG 0x06 +#define RADEON_CAP_LIST 0x100000 +#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ +#define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ +#define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ +#define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ +#define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ +#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ +#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +#define RADEON_AGP_ENABLE (1 << 8) +#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ +#define RADEON_AGP_STATUS 0x0f5c /* PCI */ +#define RADEON_AGP_1X_MODE 0x01 +#define RADEON_AGP_2X_MODE 0x02 +#define RADEON_AGP_4X_MODE 0x04 +#define RADEON_AGP_FW_MODE 0x10 +#define RADEON_AGP_MODE_MASK 0x17 +#define RADEON_AGPv3_MODE 0x08 +#define RADEON_AGPv3_4X_MODE 0x01 +#define RADEON_AGPv3_8X_MODE 0x02 +#define RADEON_ATTRDR 0x03c1 /* VGA */ +#define RADEON_ATTRDW 0x03c0 /* VGA */ +#define RADEON_ATTRX 0x03c0 /* VGA */ +#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 +#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc + +#define RADEON_BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_FP_PANEL_SCALABLE (1 << 16) +#define RADEON_FP_PANEL_SCALE_EN (1 << 17) +#define RADEON_FP_CHIP_SCALE_EN (1 << 18) +#define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) +#define RADEON_DISPLAY_ROT_MASK (3 << 28) +#define RADEON_DISPLAY_ROT_00 (0 << 28) +#define RADEON_DISPLAY_ROT_90 (1 << 28) +#define RADEON_DISPLAY_ROT_180 (2 << 28) +#define RADEON_DISPLAY_ROT_270 (3 << 28) +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_CRT1_ATTACHED_MASK (3 << 0) +#define RADEON_CRT1_ATTACHED_MONO (1 << 0) +#define RADEON_CRT1_ATTACHED_COLOR (2 << 0) +#define RADEON_LCD1_ATTACHED (1 << 2) +#define RADEON_DFP1_ATTACHED (1 << 3) +#define RADEON_TV1_ATTACHED_MASK (3 << 4) +#define RADEON_TV1_ATTACHED_COMP (1 << 4) +#define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) +#define RADEON_CRT2_ATTACHED_MASK (3 << 8) +#define RADEON_CRT2_ATTACHED_MONO (1 << 8) +#define RADEON_CRT2_ATTACHED_COLOR (2 << 8) +#define RADEON_DFP2_ATTACHED (1 << 11) +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_LCD1_ON (1 << 0) +#define RADEON_CRT1_ON (1 << 1) +#define RADEON_TV1_ON (1 << 2) +#define RADEON_DFP1_ON (1 << 3) +#define RADEON_CRT2_ON (1 << 5) +#define RADEON_CV1_ON (1 << 6) +#define RADEON_DFP2_ON (1 << 7) +#define RADEON_LCD1_CRTC_MASK (1 << 8) +#define RADEON_LCD1_CRTC_SHIFT 8 +#define RADEON_CRT1_CRTC_MASK (1 << 9) +#define RADEON_CRT1_CRTC_SHIFT 9 +#define RADEON_TV1_CRTC_MASK (1 << 10) +#define RADEON_TV1_CRTC_SHIFT 10 +#define RADEON_DFP1_CRTC_MASK (1 << 11) +#define RADEON_DFP1_CRTC_SHIFT 11 +#define RADEON_CRT2_CRTC_MASK (1 << 12) +#define RADEON_CRT2_CRTC_SHIFT 12 +#define RADEON_CV1_CRTC_MASK (1 << 13) +#define RADEON_CV1_CRTC_SHIFT 13 +#define RADEON_DFP2_CRTC_MASK (1 << 14) +#define RADEON_DFP2_CRTC_SHIFT 14 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_ACC_MODE_CHANGE (1 << 2) +#define RADEON_EXT_DESKTOP_MODE (1 << 3) +#define RADEON_LCD_DPMS_ON (1 << 20) +#define RADEON_CRT_DPMS_ON (1 << 21) +#define RADEON_TV_DPMS_ON (1 << 22) +#define RADEON_DFP_DPMS_ON (1 << 23) +#define RADEON_DPMS_MASK (3 << 24) +#define RADEON_DPMS_ON (0 << 24) +#define RADEON_DPMS_STANDBY (1 << 24) +#define RADEON_DPMS_SUSPEND (2 << 24) +#define RADEON_DPMS_OFF (3 << 24) +#define RADEON_SCREEN_BLANKING (1 << 26) +#define RADEON_DRIVER_CRITICAL (1 << 27) +#define RADEON_DISPLAY_SWITCHING_DI (1 << 30) +#define RADEON_BIOS_7_SCRATCH 0x002c +#define RADEON_SYS_HOTKEY (1 << 10) +#define RADEON_DRV_LOADED (1 << 12) +#define RADEON_BIOS_ROM 0x0f30 /* PCI */ +#define RADEON_BIST 0x0f0f /* PCI */ +#define RADEON_BRUSH_DATA0 0x1480 +#define RADEON_BRUSH_DATA1 0x1484 +#define RADEON_BRUSH_DATA10 0x14a8 +#define RADEON_BRUSH_DATA11 0x14ac +#define RADEON_BRUSH_DATA12 0x14b0 +#define RADEON_BRUSH_DATA13 0x14b4 +#define RADEON_BRUSH_DATA14 0x14b8 +#define RADEON_BRUSH_DATA15 0x14bc +#define RADEON_BRUSH_DATA16 0x14c0 +#define RADEON_BRUSH_DATA17 0x14c4 +#define RADEON_BRUSH_DATA18 0x14c8 +#define RADEON_BRUSH_DATA19 0x14cc +#define RADEON_BRUSH_DATA2 0x1488 +#define RADEON_BRUSH_DATA20 0x14d0 +#define RADEON_BRUSH_DATA21 0x14d4 +#define RADEON_BRUSH_DATA22 0x14d8 +#define RADEON_BRUSH_DATA23 0x14dc +#define RADEON_BRUSH_DATA24 0x14e0 +#define RADEON_BRUSH_DATA25 0x14e4 +#define RADEON_BRUSH_DATA26 0x14e8 +#define RADEON_BRUSH_DATA27 0x14ec +#define RADEON_BRUSH_DATA28 0x14f0 +#define RADEON_BRUSH_DATA29 0x14f4 +#define RADEON_BRUSH_DATA3 0x148c +#define RADEON_BRUSH_DATA30 0x14f8 +#define RADEON_BRUSH_DATA31 0x14fc +#define RADEON_BRUSH_DATA32 0x1500 +#define RADEON_BRUSH_DATA33 0x1504 +#define RADEON_BRUSH_DATA34 0x1508 +#define RADEON_BRUSH_DATA35 0x150c +#define RADEON_BRUSH_DATA36 0x1510 +#define RADEON_BRUSH_DATA37 0x1514 +#define RADEON_BRUSH_DATA38 0x1518 +#define RADEON_BRUSH_DATA39 0x151c +#define RADEON_BRUSH_DATA4 0x1490 +#define RADEON_BRUSH_DATA40 0x1520 +#define RADEON_BRUSH_DATA41 0x1524 +#define RADEON_BRUSH_DATA42 0x1528 +#define RADEON_BRUSH_DATA43 0x152c +#define RADEON_BRUSH_DATA44 0x1530 +#define RADEON_BRUSH_DATA45 0x1534 +#define RADEON_BRUSH_DATA46 0x1538 +#define RADEON_BRUSH_DATA47 0x153c +#define RADEON_BRUSH_DATA48 0x1540 +#define RADEON_BRUSH_DATA49 0x1544 +#define RADEON_BRUSH_DATA5 0x1494 +#define RADEON_BRUSH_DATA50 0x1548 +#define RADEON_BRUSH_DATA51 0x154c +#define RADEON_BRUSH_DATA52 0x1550 +#define RADEON_BRUSH_DATA53 0x1554 +#define RADEON_BRUSH_DATA54 0x1558 +#define RADEON_BRUSH_DATA55 0x155c +#define RADEON_BRUSH_DATA56 0x1560 +#define RADEON_BRUSH_DATA57 0x1564 +#define RADEON_BRUSH_DATA58 0x1568 +#define RADEON_BRUSH_DATA59 0x156c +#define RADEON_BRUSH_DATA6 0x1498 +#define RADEON_BRUSH_DATA60 0x1570 +#define RADEON_BRUSH_DATA61 0x1574 +#define RADEON_BRUSH_DATA62 0x1578 +#define RADEON_BRUSH_DATA63 0x157c +#define RADEON_BRUSH_DATA7 0x149c +#define RADEON_BRUSH_DATA8 0x14a0 +#define RADEON_BRUSH_DATA9 0x14a4 +#define RADEON_BRUSH_SCALE 0x1470 +#define RADEON_BRUSH_Y_X 0x1474 +#define RADEON_BUS_CNTL 0x0030 +#define RADEON_BUS_MASTER_DIS (1 << 6) +#define RADEON_BUS_BIOS_DIS_ROM (1 << 12) +#define RADEON_BUS_RD_DISCARD_EN (1 << 24) +#define RADEON_BUS_RD_ABORT_EN (1 << 25) +#define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) +#define RADEON_BUS_WRT_BURST (1 << 29) +#define RADEON_BUS_READ_BURST (1 << 30) +#define RADEON_BUS_CNTL1 0x0034 +#define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) + +#define RADEON_PCIE_INDEX 0x0030 +#define RADEON_PCIE_DATA 0x0034 +#define R600_PCIE_PORT_INDEX 0x0038 +#define R600_PCIE_PORT_DATA 0x003c +/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */ +#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */ +#define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0 +#define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7 +#define RADEON_PCIE_LC_LINK_WIDTH_X0 0 +#define RADEON_PCIE_LC_LINK_WIDTH_X1 1 +#define RADEON_PCIE_LC_LINK_WIDTH_X2 2 +#define RADEON_PCIE_LC_LINK_WIDTH_X4 3 +#define RADEON_PCIE_LC_LINK_WIDTH_X8 4 +#define RADEON_PCIE_LC_LINK_WIDTH_X12 5 +#define RADEON_PCIE_LC_LINK_WIDTH_X16 6 +#define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 +#define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 +#define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) +#define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) +#define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) +#define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) +#define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10) +#define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11) +#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c +#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c + +#define RADEON_CACHE_CNTL 0x1724 +#define RADEON_CACHE_LINE 0x0f0c /* PCI */ +#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ +#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ +#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ +#define RADEON_DONT_USE_XTALIN (1 << 4) +#define RADEON_SCLK_DYN_START_CNTL (1 << 15) +#define RADEON_CLOCK_CNTL_DATA 0x000c +#define RADEON_CLOCK_CNTL_INDEX 0x0008 +#define RADEON_PLL_WR_EN (1 << 7) +#define RADEON_PLL_DIV_SEL (3 << 8) +#define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) +#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */ +#define RADEON_M_SPLL_REF_DIV_MASK 0xff +#define RADEON_M_SPLL_REF_DIV_SHIFT 0 +#define RADEON_MPLL_FB_DIV_MASK 0xff +#define RADEON_MPLL_FB_DIV_SHIFT 8 +#define RADEON_SPLL_FB_DIV_MASK 0xff +#define RADEON_SPLL_FB_DIV_SHIFT 16 +#define RADEON_SPLL_CNTL 0x000c /* PLL */ +#define RADEON_SPLL_SLEEP (1 << 0) +#define RADEON_SPLL_RESET (1 << 1) +#define RADEON_SPLL_PCP_MASK 0x7 +#define RADEON_SPLL_PCP_SHIFT 8 +#define RADEON_SPLL_PVG_MASK 0x7 +#define RADEON_SPLL_PVG_SHIFT 11 +#define RADEON_SPLL_PDC_MASK 0x3 +#define RADEON_SPLL_PDC_SHIFT 14 +#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */ +#define RADEON_ENGIN_DYNCLK_MODE (1 << 12) +#define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) +#define RADEON_ACTIVE_HILO_LAT_SHIF 13 +#define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) +#define RADEON_MC_BUSY (1 << 16) +#define RADEON_DLL_READY (1 << 19) +#define RADEON_CG_NO1_DEBUG_0 (1 << 24) +#define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) +#define RADEON_DYN_STOP_MODE_MASK (7 << 21) +#define RADEON_TVPLL_PWRMGT_OFF (1 << 30) +#define RADEON_TVCLK_TURNOFF (1 << 31) +#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ +#define RADEON_TCL_BYPASS_DISABLE (1 << 20) +#define RADEON_CLR_CMP_CLR_3D 0x1a24 +#define RADEON_CLR_CMP_CLR_DST 0x15c8 +#define RADEON_CLR_CMP_CLR_SRC 0x15c4 +#define RADEON_CLR_CMP_CNTL 0x15c0 +#define RADEON_SRC_CMP_EQ_COLOR (4 << 0) +#define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) +#define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) +#define RADEON_CLR_CMP_MASK 0x15cc +#define RADEON_CLR_CMP_MSK 0xffffffff +#define RADEON_CLR_CMP_MASK_3D 0x1A28 +#define RADEON_COMMAND 0x0f04 /* PCI */ +#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c +#define RADEON_CONFIG_APER_0_BASE 0x0100 +#define RADEON_CONFIG_APER_1_BASE 0x0104 +#define RADEON_CONFIG_APER_SIZE 0x0108 +#define RADEON_CONFIG_BONDS 0x00e8 +#define RADEON_CONFIG_CNTL 0x00e0 +#define RADEON_CFG_ATI_REV_A11 (0 << 16) +#define RADEON_CFG_ATI_REV_A12 (1 << 16) +#define RADEON_CFG_ATI_REV_A13 (2 << 16) +#define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) +#define RADEON_CONFIG_MEMSIZE 0x00f8 +#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 +#define RADEON_CONFIG_REG_1_BASE 0x010c +#define RADEON_CONFIG_REG_APER_SIZE 0x0110 +#define RADEON_CONFIG_XSTRAP 0x00e4 +#define RADEON_CONSTANT_COLOR_C 0x1d34 +#define RADEON_CONSTANT_COLOR_MASK 0x00ffffff +#define RADEON_CONSTANT_COLOR_ONE 0x00ffffff +#define RADEON_CONSTANT_COLOR_ZERO 0x00000000 +#define RADEON_CRC_CMDFIFO_ADDR 0x0740 +#define RADEON_CRC_CMDFIFO_DOUT 0x0744 +#define RADEON_GRPH_BUFFER_CNTL 0x02f0 +#define RADEON_GRPH_START_REQ_MASK (0x7f) +#define RADEON_GRPH_START_REQ_SHIFT 0 +#define RADEON_GRPH_STOP_REQ_MASK (0x7f << 8) +#define RADEON_GRPH_STOP_REQ_SHIFT 8 +#define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f << 16) +#define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 +#define RADEON_GRPH_CRITICAL_CNTL (1 << 28) +#define RADEON_GRPH_BUFFER_SIZE (1 << 29) +#define RADEON_GRPH_CRITICAL_AT_SOF (1 << 30) +#define RADEON_GRPH_STOP_CNTL (1 << 31) +#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 +#define RADEON_GRPH2_START_REQ_MASK (0x7f) +#define RADEON_GRPH2_START_REQ_SHIFT 0 +#define RADEON_GRPH2_STOP_REQ_MASK (0x7f << 8) +#define RADEON_GRPH2_STOP_REQ_SHIFT 8 +#define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f << 16) +#define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 +#define RADEON_GRPH2_CRITICAL_CNTL (1 << 28) +#define RADEON_GRPH2_BUFFER_SIZE (1 << 29) +#define RADEON_GRPH2_CRITICAL_AT_SOF (1 << 30) +#define RADEON_GRPH2_STOP_CNTL (1 << 31) +#define RADEON_CRTC_CRNT_FRAME 0x0214 +#define RADEON_CRTC_EXT_CNTL 0x0054 +#define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) +#define RADEON_VGA_ATI_LINEAR (1 << 3) +#define RADEON_XCRT_CNT_EN (1 << 6) +#define RADEON_CRTC_HSYNC_DIS (1 << 8) +#define RADEON_CRTC_VSYNC_DIS (1 << 9) +#define RADEON_CRTC_DISPLAY_DIS (1 << 10) +#define RADEON_CRTC_SYNC_TRISTAT (1 << 11) +#define RADEON_CRTC_CRT_ON (1 << 15) +#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +#define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) +#define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) +#define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RADEON_CRTC_GEN_CNTL 0x0050 +#define RADEON_CRTC_DBL_SCAN_EN (1 << 0) +#define RADEON_CRTC_INTERLACE_EN (1 << 1) +#define RADEON_CRTC_CSYNC_EN (1 << 4) +#define RADEON_CRTC_ICON_EN (1 << 15) +#define RADEON_CRTC_CUR_EN (1 << 16) +#define RADEON_CRTC_CUR_MODE_MASK (7 << 20) +#define RADEON_CRTC_EXT_DISP_EN (1 << 24) +#define RADEON_CRTC_EN (1 << 25) +#define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) +#define RADEON_CRTC2_GEN_CNTL 0x03f8 +#define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) +#define RADEON_CRTC2_INTERLACE_EN (1 << 1) +#define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) +#define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) +#define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) +#define RADEON_CRTC2_CRT2_ON (1 << 7) +#define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 +#define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) +#define RADEON_CRTC2_ICON_EN (1 << 15) +#define RADEON_CRTC2_CUR_EN (1 << 16) +#define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) +#define RADEON_CRTC2_DISP_DIS (1 << 23) +#define RADEON_CRTC2_EN (1 << 25) +#define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) +#define RADEON_CRTC2_CSYNC_EN (1 << 27) +#define RADEON_CRTC2_HSYNC_DIS (1 << 28) +#define RADEON_CRTC2_VSYNC_DIS (1 << 29) +#define RADEON_CRTC_MORE_CNTL 0x27c +#define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) +#define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) +#define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +#define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 +#define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0 +#define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15) +#define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16 +#define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30) +#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 +#define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) +#define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +#define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +#define RADEON_CRTC_H_SYNC_WID (0x3f << 16) +#define RADEON_CRTC_H_SYNC_WID_SHIFT 16 +#define RADEON_CRTC_H_SYNC_POL (1 << 23) +#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 +#define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +#define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +#define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +#define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) +#define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 +#define RADEON_CRTC2_H_SYNC_POL (1 << 23) +#define RADEON_CRTC_H_TOTAL_DISP 0x0200 +#define RADEON_CRTC_H_TOTAL (0x03ff << 0) +#define RADEON_CRTC_H_TOTAL_SHIFT 0 +#define RADEON_CRTC_H_DISP (0x01ff << 16) +#define RADEON_CRTC_H_DISP_SHIFT 16 +#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 +#define RADEON_CRTC2_H_TOTAL (0x03ff << 0) +#define RADEON_CRTC2_H_TOTAL_SHIFT 0 +#define RADEON_CRTC2_H_DISP (0x01ff << 16) +#define RADEON_CRTC2_H_DISP_SHIFT 16 + +#define RADEON_CRTC_OFFSET_RIGHT 0x0220 +#define RADEON_CRTC_OFFSET 0x0224 +#define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1 << 30) +#define RADEON_CRTC_OFFSET__OFFSET_LOCK (1 << 31) + +#define RADEON_CRTC2_OFFSET 0x0324 +#define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1 << 30) +#define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1 << 31) +#define RADEON_CRTC_OFFSET_CNTL 0x0228 +#define RADEON_CRTC_TILE_LINE_SHIFT 0 +#define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 +#define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) +#define R300_CRTC_X_Y_MODE_EN (1 << 9) +#define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) +#define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) +#define R300_CRTC_MICRO_TILE_EN (1 << 13) +#define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) +#define R300_CRTC_MACRO_TILE_EN (1 << 15) +#define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) +#define RADEON_CRTC_TILE_EN (1 << 15) +#define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) +#define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) + +#define R300_CRTC_TILE_X0_Y0 0x0350 +#define R300_CRTC2_TILE_X0_Y0 0x0358 + +#define RADEON_CRTC2_OFFSET_CNTL 0x0328 +#define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) +#define RADEON_CRTC2_TILE_EN (1 << 15) +#define RADEON_CRTC_PITCH 0x022c +#define RADEON_CRTC_PITCH__SHIFT 0 +#define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 + +#define RADEON_CRTC2_PITCH 0x032c +#define RADEON_CRTC_STATUS 0x005c +#define RADEON_CRTC_VBLANK_SAVE (1 << 1) +#define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC2_STATUS 0x03fc +#define RADEON_CRTC2_VBLANK_SAVE (1 << 1) +#define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c +#define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) +#define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 +#define RADEON_CRTC_V_SYNC_WID (0x1f << 16) +#define RADEON_CRTC_V_SYNC_WID_SHIFT 16 +#define RADEON_CRTC_V_SYNC_POL (1 << 23) +#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c +#define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) +#define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 +#define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) +#define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 +#define RADEON_CRTC2_V_SYNC_POL (1 << 23) +#define RADEON_CRTC_V_TOTAL_DISP 0x0208 +#define RADEON_CRTC_V_TOTAL (0x07ff << 0) +#define RADEON_CRTC_V_TOTAL_SHIFT 0 +#define RADEON_CRTC_V_DISP (0x07ff << 16) +#define RADEON_CRTC_V_DISP_SHIFT 16 +#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 +#define RADEON_CRTC2_V_TOTAL (0x07ff << 0) +#define RADEON_CRTC2_V_TOTAL_SHIFT 0 +#define RADEON_CRTC2_V_DISP (0x07ff << 16) +#define RADEON_CRTC2_V_DISP_SHIFT 16 +#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 +#define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define RADEON_CRTC2_CRNT_FRAME 0x0314 +#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 +#define RADEON_CRTC2_STATUS 0x03fc +#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 +#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ +#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ +#define RADEON_CUR_CLR0 0x026c +#define RADEON_CUR_CLR1 0x0270 +#define RADEON_CUR_HORZ_VERT_OFF 0x0268 +#define RADEON_CUR_HORZ_VERT_POSN 0x0264 +#define RADEON_CUR_OFFSET 0x0260 +#define RADEON_CUR_LOCK (1 << 31) +#define RADEON_CUR2_CLR0 0x036c +#define RADEON_CUR2_CLR1 0x0370 +#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 +#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 +#define RADEON_CUR2_OFFSET 0x0360 +#define RADEON_CUR2_LOCK (1 << 31) + +#define RADEON_DAC_CNTL 0x0058 +#define RADEON_DAC_RANGE_CNTL (3 << 0) +#define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) +#define RADEON_DAC_RANGE_CNTL_MASK 0x03 +#define RADEON_DAC_BLANKING (1 << 2) +#define RADEON_DAC_CMP_EN (1 << 3) +#define RADEON_DAC_CMP_OUTPUT (1 << 7) +#define RADEON_DAC_8BIT_EN (1 << 8) +#define RADEON_DAC_TVO_EN (1 << 10) +#define RADEON_DAC_VGA_ADR_EN (1 << 13) +#define RADEON_DAC_PDWN (1 << 15) +#define RADEON_DAC_MASK_ALL (0xff << 24) +#define RADEON_DAC_CNTL2 0x007c +#define RADEON_DAC2_TV_CLK_SEL (0 << 1) +#define RADEON_DAC2_DAC_CLK_SEL (1 << 0) +#define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) +#define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) +#define RADEON_DAC2_CMP_EN (1 << 7) +#define RADEON_DAC2_CMP_OUT_R (1 << 8) +#define RADEON_DAC2_CMP_OUT_G (1 << 9) +#define RADEON_DAC2_CMP_OUT_B (1 << 10) +#define RADEON_DAC2_CMP_OUTPUT (1 << 11) +#define RADEON_DAC_EXT_CNTL 0x0280 +#define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) +#define RADEON_DAC2_FORCE_DATA_EN (1 << 1) +#define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) +#define RADEON_DAC_FORCE_DATA_EN (1 << 5) +#define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) +#define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) +#define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) +#define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) +#define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) +#define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 +#define RADEON_DAC_FORCE_DATA_SHIFT 8 +#define RADEON_DAC_MACRO_CNTL 0x0d04 +#define RADEON_DAC_PDWN_R (1 << 16) +#define RADEON_DAC_PDWN_G (1 << 17) +#define RADEON_DAC_PDWN_B (1 << 18) +#define RADEON_TV_DAC_CNTL 0x088c +#define RADEON_TV_DAC_NBLANK (1 << 0) +#define RADEON_TV_DAC_NHOLD (1 << 1) +#define RADEON_TV_DAC_PEDESTAL (1 << 2) +#define RADEON_TV_MONITOR_DETECT_EN (1 << 4) +#define RADEON_TV_DAC_CMPOUT (1 << 5) +#define RADEON_TV_DAC_STD_MASK (3 << 8) +#define RADEON_TV_DAC_STD_PAL (0 << 8) +#define RADEON_TV_DAC_STD_NTSC (1 << 8) +#define RADEON_TV_DAC_STD_PS2 (2 << 8) +#define RADEON_TV_DAC_STD_RS343 (3 << 8) +#define RADEON_TV_DAC_BGSLEEP (1 << 6) +#define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) +#define RADEON_TV_DAC_BGADJ_SHIFT 16 +#define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) +#define RADEON_TV_DAC_DACADJ_SHIFT 20 +#define RADEON_TV_DAC_RDACPD (1 << 24) +#define RADEON_TV_DAC_GDACPD (1 << 25) +#define RADEON_TV_DAC_BDACPD (1 << 26) +#define RADEON_TV_DAC_RDACDET (1 << 29) +#define RADEON_TV_DAC_GDACDET (1 << 30) +#define RADEON_TV_DAC_BDACDET (1 << 31) +#define R420_TV_DAC_DACADJ_MASK (0x1f << 20) +#define R420_TV_DAC_RDACPD (1 << 25) +#define R420_TV_DAC_GDACPD (1 << 26) +#define R420_TV_DAC_BDACPD (1 << 27) +#define R420_TV_DAC_TVENABLE (1 << 28) +#define RADEON_DISP_HW_DEBUG 0x0d14 +#define RADEON_CRT2_DISP1_SEL (1 << 5) +#define RADEON_DISP_OUTPUT_CNTL 0x0d64 +#define RADEON_DISP_DAC_SOURCE_MASK 0x03 +#define RADEON_DISP_DAC2_SOURCE_MASK 0x0c +#define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 +#define RADEON_DISP_DAC_SOURCE_RMX 0x02 +#define RADEON_DISP_DAC_SOURCE_LTU 0x03 +#define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 +#define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) +#define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 +#define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) +#define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) +#define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) +#define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) +#define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) +#define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) +#define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) +#define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ +#define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ +#define RADEON_DISP_TV_OUT_CNTL 0x0d6c +#define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) +#define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) +#define RADEON_DAC_CRC_SIG 0x02cc +#define RADEON_DAC_DATA 0x03c9 /* VGA */ +#define RADEON_DAC_MASK 0x03c6 /* VGA */ +#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ +#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ +#define RADEON_DDA_CONFIG 0x02e0 +#define RADEON_DDA_ON_OFF 0x02e4 +#define RADEON_DEFAULT_OFFSET 0x16e0 +#define RADEON_DEFAULT_PITCH 0x16e4 +#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +#define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +#define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 +#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 +#define RADEON_DEVICE_ID 0x0f02 /* PCI */ +#define RADEON_DISP_MISC_CNTL 0x0d00 +#define RADEON_SOFT_RESET_GRPH_PP (1 << 0) +#define RADEON_DISP_MERGE_CNTL 0x0d60 +#define RADEON_DISP_ALPHA_MODE_MASK 0x03 +#define RADEON_DISP_ALPHA_MODE_KEY 0 +#define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 +#define RADEON_DISP_ALPHA_MODE_GLOBAL 2 +#define RADEON_DISP_RGB_OFFSET_EN (1 << 8) +#define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) +#define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) +#define RADEON_DISP_LIN_TRANS_BYPAS (0x01 << 9) +#define RADEON_DISP2_MERGE_CNTL 0x0d68 +#define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) +#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 +#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 +#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 +#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c +#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 +#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 +#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 +#define RADEON_DP_BRUSH_FRGD_CLR 0x147c +#define RADEON_DP_CNTL 0x16c0 +#define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) +#define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) +#define RADEON_DP_DST_TILE_LINEAR (0 << 3) +#define RADEON_DP_DST_TILE_MACRO (1 << 3) +#define RADEON_DP_DST_TILE_MICRO (2 << 3) +#define RADEON_DP_DST_TILE_BOTH (3 << 3) +#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +#define RADEON_DST_Y_MAJOR (1 << 2) +#define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) +#define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) +#define RADEON_DP_DATATYPE 0x16c4 +#define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) +#define RADEON_DP_GUI_MASTER_CNTL 0x146c +#define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +#define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +#define RADEON_GMC_SRC_CLIPPING (1 << 2) +#define RADEON_GMC_DST_CLIPPING (1 << 3) +#define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +#define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +#define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +#define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +#define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +#define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) +#define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) +#define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) +#define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) +#define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) +#define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) +#define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +#define RADEON_GMC_BRUSH_NONE (15 << 4) +#define RADEON_GMC_DST_8BPP_CI (2 << 8) +#define RADEON_GMC_DST_15BPP (3 << 8) +#define RADEON_GMC_DST_16BPP (4 << 8) +#define RADEON_GMC_DST_24BPP (5 << 8) +#define RADEON_GMC_DST_32BPP (6 << 8) +#define RADEON_GMC_DST_8BPP_RGB (7 << 8) +#define RADEON_GMC_DST_Y8 (8 << 8) +#define RADEON_GMC_DST_RGB8 (9 << 8) +#define RADEON_GMC_DST_VYUY (11 << 8) +#define RADEON_GMC_DST_YVYU (12 << 8) +#define RADEON_GMC_DST_AYUV444 (14 << 8) +#define RADEON_GMC_DST_ARGB4444 (15 << 8) +#define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) +#define RADEON_GMC_DST_DATATYPE_SHIFT 8 +#define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) +#define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +#define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +#define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +#define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) +#define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) +#define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) +#define RADEON_GMC_CONVERSION_TEMP (1 << 15) +#define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) +#define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) +#define RADEON_GMC_ROP3_MASK (0xff << 16) +#define RADEON_DP_SRC_SOURCE_MASK (7 << 24) +#define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +#define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +#define RADEON_GMC_3D_FCN_EN (1 << 27) +#define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define RADEON_GMC_AUX_CLIP_DIS (1 << 29) +#define RADEON_GMC_WR_MSK_DIS (1 << 30) +#define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) +#define RADEON_ROP3_ZERO 0x00000000 +#define RADEON_ROP3_DSa 0x00880000 +#define RADEON_ROP3_SDna 0x00440000 +#define RADEON_ROP3_S 0x00cc0000 +#define RADEON_ROP3_DSna 0x00220000 +#define RADEON_ROP3_D 0x00aa0000 +#define RADEON_ROP3_DSx 0x00660000 +#define RADEON_ROP3_DSo 0x00ee0000 +#define RADEON_ROP3_DSon 0x00110000 +#define RADEON_ROP3_DSxn 0x00990000 +#define RADEON_ROP3_Dn 0x00550000 +#define RADEON_ROP3_SDno 0x00dd0000 +#define RADEON_ROP3_Sn 0x00330000 +#define RADEON_ROP3_DSno 0x00bb0000 +#define RADEON_ROP3_DSan 0x00770000 +#define RADEON_ROP3_ONE 0x00ff0000 +#define RADEON_ROP3_DPa 0x00a00000 +#define RADEON_ROP3_PDna 0x00500000 +#define RADEON_ROP3_P 0x00f00000 +#define RADEON_ROP3_DPna 0x000a0000 +#define RADEON_ROP3_D 0x00aa0000 +#define RADEON_ROP3_DPx 0x005a0000 +#define RADEON_ROP3_DPo 0x00fa0000 +#define RADEON_ROP3_DPon 0x00050000 +#define RADEON_ROP3_PDxn 0x00a50000 +#define RADEON_ROP3_PDno 0x00f50000 +#define RADEON_ROP3_Pn 0x000f0000 +#define RADEON_ROP3_DPno 0x00af0000 +#define RADEON_ROP3_DPan 0x005f0000 +#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 +#define RADEON_DP_MIX 0x16c8 +#define RADEON_DP_SRC_BKGD_CLR 0x15dc +#define RADEON_DP_SRC_FRGD_CLR 0x15d8 +#define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_DST_BRES_DEC 0x1630 +#define RADEON_DST_BRES_ERR 0x1628 +#define RADEON_DST_BRES_INC 0x162c +#define RADEON_DST_BRES_LNTH 0x1634 +#define RADEON_DST_BRES_LNTH_SUB 0x1638 +#define RADEON_DST_HEIGHT 0x1410 +#define RADEON_DST_HEIGHT_WIDTH 0x143c +#define RADEON_DST_HEIGHT_WIDTH_8 0x158c +#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 +#define RADEON_DST_HEIGHT_Y 0x15a0 +#define RADEON_DST_LINE_START 0x1600 +#define RADEON_DST_LINE_END 0x1604 +#define RADEON_DST_LINE_PATCOUNT 0x1608 +#define RADEON_BRES_CNTL_SHIFT 8 +#define RADEON_DST_OFFSET 0x1404 +#define RADEON_DST_PITCH 0x1408 +#define RADEON_DST_PITCH_OFFSET 0x142c +#define RADEON_DST_PITCH_OFFSET_C 0x1c80 +#define RADEON_PITCH_SHIFT 21 +#define RADEON_DST_TILE_LINEAR (0 << 30) +#define RADEON_DST_TILE_MACRO (1 << 30) +#define RADEON_DST_TILE_MICRO (2 << 30) +#define RADEON_DST_TILE_BOTH (3 << 30) +#define RADEON_DST_WIDTH 0x140c +#define RADEON_DST_WIDTH_HEIGHT 0x1598 +#define RADEON_DST_WIDTH_X 0x1588 +#define RADEON_DST_WIDTH_X_INCY 0x159c +#define RADEON_DST_X 0x141c +#define RADEON_DST_X_SUB 0x15a4 +#define RADEON_DST_X_Y 0x1594 +#define RADEON_DST_Y 0x1420 +#define RADEON_DST_Y_SUB 0x15a8 +#define RADEON_DST_Y_X 0x1438 + +#define RADEON_FCP_CNTL 0x0910 +#define RADEON_FCP0_SRC_PCICLK 0 +#define RADEON_FCP0_SRC_PCLK 1 +#define RADEON_FCP0_SRC_PCLKb 2 +#define RADEON_FCP0_SRC_HREF 3 +#define RADEON_FCP0_SRC_GND 4 +#define RADEON_FCP0_SRC_HREFb 5 +#define RADEON_FLUSH_1 0x1704 +#define RADEON_FLUSH_2 0x1708 +#define RADEON_FLUSH_3 0x170c +#define RADEON_FLUSH_4 0x1710 +#define RADEON_FLUSH_5 0x1714 +#define RADEON_FLUSH_6 0x1718 +#define RADEON_FLUSH_7 0x171c +#define RADEON_FOG_3D_TABLE_START 0x1810 +#define RADEON_FOG_3D_TABLE_END 0x1814 +#define RADEON_FOG_3D_TABLE_DENSITY 0x181c +#define RADEON_FOG_TABLE_INDEX 0x1a14 +#define RADEON_FOG_TABLE_DATA 0x1a18 +#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 +#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 +#define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff +#define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 +#define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff +#define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 +#define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +#define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 +#define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff +#define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 +#define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 +#define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 +#define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 +#define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 +#define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +#define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 +#define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 +#define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 +#define RADEON_FP_GEN_CNTL 0x0284 +#define RADEON_FP_FPON (1 << 0) +#define RADEON_FP_BLANK_EN (1 << 1) +#define RADEON_FP_TMDS_EN (1 << 2) +#define RADEON_FP_PANEL_FORMAT (1 << 3) +#define RADEON_FP_EN_TMDS (1 << 7) +#define RADEON_FP_DETECT_SENSE (1 << 8) +#define R200_FP_SOURCE_SEL_MASK (3 << 10) +#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP_SOURCE_SEL_RMX (2 << 10) +#define R200_FP_SOURCE_SEL_TRANS (3 << 10) +#define RADEON_FP_SEL_CRTC1 (0 << 13) +#define RADEON_FP_SEL_CRTC2 (1 << 13) +#define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +#define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +#define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) +#define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) +#define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +#define RADEON_FP_DFP_SYNC_SEL (1 << 21) +#define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) +#define RADEON_FP_CRT_SYNC_SEL (1 << 23) +#define RADEON_FP_USE_SHADOW_EN (1 << 24) +#define RADEON_FP_CRT_SYNC_ALT (1 << 26) +#define RADEON_FP2_GEN_CNTL 0x0288 +#define RADEON_FP2_BLANK_EN (1 << 1) +#define RADEON_FP2_ON (1 << 2) +#define RADEON_FP2_PANEL_FORMAT (1 << 3) +#define RADEON_FP2_DETECT_SENSE (1 << 8) +#define R200_FP2_SOURCE_SEL_MASK (3 << 10) +#define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) +#define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP2_SOURCE_SEL_RMX (2 << 10) +#define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) +#define RADEON_FP2_SRC_SEL_MASK (3 << 13) +#define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) +#define RADEON_FP2_FP_POL (1 << 16) +#define RADEON_FP2_LP_POL (1 << 17) +#define RADEON_FP2_SCK_POL (1 << 18) +#define RADEON_FP2_LCD_CNTL_MASK (7 << 19) +#define RADEON_FP2_PAD_FLOP_EN (1 << 22) +#define RADEON_FP2_CRC_EN (1 << 23) +#define RADEON_FP2_CRC_READ_EN (1 << 24) +#define RADEON_FP2_DVO_EN (1 << 25) +#define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) +#define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) +#define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) +#define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) +#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 +#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 +#define RADEON_FP_HORZ_STRETCH 0x028c +#define RADEON_FP_HORZ2_STRETCH 0x038c +#define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff +#define RADEON_HORZ_STRETCH_RATIO_MAX 4096 +#define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) +#define RADEON_HORZ_PANEL_SHIFT 16 +#define RADEON_HORZ_STRETCH_PIXREP (0 << 25) +#define RADEON_HORZ_STRETCH_BLEND (1 << 26) +#define RADEON_HORZ_STRETCH_ENABLE (1 << 25) +#define RADEON_HORZ_AUTO_RATIO (1 << 27) +#define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) +#define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) +#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 +#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 +#define RADEON_FP_VERT_STRETCH 0x0290 +#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 +#define RADEON_FP_VERT2_STRETCH 0x0390 +#define RADEON_VERT_PANEL_SIZE (0xfff << 12) +#define RADEON_VERT_PANEL_SHIFT 12 +#define RADEON_VERT_STRETCH_RATIO_MASK 0xfff +#define RADEON_VERT_STRETCH_RATIO_SHIFT 0 +#define RADEON_VERT_STRETCH_RATIO_MAX 4096 +#define RADEON_VERT_STRETCH_ENABLE (1 << 25) +#define RADEON_VERT_STRETCH_LINEREP (0 << 26) +#define RADEON_VERT_STRETCH_BLEND (1 << 26) +#define RADEON_VERT_AUTO_RATIO_EN (1 << 27) +#define RADEON_VERT_AUTO_RATIO_INC (1 << 31) +#define RADEON_VERT_STRETCH_RESERVED 0x71000000 +#define RS400_FP_2ND_GEN_CNTL 0x0384 +#define RS400_FP_2ND_ON (1 << 0) +#define RS400_FP_2ND_BLANK_EN (1 << 1) +#define RS400_TMDS_2ND_EN (1 << 2) +#define RS400_PANEL_FORMAT_2ND (1 << 3) +#define RS400_FP_2ND_EN_TMDS (1 << 7) +#define RS400_FP_2ND_DETECT_SENSE (1 << 8) +#define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) +#define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) +#define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) +#define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) +#define RS400_FP_2ND_DETECT_EN (1 << 12) +#define RS400_HPD_2ND_SEL (1 << 13) +#define RS400_FP2_2_GEN_CNTL 0x0388 +#define RS400_FP2_2_BLANK_EN (1 << 1) +#define RS400_FP2_2_ON (1 << 2) +#define RS400_FP2_2_PANEL_FORMAT (1 << 3) +#define RS400_FP2_2_DETECT_SENSE (1 << 8) +#define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) +#define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) +#define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) +#define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) +#define RS400_FP2_2_DVO2_EN (1 << 25) +#define RS400_TMDS2_CNTL 0x0394 +#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 +#define RS400_TMDS2_PLLEN (1 << 0) +#define RS400_TMDS2_PLLRST (1 << 1) + +#define RADEON_GEN_INT_CNTL 0x0040 +#define RADEON_GEN_INT_STATUS 0x0044 +#define RADEON_VSYNC_INT_AK (1 << 2) +#define RADEON_VSYNC_INT (1 << 2) +#define RADEON_VSYNC2_INT_AK (1 << 6) +#define RADEON_VSYNC2_INT (1 << 6) +#define RADEON_GENENB 0x03c3 /* VGA */ +#define RADEON_GENFC_RD 0x03ca /* VGA */ +#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ +#define RADEON_GENMO_RD 0x03cc /* VGA */ +#define RADEON_GENMO_WT 0x03c2 /* VGA */ +#define RADEON_GENS0 0x03c2 /* VGA */ +#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ +#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */ +#define RADEON_GPIO_MONIDB 0x006c +#define RADEON_GPIO_CRT2_DDC 0x006c +#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */ +#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */ +#define RADEON_GPIO_A_0 (1 << 0) +#define RADEON_GPIO_A_1 (1 << 1) +#define RADEON_GPIO_Y_0 (1 << 8) +#define RADEON_GPIO_Y_1 (1 << 9) +#define RADEON_GPIO_Y_SHIFT_0 8 +#define RADEON_GPIO_Y_SHIFT_1 9 +#define RADEON_GPIO_EN_0 (1 << 16) +#define RADEON_GPIO_EN_1 (1 << 17) +#define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ +#define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ +#define RADEON_GRPH8_DATA 0x03cf /* VGA */ +#define RADEON_GRPH8_IDX 0x03ce /* VGA */ +#define RADEON_GUI_SCRATCH_REG0 0x15e0 +#define RADEON_GUI_SCRATCH_REG1 0x15e4 +#define RADEON_GUI_SCRATCH_REG2 0x15e8 +#define RADEON_GUI_SCRATCH_REG3 0x15ec +#define RADEON_GUI_SCRATCH_REG4 0x15f0 +#define RADEON_GUI_SCRATCH_REG5 0x15f4 + +#define RADEON_HEADER 0x0f0e /* PCI */ +#define RADEON_HOST_DATA0 0x17c0 +#define RADEON_HOST_DATA1 0x17c4 +#define RADEON_HOST_DATA2 0x17c8 +#define RADEON_HOST_DATA3 0x17cc +#define RADEON_HOST_DATA4 0x17d0 +#define RADEON_HOST_DATA5 0x17d4 +#define RADEON_HOST_DATA6 0x17d8 +#define RADEON_HOST_DATA7 0x17dc +#define RADEON_HOST_DATA_LAST 0x17e0 +#define RADEON_HOST_PATH_CNTL 0x0130 +#define RADEON_HDP_SOFT_RESET (1 << 26) +#define RADEON_HDP_APER_CNTL (1 << 23) +#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ +#define RADEON_HTOT_CNTL_VGA_EN (1 << 28) +#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ + +/* Multimedia I2C bus */ +#define RADEON_I2C_CNTL_0 0x0090 +#define RADEON_I2C_DONE (1 << 0) +#define RADEON_I2C_NACK (1 << 1) +#define RADEON_I2C_HALT (1 << 2) +#define RADEON_I2C_SOFT_RST (1 << 5) +#define RADEON_I2C_DRIVE_EN (1 << 6) +#define RADEON_I2C_DRIVE_SEL (1 << 7) +#define RADEON_I2C_START (1 << 8) +#define RADEON_I2C_STOP (1 << 9) +#define RADEON_I2C_RECEIVE (1 << 10) +#define RADEON_I2C_ABORT (1 << 11) +#define RADEON_I2C_GO (1 << 12) +#define RADEON_I2C_CNTL_1 0x0094 +#define RADEON_I2C_SEL (1 << 16) +#define RADEON_I2C_EN (1 << 17) +#define RADEON_I2C_DATA 0x0098 + +#define RADEON_DVI_I2C_CNTL_0 0x02e0 +#define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) +#define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */ +#define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */ +#define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */ +#define RADEON_DVI_I2C_CNTL_1 0x02e4 +#define RADEON_DVI_I2C_DATA 0x02e8 + +#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ +#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ +#define RADEON_IO_BASE 0x0f14 /* PCI */ + +#define RADEON_LATENCY 0x0f0d /* PCI */ +#define RADEON_LEAD_BRES_DEC 0x1608 +#define RADEON_LEAD_BRES_LNTH 0x161c +#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 +#define RADEON_LVDS_GEN_CNTL 0x02d0 +#define RADEON_LVDS_ON (1 << 0) +#define RADEON_LVDS_DISPLAY_DIS (1 << 1) +#define RADEON_LVDS_PANEL_TYPE (1 << 2) +#define RADEON_LVDS_PANEL_FORMAT (1 << 3) +#define RADEON_LVDS_RST_FM (1 << 6) +#define RADEON_LVDS_EN (1 << 7) +#define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 +#define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) +#define RADEON_LVDS_BL_MOD_EN (1 << 16) +#define RADEON_LVDS_DIGON (1 << 18) +#define RADEON_LVDS_BLON (1 << 19) +#define RADEON_LVDS_SEL_CRTC2 (1 << 23) +#define RADEON_LVDS_PLL_CNTL 0x02d4 +#define RADEON_HSYNC_DELAY_SHIFT 28 +#define RADEON_HSYNC_DELAY_MASK (0xf << 28) +#define RADEON_LVDS_PLL_EN (1 << 16) +#define RADEON_LVDS_PLL_RESET (1 << 17) +#define R300_LVDS_SRC_SEL_MASK (3 << 18) +#define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) +#define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) +#define R300_LVDS_SRC_SEL_RMX (2 << 18) + +#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ +#define RADEON_MC_AGP_LOCATION 0x014c +#define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_DISPLAY_BASE_ADDR 0x23c +#define RADEON_DISPLAY2_BASE_ADDR 0x33c +#define RADEON_OV0_BASE_ADDR 0x43c +#define RADEON_NB_TOM 0x15c +#define R300_MC_INIT_MISC_LAT_TIMER 0x180 +#define R300_MC_DISP0R_INIT_LAT_SHIFT 8 +#define R300_MC_DISP0R_INIT_LAT_MASK 0xf +#define R300_MC_DISP1R_INIT_LAT_SHIFT 12 +#define R300_MC_DISP1R_INIT_LAT_MASK 0xf +#define RADEON_MCLK_CNTL 0x0012 /* PLL */ +#define RADEON_FORCEON_MCLKA (1 << 16) +#define RADEON_FORCEON_MCLKB (1 << 17) +#define RADEON_FORCEON_YCLKA (1 << 18) +#define RADEON_FORCEON_YCLKB (1 << 19) +#define RADEON_FORCEON_MC (1 << 20) +#define RADEON_FORCEON_AIC (1 << 21) +#define R300_DISABLE_MC_MCLKA (1 << 21) +#define R300_DISABLE_MC_MCLKB (1 << 21) +#define RADEON_MCLK_MISC 0x001f /* PLL */ +#define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) +#define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) +#define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) +#define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) +#define RADEON_LCD_GPIO_MASK 0x01a0 +#define RADEON_GPIOPAD_EN 0x01a0 +#define RADEON_LCD_GPIO_Y_REG 0x01a4 +#define RADEON_MDGPIO_A_REG 0x01ac +#define RADEON_MDGPIO_EN_REG 0x01b0 +#define RADEON_MDGPIO_MASK 0x0198 +#define RADEON_GPIOPAD_MASK 0x0198 +#define RADEON_GPIOPAD_A 0x019c +#define RADEON_MDGPIO_Y_REG 0x01b4 +#define RADEON_MEM_ADDR_CONFIG 0x0148 +#define RADEON_MEM_BASE 0x0f10 /* PCI */ +#define RADEON_MEM_CNTL 0x0140 +#define RADEON_MEM_NUM_CHANNELS_MASK 0x01 +#define RADEON_MEM_USE_B_CH_ONLY (1 << 1) +#define RV100_HALF_MODE (1 << 3) +#define R300_MEM_NUM_CHANNELS_MASK 0x03 +#define R300_MEM_USE_CD_CH_ONLY (1 << 2) +#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ +#define RADEON_MEM_INIT_LAT_TIMER 0x0154 +#define RADEON_MEM_INTF_CNTL 0x014c +#define RADEON_MEM_SDRAM_MODE_REG 0x0158 +#define RADEON_SDRAM_MODE_MASK 0xffff0000 +#define RADEON_B3MEM_RESET_MASK 0x6fffffff +#define RADEON_MEM_CFG_TYPE_DDR (1 << 30) +#define RADEON_MEM_STR_CNTL 0x0150 +#define RADEON_MEM_PWRUP_COMPL_A (1 << 0) +#define RADEON_MEM_PWRUP_COMPL_B (1 << 1) +#define R300_MEM_PWRUP_COMPL_C (1 << 2) +#define R300_MEM_PWRUP_COMPL_D (1 << 3) +#define RADEON_MEM_PWRUP_COMPLETE 0x03 +#define R300_MEM_PWRUP_COMPLETE 0x0f +#define RADEON_MC_STATUS 0x0150 +#define RADEON_MC_IDLE (1 << 2) +#define R300_MC_IDLE (1 << 4) +#define RADEON_MEM_VGA_RP_SEL 0x003c +#define RADEON_MEM_VGA_WP_SEL 0x0038 +#define RADEON_MIN_GRANT 0x0f3e /* PCI */ +#define RADEON_MM_DATA 0x0004 +#define RADEON_MM_INDEX 0x0000 +#define RADEON_MPLL_CNTL 0x000e /* PLL */ +#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ +#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ +#define RADEON_SEPROM_CNTL1 0x01c0 +#define RADEON_SCK_PRESCALE_SHIFT 24 +#define RADEON_SCK_PRESCALE_MASK (0xff << 24) +#define R300_MC_IND_INDEX 0x01f8 +#define R300_MC_IND_ADDR_MASK 0x3f +#define R300_MC_IND_WR_EN (1 << 8) +#define R300_MC_IND_DATA 0x01fc +#define R300_MC_READ_CNTL_AB 0x017c +#define R300_MEM_RBS_POSITION_A_MASK 0x03 +#define R300_MC_READ_CNTL_CD_mcind 0x24 +#define R300_MEM_RBS_POSITION_C_MASK 0x03 + +#define RADEON_N_VIF_COUNT 0x0248 + +#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 +#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +#define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +#define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +#define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +#define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +#define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +#define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +#define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 + +#define RADEON_OV0_COLOUR_CNTL 0x04E0 +#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 +#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 +#define RADEON_EXCL_HORZ_START_MASK 0x000000ff +#define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 +#define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +#define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define RADEON_OV0_EXCLUSIVE_VERT 0x040C +#define RADEON_EXCL_VERT_START_MASK 0x000003ff +#define RADEON_EXCL_VERT_END_MASK 0x03ff0000 +#define RADEON_OV0_FILTER_CNTL 0x04A0 +#define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 +#define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 +#define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 +#define RADEON_FILTER_HC_COEF_VERT_Y 0x4 +#define RADEON_FILTER_HC_COEF_VERT_UV 0x8 +#define RADEON_FILTER_HARDCODED_COEF 0xf +#define RADEON_FILTER_COEF_MASK 0xf + +#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 +#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 +#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 +#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC +#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 +#define RADEON_OV0_FLAG_CNTL 0x04DC +#define RADEON_OV0_GAMMA_000_00F 0x0d40 +#define RADEON_OV0_GAMMA_010_01F 0x0d44 +#define RADEON_OV0_GAMMA_020_03F 0x0d48 +#define RADEON_OV0_GAMMA_040_07F 0x0d4c +#define RADEON_OV0_GAMMA_080_0BF 0x0e00 +#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 +#define RADEON_OV0_GAMMA_100_13F 0x0e08 +#define RADEON_OV0_GAMMA_140_17F 0x0e0c +#define RADEON_OV0_GAMMA_180_1BF 0x0e10 +#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 +#define RADEON_OV0_GAMMA_200_23F 0x0e18 +#define RADEON_OV0_GAMMA_240_27F 0x0e1c +#define RADEON_OV0_GAMMA_280_2BF 0x0e20 +#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 +#define RADEON_OV0_GAMMA_300_33F 0x0e28 +#define RADEON_OV0_GAMMA_340_37F 0x0e2c +#define RADEON_OV0_GAMMA_380_3BF 0x0d50 +#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 +#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC +#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 +#define RADEON_OV0_H_INC 0x0480 +#define RADEON_OV0_KEY_CNTL 0x04F4 +#define RADEON_VIDEO_KEY_FN_MASK 0x00000003L +#define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L +#define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L +#define RADEON_VIDEO_KEY_FN_EQ 0x00000002L +#define RADEON_VIDEO_KEY_FN_NE 0x00000003L +#define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L +#define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L +#define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L +#define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L +#define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L +#define RADEON_CMP_MIX_MASK 0x00000100L +#define RADEON_CMP_MIX_OR 0x00000000L +#define RADEON_CMP_MIX_AND 0x00000100L +#define RADEON_OV0_LIN_TRANS_A 0x0d20 +#define RADEON_OV0_LIN_TRANS_B 0x0d24 +#define RADEON_OV0_LIN_TRANS_C 0x0d28 +#define RADEON_OV0_LIN_TRANS_D 0x0d2c +#define RADEON_OV0_LIN_TRANS_E 0x0d30 +#define RADEON_OV0_LIN_TRANS_F 0x0d34 +#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 +#define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +#define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L +#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 +#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 +#define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +#define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define RADEON_OV0_P1_X_START_END 0x0494 +#define RADEON_OV0_P2_X_START_END 0x0498 +#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 +#define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +#define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L +#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C +#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C +#define RADEON_OV0_P3_X_START_END 0x049C +#define RADEON_OV0_REG_LOAD_CNTL 0x0410 +#define RADEON_REG_LD_CTL_LOCK 0x00000001L +#define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +#define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +#define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L +#define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L +#define RADEON_OV0_SCALE_CNTL 0x0420 +#define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L +#define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L +#define RADEON_SCALER_SIGNED_UV 0x00000010L +#define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L +#define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L +#define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L +#define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L +#define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L +#define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +#define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L +#define RADEON_SCALER_SOURCE_15BPP 0x00000300L +#define RADEON_SCALER_SOURCE_16BPP 0x00000400L +#define RADEON_SCALER_SOURCE_32BPP 0x00000600L +#define RADEON_SCALER_SOURCE_YUV9 0x00000900L +#define RADEON_SCALER_SOURCE_YUV12 0x00000A00L +#define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L +#define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L +#define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +#define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L +#define RADEON_SCALER_CRTC_SEL 0x00004000L +#define RADEON_SCALER_SMART_SWITCH 0x00008000L +#define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L +#define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L +#define RADEON_SCALER_DIS_LIMIT 0x08000000L +#define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L +#define RADEON_SCALER_INT_EMU 0x20000000L +#define RADEON_SCALER_ENABLE 0x40000000L +#define RADEON_SCALER_SOFT_RESET 0x80000000L +#define RADEON_OV0_STEP_BY 0x0484 +#define RADEON_OV0_TEST 0x04F8 +#define RADEON_OV0_V_INC 0x0424 +#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 +#define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L +#define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L +#define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +#define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 +#define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L +#define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L +#define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +#define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 +#define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L +#define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L +#define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +#define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C +#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 +#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 +#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 +#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 +#define RADEON_OV0_Y_X_START 0x0400 +#define RADEON_OV0_Y_X_END 0x0404 +#define RADEON_OV1_Y_X_START 0x0600 +#define RADEON_OV1_Y_X_END 0x0604 +#define RADEON_OVR_CLR 0x0230 +#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 +#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 + +/* first capture unit */ +#define RADEON_CAP0_BUF0_OFFSET 0x0920 +#define RADEON_CAP0_BUF1_OFFSET 0x0924 +#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 +#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C + +#define RADEON_CAP0_BUF_PITCH 0x0930 +#define RADEON_CAP0_V_WINDOW 0x0934 +#define RADEON_CAP0_H_WINDOW 0x0938 +#define RADEON_CAP0_VBI0_OFFSET 0x093C +#define RADEON_CAP0_VBI1_OFFSET 0x0940 +#define RADEON_CAP0_VBI_V_WINDOW 0x0944 +#define RADEON_CAP0_VBI_H_WINDOW 0x0948 +#define RADEON_CAP0_PORT_MODE_CNTL 0x094C +#define RADEON_CAP0_TRIG_CNTL 0x0950 +#define RADEON_CAP0_DEBUG 0x0954 +#define RADEON_CAP0_CONFIG 0x0958 +#define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 +#define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +#define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 +#define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 +#define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +#define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +#define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +#define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +#define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +#define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 +#define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +#define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +#define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +#define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 +#define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +#define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +#define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +#define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +#define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +#define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +#define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +#define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +#define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +#define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +#define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +#define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 +#define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 +#define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +#define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +#define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +#define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +#define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +#define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C +#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 +#define RADEON_CAP0_ANC_H_WINDOW 0x0964 +#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 +#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C +#define RADEON_CAP0_BUF_STATUS 0x0970 +/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ +/* #define RADEON_CAP0_XSHARPNESS 0x097C */ +#define RADEON_CAP0_VBI2_OFFSET 0x0980 +#define RADEON_CAP0_VBI3_OFFSET 0x0984 +#define RADEON_CAP0_ANC2_OFFSET 0x0988 +#define RADEON_CAP0_ANC3_OFFSET 0x098C +#define RADEON_VID_BUFFER_CONTROL 0x0900 + +/* second capture unit */ +#define RADEON_CAP1_BUF0_OFFSET 0x0990 +#define RADEON_CAP1_BUF1_OFFSET 0x0994 +#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 +#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C + +#define RADEON_CAP1_BUF_PITCH 0x09A0 +#define RADEON_CAP1_V_WINDOW 0x09A4 +#define RADEON_CAP1_H_WINDOW 0x09A8 +#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC +#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 +#define RADEON_CAP1_VBI_V_WINDOW 0x09B4 +#define RADEON_CAP1_VBI_H_WINDOW 0x09B8 +#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC +#define RADEON_CAP1_TRIG_CNTL 0x09C0 +#define RADEON_CAP1_DEBUG 0x09C4 +#define RADEON_CAP1_CONFIG 0x09C8 +#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC +#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 +#define RADEON_CAP1_ANC_H_WINDOW 0x09D4 +#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 +#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define RADEON_CAP1_BUF_STATUS 0x09E0 +#define RADEON_CAP1_DWNSC_XRATIO 0x09E8 +#define RADEON_CAP1_XSHARPNESS 0x09EC + +/* misc multimedia registers */ +#define RADEON_IDCT_RUNS 0x1F80 +#define RADEON_IDCT_LEVELS 0x1F84 +#define RADEON_IDCT_CONTROL 0x1FBC +#define RADEON_IDCT_AUTH_CONTROL 0x1F88 +#define RADEON_IDCT_AUTH 0x1F8C + +#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ +#define RADEON_P2PLL_RESET (1 << 0) +#define RADEON_P2PLL_SLEEP (1 << 1) +#define RADEON_P2PLL_PVG_MASK (7 << 11) +#define RADEON_P2PLL_PVG_SHIFT 11 +#define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) +#define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +#define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_P2PLL_DIV_0 0x002c +#define RADEON_P2PLL_FB0_DIV_MASK 0x07ff +#define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 +#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ +#define RADEON_P2PLL_REF_DIV_MASK 0x03ff +#define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +#define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +#define R300_PPLL_REF_DIV_ACC_SHIFT 18 +#define RADEON_PALETTE_DATA 0x00b4 +#define RADEON_PALETTE_30_DATA 0x00b8 +#define RADEON_PALETTE_INDEX 0x00b0 +#define RADEON_PCI_GART_PAGE 0x017c +#define RADEON_PIXCLKS_CNTL 0x002d +#define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 +#define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +#define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) +#define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) +#define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) +#define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +#define R300_DVOCLK_ALWAYS_ONb (1 << 10) +#define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) +#define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) +#define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) +#define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +#define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +#define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +#define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +#define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +#define R300_P2G2CLK_ALWAYS_ONb (1 << 18) +#define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +#define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) +#define RADEON_PLANE_3D_MASK_C 0x1d44 +#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ +#define RADEON_PLL_MASK_READ_B (1 << 9) +#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ +#define RADEON_PMI_DATA 0x0f63 /* PCI */ +#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ +#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ +#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ +#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ +#define RADEON_PPLL_CNTL 0x0002 /* PLL */ +#define RADEON_PPLL_RESET (1 << 0) +#define RADEON_PPLL_SLEEP (1 << 1) +#define RADEON_PPLL_PVG_MASK (7 << 11) +#define RADEON_PPLL_PVG_SHIFT 11 +#define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) +#define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +#define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ +#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ +#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ +#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ +#define RADEON_PPLL_FB3_DIV_MASK 0x07ff +#define RADEON_PPLL_POST3_DIV_MASK 0x00070000 +#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ +#define RADEON_PPLL_REF_DIV_MASK 0x03ff +#define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +#define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ + +#define RADEON_RBBM_GUICNTL 0x172c +#define RADEON_HOST_DATA_SWAP_NONE (0 << 0) +#define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) +#define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) +#define RADEON_HOST_DATA_SWAP_HDW (3 << 0) +#define RADEON_RBBM_SOFT_RESET 0x00f0 +#define RADEON_SOFT_RESET_CP (1 << 0) +#define RADEON_SOFT_RESET_HI (1 << 1) +#define RADEON_SOFT_RESET_SE (1 << 2) +#define RADEON_SOFT_RESET_RE (1 << 3) +#define RADEON_SOFT_RESET_PP (1 << 4) +#define RADEON_SOFT_RESET_E2 (1 << 5) +#define RADEON_SOFT_RESET_RB (1 << 6) +#define RADEON_SOFT_RESET_HDP (1 << 7) +#define RADEON_RBBM_STATUS 0x0e40 +#define RADEON_RBBM_FIFOCNT_MASK 0x007f +#define RADEON_RBBM_ACTIVE (1 << 31) +#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c +#define RADEON_RB2D_DC_FLUSH (3 << 0) +#define RADEON_RB2D_DC_FREE (3 << 2) +#define RADEON_RB2D_DC_FLUSH_ALL 0xf +#define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB2D_DSTCACHE_MODE 0x3428 +#define RADEON_DSTCACHE_CTLSTAT 0x1714 + +#define RADEON_RB3D_ZCACHE_MODE 0x3250 +#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 +#define RADEON_RB3D_ZC_FLUSH_ALL 0x5 +#define RADEON_RB3D_DSTCACHE_MODE 0x3258 +#define RADEON_RB3D_DC_CACHE_ENABLE (0) +#define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) +#define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) +#define RADEON_RB3D_DC_CACHE_DISABLE (3) +#define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) +#define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) +#define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) +#define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) +#define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) +#define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) +#define RADEON_RB3D_DC_FORCE_RMW (1 << 16) +#define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) +#define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) + +#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C +#define RADEON_RB3D_DC_FLUSH (3 << 0) +#define RADEON_RB3D_DC_FREE (3 << 2) +#define RADEON_RB3D_DC_FLUSH_ALL 0xf +#define RADEON_RB3D_DC_BUSY (1 << 31) + +#define RADEON_REG_BASE 0x0f18 /* PCI */ +#define RADEON_REGPROG_INF 0x0f09 /* PCI */ +#define RADEON_REVISION_ID 0x0f08 /* PCI */ + +#define RADEON_SC_BOTTOM 0x164c +#define RADEON_SC_BOTTOM_RIGHT 0x16f0 +#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c +#define RADEON_SC_LEFT 0x1640 +#define RADEON_SC_RIGHT 0x1644 +#define RADEON_SC_TOP 0x1648 +#define RADEON_SC_TOP_LEFT 0x16ec +#define RADEON_SC_TOP_LEFT_C 0x1c88 +#define RADEON_SC_SIGN_MASK_LO 0x8000 +#define RADEON_SC_SIGN_MASK_HI 0x80000000 +#define RADEON_SCLK_CNTL 0x000d /* PLL */ +#define RADEON_SCLK_SRC_SEL_MASK 0x0007 +#define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 +#define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 +#define RADEON_SCLK_FORCEON_MASK 0xffff8000 +#define RADEON_SCLK_FORCE_DISP2 (1<<15) +#define RADEON_SCLK_FORCE_CP (1<<16) +#define RADEON_SCLK_FORCE_HDP (1<<17) +#define RADEON_SCLK_FORCE_DISP1 (1<<18) +#define RADEON_SCLK_FORCE_TOP (1<<19) +#define RADEON_SCLK_FORCE_E2 (1<<20) +#define RADEON_SCLK_FORCE_SE (1<<21) +#define RADEON_SCLK_FORCE_IDCT (1<<22) +#define RADEON_SCLK_FORCE_VIP (1<<23) +#define RADEON_SCLK_FORCE_RE (1<<24) +#define RADEON_SCLK_FORCE_PB (1<<25) +#define RADEON_SCLK_FORCE_TAM (1<<26) +#define RADEON_SCLK_FORCE_TDM (1<<27) +#define RADEON_SCLK_FORCE_RB (1<<28) +#define RADEON_SCLK_FORCE_TV_SCLK (1<<29) +#define RADEON_SCLK_FORCE_SUBPIC (1<<30) +#define RADEON_SCLK_FORCE_OV0 (1<<31) +#define R300_SCLK_FORCE_VAP (1<<21) +#define R300_SCLK_FORCE_SR (1<<25) +#define R300_SCLK_FORCE_PX (1<<26) +#define R300_SCLK_FORCE_TX (1<<27) +#define R300_SCLK_FORCE_US (1<<28) +#define R300_SCLK_FORCE_SU (1<<30) +#define R300_SCLK_CNTL2 0x1e /* PLL */ +#define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) +#define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) +#define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) +#define R300_SCLK_FORCE_TCL (1<<13) +#define R300_SCLK_FORCE_CBA (1<<14) +#define R300_SCLK_FORCE_GA (1<<15) +#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ +#define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 +#define RADEON_SCLK_MORE_FORCEON 0x0700 +#define RADEON_SDRAM_MODE_REG 0x0158 +#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ +#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ +#define RADEON_SNAPSHOT_F_COUNT 0x0244 +#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 +#define RADEON_SNAPSHOT_VIF_COUNT 0x024c +#define RADEON_SRC_OFFSET 0x15ac +#define RADEON_SRC_PITCH 0x15b0 +#define RADEON_SRC_PITCH_OFFSET 0x1428 +#define RADEON_SRC_SC_BOTTOM 0x165c +#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 +#define RADEON_SRC_SC_RIGHT 0x1654 +#define RADEON_SRC_X 0x1414 +#define RADEON_SRC_X_Y 0x1590 +#define RADEON_SRC_Y 0x1418 +#define RADEON_SRC_Y_X 0x1434 +#define RADEON_STATUS 0x0f06 /* PCI */ +#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ +#define RADEON_SUB_CLASS 0x0f0a /* PCI */ +#define RADEON_SURFACE_CNTL 0x0b00 +#define RADEON_SURF_TRANSLATION_DIS (1 << 8) +#define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) +#define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) +#define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) +#define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_INFO 0x0b0c +#define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) +#define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) +#define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) +#define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) +#define R200_SURF_TILE_NONE (0 << 16) +#define R200_SURF_TILE_COLOR_MACRO (1 << 16) +#define R200_SURF_TILE_COLOR_MICRO (2 << 16) +#define R200_SURF_TILE_COLOR_BOTH (3 << 16) +#define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +#define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +#define R300_SURF_TILE_NONE (0 << 16) +#define R300_SURF_TILE_COLOR_MACRO (1 << 16) +#define R300_SURF_TILE_DEPTH_32BPP (2 << 16) +#define RADEON_SURF_AP0_SWP_16BPP (1 << 20) +#define RADEON_SURF_AP0_SWP_32BPP (1 << 21) +#define RADEON_SURF_AP1_SWP_16BPP (1 << 22) +#define RADEON_SURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 +#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 +#define RADEON_SURFACE1_INFO 0x0b1c +#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 +#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 +#define RADEON_SURFACE2_INFO 0x0b2c +#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 +#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 +#define RADEON_SURFACE3_INFO 0x0b3c +#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 +#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 +#define RADEON_SURFACE4_INFO 0x0b4c +#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 +#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 +#define RADEON_SURFACE5_INFO 0x0b5c +#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 +#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 +#define RADEON_SURFACE6_INFO 0x0b6c +#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 +#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 +#define RADEON_SURFACE7_INFO 0x0b7c +#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 +#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 +#define RADEON_SW_SEMAPHORE 0x013c + +#define RADEON_TEST_DEBUG_CNTL 0x0120 +#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RADEON_TEST_DEBUG_MUX 0x0124 +#define RADEON_TEST_DEBUG_OUT 0x012c +#define RADEON_TMDS_PLL_CNTL 0x02a8 +#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 +#define RADEON_TMDS_TRANSMITTER_PLLEN 1 +#define RADEON_TMDS_TRANSMITTER_PLLRST 2 +#define RADEON_TRAIL_BRES_DEC 0x1614 +#define RADEON_TRAIL_BRES_ERR 0x160c +#define RADEON_TRAIL_BRES_INC 0x1610 +#define RADEON_TRAIL_X 0x1618 +#define RADEON_TRAIL_X_SUB 0x1620 + +#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ +#define RADEON_VCLK_SRC_SEL_MASK 0x03 +#define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 +#define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 +#define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 +#define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 +#define RADEON_PIXCLK_ALWAYS_ONb (1<<6) +#define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) +#define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + +#define RADEON_VENDOR_ID 0x0f00 /* PCI */ +#define RADEON_VGA_DDA_CONFIG 0x02e8 +#define RADEON_VGA_DDA_ON_OFF 0x02ec +#define RADEON_VID_BUFFER_CONTROL 0x0900 +#define RADEON_VIDEOMUX_CNTL 0x0190 + +/* VIP bus */ +#define RADEON_VIPH_CH0_DATA 0x0c00 +#define RADEON_VIPH_CH1_DATA 0x0c04 +#define RADEON_VIPH_CH2_DATA 0x0c08 +#define RADEON_VIPH_CH3_DATA 0x0c0c +#define RADEON_VIPH_CH0_ADDR 0x0c10 +#define RADEON_VIPH_CH1_ADDR 0x0c14 +#define RADEON_VIPH_CH2_ADDR 0x0c18 +#define RADEON_VIPH_CH3_ADDR 0x0c1c +#define RADEON_VIPH_CH0_SBCNT 0x0c20 +#define RADEON_VIPH_CH1_SBCNT 0x0c24 +#define RADEON_VIPH_CH2_SBCNT 0x0c28 +#define RADEON_VIPH_CH3_SBCNT 0x0c2c +#define RADEON_VIPH_CH0_ABCNT 0x0c30 +#define RADEON_VIPH_CH1_ABCNT 0x0c34 +#define RADEON_VIPH_CH2_ABCNT 0x0c38 +#define RADEON_VIPH_CH3_ABCNT 0x0c3c +#define RADEON_VIPH_CONTROL 0x0c40 +#define RADEON_VIP_BUSY 0 +#define RADEON_VIP_IDLE 1 +#define RADEON_VIP_RESET 2 +#define RADEON_VIPH_EN (1 << 21) +#define RADEON_VIPH_DV_LAT 0x0c44 +#define RADEON_VIPH_BM_CHUNK 0x0c48 +#define RADEON_VIPH_DV_INT 0x0c4c +#define RADEON_VIPH_TIMEOUT_STAT 0x0c50 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 + +#define RADEON_VIPH_REG_DATA 0x0084 +#define RADEON_VIPH_REG_ADDR 0x0080 + +#define RADEON_WAIT_UNTIL 0x1720 +#define RADEON_WAIT_CRTC_PFLIP (1 << 0) +#define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) +#define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) +#define RADEON_WAIT_CRTC_VLINE (1 << 3) +#define RADEON_WAIT_DMA_VID_IDLE (1 << 8) +#define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) +#define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ +#define RADEON_WAIT_OV0_FLIP (1 << 11) +#define RADEON_WAIT_AGP_FLUSH (1 << 13) +#define RADEON_WAIT_2D_IDLE (1 << 14) +#define RADEON_WAIT_3D_IDLE (1 << 15) +#define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +#define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +#define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) +#define RADEON_CMDFIFO_ENTRIES_SHIFT 10 +#define RADEON_CMDFIFO_ENTRIES_MASK 0x7f +#define RADEON_WAIT_VAP_IDLE (1 << 28) +#define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) +#define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) +#define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) + +#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ +#define RADEON_XCLK_CNTL 0x000d /* PLL */ +#define RADEON_XDLL_CNTL 0x000c /* PLL */ +#define RADEON_XPLL_CNTL 0x000b /* PLL */ + + + +/* Registers for 3D/TCL */ +#define RADEON_PP_BORDER_COLOR_0 0x1d40 +#define RADEON_PP_BORDER_COLOR_1 0x1d44 +#define RADEON_PP_BORDER_COLOR_2 0x1d48 +#define RADEON_PP_CNTL 0x1c38 +#define RADEON_STIPPLE_ENABLE (1 << 0) +#define RADEON_SCISSOR_ENABLE (1 << 1) +#define RADEON_PATTERN_ENABLE (1 << 2) +#define RADEON_SHADOW_ENABLE (1 << 3) +#define RADEON_TEX_ENABLE_MASK (0xf << 4) +#define RADEON_TEX_0_ENABLE (1 << 4) +#define RADEON_TEX_1_ENABLE (1 << 5) +#define RADEON_TEX_2_ENABLE (1 << 6) +#define RADEON_TEX_3_ENABLE (1 << 7) +#define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) +#define RADEON_TEX_BLEND_0_ENABLE (1 << 12) +#define RADEON_TEX_BLEND_1_ENABLE (1 << 13) +#define RADEON_TEX_BLEND_2_ENABLE (1 << 14) +#define RADEON_TEX_BLEND_3_ENABLE (1 << 15) +#define RADEON_PLANAR_YUV_ENABLE (1 << 20) +#define RADEON_SPECULAR_ENABLE (1 << 21) +#define RADEON_FOG_ENABLE (1 << 22) +#define RADEON_ALPHA_TEST_ENABLE (1 << 23) +#define RADEON_ANTI_ALIAS_NONE (0 << 24) +#define RADEON_ANTI_ALIAS_LINE (1 << 24) +#define RADEON_ANTI_ALIAS_POLY (2 << 24) +#define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) +#define RADEON_BUMP_MAP_ENABLE (1 << 26) +#define RADEON_BUMPED_MAP_T0 (0 << 27) +#define RADEON_BUMPED_MAP_T1 (1 << 27) +#define RADEON_BUMPED_MAP_T2 (2 << 27) +#define RADEON_TEX_3D_ENABLE_0 (1 << 29) +#define RADEON_TEX_3D_ENABLE_1 (1 << 30) +#define RADEON_MC_ENABLE (1 << 31) +#define RADEON_PP_FOG_COLOR 0x1c18 +#define RADEON_FOG_COLOR_MASK 0x00ffffff +#define RADEON_FOG_VERTEX (0 << 24) +#define RADEON_FOG_TABLE (1 << 24) +#define RADEON_FOG_USE_DEPTH (0 << 25) +#define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) +#define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +#define RADEON_REF_ALPHA_MASK 0x000000ff +#define RADEON_ALPHA_TEST_FAIL (0 << 8) +#define RADEON_ALPHA_TEST_LESS (1 << 8) +#define RADEON_ALPHA_TEST_LEQUAL (2 << 8) +#define RADEON_ALPHA_TEST_EQUAL (3 << 8) +#define RADEON_ALPHA_TEST_GEQUAL (4 << 8) +#define RADEON_ALPHA_TEST_GREATER (5 << 8) +#define RADEON_ALPHA_TEST_NEQUAL (6 << 8) +#define RADEON_ALPHA_TEST_PASS (7 << 8) +#define RADEON_ALPHA_TEST_OP_MASK (7 << 8) +#define RADEON_CHROMA_FUNC_FAIL (0 << 16) +#define RADEON_CHROMA_FUNC_PASS (1 << 16) +#define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) +#define RADEON_CHROMA_FUNC_EQUAL (3 << 16) +#define RADEON_CHROMA_KEY_NEAREST (0 << 18) +#define RADEON_CHROMA_KEY_ZERO (1 << 18) +#define RADEON_SHADOW_ID_AUTO_INC (1 << 20) +#define RADEON_SHADOW_FUNC_EQUAL (0 << 21) +#define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) +#define RADEON_SHADOW_PASS_1 (0 << 22) +#define RADEON_SHADOW_PASS_2 (1 << 22) +#define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) +#define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) +#define RADEON_PP_ROT_MATRIX_0 0x1d58 +#define RADEON_PP_ROT_MATRIX_1 0x1d5c +#define RADEON_PP_TXFILTER_0 0x1c54 +#define RADEON_PP_TXFILTER_1 0x1c6c +#define RADEON_PP_TXFILTER_2 0x1c84 +#define RADEON_MAG_FILTER_NEAREST (0 << 0) +#define RADEON_MAG_FILTER_LINEAR (1 << 0) +#define RADEON_MAG_FILTER_MASK (1 << 0) +#define RADEON_MIN_FILTER_NEAREST (0 << 1) +#define RADEON_MIN_FILTER_LINEAR (1 << 1) +#define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +#define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +#define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +#define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +#define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) +#define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) +#define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +#define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +#define RADEON_MIN_FILTER_MASK (15 << 1) +#define RADEON_MAX_ANISO_1_TO_1 (0 << 5) +#define RADEON_MAX_ANISO_2_TO_1 (1 << 5) +#define RADEON_MAX_ANISO_4_TO_1 (2 << 5) +#define RADEON_MAX_ANISO_8_TO_1 (3 << 5) +#define RADEON_MAX_ANISO_16_TO_1 (4 << 5) +#define RADEON_MAX_ANISO_MASK (7 << 5) +#define RADEON_LOD_BIAS_MASK (0xff << 8) +#define RADEON_LOD_BIAS_SHIFT 8 +#define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) +#define RADEON_MAX_MIP_LEVEL_SHIFT 16 +#define RADEON_YUV_TO_RGB (1 << 20) +#define RADEON_YUV_TEMPERATURE_COOL (0 << 21) +#define RADEON_YUV_TEMPERATURE_HOT (1 << 21) +#define RADEON_YUV_TEMPERATURE_MASK (1 << 21) +#define RADEON_WRAPEN_S (1 << 22) +#define RADEON_CLAMP_S_WRAP (0 << 23) +#define RADEON_CLAMP_S_MIRROR (1 << 23) +#define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) +#define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +#define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) +#define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +#define RADEON_CLAMP_S_CLAMP_GL (6 << 23) +#define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +#define RADEON_CLAMP_S_MASK (7 << 23) +#define RADEON_WRAPEN_T (1 << 26) +#define RADEON_CLAMP_T_WRAP (0 << 27) +#define RADEON_CLAMP_T_MIRROR (1 << 27) +#define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) +#define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +#define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) +#define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +#define RADEON_CLAMP_T_CLAMP_GL (6 << 27) +#define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +#define RADEON_CLAMP_T_MASK (7 << 27) +#define RADEON_BORDER_MODE_OGL (0 << 31) +#define RADEON_BORDER_MODE_D3D (1 << 31) +#define RADEON_PP_TXFORMAT_0 0x1c58 +#define RADEON_PP_TXFORMAT_1 0x1c70 +#define RADEON_PP_TXFORMAT_2 0x1c88 +#define RADEON_TXFORMAT_I8 (0 << 0) +#define RADEON_TXFORMAT_AI88 (1 << 0) +#define RADEON_TXFORMAT_RGB332 (2 << 0) +#define RADEON_TXFORMAT_ARGB1555 (3 << 0) +#define RADEON_TXFORMAT_RGB565 (4 << 0) +#define RADEON_TXFORMAT_ARGB4444 (5 << 0) +#define RADEON_TXFORMAT_ARGB8888 (6 << 0) +#define RADEON_TXFORMAT_RGBA8888 (7 << 0) +#define RADEON_TXFORMAT_Y8 (8 << 0) +#define RADEON_TXFORMAT_VYUY422 (10 << 0) +#define RADEON_TXFORMAT_YVYU422 (11 << 0) +#define RADEON_TXFORMAT_DXT1 (12 << 0) +#define RADEON_TXFORMAT_DXT23 (14 << 0) +#define RADEON_TXFORMAT_DXT45 (15 << 0) +#define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) +#define RADEON_TXFORMAT_FORMAT_SHIFT 0 +#define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) +#define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) +#define RADEON_TXFORMAT_NON_POWER2 (1 << 7) +#define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) +#define RADEON_TXFORMAT_WIDTH_SHIFT 8 +#define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) +#define RADEON_TXFORMAT_HEIGHT_SHIFT 12 +#define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) +#define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 +#define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +#define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 +#define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +#define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) +#define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +#define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +#define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) +#define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) +#define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) +#define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) +#define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +#define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +#define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) +#define RADEON_PP_CUBIC_FACES_0 0x1d24 +#define RADEON_PP_CUBIC_FACES_1 0x1d28 +#define RADEON_PP_CUBIC_FACES_2 0x1d2c +#define RADEON_FACE_WIDTH_1_SHIFT 0 +#define RADEON_FACE_HEIGHT_1_SHIFT 4 +#define RADEON_FACE_WIDTH_1_MASK (0xf << 0) +#define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) +#define RADEON_FACE_WIDTH_2_SHIFT 8 +#define RADEON_FACE_HEIGHT_2_SHIFT 12 +#define RADEON_FACE_WIDTH_2_MASK (0xf << 8) +#define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) +#define RADEON_FACE_WIDTH_3_SHIFT 16 +#define RADEON_FACE_HEIGHT_3_SHIFT 20 +#define RADEON_FACE_WIDTH_3_MASK (0xf << 16) +#define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) +#define RADEON_FACE_WIDTH_4_SHIFT 24 +#define RADEON_FACE_HEIGHT_4_SHIFT 28 +#define RADEON_FACE_WIDTH_4_MASK (0xf << 24) +#define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) + +#define RADEON_PP_TXOFFSET_0 0x1c5c +#define RADEON_PP_TXOFFSET_1 0x1c74 +#define RADEON_PP_TXOFFSET_2 0x1c8c +#define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) +#define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) +#define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) +#define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +#define RADEON_TXO_MACRO_LINEAR (0 << 2) +#define RADEON_TXO_MACRO_TILE (1 << 2) +#define RADEON_TXO_MICRO_LINEAR (0 << 3) +#define RADEON_TXO_MICRO_TILE_X2 (1 << 3) +#define RADEON_TXO_MICRO_TILE_OPT (2 << 3) +#define RADEON_TXO_OFFSET_MASK 0xffffffe0 +#define RADEON_TXO_OFFSET_SHIFT 5 + +#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 +#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 +#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc +#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 +#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 +#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 +#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 +#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c +#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 +#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 +#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 +#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c +#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 +#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 + +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_1 0x1d0c +#define RADEON_PP_TEX_SIZE_2 0x1d14 +#define RADEON_TEX_USIZE_MASK (0x7ff << 0) +#define RADEON_TEX_USIZE_SHIFT 0 +#define RADEON_TEX_VSIZE_MASK (0x7ff << 16) +#define RADEON_TEX_VSIZE_SHIFT 16 +#define RADEON_SIGNED_RGB_MASK (1 << 30) +#define RADEON_SIGNED_RGB_SHIFT 30 +#define RADEON_SIGNED_ALPHA_MASK (1 << 31) +#define RADEON_SIGNED_ALPHA_SHIFT 31 +#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ +#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ +#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ +/* note: bits 13-5: 32 byte aligned stride of texture map */ + +#define RADEON_PP_TXCBLEND_0 0x1c60 +#define RADEON_PP_TXCBLEND_1 0x1c78 +#define RADEON_PP_TXCBLEND_2 0x1c90 +#define RADEON_COLOR_ARG_A_SHIFT 0 +#define RADEON_COLOR_ARG_A_MASK (0x1f << 0) +#define RADEON_COLOR_ARG_A_ZERO (0 << 0) +#define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) +#define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) +#define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) +#define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) +#define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) +#define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) +#define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) +#define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) +#define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) +#define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) +#define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) +#define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) +#define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) +#define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) +#define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) +#define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) +#define RADEON_COLOR_ARG_B_SHIFT 5 +#define RADEON_COLOR_ARG_B_MASK (0x1f << 5) +#define RADEON_COLOR_ARG_B_ZERO (0 << 5) +#define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) +#define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) +#define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) +#define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) +#define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) +#define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) +#define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) +#define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) +#define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) +#define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) +#define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) +#define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) +#define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) +#define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) +#define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) +#define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) +#define RADEON_COLOR_ARG_C_SHIFT 10 +#define RADEON_COLOR_ARG_C_MASK (0x1f << 10) +#define RADEON_COLOR_ARG_C_ZERO (0 << 10) +#define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) +#define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) +#define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) +#define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) +#define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) +#define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) +#define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) +#define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) +#define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) +#define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) +#define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) +#define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) +#define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) +#define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) +#define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) +#define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) +#define RADEON_COMP_ARG_A (1 << 15) +#define RADEON_COMP_ARG_A_SHIFT 15 +#define RADEON_COMP_ARG_B (1 << 16) +#define RADEON_COMP_ARG_B_SHIFT 16 +#define RADEON_COMP_ARG_C (1 << 17) +#define RADEON_COMP_ARG_C_SHIFT 17 +#define RADEON_BLEND_CTL_MASK (7 << 18) +#define RADEON_BLEND_CTL_ADD (0 << 18) +#define RADEON_BLEND_CTL_SUBTRACT (1 << 18) +#define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) +#define RADEON_BLEND_CTL_BLEND (3 << 18) +#define RADEON_BLEND_CTL_DOT3 (4 << 18) +#define RADEON_SCALE_SHIFT 21 +#define RADEON_SCALE_MASK (3 << 21) +#define RADEON_SCALE_1X (0 << 21) +#define RADEON_SCALE_2X (1 << 21) +#define RADEON_SCALE_4X (2 << 21) +#define RADEON_CLAMP_TX (1 << 23) +#define RADEON_T0_EQ_TCUR (1 << 24) +#define RADEON_T1_EQ_TCUR (1 << 25) +#define RADEON_T2_EQ_TCUR (1 << 26) +#define RADEON_T3_EQ_TCUR (1 << 27) +#define RADEON_COLOR_ARG_MASK 0x1f +#define RADEON_COMP_ARG_SHIFT 15 +#define RADEON_PP_TXABLEND_0 0x1c64 +#define RADEON_PP_TXABLEND_1 0x1c7c +#define RADEON_PP_TXABLEND_2 0x1c94 +#define RADEON_ALPHA_ARG_A_SHIFT 0 +#define RADEON_ALPHA_ARG_A_MASK (0xf << 0) +#define RADEON_ALPHA_ARG_A_ZERO (0 << 0) +#define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) +#define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) +#define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) +#define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) +#define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) +#define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) +#define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) +#define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) +#define RADEON_ALPHA_ARG_B_SHIFT 4 +#define RADEON_ALPHA_ARG_B_MASK (0xf << 4) +#define RADEON_ALPHA_ARG_B_ZERO (0 << 4) +#define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) +#define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) +#define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) +#define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) +#define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) +#define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) +#define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) +#define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) +#define RADEON_ALPHA_ARG_C_SHIFT 8 +#define RADEON_ALPHA_ARG_C_MASK (0xf << 8) +#define RADEON_ALPHA_ARG_C_ZERO (0 << 8) +#define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) +#define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) +#define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) +#define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) +#define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) +#define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) +#define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) +#define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) +#define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) +#define RADEON_ALPHA_ARG_MASK 0xf + +#define RADEON_PP_TFACTOR_0 0x1c68 +#define RADEON_PP_TFACTOR_1 0x1c80 +#define RADEON_PP_TFACTOR_2 0x1c98 + +#define RADEON_RB3D_BLENDCNTL 0x1c20 +#define RADEON_COMB_FCN_MASK (3 << 12) +#define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) +#define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) +#define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) +#define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) +#define RADEON_SRC_BLEND_GL_ZERO (32 << 16) +#define RADEON_SRC_BLEND_GL_ONE (33 << 16) +#define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) +#define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) +#define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) +#define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) +#define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) +#define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) +#define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) +#define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) +#define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) +#define RADEON_SRC_BLEND_MASK (63 << 16) +#define RADEON_DST_BLEND_GL_ZERO (32 << 24) +#define RADEON_DST_BLEND_GL_ONE (33 << 24) +#define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) +#define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) +#define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) +#define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) +#define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) +#define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) +#define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) +#define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) +#define RADEON_DST_BLEND_MASK (63 << 24) +#define RADEON_RB3D_CNTL 0x1c3c +#define RADEON_ALPHA_BLEND_ENABLE (1 << 0) +#define RADEON_PLANE_MASK_ENABLE (1 << 1) +#define RADEON_DITHER_ENABLE (1 << 2) +#define RADEON_ROUND_ENABLE (1 << 3) +#define RADEON_SCALE_DITHER_ENABLE (1 << 4) +#define RADEON_DITHER_INIT (1 << 5) +#define RADEON_ROP_ENABLE (1 << 6) +#define RADEON_STENCIL_ENABLE (1 << 7) +#define RADEON_Z_ENABLE (1 << 8) +#define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +#define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) +#define RADEON_COLOR_FORMAT_RGB565 (4 << 10) +#define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) +#define RADEON_COLOR_FORMAT_RGB332 (7 << 10) +#define RADEON_COLOR_FORMAT_Y8 (8 << 10) +#define RADEON_COLOR_FORMAT_RGB8 (9 << 10) +#define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) +#define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) +#define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) +#define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) +#define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) +#define RADEON_RB3D_COLOROFFSET 0x1c40 +#define RADEON_COLOROFFSET_MASK 0xfffffff0 +#define RADEON_RB3D_COLORPITCH 0x1c48 +#define RADEON_COLORPITCH_MASK 0x000001ff8 +#define RADEON_COLOR_TILE_ENABLE (1 << 16) +#define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) +#define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) +#define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) +#define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_DEPTHPITCH 0x1c28 +#define RADEON_DEPTHPITCH_MASK 0x00001ff8 +#define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) +#define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) +#define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_ROPCNTL 0x1d80 +#define RADEON_ROP_MASK (15 << 8) +#define RADEON_ROP_CLEAR (0 << 8) +#define RADEON_ROP_NOR (1 << 8) +#define RADEON_ROP_AND_INVERTED (2 << 8) +#define RADEON_ROP_COPY_INVERTED (3 << 8) +#define RADEON_ROP_AND_REVERSE (4 << 8) +#define RADEON_ROP_INVERT (5 << 8) +#define RADEON_ROP_XOR (6 << 8) +#define RADEON_ROP_NAND (7 << 8) +#define RADEON_ROP_AND (8 << 8) +#define RADEON_ROP_EQUIV (9 << 8) +#define RADEON_ROP_NOOP (10 << 8) +#define RADEON_ROP_OR_INVERTED (11 << 8) +#define RADEON_ROP_COPY (12 << 8) +#define RADEON_ROP_OR_REVERSE (13 << 8) +#define RADEON_ROP_OR (14 << 8) +#define RADEON_ROP_SET (15 << 8) +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +#define RADEON_STENCIL_REF_SHIFT 0 +#define RADEON_STENCIL_REF_MASK (0xff << 0) +#define RADEON_STENCIL_MASK_SHIFT 16 +#define RADEON_STENCIL_VALUE_MASK (0xff << 16) +#define RADEON_STENCIL_WRITEMASK_SHIFT 24 +#define RADEON_STENCIL_WRITE_MASK (0xff << 24) +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +#define RADEON_DEPTH_FORMAT_MASK (0xf << 0) +#define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +#define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) +#define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) +#define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) +#define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) +#define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) +#define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) +#define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) +#define RADEON_Z_TEST_NEVER (0 << 4) +#define RADEON_Z_TEST_LESS (1 << 4) +#define RADEON_Z_TEST_LEQUAL (2 << 4) +#define RADEON_Z_TEST_EQUAL (3 << 4) +#define RADEON_Z_TEST_GEQUAL (4 << 4) +#define RADEON_Z_TEST_GREATER (5 << 4) +#define RADEON_Z_TEST_NEQUAL (6 << 4) +#define RADEON_Z_TEST_ALWAYS (7 << 4) +#define RADEON_Z_TEST_MASK (7 << 4) +#define RADEON_STENCIL_TEST_NEVER (0 << 12) +#define RADEON_STENCIL_TEST_LESS (1 << 12) +#define RADEON_STENCIL_TEST_LEQUAL (2 << 12) +#define RADEON_STENCIL_TEST_EQUAL (3 << 12) +#define RADEON_STENCIL_TEST_GEQUAL (4 << 12) +#define RADEON_STENCIL_TEST_GREATER (5 << 12) +#define RADEON_STENCIL_TEST_NEQUAL (6 << 12) +#define RADEON_STENCIL_TEST_ALWAYS (7 << 12) +#define RADEON_STENCIL_TEST_MASK (0x7 << 12) +#define RADEON_STENCIL_FAIL_KEEP (0 << 16) +#define RADEON_STENCIL_FAIL_ZERO (1 << 16) +#define RADEON_STENCIL_FAIL_REPLACE (2 << 16) +#define RADEON_STENCIL_FAIL_INC (3 << 16) +#define RADEON_STENCIL_FAIL_DEC (4 << 16) +#define RADEON_STENCIL_FAIL_INVERT (5 << 16) +#define RADEON_STENCIL_FAIL_MASK (0x7 << 16) +#define RADEON_STENCIL_ZPASS_KEEP (0 << 20) +#define RADEON_STENCIL_ZPASS_ZERO (1 << 20) +#define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) +#define RADEON_STENCIL_ZPASS_INC (3 << 20) +#define RADEON_STENCIL_ZPASS_DEC (4 << 20) +#define RADEON_STENCIL_ZPASS_INVERT (5 << 20) +#define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) +#define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) +#define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) +#define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) +#define RADEON_STENCIL_ZFAIL_INC (3 << 24) +#define RADEON_STENCIL_ZFAIL_DEC (4 << 24) +#define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) +#define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) +#define RADEON_Z_COMPRESSION_ENABLE (1 << 28) +#define RADEON_FORCE_Z_DIRTY (1 << 29) +#define RADEON_Z_WRITE_ENABLE (1 << 30) +#define RADEON_RE_LINE_PATTERN 0x1cd0 +#define RADEON_LINE_PATTERN_MASK 0x0000ffff +#define RADEON_LINE_REPEAT_COUNT_SHIFT 16 +#define RADEON_LINE_PATTERN_START_SHIFT 24 +#define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) +#define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) +#define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) +#define RADEON_RE_LINE_STATE 0x1cd4 +#define RADEON_LINE_CURRENT_PTR_SHIFT 0 +#define RADEON_LINE_CURRENT_COUNT_SHIFT 8 +#define RADEON_RE_MISC 0x26c4 +#define RADEON_STIPPLE_COORD_MASK 0x1f +#define RADEON_STIPPLE_X_OFFSET_SHIFT 0 +#define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) +#define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 +#define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) +#define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) +#define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) +#define RADEON_RE_SOLID_COLOR 0x1c1c +#define RADEON_RE_TOP_LEFT 0x26c0 +#define RADEON_RE_LEFT_SHIFT 0 +#define RADEON_RE_TOP_SHIFT 16 +#define RADEON_RE_WIDTH_HEIGHT 0x1c44 +#define RADEON_RE_WIDTH_SHIFT 0 +#define RADEON_RE_HEIGHT_SHIFT 16 + +#define RADEON_SE_CNTL 0x1c4c +#define RADEON_FFACE_CULL_CW (0 << 0) +#define RADEON_FFACE_CULL_CCW (1 << 0) +#define RADEON_FFACE_CULL_DIR_MASK (1 << 0) +#define RADEON_BFACE_CULL (0 << 1) +#define RADEON_BFACE_SOLID (3 << 1) +#define RADEON_FFACE_CULL (0 << 3) +#define RADEON_FFACE_SOLID (3 << 3) +#define RADEON_FFACE_CULL_MASK (3 << 3) +#define RADEON_BADVTX_CULL_DISABLE (1 << 5) +#define RADEON_FLAT_SHADE_VTX_0 (0 << 6) +#define RADEON_FLAT_SHADE_VTX_1 (1 << 6) +#define RADEON_FLAT_SHADE_VTX_2 (2 << 6) +#define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) +#define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) +#define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) +#define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) +#define RADEON_DIFFUSE_SHADE_MASK (3 << 8) +#define RADEON_ALPHA_SHADE_SOLID (0 << 10) +#define RADEON_ALPHA_SHADE_FLAT (1 << 10) +#define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) +#define RADEON_ALPHA_SHADE_MASK (3 << 10) +#define RADEON_SPECULAR_SHADE_SOLID (0 << 12) +#define RADEON_SPECULAR_SHADE_FLAT (1 << 12) +#define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) +#define RADEON_SPECULAR_SHADE_MASK (3 << 12) +#define RADEON_FOG_SHADE_SOLID (0 << 14) +#define RADEON_FOG_SHADE_FLAT (1 << 14) +#define RADEON_FOG_SHADE_GOURAUD (2 << 14) +#define RADEON_FOG_SHADE_MASK (3 << 14) +#define RADEON_ZBIAS_ENABLE_POINT (1 << 16) +#define RADEON_ZBIAS_ENABLE_LINE (1 << 17) +#define RADEON_ZBIAS_ENABLE_TRI (1 << 18) +#define RADEON_WIDELINE_ENABLE (1 << 20) +#define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +#define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +#define RADEON_VTX_PIX_CENTER_D3D (0 << 27) +#define RADEON_VTX_PIX_CENTER_OGL (1 << 27) +#define RADEON_ROUND_MODE_TRUNC (0 << 28) +#define RADEON_ROUND_MODE_ROUND (1 << 28) +#define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) +#define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) +#define RADEON_ROUND_PREC_16TH_PIX (0 << 30) +#define RADEON_ROUND_PREC_8TH_PIX (1 << 30) +#define RADEON_ROUND_PREC_4TH_PIX (2 << 30) +#define RADEON_ROUND_PREC_HALF_PIX (3 << 30) +#define R200_RE_CNTL 0x1c50 +#define R200_STIPPLE_ENABLE 0x1 +#define R200_SCISSOR_ENABLE 0x2 +#define R200_PATTERN_ENABLE 0x4 +#define R200_PERSPECTIVE_ENABLE 0x8 +#define R200_POINT_SMOOTH 0x20 +#define R200_VTX_STQ0_D3D 0x00010000 +#define R200_VTX_STQ1_D3D 0x00040000 +#define R200_VTX_STQ2_D3D 0x00100000 +#define R200_VTX_STQ3_D3D 0x00400000 +#define R200_VTX_STQ4_D3D 0x01000000 +#define R200_VTX_STQ5_D3D 0x04000000 +#define R200_RE_SCISSOR_TL_0 0x1cd8 +#define R200_RE_SCISSOR_BR_0 0x1cdc +#define R200_RE_SCISSOR_TL_1 0x1ce0 +#define R200_RE_SCISSOR_BR_1 0x1ce4 +#define R200_RE_SCISSOR_TL_2 0x1ce8 +#define R200_RE_SCISSOR_BR_2 0x1cec +#define R200_SCISSOR_X_SHIFT 0 +#define R200_SCISSOR_Y_SHIFT 16 +#define RADEON_SE_CNTL_STATUS 0x2140 +#define RADEON_VC_NO_SWAP (0 << 0) +#define RADEON_VC_16BIT_SWAP (1 << 0) +#define RADEON_VC_32BIT_SWAP (2 << 0) +#define RADEON_VC_HALF_DWORD_SWAP (3 << 0) +#define RADEON_TCL_BYPASS (1 << 8) +#define RADEON_SE_COORD_FMT 0x1c50 +#define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) +#define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) +#define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) +#define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) +#define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) +#define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) +#define RADEON_VTX_W0_NORMALIZE (1 << 12) +#define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) +#define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) +#define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) +#define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) +#define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) +#define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) +#define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c +#define RADEON_LIGHTING_ENABLE (1 << 0) +#define RADEON_LIGHT_IN_MODELSPACE (1 << 1) +#define RADEON_LOCAL_VIEWER (1 << 2) +#define RADEON_NORMALIZE_NORMALS (1 << 3) +#define RADEON_RESCALE_NORMALS (1 << 4) +#define RADEON_SPECULAR_LIGHTS (1 << 5) +#define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) +#define RADEON_LIGHT_ALPHA (1 << 7) +#define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) +#define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) +#define RADEON_LM_SOURCE_STATE_PREMULT 0 +#define RADEON_LM_SOURCE_STATE_MULT 1 +#define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 +#define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 +#define RADEON_EMISSIVE_SOURCE_SHIFT 16 +#define RADEON_AMBIENT_SOURCE_SHIFT 18 +#define RADEON_DIFFUSE_SOURCE_SHIFT 20 +#define RADEON_SPECULAR_SOURCE_SHIFT 22 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c +#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c +#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c +#define RADEON_MODELVIEW_0_SHIFT 0 +#define RADEON_MODELVIEW_1_SHIFT 4 +#define RADEON_MODELVIEW_2_SHIFT 8 +#define RADEON_MODELVIEW_3_SHIFT 12 +#define RADEON_IT_MODELVIEW_0_SHIFT 16 +#define RADEON_IT_MODELVIEW_1_SHIFT 20 +#define RADEON_IT_MODELVIEW_2_SHIFT 24 +#define RADEON_IT_MODELVIEW_3_SHIFT 28 +#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 +#define RADEON_MODELPROJECT_0_SHIFT 0 +#define RADEON_MODELPROJECT_1_SHIFT 4 +#define RADEON_MODELPROJECT_2_SHIFT 8 +#define RADEON_MODELPROJECT_3_SHIFT 12 +#define RADEON_TEXMAT_0_SHIFT 16 +#define RADEON_TEXMAT_1_SHIFT 20 +#define RADEON_TEXMAT_2_SHIFT 24 +#define RADEON_TEXMAT_3_SHIFT 28 + + +#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 +#define RADEON_TCL_VTX_W0 (1 << 0) +#define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) +#define RADEON_TCL_VTX_FP_ALPHA (1 << 2) +#define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) +#define RADEON_TCL_VTX_FP_SPEC (1 << 4) +#define RADEON_TCL_VTX_FP_FOG (1 << 5) +#define RADEON_TCL_VTX_PK_SPEC (1 << 6) +#define RADEON_TCL_VTX_ST0 (1 << 7) +#define RADEON_TCL_VTX_ST1 (1 << 8) +#define RADEON_TCL_VTX_Q1 (1 << 9) +#define RADEON_TCL_VTX_ST2 (1 << 10) +#define RADEON_TCL_VTX_Q2 (1 << 11) +#define RADEON_TCL_VTX_ST3 (1 << 12) +#define RADEON_TCL_VTX_Q3 (1 << 13) +#define RADEON_TCL_VTX_Q0 (1 << 14) +#define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 +#define RADEON_TCL_VTX_NORM0 (1 << 18) +#define RADEON_TCL_VTX_XY1 (1 << 27) +#define RADEON_TCL_VTX_Z1 (1 << 28) +#define RADEON_TCL_VTX_W1 (1 << 29) +#define RADEON_TCL_VTX_NORM1 (1 << 30) +#define RADEON_TCL_VTX_Z0 (1 << 31) + +#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 +#define RADEON_TCL_COMPUTE_XYZW (1 << 0) +#define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) +#define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) +#define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) +#define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) +#define RADEON_TCL_TEX_INPUT_TEX_0 0 +#define RADEON_TCL_TEX_INPUT_TEX_1 1 +#define RADEON_TCL_TEX_INPUT_TEX_2 2 +#define RADEON_TCL_TEX_INPUT_TEX_3 3 +#define RADEON_TCL_TEX_COMPUTED_TEX_0 8 +#define RADEON_TCL_TEX_COMPUTED_TEX_1 9 +#define RADEON_TCL_TEX_COMPUTED_TEX_2 10 +#define RADEON_TCL_TEX_COMPUTED_TEX_3 11 +#define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 +#define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 +#define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 +#define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 + +#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 +#define RADEON_LIGHT_0_ENABLE (1 << 0) +#define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) +#define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) +#define RADEON_LIGHT_0_IS_LOCAL (1 << 3) +#define RADEON_LIGHT_0_IS_SPOT (1 << 4) +#define RADEON_LIGHT_0_DUAL_CONE (1 << 5) +#define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) +#define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) +#define RADEON_LIGHT_0_SHIFT 0 +#define RADEON_LIGHT_1_ENABLE (1 << 16) +#define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) +#define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) +#define RADEON_LIGHT_1_IS_LOCAL (1 << 19) +#define RADEON_LIGHT_1_IS_SPOT (1 << 20) +#define RADEON_LIGHT_1_DUAL_CONE (1 << 21) +#define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) +#define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) +#define RADEON_LIGHT_1_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 +#define RADEON_LIGHT_2_SHIFT 0 +#define RADEON_LIGHT_3_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 +#define RADEON_LIGHT_4_SHIFT 0 +#define RADEON_LIGHT_5_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c +#define RADEON_LIGHT_6_SHIFT 0 +#define RADEON_LIGHT_7_SHIFT 16 + +#define RADEON_SE_TCL_SHININESS 0x2250 + +#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 +#define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) +#define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) +#define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) +#define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) +#define RADEON_TEXMAT_0_ENABLE (1 << 4) +#define RADEON_TEXMAT_1_ENABLE (1 << 5) +#define RADEON_TEXMAT_2_ENABLE (1 << 6) +#define RADEON_TEXMAT_3_ENABLE (1 << 7) +#define RADEON_TEXGEN_INPUT_MASK 0xf +#define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 +#define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 +#define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 +#define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 +#define RADEON_TEXGEN_INPUT_OBJ 4 +#define RADEON_TEXGEN_INPUT_EYE 5 +#define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 +#define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 +#define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 +#define RADEON_TEXGEN_0_INPUT_SHIFT 16 +#define RADEON_TEXGEN_1_INPUT_SHIFT 20 +#define RADEON_TEXGEN_2_INPUT_SHIFT 24 +#define RADEON_TEXGEN_3_INPUT_SHIFT 28 + +#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 +#define RADEON_UCP_IN_CLIP_SPACE (1 << 0) +#define RADEON_UCP_IN_MODEL_SPACE (1 << 1) +#define RADEON_UCP_ENABLE_0 (1 << 2) +#define RADEON_UCP_ENABLE_1 (1 << 3) +#define RADEON_UCP_ENABLE_2 (1 << 4) +#define RADEON_UCP_ENABLE_3 (1 << 5) +#define RADEON_UCP_ENABLE_4 (1 << 6) +#define RADEON_UCP_ENABLE_5 (1 << 7) +#define RADEON_TCL_FOG_MASK (3 << 8) +#define RADEON_TCL_FOG_DISABLE (0 << 8) +#define RADEON_TCL_FOG_EXP (1 << 8) +#define RADEON_TCL_FOG_EXP2 (2 << 8) +#define RADEON_TCL_FOG_LINEAR (3 << 8) +#define RADEON_RNG_BASED_FOG (1 << 10) +#define RADEON_LIGHT_TWOSIDE (1 << 11) +#define RADEON_BLEND_OP_COUNT_MASK (7 << 12) +#define RADEON_BLEND_OP_COUNT_SHIFT 12 +#define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) +#define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) +#define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) +#define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) +#define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) +#define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) +#define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) +#define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) +#define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) +#define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) +#define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) +#define RADEON_CULL_FRONT_IS_CW (0 << 28) +#define RADEON_CULL_FRONT_IS_CCW (1 << 28) +#define RADEON_CULL_FRONT (1 << 29) +#define RADEON_CULL_BACK (1 << 30) +#define RADEON_FORCE_W_TO_ONE (1 << 31) + +#define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SE_VPORT_XOFFSET 0x1d9c +#define RADEON_SE_VPORT_YSCALE 0x1da0 +#define RADEON_SE_VPORT_YOFFSET 0x1da4 +#define RADEON_SE_VPORT_ZSCALE 0x1da8 +#define RADEON_SE_VPORT_ZOFFSET 0x1dac +#define RADEON_SE_ZBIAS_FACTOR 0x1db0 +#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 + +#define RADEON_SE_VTX_FMT 0x2080 +#define RADEON_SE_VTX_FMT_XY 0x00000000 +#define RADEON_SE_VTX_FMT_W0 0x00000001 +#define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 +#define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 +#define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 +#define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 +#define RADEON_SE_VTX_FMT_FPFOG 0x00000020 +#define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 +#define RADEON_SE_VTX_FMT_ST0 0x00000080 +#define RADEON_SE_VTX_FMT_ST1 0x00000100 +#define RADEON_SE_VTX_FMT_Q1 0x00000200 +#define RADEON_SE_VTX_FMT_ST2 0x00000400 +#define RADEON_SE_VTX_FMT_Q2 0x00000800 +#define RADEON_SE_VTX_FMT_ST3 0x00001000 +#define RADEON_SE_VTX_FMT_Q3 0x00002000 +#define RADEON_SE_VTX_FMT_Q0 0x00004000 +#define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +#define RADEON_SE_VTX_FMT_N0 0x00040000 +#define RADEON_SE_VTX_FMT_XY1 0x08000000 +#define RADEON_SE_VTX_FMT_Z1 0x10000000 +#define RADEON_SE_VTX_FMT_W1 0x20000000 +#define RADEON_SE_VTX_FMT_N1 0x40000000 +#define RADEON_SE_VTX_FMT_Z 0x80000000 + +#define RADEON_SE_VF_CNTL 0x2084 +#define RADEON_VF_PRIM_TYPE_POINT_LIST 1 +#define RADEON_VF_PRIM_TYPE_LINE_LIST 2 +#define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 +#define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 +#define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 +#define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 +#define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 +#define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 +#define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 +#define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 +#define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 +#define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 +#define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 +#define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 +#define RADEON_VF_PRIM_TYPE_POLYGON 15 +#define RADEON_VF_PRIM_WALK_STATE (0<<4) +#define RADEON_VF_PRIM_WALK_INDEX (1<<4) +#define RADEON_VF_PRIM_WALK_LIST (2<<4) +#define RADEON_VF_PRIM_WALK_DATA (3<<4) +#define RADEON_VF_COLOR_ORDER_RGBA (1<<6) +#define RADEON_VF_RADEON_MODE (1<<8) +#define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) +#define RADEON_VF_PROG_STREAM_ENA (1<<10) +#define RADEON_VF_INDEX_SIZE_SHIFT 11 +#define RADEON_VF_NUM_VERTICES_SHIFT 16 + +#define RADEON_SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +#define R200_VAP_TCL_ENABLE 0x00000001 +#define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 +#define R200_VAP_FORCE_W_TO_ONE 0x00010000 +#define R200_VAP_D3D_TEX_DEFAULT 0x00020000 +#define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 +#define R200_VAP_VF_MAX_VTX_NUM (9 << 18) +#define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +#define R200_VPORT_X_SCALE_ENA 0x00000001 +#define R200_VPORT_X_OFFSET_ENA 0x00000002 +#define R200_VPORT_Y_SCALE_ENA 0x00000004 +#define R200_VPORT_Y_OFFSET_ENA 0x00000008 +#define R200_VPORT_Z_SCALE_ENA 0x00000010 +#define R200_VPORT_Z_OFFSET_ENA 0x00000020 +#define R200_VTX_XY_FMT 0x00000100 +#define R200_VTX_Z_FMT 0x00000200 +#define R200_VTX_W0_FMT 0x00000400 +#define R200_VTX_W0_NORMALIZE 0x00000800 +#define R200_VTX_ST_DENORMALIZED 0x00001000 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +#define R200_VC_NO_SWAP (0 << 0) +#define R200_VC_16BIT_SWAP (1 << 0) +#define R200_VC_32BIT_SWAP (2 << 0) +#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 +#define R200_EXCLUSIVE_SCISSOR_0 0x01000000 +#define R200_EXCLUSIVE_SCISSOR_1 0x02000000 +#define R200_EXCLUSIVE_SCISSOR_2 0x04000000 +#define R200_SCISSOR_ENABLE_0 0x10000000 +#define R200_SCISSOR_ENABLE_1 0x20000000 +#define R200_SCISSOR_ENABLE_2 0x40000000 +#define R200_PP_TXFILTER_0 0x2c00 +#define R200_PP_TXFILTER_1 0x2c20 +#define R200_PP_TXFILTER_2 0x2c40 +#define R200_PP_TXFILTER_3 0x2c60 +#define R200_PP_TXFILTER_4 0x2c80 +#define R200_PP_TXFILTER_5 0x2ca0 +#define R200_MAG_FILTER_NEAREST (0 << 0) +#define R200_MAG_FILTER_LINEAR (1 << 0) +#define R200_MAG_FILTER_MASK (1 << 0) +#define R200_MIN_FILTER_NEAREST (0 << 1) +#define R200_MIN_FILTER_LINEAR (1 << 1) +#define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +#define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +#define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +#define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +#define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) +#define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) +#define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +#define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +#define R200_MIN_FILTER_MASK (15 << 1) +#define R200_MAX_ANISO_1_TO_1 (0 << 5) +#define R200_MAX_ANISO_2_TO_1 (1 << 5) +#define R200_MAX_ANISO_4_TO_1 (2 << 5) +#define R200_MAX_ANISO_8_TO_1 (3 << 5) +#define R200_MAX_ANISO_16_TO_1 (4 << 5) +#define R200_MAX_ANISO_MASK (7 << 5) +#define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) +#define R200_MAX_MIP_LEVEL_SHIFT 16 +#define R200_YUV_TO_RGB (1 << 20) +#define R200_YUV_TEMPERATURE_COOL (0 << 21) +#define R200_YUV_TEMPERATURE_HOT (1 << 21) +#define R200_YUV_TEMPERATURE_MASK (1 << 21) +#define R200_WRAPEN_S (1 << 22) +#define R200_CLAMP_S_WRAP (0 << 23) +#define R200_CLAMP_S_MIRROR (1 << 23) +#define R200_CLAMP_S_CLAMP_LAST (2 << 23) +#define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +#define R200_CLAMP_S_CLAMP_BORDER (4 << 23) +#define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +#define R200_CLAMP_S_CLAMP_GL (6 << 23) +#define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +#define R200_CLAMP_S_MASK (7 << 23) +#define R200_WRAPEN_T (1 << 26) +#define R200_CLAMP_T_WRAP (0 << 27) +#define R200_CLAMP_T_MIRROR (1 << 27) +#define R200_CLAMP_T_CLAMP_LAST (2 << 27) +#define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +#define R200_CLAMP_T_CLAMP_BORDER (4 << 27) +#define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +#define R200_CLAMP_T_CLAMP_GL (6 << 27) +#define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +#define R200_CLAMP_T_MASK (7 << 27) +#define R200_KILL_LT_ZERO (1 << 30) +#define R200_BORDER_MODE_OGL (0 << 31) +#define R200_BORDER_MODE_D3D (1 << 31) +#define R200_PP_TXFORMAT_0 0x2c04 +#define R200_PP_TXFORMAT_1 0x2c24 +#define R200_PP_TXFORMAT_2 0x2c44 +#define R200_PP_TXFORMAT_3 0x2c64 +#define R200_PP_TXFORMAT_4 0x2c84 +#define R200_PP_TXFORMAT_5 0x2ca4 +#define R200_TXFORMAT_I8 (0 << 0) +#define R200_TXFORMAT_AI88 (1 << 0) +#define R200_TXFORMAT_RGB332 (2 << 0) +#define R200_TXFORMAT_ARGB1555 (3 << 0) +#define R200_TXFORMAT_RGB565 (4 << 0) +#define R200_TXFORMAT_ARGB4444 (5 << 0) +#define R200_TXFORMAT_ARGB8888 (6 << 0) +#define R200_TXFORMAT_RGBA8888 (7 << 0) +#define R200_TXFORMAT_Y8 (8 << 0) +#define R200_TXFORMAT_AVYU4444 (9 << 0) +#define R200_TXFORMAT_VYUY422 (10 << 0) +#define R200_TXFORMAT_YVYU422 (11 << 0) +#define R200_TXFORMAT_DXT1 (12 << 0) +#define R200_TXFORMAT_DXT23 (14 << 0) +#define R200_TXFORMAT_DXT45 (15 << 0) +#define R200_TXFORMAT_ABGR8888 (22 << 0) +#define R200_TXFORMAT_FORMAT_MASK (31 << 0) +#define R200_TXFORMAT_FORMAT_SHIFT 0 +#define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +#define R200_TXFORMAT_NON_POWER2 (1 << 7) +#define R200_TXFORMAT_WIDTH_MASK (15 << 8) +#define R200_TXFORMAT_WIDTH_SHIFT 8 +#define R200_TXFORMAT_HEIGHT_MASK (15 << 12) +#define R200_TXFORMAT_HEIGHT_SHIFT 12 +#define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ +#define R200_TXFORMAT_F5_WIDTH_SHIFT 16 +#define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +#define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 +#define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) +#define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) +#define R200_TXFORMAT_ST_ROUTE_SHIFT 24 +#define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +#define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +#define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXFORMAT_X_1 0x2c28 +#define R200_PP_TXFORMAT_X_2 0x2c48 +#define R200_PP_TXFORMAT_X_3 0x2c68 +#define R200_PP_TXFORMAT_X_4 0x2c88 +#define R200_PP_TXFORMAT_X_5 0x2ca8 + +#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ +#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ +#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ +#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ +#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ + +#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ +#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ +#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ +#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ +#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ +#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ + +#define R200_PP_TXOFFSET_0 0x2d00 +#define R200_TXO_ENDIAN_NO_SWAP (0 << 0) +#define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +#define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) +#define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +#define R200_TXO_MACRO_LINEAR (0 << 2) +#define R200_TXO_MACRO_TILE (1 << 2) +#define R200_TXO_MICRO_LINEAR (0 << 3) +#define R200_TXO_MICRO_TILE (1 << 3) +#define R200_TXO_OFFSET_MASK 0xffffffe0 +#define R200_TXO_OFFSET_SHIFT 5 +#define R200_PP_TXOFFSET_1 0x2d18 +#define R200_PP_TXOFFSET_2 0x2d30 +#define R200_PP_TXOFFSET_3 0x2d48 +#define R200_PP_TXOFFSET_4 0x2d60 +#define R200_PP_TXOFFSET_5 0x2d78 + +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_PP_TFACTOR_1 0x2ee4 +#define R200_PP_TFACTOR_2 0x2ee8 +#define R200_PP_TFACTOR_3 0x2eec +#define R200_PP_TFACTOR_4 0x2ef0 +#define R200_PP_TFACTOR_5 0x2ef4 + +#define R200_PP_TXCBLEND_0 0x2f00 +#define R200_TXC_ARG_A_ZERO (0) +#define R200_TXC_ARG_A_CURRENT_COLOR (2) +#define R200_TXC_ARG_A_CURRENT_ALPHA (3) +#define R200_TXC_ARG_A_DIFFUSE_COLOR (4) +#define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) +#define R200_TXC_ARG_A_SPECULAR_COLOR (6) +#define R200_TXC_ARG_A_SPECULAR_ALPHA (7) +#define R200_TXC_ARG_A_TFACTOR_COLOR (8) +#define R200_TXC_ARG_A_TFACTOR_ALPHA (9) +#define R200_TXC_ARG_A_R0_COLOR (10) +#define R200_TXC_ARG_A_R0_ALPHA (11) +#define R200_TXC_ARG_A_R1_COLOR (12) +#define R200_TXC_ARG_A_R1_ALPHA (13) +#define R200_TXC_ARG_A_R2_COLOR (14) +#define R200_TXC_ARG_A_R2_ALPHA (15) +#define R200_TXC_ARG_A_R3_COLOR (16) +#define R200_TXC_ARG_A_R3_ALPHA (17) +#define R200_TXC_ARG_A_R4_COLOR (18) +#define R200_TXC_ARG_A_R4_ALPHA (19) +#define R200_TXC_ARG_A_R5_COLOR (20) +#define R200_TXC_ARG_A_R5_ALPHA (21) +#define R200_TXC_ARG_A_TFACTOR1_COLOR (26) +#define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) +#define R200_TXC_ARG_A_MASK (31 << 0) +#define R200_TXC_ARG_A_SHIFT 0 +#define R200_TXC_ARG_B_ZERO (0 << 5) +#define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) +#define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) +#define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) +#define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) +#define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) +#define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) +#define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) +#define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) +#define R200_TXC_ARG_B_R0_COLOR (10 << 5) +#define R200_TXC_ARG_B_R0_ALPHA (11 << 5) +#define R200_TXC_ARG_B_R1_COLOR (12 << 5) +#define R200_TXC_ARG_B_R1_ALPHA (13 << 5) +#define R200_TXC_ARG_B_R2_COLOR (14 << 5) +#define R200_TXC_ARG_B_R2_ALPHA (15 << 5) +#define R200_TXC_ARG_B_R3_COLOR (16 << 5) +#define R200_TXC_ARG_B_R3_ALPHA (17 << 5) +#define R200_TXC_ARG_B_R4_COLOR (18 << 5) +#define R200_TXC_ARG_B_R4_ALPHA (19 << 5) +#define R200_TXC_ARG_B_R5_COLOR (20 << 5) +#define R200_TXC_ARG_B_R5_ALPHA (21 << 5) +#define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) +#define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) +#define R200_TXC_ARG_B_MASK (31 << 5) +#define R200_TXC_ARG_B_SHIFT 5 +#define R200_TXC_ARG_C_ZERO (0 << 10) +#define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) +#define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) +#define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) +#define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) +#define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) +#define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) +#define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) +#define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) +#define R200_TXC_ARG_C_R0_COLOR (10 << 10) +#define R200_TXC_ARG_C_R0_ALPHA (11 << 10) +#define R200_TXC_ARG_C_R1_COLOR (12 << 10) +#define R200_TXC_ARG_C_R1_ALPHA (13 << 10) +#define R200_TXC_ARG_C_R2_COLOR (14 << 10) +#define R200_TXC_ARG_C_R2_ALPHA (15 << 10) +#define R200_TXC_ARG_C_R3_COLOR (16 << 10) +#define R200_TXC_ARG_C_R3_ALPHA (17 << 10) +#define R200_TXC_ARG_C_R4_COLOR (18 << 10) +#define R200_TXC_ARG_C_R4_ALPHA (19 << 10) +#define R200_TXC_ARG_C_R5_COLOR (20 << 10) +#define R200_TXC_ARG_C_R5_ALPHA (21 << 10) +#define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) +#define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) +#define R200_TXC_ARG_C_MASK (31 << 10) +#define R200_TXC_ARG_C_SHIFT 10 +#define R200_TXC_COMP_ARG_A (1 << 16) +#define R200_TXC_COMP_ARG_A_SHIFT (16) +#define R200_TXC_BIAS_ARG_A (1 << 17) +#define R200_TXC_SCALE_ARG_A (1 << 18) +#define R200_TXC_NEG_ARG_A (1 << 19) +#define R200_TXC_COMP_ARG_B (1 << 20) +#define R200_TXC_COMP_ARG_B_SHIFT (20) +#define R200_TXC_BIAS_ARG_B (1 << 21) +#define R200_TXC_SCALE_ARG_B (1 << 22) +#define R200_TXC_NEG_ARG_B (1 << 23) +#define R200_TXC_COMP_ARG_C (1 << 24) +#define R200_TXC_COMP_ARG_C_SHIFT (24) +#define R200_TXC_BIAS_ARG_C (1 << 25) +#define R200_TXC_SCALE_ARG_C (1 << 26) +#define R200_TXC_NEG_ARG_C (1 << 27) +#define R200_TXC_OP_MADD (0 << 28) +#define R200_TXC_OP_CND0 (2 << 28) +#define R200_TXC_OP_LERP (3 << 28) +#define R200_TXC_OP_DOT3 (4 << 28) +#define R200_TXC_OP_DOT4 (5 << 28) +#define R200_TXC_OP_CONDITIONAL (6 << 28) +#define R200_TXC_OP_DOT2_ADD (7 << 28) +#define R200_TXC_OP_MASK (7 << 28) +#define R200_PP_TXCBLEND2_0 0x2f04 +#define R200_TXC_TFACTOR_SEL_SHIFT 0 +#define R200_TXC_TFACTOR_SEL_MASK 0x7 +#define R200_TXC_TFACTOR1_SEL_SHIFT 4 +#define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) +#define R200_TXC_SCALE_SHIFT 8 +#define R200_TXC_SCALE_MASK (7 << 8) +#define R200_TXC_SCALE_1X (0 << 8) +#define R200_TXC_SCALE_2X (1 << 8) +#define R200_TXC_SCALE_4X (2 << 8) +#define R200_TXC_SCALE_8X (3 << 8) +#define R200_TXC_SCALE_INV2 (5 << 8) +#define R200_TXC_SCALE_INV4 (6 << 8) +#define R200_TXC_SCALE_INV8 (7 << 8) +#define R200_TXC_CLAMP_SHIFT 12 +#define R200_TXC_CLAMP_MASK (3 << 12) +#define R200_TXC_CLAMP_WRAP (0 << 12) +#define R200_TXC_CLAMP_0_1 (1 << 12) +#define R200_TXC_CLAMP_8_8 (2 << 12) +#define R200_TXC_OUTPUT_REG_MASK (7 << 16) +#define R200_TXC_OUTPUT_REG_NONE (0 << 16) +#define R200_TXC_OUTPUT_REG_R0 (1 << 16) +#define R200_TXC_OUTPUT_REG_R1 (2 << 16) +#define R200_TXC_OUTPUT_REG_R2 (3 << 16) +#define R200_TXC_OUTPUT_REG_R3 (4 << 16) +#define R200_TXC_OUTPUT_REG_R4 (5 << 16) +#define R200_TXC_OUTPUT_REG_R5 (6 << 16) +#define R200_TXC_OUTPUT_MASK_MASK (7 << 20) +#define R200_TXC_OUTPUT_MASK_RGB (0 << 20) +#define R200_TXC_OUTPUT_MASK_RG (1 << 20) +#define R200_TXC_OUTPUT_MASK_RB (2 << 20) +#define R200_TXC_OUTPUT_MASK_R (3 << 20) +#define R200_TXC_OUTPUT_MASK_GB (4 << 20) +#define R200_TXC_OUTPUT_MASK_G (5 << 20) +#define R200_TXC_OUTPUT_MASK_B (6 << 20) +#define R200_TXC_OUTPUT_MASK_NONE (7 << 20) +#define R200_TXC_REPL_NORMAL 0 +#define R200_TXC_REPL_RED 1 +#define R200_TXC_REPL_GREEN 2 +#define R200_TXC_REPL_BLUE 3 +#define R200_TXC_REPL_ARG_A_SHIFT 26 +#define R200_TXC_REPL_ARG_A_MASK (3 << 26) +#define R200_TXC_REPL_ARG_B_SHIFT 28 +#define R200_TXC_REPL_ARG_B_MASK (3 << 28) +#define R200_TXC_REPL_ARG_C_SHIFT 30 +#define R200_TXC_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXABLEND_0 0x2f08 +#define R200_TXA_ARG_A_ZERO (0) +#define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ +#define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ +#define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) +#define R200_TXA_ARG_A_DIFFUSE_BLUE (5) +#define R200_TXA_ARG_A_SPECULAR_ALPHA (6) +#define R200_TXA_ARG_A_SPECULAR_BLUE (7) +#define R200_TXA_ARG_A_TFACTOR_ALPHA (8) +#define R200_TXA_ARG_A_TFACTOR_BLUE (9) +#define R200_TXA_ARG_A_R0_ALPHA (10) +#define R200_TXA_ARG_A_R0_BLUE (11) +#define R200_TXA_ARG_A_R1_ALPHA (12) +#define R200_TXA_ARG_A_R1_BLUE (13) +#define R200_TXA_ARG_A_R2_ALPHA (14) +#define R200_TXA_ARG_A_R2_BLUE (15) +#define R200_TXA_ARG_A_R3_ALPHA (16) +#define R200_TXA_ARG_A_R3_BLUE (17) +#define R200_TXA_ARG_A_R4_ALPHA (18) +#define R200_TXA_ARG_A_R4_BLUE (19) +#define R200_TXA_ARG_A_R5_ALPHA (20) +#define R200_TXA_ARG_A_R5_BLUE (21) +#define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) +#define R200_TXA_ARG_A_TFACTOR1_BLUE (27) +#define R200_TXA_ARG_A_MASK (31 << 0) +#define R200_TXA_ARG_A_SHIFT 0 +#define R200_TXA_ARG_B_ZERO (0 << 5) +#define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ +#define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ +#define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) +#define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) +#define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) +#define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) +#define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) +#define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) +#define R200_TXA_ARG_B_R0_ALPHA (10 << 5) +#define R200_TXA_ARG_B_R0_BLUE (11 << 5) +#define R200_TXA_ARG_B_R1_ALPHA (12 << 5) +#define R200_TXA_ARG_B_R1_BLUE (13 << 5) +#define R200_TXA_ARG_B_R2_ALPHA (14 << 5) +#define R200_TXA_ARG_B_R2_BLUE (15 << 5) +#define R200_TXA_ARG_B_R3_ALPHA (16 << 5) +#define R200_TXA_ARG_B_R3_BLUE (17 << 5) +#define R200_TXA_ARG_B_R4_ALPHA (18 << 5) +#define R200_TXA_ARG_B_R4_BLUE (19 << 5) +#define R200_TXA_ARG_B_R5_ALPHA (20 << 5) +#define R200_TXA_ARG_B_R5_BLUE (21 << 5) +#define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) +#define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) +#define R200_TXA_ARG_B_MASK (31 << 5) +#define R200_TXA_ARG_B_SHIFT 5 +#define R200_TXA_ARG_C_ZERO (0 << 10) +#define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ +#define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ +#define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) +#define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) +#define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) +#define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) +#define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) +#define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) +#define R200_TXA_ARG_C_R0_ALPHA (10 << 10) +#define R200_TXA_ARG_C_R0_BLUE (11 << 10) +#define R200_TXA_ARG_C_R1_ALPHA (12 << 10) +#define R200_TXA_ARG_C_R1_BLUE (13 << 10) +#define R200_TXA_ARG_C_R2_ALPHA (14 << 10) +#define R200_TXA_ARG_C_R2_BLUE (15 << 10) +#define R200_TXA_ARG_C_R3_ALPHA (16 << 10) +#define R200_TXA_ARG_C_R3_BLUE (17 << 10) +#define R200_TXA_ARG_C_R4_ALPHA (18 << 10) +#define R200_TXA_ARG_C_R4_BLUE (19 << 10) +#define R200_TXA_ARG_C_R5_ALPHA (20 << 10) +#define R200_TXA_ARG_C_R5_BLUE (21 << 10) +#define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) +#define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) +#define R200_TXA_ARG_C_MASK (31 << 10) +#define R200_TXA_ARG_C_SHIFT 10 +#define R200_TXA_COMP_ARG_A (1 << 16) +#define R200_TXA_COMP_ARG_A_SHIFT (16) +#define R200_TXA_BIAS_ARG_A (1 << 17) +#define R200_TXA_SCALE_ARG_A (1 << 18) +#define R200_TXA_NEG_ARG_A (1 << 19) +#define R200_TXA_COMP_ARG_B (1 << 20) +#define R200_TXA_COMP_ARG_B_SHIFT (20) +#define R200_TXA_BIAS_ARG_B (1 << 21) +#define R200_TXA_SCALE_ARG_B (1 << 22) +#define R200_TXA_NEG_ARG_B (1 << 23) +#define R200_TXA_COMP_ARG_C (1 << 24) +#define R200_TXA_COMP_ARG_C_SHIFT (24) +#define R200_TXA_BIAS_ARG_C (1 << 25) +#define R200_TXA_SCALE_ARG_C (1 << 26) +#define R200_TXA_NEG_ARG_C (1 << 27) +#define R200_TXA_OP_MADD (0 << 28) +#define R200_TXA_OP_CND0 (2 << 28) +#define R200_TXA_OP_LERP (3 << 28) +#define R200_TXA_OP_CONDITIONAL (6 << 28) +#define R200_TXA_OP_MASK (7 << 28) +#define R200_PP_TXABLEND2_0 0x2f0c +#define R200_TXA_TFACTOR_SEL_SHIFT 0 +#define R200_TXA_TFACTOR_SEL_MASK 0x7 +#define R200_TXA_TFACTOR1_SEL_SHIFT 4 +#define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) +#define R200_TXA_SCALE_SHIFT 8 +#define R200_TXA_SCALE_MASK (7 << 8) +#define R200_TXA_SCALE_1X (0 << 8) +#define R200_TXA_SCALE_2X (1 << 8) +#define R200_TXA_SCALE_4X (2 << 8) +#define R200_TXA_SCALE_8X (3 << 8) +#define R200_TXA_SCALE_INV2 (5 << 8) +#define R200_TXA_SCALE_INV4 (6 << 8) +#define R200_TXA_SCALE_INV8 (7 << 8) +#define R200_TXA_CLAMP_SHIFT 12 +#define R200_TXA_CLAMP_MASK (3 << 12) +#define R200_TXA_CLAMP_WRAP (0 << 12) +#define R200_TXA_CLAMP_0_1 (1 << 12) +#define R200_TXA_CLAMP_8_8 (2 << 12) +#define R200_TXA_OUTPUT_REG_MASK (7 << 16) +#define R200_TXA_OUTPUT_REG_NONE (0 << 16) +#define R200_TXA_OUTPUT_REG_R0 (1 << 16) +#define R200_TXA_OUTPUT_REG_R1 (2 << 16) +#define R200_TXA_OUTPUT_REG_R2 (3 << 16) +#define R200_TXA_OUTPUT_REG_R3 (4 << 16) +#define R200_TXA_OUTPUT_REG_R4 (5 << 16) +#define R200_TXA_OUTPUT_REG_R5 (6 << 16) +#define R200_TXA_DOT_ALPHA (1 << 20) +#define R200_TXA_REPL_NORMAL 0 +#define R200_TXA_REPL_RED 1 +#define R200_TXA_REPL_GREEN 2 +#define R200_TXA_REPL_ARG_A_SHIFT 26 +#define R200_TXA_REPL_ARG_A_MASK (3 << 26) +#define R200_TXA_REPL_ARG_B_SHIFT 28 +#define R200_TXA_REPL_ARG_B_MASK (3 << 28) +#define R200_TXA_REPL_ARG_C_SHIFT 30 +#define R200_TXA_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXCBLEND_1 0x2f10 +#define R200_PP_TXCBLEND2_1 0x2f14 +#define R200_PP_TXABLEND_1 0x2f18 +#define R200_PP_TXABLEND2_1 0x2f1c +#define R200_PP_TXCBLEND_2 0x2f20 +#define R200_PP_TXCBLEND2_2 0x2f24 +#define R200_PP_TXABLEND_2 0x2f28 +#define R200_PP_TXABLEND2_2 0x2f2c +#define R200_PP_TXCBLEND_3 0x2f30 +#define R200_PP_TXCBLEND2_3 0x2f34 +#define R200_PP_TXABLEND_3 0x2f38 +#define R200_PP_TXABLEND2_3 0x2f3c + +#define R200_SE_VTX_FMT_0 0x2088 +#define R200_VTX_XY 0 /* always have xy */ +#define R200_VTX_Z0 (1<<0) +#define R200_VTX_W0 (1<<1) +#define R200_VTX_WEIGHT_COUNT_SHIFT (2) +#define R200_VTX_PV_MATRIX_SEL (1<<5) +#define R200_VTX_N0 (1<<6) +#define R200_VTX_POINT_SIZE (1<<7) +#define R200_VTX_DISCRETE_FOG (1<<8) +#define R200_VTX_SHININESS_0 (1<<9) +#define R200_VTX_SHININESS_1 (1<<10) +#define R200_VTX_COLOR_NOT_PRESENT 0 +#define R200_VTX_PK_RGBA 1 +#define R200_VTX_FP_RGB 2 +#define R200_VTX_FP_RGBA 3 +#define R200_VTX_COLOR_MASK 3 +#define R200_VTX_COLOR_0_SHIFT 11 +#define R200_VTX_COLOR_1_SHIFT 13 +#define R200_VTX_COLOR_2_SHIFT 15 +#define R200_VTX_COLOR_3_SHIFT 17 +#define R200_VTX_COLOR_4_SHIFT 19 +#define R200_VTX_COLOR_5_SHIFT 21 +#define R200_VTX_COLOR_6_SHIFT 23 +#define R200_VTX_COLOR_7_SHIFT 25 +#define R200_VTX_XY1 (1<<28) +#define R200_VTX_Z1 (1<<29) +#define R200_VTX_W1 (1<<30) +#define R200_VTX_N1 (1<<31) +#define R200_SE_VTX_FMT_1 0x208c +#define R200_VTX_TEX0_COMP_CNT_SHIFT 0 +#define R200_VTX_TEX1_COMP_CNT_SHIFT 3 +#define R200_VTX_TEX2_COMP_CNT_SHIFT 6 +#define R200_VTX_TEX3_COMP_CNT_SHIFT 9 +#define R200_VTX_TEX4_COMP_CNT_SHIFT 12 +#define R200_VTX_TEX5_COMP_CNT_SHIFT 15 + +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +#define R200_OUTPUT_XYZW (1<<0) +#define R200_OUTPUT_COLOR_0 (1<<8) +#define R200_OUTPUT_COLOR_1 (1<<9) +#define R200_OUTPUT_TEX_0 (1<<16) +#define R200_OUTPUT_TEX_1 (1<<17) +#define R200_OUTPUT_TEX_2 (1<<18) +#define R200_OUTPUT_TEX_3 (1<<19) +#define R200_OUTPUT_TEX_4 (1<<20) +#define R200_OUTPUT_TEX_5 (1<<21) +#define R200_OUTPUT_TEX_MASK (0x3f<<16) +#define R200_OUTPUT_DISCRETE_FOG (1<<24) +#define R200_OUTPUT_PT_SIZE (1<<25) +#define R200_FORCE_INORDER_PROC (1<<31) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +#define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) + +/* Registers for CP and Microcode Engine */ +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_IB_BASE 0x0738 +#define RADEON_CP_IB_BUFSZ 0x073c + +#define RADEON_CP_CSQ_CNTL 0x0740 +#define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +#define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +#define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +#define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +#define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +#define RADEON_CSQ_PRIBM_INDBM (4 << 28) +#define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) +#define RADEON_CP_CSQ_STAT 0x07f8 +#define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) +#define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) +#define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) +#define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) +#define RADEON_CP_CSQ_ADDR 0x07f0 +#define RADEON_CP_CSQ_DATA 0x07f4 +#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 +#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +#define RADEON_PRE_WRITE_TIMER_SHIFT 0 +#define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_AIC_CNTL 0x01d0 +#define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +#define RADEON_AIC_LO_ADDR 0x01dc + +/* Constants */ +#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 +#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 + +/* CP packet types */ +#define RADEON_CP_PACKET0 0x00000000 +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 +#define RADEON_CP_PACKET_MASK 0xC0000000 +#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +#define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) +#define RADEON_CP_PACKET0_REG_MASK 0x000007ff +#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff +#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + + +#define RADEON_CP_VC_FRMT_XY 0x00000000 +#define RADEON_CP_VC_FRMT_W0 0x00000001 +#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 +#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 +#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 +#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 +#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 +#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 +#define RADEON_CP_VC_FRMT_ST0 0x00000080 +#define RADEON_CP_VC_FRMT_ST1 0x00000100 +#define RADEON_CP_VC_FRMT_Q1 0x00000200 +#define RADEON_CP_VC_FRMT_ST2 0x00000400 +#define RADEON_CP_VC_FRMT_Q2 0x00000800 +#define RADEON_CP_VC_FRMT_ST3 0x00001000 +#define RADEON_CP_VC_FRMT_Q3 0x00002000 +#define RADEON_CP_VC_FRMT_Q0 0x00004000 +#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 +#define RADEON_CP_VC_FRMT_N0 0x00040000 +#define RADEON_CP_VC_FRMT_XY1 0x08000000 +#define RADEON_CP_VC_FRMT_Z1 0x10000000 +#define RADEON_CP_VC_FRMT_W1 0x20000000 +#define RADEON_CP_VC_FRMT_N1 0x40000000 +#define RADEON_CP_VC_FRMT_Z 0x80000000 + +#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a +#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d +#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 +#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 +#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 +#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 +#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 +#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 +#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 + +#define RADEON_VS_MATRIX_0_ADDR 0 +#define RADEON_VS_MATRIX_1_ADDR 4 +#define RADEON_VS_MATRIX_2_ADDR 8 +#define RADEON_VS_MATRIX_3_ADDR 12 +#define RADEON_VS_MATRIX_4_ADDR 16 +#define RADEON_VS_MATRIX_5_ADDR 20 +#define RADEON_VS_MATRIX_6_ADDR 24 +#define RADEON_VS_MATRIX_7_ADDR 28 +#define RADEON_VS_MATRIX_8_ADDR 32 +#define RADEON_VS_MATRIX_9_ADDR 36 +#define RADEON_VS_MATRIX_10_ADDR 40 +#define RADEON_VS_MATRIX_11_ADDR 44 +#define RADEON_VS_MATRIX_12_ADDR 48 +#define RADEON_VS_MATRIX_13_ADDR 52 +#define RADEON_VS_MATRIX_14_ADDR 56 +#define RADEON_VS_MATRIX_15_ADDR 60 +#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 +#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 +#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 +#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 +#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 +#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 +#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 +#define RADEON_VS_UCP_ADDR 116 +#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 +#define RADEON_VS_FOG_PARAM_ADDR 123 +#define RADEON_VS_EYE_VECTOR_ADDR 124 + +#define RADEON_SS_LIGHT_DCD_ADDR 0 +#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 +#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 +#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 +#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 +#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 +#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 +#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 +#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 +#define RADEON_SS_SHININESS 60 + +#define RADEON_TV_MASTER_CNTL 0x0800 +#define RADEON_TV_ASYNC_RST (1 << 0) +#define RADEON_CRT_ASYNC_RST (1 << 1) +#define RADEON_RESTART_PHASE_FIX (1 << 3) +#define RADEON_TV_FIFO_ASYNC_RST (1 << 4) +#define RADEON_VIN_ASYNC_RST (1 << 5) +#define RADEON_AUD_ASYNC_RST (1 << 6) +#define RADEON_DVS_ASYNC_RST (1 << 7) +#define RADEON_CRT_FIFO_CE_EN (1 << 9) +#define RADEON_TV_FIFO_CE_EN (1 << 10) +#define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) +#define RADEON_TVCLK_ALWAYS_ONb (1 << 30) +#define RADEON_TV_ON (1 << 31) +#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 +#define RADEON_Y_RED_EN (1 << 0) +#define RADEON_C_GRN_EN (1 << 1) +#define RADEON_CMP_BLU_EN (1 << 2) +#define RADEON_DAC_DITHER_EN (1 << 3) +#define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) +#define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) +#define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) +#define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 +#define RADEON_TV_RGB_CNTL 0x0804 +#define RADEON_SWITCH_TO_BLUE (1 << 4) +#define RADEON_RGB_DITHER_EN (1 << 5) +#define RADEON_RGB_SRC_SEL_MASK (3 << 8) +#define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) +#define RADEON_RGB_SRC_SEL_RMX (1 << 8) +#define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) +#define RADEON_RGB_CONVERT_BY_PASS (1 << 10) +#define RADEON_UVRAM_READ_MARGIN_SHIFT 16 +#define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 +#define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) +#define RADEON_TVOUT_SCALE_EN (1 << 26) +#define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) +#define RADEON_TV_SYNC_CNTL 0x0808 +#define RADEON_SYNC_OE (1 << 0) +#define RADEON_SYNC_OUT (1 << 1) +#define RADEON_SYNC_IN (1 << 2) +#define RADEON_SYNC_PUB (1 << 3) +#define RADEON_SYNC_PD (1 << 4) +#define RADEON_TV_SYNC_IO_DRIVE (1 << 5) +#define RADEON_TV_HTOTAL 0x080c +#define RADEON_TV_HDISP 0x0810 +#define RADEON_TV_HSTART 0x0818 +#define RADEON_TV_HCOUNT 0x081C +#define RADEON_TV_VTOTAL 0x0820 +#define RADEON_TV_VDISP 0x0824 +#define RADEON_TV_VCOUNT 0x0828 +#define RADEON_TV_FTOTAL 0x082c +#define RADEON_TV_FCOUNT 0x0830 +#define RADEON_TV_FRESTART 0x0834 +#define RADEON_TV_HRESTART 0x0838 +#define RADEON_TV_VRESTART 0x083c +#define RADEON_TV_HOST_READ_DATA 0x0840 +#define RADEON_TV_HOST_WRITE_DATA 0x0844 +#define RADEON_TV_HOST_RD_WT_CNTL 0x0848 +#define RADEON_HOST_FIFO_RD (1 << 12) +#define RADEON_HOST_FIFO_RD_ACK (1 << 13) +#define RADEON_HOST_FIFO_WT (1 << 14) +#define RADEON_HOST_FIFO_WT_ACK (1 << 15) +#define RADEON_TV_VSCALER_CNTL1 0x084c +#define RADEON_UV_INC_MASK 0xffff +#define RADEON_UV_INC_SHIFT 0 +#define RADEON_Y_W_EN (1 << 24) +#define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ +#define RADEON_Y_DEL_W_SIG_SHIFT 26 +#define RADEON_TV_TIMING_CNTL 0x0850 +#define RADEON_H_INC_MASK 0xfff +#define RADEON_H_INC_SHIFT 0 +#define RADEON_REQ_Y_FIRST (1 << 19) +#define RADEON_FORCE_BURST_ALWAYS (1 << 21) +#define RADEON_UV_POST_SCALE_BYPASS (1 << 23) +#define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 +#define RADEON_TV_VSCALER_CNTL2 0x0854 +#define RADEON_DITHER_MODE (1 << 0) +#define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) +#define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) +#define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) +#define RADEON_TV_Y_FALL_CNTL 0x0858 +#define RADEON_Y_FALL_PING_PONG (1 << 16) +#define RADEON_Y_COEF_EN (1 << 17) +#define RADEON_TV_Y_RISE_CNTL 0x085c +#define RADEON_Y_RISE_PING_PONG (1 << 16) +#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 +#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 +#define RADEON_YUPSAMP_EN (1 << 0) +#define RADEON_UVUPSAMP_EN (1 << 2) +#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 +#define RADEON_Y_GAIN_LIMIT_SHIFT 0 +#define RADEON_UV_GAIN_LIMIT_SHIFT 16 +#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c +#define RADEON_Y_GAIN_SHIFT 0 +#define RADEON_UV_GAIN_SHIFT 16 +#define RADEON_TV_MODULATOR_CNTL1 0x0870 +#define RADEON_YFLT_EN (1 << 2) +#define RADEON_UVFLT_EN (1 << 3) +#define RADEON_ALT_PHASE_EN (1 << 6) +#define RADEON_SYNC_TIP_LEVEL (1 << 7) +#define RADEON_BLANK_LEVEL_SHIFT 8 +#define RADEON_SET_UP_LEVEL_SHIFT 16 +#define RADEON_SLEW_RATE_LIMIT (1 << 23) +#define RADEON_CY_FILT_BLEND_SHIFT 28 +#define RADEON_TV_MODULATOR_CNTL2 0x0874 +#define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff +#define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff +#define RADEON_TV_V_BURST_LEVEL_SHIFT 16 +#define RADEON_TV_CRC_CNTL 0x0890 +#define RADEON_TV_UV_ADR 0x08ac +#define RADEON_MAX_UV_ADR_MASK 0x000000ff +#define RADEON_MAX_UV_ADR_SHIFT 0 +#define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 +#define RADEON_TABLE1_BOT_ADR_SHIFT 8 +#define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 +#define RADEON_TABLE3_TOP_ADR_SHIFT 16 +#define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 +#define RADEON_HCODE_TABLE_SEL_SHIFT 25 +#define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 +#define RADEON_VCODE_TABLE_SEL_SHIFT 27 +#define RADEON_TV_MAX_FIFO_ADDR 0x1a7 +#define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff +#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ +#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ +#define RADEON_TV_M0LO_MASK 0xff +#define RADEON_TV_M0HI_MASK 0x7 +#define RADEON_TV_M0HI_SHIFT 18 +#define RADEON_TV_N0LO_MASK 0x1ff +#define RADEON_TV_N0LO_SHIFT 8 +#define RADEON_TV_N0HI_MASK 0x3 +#define RADEON_TV_N0HI_SHIFT 21 +#define RADEON_TV_P_MASK 0xf +#define RADEON_TV_P_SHIFT 24 +#define RADEON_TV_SLIP_EN (1 << 23) +#define RADEON_TV_DTO_EN (1 << 28) +#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ +#define RADEON_TVPLL_RESET (1 << 1) +#define RADEON_TVPLL_SLEEP (1 << 3) +#define RADEON_TVPLL_REFCLK_SEL (1 << 4) +#define RADEON_TVPCP_SHIFT 8 +#define RADEON_TVPCP_MASK (7 << 8) +#define RADEON_TVPVG_SHIFT 11 +#define RADEON_TVPVG_MASK (7 << 11) +#define RADEON_TVPDC_SHIFT 14 +#define RADEON_TVPDC_MASK (3 << 14) +#define RADEON_TVPLL_TEST_DIS (1 << 31) +#define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) + +#define RS400_DISP2_REQ_CNTL1 0xe30 +#define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 +#define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff +#define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 +#define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff +#define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 +#define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff +#define RS400_DISP2_REQ_CNTL2 0xe34 +#define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 +#define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff +#define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 +#define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff +#define RS400_DMIF_MEM_CNTL1 0xe38 +#define RS400_DISP2_START_ADR_SHIFT 0 +#define RS400_DISP2_START_ADR_MASK 0x3ff +#define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 +#define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff +#define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 +#define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff +#define RS400_DISP1_REQ_CNTL1 0xe3c +#define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 +#define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff +#define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 +#define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff +#define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 +#define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff + +#define RS690_MC_INDEX 0x78 +#define RS690_MC_INDEX_MASK 0x1ff +#define RS690_MC_INDEX_WR_EN (1 << 9) +#define RS690_MC_INDEX_WR_ACK 0x7f +#define RS690_MC_DATA 0x7c + +#define RS690_MC_FB_LOCATION 0x100 +#define RS690_MC_AGP_LOCATION 0x101 +#define RS690_MC_AGP_BASE 0x102 +#define RS690_MC_AGP_BASE_2 0x103 +#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 +#define RS690_MC_STATUS 0x90 +#define RS690_MC_STATUS_IDLE (1 << 0) + +#define RS600_MC_INDEX 0x70 +#define RS600_MC_ADDR_MASK 0xffff +#define RS600_MC_IND_SEQ_RBS_0 (1 << 16) +#define RS600_MC_IND_SEQ_RBS_1 (1 << 17) +#define RS600_MC_IND_SEQ_RBS_2 (1 << 18) +#define RS600_MC_IND_SEQ_RBS_3 (1 << 19) +#define RS600_MC_IND_AIC_RBS (1 << 20) +#define RS600_MC_IND_CITF_ARB0 (1 << 21) +#define RS600_MC_IND_CITF_ARB1 (1 << 22) +#define RS600_MC_IND_WR_EN (1 << 23) +#define RS600_MC_DATA 0x74 + +#define RS600_MC_STATUS 0x0 +#define RS600_MC_IDLE (1 << 1) +#define RS600_MC_FB_LOCATION 0x4 +#define RS600_MC_AGP_LOCATION 0x5 +#define RS600_AGP_BASE 0x6 +#define RS600_AGP_BASE2 0x7 + +#define AVIVO_MC_INDEX 0x0070 +#define R520_MC_STATUS 0x00 +#define R520_MC_STATUS_IDLE (1 << 1) +#define RV515_MC_STATUS 0x08 +#define RV515_MC_STATUS_IDLE (1 << 4) +#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 +#define AVIVO_MC_DATA 0x0074 + +#define RV515_MC_FB_LOCATION 0x1 +#define RV515_MC_AGP_LOCATION 0x2 +#define RV515_MC_AGP_BASE 0x3 +#define RV515_MC_AGP_BASE_2 0x4 +#define RV515_MC_CNTL 0x5 +#define RV515_MEM_NUM_CHANNELS_MASK 0x3 +#define R520_MC_FB_LOCATION 0x4 +#define R520_MC_AGP_LOCATION 0x5 +#define R520_MC_AGP_BASE 0x6 +#define R520_MC_AGP_BASE_2 0x7 +#define R520_MC_CNTL0 0x8 +#define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) +#define R520_MEM_NUM_CHANNELS_SHIFT 24 +#define R520_MC_CHANNEL_SIZE (1 << 23) + +#define RS780_MC_INDEX 0x28f8 +#define RS780_MC_INDEX_MASK 0x1ff +#define RS780_MC_INDEX_WR_EN (1 << 9) +#define RS780_MC_DATA 0x28fc + +#define R600_RAMCFG 0x2408 +#define R600_CHANSIZE (1 << 7) +#define R600_CHANSIZE_OVERRIDE (1 << 10) + +#define R600_SRBM_STATUS 0x0e50 + +#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ +#define AVIVO_CP_FORCEON (1 << 0) +#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ +#define AVIVO_E2_FORCEON (1 << 0) +#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ +#define AVIVO_IDCT_FORCEON (1 << 0) + +#define AVIVO_HDP_FB_LOCATION 0x134 + +#define AVIVO_VGA_RENDER_CONTROL 0x0300 +#define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) +#define AVIVO_D1VGA_CONTROL 0x0330 +#define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) +#define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) +#define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) +#define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) +#define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) +#define AVIVO_DVGA_CONTROL_ROTATE (1<<24) +#define AVIVO_D2VGA_CONTROL 0x0338 + +#define AVIVO_VGA25_PPLL_REF_DIV_SRC 0x0360 +#define AVIVO_VGA25_PPLL_REF_DIV 0x0364 +#define AVIVO_VGA28_PPLL_REF_DIV_SRC 0x0368 +#define AVIVO_VGA28_PPLL_REF_DIV 0x036c +#define AVIVO_VGA41_PPLL_REF_DIV_SRC 0x0370 +#define AVIVO_VGA41_PPLL_REF_DIV 0x0374 +#define AVIVO_VGA25_PPLL_FB_DIV 0x0378 +#define AVIVO_VGA28_PPLL_FB_DIV 0x037c +#define AVIVO_VGA41_PPLL_FB_DIV 0x0380 +#define AVIVO_VGA25_PPLL_POST_DIV_SRC 0x0384 +#define AVIVO_VGA25_PPLL_POST_DIV 0x0388 +#define AVIVO_VGA28_PPLL_POST_DIV_SRC 0x038c +#define AVIVO_VGA28_PPLL_POST_DIV 0x0390 +#define AVIVO_VGA41_PPLL_POST_DIV_SRC 0x0394 +#define AVIVO_VGA41_PPLL_POST_DIV 0x0398 +#define AVIVO_VGA25_PPLL_CNTL 0x039c +#define AVIVO_VGA28_PPLL_CNTL 0x03a0 +#define AVIVO_VGA41_PPLL_CNTL 0x03a4 + +#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 +#define AVIVO_EXT1_PPLL_REF_DIV 0x404 +#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 +#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c + +#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 +#define AVIVO_EXT2_PPLL_REF_DIV 0x414 +#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 +#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c + +#define AVIVO_EXT1_PPLL_FB_DIV 0x430 +#define AVIVO_EXT2_PPLL_FB_DIV 0x434 + +#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 +#define AVIVO_EXT1_PPLL_POST_DIV 0x43c + +#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 +#define AVIVO_EXT2_PPLL_POST_DIV 0x444 + +#define AVIVO_EXT1_PPLL_CNTL 0x448 +#define AVIVO_EXT2_PPLL_CNTL 0x44c + +#define AVIVO_P1PLL_CNTL 0x450 +#define AVIVO_P2PLL_CNTL 0x454 +#define AVIVO_P1PLL_INT_SS_CNTL 0x458 +#define AVIVO_P2PLL_INT_SS_CNTL 0x45c +#define AVIVO_P1PLL_TMDSA_CNTL 0x460 +#define AVIVO_P2PLL_LVTMA_CNTL 0x464 + +#define AVIVO_PCLK_CRTC1_CNTL 0x480 +#define AVIVO_PCLK_CRTC2_CNTL 0x484 + +#define AVIVO_D1CRTC_H_TOTAL 0x6000 +#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 +#define AVIVO_D1CRTC_H_SYNC_A 0x6008 +#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c +#define AVIVO_D1CRTC_H_SYNC_B 0x6010 +#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 + +#define AVIVO_D1CRTC_V_TOTAL 0x6020 +#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 +#define AVIVO_D1CRTC_V_SYNC_A 0x6028 +#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c +#define AVIVO_D1CRTC_V_SYNC_B 0x6030 +#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 + +#define AVIVO_D1CRTC_CONTROL 0x6080 +#define AVIVO_CRTC_EN (1<<0) +#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 +#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 +#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c +#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 + +/* master controls */ +#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 +#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc + +#define AVIVO_D1GRPH_ENABLE 0x6100 +#define AVIVO_D1GRPH_CONTROL 0x6104 +#define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) +#define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) +#define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) +#define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) + +#define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) + +#define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) +#define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) +#define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) +#define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) +#define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) + +#define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) +#define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) +#define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) +#define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) + + +#define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) + +#define AVIVO_D1GRPH_SWAP_RB (1<<16) +#define AVIVO_D1GRPH_TILED (1<<20) +#define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) + +#define AVIVO_D1GRPH_LUT_SEL 0x6108 + +#define R600_D1GRPH_SWAP_CONTROL 0x610C +#define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) +#define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) +#define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) +#define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) + +/* + * the *_HIGH surface regs are backwards; the D1 regs are in the D2 + * block and vice versa. This applies to GRPH, CUR, etc. + */ +#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 +#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 +#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 +#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c +#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c +#define AVIVO_D1GRPH_PITCH 0x6120 +#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 +#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 +#define AVIVO_D1GRPH_X_START 0x612c +#define AVIVO_D1GRPH_Y_START 0x6130 +#define AVIVO_D1GRPH_X_END 0x6134 +#define AVIVO_D1GRPH_Y_END 0x6138 +#define AVIVO_D1GRPH_UPDATE 0x6144 +#define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) +#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 + +#define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380 + +#define AVIVO_D1CUR_CONTROL 0x6400 +#define AVIVO_D1CURSOR_EN (1<<0) +#define AVIVO_D1CURSOR_MODE_SHIFT 8 +#define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) +#define AVIVO_D1CURSOR_MODE_24BPP (0x2) +#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 +#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c +#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c +#define AVIVO_D1CUR_SIZE 0x6410 +#define AVIVO_D1CUR_POSITION 0x6414 +#define AVIVO_D1CUR_HOT_SPOT 0x6418 +#define AVIVO_D1CUR_UPDATE 0x6424 +#define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) + +#define AVIVO_DC_LUT_RW_SELECT 0x6480 +#define AVIVO_DC_LUT_RW_MODE 0x6484 +#define AVIVO_DC_LUT_RW_INDEX 0x6488 +#define AVIVO_DC_LUT_SEQ_COLOR 0x648c +#define AVIVO_DC_LUT_PWL_DATA 0x6490 +#define AVIVO_DC_LUT_30_COLOR 0x6494 +#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 +#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c +#define AVIVO_DC_LUT_AUTOFILL 0x64a0 + +#define AVIVO_DC_LUTA_CONTROL 0x64c0 +#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 +#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 +#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc +#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 +#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 +#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 + +#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 +#define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 +#define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 +#define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 +#define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 +#define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 +#define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 +#define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) +#define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 +#define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff +#define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548 +#define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff +#define AVIVO_DxMODE_PRIORITY_OFF (1 << 16) +#define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20) +#define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24) +#define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c +#define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48 +#define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c +#define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58 +#define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf +#define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 +#define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf +#define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 + +#define AVIVO_D1MODE_DATA_FORMAT 0x6528 +#define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) +#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c +#define AVIVO_D1MODE_VLINE_START_END 0x6538 +#define AVIVO_D1MODE_VLINE_START_SHIFT 0 +#define AVIVO_D1MODE_VLINE_END_SHIFT 16 +#define AVIVO_D1MODE_VLINE_INV (1 << 31) +#define AVIVO_D1MODE_VLINE_STATUS 0x653c +#define AVIVO_D1MODE_VLINE_STAT (1 << 12) +#define AVIVO_D1MODE_VIEWPORT_START 0x6580 +#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 +#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 +#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c + +#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 +#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 +#define AVIVO_D1SCL_UPDATE 0x65cc +#define AVIVO_D1SCL_UPDATE_LOCK (1<<16) + +/* second crtc */ +#define AVIVO_D2CRTC_H_TOTAL 0x6800 +#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 +#define AVIVO_D2CRTC_H_SYNC_A 0x6808 +#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c +#define AVIVO_D2CRTC_H_SYNC_B 0x6810 +#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 + +#define AVIVO_D2CRTC_V_TOTAL 0x6820 +#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 +#define AVIVO_D2CRTC_V_SYNC_A 0x6828 +#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c +#define AVIVO_D2CRTC_V_SYNC_B 0x6830 +#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 + +#define AVIVO_D2CRTC_CONTROL 0x6880 +#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 +#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 +#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c +#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 + +#define AVIVO_D2GRPH_ENABLE 0x6900 +#define AVIVO_D2GRPH_CONTROL 0x6904 +#define AVIVO_D2GRPH_LUT_SEL 0x6908 +#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 +#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 +#define AVIVO_D2GRPH_PITCH 0x6920 +#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 +#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 +#define AVIVO_D2GRPH_X_START 0x692c +#define AVIVO_D2GRPH_Y_START 0x6930 +#define AVIVO_D2GRPH_X_END 0x6934 +#define AVIVO_D2GRPH_Y_END 0x6938 +#define AVIVO_D2GRPH_UPDATE 0x6944 +#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 + +#define AVIVO_D2CUR_CONTROL 0x6c00 +#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 +#define AVIVO_D2CUR_SIZE 0x6c10 +#define AVIVO_D2CUR_POSITION 0x6c14 + +#define RS690_DCP_CONTROL 0x6c9c + +#define AVIVO_D2MODE_DATA_FORMAT 0x6d28 +#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c +#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 +#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 +#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 +#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c + +#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 +#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 +#define AVIVO_D2SCL_UPDATE 0x6dcc + +#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 + +#define AVIVO_DACA_ENABLE 0x7800 +#define AVIVO_DAC_ENABLE (1 << 0) +#define AVIVO_DACA_SOURCE_SELECT 0x7804 +#define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) +#define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) +#define AVIVO_DAC_SOURCE_TV (2 << 0) + +#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c +#define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACA_POWERDOWN 0x7850 +#define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) +#define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) +#define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) +#define AVIVO_DACA_POWERDOWN_RED (1 << 24) + +#define AVIVO_DACB_ENABLE 0x7a00 +#define AVIVO_DACB_SOURCE_SELECT 0x7a04 +#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c +#define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACB_POWERDOWN 0x7a50 +#define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) +#define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) +#define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) +#define AVIVO_DACB_POWERDOWN_RED + +#define AVIVO_TMDSA_CNTL 0x7880 +#define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) +#define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) +#define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) +#define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) +#define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) +#define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) +#define AVIVO_TMDSA_CNTL_SWAP (1 << 28) +#define AVIVO_TMDSA_SOURCE_SELECT ß 0x7884 +/* 78a8 appears to be some kind of (reasonably tolerant) clock? + * 78d0 definitely hits the transmitter, definitely clock. */ +/* MYSTERY1 This appears to control dithering? */ +#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) +#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 +#define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) +#define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +#define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +#define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) +#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 +#define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +#define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 +#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +#define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define AVIVO_LVTMA_CNTL 0x7a80 +#define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) +#define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) +#define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) +#define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) +#define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) +#define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) +#define AVIVO_LVTMA_CNTL_SWAP (1 << 28) +#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 +#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) + + + +#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 +#define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) +#define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +#define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +#define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) + +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define R500_LVTMA_CLOCK_ENABLE 0x7b00 +#define R600_LVTMA_CLOCK_ENABLE 0x7b04 + +#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 +#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 +#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +#define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 +#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 +#define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) +#define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) +#define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) +#define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) +#define AVIVO_LVTMA_SYNCEN (1 << 8) +#define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) +#define AVIVO_LVTMA_SYNCEN_POL (1 << 10) +#define AVIVO_LVTMA_DIGON (1 << 16) +#define AVIVO_LVTMA_DIGON_OVRD (1 << 17) +#define AVIVO_LVTMA_DIGON_POL (1 << 18) +#define AVIVO_LVTMA_BLON (1 << 24) +#define AVIVO_LVTMA_BLON_OVRD (1 << 25) +#define AVIVO_LVTMA_BLON_POL (1 << 26) + +#define R500_LVTMA_PWRSEQ_STATE 0x7af4 +#define R600_LVTMA_PWRSEQ_STATE 0x7af8 +#define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) +#define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) +#define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) +#define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) +#define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) +#define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) + +#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 +#define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) +#define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 +#define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 + +#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 + +#define AVIVO_GPIO_0 0x7e30 +#define AVIVO_GPIO_1 0x7e40 +#define AVIVO_GPIO_2 0x7e50 +#define AVIVO_GPIO_3 0x7e60 + +#define AVIVO_DC_GPIO_HPD_MASK 0x7e90 +#define AVIVO_DC_GPIO_HPD_A 0x7e94 +#define AVIVO_DC_GPIO_HPD_EN 0x7e98 +#define AVIVO_DC_GPIO_HPD_Y 0x7e9c + +#define AVIVO_I2C_STATUS 0x7d30 +#define AVIVO_I2C_STATUS_DONE (1 << 0) +#define AVIVO_I2C_STATUS_NACK (1 << 1) +#define AVIVO_I2C_STATUS_HALT (1 << 2) +#define AVIVO_I2C_STATUS_GO (1 << 3) +#define AVIVO_I2C_STATUS_MASK 0x7 +/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe + * DONE? */ +#define AVIVO_I2C_STATUS_CMD_RESET 0x7 +#define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) +#define AVIVO_I2C_STOP 0x7d34 +#define AVIVO_I2C_START_CNTL 0x7d38 +#define AVIVO_I2C_START (1 << 8) +#define AVIVO_I2C_CONNECTOR0 (0 << 16) +#define AVIVO_I2C_CONNECTOR1 (1 << 16) +#define R520_I2C_START (1<<0) +#define R520_I2C_STOP (1<<1) +#define R520_I2C_RX (1<<2) +#define R520_I2C_EN (1<<8) +#define R520_I2C_DDC1 (0<<16) +#define R520_I2C_DDC2 (1<<16) +#define R520_I2C_DDC3 (2<<16) +#define R520_I2C_DDC_MASK (3<<16) +#define AVIVO_I2C_CONTROL2 0x7d3c +#define AVIVO_I2C_7D3C_SIZE_SHIFT 8 +#define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) +#define AVIVO_I2C_CONTROL3 0x7d40 +/* Reading is done 4 bytes at a time: read the bottom 8 bits from + * 7d44, four times in a row. + * Writing is a little more complex. First write DATA with + * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic + * magic number, zz is, I think, the slave address, and yy is the byte + * you want to write. */ +#define AVIVO_I2C_DATA 0x7d44 +#define R520_I2C_ADDR_COUNT_MASK (0x7) +#define R520_I2C_DATA_COUNT_SHIFT (8) +#define R520_I2C_DATA_COUNT_MASK (0xF00) +#define AVIVO_I2C_CNTL 0x7d50 +#define AVIVO_I2C_EN (1 << 0) +#define AVIVO_I2C_RESET (1 << 8) + +#define R600_GENERAL_PWRMGT 0x618 +#define R600_OPEN_DRAIN_PADS (1 << 11) + +#define R600_LOWER_GPIO_ENABLE 0x710 +#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 +#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c +#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 +#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 + +#define R600_MC_VM_FB_LOCATION 0x2180 +#define R600_MC_VM_AGP_TOP 0x2184 +#define R600_MC_VM_AGP_BOT 0x2188 +#define R600_MC_VM_AGP_BASE 0x218c +#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 +#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 +#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 + +#define R700_MC_VM_FB_LOCATION 0x2024 +#define R700_MC_VM_AGP_TOP 0x2028 +#define R700_MC_VM_AGP_BOT 0x202c +#define R700_MC_VM_AGP_BASE 0x2030 + +#define R600_HDP_NONSURFACE_BASE 0x2c04 + +#define R600_BUS_CNTL 0x5420 +#define R600_CONFIG_CNTL 0x5424 +#define R600_CONFIG_MEMSIZE 0x5428 +#define R600_CONFIG_F0_BASE 0x542C +#define R600_CONFIG_APER_SIZE 0x5430 + +#define R600_ROM_CNTL 0x1600 +#define R600_SCK_OVERWRITE (1 << 1) +#define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 +#define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) + +#define R600_CG_SPLL_FUNC_CNTL 0x600 +#define R600_SPLL_BYPASS_EN (1 << 3) +#define R600_CG_SPLL_STATUS 0x60c +#define R600_SPLL_CHG_STATUS (1 << 1) + +#define R600_BIOS_0_SCRATCH 0x1724 +#define R600_BIOS_1_SCRATCH 0x1728 +#define R600_BIOS_2_SCRATCH 0x172c +#define R600_BIOS_3_SCRATCH 0x1730 +#define R600_BIOS_4_SCRATCH 0x1734 +#define R600_BIOS_5_SCRATCH 0x1738 +#define R600_BIOS_6_SCRATCH 0x173c +#define R600_BIOS_7_SCRATCH 0x1740 + +/* evergreen */ +#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 +#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 +#define EVERGREEN_D3VGA_CONTROL 0x3e0 +#define EVERGREEN_D4VGA_CONTROL 0x3e4 +#define EVERGREEN_D5VGA_CONTROL 0x3e8 +#define EVERGREEN_D6VGA_CONTROL 0x3ec + +#define EVERGREEN_P1PLL_SS_CNTL 0x414 +#define EVERGREEN_P2PLL_SS_CNTL 0x454 +#define EVERGREEN_PxPLL_SS_EN (1 << 12) +/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ +#define EVERGREEN_GRPH_ENABLE 0x6800 +#define EVERGREEN_GRPH_CONTROL 0x6804 +#define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) +#define EVERGREEN_GRPH_DEPTH_8BPP 0 +#define EVERGREEN_GRPH_DEPTH_16BPP 1 +#define EVERGREEN_GRPH_DEPTH_32BPP 2 +#define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) +/* 8 BPP */ +#define EVERGREEN_GRPH_FORMAT_INDEXED 0 +/* 16 BPP */ +#define EVERGREEN_GRPH_FORMAT_ARGB1555 0 +#define EVERGREEN_GRPH_FORMAT_ARGB565 1 +#define EVERGREEN_GRPH_FORMAT_ARGB4444 2 +#define EVERGREEN_GRPH_FORMAT_AI88 3 +#define EVERGREEN_GRPH_FORMAT_MONO16 4 +#define EVERGREEN_GRPH_FORMAT_BGRA5551 5 +/* 32 BPP */ +#define EVERGREEN_GRPH_FORMAT_ARGB8888 0 +#define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 +#define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 +#define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 +#define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 +#define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 +#define EVERGREEN_GRPH_FORMAT_RGB111110 6 +#define EVERGREEN_GRPH_FORMAT_BGR101111 7 +#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c +#define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) +#define EVERGREEN_GRPH_ENDIAN_NONE 0 +#define EVERGREEN_GRPH_ENDIAN_8IN16 1 +#define EVERGREEN_GRPH_ENDIAN_8IN32 2 +#define EVERGREEN_GRPH_ENDIAN_8IN64 3 +#define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) +#define EVERGREEN_GRPH_RED_SEL_R 0 +#define EVERGREEN_GRPH_RED_SEL_G 1 +#define EVERGREEN_GRPH_RED_SEL_B 2 +#define EVERGREEN_GRPH_RED_SEL_A 3 +#define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) +#define EVERGREEN_GRPH_GREEN_SEL_G 0 +#define EVERGREEN_GRPH_GREEN_SEL_B 1 +#define EVERGREEN_GRPH_GREEN_SEL_A 2 +#define EVERGREEN_GRPH_GREEN_SEL_R 3 +#define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) +#define EVERGREEN_GRPH_BLUE_SEL_B 0 +#define EVERGREEN_GRPH_BLUE_SEL_A 1 +#define EVERGREEN_GRPH_BLUE_SEL_R 2 +#define EVERGREEN_GRPH_BLUE_SEL_G 3 +#define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) +#define EVERGREEN_GRPH_ALPHA_SEL_A 0 +#define EVERGREEN_GRPH_ALPHA_SEL_R 1 +#define EVERGREEN_GRPH_ALPHA_SEL_G 2 +#define EVERGREEN_GRPH_ALPHA_SEL_B 3 +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 +#define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) +#define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 +#define EVERGREEN_GRPH_PITCH 0x6818 +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 +#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 +#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 +#define EVERGREEN_GRPH_X_START 0x682c +#define EVERGREEN_GRPH_Y_START 0x6830 +#define EVERGREEN_GRPH_X_END 0x6834 +#define EVERGREEN_GRPH_Y_END 0x6838 + +/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ +#define EVERGREEN_CUR_CONTROL 0x6998 +#define EVERGREEN_CURSOR_EN (1 << 0) +#define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) +#define EVERGREEN_CURSOR_MONO 0 +#define EVERGREEN_CURSOR_24_1 1 +#define EVERGREEN_CURSOR_24_8_PRE_MULT 2 +#define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 +#define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) +#define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) +#define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) +#define EVERGREEN_CURSOR_URGENT_ALWAYS 0 +#define EVERGREEN_CURSOR_URGENT_1_8 1 +#define EVERGREEN_CURSOR_URGENT_1_4 2 +#define EVERGREEN_CURSOR_URGENT_3_8 3 +#define EVERGREEN_CURSOR_URGENT_1_2 4 +#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c +#define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 +#define EVERGREEN_CUR_SIZE 0x69a0 +#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 +#define EVERGREEN_CUR_POSITION 0x69a8 +#define EVERGREEN_CUR_HOT_SPOT 0x69ac +#define EVERGREEN_CUR_COLOR1 0x69b0 +#define EVERGREEN_CUR_COLOR2 0x69b4 +#define EVERGREEN_CUR_UPDATE 0x69b8 +#define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) +#define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) +#define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) +#define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDAT (1 << 24) + +/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ +#define EVERGREEN_DC_LUT_RW_MODE 0x69e0 +#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 +#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 +#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec +#define EVERGREEN_DC_LUT_30_COLOR 0x69f0 +#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 +#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 +#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc +#define EVERGREEN_DC_LUT_CONTROL 0x6a00 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c +#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 +#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 +#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 + +#define EVERGREEN_DATA_FORMAT 0x6b00 +#define EVERGREEN_INTERLEAVE_EN (1 << 0) +#define EVERGREEN_DESKTOP_HEIGHT 0x6b04 + +#define EVERGREEN_VIEWPORT_START 0x6d70 +#define EVERGREEN_VIEWPORT_SIZE 0x6d74 + +/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ +#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) +#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) +#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) +#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) +#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) +#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) + +/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ +#define EVERGREEN_CRTC_CONTROL 0x6e70 +#define EVERGREEN_CRTC_MASTER_EN (1 << 0) +#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 + +#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 +#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 +#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 +#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc + +#define R300_GB_TILE_CONFIG 0x4018 +#define R300_ENABLE_TILING (1 << 0) +#define R300_PIPE_COUNT_RV350 (0 << 1) +#define R300_PIPE_COUNT_R300 (3 << 1) +#define R300_PIPE_COUNT_R420_3P (6 << 1) +#define R300_PIPE_COUNT_R420 (7 << 1) +#define R300_TILE_SIZE_8 (0 << 4) +#define R300_TILE_SIZE_16 (1 << 4) +#define R300_TILE_SIZE_32 (2 << 4) +#define R300_SUBPIXEL_1_12 (0 << 16) +#define R300_SUBPIXEL_1_16 (1 << 16) +#define R300_GB_SELECT 0x401c +#define R300_GB_ENABLE 0x4008 +#define R300_GB_AA_CONFIG 0x4020 +#define R400_GB_PIPE_SELECT 0x402c +#define R300_GB_MSPOS0 0x4010 +#define R300_MS_X0_SHIFT 0 +#define R300_MS_Y0_SHIFT 4 +#define R300_MS_X1_SHIFT 8 +#define R300_MS_Y1_SHIFT 12 +#define R300_MS_X2_SHIFT 16 +#define R300_MS_Y2_SHIFT 20 +#define R300_MSBD0_Y_SHIFT 24 +#define R300_MSBD0_X_SHIFT 28 +#define R300_GB_MSPOS1 0x4014 +#define R300_MS_X3_SHIFT 0 +#define R300_MS_Y3_SHIFT 4 +#define R300_MS_X4_SHIFT 8 +#define R300_MS_Y4_SHIFT 12 +#define R300_MS_X5_SHIFT 16 +#define R300_MS_Y5_SHIFT 20 +#define R300_MSBD1_SHIFT 24 + +#define R300_GA_ENHANCE 0x4274 +#define R300_GA_DEADLOCK_CNTL (1 << 0) +#define R300_GA_FASTSYNC_CNTL (1 << 1) + +#define R300_GA_POLY_MODE 0x4288 +#define R300_FRONT_PTYPE_POINT (0 << 4) +#define R300_FRONT_PTYPE_LINE (1 << 4) +#define R300_FRONT_PTYPE_TRIANGE (2 << 4) +#define R300_BACK_PTYPE_POINT (0 << 7) +#define R300_BACK_PTYPE_LINE (1 << 7) +#define R300_BACK_PTYPE_TRIANGE (2 << 7) +#define R300_GA_ROUND_MODE 0x428c +#define R300_GEOMETRY_ROUND_TRUNC (0 << 0) +#define R300_GEOMETRY_ROUND_NEAREST (1 << 0) +#define R300_COLOR_ROUND_TRUNC (0 << 2) +#define R300_COLOR_ROUND_NEAREST (1 << 2) +#define R300_GA_COLOR_CONTROL 0x4278 +#define R300_RGB0_SHADING_SOLID (0 << 0) +#define R300_RGB0_SHADING_FLAT (1 << 0) +#define R300_RGB0_SHADING_GOURAUD (2 << 0) +#define R300_ALPHA0_SHADING_SOLID (0 << 2) +#define R300_ALPHA0_SHADING_FLAT (1 << 2) +#define R300_ALPHA0_SHADING_GOURAUD (2 << 2) +#define R300_RGB1_SHADING_SOLID (0 << 4) +#define R300_RGB1_SHADING_FLAT (1 << 4) +#define R300_RGB1_SHADING_GOURAUD (2 << 4) +#define R300_ALPHA1_SHADING_SOLID (0 << 6) +#define R300_ALPHA1_SHADING_FLAT (1 << 6) +#define R300_ALPHA1_SHADING_GOURAUD (2 << 6) +#define R300_RGB2_SHADING_SOLID (0 << 8) +#define R300_RGB2_SHADING_FLAT (1 << 8) +#define R300_RGB2_SHADING_GOURAUD (2 << 8) +#define R300_ALPHA2_SHADING_SOLID (0 << 10) +#define R300_ALPHA2_SHADING_FLAT (1 << 10) +#define R300_ALPHA2_SHADING_GOURAUD (2 << 10) +#define R300_RGB3_SHADING_SOLID (0 << 12) +#define R300_RGB3_SHADING_FLAT (1 << 12) +#define R300_RGB3_SHADING_GOURAUD (2 << 12) +#define R300_ALPHA3_SHADING_SOLID (0 << 14) +#define R300_ALPHA3_SHADING_FLAT (1 << 14) +#define R300_ALPHA3_SHADING_GOURAUD (2 << 14) +#define R300_GA_OFFSET 0x4290 + +#define R500_SU_REG_DEST 0x42c8 + +#define R300_VAP_CNTL_STATUS 0x2140 +#define R300_PVS_BYPASS (1 << 8) +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 +#define R300_VAP_CNTL 0x2080 +#define R300_PVS_NUM_SLOTS_SHIFT 0 +#define R300_PVS_NUM_CNTLRS_SHIFT 4 +#define R300_PVS_NUM_FPUS_SHIFT 8 +#define R300_VF_MAX_VTX_NUM_SHIFT 18 +#define R300_GL_CLIP_SPACE_DEF (0 << 22) +#define R300_DX_CLIP_SPACE_DEF (1 << 22) +#define R500_TCL_STATE_OPTIMIZATION (1 << 23) +#define R300_VAP_VTE_CNTL 0x20B0 +#define R300_VPORT_X_SCALE_ENA (1 << 0) +#define R300_VPORT_X_OFFSET_ENA (1 << 1) +#define R300_VPORT_Y_SCALE_ENA (1 << 2) +#define R300_VPORT_Y_OFFSET_ENA (1 << 3) +#define R300_VPORT_Z_SCALE_ENA (1 << 4) +#define R300_VPORT_Z_OFFSET_ENA (1 << 5) +#define R300_VTX_XY_FMT (1 << 8) +#define R300_VTX_Z_FMT (1 << 9) +#define R300_VTX_W0_FMT (1 << 10) +#define R300_VAP_VTX_STATE_CNTL 0x2180 +#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC +#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 +#define R300_DATA_TYPE_0_SHIFT 0 +#define R300_DATA_TYPE_FLOAT_1 0 +#define R300_DATA_TYPE_FLOAT_2 1 +#define R300_DATA_TYPE_FLOAT_3 2 +#define R300_DATA_TYPE_FLOAT_4 3 +#define R300_DATA_TYPE_BYTE 4 +#define R300_DATA_TYPE_D3DCOLOR 5 +#define R300_DATA_TYPE_SHORT_2 6 +#define R300_DATA_TYPE_SHORT_4 7 +#define R300_DATA_TYPE_VECTOR_3_TTT 8 +#define R300_DATA_TYPE_VECTOR_3_EET 9 +#define R300_SKIP_DWORDS_0_SHIFT 4 +#define R300_DST_VEC_LOC_0_SHIFT 8 +#define R300_LAST_VEC_0 (1 << 13) +#define R300_SIGNED_0 (1 << 14) +#define R300_NORMALIZE_0 (1 << 15) +#define R300_DATA_TYPE_1_SHIFT 16 +#define R300_SKIP_DWORDS_1_SHIFT 20 +#define R300_DST_VEC_LOC_1_SHIFT 24 +#define R300_LAST_VEC_1 (1 << 29) +#define R300_SIGNED_1 (1 << 30) +#define R300_NORMALIZE_1 (1 << 31) +#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 +#define R300_DATA_TYPE_2_SHIFT 0 +#define R300_SKIP_DWORDS_2_SHIFT 4 +#define R300_DST_VEC_LOC_2_SHIFT 8 +#define R300_LAST_VEC_2 (1 << 13) +#define R300_SIGNED_2 (1 << 14) +#define R300_NORMALIZE_2 (1 << 15) +#define R300_DATA_TYPE_3_SHIFT 16 +#define R300_SKIP_DWORDS_3_SHIFT 20 +#define R300_DST_VEC_LOC_3_SHIFT 24 +#define R300_LAST_VEC_3 (1 << 29) +#define R300_SIGNED_3 (1 << 30) +#define R300_NORMALIZE_3 (1 << 31) +#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 +#define R300_SWIZZLE_SELECT_X_0_SHIFT 0 +#define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 +#define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 +#define R300_SWIZZLE_SELECT_W_0_SHIFT 9 +#define R300_SWIZZLE_SELECT_X 0 +#define R300_SWIZZLE_SELECT_Y 1 +#define R300_SWIZZLE_SELECT_Z 2 +#define R300_SWIZZLE_SELECT_W 3 +#define R300_SWIZZLE_SELECT_FP_ZERO 4 +#define R300_SWIZZLE_SELECT_FP_ONE 5 +#define R300_WRITE_ENA_0_SHIFT 12 +#define R300_WRITE_ENA_X 1 +#define R300_WRITE_ENA_Y 2 +#define R300_WRITE_ENA_Z 4 +#define R300_WRITE_ENA_W 8 +#define R300_SWIZZLE_SELECT_X_1_SHIFT 16 +#define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 +#define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 +#define R300_SWIZZLE_SELECT_W_1_SHIFT 25 +#define R300_WRITE_ENA_1_SHIFT 28 +#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 +#define R300_SWIZZLE_SELECT_X_2_SHIFT 0 +#define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 +#define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 +#define R300_SWIZZLE_SELECT_W_2_SHIFT 9 +#define R300_WRITE_ENA_2_SHIFT 12 +#define R300_SWIZZLE_SELECT_X_3_SHIFT 16 +#define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 +#define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 +#define R300_SWIZZLE_SELECT_W_3_SHIFT 25 +#define R300_WRITE_ENA_3_SHIFT 28 +#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 +#define R300_PVS_FIRST_INST_SHIFT 0 +#define R300_PVS_XYZW_VALID_INST_SHIFT 10 +#define R300_PVS_LAST_INST_SHIFT 20 +#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 +#define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 +#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 +#define R300_PVS_CODE_START 0 +#define R300_PVS_CONST_START 512 +#define R500_PVS_CONST_START 1024 +#define R300_PVS_VECTOR_INST_INDEX(x) ((x) + R300_PVS_CODE_START) +#define R300_PVS_VECTOR_CONST_INDEX(x) ((x) + R300_PVS_CONST_START) +#define R500_PVS_VECTOR_CONST_INDEX(x) ((x) + R500_PVS_CONST_START) +#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 +/* PVS instructions */ +/* Opcode and dst instruction */ +#define R300_PVS_DST_OPCODE(x) ((x) << 0) +/* Vector ops */ +#define R300_VECTOR_NO_OP 0 +#define R300_VE_DOT_PRODUCT 1 +#define R300_VE_MULTIPLY 2 +#define R300_VE_ADD 3 +#define R300_VE_MULTIPLY_ADD 4 +#define R300_VE_DISTANCE_VECTOR 5 +#define R300_VE_FRACTION 6 +#define R300_VE_MAXIMUM 7 +#define R300_VE_MINIMUM 8 +#define R300_VE_SET_GREATER_THAN_EQUAL 9 +#define R300_VE_SET_LESS_THAN 10 +#define R300_VE_MULTIPLYX2_ADD 11 +#define R300_VE_MULTIPLY_CLAMP 12 +#define R300_VE_FLT2FIX_DX 13 +#define R300_VE_FLT2FIX_DX_RND 14 +/* R500 additions */ +#define R500_VE_PRED_SET_EQ_PUSH 15 +#define R500_VE_PRED_SET_GT_PUSH 16 +#define R500_VE_PRED_SET_GTE_PUSH 17 +#define R500_VE_PRED_SET_NEQ_PUSH 18 +#define R500_VE_COND_WRITE_EQ 19 +#define R500_VE_COND_WRITE_GT 20 +#define R500_VE_COND_WRITE_GTE 21 +#define R500_VE_COND_WRITE_NEQ 22 +#define R500_VE_COND_MUX_EQ 23 +#define R500_VE_COND_MUX_GT 24 +#define R500_VE_COND_MUX_GTE 25 +#define R500_VE_SET_GREATER_THAN 26 +#define R500_VE_SET_EQUAL 27 +#define R500_VE_SET_NOT_EQUAL 28 +/* Math ops */ +#define R300_MATH_NO_OP 0 +#define R300_ME_EXP_BASE2_DX 1 +#define R300_ME_LOG_BASE2_DX 2 +#define R300_ME_EXP_BASEE_FF 3 +#define R300_ME_LIGHT_COEFF_DX 4 +#define R300_ME_POWER_FUNC_FF 5 +#define R300_ME_RECIP_DX 6 +#define R300_ME_RECIP_FF 7 +#define R300_ME_RECIP_SQRT_DX 8 +#define R300_ME_RECIP_SQRT_FF 9 +#define R300_ME_MULTIPLY 10 +#define R300_ME_EXP_BASE2_FULL_DX 11 +#define R300_ME_LOG_BASE2_FULL_DX 12 +#define R300_ME_POWER_FUNC_FF_CLAMP_B 13 +#define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 +#define R300_ME_POWER_FUNC_FF_CLAMP_01 15 +#define R300_ME_SIN 16 +#define R300_ME_COS 17 +/* R500 additions */ +#define R500_ME_LOG_BASE2_IEEE 18 +#define R500_ME_RECIP_IEEE 19 +#define R500_ME_RECIP_SQRT_IEEE 20 +#define R500_ME_PRED_SET_EQ 21 +#define R500_ME_PRED_SET_GT 22 +#define R500_ME_PRED_SET_GTE 23 +#define R500_ME_PRED_SET_NEQ 24 +#define R500_ME_PRED_SET_CLR 25 +#define R500_ME_PRED_SET_INV 26 +#define R500_ME_PRED_SET_POP 27 +#define R500_ME_PRED_SET_RESTORE 28 +/* macro */ +#define R300_PVS_MACRO_OP_2CLK_MADD 0 +#define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 +#define R300_PVS_DST_MATH_INST (1 << 6) +#define R300_PVS_DST_MACRO_INST (1 << 7) +#define R300_PVS_DST_REG_TYPE(x) ((x) << 8) +#define R300_PVS_DST_REG_TEMPORARY 0 +#define R300_PVS_DST_REG_A0 1 +#define R300_PVS_DST_REG_OUT 2 +#define R500_PVS_DST_REG_OUT_REPL_X 3 +#define R300_PVS_DST_REG_ALT_TEMPORARY 4 +#define R300_PVS_DST_REG_INPUT 5 +#define R300_PVS_DST_ADDR_MODE_1 (1 << 12) +#define R300_PVS_DST_OFFSET(x) ((x) << 13) +#define R300_PVS_DST_WE_X (1 << 20) +#define R300_PVS_DST_WE_Y (1 << 21) +#define R300_PVS_DST_WE_Z (1 << 22) +#define R300_PVS_DST_WE_W (1 << 23) +#define R300_PVS_DST_VE_SAT (1 << 24) +#define R300_PVS_DST_ME_SAT (1 << 25) +#define R300_PVS_DST_PRED_ENABLE (1 << 26) +#define R300_PVS_DST_PRED_SENSE (1 << 27) +#define R300_PVS_DST_DUAL_MATH_OP (1 << 28) +#define R300_PVS_DST_ADDR_SEL(x) ((x) << 29) +#define R300_PVS_DST_ADDR_MODE_0 (1 << 31) +/* src operand instruction */ +#define R300_PVS_SRC_REG_TYPE(x) ((x) << 0) +#define R300_PVS_SRC_REG_TEMPORARY 0 +#define R300_PVS_SRC_REG_INPUT 1 +#define R300_PVS_SRC_REG_CONSTANT 2 +#define R300_PVS_SRC_REG_ALT_TEMPORARY 3 +#define R300_SPARE_0 (1 << 2) +#define R300_PVS_SRC_ABS_XYZW (1 << 3) +#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) +#define R300_PVS_SRC_OFFSET(x) ((x) << 5) +#define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13) +#define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16) +#define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19) +#define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22) +#define R300_PVS_SRC_SELECT_X 0 +#define R300_PVS_SRC_SELECT_Y 1 +#define R300_PVS_SRC_SELECT_Z 2 +#define R300_PVS_SRC_SELECT_W 3 +#define R300_PVS_SRC_SELECT_FORCE_0 4 +#define R300_PVS_SRC_SELECT_FORCE_1 5 +#define R300_PVS_SRC_NEG_X (1 << 25) +#define R300_PVS_SRC_NEG_Y (1 << 26) +#define R300_PVS_SRC_NEG_Z (1 << 27) +#define R300_PVS_SRC_NEG_W (1 << 28) +#define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29) +#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) + +#define R300_VAP_PVS_CONST_CNTL 0x22d4 +#define R300_PVS_CONST_BASE_OFFSET(x) ((x) << 0) +#define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16) + +#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc +#define R300_VAP_OUT_VTX_FMT_0 0x2090 +#define R300_VTX_POS_PRESENT (1 << 0) +#define R300_VTX_COLOR_0_PRESENT (1 << 1) +#define R300_VTX_COLOR_1_PRESENT (1 << 2) +#define R300_VTX_COLOR_2_PRESENT (1 << 3) +#define R300_VTX_COLOR_3_PRESENT (1 << 4) +#define R300_VTX_PT_SIZE_PRESENT (1 << 16) +#define R300_VAP_OUT_VTX_FMT_1 0x2094 +#define R300_TEX_0_COMP_CNT_SHIFT 0 +#define R300_TEX_1_COMP_CNT_SHIFT 3 +#define R300_TEX_2_COMP_CNT_SHIFT 6 +#define R300_TEX_3_COMP_CNT_SHIFT 9 +#define R300_TEX_4_COMP_CNT_SHIFT 12 +#define R300_TEX_5_COMP_CNT_SHIFT 15 +#define R300_TEX_6_COMP_CNT_SHIFT 18 +#define R300_TEX_7_COMP_CNT_SHIFT 21 +#define R300_VAP_VTX_SIZE 0x20b4 +#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 +#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 +#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 +#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c +#define R300_VAP_CLIP_CNTL 0x221c +#define R300_UCP_ENA_0 (1 << 0) +#define R300_UCP_ENA_1 (1 << 1) +#define R300_UCP_ENA_2 (1 << 2) +#define R300_UCP_ENA_3 (1 << 3) +#define R300_UCP_ENA_4 (1 << 4) +#define R300_UCP_ENA_5 (1 << 5) +#define R300_PS_UCP_MODE_SHIFT 14 +#define R300_CLIP_DISABLE (1 << 16) +#define R300_UCP_CULL_ONLY_ENA (1 << 17) +#define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 + +#define R500_VAP_INDEX_OFFSET 0x208c + +#define R300_SU_TEX_WRAP 0x42a0 +#define R300_SU_POLY_OFFSET_ENABLE 0x42b4 +#define R300_SU_CULL_MODE 0x42b8 +#define R300_CULL_FRONT (1 << 0) +#define R300_CULL_BACK (1 << 1) +#define R300_FACE_POS (0 << 2) +#define R300_FACE_NEG (1 << 2) +#define R300_SU_DEPTH_SCALE 0x42c0 +#define R300_SU_DEPTH_OFFSET 0x42c4 + +#define R300_RS_COUNT 0x4300 +#define R300_RS_COUNT_IT_COUNT_SHIFT 0 +#define R300_RS_COUNT_IC_COUNT_SHIFT 7 +#define R300_RS_COUNT_HIRES_EN (1 << 18) + +#define R300_RS_IP_0 0x4310 +#define R300_RS_IP_1 0x4314 +#define R300_RS_TEX_PTR(x) ((x) << 0) +#define R300_RS_COL_PTR(x) ((x) << 6) +#define R300_RS_COL_FMT(x) ((x) << 9) +#define R300_RS_COL_FMT_RGBA 0 +#define R300_RS_COL_FMT_RGB0 2 +#define R300_RS_COL_FMT_RGB1 3 +#define R300_RS_COL_FMT_000A 4 +#define R300_RS_COL_FMT_0000 5 +#define R300_RS_COL_FMT_0001 6 +#define R300_RS_COL_FMT_111A 8 +#define R300_RS_COL_FMT_1110 9 +#define R300_RS_COL_FMT_1111 10 +#define R300_RS_SEL_S(x) ((x) << 13) +#define R300_RS_SEL_T(x) ((x) << 16) +#define R300_RS_SEL_R(x) ((x) << 19) +#define R300_RS_SEL_Q(x) ((x) << 22) +#define R300_RS_SEL_C0 0 +#define R300_RS_SEL_C1 1 +#define R300_RS_SEL_C2 2 +#define R300_RS_SEL_C3 3 +#define R300_RS_SEL_K0 4 +#define R300_RS_SEL_K1 5 +#define R300_RS_INST_COUNT 0x4304 +#define R300_INST_COUNT_RS(x) ((x) << 0) +#define R300_RS_W_EN (1 << 4) +#define R300_TX_OFFSET_RS(x) ((x) << 5) +#define R300_RS_INST_0 0x4330 +#define R300_RS_INST_1 0x4334 +#define R300_INST_TEX_ID(x) ((x) << 0) +#define R300_RS_INST_TEX_CN_WRITE (1 << 3) +#define R300_INST_TEX_ADDR(x) ((x) << 6) + +#define R300_TX_INVALTAGS 0x4100 +#define R300_TX_FILTER0_0 0x4400 +#define R300_TX_FILTER0_1 0x4404 +#define R300_TX_FILTER0_2 0x4408 +#define R300_TX_CLAMP_S(x) ((x) << 0) +#define R300_TX_CLAMP_T(x) ((x) << 3) +#define R300_TX_CLAMP_R(x) ((x) << 6) +#define R300_TX_CLAMP_WRAP 0 +#define R300_TX_CLAMP_MIRROR 1 +#define R300_TX_CLAMP_CLAMP_LAST 2 +#define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 +#define R300_TX_CLAMP_CLAMP_BORDER 4 +#define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 +#define R300_TX_CLAMP_CLAMP_GL 6 +#define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 +#define R300_TX_MAG_FILTER_NEAREST (1 << 9) +#define R300_TX_MIN_FILTER_NEAREST (1 << 11) +#define R300_TX_MAG_FILTER_LINEAR (2 << 9) +#define R300_TX_MIN_FILTER_LINEAR (2 << 11) +#define R300_TX_ID_SHIFT 28 +#define R300_TX_FILTER1_0 0x4440 +#define R300_TX_FILTER1_1 0x4444 +#define R300_TX_FILTER1_2 0x4448 +#define R300_TX_FORMAT0_0 0x4480 +#define R300_TX_FORMAT0_1 0x4484 +#define R300_TX_FORMAT0_2 0x4488 +#define R300_TXWIDTH_SHIFT 0 +#define R300_TXHEIGHT_SHIFT 11 +#define R300_NUM_LEVELS_SHIFT 26 +#define R300_NUM_LEVELS_MASK 0x +#define R300_TXPROJECTED (1 << 30) +#define R300_TXPITCH_EN (1 << 31) +#define R300_TX_FORMAT1_0 0x44c0 +#define R300_TX_FORMAT1_1 0x44c4 +#define R300_TX_FORMAT1_2 0x44c8 +#define R300_TX_FORMAT_X8 0x0 +#define R300_TX_FORMAT_X16 0x1 +#define R300_TX_FORMAT_Y4X4 0x2 +#define R300_TX_FORMAT_Y8X8 0x3 +#define R300_TX_FORMAT_Y16X16 0x4 +#define R300_TX_FORMAT_Z3Y3X2 0x5 +#define R300_TX_FORMAT_Z5Y6X5 0x6 +#define R300_TX_FORMAT_Z6Y5X5 0x7 +#define R300_TX_FORMAT_Z11Y11X10 0x8 +#define R300_TX_FORMAT_Z10Y11X11 0x9 +#define R300_TX_FORMAT_W4Z4Y4X4 0xA +#define R300_TX_FORMAT_W1Z5Y5X5 0xB +#define R300_TX_FORMAT_W8Z8Y8X8 0xC +#define R300_TX_FORMAT_W2Z10Y10X10 0xD +#define R300_TX_FORMAT_W16Z16Y16X16 0xE +#define R300_TX_FORMAT_DXT1 0xF +#define R300_TX_FORMAT_DXT3 0x10 +#define R300_TX_FORMAT_DXT5 0x11 +#define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ +#define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ +#define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ +#define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ +#define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ +#define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ +#define R300_TX_FORMAT_X24_Y8 0x1e +#define R300_TX_FORMAT_X32 0x1e +/* Floating point formats */ +/* Note - hardware supports both 16 and 32 bit floating point */ +#define R300_TX_FORMAT_FL_I16 0x18 +#define R300_TX_FORMAT_FL_I16A16 0x19 +#define R300_TX_FORMAT_FL_R16G16B16A16 0x1A +#define R300_TX_FORMAT_FL_I32 0x1B +#define R300_TX_FORMAT_FL_I32A32 0x1C +#define R300_TX_FORMAT_FL_R32G32B32A32 0x1D +/* alpha modes, convenience mostly */ +/* if you have alpha, pick constant appropriate to the + number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ +#define R300_TX_FORMAT_ALPHA_1CH 0x000 +#define R300_TX_FORMAT_ALPHA_2CH 0x200 +#define R300_TX_FORMAT_ALPHA_4CH 0x600 +#define R300_TX_FORMAT_ALPHA_NONE 0xA00 +/* Swizzling */ +/* constants */ +#define R300_TX_FORMAT_X 0 +#define R300_TX_FORMAT_Y 1 +#define R300_TX_FORMAT_Z 2 +#define R300_TX_FORMAT_W 3 +#define R300_TX_FORMAT_ZERO 4 +#define R300_TX_FORMAT_ONE 5 +/* 2.0*Z, everything above 1.0 is set to 0.0 */ +#define R300_TX_FORMAT_CUT_Z 6 +/* 2.0*W, everything above 1.0 is set to 0.0 */ +#define R300_TX_FORMAT_CUT_W 7 + +#define R300_TX_FORMAT_B_SHIFT 18 +#define R300_TX_FORMAT_G_SHIFT 15 +#define R300_TX_FORMAT_R_SHIFT 12 +#define R300_TX_FORMAT_A_SHIFT 9 + +/* Convenience macro to take care of layout and swizzling */ +#define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ + ((R300_TX_FORMAT_##B)< r784) ported to a module. + This code has no support for "legacy" ATI cards. + If your HD card was supported on the old code and you find + it missing on this, please file an issue at: + http://forge.voodooprojects.org/p/chameleon/issues/ + The same applies to any missing card on this code. + Only cards known to work will be added. + +Dependencies: none + +Keys: GraphicsEnabler Yes/No (enabled by default) + Disable GraphicsEnabler patch. + + ATYbinimage Yes/No (enabled by default) + Disable adding VBIOS read from "legacy space or PCI ROM" + to "ATY,bin_image" ioreg property. ???confirm + + UseAtiROM Yes/No (disabled by default) + Enable the use of a custom VBIOS ROM image added + to "ATY,bin_image" ioreg property. ??? Azi: confirm + + AtiConfig Used to test a framebuffer different from the default one. + + +Adaptation of Meklort's work. + +TODO: +- fix malloc error (ati.c #1235) when compiling with XCode 4 +- merge ATiGraphicsEnabler into this module ?? +- finish styling ati_reg.h +- review "radeon_card_info_t radeon_cards" \ No newline at end of file Index: branches/ErmaC/i386/modules/AMDGraphicsEnabler/AMDGraphicsEnabler.c =================================================================== --- branches/ErmaC/i386/modules/AMDGraphicsEnabler/AMDGraphicsEnabler.c (revision 0) +++ branches/ErmaC/i386/modules/AMDGraphicsEnabler/AMDGraphicsEnabler.c (revision 1568) @@ -0,0 +1,44 @@ +/* + * AMDGraphicsEnabler Module + * Enables many AMD/ATI HD cards to be used out of the box in OS X. + * This was converted from boot2 code ( > r784) to a boot2 module. + * + */ + +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "modules.h" + +#define kGraphicsEnablerKey "GraphicsEnabler" + +extern bool setup_ati_devprop(pci_dt_t *ati_dev); +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4); + + +void AMDGraphicsEnabler_start() +{ + register_hook_callback("PCIDevice", &GraphicsEnabler_hook); +} + +void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4) +{ + pci_dt_t* current = arg1; + + if (current->class_id != PCI_CLASS_DISPLAY_VGA) return; + + char *devicepath = get_pci_dev_path(current); + + bool do_gfx_devprop = true; + getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->chameleonConfig); + + if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI)) + { + verbose("AMD/ATI VGA Controller [%04x:%04x] :: %s \n", + current->vendor_id, current->device_id, devicepath); + setup_ati_devprop(current); + } + else + verbose("[%04x:%04x] :: %s, is not a AMD/ATI VGA Controller.\n", + current->vendor_id, current->device_id, devicepath); +} Index: branches/ErmaC/i386/modules/AMDGraphicsEnabler/Makefile =================================================================== --- branches/ErmaC/i386/modules/AMDGraphicsEnabler/Makefile (revision 0) +++ branches/ErmaC/i386/modules/AMDGraphicsEnabler/Makefile (revision 1568) @@ -0,0 +1,13 @@ +MODULE_NAME = AMDGraphicsEnabler +MODULE_AUTHOR = Chameleon +MODULE_DESCRIPTION = to be added... +MODULE_VERSION = "1.0.0" +MODULE_COMPAT_VERSION = "1.0.0" +MODULE_START = $(MODULE_NAME)_start +MODULE_DEPENDENCIES = + +DIR = AMDGraphicsEnabler + +MODULE_OBJS = ati.o AMDGraphicsEnabler.o + +include ../MakeInc.dir Index: branches/ErmaC/i386/modules/AMDGraphicsEnabler/ati.c =================================================================== --- branches/ErmaC/i386/modules/AMDGraphicsEnabler/ati.c (revision 0) +++ branches/ErmaC/i386/modules/AMDGraphicsEnabler/ati.c (revision 1568) @@ -0,0 +1,1467 @@ +/* + * ATI Graphics Card Enabler, part of the Chameleon Boot Loader Project + * + * Copyright 2010 by Islam M. Ahmed Zaid. All rights reserved. + * + */ + +#include "libsa.h" +#include "saio_internal.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "device_inject.h" +#include "ati_reg.h" + +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x6e + +#define kUseAtiROM "UseAtiROM" +#define kAtiConfig "AtiConfig" +#define kAtiPorts "AtiPorts" +#define kATYbinimage "ATYbinimage" + +#define Reg32(reg) (*(volatile uint32_t *)(card->mmio + reg)) +#define RegRead32(reg) (Reg32(reg)) +#define RegWrite32(reg, value) (Reg32(reg) = value) + +typedef enum { + kNul, + kStr, + kPtr, + kCst +} type_t; + +typedef enum { + CHIP_FAMILY_UNKNOW, + /* IGP */ + CHIP_FAMILY_RS600, + CHIP_FAMILY_RS690, + CHIP_FAMILY_RS740, + CHIP_FAMILY_RS780, + CHIP_FAMILY_RS880, + /* R600 */ + CHIP_FAMILY_R600, + CHIP_FAMILY_RV610, + CHIP_FAMILY_RV620, + CHIP_FAMILY_RV630, + CHIP_FAMILY_RV635, + CHIP_FAMILY_RV670, + /* R700 */ + CHIP_FAMILY_RV710, + CHIP_FAMILY_RV730, + CHIP_FAMILY_RV740, + CHIP_FAMILY_RV770, + /* Evergreen */ + CHIP_FAMILY_CEDAR, + CHIP_FAMILY_CYPRESS, + CHIP_FAMILY_HEMLOCK, + CHIP_FAMILY_JUNIPER, + CHIP_FAMILY_REDWOOD, + /* Northern Islands */ + CHIP_FAMILY_BARTS, + CHIP_FAMILY_CAICOS, + CHIP_FAMILY_CAYMAN, + CHIP_FAMILY_TURKS, + CHIP_FAMILY_LAST +} chip_family_t; + +static const char *chip_family_name[] = { + "UNKNOW", + /* IGP */ + "RS600", + "RS690", + "RS740", + "RS780", + "RS880", + /* R600 */ + "R600", + "RV610", + "RV620", + "RV630", + "RV635", + "RV670", + /* R700 */ + "RV710", + "RV730", + "RV740", + "RV770", + /* Evergreen */ + "Cedar", + "Cypress", + "Hemlock", + "Juniper", + "Redwood", + /* Northern Islands */ + "Barts", + "Caicos", + "Cayman", + "Turks", + "" +}; + +typedef struct { + const char *name; + uint8_t ports; +} card_config_t; + +static card_config_t card_configs[] = { + {NULL, 0}, + {"Alopias", 2}, + {"Alouatta", 4}, + {"Baboon", 3}, + {"Cardinal", 2}, + {"Caretta", 1}, + {"Colobus", 2}, + {"Douc", 2}, + {"Eulemur", 3}, + {"Flicker", 3}, + {"Galago", 2}, + {"Gliff", 3}, + {"Hoolock", 3}, + {"Hypoprion", 2}, + {"Iago", 2}, + {"Kakapo", 3}, + {"Kipunji", 4}, + {"Lamna", 2}, + {"Langur", 3}, + {"Megalodon", 3}, + {"Motmot", 2}, + {"Nomascus", 5}, + {"Orangutan", 2}, + {"Peregrine", 2}, + {"Quail", 3}, + {"Raven", 3}, + {"Shrike", 3}, + {"Sphyrna", 1}, + {"Triakis", 2}, + {"Uakari", 4}, + {"Vervet", 4}, + {"Zonalis", 6}, + {"Pithecia", 3}, + {"Bulrushes", 6}, + {"Cattail", 4}, + {"Hydrilla", 5}, + {"Duckweed", 4}, + {"Fanwort", 4}, + {"Elodea", 5}, + {"Kudzu", 2}, + {"Gibba", 5}, + {"Lotus", 3}, + {"Ipomoea", 3}, + {"Mangabey", 2}, + {"Muskgrass", 4}, + {"Juncus", 4} +}; + +typedef enum { + kNull, + kAlopias, + kAlouatta, + kBaboon, + kCardinal, + kCaretta, + kColobus, + kDouc, + kEulemur, + kFlicker, + kGalago, + kGliff, + kHoolock, + kHypoprion, + kIago, + kKakapo, + kKipunji, + kLamna, + kLangur, + kMegalodon, + kMotmot, + kNomascus, + kOrangutan, + kPeregrine, + kQuail, + kRaven, + kShrike, + kSphyrna, + kTriakis, + kUakari, + kVervet, + kZonalis, + kPithecia, + kBulrushes, + kCattail, + kHydrilla, + kDuckweed, + kFanwort, + kElodea, + kKudzu, + kGibba, + kLotus, + kIpomoea, + kMangabey, + kMuskgrass, + kJuncus, + kCfgEnd +} config_name_t; + +typedef struct { + uint16_t device_id; + uint32_t subsys_id; + chip_family_t chip_family; + const char *model_name; + config_name_t cfg_name; + uint8_t max_ports; +} radeon_card_info_t; + +static radeon_card_info_t radeon_cards[] = { + + // Earlier cards are not supported + // + // Layout is device_id, subsys_id (subsystem id plus vendor id), chip_family_name, display name, frame buffer + // Cards are grouped by device id and vendor id then sorted by subsystem id to make it easier to add new cards + // + { 0x9400, 0x25521002, CHIP_FAMILY_R600, "ATI Radeon HD 2900 XT", kNull , 0 }, + { 0x9400, 0x30001002, CHIP_FAMILY_R600, "ATI Radeon HD 2900 PRO", kNull , 0 }, + + { 0x9440, 0x24401682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot , 0 }, + { 0x9440, 0x24411682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot , 0 }, + { 0x9440, 0x24441682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot , 0 }, + { 0x9440, 0x24451682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot , 0 }, + + { 0x9441, 0x24401682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870 X2", kMotmot , 0 }, + + { 0x9442, 0x080110B0, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot , 0 }, + + { 0x9442, 0x24701682, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot , 0 }, + { 0x9442, 0x24711682, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot , 0 }, + + { 0x9442, 0xE104174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot , 0 }, + + { 0x944A, 0x30001043, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944A, 0x30001458, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944A, 0x30001462, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944A, 0x30001545, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944A, 0x30001682, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944A, 0x3000174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944A, 0x30001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944A, 0x300017AF, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x944C, 0x24801682, CHIP_FAMILY_RV770, "ATI Radeon HD 4830", kMotmot , 0 }, + { 0x944C, 0x24811682, CHIP_FAMILY_RV770, "ATI Radeon HD 4830", kMotmot , 0 }, + + { 0x944E, 0x3260174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 Series", kMotmot , 0 }, + { 0x944E, 0x3261174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 series", kMotmot , 0 }, + + { 0x944E, 0x30001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4730 Series", kMotmot , 0 }, + { 0x944E, 0x30101787, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 Series", kMotmot , 0 }, + { 0x944E, 0x31001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4820", kMotmot , 0 }, + + { 0x9480, 0x3628103C, CHIP_FAMILY_RV730, "ATI Radeon HD 4650M", kGliff , 2 }, + + { 0x9480, 0x9035104D, CHIP_FAMILY_RV730, "ATI Radeon HD 4650M", kGliff , 0 }, + + { 0x9490, 0x4710174B, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull , 0 }, + + { 0x9490, 0x20031787, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kFlicker , 0 }, + { 0x9490, 0x30501787, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull , 0 }, + + { 0x9490, 0x300017AF, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull , 0 }, + + { 0x9498, 0x21CF1458, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kNull , 0 }, + + { 0x9498, 0x24511682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull , 0 }, + { 0x9498, 0x24521682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull , 0 }, + { 0x9498, 0x24541682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull , 0 }, + { 0x9498, 0x29331682, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kNull , 0 }, + { 0x9498, 0x29341682, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kNull , 0 }, + + { 0x9498, 0x30501787, CHIP_FAMILY_RV730, "ATI Radeon HD 4700", kNull , 0 }, + { 0x9498, 0x31001787, CHIP_FAMILY_RV730, "ATI Radeon HD 4720", kNull , 0 }, + + { 0x94B3, 0x0D001002, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker , 0 }, + + { 0x94B3, 0x29001682, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker , 0 }, + + { 0x94B3, 0x1170174B, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker , 0 }, + + { 0x94C1, 0x0D021002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull , 0 }, + { 0x94C1, 0x10021002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Pro", kNull , 0 }, + + { 0x94C1, 0x0D021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull , 0 }, + + { 0x94C1, 0x21741458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull , 0 }, + + { 0x94C1, 0x10331462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull , 0 }, + { 0x94C1, 0x10401462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull , 0 }, + { 0x94C1, 0x11101462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull , 0 }, + + { 0x94C3, 0x03421002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + + { 0x94C3, 0x30001025, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull , 0 }, + + { 0x94C3, 0x03021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + { 0x94C3, 0x04021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + + { 0x94C3, 0x216A1458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + { 0x94C3, 0x21721458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + { 0x94C3, 0x30001458, CHIP_FAMILY_RV610, "ATI Radeon HD 3410", kNull , 0 }, + + { 0x94C3, 0x10321462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + { 0x94C3, 0x10411462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull , 0 }, + { 0x94C3, 0x11041462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull , 0 }, + { 0x94C3, 0x11051462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull , 0 }, + { 0x94C3, 0x30001462, CHIP_FAMILY_RV610, "ATI Radeon HD 3410", kNull , 0 }, + + { 0x94C3, 0x2247148C, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 LE", kNull , 0 }, + { 0x94C3, 0x3000148C, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull , 0 }, + + { 0x94C3, 0x3000174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull , 0 }, + { 0x94C3, 0xE370174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + { 0x94C3, 0xE400174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull , 0 }, + + { 0x94C3, 0x203817AF, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull , 0 }, + + { 0x94C3, 0x22471787, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 LE", kNull , 0 }, + { 0x94C3, 0x30001787, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull , 0 }, + + { 0x94C3, 0x01011A93, CHIP_FAMILY_RV610, "Qimonda Radeon HD 2400 PRO", kNull , 0 }, + + { 0x9501, 0x25421002, CHIP_FAMILY_RV670, "ATI Radeon HD 3870", kNull , 0 }, + { 0x9501, 0x30001002, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull , 0 }, + + { 0x9501, 0x3000174B, CHIP_FAMILY_RV670, "Sapphire Radeon HD 3690", kNull , 0 }, + { 0x9501, 0x4750174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull , 0 }, + + { 0x9501, 0x30001787, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull , 0 }, + + { 0x9505, 0x25421002, CHIP_FAMILY_RV670, "ATI Radeon HD 3850", kNull , 0 }, + { 0x9505, 0x30001002, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull , 0 }, + + { 0x9505, 0x30011043, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull , 0 }, + + { 0x9505, 0x3000148C, CHIP_FAMILY_RV670, "ATI Radeon HD 3850", kNull , 0 }, + { 0x9505, 0x3001148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull , 0 }, + { 0x9505, 0x3002148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull , 0 }, + { 0x9505, 0x3003148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull , 0 }, + { 0x9505, 0x3004148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull , 0 }, + + { 0x9505, 0x3000174B, CHIP_FAMILY_RV670, "Sapphire Radeon HD 3690", kNull , 0 }, + { 0x9505, 0x3001174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull , 0 }, + { 0x9505, 0x3010174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull , 0 }, + { 0x9505, 0x4730174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull , 0 }, + + { 0x9505, 0x30001787, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull , 0 }, + { 0x9505, 0x301017AF, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull , 0 }, + + { 0x9540, 0x4590174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4590", kNull , 0 }, + + { 0x9540, 0x30501787, CHIP_FAMILY_RV710, "ATI Radeon HD 4590", kNull , 0 }, + + { 0x954F, 0x29201682, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull , 0 }, + { 0x954F, 0x29211682, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull , 0 }, + { 0x954F, 0x30901682, CHIP_FAMILY_RV710, "XFX Radeon HD 4570", kNull , 0 }, + + { 0x954F, 0x30501787, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull , 0 }, + { 0x954F, 0x31001787, CHIP_FAMILY_RV710, "ATI Radeon HD 4520", kNull , 0 }, + + { 0x954F, 0x3000174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4520", kNull , 0 }, + { 0x954F, 0x4450174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull , 0 }, + { 0x954F, 0x4570174B, CHIP_FAMILY_RV710, "Sapphire Radeon HD 4570", kNull , 0 }, + { 0x954F, 0xE990174B, CHIP_FAMILY_RV710, "Sapphire Radeon HD 4350", kNull , 0 }, + + { 0x954F, 0x301017AF, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull , 0 }, + + { 0x9552, 0x04341028, CHIP_FAMILY_RV710, "ATI Mobility Radeon 4330", kShrike , 2 }, + + { 0x9552, 0x308B103C, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4300 Series", kShrike , 0 }, + + { 0x9552, 0x3000148C, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull , 0 }, + + { 0x9552, 0x3000174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull , 0 }, + + { 0x9552, 0x30001787, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull , 0 }, + + { 0x9552, 0x300017AF, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull , 0 }, + + { 0x9553, 0x18751043, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4570", kShrike , 0 }, + { 0x9553, 0x1B321043, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4570", kShrike , 0 }, + + { 0x9581, 0x95811002, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull , 0 }, + + { 0x9581, 0x3000148C, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull , 0 }, + + { 0x9583, 0x3000148C, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull , 0 }, + + { 0x9588, 0x01021A93, CHIP_FAMILY_RV630, "Qimonda Radeon HD 2600 XT", kNull , 0 }, + + { 0x9589, 0x30001462, CHIP_FAMILY_RV630, "ATI Radeon HD 3610", kNull , 0 }, + + { 0x9589, 0x0E41174B, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull , 0 }, + + { 0x9589, 0x30001787, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull , 0 }, + + { 0x9589, 0x01001A93, CHIP_FAMILY_RV630, "Qimonda Radeon HD 2600 PRO", kNull , 0 }, + + { 0x9591, 0x2303148C, CHIP_FAMILY_RV635, "ATI Radeon HD 3600 Series", kNull , 0 }, + + { 0x9598, 0xB3831002, CHIP_FAMILY_RV635, "ATI All-in-Wonder HD", kNull , 0 }, + + { 0x9598, 0x30001043, CHIP_FAMILY_RV635, "HD3730", kNull , 0 }, + { 0x9598, 0x30011043, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull , 0 }, + + { 0x9598, 0x3000148C, CHIP_FAMILY_RV635, "ATI Radeon HD 3730", kNull , 0 }, + { 0x9598, 0x3001148C, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull , 0 }, + { 0x9598, 0x3031148C, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull , 0 }, + + { 0x9598, 0x30001545, CHIP_FAMILY_RV635, "VisionTek Radeon HD 2600 XT", kNull , 0 }, + { 0x9598, 0x30011545, CHIP_FAMILY_RV635, "VisionTek Radeon HD 2600 Pro", kNull , 0 }, + + { 0x9598, 0x3000174B, CHIP_FAMILY_RV635, "Sapphire Radeon HD 3730", kNull , 0 }, + { 0x9598, 0x3001174B, CHIP_FAMILY_RV635, "Sapphire Radeon HD 3750", kNull , 0 }, + { 0x9598, 0x4570174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull , 0 }, + { 0x9598, 0x4580174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull , 0 }, + { 0x9598, 0x4610174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4610", kNull , 0 }, + + { 0x9598, 0x300117AF, CHIP_FAMILY_RV635, "ATI Radeon HD 3750", kNull , 0 }, + { 0x9598, 0x301017AF, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull , 0 }, + { 0x9598, 0x301117AF, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull , 0 }, + + { 0x9598, 0x30501787, CHIP_FAMILY_RV635, "ATI Radeon HD 4610", kNull , 0 }, + + { 0x95C0, 0x3000148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull , 0 }, + + { 0x95C0, 0xE3901745, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull , 0 }, + + { 0x95C0, 0x3000174B, CHIP_FAMILY_RV620, "Sapphire Radeon HD 3550", kNull , 0 }, + { 0x95C0, 0x3002174B, CHIP_FAMILY_RV620, "ATI Radeon HD 3570", kNull , 0 }, + { 0x95C0, 0x3020174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull , 0 }, + + { 0x95C5, 0x3000148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3450", kNull , 0 }, + { 0x95C5, 0x3001148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull , 0 }, + { 0x95C5, 0x3002148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull , 0 }, + { 0x95C5, 0x3003148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull , 0 }, + { 0x95C5, 0x3032148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull , 0 }, + { 0x95C5, 0x3033148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull , 0 }, + + { 0x95C5, 0x3010174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull , 0 }, + { 0x95C5, 0x4250174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull , 0 }, + + { 0x95C5, 0x30501787, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull , 0 }, + + { 0x95C5, 0x301017AF, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull , 0 }, + + { 0x95C5, 0x01041A93, CHIP_FAMILY_RV620, "Qimonda Radeon HD 3450", kNull , 0 }, + { 0x95C5, 0x01051A93, CHIP_FAMILY_RV620, "Qimonda Radeon HD 3450", kNull , 0 }, + + /* Evergreen */ + { 0x6898, 0x0B001002, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kZonalis , 0 }, + + { 0x6898, 0x032E1043, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari , 0 }, + + { 0x6898, 0x00D0106B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kLangur , 0 }, + + { 0x6898, 0xE140174B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari , 0 }, + + { 0x6898, 0x29611682, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari , 0 }, + + { 0x6899, 0x21E41458, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari , 0 }, + + { 0x6899, 0xE140174B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari , 0 }, + + { 0x6899, 0x200A1787, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari , 0 }, + { 0x6899, 0x22901787, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari , 0 }, + + { 0x689C, 0x03521043, CHIP_FAMILY_HEMLOCK, "ASUS ARES", kUakari , 0 }, + { 0x689C, 0x039E1043, CHIP_FAMILY_HEMLOCK, "ASUS EAH5870 Series", kUakari , 0 }, + + { 0x689C, 0x30201682, CHIP_FAMILY_HEMLOCK, "ATI Radeon HD 5970", kUakari , 0 }, + + { 0x68A1, 0x144D103C, CHIP_FAMILY_CYPRESS, "ATI Mobility Radeon HD 5850", kNomascus , 0 }, + { 0x68A1, 0x1522103C, CHIP_FAMILY_CYPRESS, "ATI Mobility Radeon HD 5850", kHoolock , 0 }, + + { 0x68A8, 0x050E1025, CHIP_FAMILY_CYPRESS, "AMD Radeon HD 6850M", kUakari , 0 }, + + { 0x68B8, 0x00CF106B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kHoolock , 0 }, + + { 0x68B8, 0x29901682, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet , 0 }, + { 0x68B8, 0x29911682, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet , 0 }, + + { 0x68B8, 0x1482174B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet , 0 }, + { 0x68B8, 0xE147174B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet , 0 }, + + { 0x68B8, 0x21D71458, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet , 0 }, + + { 0x68B8, 0x200B1787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet , 0 }, + { 0x68B8, 0x22881787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet , 0 }, + + { 0x68BF, 0x220E1458, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 6750", kVervet , 0 }, + + { 0x68C0, 0x1594103C, CHIP_FAMILY_REDWOOD, "AMD Radeon HD 6570M", kNull , 0 }, + + { 0x68C0, 0x392717AA, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5730", kNull , 0 }, + + { 0x68C1, 0x033E1025, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5650", kNull , 0 }, + { 0x68C1, 0x9071104D, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5650", kEulemur , 0 }, + + { 0x68C8, 0x2306103C, CHIP_FAMILY_REDWOOD, "ATI FirePro V4800 (FireGL)", kNull , 0 }, + + { 0x68D8, 0x03561043, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon , 0 }, + + { 0x68D8, 0x21D91458, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon , 0 }, + + { 0x68D8, 0x5690174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5690", kNull , 0 }, + { 0x68D8, 0x5730174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull , 0 }, + { 0x68D8, 0xE151174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon , 0 }, + + { 0x68D8, 0x30001787, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull , 0 }, + + { 0x68D8, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull , 0 }, + { 0x68D8, 0x301117AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5690", kNull , 0 }, + + { 0x68D9, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull , 0 }, + + { 0x68DA, 0x5630174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull , 0 }, + + { 0x68DA, 0x30001787, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull , 0 }, + + { 0x68DA, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull , 0 }, + + { 0x68E0, 0x04561028, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470M", kEulemur , 0 }, + + { 0x68E0, 0x1433103C, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470M", kEulemur , 0 }, + + { 0x68E1, 0x1426103C, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5430M", kEulemur , 0 }, + + { 0x68F9, 0x5470174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull , 0 }, + { 0x68F9, 0x5490174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull , 0 }, + { 0x68F9, 0x5530174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5530", kNull , 0 }, + + { 0x68F9, 0x20091787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur , 0 }, + { 0x68F9, 0x22911787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur , 0 }, + { 0x68F9, 0x30001787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull , 0 }, + { 0x68F9, 0x30011787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5530", kNull , 0 }, + { 0x68F9, 0x30021787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull , 0 }, + + { 0x68F9, 0x301117AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull , 0 }, + { 0x68F9, 0x301217AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull , 0 }, + { 0x68F9, 0x301317AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull , 0 }, + + /* Northen Islands */ + { 0x6718, 0x0B001002, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull , 0 }, + { 0x6718, 0x67181002, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull , 0 }, + + { 0x6718, 0x31301682, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull , 0 }, + + { 0x6738, 0x00D01002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + { 0x6738, 0x21FA1002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + { 0x6738, 0x67381002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + + { 0x6738, 0x21FA1458, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + + { 0x6738, 0x31031682, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + { 0x6738, 0x31041682, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + + { 0x6738, 0xE178174B, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + + { 0x6738, 0x20101787, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + { 0x6738, 0x23051787, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed , 0 }, + + { 0x6739, 0x67391002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed , 0 }, + + { 0x6739, 0x21F81458, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed , 0 }, + + { 0x6739, 0x24411462, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed , 0 }, + + { 0x6739, 0xE177174B, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed , 0 }, + + { 0x6740, 0x1657103C, CHIP_FAMILY_TURKS, "AMD Radeon HD 6770M", kNull , 0 }, + + { 0x6741, 0x050E1025, CHIP_FAMILY_TURKS, "AMD Radeon HD 6650M", kNull , 0 }, + { 0x6741, 0x05131025, CHIP_FAMILY_TURKS, "AMD Radeon HD 6650M", kNull , 0 }, + { 0x6741, 0x1646103C, CHIP_FAMILY_TURKS, "AMD Radeon HD 6750M", kNull , 0 }, + { 0x6741, 0x9080104D, CHIP_FAMILY_TURKS, "AMD Radeon HD 6630M", kNull , 0 }, + + { 0x6758, 0x67581002, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes , 0 }, + + { 0x6758, 0x22051458, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes , 0 }, + + { 0x6758, 0x31811682, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes , 0 }, + { 0x6758, 0x31831682, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes , 0 }, + + { 0x6758, 0xE1941746, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kBulrushes , 0 }, + + { 0x6759, 0xE193174B, CHIP_FAMILY_TURKS, "AMD Radeon HD 6570", kNull , 0 }, + + { 0x6760, 0x04CC1028, CHIP_FAMILY_RV730, "AMD Radeon HD 6490M", kNull , 0 }, + { 0x6760, 0x1CB21043, CHIP_FAMILY_RV730, "AMD Radeon HD 6470M", kNull , 0 }, + + { 0x6760, 0x1656103C, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6490M", kNull , 0 }, // ErmaC no tested + + { 0x6779, 0x64501092, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450", kBulrushes , 0 }, + + { 0x6779, 0xE164174B, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450", kBulrushes , 0 }, + + /* standard/default models */ + { 0x9400, 0x00000000, CHIP_FAMILY_R600, "ATI Radeon HD 2900 XT", kNull , 0 }, + { 0x9405, 0x00000000, CHIP_FAMILY_R600, "ATI Radeon HD 2900 GT", kNull , 0 }, + + { 0x9440, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + { 0x9441, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4870 X2", kMotmot , 0 }, + { 0x9442, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + { 0x9443, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4850 X2", kMotmot , 0 }, + { 0x944C, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + { 0x944E, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4700 Series", kMotmot , 0 }, + + { 0x9450, 0x00000000, CHIP_FAMILY_RV770, "AMD FireStream 9270", kMotmot , 0 }, + { 0x9452, 0x00000000, CHIP_FAMILY_RV770, "AMD FireStream 9250", kMotmot , 0 }, + + { 0x9460, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + { 0x9462, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot , 0 }, + + { 0x9490, 0x00000000, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kFlicker , 0 }, + { 0x9498, 0x00000000, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kFlicker , 0 }, + + { 0x94B3, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker , 0 }, + { 0x94B4, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4700 Series", kFlicker , 0 }, + { 0x94B5, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker , 0 }, + + { 0x94C1, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago , 0 }, + { 0x94C3, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago , 0 }, + { 0x94C7, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2350", kIago , 0 }, + { 0x94CC, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago , 0 }, + + { 0x9501, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3800 Series", kMegalodon , 0 }, + { 0x9505, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3800 Series", kMegalodon , 0 }, + { 0x9507, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3830", kMegalodon , 0 }, + { 0x950F, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3870 X2", kMegalodon , 0 }, + + { 0x9513, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3850 X2", kMegalodon , 0 }, + { 0x9519, 0x00000000, CHIP_FAMILY_RV670, "AMD FireStream 9170", kMegalodon , 0 }, + + { 0x9540, 0x00000000, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull , 0 }, + { 0x954F, 0x00000000, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull , 0 }, + + { 0x9553, 0x00000000, CHIP_FAMILY_RV710, "ATI Mobility Radeon HD 4500/5100 Series", kShrike , 0 }, + + { 0x9588, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 XT", kLamna , 0 }, + { 0x9589, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 PRO", kLamna , 0 }, + { 0x958A, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 X2 Series", kLamna , 0 }, + + { 0x9598, 0x00000000, CHIP_FAMILY_RV635, "ATI Radeon HD 3600 Series", kMegalodon , 0 }, + + { 0x95C0, 0x00000000, CHIP_FAMILY_RV620, "ATI Radeon HD 3400 Series", kIago , 0 }, + { 0x95C5, 0x00000000, CHIP_FAMILY_RV620, "ATI Radeon HD 3400 Series", kIago , 0 }, + + /* IGP */ + { 0x9610, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon HD 3200 Graphics", kNull , 0 }, + { 0x9611, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon 3100 Graphics", kNull , 0 }, + { 0x9614, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon HD 3300 Graphics", kNull , 0 }, + { 0x9616, 0x00000000, CHIP_FAMILY_RS780, "AMD 760G", kNull , 0 }, + + { 0x9710, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4200", kNull , 0 }, + { 0x9715, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4250", kNull , 0 }, + { 0x9714, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4290", kNull , 0 }, + + /* Evergreen */ + { 0x688D, 0x00000000, CHIP_FAMILY_CYPRESS, "AMD FireStream 9350", kUakari , 0 }, + + { 0x6898, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari , 0 }, + { 0x6899, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari , 0 }, + { 0x689C, 0x00000000, CHIP_FAMILY_HEMLOCK, "ATI Radeon HD 5900 Series", kUakari , 0 }, + { 0x689E, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari , 0 }, + + { 0x68B8, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5700 Series", kVervet , 0 }, + { 0x68B9, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5600 Series", kVervet , 0 }, + { 0x68BE, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5700 Series", kVervet , 0 }, + + { 0x68D8, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5600 Series", kBaboon , 0 }, + { 0x68D9, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5500 Series", kBaboon , 0 }, + { 0x68DA, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5500 Series", kBaboon , 0 }, + + { 0x68F9, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5400 Series", kNull , 0 }, + + /* Northen Islands */ + { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970 Series", kNull , 0 }, + { 0x6719, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950 Series", kNull , 0 }, + + { 0x6738, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870 Series", kDuckweed , 0 }, + { 0x6739, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850 Series", kDuckweed , 0 }, + { 0x673E, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6790 Series", kNull , 0 }, + + { 0x6740, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6700M Series", kNull , 0 }, + { 0x6741, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6600/6700M Series", kNull , 0 }, + + { 0x6758, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670 Series", kNull , 0 }, + { 0x6759, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6500 Series", kNull , 0 }, + + { 0x6760, 0x00000000, CHIP_FAMILY_RV730, "AMD Radeon HD 6470M", kNull , 0 }, + + { 0x6770, 0x00000000, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6400 Series", kNull , 0 }, + { 0x6779, 0x00000000, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450 Series", kNull , 0 } +}; + +typedef struct { + struct DevPropDevice *device; + radeon_card_info_t *info; + pci_dt_t *pci_dev; + uint8_t *fb; + uint8_t *mmio; + uint8_t *io; + uint8_t *rom; + uint32_t rom_size; + uint32_t vram_size; + const char *cfg_name; + uint8_t ports; + uint32_t flags; + bool posted; +} card_t; +card_t *card; + +/* Flags */ +#define MKFLAG(n) (1 << n) +#define FLAGTRUE MKFLAG(0) +#define EVERGREEN MKFLAG(1) + +//static uint8_t atN = 0; + +typedef struct { + type_t type; + uint32_t size; + uint8_t *data; +} value_t; + +static value_t aty_name; +static value_t aty_nameparent; +//static value_t aty_model; + +#define DATVAL(x) {kPtr, sizeof(x), (uint8_t *)x} +#define STRVAL(x) {kStr, sizeof(x), (uint8_t *)x} +#define BYTVAL(x) {kCst, 1, (uint8_t *)x} +#define WRDVAL(x) {kCst, 2, (uint8_t *)x} +#define DWRVAL(x) {kCst, 4, (uint8_t *)x} +#define QWRVAL(x) {kCst, 8, (uint8_t *)x} +#define NULVAL {kNul, 0, (uint8_t *)NULL} + +bool get_bootdisplay_val(value_t *val); +bool get_vrammemory_val(value_t *val); +bool get_name_val(value_t *val); +bool get_nameparent_val(value_t *val); +bool get_model_val(value_t *val); +bool get_conntype_val(value_t *val); +bool get_vrammemsize_val(value_t *val); +bool get_binimage_val(value_t *val); +bool get_romrevision_val(value_t *val); +bool get_deviceid_val(value_t *val); +bool get_mclk_val(value_t *val); +bool get_sclk_val(value_t *val); +bool get_refclk_val(value_t *val); +bool get_platforminfo_val(value_t *val); +bool get_vramtotalsize_val(value_t *val); + +typedef struct { + uint32_t flags; + bool all_ports; + char *name; + bool (*get_value)(value_t *val); + value_t default_val; +} dev_prop_t; + +dev_prop_t ati_devprop_list[] = { + {FLAGTRUE, false, "@0,AAPL,boot-display", get_bootdisplay_val, NULVAL }, +// {FLAGTRUE, false, "@0,ATY,EFIDisplay", NULL, STRVAL("TMDSA") }, + +// {FLAGTRUE, true, "@0,AAPL,vram-memory", get_vrammemory_val, NULVAL }, +// {FLAGTRUE, true, "@0,compatible", get_name_val, NULVAL }, +// {FLAGTRUE, true, "@0,connector-type", get_conntype_val, NULVAL }, +// {FLAGTRUE, true, "@0,device_type", NULL, STRVAL("display") }, +// {FLAGTRUE, false, "@0,display-connect-flags", NULL, DWRVAL((uint32_t)0) }, +// {FLAGTRUE, true, "@0,display-type", NULL, STRVAL("NONE") }, + {FLAGTRUE, true, "@0,name", get_name_val, NULVAL }, +// {FLAGTRUE, true, "@0,VRAM,memsize", get_vrammemsize_val, NULVAL }, + +// {FLAGTRUE, false, "AAPL,aux-power-connected", NULL, DWRVAL((uint32_t)1) }, +// {FLAGTRUE, false, "AAPL,backlight-control", NULL, DWRVAL((uint32_t)0) }, + {FLAGTRUE, false, "ATY,bin_image", get_binimage_val, NULVAL }, + {FLAGTRUE, false, "ATY,Copyright", NULL, STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010") }, + {FLAGTRUE, false, "ATY,Card#", get_romrevision_val, NULVAL }, + {FLAGTRUE, false, "ATY,VendorID", NULL, WRDVAL((uint16_t)0x1002) }, + {FLAGTRUE, false, "ATY,DeviceID", get_deviceid_val, NULVAL }, + +// {FLAGTRUE, false, "ATY,MCLK", get_mclk_val, NULVAL }, +// {FLAGTRUE, false, "ATY,SCLK", get_sclk_val, NULVAL }, +// {FLAGTRUE, false, "ATY,RefCLK", get_refclk_val, DWRVAL((uint32_t)0x0a8c) }, + +// {FLAGTRUE, false, "ATY,PlatformInfo", get_platforminfo_val, NULVAL }, + + {FLAGTRUE, false, "name", get_nameparent_val, NULVAL }, + {FLAGTRUE, false, "device_type", get_nameparent_val, NULVAL }, + {FLAGTRUE, false, "model", get_model_val, STRVAL("ATI Radeon") }, +// {FLAGTRUE, false, "VRAM,totalsize", get_vramtotalsize_val, NULVAL }, + + {FLAGTRUE, false, NULL, NULL, NULVAL } +}; + +bool get_bootdisplay_val(value_t *val) +{ + static uint32_t v = 0; + + if (v) + return false; + + if (!card->posted) + return false; + + v = 1; + val->type = kCst; + val->size = 4; + val->data = (uint8_t *)&v; + + return true; +} + +bool get_vrammemory_val(value_t *val) +{ + return false; +} + +bool get_name_val(value_t *val) +{ + val->type = aty_name.type; + val->size = aty_name.size; + val->data = aty_name.data; + + return true; +} + +bool get_nameparent_val(value_t *val) +{ + val->type = aty_nameparent.type; + val->size = aty_nameparent.size; + val->data = aty_nameparent.data; + + return true; +} + +bool get_model_val(value_t *val) +{ + if (!card->info->model_name) + return false; + + val->type = kStr; + val->size = strlen(card->info->model_name) + 1; + val->data = (uint8_t *)card->info->model_name; + + return true; +} + +bool get_conntype_val(value_t *val) +{ +//Connector types: +//0x4 : DisplayPort +//0x400: DL DVI-I +//0x800: HDMI + + return false; +} + +bool get_vrammemsize_val(value_t *val) +{ + static int idx = -1; + static uint64_t memsize; + + idx++; + memsize = ((uint64_t)card->vram_size << 32); + if (idx == 0) + memsize = memsize | (uint64_t)card->vram_size; + + val->type = kCst; + val->size = 8; + val->data = (uint8_t *)&memsize; + + return true; +} + +bool get_binimage_val(value_t *val) +{ + if (!card->rom) + return false; + + val->type = kPtr; + val->size = card->rom_size; + val->data = card->rom; + + return true; +} + +bool get_romrevision_val(value_t *val) +{ + uint8_t *rev; + if (!card->rom) + return false; + + rev = card->rom + *(uint8_t *)(card->rom + OFFSET_TO_GET_ATOMBIOS_STRINGS_START); + + val->type = kPtr; + val->size = strlen((char *)rev); + val->data = malloc(val->size); + + if (!val->data) + return false; + + memcpy(val->data, rev, val->size); + + return true; +} + +bool get_deviceid_val(value_t *val) +{ + val->type = kCst; + val->size = 2; + val->data = (uint8_t *)&card->pci_dev->device_id; + + return true; +} + +bool get_mclk_val(value_t *val) +{ + return false; +} + +bool get_sclk_val(value_t *val) +{ + return false; +} + +bool get_refclk_val(value_t *val) +{ + return false; +} + +bool get_platforminfo_val(value_t *val) +{ + val->data = malloc(0x80); + if (!val->data) + return false; + + bzero(val->data, 0x80); + + val->type = kPtr; + val->size = 0x80; + val->data[0] = 1; + + return true; +} + +bool get_vramtotalsize_val(value_t *val) +{ + val->type = kCst; + val->size = 4; + val->data = (uint8_t *)&card->vram_size; + + return true; +} + +void free_val(value_t *val) +{ + if (val->type == kPtr) + free(val->data); + + bzero(val, sizeof(value_t)); +} + +void devprop_add_list(dev_prop_t devprop_list[]) +{ + value_t *val = malloc(sizeof(value_t)); + int i, pnum; + + for (i = 0; devprop_list[i].name != NULL; i++) + { + if ((devprop_list[i].flags == FLAGTRUE) || (devprop_list[i].flags | card->flags)) + { + if (devprop_list[i].get_value && devprop_list[i].get_value(val)) + { + devprop_add_value(card->device, devprop_list[i].name, val->data, val->size); + free_val(val); + + if (devprop_list[i].all_ports) + { + for (pnum = 1; pnum < card->ports; pnum++) + { + if (devprop_list[i].get_value(val)) + { + devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii + devprop_add_value(card->device, devprop_list[i].name, val->data, val->size); + free_val(val); + } + } + devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card + } + } + else + { + if (devprop_list[i].default_val.type != kNul) + { + devprop_add_value(card->device, devprop_list[i].name, + devprop_list[i].default_val.type == kCst ? + (uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, + devprop_list[i].default_val.size); + } + + if (devprop_list[i].all_ports) + { + for (pnum = 1; pnum < card->ports; pnum++) + { + if (devprop_list[i].default_val.type != kNul) + { + devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii + devprop_add_value(card->device, devprop_list[i].name, + devprop_list[i].default_val.type == kCst ? + (uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, + devprop_list[i].default_val.size); + } + } + devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card + } + } + } + } + + free(val); +} + +bool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev) +{ + option_rom_pci_header_t *rom_pci_header; + + if (rom_header->signature != 0xaa55) + return false; + + rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset); + + if (rom_pci_header->signature != 0x52494350) + return false; + + if (rom_pci_header->vendor_id != pci_dev->vendor_id || rom_pci_header->device_id != pci_dev->device_id) + return false; + + return true; +} + +bool load_vbios_file(const char *key, uint16_t vendor_id, uint16_t device_id, uint32_t subsys_id) +{ + int fd; + char file_name[24]; + bool do_load = false; + + getBoolForKey(key, &do_load, &bootInfo->chameleonConfig); + if (!do_load) + return false; + + sprintf(file_name, "/Extra/%04x_%04x_%08x.rom", vendor_id, device_id, subsys_id); + if ((fd = open_bvdev("bt(0,0)", file_name, 0)) < 0) + return false; + + card->rom_size = file_size(fd); + card->rom = malloc(card->rom_size); + if (!card->rom) + return false; + + read(fd, (char *)card->rom, card->rom_size); + + if (!validate_rom((option_rom_header_t *)card->rom, card->pci_dev)) + { + card->rom_size = 0; + card->rom = 0; + return false; + } + + card->rom_size = ((option_rom_header_t *)card->rom)->rom_size * 512; + + close(fd); + + return true; +} + +void get_vram_size(void) +{ + chip_family_t chip_family = card->info->chip_family; + + card->vram_size = 0; + + if (chip_family >= CHIP_FAMILY_CEDAR) + // size in MB on evergreen + // XXX watch for overflow!!! + card->vram_size = RegRead32(R600_CONFIG_MEMSIZE) * 1024 * 1024; + else + if (chip_family >= CHIP_FAMILY_R600) + card->vram_size = RegRead32(R600_CONFIG_MEMSIZE); +} + +bool read_vbios(bool from_pci) +{ + option_rom_header_t *rom_addr; + + if (from_pci) + { + rom_addr = (option_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff); + verbose(" @0x%x", rom_addr); + } + else + rom_addr = (option_rom_header_t *)0xc0000; + + if (!validate_rom(rom_addr, card->pci_dev)) + return false; + + card->rom_size = rom_addr->rom_size * 512; + if (!card->rom_size) + return false; + + card->rom = malloc(card->rom_size); + if (!card->rom) + return false; + + memcpy(card->rom, (void *)rom_addr, card->rom_size); + + return true; +} + +bool read_disabled_vbios(void) +{ + bool ret = false; + chip_family_t chip_family = card->info->chip_family; + + if (chip_family >= CHIP_FAMILY_RV770) + { + uint32_t viph_control = RegRead32(RADEON_VIPH_CONTROL); + uint32_t bus_cntl = RegRead32(RADEON_BUS_CNTL); + uint32_t d1vga_control = RegRead32(AVIVO_D1VGA_CONTROL); + uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL); + uint32_t vga_render_control = RegRead32(AVIVO_VGA_RENDER_CONTROL); + uint32_t rom_cntl = RegRead32(R600_ROM_CNTL); + uint32_t cg_spll_func_cntl = 0; + uint32_t cg_spll_status; + + // disable VIP + RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); + + // enable the rom + RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); + + // Disable VGA mode + RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + + if (chip_family == CHIP_FAMILY_RV730) + { + cg_spll_func_cntl = RegRead32(R600_CG_SPLL_FUNC_CNTL); + + // enable bypass mode + RegWrite32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN)); + + // wait for SPLL_CHG_STATUS to change to 1 + cg_spll_status = 0; + while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) + cg_spll_status = RegRead32(R600_CG_SPLL_STATUS); + + RegWrite32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); + } + else + RegWrite32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); + + ret = read_vbios(true); + + // restore regs + if (chip_family == CHIP_FAMILY_RV730) + { + RegWrite32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); + + // wait for SPLL_CHG_STATUS to change to 1 + cg_spll_status = 0; + while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) + cg_spll_status = RegRead32(R600_CG_SPLL_STATUS); + } + RegWrite32(RADEON_VIPH_CONTROL, viph_control); + RegWrite32(RADEON_BUS_CNTL, bus_cntl); + RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control); + RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + RegWrite32(R600_ROM_CNTL, rom_cntl); + } + else + if (chip_family >= CHIP_FAMILY_R600) + { + uint32_t viph_control = RegRead32(RADEON_VIPH_CONTROL); + uint32_t bus_cntl = RegRead32(RADEON_BUS_CNTL); + uint32_t d1vga_control = RegRead32(AVIVO_D1VGA_CONTROL); + uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL); + uint32_t vga_render_control = RegRead32(AVIVO_VGA_RENDER_CONTROL); + uint32_t rom_cntl = RegRead32(R600_ROM_CNTL); + uint32_t general_pwrmgt = RegRead32(R600_GENERAL_PWRMGT); + uint32_t low_vid_lower_gpio_cntl = RegRead32(R600_LOW_VID_LOWER_GPIO_CNTL); + uint32_t medium_vid_lower_gpio_cntl = RegRead32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); + uint32_t high_vid_lower_gpio_cntl = RegRead32(R600_HIGH_VID_LOWER_GPIO_CNTL); + uint32_t ctxsw_vid_lower_gpio_cntl = RegRead32(R600_CTXSW_VID_LOWER_GPIO_CNTL); + uint32_t lower_gpio_enable = RegRead32(R600_LOWER_GPIO_ENABLE); + + // disable VIP + RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); + + // enable the rom + RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); + + // Disable VGA mode + RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + RegWrite32(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | R600_SCK_OVERWRITE)); + RegWrite32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); + RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); + + ret = read_vbios(true); + + // restore regs + RegWrite32(RADEON_VIPH_CONTROL, viph_control); + RegWrite32(RADEON_BUS_CNTL, bus_cntl); + RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control); + RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + RegWrite32(R600_ROM_CNTL, rom_cntl); + RegWrite32(R600_GENERAL_PWRMGT, general_pwrmgt); + RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); + RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); + RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); + RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); + RegWrite32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); + } + + return ret; +} + +bool radeon_card_posted(void) +{ + uint32_t reg; + + // first check CRTCs + reg = RegRead32(RADEON_CRTC_GEN_CNTL) | RegRead32(RADEON_CRTC2_GEN_CNTL); + if (reg & RADEON_CRTC_EN) + return true; + + // then check MEM_SIZE, in case something turned the crtcs off + reg = RegRead32(R600_CONFIG_MEMSIZE); + if (reg) + return true; + + return false; +} + +#if 0 +bool devprop_add_pci_config_space(void) +{ + int offset; + + uint8_t *config_space = malloc(0x100); + if (!config_space) + return false; + + for (offset = 0; offset < 0x100; offset += 4) + config_space[offset / 4] = pci_config_read32(card->pci_dev->dev.addr, offset); + + devprop_add_value(card->device, "ATY,PCIConfigSpace", config_space, 0x100); + free(config_space); + + return true; +} +#endif + +static bool init_card(pci_dt_t *pci_dev) +{ + bool add_vbios = true; + char name[24]; + char name_parent[24]; + int i; + int n_ports = 0; + + card = malloc(sizeof(card_t)); + if (!card) + return false; + bzero(card, sizeof(card_t)); + + card->pci_dev = pci_dev; + + for (i = 0; radeon_cards[i].device_id ; i++) + { + if (radeon_cards[i].device_id == pci_dev->device_id) + { + card->info = &radeon_cards[i]; + if ((radeon_cards[i].subsys_id == 0x00000000) || + (radeon_cards[i].subsys_id == pci_dev->subsys_id.subsys_id)) + break; + } + } + + if (!card->info->device_id || !card->info->cfg_name) + { + printf("Unsupported card!\n"); + return false; + } + + card->fb = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_0) & ~0x0f); + card->mmio = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f); + card->io = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03); + + verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n", + card->fb, card->mmio, card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS)); + + card->posted = radeon_card_posted(); + verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed"); + + get_vram_size(); + + getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->chameleonConfig); + + if (add_vbios) + { + if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id)) + { + verbose("reading VBIOS from %s", card->posted ? "legacy space" : "PCI ROM"); + if (card->posted) + read_vbios(false); + else + read_disabled_vbios(); + verbose("\n"); + } + } + +// card->ports = 2; // default - Azi: default is card_configs + + if (card->info->chip_family >= CHIP_FAMILY_CEDAR) + { + card->flags |= EVERGREEN; +// card->ports = 3; //Azi: use the AtiPorts key if needed + } + +// atN = 0; + + // Check AtiConfig key for a framebuffer name, + card->cfg_name = getStringForKey(kAtiConfig, &bootInfo->chameleonConfig); + // if none, + if (!card->cfg_name) + { + // use cfg_name on radeon_cards, to retrive the default name from card_configs, + card->cfg_name = card_configs[card->info->cfg_name].name; + // and leave ports alone! +// card->ports = card_configs[card->info->cfg_name].ports; + + // which means one of the fb's or kNull + verbose("Framebuffer set to device's default: %s\n", card->cfg_name); + } + else + { + // else, use the fb name returned by AtiConfig. + verbose("(AtiConfig) Framebuffer set to: %s\n", card->cfg_name); + } + + // Check AtiPorts key for nr of ports, + card->ports = getIntForKey(kAtiPorts, &n_ports, &bootInfo->chameleonConfig); + // if a value bigger than 0 ?? is found, (do we need >= 0 ?? that's null FB on card_configs) + if (n_ports > 0) + { + card->ports = n_ports; // use it. + verbose("(AtiPorts) Nr of ports set to: %d\n", card->ports); + } + else// if (card->cfg_name > 0) // do we want 0 ports if fb is kNull or mistyped ? + { + // use max_ports value on radeon_cards + card->ports = card->info->max_ports; + // if max_ports value is 0 + if (card->ports <= 0) + { + // match cfg_name with card_configs list and retrive default nr of ports. + for (i = 0; i < kCfgEnd; i++) + { + if (strcmp(card->cfg_name, card_configs[i].name) == 0) + card->ports = card_configs[i].ports; // default + } + verbose("Nr of ports set to framebuffer's default: %d\n", card->ports); + } + else + { + verbose("Nr of ports set to card's ?? max: %d\n", card->ports); + } + } +// else +// card->ports = 2/1 ?; // set a min if 0 ports ? +// verbose("Nr of ports set to min: %d\n", card->ports); + + sprintf(name, "ATY,%s", card->cfg_name); + aty_name.type = kStr; + aty_name.size = strlen(name) + 1; + aty_name.data = (uint8_t *)name; + + sprintf(name_parent, "ATY,%sParent", card->cfg_name); + aty_nameparent.type = kStr; + aty_nameparent.size = strlen(name_parent) + 1; + aty_nameparent.data = (uint8_t *)name_parent; + + return true; +} + +bool setup_ati_devprop(pci_dt_t *ati_dev) +{ + char *devicepath; + + if (!init_card(ati_dev)) + return false; + + // ------------------------------------------------- + // Find a better way to do this (in device_inject.c) + if (!string) + string = devprop_create_string(); + + devicepath = get_pci_dev_path(ati_dev); + card->device = devprop_add_device(string, devicepath); + if (!card->device) + return false; + // ------------------------------------------------- + +#if 0 + uint64_t fb = (uint32_t)card->fb; + uint64_t mmio = (uint32_t)card->mmio; + uint64_t io = (uint32_t)card->io; + devprop_add_value(card->device, "ATY,FrameBufferOffset", &fb, 8); + devprop_add_value(card->device, "ATY,RegisterSpaceOffset", &mmio, 8); + devprop_add_value(card->device, "ATY,IOSpaceOffset", &io, 8); +#endif + + devprop_add_list(ati_devprop_list); + + // ------------------------------------------------- + // Find a better way to do this (in device_inject.c) + //Azi: XXX tried to fix a malloc error in vain; this is related to XCode 4 compilation! + stringdata = malloc(sizeof(uint8_t) * string->length); + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + // ------------------------------------------------- + + verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n", + chip_family_name[card->info->chip_family], card->info->model_name, + (uint32_t)(card->vram_size / (1024 * 1024)), card->cfg_name, + ati_dev->vendor_id, ati_dev->device_id, + ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id, + devicepath); + + free(card); + + return true; +} Index: branches/ErmaC/i386/modules/Makefile =================================================================== --- branches/ErmaC/i386/modules/Makefile (revision 1567) +++ branches/ErmaC/i386/modules/Makefile (revision 1568) @@ -33,6 +33,22 @@ SUBDIRS += Keylayout endif +ifdef CONFIG_ATIGRAPHICSENABLER_MODULE +SUBDIRS += ATiGraphicsEnabler +endif + +ifdef CONFIG_AMDGRAPHICSENABLER_MODULE +SUBDIRS += AMDGraphicsEnabler +endif + +ifdef CONFIG_NVIDIAGRAPHICSENABLER_MODULE +SUBDIRS += NVIDIAGraphicsEnabler +endif + +ifdef CONFIG_INTELGRAPHICSENABLER_MODULE +SUBDIRS += IntelGraphicsEnabler +endif + CFLAGS= -O3 $(MORECPP) -arch i386 -g -static DEFINES= CONFIG = hd Index: branches/ErmaC/package/Scripts/Standard/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Standard/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Standard/postinstall (revision 1568) @@ -1,364 +1,182 @@ #!/bin/bash - -diskloader="boot0" -diskloaderdualboot="boot0md" -partitionloaderhfs="boot1h" -partitionloaderfat="boot1f32" -filesystemloader="boot" - -diskmicrocodetype[1]="GRUB,47525542" -diskmicrocodetype[2]="LILO,4c494c4f" - -start () -{ -# $1 volume - -bootvolume="${@}" -echo "Volume is $bootvolume" -bootresources="${0%/*}" -echo "$bootresources" - -if [ -z "${bootvolume}" ]; then - echo - echo "Cannot find the volume. Exiting." - echo - exit -fi - -bootdev=$( df "${bootvolume}" | sed -n '2p' | awk '{print $1}' ) -bootrdev=${bootdev/disk/rdisk} - -if [ "${bootdev}" = "${bootdev#*disk*s}" ]; then - echo - echo "ERROR Volume does not use slices." - echo - exit -fi - -bootdisk=${bootdev%s*} -bootrdisk=${bootdisk/disk/rdisk} -bootslice=${bootdev#*disk*s} - echo "===============================================" -echo "Installer Variables:" -echo "********************" -echo "bootvolume: Volume is ${bootvolume}" -echo "bootdev: Volume device is ${bootdev}" -echo "bootrdev: Volume raw device is ${bootrdev}" -echo "bootslice: Volume slice is ${bootslice}" -echo "bootdisk: Disk device is ${bootdisk}" -echo "bootrdisk: Disk raw device is ${bootrdisk}" -echo "diskloader: Disk loader is ${diskloader}" -echo "partitionloaderhfs: Partition loader is ${partitionloaderhfs}" -echo "partitionloaderfat: Partition loader is ${partitionloaderfat}" -echo "filesystemloader: Filesystem loader is ${filesystemloader}" -echo "bootresources: Boot Resources is ${bootresources}" +echo "Main Standard Post-Install Script" +echo "*********************************" echo "-----------------------------------------------" echo "" -echo "" -} -checkdiskmicrocodetype () -{ -echo "===============================================" -echo "Diskmicrocodetype:" -echo "******************" +# Find location of this script in the package installer +# so we know where all the other scripts are located. -diskmicrocode=$( dd 2>/dev/null if=${bootdisk} count=1 | dd 2>/dev/null count=1 bs=437 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) -diskmicrocodetypecounter=0 -while [ ${diskmicrocodetypecounter} -lt ${#diskmicrocodetype[@]} ]; do - diskmicrocodetypecounter=$(( ${diskmicrocodetypecounter} + 1 )) - diskmicrocodetypeid=${diskmicrocodetype[${diskmicrocodetypecounter}]#*,} - if [ ! "${diskmicrocode}" = "${diskmicrocode/${diskmicrocodetypeid}/}" ]; then - echo "${diskmicrocodetype[${diskmicrocodetypecounter}]%,*} found." - else - echo "Didn't find a match for ${diskmicrocodetype[${diskmicrocodetypecounter}]%,*}" - fi -done -echo "-----------------------------------------------" -echo "" -echo "" -} +MYLOCATION="${PWD}/${BASH_ARGV[0]}" +export MYLOCATION="${MYLOCATION%/*}" +scriptDir=$MYLOCATION +#echo "===============================================" +#echo "Apple Installer Package Variables" +#echo "*********************************" +#echo "DEBUG: $ 1 = Full path to the installation package the installer app is processing: " $1 +#echo "DEBUG: $ 2 = Full path to the installation destination: " $2 +#echo "DEBUG: $ 3 = Installation volume (mountpoint) to receive the payload: " $3 +#echo "DEBUG: $ 4 = Root directory for the system: " $4 +#echo "DEBUG: Script Name: " $SCRIPT_NAME +#echo "DEBUG: Package Path: " $PACKAGE_PATH +#echo "DEBUG: Installer Temp: " $INSTALLER_TEMP +#echo "DEBUG: Full path to the temp directory containing the operation executable: " $RECEIPT_PATH +#echo "-----------------------------------------------" +#echo "" -checkdiskmicrocode () -{ -echo "===============================================" -echo "Diskmicrocode:" -echo "*************" -# Note: The checks for Boot0 and Boot0hfs assume the code doesn't change!! -# 1 action ( check or set ) +# Initialise Script Globals -diskmicrocode=$( dd 2>/dev/null if=${bootdisk} count=1 | dd 2>/dev/null count=1 bs=437 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) -diskmicrocodemd5=$( dd 2>/dev/null if=${bootdisk} count=1 | dd 2>/dev/null count=1 bs=437 | md5 ) +stage0Loader="boot0" +stage0LoaderDualBoot="boot0md" +stage1LoaderHFS="boot1h" +stage1LoaderFAT="boot1f32" +stage2Loader="boot" -#echo "${diskmicrocode}" +targetVolume=$3 +targetDevice=$( df "${targetVolume}" | sed -n '2p' | awk '{print $1}' ) +targetDeviceRaw=${targetDevice/disk/rdisk} +targetDisk=${targetDevice%s*} +targetDiskRaw=${targetDisk/disk/rdisk} +targetSlice=${targetDevice#*disk*s} -if [ $( echo "${diskmicrocode}" | awk -F0 '{print NF-1}' ) = 874 ]; then - echo "Diskmicrocode = 874 (Which means the first 437 bytes of the MBR Disk Sector is blank)" - if [ "${1}" = "set" ]; then - echo "No disk microcode found. Updating." - diskupdate=true - echo "diskupdate is now set to true." - else - echo "No disk microcode found." - fi -else - # There is already something on the MBR - if [ ${1} = set ]; then +targetResources="${targetVolume}/usr/local/bin/" - # See if a Windows bootloader already exists - windowsloader=$( dd 2>/dev/null if=${bootdisk} count=4 bs=1 | xxd | awk '{print $2$3}' ) - if [ "${windowsloader}" == "33c08ed0" ] ; then - echo "Found existing Windows Boot Loader" - echo "Will replace loader with Boot0hfs" - diskupdate=true - echo "diskupdate is now set to true." - fi +echo "===============================================" +echo "DEBUG: display script variables" +echo "*******************************" - # See if a Chameleon stage0 boot file already exists - stage0type=$( dd 2>/dev/null if=${bootdisk} count=3 bs=1 skip=105 | xxd | awk '{print $2$3}' ) - if [ "${stage0type}" == "0b807c" ] || [ "${stage0type}" == "0a803c" ] ; then - - echo "Found existing Chameleon Stage 0 Loader" - # if found Boot0HFS without a Windows installation set diskupdate to true - if [ "${stage0type}" == "0b807c" ] && [ "${disksignature}" == "00000000" ]; then - echo "Found existing Chameleon Boot0HFS without a Windows installation" - echo "Will replace loader with Boot0" - diskupdate=true - echo "diskupdate is now set to true." - fi - - # if found Boot0 with a Windows installation set diskupdate to true - if [ "${stage0type}" == "0a803c" ] && [ "${disksignature}" != "00000000" ]; then - echo "Found existing Chameleon Boot0 with a Windows installation" - echo "Will replace loader with Boot0hfs" - diskupdate=true - echo "diskupdate is now set to true." - fi - fi - - # If neither a Windows or Chameleon Boot Loader exists - if [ "${stage0type}" != "0b807c" ] && [ "${stage0type}" != "0a803c" ] && [ "${windowsloader}" != "33c08ed0" ] ; then - test=$(echo "${diskmicrocode}" | awk -F0 '{print NF-1}' ) - echo "Disk microcode found: ${test} - Preserving." - echo "diskupdate is left at false" - fi - else - test=$(echo "${diskmicrocode}" | awk -F0 '{print NF-1}' ) - echo "Disk microcode found: ${test}" - fi - echo "Disk microcode MD5 is ${diskmicrocodemd5}" -fi +echo "DEBUG: stage0Loader: Disk loader is ${stage0Loader}" +echo "DEBUG: stage0LoaderDualBoot: Disk loader is ${stage0LoaderDualBoot}" +echo "DEBUG: stage1LoaderHFS: Partition loader is ${stage1LoaderHFS}" +echo "DEBUG: stage1LoaderFat: Partition loader is ${stage1LoaderFAT}" +echo "DEBUG: stage2Loader: Filesystem loader is ${stage2Loader}" +echo "DEBUG: targetVolume: Volume is ${targetVolume}" +echo "DEBUG: targetDevice: Volume device is ${targetDevice}" +echo "DEBUG: targetDeviceRaw: Volume raw device is ${targetDeviceRaw}" +echo "DEBUG: targetDisk: Disk device is ${targetDisk}" +echo "DEBUG: targetDiskRaw: Disk raw device is ${targetDiskRaw}" +echo "DEBUG: targetSlice: Volume slice is ${targetSlice}" +echo "DEBUG: targetResources: Boot Resources is ${targetResources}" echo "-----------------------------------------------" echo "" -echo "" -} -checkdisksignature () -{ -echo "===============================================" -echo "Find Disk Signature:" -echo "*************" +# Write some information to the Install Log +versionNumber=`cat "${scriptDir}"/Resources/version` +revisionNumber=`cat "${scriptDir}"/Resources/revision` +"$scriptDir"InstallLog.sh "${targetVolume}" "Installer version: ${versionNumber} ${revisionNumber}" +"$scriptDir"InstallLog.sh "${targetVolume}" "Running Standard postinstall script +Target volume = ${targetVolume}" -disksignature=$( dd 2>/dev/null if=${bootdisk} count=1 | dd 2>/dev/null count=4 bs=1 skip=440 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) -echo "${disksignature}" +# Double check we can see the selected partition and it's of the right type +# if not the following script returns to indicate failure. -if [ $disksignature = "00000000" ]; then - echo "Just Zero's found meaning Windows isn't installed." -else - echo "Non Zero means we've found a Windows installation" -fi -echo "-----------------------------------------------" -echo "" -echo "" -} +"$scriptDir"CheckProceed.sh "${targetVolume}" "${targetDevice}" "${targetVolume}" "${scriptDir}" +returnValue=$? +if [ ${returnValue}=0 ]; then + # OK to proceed + # Does a GRUB or Linux loader already exist in the disk's MBR? + # The script returns 1 if yes, 0 if no. -checkpartitionbootcode () -{ -echo "===============================================" -echo "Find Partition Bootcode:" -echo "************************" + "$scriptDir"CheckGRUBLinuxLoader.sh "${targetDisk}" "${targetVolume}" "${scriptDir}" + returnValue=$? + if [ ${returnValue} = 0 ]; then + # OK to proceed -# 1 action ( check or set ) -partitionbootcode=$( dd if=${bootrdev} count=1 2>/dev/null | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) -partitionbootcodeextended=$( dd if=${bootrdev} count=1 skip=1 2>/dev/null | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) + # check for a 4-byte Windows disk signature in the disk's MBR. + # the following script returns 1 if a Windows disk signature exists, and 0 if not. -echo "${partitionbootcode}" + "$scriptDir"CheckWindowsDiskSignature.sh "${targetDisk}" "${targetVolume}" "${scriptDir}" + diskSigCheck=$? -if [ $( echo "${partitionbootcode}" | awk -F0 '{print NF-1}' ) = 1024 ]; then - echo "partitionbootcode = 1024 (Which means the whole 512 bytes of the MBR Disk Sector is blank)" - if [ "${1}" = "set" ]; then - echo "No partition bootcode found. Updating." - else - echo "No partition bootcode found." - fi -else - if [ "${1}" = "set" ]; then - echo "Partition bootcode found. Overwriting." - else - echo "Partition bootcode found." - fi - if [ $( echo "${partitionbootcodeextended}" | awk -F0 '{print NF-1}' ) = 1024 ]; then - partitionbootcodemd5=$( dd 2>/dev/null if=${bootrdev} count=1 | md5 ) - else - partitionbootcodemd5=$( dd 2>/dev/null if=${bootrdev} count=2 | md5 ) - echo "Partition bootcode is dual sector." - fi - echo "Partition bootcode MD5 is ${partitionbootcodemd5}" -fi -echo "-----------------------------------------------" -echo "" -echo "" -} + # check for existing bootloaders in the disk's MBR + # and find out if we can write the Chameleon boot files. + # the following script returns 0 if we can proceed + # with writing the boot files, and 1 for not. + "$scriptDir"CheckDiskMicrocode.sh "${targetDisk}" "${diskSigCheck}" "${targetVolume}" "${scriptDir}" + diskupdate=$? -start ${3} + # check the format of the selected partition. + # the following script returns 1 if HFS + # the following script returns 2 if MSDOS + # the following script returns 0 if nothing -echo "===============================================" -echo "Check the format of the selected partition" -echo "*************************************" + "$scriptDir"CheckFormat.sh "${targetDevice}" "${targetVolume}" "${scriptDir}" + espformat=$? -if [ "$( fstyp ${bootdev} | grep hfs )" ]; then - echo "${bootdev} is currently formatted as HFS" - efiformat="hfs" -fi -if [ "$( fstyp ${bootdev} | grep msdos )" ]; then - echo "${bootdev} is currently formatted as msdos" - efiformat="msdos" -fi -echo "-----------------------------------------------" -echo "" -echo "" + # check the partition scheme used for the selected disk. + # the following script returns 1 if GPT + # the following script returns 2 if GPT/MBR + # the following script returns 3 if MBR + # the following script returns 0 if nothing -echo "===============================================" -echo "Determine Partition Scheme:" -echo "***************************" + "$scriptDir"CheckPartitionScheme.sh "${targetDisk}" "${targetVolume}" "${scriptDir}" + partitionTable=$? + if [ ${partitionTable} = 3 ]; then + # If MBR partition scheme then check for FAT16 or FAT32 -partitiontable=$( dd 2>/dev/null if=${bootdisk} count=1 skip=1 | dd 2>/dev/null count=8 bs=1 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) -if [ "${partitiontable:0:16}" == "4546492050415254" ]; then - partitiontable=$( dd 2>/dev/null if=${bootdisk} count=1 | dd 2>/dev/null count=64 bs=1 skip=446 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) - if [ "${partitiontable:8:2}" == "ee" ]; then - echo "Found System ID 'EE' to identify GPT Partition" - if [ "${partitiontable:40:2}" == "00" ] && [ "${partitiontable:72:2}" == "00" ] && [ "${partitiontable:104:2}" == "00" ]; then - echo "Found System ID '00' for each remaining possible partition" - partitiontable="GPT" - else - partitiontable="GPT/MBR" + # the following script returns 1 if FAT16 + # the following script returns 2 if FAT32 + # the following script returns 0 if nothing + + "$scriptDir"CheckFatType.sh "${targetDeviceRaw}" "${targetVolume}" "${scriptDir}" + fatType=$? fi - fi -else - partitiontable="MBR" -fi -echo "${partitiontable} found." -echo "-----------------------------------------------" -echo "" -echo "" + if [ "${fatType}" = 1 ] && [ "${partitionTable}" = 3 ]; then + echo "ERROR: - Can't install to a device using FAT16" + # Write error to Chameleon_Error_Log file + "$scriptDir"InstallLog.sh "${targetVolume}" "FAIL: Cannot install to a device using FAT16" + else + # Continue if the selected device is not a FAT16 format device + # Append a line break to the installer log + "$scriptDir"InstallLog.sh "${targetVolume}" "Line Break" -diskupdate=false + if [ ${diskupdate} = "0" ]; then + # Write the stage 0 loader to the MBR + "$scriptDir"WriteChameleonStage0.sh "${diskSigCheck}" "${stage0Loader}" "${stage0LoaderDualBoot}" "${targetDisk}" "${targetResources}" "${targetVolume}" "${scriptDir}" + else + #echo "Diskupdate = false, so didn't write the stage 0 loader to the MBR." + "$scriptDir"InstallLog.sh "${targetVolume}" "Stage 0 loader not written to ${targetDisk}." + fi + # Write the stage 1 loader to the partition boot sector + "$scriptDir"WriteChameleonStage1.sh "${espformat}" "${stage1LoaderHFS}" "${stage1LoaderFAT}" "${3}" "${targetDeviceRaw}" "${targetVolume}" "${scriptDir}" -checkdisksignature -checkdiskmicrocodetype -checkdiskmicrocode set -checkpartitionbootcode set + # Write the stage 2 loader to the root of the selected partition + "$scriptDir"WriteChameleonStage2.sh "${espformat}" "${stage2Loader}" "${3}" "${targetDevice}" "${targetVolume}" "${scriptDir}" + # Append a line break to the installer log + "$scriptDir"InstallLog.sh "${targetVolume}" "Line Break" - -echo "===============================================" -echo "Can we install the Chameleon bootloader files?" -echo "**********************************************" - -if ${diskupdate}; then - echo "Diskupdate = true, so yes" - #--------------------------------------------------------------------- - # Check bytes 438-446 of the GPTdiskProtectiveMBR for a Windows Disk Signature - # If there's no Windows disk signature then we can write boot0 - #--------------------------------------------------------------------- - - if [ ${disksignature} == "00000000" ]; then - echo "Executing command: fdisk440 -u -f /usr/standalone/i386/${diskloader} -y ${bootdisk}" - "${bootresources}/Tools/fdisk440" -u -f "${bootvolume}/usr/standalone/i386/${diskloader}" -y ${bootdisk} - else - #--------------------------------------------------------------------- - # If it exists then Windows is also installed on the HDD and we need to write boot0hfs - #--------------------------------------------------------------------- - echo "Executing command: fdisk440 -u -f /usr/standalone/i386/${diskloaderdualboot} -y ${bootdisk}" - "${bootresources}/Tools/fdisk440" -u -f "${bootvolume}/usr/standalone/i386/${diskloaderdualboot}" -y ${bootdisk} + # Set the active partition ONLY if Windows is not installed + "$scriptDir"SetActivePartition.sh "${espformat}" "${diskSigCheck}" "${targetDiskRaw}" "${targetSlice}" "${targetVolume}" "${scriptDir}" + fi fi -else -echo "Diskupdate is false, so no stage 0 file was written" fi -if [ ${efiformat} = "hfs" ]; then - echo "Executing command: dd if=/usr/standalone/i386/${partitionloaderhfs} of=${bootrdev}" - dd if="${bootvolume}/usr/standalone/i386/${partitionloaderhfs}" of=${bootrdev} -fi +"$scriptDir"InstallLog.sh "${targetVolume}" "Line Break" +"$scriptDir"InstallLog.sh "${targetVolume}" "Standard script complete" -if [ ${efiformat} = "msdos" ]; then - echo "Executing command: dd if=/usr/standalone/i386/${partitionloaderfat} of=${bootrdev}" - dd if="${bootvolume}/usr/standalone/i386/${partitionloaderfat}" of=${bootrdev} -fi - -echo "Executing command: cp /usr/standalone/i386/${filesystemloader} ${bootvolume}" -cp "${bootvolume}/usr/standalone/i386/${filesystemloader}" "${bootvolume}" - -echo "Executing command: ${bootresources}/Tools/SetFile -a V ${bootvolume}/${filesystemloader}" -"${bootresources}/Tools/SetFile" -a V "${bootvolume}/${filesystemloader}" - -echo "-----------------------------------------------" -echo "" -echo "" - - echo "===============================================" -echo "Set Active Partition ONLY if Windows is not installed" -echo "*****************************************************" - -if [ ${disksignature} == "00000000" ]; then - # echo "Windows is not installed so let's change the active partition" - - partitionactive=$( "${bootresources}/Tools/fdisk440" -d ${bootrdisk} | grep -n "*" | awk -F: '{print $1}') - echo "Current Active Partition: ${partitionactive}" - - if [ "${partitionactive}" = "${bootslice}" ]; then - echo "${bootvolume} is already flagged as active" - else - echo "${bootvolume} is not flagged as active, so let's do it." - # BadAxe requires EFI partition to be flagged active. - # but it doesn't' hurt to do it for any non-windows partition. - - "${bootresources}/Tools/fdisk440" -e ${bootrdisk} <<-MAKEACTIVE - print - flag ${bootslice} - write - y - quit - MAKEACTIVE - fi -else - echo "Windows is installed so we let that remain the active partition" -fi +echo "END - Standard Post-Install Script" +echo "*********************************" echo "-----------------------------------------------" echo "" -echo "" -# hide boot file -chflags hidden "${3}/boot" -echo "boot file hidden ${3}/boot" - -exit +exit 0 Index: branches/ErmaC/package/Scripts/Advanced/ForceHPET/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/ForceHPET/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/ForceHPET/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/UseKernelCache/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/UseKernelCache/postinstall (revision 0) +++ branches/ErmaC/package/Scripts/Advanced/UseKernelCache/postinstall (revision 1568) @@ -0,0 +1,39 @@ +#!/usr/bin/python +# Script to add UseKernelCache for Chameleon boot loaders + +import sys +import os +import shutil + +vol = str(sys.argv[3]) +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" +plist = vol + boot + +if not os.path.exists(plist): + shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) + +infile = open(plist, "r") +# check if UseKernelCache has been written or not +UseKernelCacheCheck = False + +body = "" + +for line in infile: + # if we finish the tags and haven't written UseKernelCache Yet + if "" in line and UseKernelCacheCheck == False: + line = " UseKernelCache\n" + line += " Yes\n" + line += "\n" + UseKernelCacheCheck = True + + body += line + +infile.close() + +outfile = open(plist, "w") +outfile.write(body) +outfile.close() Property changes on: branches/ErmaC/package/Scripts/Advanced/UseKernelCache/postinstall ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Advanced/EHCIacquire/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/EHCIacquire/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/EHCIacquire/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/VBIOS/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/VBIOS/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/VBIOS/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/GUI/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/GUI/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/GUI/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/SMBIOSdefaults/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/SMBIOSdefaults/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/SMBIOSdefaults/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/UseMemDetect/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/UseMemDetect/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/UseMemDetect/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/LegacyLogo/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/LegacyLogo/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/LegacyLogo/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/Wake/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/Wake/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/Wake/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/BootBanner/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/BootBanner/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/BootBanner/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/Npci/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/Npci/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/Npci/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/UHCIreset/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/UHCIreset/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/UHCIreset/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/ShowInfo/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/ShowInfo/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/ShowInfo/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/Wait/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/Wait/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/Wait/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/UseNvidiaROM/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/UseNvidiaROM/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/UseNvidiaROM/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/ForceWake/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/ForceWake/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/ForceWake/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/UseAtiROM/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/UseAtiROM/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/UseAtiROM/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Advanced/QuietBoot/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Advanced/QuietBoot/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Advanced/QuietBoot/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Post/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Post/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Post/postinstall (revision 1568) @@ -17,11 +17,11 @@ echo "preinstall: Path to dest volume..... $3" echo "preinstall: Root of system folder... $4" -set -x +#set -x # Useful for echoing everything the script does to the installer log!! if [ ! -e "$3" ] then - echo "destination volume does not exist!" + echo "$3 volume does not exist!" exit 1 fi @@ -33,8 +33,43 @@ dest_vol="$3" fi +# Extra folder now resides in /tmpcham. +# Copy /tmpcham/Extra to correct location. +if [ ! -f "$dest_vol"/.ChameleonEFI ]; then + echo "Copying $dest_vol/tmpcham/Extra/* $dest_vol/Extra" + if [ ! -f "$dest_vol"/Extra ]; then + mkdir "$dest_vol"/Extra + fi + cp -R "$dest_vol"/tmpcham/Extra/* "$dest_vol"/Extra +else + echo "Copying $dest_vol/tmpcham/Extra/* $/Volumes/EFI/Extra" + if [ ! -f "/Volumes/EFI/Extra" ]; then + mkdir "/Volumes/EFI/Extra" + fi + cp -R "$dest_vol"/tmpcham/Extra/* /Volumes/EFI/Extra + + # unmount /Volumes/EFI + attempts=1 + while [ "$( df | grep EFI )" ] && [ "${attempts}" -lt 5 ]; do + echo "Unmounting $( df | grep EFI | awk '{print $1}' )" + umount -f $( df | grep EFI | awk '{print $1}' ) + attempts=$(( ${attempts} + 1 )) + done + + # Remove /.ChameleonEFI file + echo "Removing /.ChameleonEFI file" + rm "$dest_vol"/.ChameleonEFI +fi + +# Remove /.ChameleonLogFlag file +if [ -f "$dest_vol"/.ChameleonLogFlag ]; then + echo "Removing /.ChameleonLogFlag file" + rm "$dest_vol"/.ChameleonLogFlag +fi + # delete the temporary Chameleon folder - +echo "Removing $dest_vol/tmpcham file" rm -rf "$dest_vol/tmpcham" + echo "Done..." Index: branches/ErmaC/package/Scripts/BaseOptions/GenerateCStates/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/GenerateCStates/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/GenerateCStates/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/DropSSDT/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/DropSSDT/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/DropSSDT/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/EthernetBuiltIn/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/EthernetBuiltIn/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/EthernetBuiltIn/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/InstantMenu/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/InstantMenu/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/InstantMenu/postinstall (revision 1568) @@ -7,8 +7,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/SkipFTFix/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/SkipFTFix/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/SkipFTFix/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/GraphicsEnabler/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/GraphicsEnabler/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/GraphicsEnabler/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/RestartFix/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/RestartFix/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/RestartFix/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/CSTUsingSystemIO/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/CSTUsingSystemIO/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/CSTUsingSystemIO/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/EnableC2State/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/EnableC2State/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/EnableC2State/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/EnableC3State/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/EnableC3State/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/EnableC3State/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/arch/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/arch/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/arch/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/EnableC4State/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/EnableC4State/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/EnableC4State/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/BaseOptions/GeneratePStates/postinstall =================================================================== --- branches/ErmaC/package/Scripts/BaseOptions/GeneratePStates/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/BaseOptions/GeneratePStates/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Install/CheckFormat.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/CheckFormat.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/CheckFormat.sh (revision 1568) @@ -0,0 +1,50 @@ +#!/bin/bash + +echo "===============================================" +echo "CheckFormat: Is target HFS or MSDOS?" +echo "**********************************************" + +# if the selected partition is formatted as HFS then exit with 1 +# if the selected partition is formatted as MSDOS then exit with 2 +# if fstyp doesn't return a value then exit with 0 + +# Receives targetDevice: for example, /dev/disk0s2 +# Receives targetVolume: Volume to install to. +# Receives scriptDir: The location of the main script dir. + + +if [ "$#" -eq 3 ]; then + targetDevice="$1" + targetVolume="$2" + scriptDir="$3" + echo "DEBUG: passed argument for targetDevice = $targetDevice" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + +if [ "$( fstyp "$targetDevice" | grep hfs )" ]; then + echo "${targetDevice} is currently formatted as HFS" + echo "-----------------------------------------------" + echo "" + #"$scriptDir"InstallLog.sh "${targetVolume}" "${targetDevice} is currently formatted as HFS" + exit 1 + +fi +if [ "$( fstyp "$targetDevice" | grep msdos )" ]; then + echo "${targetDevice} is currently formatted as msdos" + echo "-----------------------------------------------" + echo "" + #"$scriptDir"InstallLog.sh "${targetVolume}" "${targetDevice} is currently formatted as msdos" + exit 2 +fi + +echo "WARNING: ${targetDevice} is currently not formatted as either HFS or msdos" +echo "-----------------------------------------------" +echo "" + +"$scriptDir"InstallLog.sh "${targetVolume}" "WARNING: ${targetDevice} is currently not formatted as either HFS or msdos" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/CheckFormat.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/InstallLog.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/InstallLog.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/InstallLog.sh (revision 1568) @@ -0,0 +1,73 @@ +#!/bin/bash + +echo "===============================================" +echo "InstallLog: Create/Append installation log" +echo "**********************************************" + +# Creates text file named 'Chameleon_Installer_Log.txt' +# at the root of the target volume. This is to help show the +# user why the installation process failed (even though the +# package installer ends reading 'Installation Successful'. + +# Receives two parameters +# $1 = selected volume for location of the install log +# $2 = text to write to the installer log + +if [ "$#" -eq 2 ]; then + logLocation="$1" + verboseText="$2" + echo "DEBUG: passed argument = $logLocation" + echo "DEBUG: passed argument = $verboseText" +else + echo "Error - wrong number of values passed" + exit 9 +fi + +logName="Chameleon_Installer_Log.txt" +logFile="${logLocation}"/$logName + +# On first run, create a file named .ChameleonLogFlag at +# the root of the target volume. Then check for this file +# on subsequent runs to know the initialisation sequence +# has been done. + +if [ ! -f "${logLocation}"/.ChameleonLogFlag ]; then + # This is the first run, so setup + # Chameleon_Installer_Log.txt file + # by writing header. + + # Also include the first message that this script + # would be called with which will be version/revision + # of Chameleon package. + + echo "Chameleon installer log - $( date ) +${verboseText} +====================================================== +" >"${logFile}" + diskutil list >>"${logFile}" + echo " +====================================================== +" >>"${logFile}" + + # Create /.ChameleonLogFlag file. + echo "Log" >"${logLocation}"/.ChameleonLogFlag +else + # Append messages to the log as passed by other scripts. + if [ "${verboseText}" = "Line Break" ]; then + echo " +====================================================== +" >>"${logFile}" + fi + + if [[ "${verboseText}" == *fdisk* ]]; then + targetDiskRaw="${verboseText#fdisk *}" + fdisk $targetDiskRaw >>"${logFile}" + echo " " >>"${logFile}" + fi + + if [ "${verboseText}" != "Line Break" ] && [[ "${verboseText}" != *fdisk* ]]; then + echo "${verboseText}" >> "${logFile}" + fi +fi + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/InstallLog.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/CheckFatType.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/CheckFatType.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/CheckFatType.sh (revision 1568) @@ -0,0 +1,78 @@ +#!/bin/bash + +echo "===============================================" +echo "CheckFatType: Do we have FAT16 or FAT32?" +echo "****************************************" + +# Looks for the following in the partition boot sector +# Byte number 19 to see if it's either 00 or 02 +# Byte number 22 to see if it's either F8 or F0 +# Byte number 25 to see if it's either 3F or 20 +# +# Exit with value 1 for FAT16, 2 for FAT32 +# Exit with value 0 if nothing is found - this shouldn't happen.? + +# Receives targetDeviceRaw: for example, /dev/rdisk0s2. +# Receives targetVolume: Volume to install to. +# Receives scriptDir: The location of the main script dir. + + +if [ "$#" -eq 3 ]; then + targetDeviceRaw="$1" + targetVolume="$2" + scriptDir="$3" + echo "DEBUG: passed argument = $targetDeviceRaw" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + + +partitionBootSector=$( dd 2>/dev/null if="$targetDeviceRaw" count=1 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) +if [ "${partitionBootSector:36:2}" == "00" ] && [ "${partitionBootSector:42:2}" == "f8" ] && [ "${partitionBootSector:48:2}" == "3f" ]; then + echo "Found a FAT32 device formatted by Windows Explorer" + echo "--------------------------------------------------" + echo "" + "$scriptDir"InstallLog.sh "${targetVolume}" "${targetDeviceRaw} is on a FAT32 volume formatted by Windows Explorer" + exit 2 +fi +if [ "${partitionBootSector:36:2}" == "02" ] && [ "${partitionBootSector:42:2}" == "f8" ] && [ "${partitionBootSector:48:2}" == "3f" ]; then + echo "Found a FAT16 device formatted by Windows Explorer" + echo "--------------------------------------------------" + echo "" + "$scriptDir"InstallLog.sh "${targetVolume}" "${targetDeviceRaw} is on a FAT16 volume formatted by Windows Explorer" + exit 1 +fi +if [ "${partitionBootSector:36:2}" == "00" ] && [ "${partitionBootSector:42:2}" == "f0" ] && [ "${partitionBootSector:48:2}" == "20" ]; then + echo "Found a FAT32 device formatted by OS X Snow Leopard Disk Utility" + echo "----------------------------------------------------------------" + echo "" + "$scriptDir"InstallLog.sh "${targetVolume}" "${targetDeviceRaw} is on a FAT32 volume formatted by OS X Snow Leopard Disk Utility" + exit 2 +fi +if [ "${partitionBootSector:36:2}" == "02" ] && [ "${partitionBootSector:42:2}" == "f0" ] && [ "${partitionBootSector:48:2}" == "20" ]; then + echo "Found a FAT16 device formatted by OS X Snow Leopard Disk Utility" + echo "----------------------------------------------------------------" + echo "" + "$scriptDir"InstallLog.sh "${targetVolume}" "${targetDeviceRaw} is on a FAT16 volume formatted by OS X Snow Leopard Disk Utility" + exit 1 +fi +if [ "${partitionBootSector:36:2}" == "00" ] && [ "${partitionBootSector:42:2}" == "f8" ] && [ "${partitionBootSector:48:2}" == "20" ]; then + echo "Found a FAT32 device formatted by OS X Lion Disk Utility" + echo "--------------------------------------------------------" + echo "" + "$scriptDir"InstallLog.sh "${targetVolume}" "${targetDeviceRaw} is on a FAT32 volume formatted by OS X Lion Disk Utility" + exit 2 +fi +if [ "${partitionBootSector:36:2}" == "02" ] && [ "${partitionBootSector:42:2}" == "f8" ] && [ "${partitionBootSector:48:2}" == "20" ]; then + echo "Found a FAT16 device formatted by OS X Lion Disk Utility" + echo "--------------------------------------------------------" + echo "" + "$scriptDir"InstallLog.sh "${targetVolume}" "${targetDeviceRaw} is on a FAT16 volume formatted by OS X Lion Disk Utility" + exit 1 +fi +echo "-----------------------------------------------" +echo "" +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/CheckFatType.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/WriteChameleonStage0.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/WriteChameleonStage0.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/WriteChameleonStage0.sh (revision 1568) @@ -0,0 +1,58 @@ +#!/bin/bash + +echo "===============================================" +echo "Write Chameleon Stage 0 Loader:" +echo "*******************************" + +# Writes Chameleon stage 0 loader. + +# Receives disksignature: 0 = Windows not found, 1 = Windows Found +# Receives stage0Loader: for example, boot0 +# Receives stage0Loaderdualboot: for example, boot0md +# Receives targetDisk: for example, /dev/disk3 +# Receives targetResources: location of fdisk440 +# Receives targetVolume: for example, /Volumes/USB +# Receives scriptDir: The location of the main script dir. + + +if [ "$#" -eq 7 ]; then + disksignature="$1" + stage0Loader="$2" + stage0Loaderdualboot="$3" + targetDisk="$4" + targetResources="$5" + targetVolume="$6" + scriptDir="$7" + echo "DEBUG: passed argument for disksignature = $disksignature" + echo "DEBUG: passed argument for stage0Loader = $stage0Loader" + echo "DEBUG: passed argument for stage0Loaderdualboot = $stage0Loaderdualboot" + echo "DEBUG: passed argument for targetDisk = $targetDisk" + echo "DEBUG: passed argument for targetResources = $targetResources" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + + +if [ ${disksignature} = "0" ]; then + # ThereÕs no Windows disk signature so we can write boot0 + + echo "Executing command: ${targetResources}fdisk440 -u -f /usr/standalone/i386/${stage0Loader} -y ${targetDisk}" + "${targetResources}"fdisk440 -u -f "${targetVolume}"/usr/standalone/i386/${stage0Loader} -y ${targetDisk} + "$scriptDir"InstallLog.sh "${targetVolume}" "Written ${stage0Loader} to ${targetDisk}." +else + # Windows is also installed on the HDD so we need to write boot0md + + echo "Executing command: ${targetResources}fdisk440 -u -f /usr/standalone/i386/${stage0Loaderdualboot} -y ${targetDisk}" + "${targetResources}"fdisk440 -u -f "${targetVolume}"/usr/standalone/i386/${stage0Loaderdualboot} -y ${targetDisk} + "$scriptDir"InstallLog.sh "${targetVolume}" "Written ${stage0Loaderdualboot} to ${targetDisk}." +fi + + +echo "-----------------------------------------------" +echo "" +echo "" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/WriteChameleonStage0.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/WriteChameleonStage1.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/WriteChameleonStage1.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/WriteChameleonStage1.sh (revision 1568) @@ -0,0 +1,67 @@ +#!/bin/bash + +echo "===============================================" +echo "Write Chameleon Stage 1 Loader:" +echo "*******************************" + +# Writes Chameleon stage 1 loader. + +# Receives espformat: 1 for HFS, 2 for MSDOS, 0 for unknown +# Receives stage1LoaderHFS: Name of file - boot1h +# Receives stage1LoaderFAT: Name of file - boot1f32 +# Receives selectedDestination: for example, /Volumes/USB +# Receives targetDeviceRaw: for example, /dev/disk3s1 +# Receives targetVolume: for example, /Volumes/USB +# Receives scriptDir: The location of the main script dir. + +if [ "$#" -eq 7 ]; then + espformat="$1" + stage1LoaderHFS="$2" + stage1LoaderFAT="$3" + selectedDestination="$4" + targetDeviceRaw="$5" + targetVolume="$6" + scriptDir="$7" + echo "DEBUG: passed argument for espformat = $espformat" + echo "DEBUG: passed argument for stage1LoaderHFS = $stage1LoaderHFS" + echo "DEBUG: passed argument for stage1LoaderFAT = $stage1LoaderFAT" + echo "DEBUG: passed argument for selectedDestination = $selectedDestination" + echo "DEBUG: passed argument for targetDeviceRaw = $targetDeviceRaw" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + +if [ ${espformat} = "1" ]; then + # the selected partition is HFS formatted + + echo "Executing command: dd if=${selectedDestination}/usr/standalone/i386/${stage1LoaderHFS} of=${targetDeviceRaw}" + dd if="${selectedDestination}"/usr/standalone/i386/${stage1LoaderHFS} of=${targetDeviceRaw} + + "$scriptDir"InstallLog.sh "${targetVolume}" "Written ${stage1LoaderHFS} to ${targetDeviceRaw}." +fi + +if [ ${espformat} = "2" ]; then + # the selected partition FAT formatted + + echo "Executing command: dd if=${targetDeviceRaw} count=1 bs=512 of=/tmp/origbs" + dd if=${targetDeviceRaw} count=1 bs=512 of=/tmp/origbs + + echo "Executing command: cp "${selectedDestination}"/usr/standalone/i386/${stage1LoaderFAT} /tmp/newbs" + cp "${selectedDestination}"/usr/standalone/i386/${stage1LoaderFAT} /tmp/newbs + + echo "Executing command: dd if=/tmp/origbs of=/tmp/newbs skip=3 seek=3 bs=1 count=87 conv=notrunc" + dd if=/tmp/origbs of=/tmp/newbs skip=3 seek=3 bs=1 count=87 conv=notrunc + + echo "Executing command: dd of=${targetDeviceRaw} count=1 bs=512 if=/tmp/newbs" + dd if=/tmp/newbs of="${targetDeviceRaw}" count=1 bs=512 + + "$scriptDir"InstallLog.sh "${targetVolume}" "Written ${stage1LoaderFAT} to ${targetDeviceRaw}." +fi + +echo "-----------------------------------------------" +echo "" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/WriteChameleonStage1.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/CheckPartitionScheme.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/CheckPartitionScheme.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/CheckPartitionScheme.sh (revision 1568) @@ -0,0 +1,71 @@ +#!/bin/bash + +echo "===============================================" +echo "Check the Partition Scheme: GPT, GPT/MBR or MBR?" +echo "************************************************" + +# Looks for the first 8 bytes of the GPTdiskGPTHeader to identify a GUID partition table. +# Byte number 450 of the GPTdiskProtectiveMBR to identify ID of 'EE' to identify a GPT partition. +# Byte numbers 466, 482 & 498 of the GPTdiskProtectiveMBR to identify further partitions. +# +# Exit with value 1 for GPT, 2 for GPT/MBR and 3 for MBR. +# Exit with value 0 if nothing is found - this shouldn't happen.? + +# Receives targetDisk: for example, /dev/disk0s2 +# Receives targetVolume: Volume to install to. +# Receives scriptDir: The location of the main script dir. + + +if [ "$#" -eq 3 ]; then + targetDisk="$1" + targetVolume="$2" + scriptDir="$3" + echo "DEBUG: passed argument = $targetDisk" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + + +partitiontable=$( dd 2>/dev/null if="$targetDisk" count=1 skip=1 | dd 2>/dev/null count=8 bs=1 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) +if [ "${partitiontable:0:16}" == "4546492050415254" ]; then + partitiontable=$( dd 2>/dev/null if="$targetDisk" count=1 | dd 2>/dev/null count=64 bs=1 skip=446 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) + + if [ "${partitiontable:8:2}" == "ee" ]; then + echo "Found System ID 'EE' to identify GPT Partition" + + if [ "${partitiontable:40:2}" == "00" ] && [ "${partitiontable:72:2}" == "00" ] && [ "${partitiontable:104:2}" == "00" ]; then + echo "Found System ID '00' for each remaining possible partition" + partitiontable="GPT" + echo "${partitiontable} found." + echo "-----------------------------------------------" + echo "" + #"$scriptDir"InstallLog.sh "${targetVolume}" "${targetDisk} is using a GPT." + exit 1 + else + partitiontable="GPT/MBR" + echo "${partitiontable} found." + echo "-----------------------------------------------" + echo "" + #"$scriptDir"InstallLog.sh "${targetVolume}" "${targetDisk} is using a GPT/MBR." + exit 2 + fi + fi +else + partitiontable="MBR" + echo "${partitiontable} found." + echo "-----------------------------------------------" + echo "" + #"$scriptDir"InstallLog.sh "${targetVolume}" "${targetDisk} is using MBR." + exit 3 +fi + +echo "No partition table found." +echo "-----------------------------------------------" +echo "" + +"$scriptDir"InstallLog.sh "${targetVolume}" "NOTE: No partition table found." + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/CheckPartitionScheme.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/WriteChameleonStage2.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/WriteChameleonStage2.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/WriteChameleonStage2.sh (revision 1568) @@ -0,0 +1,79 @@ +#!/bin/bash + +echo "===============================================" +echo "Write Chameleon Stage 2 Loader:" +echo "*******************************" + +# Writes Chameleon stage 2 loader. + +# Receives espformat: 1 for HFS, 2 for MSDOS, 0 for unknown +# Receives stage2Loader: Name of file - boot +# Receives selectedDestination: for example, /Volumes/USB +# Receives targetDevice: for example, /dev/disk3s1 +# Receives targetVolume: for example, /Volumes/USB +# Receives scriptDir: The location of the main script dir. + + +if [ "$#" -eq 6 ]; then + espformat="$1" + stage2Loader="$2" + selectedDestination="$3" + targetDevice="$4" + targetVolume="$5" + scriptDir="$6" + echo "DEBUG: passed argument for espformat = $espformat" + echo "DEBUG: passed argument for stage2Loader = $stage2Loader" + echo "DEBUG: passed argument for selectedDestination = $selectedDestination" + echo "DEBUG: passed argument for targetDevice = $targetDevice" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + +# check to see if install to EFI system partition was selected +if [ "${selectedDestination}" = "/Volumes/EFI" ]; then + echo "DEBUG: EFI install chosen" + + if [ ! -d "${selectedDestination}" ]; then + echo "Executing Command: mkdir -p ${selectedDestination}" + mkdir -p "${targetVolume}" + else + echo "DEBUG: folder /Volumes/EFI already exists" + fi + + #if the EFI system partition was selected then + # mount '/Volumes/EFI' with the correct format type + + if [ ${espformat} = 1 ]; then + + echo "Executing command: mount_hfs ${targetDevice} ${targetVolume}" + mount_hfs "${targetDevice}" "${targetVolume}" + fi + if [ ${espformat} = 2 ]; then + [ -d "${selectedDestination}" ] || mkdir -p "${selectedDestination}" + echo "Executing command: mount_msdos -u 0 -g 0 ${targetDevice} ${selectedDestination}" + mount_msdos -u 0 -g 0 "${targetDevice}" "${selectedDestination}" + fi + + echo "Executing command: cp "${targetVolume}"/usr/standalone/i386/${stage2Loader} ${selectedDestination}" + cp "${targetVolume}"/usr/standalone/i386/"${stage2Loader}" "${selectedDestination}" + "$scriptDir"InstallLog.sh "${targetVolume}" "Written boot to ${selectedDestination}." +else + echo "Executing command: cp "${targetVolume}"/usr/standalone/i386/${stage2Loader} ${targetVolume}" + cp "${targetVolume}"/usr/standalone/i386/"${stage2Loader}" "${targetVolume}" + "$scriptDir"InstallLog.sh "${targetVolume}" "Written boot to ${targetVolume}." +fi + +#ÊCheck to see if the user wants to hide the boot file +#if [ -f "${selectedDestination}"/.Chameleon/nullhideboot ]; then +# echo "Executing command: SetFile -a V ${targetVolume}/${stage2Loader}" +# "${selectedDestination}"/.Chameleon/Resources/SetFile -a V "${targetVolume}"/"${stage2Loader}" +#fi + +echo "-----------------------------------------------" +echo "" +echo "" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/WriteChameleonStage2.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/CheckDiskMicrocode.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/CheckDiskMicrocode.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/CheckDiskMicrocode.sh (revision 1568) @@ -0,0 +1,110 @@ +#!/bin/bash + +echo "===============================================" +echo "CheckDiskMicrocode: Any existing bootloaders?" +echo "*********************************************" + +# Reads the GPTdiskProtectiveMBR and searches for an existing +# Windows bootloader and also for an existing Chameleon stage 0 loader +# which might be better changed depending on whether or not a Windows +# signature is found or not. +# The script then exits with the value 0 to indicate that Chameleon stage0 +# loader can be written, or 1 to indicate not to write the stage0 loader. + +# Receives targetDisk: for example, /dev/disk2. +# Receives diskSigCheck: 0 = Windows not installed / 1 = Windows installed. +# Receives targetVolume: Volume to install to. +# Receives scriptDir: The location of the main script dir. + + +if [ "$#" -eq 4 ]; then + targetDisk="$1" + diskSigCheck="$2" + targetVolume="$3" + scriptDir="$4" + echo "DEBUG: passed argument for targetDisk = $targetDisk" + echo "DEBUG: passed argument for diskSigCheck = $diskSigCheck" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed - Exiting" + exit 9 +fi + + +# read the first 437 bytes of the MBR + +mbr437=$( dd 2>/dev/null if="$targetDisk" count=1 | dd 2>/dev/null count=1 bs=437 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) +#mbr437md5=$( dd 2>/dev/null if="$targetDisk" count=1 | dd 2>/dev/null count=1 bs=437 | md5 ) + +#echo "DEBUG: ${mbr437}" + +if [ $( echo "${mbr437}" | awk -F0 '{print NF-1}' ) = 874 ]; then + echo "The first 437 bytes of the MBR Disk Sector is blank - Updating" + #"$scriptDir"InstallLog.sh "${targetVolume}" "Target has no bootcode in the MBR disk sector." +else + # There is already something on the MBR + + # See if a Windows bootloader already exists + # Check bytes 440-443 of the GPTdiskProtectiveMBR for a Windows Disk Signature + windowsloader=$( dd 2>/dev/null if="$targetDisk" count=4 bs=1 | xxd | awk '{print $2$3}' ) + if [ "${windowsloader}" == "33c08ed0" ] ; then + echo "Found existing Windows Boot Loader so will replace with Chameleon boot0md" + "$scriptDir"InstallLog.sh "${targetVolume}" "Target has existing Windows boot loader - Will replace with boot0md" + fi + + # See if a Chameleon stage0 boot file already exists + + # Note: The checks for Boot0 and Boot0hfs assume the code stays the same. + # if the code changes then the hex values 0b807c, 0a803c and ee7505 used for matching + # need to be checked to see if they are the same or not. + + stage0type=$( dd 2>/dev/null if="$targetDisk" count=3 bs=1 skip=105 | xxd | awk '{print $2$3}' ) + if [ "${stage0type}" == "0b807c" ]; then + echo "Target has existing Chameleon stage 0 loader - Boot0hfs" + "$scriptDir"InstallLog.sh "${targetVolume}" "Target has existing Chameleon stage 0 loader - boot0hfs" + + # Script CheckDiskSignature.sh returned 0 if a Windows installation was NOT found + if [ "$diskSigCheck" == "0" ]; then + echo "Found no existing Windows installation so will replace stage 0 loader with Boot0" + "$scriptDir"InstallLog.sh "${targetVolume}" "Will replace boot0hfs with boot0 as Windows is not on target disk." + exit 0 + fi + fi + + if [ "${stage0type}" == "0a803c" ]; then + echo "Found existing Chameleon stage 0 loader - Boot0" + "$scriptDir"InstallLog.sh "${targetVolume}" "Target has existing Chameleon stage 0 loader - boot0" + + # Script CheckDiskSignature.sh returned 1 if a Windows installation was found + if [ "$diskSigCheck" = "1" ]; then + echo "Found existing Windows installation so will replace stage 0 loader with boot0md" + "$scriptDir"InstallLog.sh "${targetVolume}" "Will replace boot0 with boot0md as Windows is on target disk." + exit 0 + fi + fi + + if [ "${stage0type}" == "ee7505" ]; then + echo "Found existing Chameleon stage 0 loader - Boot0md" + echo "And will leave boot0md installed." + "$scriptDir"InstallLog.sh "${targetVolume}" "Target has existing Chameleon stage 0 loader - boot0md. Leaving as is." + exit 1 + fi + + if [ "${stage0type}" != "0b807c" ] && [ "${stage0type}" != "0a803c" ] && [ "${stage0type}" != "ee7505" ] && [ "${windowsloader}" != "33c08ed0" ] ; then + echo "Something other than Chameleon or a Windows bootloader was found" + test=$(echo "${mbr437}" | awk -F0 '{print NF-1}' ) + echo "Disk microcode found: ${test} - Preserving." + echo "diskupdate is set to false" + echo "-----------------------------------------------" + "$scriptDir"InstallLog.sh "${targetVolume}" "NOTE: Target has existing unrecognised bootcode in the MBR. Leaving as is." + echo "" + exit 1 + fi +fi + +echo "diskupdate is now set to true." +echo "-----------------------------------------------" +echo "" + +exit 0 Property changes on: branches/ErmaC/package/Scripts/Install/CheckDiskMicrocode.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/CheckProceed.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/CheckProceed.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/CheckProceed.sh (revision 1568) @@ -0,0 +1,65 @@ +#!/bin/bash + +echo "===============================================" +echo "Check Proceed: Can the script continue?" +echo "***************************************" + +# Checks the selected volume is present and the disk is partitioned. + +# Receives targetVolume: Volume to install to (will be '/Volumes/EFI' if EFI install) +# Receives targetDevice: Stores device number, for example /dev/disk2s1. +# Receives installerVolume: Volume to write the installer log to. +# Receives scriptDir: The location of the main script dir. + +if [ "$#" -eq 4 ]; then + targetVolume="$1" + targetDevice="$2" + installerVolume="$3" + scriptDir="$4" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for targetDevice = $targetDevice" + echo "DEBUG: passed argument for installerVolume = $installerVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + +if [ -z "$targetVolume" ]; then + echo "*** Cannot find the volume. Exiting." + "$scriptDir"InstallLog.sh "${installerVolume}" "FAIL: Cannot file the volume: $targetVolume." + exit 1 +else + echo "Confirming target volume exists" +fi + +if [ "$targetDevice" = "$targetDevice#*disk*s" ]; then + echo "*** ERROR Volume does not use slices. Exiting." + "$scriptDir"InstallLog.sh "${installerVolume}" "FAIL: $targetVolume doesn't use slices." + exit 1 +else + echo "Confirming target device uses slices" +fi + +# Add check for installing to a 'small' HFS device like a +# 1GB USB flash drive which won't have an EFI System Partition. + +if [ "$targetVolume" = "/Volumes/EFI" ]; then + # Take target device and check slice 1 matches partition named "EFI" + stripped=$( echo ${targetDevice#/dev/} ) + if [ ! $(echo ${stripped#*disk*s}) = 1 ]; then + stripped=$( echo ${stripped%s*})"s1" + fi + if [ ! $( diskutil list | grep ${stripped} | awk {'print $2'} ) = "EFI" ]; then + echo "*** The selected volume doesn't have an EFI System Partition. Exiting." + "$scriptDir"InstallLog.sh "${installerVolume}" "FAIL: Selected disk does not have an EFI System Partition." + exit 1 + fi +fi + +echo "-----------------------------------------------" +echo "" + +#"$scriptDir"InstallLog.sh "${installerVolume}" "CheckProceed: PASS" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/CheckProceed.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/SetActivePartition.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/SetActivePartition.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/SetActivePartition.sh (revision 1568) @@ -0,0 +1,69 @@ +#!/bin/bash + +echo "===============================================" +echo "Set Active Partition ONLY if Windows is not installed" +echo "*****************************************************" + +# Sets partition active if Windows is not installed. + +# Receives efiformat: code is 1 for HFS, 2 for MSDOS, 0 for unknown +# Receives diskSigCheck: code is 1 for a Windows install, 0 for no Windows install +# Receives targetDiskRaw: for example, /dev/rdisk1 +# Receives targetSlice: for example, 1 +# Receives targetVolume: Volume to install to. +# Receives scriptDir: The location of the main script dir. + +if [ "$#" -eq 6 ]; then + efiformat="$1" + diskSigCheck="$2" + targetDiskRaw="$3" + targetSlice="$4" + targetVolume="$5" + scriptDir="$6" + + echo "DEBUG: passed argument for efiformat = $efiformat" + echo "DEBUG: passed argument for diskSigCheck = $diskSigCheck" + echo "DEBUG: passed argument for targetDiskRaw = $targetDiskRaw" + echo "DEBUG: passed argument for targetSlice = $targetSlice" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + +# Append fdisk output to the installer log +"$scriptDir"InstallLog.sh "${targetVolume}" "fdisk ${targetDiskRaw}" + +if [ ${diskSigCheck} == "0" ]; then + #Windows is not installed so let's change the active partition" + + partitionactive=$( fdisk -d ${targetDiskRaw} | grep -n "*" | awk -F: '{print $1}') + if [ "${partitionactive}" ] && [ "${partitionactive}" = "${targetSlice}" ]; then + "$scriptDir"InstallLog.sh "${targetVolume}" "${targetDiskRaw#/dev/r}, slice "${targetSlice}" is already set active. No need to change it." + else + "$scriptDir"InstallLog.sh "${targetVolume}" "Setting ${targetVolume} partition active." + # BadAxe requires EFI partition to be flagged active. + # but it doesn't' hurt to do it for any non-windows partition. + + fdisk -e ${targetDiskRaw} <<-MAKEACTIVE + print + flag ${targetSlice} + write + y + quit + MAKEACTIVE + fi +else + # TO DO + # Add check to make sure that the active partition is actually the Windows partition + # before printing next statement. + #echo "Windows is installed so we let that remain the active partition" + "$scriptDir"InstallLog.sh "${targetVolume}" "Windows is installed so that can remain the active partition" +fi + +echo "-----------------------------------------------" +echo "" +echo "" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/SetActivePartition.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/CheckGRUBLinuxLoader.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/CheckGRUBLinuxLoader.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/CheckGRUBLinuxLoader.sh (revision 1568) @@ -0,0 +1,50 @@ +#!/bin/bash + +echo "===============================================" +echo "CheckGRUBLinuxLoader: Does GRUB or LILO exist?" +echo "**********************************************" + +# This reads the MBR of the disk in the attempt to find the +# signature for either the GRUB or Linux bootloaders. +# The script returns 1 if either is found, or 0 if none found. + +# Receives targetdisk: for example, /dev/disk2. +# Receives targetVolume: Volume to install to. +# Receives scriptDir: The location of the main script dir. + +if [ "$#" -eq 3 ]; then + targetDisk="$1" + targetVolume="$2" + scriptDir="$3" + echo "DEBUG: passed argument for targetDisk = $targetDisk" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + +diskmicrocodetype[1]="GRUB,47525542" +diskmicrocodetype[2]="LILO,4c494c4f" + +diskmicrocode=$( dd 2>/dev/null if="$targetDisk" count=1 | dd 2>/dev/null count=1 bs=437 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) +#echo "${diskmicrocode}" +diskmicrocodetypecounter=0 + +while [ ${diskmicrocodetypecounter} -lt ${#diskmicrocodetype[@]} ]; do + diskmicrocodetypecounter=$(( ${diskmicrocodetypecounter} + 1 )) + diskmicrocodetypeid=${diskmicrocodetype[${diskmicrocodetypecounter}]#*,} + if [ ! "${diskmicrocode}" = "${diskmicrocode/${diskmicrocodetypeid}/}" ]; then + echo "${diskmicrocodetype[${diskmicrocodetypecounter}]%,*} found." + "$scriptDir"InstallLog.sh "${targetVolume}" "FAIL: Found an exisitng GRUB/LILO bootloader in the MBR." + exit 1 + else + echo "Didn't find a match for ${diskmicrocodetype[${diskmicrocodetypecounter}]%,*}" + fi +done +echo "-----------------------------------------------" +echo "" + +#"$scriptDir"InstallLog.sh "${targetVolume}" "GRUB/LILO: PASS" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/CheckGRUBLinuxLoader.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/UnMountEFIvolumes.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/UnMountEFIvolumes.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/UnMountEFIvolumes.sh (revision 1568) @@ -0,0 +1,47 @@ +#!/bin/bash + +echo "===============================================" +echo "Unmount all volumes named EFI" +echo "*****************************" + +# loop through and un-mount ALL mounted 'EFI' system partitions - Thanks kizwan + +# Receives scriptDir: The location of the main script dir. +# Receives targetVolumeTemp: Stores original target if EFI install selected. + +if [ "$#" -eq 2 ]; then + targetVolumeTemp="$1" + scriptDir="$2" + echo "DEBUG: passed argument for targetVolumeTemp = $targetVolumeTemp" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed" + exit 9 +fi + + +attempts=1 +while [ "$( df | grep EFI )" ] && [ "${attempts}" -lt 5 ]; do + echo "Unmounting $( df | grep EFI | awk '{print $1}' )" + umount -f $( df | grep EFI | awk '{print $1}' ) + attempts=$(( ${attempts} + 1 )) +done +if [ ${attempts} = 5 ]; then + echo "failed to unmount 'EFI' System Partition." + echo "-----------------------------------------------" + "$scriptDir"InstallLog.sh "${targetVolumeTemp}" "Failed to unmount 'EFI' System Partition." + echo "" + echo "" + echo "" + exit 1 +fi + +echo "-----------------------------------------------" +echo "" +echo "" +echo "" + +exit 0 + + + Property changes on: branches/ErmaC/package/Scripts/Install/UnMountEFIvolumes.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Install/CheckWindowsDiskSignature.sh =================================================================== --- branches/ErmaC/package/Scripts/Install/CheckWindowsDiskSignature.sh (revision 0) +++ branches/ErmaC/package/Scripts/Install/CheckWindowsDiskSignature.sh (revision 1568) @@ -0,0 +1,46 @@ +#!/bin/bash + +echo "===============================================" +echo "CheckWindowsDiskSignature: Is Windows installed?" +echo "************************************************" + +# Checks the disk sector for a 4-byte Windows disk signature +# if one is found then it exits with 1, otherwise it exits with 0 + +# Receives targetdisk: for example, /dev/disk0 +# Receives targetVolume: Volume to install to. +# Receives scriptDir: The location of the main script dir. + +if [ "$#" -eq 3 ]; then + targetDisk="$1" + targetVolume="$2" + scriptDir="$3" + echo "DEBUG: passed argument for targetDisk = $targetDisk" + echo "DEBUG: passed argument for targetVolume = $targetVolume" + echo "DEBUG: passed argument for scriptDir = $scriptDir" +else + echo "Error - wrong number of values passed - Exiting" + exit 9 +fi + +disksignature=$( dd 2>/dev/null if="$targetDisk" count=1 | dd 2>/dev/null count=4 bs=1 skip=440 | perl -ne '@a=split"";for(@a){printf"%02x",ord}' ) + +#echo "${disksignature}" + +if [ "${disksignature}" = "00000000" ]; then + echo "No Windows installation detected." + echo "-----------------------------------------------" + echo "" + exit 0 +else + echo "Detected an existing Windows installation" + echo "-----------------------------------------------" + echo "" + "$scriptDir"InstallLog.sh "${targetVolume}" "Detected a Windows installation on this volume." + exit 1 +fi + +echo "-----------------------------------------------" +echo "" + +exit 0 \ No newline at end of file Property changes on: branches/ErmaC/package/Scripts/Install/CheckWindowsDiskSignature.sh ___________________________________________________________________ Added: svn:executable + * Index: branches/ErmaC/package/Scripts/Resolutions/1024x768x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1024x768x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1024x768x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1024x600x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1024x600x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1024x600x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1920x1200x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1920x1200x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1920x1200x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1280x768x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1280x768x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1280x768x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1600x900x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1600x900x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1600x900x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1280x1024x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1280x1024x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1280x1024x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1440x900x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1440x900x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1440x900x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1280x800x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1280x800x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1280x800x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1680x1050x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1680x1050x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1680x1050x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1920x1080x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1920x1080x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1920x1080x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Resolutions/1280x960x32/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Resolutions/1280x960x32/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Resolutions/1280x960x32/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: branches/ErmaC/package/Scripts/Keymaps/postinstall =================================================================== --- branches/ErmaC/package/Scripts/Keymaps/postinstall (revision 1567) +++ branches/ErmaC/package/Scripts/Keymaps/postinstall (revision 1568) @@ -6,8 +6,13 @@ import shutil vol = str(sys.argv[3]) -boot = "/Extra/org.chameleon.Boot.plist" +extrafolder = vol + "/tmpcham/Extra" +if not os.path.exists(extrafolder): + os.makedirs(extrafolder) + +boot = "/tmpcham/Extra/org.chameleon.Boot.plist" plist = vol + boot + if not os.path.exists(plist): shutil.copy('/Library/Preferences/SystemConfiguration/com.apple.Boot.plist', plist) Index: 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=================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: branches/ErmaC/package/Resources/de.lproj/Localizable.strings =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: branches/ErmaC/package/Resources/bg.lproj/Localizable.strings =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: branches/ErmaC/package/buildpkg.sh =================================================================== --- branches/ErmaC/package/buildpkg.sh (revision 1567) +++ branches/ErmaC/package/buildpkg.sh (revision 1568) @@ -70,9 +70,8 @@ ditto --noextattr --noqtn ${1%/*}/i386/boot1hp ${1}/Core/Root/usr/standalone/i386 ditto --noextattr --noqtn ${1%/*}/i386/cdboot ${1}/Core/Root/usr/standalone/i386 ditto --noextattr --noqtn ${1%/*}/i386/chain0 ${1}/Core/Root/usr/standalone/i386 -# fixperms "${1}/Core/Root/" - ditto --noextattr --noqtn ${1%/*}/i386/fdisk440 ${1}/Core/Root/usr/sbin - ditto --noextattr --noqtn ${1%/*}/i386/bdmesg ${1}/Core/Root/usr/sbin + ditto --noextattr --noqtn ${1%/*}/i386/fdisk440 ${1}/Core/Root/usr/local/bin + ditto --noextattr --noqtn ${1%/*}/i386/bdmesg ${1}/Core/Root/usr/local/bin local coresize=$( du -hkc "${1}/Core/Root" | tail -n1 | awk {'print $1'} ) echo " [BUILD] i386 " buildpackage "${1}/Core" "/" "0" "start_visible=\"false\" start_selected=\"true\"" >/dev/null 2>&1 @@ -84,20 +83,24 @@ # build standard package mkdir -p ${1}/Standard/Root - mkdir -p ${1}/Standard/Scripts/Tools + mkdir -p ${1}/Standard/Scripts/Resources cp -f ${pkgroot}/Scripts/Standard/* ${1}/Standard/Scripts - ditto --arch i386 `which SetFile` ${1}/Standard/Scripts/Tools/SetFile - ditto --noextattr --noqtn ${1%/*}/i386/fdisk440 ${1}/Standard/Scripts/Tools + cp -f ${pkgroot}/Scripts/Install/* ${1}/Standard/Scripts + ditto --arch i386 `which SetFile` ${1}/Standard/Scripts/Resources/SetFile + ditto --noextattr --noqtn ${1%/*/*}/revision ${1}/Standard/Scripts/Resources/revision + ditto --noextattr --noqtn ${1%/*/*}/version ${1}/Standard/Scripts/Resources/version echo " [BUILD] Standard " buildpackage "${1}/Standard" "/" "${coresize}" "start_enabled=\"true\" start_selected=\"upgrade_allowed()\" selected=\"exclusive(choices['EFI']) && exclusive(choices['noboot'])\"" >/dev/null 2>&1 # End build standard package # build efi package mkdir -p ${1}/EFI/Root - mkdir -p ${1}/EFI/Scripts/Tools + mkdir -p ${1}/EFI/Scripts/Resources cp -f ${pkgroot}/Scripts/EFI/* ${1}/EFI/Scripts - ditto --arch i386 `which SetFile` ${1}/EFI/Scripts/Tools/SetFile - ditto --noextattr --noqtn ${1%/*}/i386/fdisk440 ${1}/Standard/Scripts/Tools + cp -f ${pkgroot}/Scripts/Install/* ${1}/EFI/Scripts + ditto --arch i386 `which SetFile` ${1}/EFI/Scripts/Resources/SetFile + ditto --noextattr --noqtn ${1%/*/*}/revision ${1}/EFI/Scripts/Resources/revision + ditto --noextattr --noqtn ${1%/*/*}/version ${1}/EFI/Scripts/Resources/version echo " [BUILD] EFI " buildpackage "${1}/EFI" "/" "${coresize}" "start_visible=\"systemHasGPT()\" start_selected=\"false\" selected=\"exclusive(choices['Standard']) && exclusive(choices['noboot'])\"" >/dev/null 2>&1 # End build efi package @@ -129,6 +132,55 @@ ((xmlindent++)) packagesidentity="org.chameleon.modules" # - + if [ -e ${1%/*}/i386/modules/klibc.dylib ]; then + { + mkdir -p ${1}/klibc/Root + ditto --noextattr --noqtn ${1%/*}/i386/modules/klibc.dylib ${1}/klibc/Root + echo " [BUILD] klibc " + buildpackage "${1}/klibc" "/tmpcham/Extra/modules" "" "start_selected=\"true\"" >/dev/null 2>&1 #blackosx = add tmpcham to path + } + fi +# - + if [ -e ${1%/*}/i386/modules/uClibcxx.dylib ]; then + { + mkdir -p ${1}/uClibc/Root + ditto --noextattr --noqtn ${1%/*}/i386/modules/uClibcxx.dylib ${1}/uClibc/Root + ditto --noextattr --noqtn ${1%/*}/i386/modules/klibc.dylib ${1}/uClibc/Root + echo " [BUILD] uClibc++ " + buildpackage "${1}/uClibc" "/tmpcham/Extra/modules" "" "start_selected=\"true\"" >/dev/null 2>&1 #blackosx = add tmpcham to path + } + fi +# - + if [ -e ${1%/*}/i386/modules/Resolution.dylib ]; then + { + mkdir -p ${1}/AutoReso/Root + ditto --noextattr --noqtn ${1%/*}/i386/modules/Resolution.dylib ${1}/AutoReso/Root + echo " [BUILD] Resolution " + buildpackage "${1}/AutoReso" "/tmpcham/Extra/modules" "" "start_selected=\"false\"" >/dev/null 2>&1 #blackosx = add tmpcham to path + } + fi +# - + if [ -e ${1%/*}/i386/modules/Keylayout.dylib ]; then + { + mkdir -p ${1}/Keylayout/Root/tmpcham/Extra/{modules,Keymaps} #blackosx = add tmpcham to path + mkdir -p ${1}/Keylayout/Root/usr/bin + layout_src_dir="${1%/sym/*}/i386/modules/Keylayout/layouts/layouts-src" + if [ -d "$layout_src_dir" ];then + # Create a tar.gz from layout sources + (cd "$layout_src_dir"; \ + tar czf "${1}/Keylayout/Root/tmpcham/Extra/Keymaps/layouts-src.tar.gz" README *.slt) #blackosx = add tmpcham to path + fi + # Adding module + ditto --noextattr --noqtn ${1%/*}/i386/modules/Keylayout.dylib ${1}/Keylayout/Root/tmpcham/Extra/modules #blackosx = add tmpcham to path + # Adding Keymaps + ditto --noextattr --noqtn ${1%/sym/*}/Keymaps ${1}/Keylayout/Root/tmpcham/Extra/Keymaps #blackosx = add tmpcham to path + # Adding tools + ditto --noextattr --noqtn ${1%/*}/i386/cham-mklayout ${1}/Keylayout/Root/usr/bin + echo " [BUILD] Keylayout " + buildpackage "${1}/Keylayout" "/" "" "start_selected=\"true\"" >/dev/null 2>&1 + } + fi +# - if [ -e ${1%/*}/i386/modules/AMDGraphicsEnabler.dylib ]; then { mkdir -p ${1}/AMDGraphicsEnabler/Root @@ -156,15 +208,6 @@ } fi # - - if [ -e ${1%/*}/i386/modules/klibc.dylib ]; then - { - mkdir -p ${1}/klibc/Root - ditto --noextattr --noqtn ${1%/*}/i386/modules/klibc.dylib ${1}/klibc/Root - echo " [BUILD] klibc " - buildpackage "${1}/klibc" "/Extra/modules" "" "start_selected=\"true\"" >/dev/null 2>&1 - } - fi -# - if [ -e ${1%/*}/i386/modules/NVIDIAGraphicsEnabler.dylib ]; then { mkdir -p ${1}/NVIDIAGraphicsEnabler/Root @@ -173,46 +216,6 @@ buildpackage "${1}/NVIDIAGraphicsEnabler" "/Extra/modules" "" "start_selected=\"false\"" >/dev/null 2>&1 } fi -# - - if [ -e ${1%/*}/i386/modules/Resolution.dylib ]; then - { - mkdir -p ${1}/AutoReso/Root - ditto --noextattr --noqtn ${1%/*}/i386/modules/Resolution.dylib ${1}/AutoReso/Root - echo " [BUILD] Resolution " - buildpackage "${1}/AutoReso" "/Extra/modules" "" "start_selected=\"false\"" >/dev/null 2>&1 - } - fi -# - - if [ -e ${1%/*}/i386/modules/Keylayout.dylib ]; then - { - mkdir -p ${1}/Keylayout/Root/Extra/{modules,Keymaps} - mkdir -p ${1}/Keylayout/Root/usr/bin - layout_src_dir="${1%/sym/*}/i386/modules/Keylayout/layouts/layouts-src" - if [ -d "$layout_src_dir" ];then - # Create a tar.gz from layout sources - (cd "$layout_src_dir"; \ - tar czf "${1}/Keylayout/Root/Extra/Keymaps/layouts-src.tar.gz" README *.slt) - fi - # Adding module - ditto --noextattr --noqtn ${1%/*}/i386/modules/Keylayout.dylib ${1}/Keylayout/Root/Extra/modules - # Adding Keymaps - ditto --noextattr --noqtn ${1%/sym/*}/Keymaps ${1}/Keylayout/Root/Extra/Keymaps - # Adding tools - ditto --noextattr --noqtn ${1%/*}/i386/cham-mklayout ${1}/Keylayout/Root/usr/bin - echo " [BUILD] Keylayout " - buildpackage "${1}/Keylayout" "/" "" "start_selected=\"true\"" >/dev/null 2>&1 - } - fi -# - - if [ -e ${1%/*}/i386/modules/uClibcxx.dylib ]; then - { - mkdir -p ${1}/uClibc/Root - ditto --noextattr --noqtn ${1%/*}/i386/modules/uClibcxx.dylib ${1}/uClibc/Root - ditto --noextattr --noqtn ${1%/*}/i386/modules/klibc.dylib ${1}/uClibc/Root - echo " [BUILD] uClibc++ " - buildpackage "${1}/uClibc" "/Extra/modules" "" "start_selected=\"true\"" >/dev/null 2>&1 - } - fi ((xmlindent--)) outline[$((outlinecount++))]="${indent[$xmlindent]}\t" } @@ -300,7 +303,8 @@ sed "s/@@KEYMAP@@/${keymaps[$i]}/g" "${pkgroot}/Scripts/Keymaps/postinstall" > "${1}/${keymaps[$i]}/Scripts/postinstall" && \ chmod +rx "${1}/${keymaps[$i]}/Scripts/postinstall" echo " [BUILD] ${keymaps[$i]} " - buildpackage "${1}/${keymaps[$i]}" "/tmpcham" "" "start_selected=\"false\"" >/dev/null 2>&1 +#blackosx = why use install location /tmpcham for this ? changing to root + buildpackage "${1}/${keymaps[$i]}" "/" "" "start_selected=\"false\"" >/dev/null 2>&1 done ((xmlindent--)) outline[$((outlinecount++))]="${indent[$xmlindent]}\t" @@ -319,7 +323,8 @@ mkdir -p "${1}/${resolutions[$i]##*/}/Scripts/" ditto --noextattr --noqtn "${resolutions[$i]}/postinstall" "${1}/${resolutions[$i]##*/}/Scripts/postinstall" echo " [BUILD] ${resolutions[$i]##*/} " - buildpackage "${1}/${resolutions[$i]##*/}" "/tmpcham" "" "start_selected=\"false\"" >/dev/null 2>&1 +#blackosx = why use install location /tmpcham for this ? changing to root + buildpackage "${1}/${resolutions[$i]##*/}" "/" "" "start_selected=\"false\"" >/dev/null 2>&1 done ((xmlindent--)) @@ -357,22 +362,19 @@ outline[$((outlinecount++))]="${indent[$xmlindent]}\t" choices[$((choicescount++))]="\n\n" ((xmlindent++)) + + # Using themes section from Azi's/package branch. packagesidentity="org.chameleon.themes" - artwork="${1%/*}" - themes=($( find "${artwork%/*}/artwork/themes" -type d -depth 1 -not -name '.svn' )) + artwork="${1%/sym/package}/artwork/themes" + themes=($( find "${artwork}" -type d -depth 1 -not -name '.svn' )) for (( i = 0 ; i < ${#themes[@]} ; i++ )) do theme=$( echo ${themes[$i]##*/} | awk 'BEGIN{OFS=FS=""}{$1=toupper($1);print}' ) - mkdir -p "${1}/${themes[$i]##*/}/Root/" - rsync -r --exclude=.svn "${themes[$i]}/" "${1}/${themes[$i]##*/}/Root/${theme}" - # #### Comment out thx meklort - # ditto --noextattr --noqtn "${themes[$i]}" "${1}/${themes[$i]##*/}/Root/${theme}" - # #### - find "${1}/${themes[$i]##*/}" -name '.DS_Store' -or -name '.svn' -exec rm -R {} \+ - find "${1}/${themes[$i]##*/}" -type f -exec chmod 644 {} \+ - echo " [BUILD] ${themes[$i]##*/} " - buildpackage "${1}/${theme}" "/Extra/Themes" "" "start_selected=\"false\"" >/dev/null 2>&1 - rm -R -f "${1}/${i##*/}" + mkdir -p "${1}/${theme}/Root/" + rsync -r --exclude=.svn "${themes[$i]}/" "${1}/${theme}/Root/${theme}" + echo " [BUILD] ${theme}" +#blackosx = maybe use install location /tmpcham for this, then move at the end depending on standard to efi install? going to try it + buildpackage "${1}/${theme}" "/tmpcham/Extra/Themes" "" "start_selected=\"false\"" >/dev/null 2>&1 done ((xmlindent--)) @@ -458,6 +460,7 @@ fi header+="" + echo -e "${header}" >> ~/Desktop/header echo -e "${header}" > "${1}/Temp/PackageInfo" pushd "${1}/Root" >/dev/null find . -print | cpio -o -z -H cpio > "../Temp/Payload"