Index: branches/Chimera/version =================================================================== --- branches/Chimera/version (revision 1908) +++ branches/Chimera/version (revision 1909) @@ -1 +1 @@ -1.8.0 +1.9.0 Index: branches/Chimera/i386/libsaio/acpi_patcher.c =================================================================== --- branches/Chimera/i386/libsaio/acpi_patcher.c (revision 1908) +++ branches/Chimera/i386/libsaio/acpi_patcher.c (revision 1909) @@ -563,8 +563,9 @@ case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 - case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) - case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 + case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) + case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) { maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)... minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff; Index: branches/Chimera/i386/libsaio/nvidia.c =================================================================== --- branches/Chimera/i386/libsaio/nvidia.c (revision 1908) +++ branches/Chimera/i386/libsaio/nvidia.c (revision 1909) @@ -74,14 +74,15 @@ extern uint32_t devices_number; -const char *nvidia_compatible_0[] = { "@0,compatible", "NVDA,NVMac" }; -const char *nvidia_compatible_1[] = { "@1,compatible", "NVDA,NVMac" }; -const char *nvidia_device_type_0[] = { "@0,device_type", "display" }; -const char *nvidia_device_type_1[] = { "@1,device_type", "display" }; -const char *nvidia_device_type[] = { "device_type", "NVDA,Parent" }; -const char *nvidia_name_0[] = { "@0,name", "NVDA,Display-A" }; -const char *nvidia_name_1[] = { "@1,name", "NVDA,Display-B" }; -const char *nvidia_slot_name[] = { "AAPL,slot-name", "Slot-1" }; +const char *nvidia_compatible_0[] = { "@0,compatible", "NVDA,NVMac" }; +const char *nvidia_compatible_1[] = { "@1,compatible", "NVDA,NVMac" }; +const char *nvidia_device_type_0[] = { "@0,device_type", "display" }; +const char *nvidia_device_type_1[] = { "@1,device_type", "display" }; +const char *nvidia_device_type[] = { "device_type", "NVDA,Parent" }; +const char *nvidia_device_type_child[] = { "device_type", "NVDA,Child" }; +const char *nvidia_name_0[] = { "@0,name", "NVDA,Display-A" }; +const char *nvidia_name_1[] = { "@1,name", "NVDA,Display-B" }; +const char *nvidia_slot_name[] = { "AAPL,slot-name", "Slot-1" }; static uint8_t default_NVCAP[]= { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, @@ -604,7 +605,8 @@ // 0890 - 089F // 08A0 - 08AF { 0x10DE08A0, "GeForce 320M" }, - { 0x10DE08A4, "GeForce 320M" }, + { 0x10DE08A4, "GeForce 320M" }, + { 0x10DE08A5, "GeForce 320M" }, // 08B0 - 08BF // 08C0 - 08CF // 08D0 - 08DF @@ -760,7 +762,9 @@ { 0x10DE0DE0, "GeForce GT 440" }, { 0x10DE0DE1, "GeForce GT 430" }, { 0x10DE0DE2, "GeForce GT 420" }, + { 0x10DE0DE4, "GeForce GT 520" }, { 0x10DE0DE5, "GeForce GT 530" }, + { 0x10DE0DE9, "GeForce GT 630M" }, { 0x10DE0DEB, "GeForce GT 555M" }, { 0x10DE0DEC, "GeForce GT 525M" }, { 0x10DE0DED, "GeForce GT 520M" }, @@ -776,6 +780,7 @@ { 0x10DE0DF7, "GeForce GT 520M" }, { 0x10DE0DF8, "Quadro 600" }, { 0x10DE0DFA, "Quadro 1000M" }, + { 0x10DE0DFC, "NVS 5200M" }, { 0x10DE0DFE, "GF108 ES" }, { 0x10DE0DFF, "GF108 INT" }, // 0E00 - 0E0F @@ -827,11 +832,14 @@ // 1020 - 102F // 1030 - 103F // 1040 - 104F - { 0x10DE1040, "GeForce GT 520" }, + { 0x10DE1040, "GeForce GT 520" }, + { 0x10DE1042, "GeForce 510" }, + { 0x10DE1049, "GeForce GT 620" }, // 1050 - 105F { 0x10DE1050, "GeForce GT 520M" }, { 0x10DE1051, "GeForce GT 520MX" }, { 0x10DE1054, "GeForce GT 410M" }, + { 0x10DE1055, "GeForce 410M" }, { 0x10DE1056, "Quadro NVS 4200M" }, { 0x10DE1057, "Quadro NVS 4200M" }, // 1060 - 106F @@ -850,6 +858,8 @@ { 0x10DE108B, "GeForce GTX 590" }, // 1090 - 109F { 0x10DE1091, "Tesla M2090" }, + { 0x10DE1094, "Tesla M2075" }, + { 0x10DE1096, "Tesla C2075" }, { 0x10DE1098, "D13U" }, { 0x10DE109A, "Quadro 5010M" }, { 0x10DE109B, "Quadro 7000" }, @@ -861,14 +871,52 @@ { 0x10DE10C5, "GeForce 405" }, // 10D0 - 10DF { 0x10DE10D8, "NVS 300" }, - // 1200 - + // 10E0 - 10EF + // 10F0 - 10FF + // 1100 - 110F + // 1110 - 111F + // 1120 - 112F + // 1130 - 113F + // 1140 - 114F + // 1150 - 115F + // 1160 - 116F + // 1170 - 117F + // 1180 - 118F + { 0x10DE1180, "GeForce GTX 680" }, + // 1190 - 119F + // 11A0 - 11AF + // 11B0 - 11BF + // 11C0 - 11CF + // 11D0 - 11DF + // 11E0 - 11EF + // 11F0 - 11FF + // 1200 - 120F { 0x10DE1200, "GeForce GTX 560 Ti" }, { 0x10DE1201, "GeForce GTX 560" }, + { 0x10DE1203, "GeForce GTX 460 SE v2" }, + // 1210 - 121F + { 0x10DE1210, "GeForce GTX 570M" }, + { 0x10DE1211, "GeForce GTX 580M" }, + // 1220 - 122F + // 1230 - 123F + // 1240 - 124F { 0x10DE1241, "GeForce GT 545" }, { 0x10DE1243, "GeForce GT 545" }, { 0x10DE1244, "GeForce GTX 550 Ti" }, { 0x10DE1245, "GeForce GTS 450" }, + { 0x10DE1247, "GeForce GT 555M" }, + // 1250 - 125F { 0x10DE1251, "GeForce GTX 560M" }, + // 1260 - 126F + // 1270 - 127F + // 1280 - 128F + // 1290 - 129F + // 12A0 - 12AF + // 12B0 - 12BF + // 12C0 - 12CF + // 12D0 - 12DF + // 12E0 - 12EF + // 12F0 - 12FF }; static uint16_t swap16(uint16_t x) @@ -1190,8 +1238,16 @@ return 0; if (!DP_ADD_TEMP_VAL(device, nvidia_name_1)) return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_device_type)) - return 0; + if (devices_number == 1) + { + if (!DP_ADD_TEMP_VAL(device, nvidia_device_type)) + return 0; + } + else + { + if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child)) + return 0; + } // Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0! // len = sprintf(tmp, "Slot-%x", devices_number); @@ -1250,7 +1306,7 @@ vram_size *= REG32(NVC0_MEM_CTRLR_COUNT); } - // Workaround for 9600M GT, GT 420/430/440 & GT 525M + // Workaround for 9600M GT, GT 420/430/440 & GT 525M/540M switch (nvda_dev->device_id) { case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT @@ -1258,6 +1314,7 @@ case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430 case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420 case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M + case 0x0DF4: vram_size = 1024*1024*1024; break; // GT 540M case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M default: break; } @@ -1403,7 +1460,10 @@ /* FIXME: for primary graphics card only */ boot_display = 1; - devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4); + if (devices_number == 1) + { + devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4); + } if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) { uint8_t built_in = 0x01; Index: branches/Chimera/i386/libsaio/cpu.c =================================================================== --- branches/Chimera/i386/libsaio/cpu.c (revision 1908) +++ branches/Chimera/i386/libsaio/cpu.c (revision 1909) @@ -200,8 +200,8 @@ if (p->CPU.Vendor == CPUID_VENDOR_INTEL && p->CPU.Family == 0x06 && - p->CPU.Model >= CPUID_MODEL_NEHALEM && - p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU + p->CPU.Model >= CPU_MODEL_NEHALEM && + p->CPU.Model != CPU_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU ) { msr = rdmsr64(MSR_CORE_THREAD_COUNT); // Undocumented MSR in Nehalem and newer CPUs @@ -288,15 +288,16 @@ int intelCPU = p->CPU.Model; if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) { /* Nehalem CPU model */ - if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || - p->CPU.Model == CPU_MODEL_FIELDS || - p->CPU.Model == CPU_MODEL_DALES || - p->CPU.Model == CPU_MODEL_DALES_32NM || - p->CPU.Model == CPU_MODEL_WESTMERE || - p->CPU.Model == CPU_MODEL_NEHALEM_EX || + if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || + p->CPU.Model == CPU_MODEL_FIELDS || + p->CPU.Model == CPU_MODEL_DALES || + p->CPU.Model == CPU_MODEL_DALES_32NM || + p->CPU.Model == CPU_MODEL_WESTMERE || + p->CPU.Model == CPU_MODEL_NEHALEM_EX || p->CPU.Model == CPU_MODEL_WESTMERE_EX || - p->CPU.Model == CPU_MODEL_SANDY || - p->CPU.Model == CPU_MODEL_SANDY_XEON)) { + p->CPU.Model == CPU_MODEL_SANDYBRIDGE || + p->CPU.Model == CPU_MODEL_JAKETOWN || + p->CPU.Model == CPU_MODEL_IVYBRIDGE )) { msr = rdmsr64(MSR_PLATFORM_INFO); DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0)); bus_ratio_max = bitfield(msr, 14, 8); Index: branches/Chimera/i386/libsaio/platform.h =================================================================== --- branches/Chimera/i386/libsaio/platform.h (revision 1908) +++ branches/Chimera/i386/libsaio/platform.h (revision 1909) @@ -38,11 +38,12 @@ #define CPU_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper Forest #define CPU_MODEL_DALES 0x1F // Havendale, Auburndale #define CPU_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale -#define CPU_MODEL_SANDY 0x2A // Sandy Bridge +#define CPU_MODEL_SANDYBRIDGE 0x2A // Sandy Bridge #define CPU_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS -#define CPU_MODEL_SANDY_XEON 0x2D // Sandy Bridge Xeon +#define CPU_MODEL_JAKETOWN 0x2D // Sandy Bridge-E, Sandy Bridge-EP #define CPU_MODEL_NEHALEM_EX 0x2E // Beckton #define CPU_MODEL_WESTMERE_EX 0x2F +#define CPU_MODEL_IVYBRIDGE 0x3A // Ivy Bridge /* CPU Features */ #define CPU_FEATURE_MMX 0x00000001 // MMX Instruction Set Index: branches/Chimera/i386/libsaio/cpu.h =================================================================== --- branches/Chimera/i386/libsaio/cpu.h (revision 1908) +++ branches/Chimera/i386/libsaio/cpu.h (revision 1909) @@ -40,21 +40,7 @@ #define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ #define CALIBRATE_LATCH ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) -// CPUID Values -#define CPUID_MODEL_YONAH 14 // Intel Mobile Core Solo, Duo -#define CPUID_MODEL_MEROM 15 // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx -#define CPUID_MODEL_PENRYN 23 // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx -#define CPUID_MODEL_NEHALEM 26 // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) -#define CPUID_MODEL_ATOM 28 // Intel Atom (45nm) -#define CPUID_MODEL_FIELDS 30 // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) -#define CPUID_MODEL_DALES 31 // Havendale, Auburndale -#define CPUID_MODEL_DALES_32NM 37 // Intel Core i3, i5 LGA1156 (32nm) -#define CPUID_MODEL_SANDY 42 // Intel Core i3, i5, i7 LGA1155 (32nm) -#define CPUID_MODEL_WESTMERE 44 // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core -#define CPUID_MODEL_NEHALEM_EX 46 // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x -#define CPUID_MODEL_WESTMERE_EX 47 // Intel Xeon E7 - static inline uint64_t rdtsc64(void) { uint64_t ret; Index: branches/Chimera/i386/libsaio/smbios.c =================================================================== --- branches/Chimera/i386/libsaio/smbios.c (revision 1908) +++ branches/Chimera/i386/libsaio/smbios.c (revision 1909) @@ -333,8 +333,8 @@ defaultSystemInfo.family = kDefaultiMacFamily; break; - case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) - case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 + case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) defaultBIOSInfo.version = kDefaultiMacSandyBIOSVersion; defaultSystemInfo.productName = kDefaultiMacSandy; defaultSystemInfo.family = kDefaultiMacFamily; @@ -348,6 +348,7 @@ case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) defaultBIOSInfo.version = kDefaultMacProWestmereBIOSVersion; defaultBIOSInfo.releaseDate = kDefaulMacProWestmereBIOSReleaseDate; defaultSystemInfo.productName = kDefaultMacProWestmere; Index: branches/Chimera/i386/libsaio/smbios_getters.c =================================================================== --- branches/Chimera/i386/libsaio/smbios_getters.c (revision 1908) +++ branches/Chimera/i386/libsaio/smbios_getters.c (revision 1909) @@ -155,8 +155,8 @@ value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) - case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 + case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) value->word = 0x0901; // Core i3 @@ -169,6 +169,7 @@ case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) value->word = 0x0501; // Core i7 return true; }