Index: trunk/i386/libsaio/smbios_getters.h =================================================================== --- trunk/i386/libsaio/smbios_getters.h (revision 2268) +++ trunk/i386/libsaio/smbios_getters.h (revision 2269) @@ -12,7 +12,8 @@ #define NOT_AVAILABLE "N/A" -typedef enum { +typedef enum +{ kSMBString, kSMBByte, kSMBWord, @@ -20,7 +21,8 @@ // kSMBQWord } SMBValueType; -typedef union { +typedef union +{ const char *string; uint8_t byte; uint16_t word; Index: trunk/i386/libsaio/acpi_patcher.c =================================================================== --- trunk/i386/libsaio/acpi_patcher.c (revision 2268) +++ trunk/i386/libsaio/acpi_patcher.c (revision 2269) @@ -1,5 +1,6 @@ /* * Copyright 2008 mackerintel + * 2010 mojodojo, 2012 slice */ #include "libsaio.h" @@ -29,8 +30,10 @@ boolean_t tableSign(char *table, const char *sgn) { int i; - for (i=0; i<4; i++) { - if ((table[i] &~0x20) != (sgn[i] &~0x20)) { + for (i=0; i<4; i++) + { + if ((table[i] &~0x20) != (sgn[i] &~0x20)) + { return false; } } @@ -40,53 +43,56 @@ /* Gets the ACPI 1.0 RSDP address */ static struct acpi_2_rsdp* getAddressOfAcpiTable() { - /* TODO: Before searching the BIOS space we are supposed to search the first 1K of the EBDA */ - - void *acpi_addr = (void*)ACPI_RANGE_START; - for(; acpi_addr <= (void*)ACPI_RANGE_END; acpi_addr += 16) - { - if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE) - { - uint8_t csum = checksum8(acpi_addr, 20); - if(csum == 0) - { - // Only return the table if it is a true version 1.0 table (Revision 0) - if(((struct acpi_2_rsdp*)acpi_addr)->Revision == 0) - return acpi_addr; - } - } - } - return NULL; + /* TODO: Before searching the BIOS space we are supposed to search the first 1K of the EBDA */ + + void *acpi_addr = (void*)ACPI_RANGE_START; + for(; acpi_addr <= (void*)ACPI_RANGE_END; acpi_addr += 16) + { + if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE) + { + uint8_t csum = checksum8(acpi_addr, 20); + if(csum == 0) + { + // Only return the table if it is a true version 1.0 table (Revision 0) + if(((struct acpi_2_rsdp*)acpi_addr)->Revision == 0) + return acpi_addr; + } + } + } + return NULL; } /* Gets the ACPI 2.0 RSDP address */ static struct acpi_2_rsdp* getAddressOfAcpi20Table() { - /* TODO: Before searching the BIOS space we are supposed to search the first 1K of the EBDA */ - - void *acpi_addr = (void*)ACPI_RANGE_START; - for(; acpi_addr <= (void*)ACPI_RANGE_END; acpi_addr += 16) - { - if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE) - { - uint8_t csum = checksum8(acpi_addr, 20); - - /* Only assume this is a 2.0 or better table if the revision is greater than 0 - * NOTE: ACPI 3.0 spec only seems to say that 1.0 tables have revision 1 - * and that the current revision is 2.. I am going to assume that rev > 0 is 2.0. - */ - - if(csum == 0 && (((struct acpi_2_rsdp*)acpi_addr)->Revision > 0)) - { - uint8_t csum2 = checksum8(acpi_addr, sizeof(struct acpi_2_rsdp)); - if(csum2 == 0) - return acpi_addr; - } - } - } - return NULL; + /* TODO: Before searching the BIOS space we are supposed to search the first 1K of the EBDA */ + + void *acpi_addr = (void*)ACPI_RANGE_START; + for(; acpi_addr <= (void*)ACPI_RANGE_END; acpi_addr += 16) + { + if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE) + { + uint8_t csum = checksum8(acpi_addr, 20); + + /* Only assume this is a 2.0 or better table if the revision is greater than 0 + * NOTE: ACPI 3.0 spec only seems to say that 1.0 tables have revision 1 + * and that the current revision is 2.. I am going to assume that rev > 0 is 2.0. + */ + + if(csum == 0 && (((struct acpi_2_rsdp*)acpi_addr)->Revision > 0)) + { + uint8_t csum2 = checksum8(acpi_addr, sizeof(struct acpi_2_rsdp)); + if(csum2 == 0) + { + return acpi_addr; + } + } + } + } + return NULL; } -/** The folowing ACPI Table search algo. should be reused anywhere needed:*/ + +/* The folowing ACPI Table search algo. should be reused anywhere needed:*/ int search_and_get_acpi_fd(const char * filename, const char ** outDirspec) { int fd = 0; @@ -110,7 +116,7 @@ if (fd < 0) { // NOT FOUND: - verbose("ACPI table not found: %s\n", filename); + verbose("ACPI Table not found: %s\n", filename); *dirSpec = '\0'; } @@ -194,7 +200,10 @@ verbose("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]); - if (++acpi_cpu_count == 32) return; + if (++acpi_cpu_count == 32) + { + return; + } } } } @@ -507,7 +516,7 @@ // Sanity check if (maximum.CID < minimum.CID) { - DBG("Insane FID values!"); + DBG("P-States: Insane FID values!"); p_states_count = 0; } else @@ -576,13 +585,13 @@ //case CPU_MODEL_HASWELL_H: // case CPU_MODEL_HASWELL_MB: // case CPU_MODEL_HASWELL_ULT: // - case CPU_MODEL_HASWELL_ULX: // + case CPU_MODEL_CRYSTALWELL: // { if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_JAKETOWN) || (Platform.CPU.Model == CPU_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_HASWELL) || (Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_MB) || - (Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_HASWELL_ULX)) + (Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_CRYSTALWELL)) { maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff; } @@ -696,20 +705,29 @@ const char * value; // Restart Fix - if (Platform.CPU.Vendor == 0x756E6547) { /* Intel */ + if (Platform.CPU.Vendor == 0x756E6547) + { /* Intel */ fix_restart = true; fix_restart_ps2 = false; if ( getBoolForKey(kPS2RestartFix, &fix_restart_ps2, &bootInfo->chameleonConfig) && fix_restart_ps2) + { fix_restart = true; + } else + { getBoolForKey(kRestartFix, &fix_restart, &bootInfo->chameleonConfig); - - } else { + } + } + else + { verbose ("Not an Intel platform: Restart Fix not applied !!!\n"); fix_restart = false; } - if (fix_restart) fadt_rev2_needed = true; + if (fix_restart) + { + fadt_rev2_needed = true; + } // Allocate new fadt table if (fadt->Length < 0x84 && fadt_rev2_needed) @@ -730,13 +748,19 @@ if (Platform.Type > 6) { if(fadt_mod->PM_Profile<=6) + { Platform.Type = fadt_mod->PM_Profile; // get the fadt if correct + } else + { Platform.Type = 1; /* Set a fixed value (Desktop) */ + } verbose("Error: system-type must be 0..6. Defaulting to %d !\n", Platform.Type); } else + { Platform.Type = (unsigned char) strtoul(value, NULL, 10); + } } // Set PM_Profile from System-type if only user wanted this value to be forced if (fadt_mod->PM_Profile != Platform.Type) @@ -760,7 +784,8 @@ // Patch FADT to fix restart if (fix_restart) { - if (fix_restart_ps2) { + if (fix_restart_ps2) + { fadt_mod->Flags|= 0x400; fadt_mod->Reset_SpaceID = 0x01; // System I/O fadt_mod->Reset_BitWidth = 0x08; // 1 byte @@ -770,7 +795,8 @@ fadt_mod->Reset_Value = 0xfe; // Value to write to reset the system msglog("FADT: PS2 Restart Fix applied!\n"); } - else { + else + { fadt_mod->Flags|= 0x400; fadt_mod->Reset_SpaceID = 0x01; // System I/O fadt_mod->Reset_BitWidth = 0x08; // 1 byte @@ -790,7 +816,9 @@ fadt_mod->DSDT=(uint32_t)new_dsdt; if ((uint32_t)(&(fadt_mod->X_DSDT))-(uint32_t)fadt_mod+8<=fadt_mod->Length) + { fadt_mod->X_DSDT=(uint32_t)new_dsdt; + } DBG("New @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT); @@ -807,8 +835,8 @@ /* Setup ACPI without replacing DSDT. */ int setupAcpiNoMod() { - // addConfigurationTable(&gEfiAcpiTableGuid, getAddressOfAcpiTable(), "ACPI"); - // addConfigurationTable(&gEfiAcpi20TableGuid, getAddressOfAcpi20Table(), "ACPI_20"); +// addConfigurationTable(&gEfiAcpiTableGuid, getAddressOfAcpiTable(), "ACPI"); +// addConfigurationTable(&gEfiAcpi20TableGuid, getAddressOfAcpi20Table(), "ACPI_20"); /* XXX aserebln why uint32 cast if pointer is uint64 ? */ acpi10_p = (uint32_t)getAddressOfAcpiTable(); acpi20_p = (uint32_t)getAddressOfAcpi20Table(); @@ -831,7 +859,7 @@ // always reset cpu count to 0 when injecting new acpi acpi_cpu_count = 0; - // Try using the file specified with the DSDT option + /* Try using the file specified with the DSDT option */ if (getValueForKey(kDSDT, &filename, &len, &bootInfo->chameleonConfig)) { sprintf(dirSpec, filename); @@ -854,7 +882,7 @@ int ssdt_count=0; // SSDT Options - bool drop_ssdt=false, generate_pstates=false, generate_cstates=false; + bool drop_ssdt=false, generate_pstates=false, generate_cstates=false; getBoolForKey(kDropSSDT, &drop_ssdt, &bootInfo->chameleonConfig); getBoolForKey(kGeneratePStates, &generate_pstates, &bootInfo->chameleonConfig); @@ -895,9 +923,13 @@ { DBG("No ACPI version %d found. Ignoring\n", version+1); if (version) + { addConfigurationTable(&gEfiAcpi20TableGuid, NULL, "ACPI_20"); + } else + { addConfigurationTable(&gEfiAcpiTableGuid, NULL, "ACPI"); + } continue; } rsdplength=version?rsdp->Length:20; @@ -932,7 +964,9 @@ { char *table=(char *)(rsdt_entries[i]); if (!table) + { continue; + } DBG("TABLE %c%c%c%c,",table[0],table[1],table[2],table[3]); @@ -948,10 +982,13 @@ DBG("DSDT found\n"); if(new_dsdt) + { rsdt_entries[i-dropoffset]=(uint32_t)new_dsdt; + } continue; } + if (tableSign(table, "FACP")) { struct acpi_2_fadt *fadt, *fadt_mod; @@ -1021,7 +1058,7 @@ else { rsdp_mod->RsdtAddress=0; - printf("RSDT not found or RSDT incorrect\n"); + printf("RSDT not found or incorrect\n"); } if (version) @@ -1050,8 +1087,9 @@ { char *table=(char *)((uint32_t)(xsdt_entries[i])); if (!table) + { continue; - + } xsdt_entries[i-dropoffset]=xsdt_entries[i]; if (drop_ssdt && tableSign(table, "SSDT")) @@ -1064,7 +1102,9 @@ DBG("DSDT found\n"); if (new_dsdt) + { xsdt_entries[i-dropoffset]=(uint32_t)new_dsdt; + } DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]); @@ -1146,7 +1186,7 @@ */ rsdp_mod->XsdtAddress=0xffffffffffffffffLL; - verbose("XSDT not found or XSDT incorrect\n"); + verbose("XSDT not found or incorrect\n"); } } Index: trunk/i386/libsaio/acpi_patcher.h =================================================================== --- trunk/i386/libsaio/acpi_patcher.h (revision 2268) +++ trunk/i386/libsaio/acpi_patcher.h (revision 2269) @@ -1,5 +1,6 @@ /* * Copyright 2008 mackerintel + * 2010 mojodojo */ #ifndef __LIBSAIO_ACPI_PATCHER_H Index: trunk/i386/libsaio/gma.c =================================================================== --- trunk/i386/libsaio/gma.c (revision 2268) +++ trunk/i386/libsaio/gma.c (revision 2269) @@ -620,6 +620,9 @@ case GMA_HASWELL_D_GT2: // 0412 case GMA_HASWELL_M_GT2: // 0416 case GMA_HASWELL_S_GT2: // 041a + case GMA_HASWELL_E_GT1: // 040e + case GMA_HASWELL_E_GT2: // 041e + case GMA_HASWELL_E_GT3: // 042e case GMA_HASWELL_D_GT3: // 0422 case GMA_HASWELL_M_GT3: // 0426 case GMA_HASWELL_S_GT3: // 042a Index: trunk/i386/libsaio/nvidia.c =================================================================== --- trunk/i386/libsaio/nvidia.c (revision 2268) +++ trunk/i386/libsaio/nvidia.c (revision 2269) @@ -1010,6 +1010,7 @@ { 0x10DE0FC1, "GeForce GT 640" }, { 0x10DE0FC2, "GeForce GT 630" }, { 0x10DE0FC6, "GeForce GTX 650" }, + { 0x10DE0FCD, "GeForce GT 755M" }, // 0FD0 - 0FDF { 0x10DE0FD1, "GeForce GT 650M" }, { 0x10DE0FD2, "GeForce GT 640M" }, @@ -1039,6 +1040,7 @@ { 0x10DE1003, "GeForce GTX Titan LE" }, { 0x10DE1004, "GeForce GTX 780" }, { 0x10DE1005, "GeForce GTX Titan" }, + { 0x10DE100A, "GeForce GTX 780 Ti" }, // 1010 - 101F { 0x10DE101F, "Tesla K20" }, // 1020 - 102F @@ -1129,8 +1131,12 @@ { 0x10DE1183, "GeForce GTX 660 Ti" }, { 0x10DE1184, "GeForce GTX 770" }, { 0x10DE1185, "GeForce GTX 660" }, + { 0x10DE1187, "GeForce GTX 760" }, { 0x10DE1188, "GeForce GTX 690" }, { 0x10DE1189, "GeForce GTX 670" }, +// { 0x10DE118A, "GRID K520" }, +// { 0x10DE118B, "GRID K200" }, + { 0x10DE118E, "GeForce GTX 760 (192-bit)" }, { 0x10DE118F, "Tesla K10" }, // 1190 - 119F { 0x10DE119F, "GeForce GTX 780M" }, @@ -1201,6 +1207,7 @@ { 0x10DE1293, "GeForce GT 730M" }, { 0x10DE1294, "GeForce GT 740M" }, { 0x10DE1295, "GeForce GT 710M" }, + { 0x10DE1298, "GeForce GT 720M" }, // 12A0 - 12AF //{ 0x10DE12A0, "GeForce GT ???" }, { 0x10DE12AF, "GK208-INT" }, @@ -1389,6 +1396,8 @@ { 0x10DE1180, 0x38422682, "EVGA GTX 680 SC" }, { 0x10DE1180, 0x38422683, "EVGA GTX 680 SC" }, + { 0x10DE1187, 0x14583614, "GV-N760OC-4GD" }, + { 0x10DE1189, 0x10438405, "Asus GTX 670 Direct CU II TOP" }, { 0x10DE1189, 0x15691189, "Palit GTX 670 JetStream" }, { 0x10DE1189, 0x19DA1255, "Zotac GTX 670 AMP! Edition" }, @@ -1672,8 +1681,7 @@ { for (i = 0; i < (sizeof(nvidia_card_exceptions) / sizeof(nvidia_card_exceptions[0])); i++) { - if ((nvidia_card_exceptions[i].device == device_id) && - (nvidia_card_exceptions[i].subdev == subsys_id)) + if ((nvidia_card_exceptions[i].device == device_id) && (nvidia_card_exceptions[i].subdev == subsys_id)) { return nvidia_card_exceptions[i].name; } @@ -1896,8 +1904,7 @@ // Amount of VRAM in kilobytes videoRam = mem_detect(regs, nvCardType, nvda_dev,((nvda_dev->vendor_id << 16) | nvda_dev->device_id),((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id) ); - sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, - (uint16_t)nvda_dev->device_id); + sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id); if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit) { @@ -1919,7 +1926,6 @@ else { rom = malloc(NVIDIA_ROM_SIZE); - // Otherwise read bios from card nvBiosOveride = 0; Index: trunk/i386/libsaio/cpu.c =================================================================== --- trunk/i386/libsaio/cpu.c (revision 2268) +++ trunk/i386/libsaio/cpu.c (revision 2269) @@ -51,6 +51,8 @@ ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5)) }; + //int_enabled = ml_set_interrupts_enabled(FALSE); + restart: if (attempts >= 9) // increase to up to 9 attempts. { @@ -89,6 +91,7 @@ set_PIT2(0); // reset timer 2 to be zero disable_PIT2(); // turn off PIT 2 + //ml_set_interrupts_enabled(int_enabled); return intermediate; } @@ -288,6 +291,20 @@ } #endif +/* + EAX (Intel): + 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 + +--------+----------------+--------+----+----+--------+--------+--------+ + |########|Extended family |Extmodel|####|type|familyid| model |stepping| + +--------+----------------+--------+----+----+--------+--------+--------+ + + EAX (AMD): + 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 + +--------+----------------+--------+----+----+--------+--------+--------+ + |########|Extended family |Extmodel|####|####|familyid| model |stepping| + +--------+----------------+--------+----+----+--------+--------+--------+ +*/ + p->CPU.Vendor = p->CPU.CPUID[CPUID_0][1]; p->CPU.Signature = p->CPU.CPUID[CPUID_1][0]; p->CPU.Stepping = bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); @@ -397,9 +414,9 @@ tscFrequency = measure_tsc_frequency(); /* if usual method failed */ - if ( tscFrequency < 1000 ) + if ( tscFrequency < 1000 )//TEST { - tscFrequency = timeRDTSC() * 20; + tscFrequency = timeRDTSC() * 20; } fsbFrequency = 0; cpuFrequency = 0; @@ -425,7 +442,7 @@ p->CPU.Model == CPU_MODEL_HASWELL_MB || //p->CPU.Model == CPU_MODEL_HASWELL_H || p->CPU.Model == CPU_MODEL_HASWELL_ULT || - p->CPU.Model == CPU_MODEL_HASWELL_ULX )) + p->CPU.Model == CPU_MODEL_CRYSTALWELL )) { msr = rdmsr64(MSR_PLATFORM_INFO); DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0)); @@ -510,14 +527,14 @@ p->CPU.MinRatio = min_ratio; myfsb = fsbFrequency / 1000000; - verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio); + verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); currcoef = bus_ratio_max; } else { msr = rdmsr64(MSR_IA32_PERF_STATUS); DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0)); - currcoef = bitfield(msr, 15, 8); + currcoef = bitfield(msr, 12, 8); /* Non-integer bus ratio for the max-multi*/ maxdiv = bitfield(msr, 46, 46); /* Non-integer bus ratio for the current-multi (undocumented)*/ Index: trunk/i386/libsaio/platform.h =================================================================== --- trunk/i386/libsaio/platform.h (revision 2268) +++ trunk/i386/libsaio/platform.h (revision 2269) @@ -61,7 +61,7 @@ #define CPU_MODEL_HASWELL_MB 0x3F // Haswell MB //#define CPU_MODEL_HASWELL_H 0x?? // Haswell H #define CPU_MODEL_HASWELL_ULT 0x45 // Haswell ULT -#define CPU_MODEL_HASWELL_ULX 0x46 // Haswell ULX +#define CPU_MODEL_CRYSTALWELL 0x46 // Haswell ULX /* CPU Features */ #define CPU_FEATURE_MMX 0x00000001 // MMX Instruction Set @@ -115,17 +115,18 @@ /* Size of SMBIOS UUID in bytes */ #define UUID_LEN 16 -typedef struct _RamSlotInfo_t { - uint32_t ModuleSize; // Size of Module in MB - uint32_t Frequency; // in Mhz - const char* Vendor; - const char* PartNo; - const char* SerialNo; - char* spd; // SPD Dump - bool InUse; - uint8_t Type; - uint8_t BankConnections; // table type 6, see (3.3.7) - uint8_t BankConnCnt; +typedef struct _RamSlotInfo_t +{ + uint32_t ModuleSize; // Size of Module in MB + uint32_t Frequency; // in Mhz + const char* Vendor; + const char* PartNo; + const char* SerialNo; + char* spd; // SPD Dump + bool InUse; + uint8_t Type; + uint8_t BankConnections; // table type 6, see (3.3.7) + uint8_t BankConnCnt; } RamSlotInfo_t; typedef struct _PlatformInfo_t { Index: trunk/i386/libsaio/cpu.h =================================================================== --- trunk/i386/libsaio/cpu.h (revision 2268) +++ trunk/i386/libsaio/cpu.h (revision 2269) @@ -41,7 +41,7 @@ #define CALIBRATE_LATCH ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) // CPUID Values - +/* #define CPUID_MODEL_PRESCOTT 3 // 0x03 Celeron D, Pentium 4 (90nm) #define CPUID_MODEL_NOCONA 4 // 0x04 Xeon Nocona, Irwindale (90nm) #define CPUID_MODEL_PRESLER 6 // 0x06 Pentium 4, Pentium D (65nm) @@ -73,10 +73,12 @@ #define CPUID_MODEL_HASWELL_MB 63 // 0x3F Mobile/Laptop version //#define CPUID_MODEL_HASWELL_H ?? // 0x?? #define CPUID_MODEL_HASWELL_ULT 69 // 0x45 -#define CPUID_MODEL_HASWELL_ULX 70 // 0x46 - +#define CPUID_MODEL_CRYSTALWELL 70 // 0x46 +*/ /* HASWELL-DT HASWELL-MB HASWELL-H HASWELL-ULT HASWELL ULX*/ +//BROADWELL-ROCKWELL + static inline uint64_t rdtsc64(void) { uint64_t ret; Index: trunk/i386/libsaio/smbios.c =================================================================== --- trunk/i386/libsaio/smbios.c (revision 2268) +++ trunk/i386/libsaio/smbios.c (revision 2269) @@ -571,6 +571,7 @@ { switch (Platform.CPU.Model) { + case 0x19: // Intel Core i5 650 @3.20 Ghz case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) case CPU_MODEL_DALES: case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) @@ -585,7 +586,7 @@ case CPU_MODEL_HASWELL: case CPU_MODEL_HASWELL_MB: case CPU_MODEL_HASWELL_ULT: - case CPU_MODEL_HASWELL_ULX: + case CPU_MODEL_CRYSTALWELL: break; Index: trunk/i386/libsaio/fake_efi.c =================================================================== --- trunk/i386/libsaio/fake_efi.c (revision 2268) +++ trunk/i386/libsaio/fake_efi.c (revision 2269) @@ -18,8 +18,6 @@ #include "pci.h" #include "sl.h" - - extern void setup_pci_devs(pci_dt_t *pci_dt); /* @@ -109,10 +107,14 @@ // We only do adds, not modifications and deletes like InstallConfigurationTable if (i >= MAX_CONFIGURATION_TABLE_ENTRIES) + { stop("Ran out of space for configuration tables. Increase the reserved size in the code.\n"); + } if (pGuid == NULL) + { return EFI_INVALID_PARAMETER; + } if (table != NULL) { @@ -132,7 +134,9 @@ // Assume the alias pointer is a global or static piece of data if (alias != NULL) + { DT__AddProperty(tableNode, "alias", strlen(alias)+1, (char*)alias); + } return EFI_SUCCESS; } @@ -447,11 +451,17 @@ EFI_CHAR16* dst = 0; size_t i = 0; - if (!key || !(*key) || !len || !src) return 0; + if (!key || !(*key) || !len || !src) + { + return 0; + } *len = strlen(src); dst = (EFI_CHAR16*) malloc( ((*len)+1) * 2 ); - for (; i < (*len); i++) dst[i] = src[i]; + for (; i < (*len); i++) + { + dst[i] = src[i]; + } dst[(*len)] = '\0'; *len = ((*len)+1)*2; // return the CHAR16 bufsize in cluding zero terminated CHAR16 return dst; @@ -470,8 +480,15 @@ for (i=0, isZero=1, isOnes=1; ismbiosConfig); if (boardid) + { DT__AddProperty(node, BOARDID_PROP, strlen(boardid)+1, (EFI_CHAR16*)boardid); + } } /* @@ -631,11 +671,15 @@ Node *chosenNode; chosenNode = DT__FindNode("/chosen", false); if (chosenNode == 0) + { stop("Couldn't get chosen node"); + } int bootUUIDLength = strlen(gBootUUIDString); if (bootUUIDLength) + { DT__AddProperty(chosenNode, "boot-uuid", bootUUIDLength + 1, gBootUUIDString); + } } /* @@ -644,8 +688,8 @@ static void setupSmbiosConfigFile(const char *filename) { char dirSpecSMBIOS[128]; - const char *override_pathname = NULL; - int len = 0, err = 0; + const char *override_pathname = NULL; + int len = 0, err = 0; extern void scan_mem(); // Take in account user overriding Index: trunk/i386/libsaio/smbios_getters.c =================================================================== --- trunk/i386/libsaio/smbios_getters.c (revision 2268) +++ trunk/i386/libsaio/smbios_getters.c (revision 2269) @@ -37,7 +37,7 @@ case CPU_MODEL_HASWELL: case CPU_MODEL_HASWELL_MB: case CPU_MODEL_HASWELL_ULT: - case CPU_MODEL_HASWELL_ULX: + case CPU_MODEL_CRYSTALWELL: value->word = 0; break; @@ -75,6 +75,7 @@ { switch (Platform.CPU.Model) { + case CPU_MODEL_PENTIUM_M: case CPU_MODEL_DOTHAN: // Intel Pentium M case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx @@ -82,6 +83,7 @@ case CPU_MODEL_ATOM: // Intel Atom (45nm) return false; + case 0x19: case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) case CPU_MODEL_DALES: @@ -89,12 +91,14 @@ case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPU_MODEL_SANDYBRIDGE: + case CPU_MODEL_JAKETOWN: { // thanks to dgobe for i3/i5/i7 bus speed detection int nhm_bus = 0x3F; static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F}; unsigned long did, vid; - int i; + unsigned int i; // Nehalem supports Scrubbing // First, locate the PCI bus where the MCH is located @@ -115,7 +119,10 @@ DBG("qpimult %d\n", qpimult); qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000)); // Rek: rounding decimals to match original mac profile info - if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100; + if (qpibusspeed%100 != 0) + { + qpibusspeed = ((qpibusspeed+50)/100)*100; + } DBG("qpibusspeed %d\n", qpibusspeed); value->word = qpibusspeed; return true; @@ -161,6 +168,7 @@ { switch (Platform.CPU.Model) { + case CPU_MODEL_PENTIUM_M: case CPU_MODEL_DOTHAN: // Intel Pentium M case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx @@ -169,49 +177,84 @@ return true; case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) - case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core - case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 - case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5-xxxx LGA2011 (32nm) if (strstr(Platform.CPU.BrandString, "Xeon(R)")) + { value->word = 0x0501; // Xeon - else + } + if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) + { value->word = 0x0701; // Core i7 + } return true; case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) if (strstr(Platform.CPU.BrandString, "Xeon(R)")) - value->word = 0x0501;// Xeon - else - if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) - value->word = 0x0601; // Core i5 - else - value->word = 0x0701; // Core i7 + { + value->word = 0x501;// Xeon + } + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + { + value->word = 0x601; // Core i5 + } + if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) + { + value->word = 0x701; // Core i7 + } + return true; case CPU_MODEL_DALES: if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) - value->word = 0x0601; // Core i5 + { + value->word = 0x601; // Core i5 + } else + { value->word = 0x0701; // Core i7 + } return true; case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) + case CPU_MODEL_IVYBRIDGE_XEON: case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) case CPU_MODEL_HASWELL: case CPU_MODEL_HASWELL_MB: case CPU_MODEL_HASWELL_ULT: - case CPU_MODEL_HASWELL_ULX: + case CPU_MODEL_CRYSTALWELL: + if (strstr(Platform.CPU.BrandString, "Xeon(R)")) + { + value->word = 0x0501; // Xeon + } if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) - value->word = 0x0901; // Core i3 - else - if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) - value->word = 0x0601; // Core i5 - else - value->word = 0x0701; // Core i7 + { + value->word = 0x901; // Core i3 + } + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + { + value->word = 0x601; // Core i5 + } + if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) + { + value->word = 0x0701; // Core i7 + } return true; + + case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5-xxxx LGA2011 (32nm) + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 + value->word = 0x0501; // Core i7 + return true; + + case 0x19: // Intel Core i5 650 @3.20 Ghz + value->word = 0x601; // Core i5 + return true; + default: + break; //Unsupported CPU type } } + default: + break; } } @@ -292,7 +335,7 @@ value->string = NOT_AVAILABLE; return true; } - + bool getSMBMemoryDeviceSerialNumber(returnType *value) { static int idx = -1; @@ -300,7 +343,7 @@ idx++; - DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS); + DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS); if (idx < MAX_RAM_SLOTS) { Index: trunk/i386/libsaio/saio_internal.h =================================================================== --- trunk/i386/libsaio/saio_internal.h (revision 2268) +++ trunk/i386/libsaio/saio_internal.h (revision 2269) @@ -218,7 +218,7 @@ unsigned int byteoff, unsigned int byteCount, void * buffer ); -// Base64-decode.c +/* Base64-decode.c */ char *BASE64Decode(const char* src, int in_len, int* out_len); #endif /* !__LIBSAIO_SAIO_INTERNAL_H */