Index: branches/ErmaC/Enoch/i386/libsaio/acpi_patcher.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/acpi_patcher.c (revision 2353) +++ branches/ErmaC/Enoch/i386/libsaio/acpi_patcher.c (revision 2354) @@ -574,14 +574,14 @@ case CPU_MODEL_HASWELL: // case CPU_MODEL_IVYBRIDGE_XEON: // //case CPU_MODEL_HASWELL_H: // - case CPU_MODEL_HASWELL_MB: // + case CPU_MODEL_HASWELL_SVR: // case CPU_MODEL_HASWELL_ULT: // case CPU_MODEL_CRYSTALWELL: // { if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_JAKETOWN) || (Platform.CPU.Model == CPU_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_HASWELL) || - (Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_MB) || + (Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_SVR) || (Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_CRYSTALWELL)) { maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff; Index: branches/ErmaC/Enoch/i386/libsaio/aml_generator.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/aml_generator.c (revision 2353) +++ branches/ErmaC/Enoch/i386/libsaio/aml_generator.c (revision 2354) @@ -371,7 +371,7 @@ if (node) { unsigned int offset = 0; - unsigned int len = strlen(StringBuf)+1; + unsigned int len = strlen(StringBuf); node->Type = AML_CHUNK_BUFFER; node->Length = (uint8_t)(len + 3); node->Buffer = malloc (node->Length); Index: branches/ErmaC/Enoch/i386/libsaio/cpu.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/cpu.c (revision 2353) +++ branches/ErmaC/Enoch/i386/libsaio/cpu.c (revision 2354) @@ -417,7 +417,7 @@ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON || p->CPU.Model == CPU_MODEL_IVYBRIDGE || p->CPU.Model == CPU_MODEL_HASWELL || - p->CPU.Model == CPU_MODEL_HASWELL_MB || + p->CPU.Model == CPU_MODEL_HASWELL_SVR || //p->CPU.Model == CPU_MODEL_HASWELL_H || p->CPU.Model == CPU_MODEL_HASWELL_ULT || p->CPU.Model == CPU_MODEL_CRYSTALWELL )) @@ -442,7 +442,7 @@ /* Clear bit 16 (evidently the presence bit) */ wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL)); msr = rdmsr64(MSR_FLEX_RATIO); - DBG("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0)); + verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0)); } else { if (bus_ratio_max > flex_ratio) { bus_ratio_max = flex_ratio; @@ -626,7 +626,7 @@ DBG("Family: 0x%x\n", p->CPU.Family); // Family ex: 6 (06h) DBG("ExtFamily: 0x%x\n", p->CPU.ExtFamily); DBG("Signature: %x\n", p->CPU.Signature); // CPUID signature - /*switch (p->CPU.CpuType) { + /*switch (p->CPU.Type) { case PT_OEM: DBG("Processor type: Intel Original OEM Processor\n"); break; Index: branches/ErmaC/Enoch/i386/libsaio/platform.h =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/platform.h (revision 2353) +++ branches/ErmaC/Enoch/i386/libsaio/platform.h (revision 2354) @@ -58,7 +58,7 @@ #define CPU_MODEL_IVYBRIDGE 0x3A // Ivy Bridge #define CPU_MODEL_HASWELL 0x3C // Haswell DT #define CPU_MODEL_IVYBRIDGE_XEON 0x3E // Ivy Bridge Xeon -#define CPU_MODEL_HASWELL_MB 0x3F // Haswell MB +#define CPU_MODEL_HASWELL_SVR 0x3F // Haswell MB //#define CPU_MODEL_HASWELL_H 0x?? // Haswell H #define CPU_MODEL_HASWELL_ULT 0x45 // Haswell ULT #define CPU_MODEL_CRYSTALWELL 0x46 // Haswell ULX @@ -137,7 +137,7 @@ uint32_t Vendor; // Vendor uint32_t Signature; // Processor Signature uint32_t Stepping; // Stepping - //uint32_t Type; // Type + //uint16_t Type; // Type uint32_t Model; // Model uint32_t ExtModel; // Extended Model uint32_t Family; // Family Index: branches/ErmaC/Enoch/i386/libsaio/cpu.h =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/cpu.h (revision 2353) +++ branches/ErmaC/Enoch/i386/libsaio/cpu.h (revision 2354) @@ -16,6 +16,112 @@ #define CPU_STRING_UNKNOWN "Unknown CPU Type" +/* + * The CPUID_FEATURE_XXX values define 64-bit values + * returned in %ecx:%edx to a CPUID request with %eax of 1: + */ +#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */ +#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */ +#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */ +#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */ +#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */ +#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */ +#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */ +#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */ +#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */ +#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */ +#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */ +#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */ +#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */ +#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */ +#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */ +#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */ +#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */ +#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */ +#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */ +#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */ +#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */ +#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */ +#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */ +#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */ +#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */ +#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */ +#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */ +#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */ +#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */ + +#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */ +#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */ +#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */ +#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */ +#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */ +#define CPUID_FEATURE_VMX _HBit(5) /* VMX */ +#define CPUID_FEATURE_SMX _HBit(6) /* SMX */ +#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */ +#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */ +#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */ +#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */ +#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */ +#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */ +#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */ +#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */ +#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */ + +#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */ +#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */ +#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */ +#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */ +#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */ +#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */ +#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */ +#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */ +#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */ +#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */ +#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */ +#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */ +#define CPUID_FEATURE_F16C _HBit(29) /* Float16 convert instructions */ +#define CPUID_FEATURE_RDRAND _HBit(30) /* RDRAND instruction */ +#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */ + +/* + * Leaf 7, subleaf 0 additional features. + * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}: + */ +#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */ +#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1) /* TSC thread offset */ +#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3) /* Bit Manipulation Instrs, set 1 */ +#define CPUID_LEAF7_FEATURE_HLE _Bit(4) /* Hardware Lock Elision*/ +#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5) /* AVX2 Instructions */ +#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */ +#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8) /* Bit Manipulation Instrs, set 2 */ +#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9) /* ENhanced Fast STRinG copy */ +#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10) /* INVPCID intruction, TDB */ +#define CPUID_LEAF7_FEATURE_RTM _Bit(11) /* TBD */ + +/* + * The CPUID_EXTFEATURE_XXX values define 64-bit values + * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: + */ +#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */ +#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */ + +#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1GB pages */ +#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */ +#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */ + +#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAFH/SAHF instructions */ + +/* + * The CPUID_EXTFEATURE_XXX values define 64-bit values + * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: + */ +#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */ + +#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */ + +#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */ +#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */ + //-- processor type -> p_type: #define PT_OEM 0x00 // Intel Original OEM Processor; #define PT_OD 0x01 // Intel Over Drive Processor; @@ -24,31 +130,32 @@ /* Known MSR registers */ #define MSR_IA32_PLATFORM_ID 0x0017 -#define MSR_CORE_THREAD_COUNT 0x0035 /* limited use - not for Penryn or older */ +#define MSR_CORE_THREAD_COUNT 0x0035 /* limited use - not for Penryn or older */ #define IA32_TSC_ADJUST 0x003B -#define MSR_IA32_BIOS_SIGN_ID 0x008B /* microcode version */ -#define MSR_FSB_FREQ 0x00CD /* limited use - not for i7 */ -#define MSR_PLATFORM_INFO 0x00CE /* limited use - MinRatio for i7 but Max for Yonah */ +#define MSR_IA32_BIOS_SIGN_ID 0x008B /* microcode version */ +#define MSR_FSB_FREQ 0x00CD /* limited use - not for i7 */ +#define MSR_PLATFORM_INFO 0x00CE /* limited use - MinRatio for i7 but Max for Yonah */ /* turbo for penryn */ -#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2 /* sandy and ivy */ -#define IA32_MPERF 0x00E7 /* TSC in C0 only */ -#define IA32_APERF 0x00E8 /* actual clocks in C0 */ -#define MSR_IA32_EXT_CONFIG 0x00EE /* limited use - not for i7 */ -#define MSR_FLEX_RATIO 0x0194 /* limited use - not for Penryn or older */ - //see no value on most CPUs +#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2 /* sandy and ivy */ +#define MSR_PMG_IO_CAPTURE_BASE 0x00E4 +#define IA32_MPERF 0x00E7 /* TSC in C0 only */ +#define IA32_APERF 0x00E8 /* actual clocks in C0 */ +#define MSR_IA32_EXT_CONFIG 0x00EE /* limited use - not for i7 */ +#define MSR_FLEX_RATIO 0x0194 /* limited use - not for Penryn or older */ + //see no value on most CPUs #define MSR_IA32_PERF_STATUS 0x0198 #define MSR_IA32_PERF_CONTROL 0x0199 #define MSR_IA32_CLOCK_MODULATION 0x019A #define MSR_THERMAL_STATUS 0x019C #define MSR_IA32_MISC_ENABLE 0x01A0 -#define MSR_THERMAL_TARGET 0x01A2 /* limited use - not for Penryn or older */ -#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */ +#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older */ +#define MSR_MISC_PWR_MGMT 0x01AA +#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */ #define IA32_ENERGY_PERF_BIAS 0x01B0 -//MSR 000001B0 0000-0000-0000-0005 -//MSR 000001B1 0000-0000-8838-0000 +#define MSR_PACKAGE_THERM_STATUS 0x01B1 #define IA32_PLATFORM_DCA_CAP 0x01F8 -//MSR 000001FC 0000-0000-0004-005F +#define MSR_POWER_CTL 0x01FC // MSR 000001FC 0000-0000-0004-005F // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's. #define MSR_RAPL_POWER_UNIT 0x606 /* R/O */ @@ -62,38 +169,10 @@ //MSR 0000060C 0000-0000-0000-8854 #define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */ -#define MSR_PKG_RAPL_POWER_LIMIT 0x610 -//MSR 00000610 0000-A580-0000-8960 -#define MSR_PKG_ENERGY_STATUS 0x611 -//MSR 00000611 0000-0000-3212-A857 -#define MSR_PKG_POWER_INFO 0x614 -//MSR 00000614 0000-0000-01E0-02F8 -// Sandy Bridge IA (Core) domain MSR's. -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP0_ENERGY_STATUS 0x639 -#define MSR_PP0_POLICY 0x63A -#define MSR_PP0_PERF_STATUS 0x63B +#define MSR_PKG_RAPL_POWER_LIMIT 0x610 //MSR 00000610 0000-A580-0000-8960 +#define MSR_PKG_ENERGY_STATUS 0x611 //MSR 00000611 0000-0000-3212-A857 +#define MSR_PKG_POWER_INFO 0x614 //MSR 00000614 0000-0000-01E0-02F8 -// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown). -#define MSR_PP1_POWER_LIMIT 0x640 -#define MSR_PP1_ENERGY_STATUS 0x641 -//MSR 00000641 0000-0000-0000-0000 -#define MSR_PP1_POLICY 0x642 - -// JakeTown only Memory MSR's. -#define MSR_PKG_PERF_STATUS 0x613 -#define MSR_DRAM_POWER_LIMIT 0x618 -#define MSR_DRAM_ENERGY_STATUS 0x619 -#define MSR_DRAM_PERF_STATUS 0x61B -#define MSR_DRAM_POWER_INFO 0x61C - -//IVY_BRIDGE -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64A -#define MSR_CONFIG_TDP_CONTROL 0x64B /* write once to lock */ -#define MSR_TURBO_ACTIVATION_RATIO 0x64C - //AMD #define K8_FIDVID_STATUS 0xC0010042 #define K10_COFVID_LIMIT 0xC0010061 @@ -112,45 +191,6 @@ #define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ #define CALIBRATE_LATCH ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) -// CPUID Values Reference -/* -#define CPUID_MODEL_PRESCOTT 3 // 0x03 Celeron D, Pentium 4 (90nm) -#define CPUID_MODEL_NOCONA 4 // 0x04 Xeon Nocona, Irwindale (90nm) -#define CPUID_MODEL_PRESLER 6 // 0x06 Pentium 4, Pentium D (65nm) -#define CPUID_MODEL_PENTIUM_M 9 // 0x09 -#define CPUID_MODEL_DOTHAN 13 // 0x0D Dothan -#define CPUID_MODEL_YONAH 14 // 0x0E Intel Mobile Core Solo, Duo -#define CPUID_MODEL_MEROM 15 // 0x0F Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx -#define CPUID_MODEL_CONROE 15 // 0x0F -#define CPUID_MODEL_CELERON 22 // 0x16 -#define CPUID_MODEL_PENRYN 23 // 0x17 Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx -#define CPUID_MODEL_WOLFDALE 23 // 0x17 -#define CPUID_MODEL_NEHALEM 26 // 0x1A Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) -#define CPUID_MODEL_ATOM 28 // 0x1C Intel Atom (45nm) Pineview, Silverthorne -#define CPUID_MODEL_XEON_MP 29 // 0x1D MP 7400 -#define CPUID_MODEL_FIELDS 30 // 0x1E Intel Core i5, i7, Xeon X34xx LGA1156 (45nm),(Clarksfiled, Lynnfield, Jasper Forest) -#define CPUID_MODEL_DALES 31 // 0x1F Havendale, Auburndale -#define CPUID_MODEL_DALES_32NM 37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale) -#define CPUID_MODEL_ATOM_SAN 38 // 0x26 -#define CPUID_MODEL_LINCROFT 39 // 0x27 Intel Atom (45nm) Z6xx (single core) -#define CPUID_MODEL_SANDYBRIDGE 42 // 0x2A Intel Core i3, i5, i7 LGA1155 (32nm) -#define CPUID_MODEL_WESTMERE 44 // 0x2C Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core -#define CPUID_MODEL_JAKETOWN 45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP -#define CPUID_MODEL_NEHALEM_EX 46 // 0x2E Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x -#define CPUID_MODEL_WESTMERE_EX 47 // 0x2F Intel Xeon E7 -#define CPUID_MODEL_ATOM_2000 54 // 0x36 Intel Atom (32nm) Cedarview -#define CPUID_MODEL_IVYBRIDGE 58 // 0x3A Intel Core i5, i7 LGA1155 (22nm) -#define CPUID_MODEL_HASWELL 60 // 0x3C Desktop version -#define CPUID_MODEL_IVYBRIDGE_XEON 62 // 0x3E -#define CPUID_MODEL_HASWELL_MB 63 // 0x3F Mobile/Laptop version -//#define CPUID_MODEL_HASWELL_H ?? // 0x?? -#define CPUID_MODEL_HASWELL_ULT 69 // 0x45 -#define CPUID_MODEL_CRYSTALWELL 70 // 0x46 -*/ -/* HASWELL-DT HASWELL-MB HASWELL-H HASWELL-ULT HASWELL ULX*/ - -//BROADWELL-ROCKWELL - static inline uint64_t rdtsc64(void) { uint64_t ret; Index: branches/ErmaC/Enoch/i386/libsaio/fake_efi.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/fake_efi.c (revision 2353) +++ branches/ErmaC/Enoch/i386/libsaio/fake_efi.c (revision 2354) @@ -443,7 +443,8 @@ static const char SYSTEM_TYPE_PROP[] = "system-type"; static const char MODEL_PROP[] = "Model"; static const char BOARDID_PROP[] = "board-id"; - +static const char DEV_PATH_SUP[] = "DevicePathsSupported"; +static uint32_t DevPathSup = 1; /* * Get an smbios option string option to convert to EFI_CHAR16 string */ @@ -567,12 +568,9 @@ // too so we might as well create it so we have a pointer for it too. node = DT__AddChild(node, "efi"); - if (archCpuType == CPU_TYPE_I386) - { + if (archCpuType == CPU_TYPE_I386) { DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_32_PROP_VALUE), (char*)FIRMWARE_ABI_32_PROP_VALUE); - } - else - { + } else { DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_64_PROP_VALUE), (char*)FIRMWARE_ABI_64_PROP_VALUE); } @@ -585,17 +583,14 @@ // is set up. That is, name and table properties Node *runtimeServicesNode = DT__AddChild(node, "runtime-services"); - if (archCpuType == CPU_TYPE_I386) - { + if (archCpuType == CPU_TYPE_I386) { // The value of the table property is the 32-bit physical address for the RuntimeServices table. // Since the EFI system table already has a pointer to it, we simply use the address of that pointer // for the pointer to the property data. Warning.. DT finalization calls free on that but we're not // the only thing to use a non-malloc'd pointer for something in the DT DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST32->RuntimeServices); - } - else - { + } else { DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST64->RuntimeServices); } @@ -610,22 +605,21 @@ // the value in the fsbFrequency global and not an malloc'd pointer // because the DT_AddProperty function does not copy its args. - if (Platform.CPU.FSBFrequency != 0) - { + if (Platform.CPU.FSBFrequency != 0) { DT__AddProperty(efiPlatformNode, FSB_Frequency_prop, sizeof(uint64_t), &Platform.CPU.FSBFrequency); } // Export TSC and CPU frequencies for use by the kernel or KEXTs - if (Platform.CPU.TSCFrequency != 0) - { + if (Platform.CPU.TSCFrequency != 0) { DT__AddProperty(efiPlatformNode, TSC_Frequency_prop, sizeof(uint64_t), &Platform.CPU.TSCFrequency); } - if (Platform.CPU.CPUFrequency != 0) - { + if (Platform.CPU.CPUFrequency != 0) { DT__AddProperty(efiPlatformNode, CPU_Frequency_prop, sizeof(uint64_t), &Platform.CPU.CPUFrequency); } + DT__AddProperty(efiPlatformNode,DEV_PATH_SUP, sizeof(uint32_t), &DevPathSup); + // Bungo /* Export system-id. Can be disabled with SystemId=No in com.apple.Boot.plist if ((ret=getSystemID())) { @@ -636,14 +630,12 @@ DT__AddProperty(efiPlatformNode, SYSTEM_ID_PROP, UUID_LEN, (EFI_UINT32 *)Platform.UUID); // Export SystemSerialNumber if present - if ((ret16=getSmbiosChar16("SMserial", &len))) - { + if ((ret16=getSmbiosChar16("SMserial", &len))) { DT__AddProperty(efiPlatformNode, SYSTEM_SERIAL_PROP, len, ret16); } // Export Model if present - if ((ret16=getSmbiosChar16("SMproductname", &len))) - { + if ((ret16=getSmbiosChar16("SMproductname", &len))) { DT__AddProperty(efiPlatformNode, MODEL_PROP, len, ret16); }