Index: branches/ErmaC/Enoch/i386/libsaio/cpu.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/cpu.c (revision 2469) +++ branches/ErmaC/Enoch/i386/libsaio/cpu.c (revision 2470) @@ -308,8 +308,8 @@ if (p->CPU.Vendor == CPUID_VENDOR_INTEL && p->CPU.Family == 0x06 && - p->CPU.Model >= CPU_MODEL_NEHALEM && - p->CPU.Model != CPU_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU + p->CPU.Model >= CPUID_MODEL_NEHALEM && + p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU ) { /* * Find the number of enabled cores and threads @@ -317,26 +317,26 @@ */ switch (p->CPU.Model) { - case CPU_MODEL_NEHALEM: - case CPU_MODEL_FIELDS: - case CPU_MODEL_DALES: - case CPU_MODEL_NEHALEM_EX: - case CPU_MODEL_JAKETOWN: - case CPU_MODEL_SANDYBRIDGE: - case CPU_MODEL_IVYBRIDGE: - case CPU_MODEL_HASWELL: - case CPU_MODEL_HASWELL_SVR: - //case CPU_MODEL_HASWELL_H: - case CPU_MODEL_HASWELL_ULT: - case CPU_MODEL_CRYSTALWELL: + case CPUID_MODEL_NEHALEM: + case CPUID_MODEL_FIELDS: + case CPUID_MODEL_DALES: + case CPUID_MODEL_NEHALEM_EX: + case CPUID_MODEL_JAKETOWN: + case CPUID_MODEL_SANDYBRIDGE: + case CPUID_MODEL_IVYBRIDGE: + case CPUID_MODEL_HASWELL: + case CPUID_MODEL_HASWELL_SVR: + //case CPUID_MODEL_HASWELL_H: + case CPUID_MODEL_HASWELL_ULT: + case CPUID_MODEL_CRYSTALWELL: msr = rdmsr64(MSR_CORE_THREAD_COUNT); p->CPU.NoCores = (uint8_t)bitfield((uint32_t)msr, 31, 16); p->CPU.NoThreads = (uint8_t)bitfield((uint32_t)msr, 15, 0); break; - case CPU_MODEL_DALES_32NM: - case CPU_MODEL_WESTMERE: - case CPU_MODEL_WESTMERE_EX: + case CPUID_MODEL_DALES_32NM: + case CPUID_MODEL_WESTMERE: + case CPUID_MODEL_WESTMERE_EX: msr = rdmsr64(MSR_CORE_THREAD_COUNT); p->CPU.NoCores = (uint8_t)bitfield((uint32_t)msr, 19, 16); p->CPU.NoThreads = (uint8_t)bitfield((uint32_t)msr, 15, 0); @@ -346,7 +346,7 @@ p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16); p->CPU.NoThreads = (uint8_t)(p->CPU.LogicalPerPackage & 0xff); //workaround for N270. I don't know why it detected wrong - if ((p->CPU.Model == CPU_MODEL_ATOM) && + if ((p->CPU.Model == CPUID_MODEL_ATOM) && (p->CPU.Stepping == 2)) { p->CPU.NoCores = 1; } @@ -461,23 +461,23 @@ if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) { /* Nehalem CPU model */ switch (p->CPU.Model) { - case CPU_MODEL_NEHALEM: - case CPU_MODEL_FIELDS: - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: - case CPU_MODEL_WESTMERE: - case CPU_MODEL_NEHALEM_EX: - case CPU_MODEL_WESTMERE_EX: + case CPUID_MODEL_NEHALEM: + case CPUID_MODEL_FIELDS: + case CPUID_MODEL_DALES: + case CPUID_MODEL_DALES_32NM: + case CPUID_MODEL_WESTMERE: + case CPUID_MODEL_NEHALEM_EX: + case CPUID_MODEL_WESTMERE_EX: /* --------------------------------------------------------- */ - case CPU_MODEL_SANDYBRIDGE: - case CPU_MODEL_JAKETOWN: - case CPU_MODEL_IVYBRIDGE_XEON: - case CPU_MODEL_IVYBRIDGE: - case CPU_MODEL_HASWELL: - case CPU_MODEL_HASWELL_SVR: + case CPUID_MODEL_SANDYBRIDGE: + case CPUID_MODEL_JAKETOWN: + case CPUID_MODEL_IVYBRIDGE_XEON: + case CPUID_MODEL_IVYBRIDGE: + case CPUID_MODEL_HASWELL: + case CPUID_MODEL_HASWELL_SVR: - case CPU_MODEL_HASWELL_ULT: - case CPU_MODEL_CRYSTALWELL: + case CPUID_MODEL_HASWELL_ULT: + case CPUID_MODEL_CRYSTALWELL: /* --------------------------------------------------------- */ msr = rdmsr64(MSR_PLATFORM_INFO); DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0)); Index: branches/ErmaC/Enoch/i386/libsaio/platform.h =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/platform.h (revision 2469) +++ branches/ErmaC/Enoch/i386/libsaio/platform.h (revision 2470) @@ -30,50 +30,50 @@ #define CPUID_88 9 #define CPUID_MAX 10 -#define CPU_MODEL_ANY 0x00 -#define CPU_MODEL_UNKNOWN 0x01 -#define CPU_MODEL_PRESCOTT 0x03 // Celeron D, Pentium 4 (90nm) -#define CPU_MODEL_NOCONA 0x04 // Xeon Nocona/Paxville, Irwindale (90nm) -#define CPU_MODEL_PRESLER 0x06 // Pentium 4, Pentium D (65nm) -#define CPU_MODEL_PENTIUM_M 0x09 // Banias Pentium M (130nm) -#define CPU_MODEL_DOTHAN 0x0D // Dothan Pentium M, Celeron M (90nm) -#define CPU_MODEL_YONAH 0x0E // Sossaman, Yonah -#define CPU_MODEL_MEROM 0x0F // Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom -#define CPU_MODEL_CONROE 0x0F // -#define CPU_MODEL_CELERON 0x16 // Merom, Conroe (65nm) -#define CPU_MODEL_PENRYN 0x17 // Wolfdale, Yorkfield, Harpertown, Penryn -#define CPU_MODEL_WOLFDALE 0x17 // -#define CPU_MODEL_NEHALEM 0x1A // Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown -#define CPU_MODEL_ATOM 0x1C // Pineview, Bonnell -#define CPU_MODEL_XEON_MP 0x1D // MP 7400 -#define CPU_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper Forest -#define CPU_MODEL_DALES 0x1F // Havendale, Auburndale -#define CPU_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale -#define CPU_MODEL_ATOM_SAN 0x26 // Lincroft -#define CPU_MODEL_LINCROFT 0x27 // Bonnell -#define CPU_MODEL_SANDYBRIDGE 0x2A // Sandy Bridge -#define CPU_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS -#define CPU_MODEL_JAKETOWN 0x2D // Sandy Bridge-E, Sandy Bridge-EP -#define CPU_MODEL_NEHALEM_EX 0x2E // Beckton -#define CPU_MODEL_WESTMERE_EX 0x2F // Westmere-EX -//#define CPU_MODEL_BONNELL_ATOM 0x35 // Bonnell -#define CPU_MODEL_ATOM_2000 0x36 // Cedarview / Saltwell -#define CPU_MODEL_SILVERMONT 0x37 // Atom Silvermont -#define CPU_MODEL_IVYBRIDGE 0x3A // Ivy Bridge -#define CPU_MODEL_HASWELL 0x3C // Haswell DT -#define CPU_MODEL_BROADWELL 0x3D // Core M, Broadwell / Core-AVX2 -#define CPU_MODEL_IVYBRIDGE_XEON 0x3E // Ivy Bridge Xeon -#define CPU_MODEL_HASWELL_SVR 0x3F // Haswell Server -//#define CPU_MODEL_HASWELL_H 0x?? // Haswell H -#define CPU_MODEL_HASWELL_ULT 0x45 // Haswell ULT -#define CPU_MODEL_CRYSTALWELL 0x46 // Crystal Well -// 4A silvermont / atom -#define CPU_MODEL_AVOTON 0x4D // Silvermont/Avoton Atom C2000 -// 4E Core??? -#define CPU_MODEL_BRODWELL_SVR 0x4F // Broadwell Server -#define CPU_MODEL_BRODWELL_MSVR 0x56 // Broadwell Micro Server -// 5A silvermont / atom -// 5D silvermont / atom +#define CPUID_MODEL_ANY 0x00 +#define CPUID_MODEL_UNKNOWN 0x01 +#define CPUID_MODEL_PRESCOTT 0x03 // Celeron D, Pentium 4 (90nm) +#define CPUID_MODEL_NOCONA 0x04 // Xeon Nocona/Paxville, Irwindale (90nm) +#define CPUID_MODEL_PRESLER 0x06 // Pentium 4, Pentium D (65nm) +#define CPUID_MODEL_PENTIUM_M 0x09 // Banias Pentium M (130nm) +#define CPUID_MODEL_DOTHAN 0x0D // Dothan Pentium M, Celeron M (90nm) +#define CPUID_MODEL_YONAH 0x0E // Sossaman, Yonah +#define CPUID_MODEL_MEROM 0x0F // Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom +#define CPUID_MODEL_CONROE 0x0F // +#define CPUID_MODEL_CELERON 0x16 // Merom, Conroe (65nm), Celeron (45nm) +#define CPUID_MODEL_PENRYN 0x17 // Wolfdale, Yorkfield, Harpertown, Penryn +#define CPUID_MODEL_WOLFDALE 0x17 // Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx +#define CPUID_MODEL_NEHALEM 0x1A // Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown +#define CPUID_MODEL_ATOM 0x1C // Pineview, Bonnell +#define CPUID_MODEL_XEON_MP 0x1D // MP 7400 +#define CPUID_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper Forest +#define CPUID_MODEL_DALES 0x1F // Havendale, Auburndale +#define CPUID_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale +#define CPUID_MODEL_ATOM_SAN 0x26 // Lincroft +#define CPUID_MODEL_LINCROFT 0x27 // Bonnell +#define CPUID_MODEL_SANDYBRIDGE 0x2A // Sandy Bridge +#define CPUID_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS +#define CPUID_MODEL_JAKETOWN 0x2D // Sandy Bridge-E, Sandy Bridge-EP +#define CPUID_MODEL_NEHALEM_EX 0x2E // Beckton +#define CPUID_MODEL_WESTMERE_EX 0x2F // Westmere-EX +//#define CPUID_MODEL_BONNELL_ATOM 0x35 // Atom Family Bonnell +#define CPUID_MODEL_ATOM_2000 0x36 // Cedarview / Saltwell +#define CPUID_MODEL_SILVERMONT 0x37 // Atom E3000, Z3000 Atom Silvermont +#define CPUID_MODEL_IVYBRIDGE 0x3A // Ivy Bridge +#define CPUID_MODEL_HASWELL 0x3C // Haswell DT +#define CPUID_MODEL_BROADWELL 0x3D // Core M, Broadwell / Core-AVX2 +#define CPUID_MODEL_IVYBRIDGE_XEON 0x3E // Ivy Bridge Xeon +#define CPUID_MODEL_HASWELL_SVR 0x3F // Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E) +//#define CPUID_MODEL_HASWELL_H 0x?? // Haswell H +#define CPUID_MODEL_HASWELL_ULT 0x45 // Haswell ULT, 4th gen Core, Xeon E3-12xx v3 +#define CPUID_MODEL_CRYSTALWELL 0x46 // Crystal Well, 4th gen Core, Xeon E3-12xx v3 +//#define CPUID_MODEL_ 0x4A // Future Atom E3000, Z3000 silvermont / atom +#define CPUID_MODEL_AVOTON 0x4D // Silvermont/Avoton Atom C2000 +//#define CPUID_MODEL_ 0x4E // Future Core +#define CPUID_MODEL_BRODWELL_SVR 0x4F // Broadwell Server +#define CPUID_MODEL_BRODWELL_MSVR 0x56 // Broadwell Micro Server, Future Xeon +//#define CPUID_MODEL_ 0x5A // Silvermont, Future Atom E3000, Z3000 +//#define CPUID_MODEL_ 0x5D // Silvermont, Future Atom E3000, Z3000 /* Unknown CPU */ #define CPU_STRING_UNKNOWN "Unknown CPU Type" Index: branches/ErmaC/Enoch/i386/libsaio/smbios.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/smbios.c (revision 2469) +++ branches/ErmaC/Enoch/i386/libsaio/smbios.c (revision 2470) @@ -691,9 +691,9 @@ { switch (Platform.CPU.Model) { - case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPUID_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPUID_MODEL_DALES: + case CPUID_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) defaultBIOSInfo.version = kDefaultiMacNehalemBIOSVersion; defaultBIOSInfo.releaseDate = kDefaultiMacNehalemBIOSReleaseDate; defaultSystemInfo.productName = kDefaultiMacNehalem; @@ -703,8 +703,8 @@ defaultChassis.chassisType = kSMBchassisAllInOne; break; - case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) - case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) + case CPUID_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPUID_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) defaultBIOSInfo.version = kDefaultiMacSandyBIOSVersion; defaultBIOSInfo.releaseDate = kDefaultiMacSandyBIOSReleaseDate; defaultSystemInfo.productName = kDefaultiMacSandy; @@ -714,8 +714,8 @@ defaultChassis.chassisType = kSMBchassisAllInOne; break; - case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) - case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x + case CPUID_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPUID_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x defaultBIOSInfo.version = kDefaultMacProNehalemBIOSVersion; defaultBIOSInfo.releaseDate = kDefaultMacProNehalemBIOSReleaseDate; defaultSystemInfo.productName = kDefaultMacProNehalem; @@ -726,10 +726,10 @@ defaultChassis.chassisType = kSMBchassisTower; break; - case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core - case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 - case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) - case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm) + case CPUID_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPUID_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPUID_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) + case CPUID_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm) defaultBIOSInfo.version = kDefaultMacProWestmereBIOSVersion; defaultBIOSInfo.releaseDate = kDefaultMacProWestmereBIOSReleaseDate; defaultSystemInfo.productName = kDefaultMacProWestmere; @@ -1008,21 +1008,21 @@ switch (Platform.CPU.Model) { case 0x19: // Intel Core i5 650 @3.20 Ghz - case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) - case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) - case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x - case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core - case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 - case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) - case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) - case CPU_MODEL_IVYBRIDGE_XEON: - case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) - case CPU_MODEL_HASWELL: - case CPU_MODEL_HASWELL_SVR: - case CPU_MODEL_HASWELL_ULT: - case CPU_MODEL_CRYSTALWELL: + case CPUID_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPUID_MODEL_DALES: + case CPUID_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPUID_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPUID_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x + case CPUID_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPUID_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPUID_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPUID_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) + case CPUID_MODEL_IVYBRIDGE_XEON: + case CPUID_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) + case CPUID_MODEL_HASWELL: + case CPUID_MODEL_HASWELL_SVR: + case CPUID_MODEL_HASWELL_ULT: + case CPUID_MODEL_CRYSTALWELL: break; Index: branches/ErmaC/Enoch/i386/libsaio/state_generator.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/state_generator.c (revision 2469) +++ branches/ErmaC/Enoch/i386/libsaio/state_generator.c (revision 2470) @@ -102,11 +102,11 @@ { switch (Platform.CPU.Model) { - case CPU_MODEL_DOTHAN: // Intel Pentium M - case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo - case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx - case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx - case CPU_MODEL_ATOM: // Intel Atom (45nm) + case CPUID_MODEL_DOTHAN: // Intel Pentium M + case CPUID_MODEL_YONAH: // Intel Mobile Core Solo, Duo + case CPUID_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx + case CPUID_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx + case CPUID_MODEL_ATOM: // Intel Atom (45nm) { bool cpu_dynamic_fsb = false; @@ -227,28 +227,28 @@ break; } - case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) - case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) - case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx - case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core - case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 - case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) - case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) - case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) - case CPU_MODEL_HASWELL: // - case CPU_MODEL_IVYBRIDGE_XEON: // - //case CPU_MODEL_HASWELL_H: // - case CPU_MODEL_HASWELL_SVR: // - case CPU_MODEL_HASWELL_ULT: // - case CPU_MODEL_CRYSTALWELL: // + case CPUID_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPUID_MODEL_DALES: + case CPUID_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPUID_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPUID_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx + case CPUID_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPUID_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPUID_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPUID_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) + case CPUID_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) + case CPUID_MODEL_HASWELL: // + case CPUID_MODEL_IVYBRIDGE_XEON: // + //case CPUID_MODEL_HASWELL_H: // + case CPUID_MODEL_HASWELL_SVR: // + case CPUID_MODEL_HASWELL_ULT: // + case CPUID_MODEL_CRYSTALWELL: // { - if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_JAKETOWN) || - (Platform.CPU.Model == CPU_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_HASWELL) || - (Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_SVR) || - (Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_CRYSTALWELL)) + if ((Platform.CPU.Model == CPUID_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPUID_MODEL_JAKETOWN) || + (Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPUID_MODEL_HASWELL) || + (Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPUID_MODEL_HASWELL_SVR) || + (Platform.CPU.Model == CPUID_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPUID_MODEL_CRYSTALWELL)) { maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff; } Index: branches/ErmaC/Enoch/i386/libsaio/smbios_getters.c =================================================================== --- branches/ErmaC/Enoch/i386/libsaio/smbios_getters.c (revision 2469) +++ branches/ErmaC/Enoch/i386/libsaio/smbios_getters.c (revision 2470) @@ -27,16 +27,16 @@ { switch (Platform.CPU.Model) { - // set external clock to 0 for SANDY - // removes FSB info from system profiler as on real mac's. - case CPU_MODEL_SANDYBRIDGE: - case CPU_MODEL_JAKETOWN: - case CPU_MODEL_IVYBRIDGE_XEON: - case CPU_MODEL_IVYBRIDGE: - case CPU_MODEL_HASWELL: - case CPU_MODEL_HASWELL_SVR: - case CPU_MODEL_HASWELL_ULT: - case CPU_MODEL_CRYSTALWELL: + // set external clock to 0 for SANDY + // removes FSB info from system profiler as on real mac's. + case CPUID_MODEL_SANDYBRIDGE: + case CPUID_MODEL_JAKETOWN: + case CPUID_MODEL_IVYBRIDGE_XEON: + case CPUID_MODEL_IVYBRIDGE: + case CPUID_MODEL_HASWELL: + case CPUID_MODEL_HASWELL_SVR: + case CPUID_MODEL_HASWELL_ULT: + case CPUID_MODEL_CRYSTALWELL: value->word = 0; break; @@ -70,28 +70,29 @@ { case 0x06: { - switch (Platform.CPU.Model) { - case CPU_MODEL_PENTIUM_M: - case CPU_MODEL_DOTHAN: // Intel Pentium M - case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo - case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx - case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx - case CPU_MODEL_ATOM: // Intel Atom (45nm) + switch (Platform.CPU.Model) + { + case CPUID_MODEL_PENTIUM_M: + case CPUID_MODEL_DOTHAN: // Intel Pentium M + case CPUID_MODEL_YONAH: // Intel Mobile Core Solo, Duo + case CPUID_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx + case CPUID_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx + case CPUID_MODEL_ATOM: // Intel Atom (45nm) return false; case 0x19: - case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) - case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) - case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core - case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x - case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 - case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) - case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) - case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) - case CPU_MODEL_IVYBRIDGE_XEON: - case CPU_MODEL_HASWELL: + case CPUID_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPUID_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPUID_MODEL_DALES: + case CPUID_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPUID_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPUID_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x + case CPUID_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPUID_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPUID_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm) + case CPUID_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) + case CPUID_MODEL_IVYBRIDGE_XEON: + case CPUID_MODEL_HASWELL: { // thanks to dgobe for i3/i5/i7 bus speed detection int nhm_bus = 0x3F; @@ -163,26 +164,29 @@ case 0x0F: case 0x06: { - switch (Platform.CPU.Model) { - case CPU_MODEL_PENTIUM_M: - case CPU_MODEL_DOTHAN: // 0x0D - Intel Pentium M model D - case CPU_MODEL_PRESCOTT: - case CPU_MODEL_NOCONA: - if (strstr(Platform.CPU.BrandString, "Xeon")) { + switch (Platform.CPU.Model) + { + case CPUID_MODEL_PENTIUM_M: + case CPUID_MODEL_DOTHAN: // 0x0D - Intel Pentium M model D + case CPUID_MODEL_PRESCOTT: + case CPUID_MODEL_NOCONA: + if (strstr(Platform.CPU.BrandString, "Xeon")) + { value->word = 0x402; // 1026 - Xeon } return true; - case CPU_MODEL_PRESLER: - case CPU_MODEL_CELERON: - case CPU_MODEL_YONAH: // 0x0E - Intel Mobile Core Solo, Duo + case CPUID_MODEL_PRESLER: + case CPUID_MODEL_CELERON: + case CPUID_MODEL_YONAH: // 0x0E - Intel Mobile Core Solo, Duo value->word = 0x201; // 513 return true; - case CPU_MODEL_MEROM: // 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx - case CPU_MODEL_XEON_MP: // 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm - case CPU_MODEL_PENRYN: // 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx - if (strstr(Platform.CPU.BrandString, "Xeon")) { + case CPUID_MODEL_MEROM: // 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx + case CPUID_MODEL_XEON_MP: // 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm + case CPUID_MODEL_PENRYN: // 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx + if (strstr(Platform.CPU.BrandString, "Xeon")) + { value->word = 0x402; // 1026 - Xeon return true; } @@ -193,16 +197,17 @@ } return true; - case CPU_MODEL_LINCROFT: // 0x27 - Intel Atom, "Lincroft", 45nm - case CPU_MODEL_ATOM: // 0x1C - Intel Atom (45nm) + case CPUID_MODEL_LINCROFT: // 0x27 - Intel Atom, "Lincroft", 45nm + case CPUID_MODEL_ATOM: // 0x1C - Intel Atom (45nm) return true; - case CPU_MODEL_NEHALEM_EX: // 0x2E - Nehalem-ex, "Beckton", 45nm - case CPU_MODEL_NEHALEM: // 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) - case CPU_MODEL_FIELDS: // 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) - case CPU_MODEL_DALES: // 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale) - if (strstr(Platform.CPU.BrandString, "Xeon")) { - value->word = 0x501; // 1281 - Lynnfiled Quad-Core Xeon + case CPUID_MODEL_NEHALEM_EX: // 0x2E - Nehalem-ex, "Beckton", 45nm + case CPUID_MODEL_NEHALEM: // 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPUID_MODEL_FIELDS: // 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPUID_MODEL_DALES: // 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale) + if (strstr(Platform.CPU.BrandString, "Xeon")) + { + value->word = 0x501; // 1281 - Lynnfiled Quad-Core Xeon return true; } if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) { @@ -222,10 +227,11 @@ } return true; - case CPU_MODEL_DALES_32NM: // 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale) - case CPU_MODEL_WESTMERE: // 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core - case CPU_MODEL_WESTMERE_EX: // 0x2F - Intel Xeon E7 - if (strstr(Platform.CPU.BrandString, "Xeon")) { + case CPUID_MODEL_DALES_32NM: // 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale) + case CPUID_MODEL_WESTMERE: // 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPUID_MODEL_WESTMERE_EX: // 0x2F - Intel Xeon E7 + if (strstr(Platform.CPU.BrandString, "Xeon")) + { value->word = 0x501; // 1281 - Xeon return true; } @@ -246,9 +252,10 @@ } return true; - case CPU_MODEL_JAKETOWN: // 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm) - case CPU_MODEL_SANDYBRIDGE: // 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm) - if (strstr(Platform.CPU.BrandString, "Xeon")) { + case CPUID_MODEL_JAKETOWN: // 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm) + case CPUID_MODEL_SANDYBRIDGE: // 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm) + if (strstr(Platform.CPU.BrandString, "Xeon")) + { value->word = 0x501; // 1281 - Xeon return true; } @@ -269,8 +276,9 @@ } return true; - case CPU_MODEL_IVYBRIDGE: // 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm) - if (strstr(Platform.CPU.BrandString, "Xeon")) { + case CPUID_MODEL_IVYBRIDGE: // 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm) + if (strstr(Platform.CPU.BrandString, "Xeon")) + { value->word = 0xA01; // 2561 - Xeon return true; } @@ -291,15 +299,16 @@ } return true; - case CPU_MODEL_IVYBRIDGE_XEON: // 0x3E - Mac Pro 6,1 - value->word = 0xA01; // 2561 - Xeon + case CPUID_MODEL_IVYBRIDGE_XEON: // 0x3E - Mac Pro 6,1 + value->word = 0xA01; // 2561 - Xeon return true; - case CPU_MODEL_HASWELL: // 0x3C - - case CPU_MODEL_HASWELL_SVR: // 0x3F - - case CPU_MODEL_HASWELL_ULT: // 0x45 - - case CPU_MODEL_CRYSTALWELL: // 0x46 - if (strstr(Platform.CPU.BrandString, "Xeon")) { + case CPUID_MODEL_HASWELL: // 0x3C - + case CPUID_MODEL_HASWELL_SVR: // 0x3F - + case CPUID_MODEL_HASWELL_ULT: // 0x45 - + case CPUID_MODEL_CRYSTALWELL: // 0x46 + if (strstr(Platform.CPU.BrandString, "Xeon")) + { value->word = 0xA01; // 2561 - Xeon return true; } Index: branches/ErmaC/Enoch/i386/modules/AcpiCodec/acpi_codec.c =================================================================== --- branches/ErmaC/Enoch/i386/modules/AcpiCodec/acpi_codec.c (revision 2469) +++ branches/ErmaC/Enoch/i386/modules/AcpiCodec/acpi_codec.c (revision 2470) @@ -775,12 +775,12 @@ static bool is_sandybridge(void) { - return Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE; + return Platform.CPU.Model == CPUID_MODEL_SANDYBRIDGE; } static bool is_jaketown(void) { - return Platform.CPU.Model == CPU_MODEL_JAKETOWN; + return Platform.CPU.Model == CPUID_MODEL_JAKETOWN; } static U32 get_bclk(void) @@ -1071,17 +1071,17 @@ { switch (Platform.CPU.Model) { - case CPU_MODEL_DOTHAN: - case CPU_MODEL_YONAH: // Yonah - case CPU_MODEL_MEROM: // Merom - case CPU_MODEL_PENRYN: // Penryn - case CPU_MODEL_ATOM: // Intel Atom (45nm) + case CPUID_MODEL_DOTHAN: + case CPUID_MODEL_YONAH: // Yonah + case CPUID_MODEL_MEROM: // Merom + case CPUID_MODEL_PENRYN: // Penryn + case CPUID_MODEL_ATOM: // Intel Atom (45nm) { cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0; cpu->core_c4_supported = ((sub_Cstates >> 16) & 0xf) ? 1 : 0; - if (Platform.CPU.Model == CPU_MODEL_ATOM) + if (Platform.CPU.Model == CPUID_MODEL_ATOM) { cpu->core_c2_supported = cpu->core_c3_supported = ((sub_Cstates >> 8) & 0xf) ? 1 : 0; cpu->core_c6_supported = ((sub_Cstates >> 12) & 0xf) ? 1 : 0; @@ -1121,15 +1121,15 @@ break; } - case CPU_MODEL_FIELDS: - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: - case CPU_MODEL_NEHALEM: - case CPU_MODEL_NEHALEM_EX: - case CPU_MODEL_WESTMERE: - case CPU_MODEL_WESTMERE_EX: - case CPU_MODEL_SANDYBRIDGE: - case CPU_MODEL_JAKETOWN: + case CPUID_MODEL_FIELDS: + case CPUID_MODEL_DALES: + case CPUID_MODEL_DALES_32NM: + case CPUID_MODEL_NEHALEM: + case CPUID_MODEL_NEHALEM_EX: + case CPUID_MODEL_WESTMERE: + case CPUID_MODEL_WESTMERE_EX: + case CPUID_MODEL_SANDYBRIDGE: + case CPUID_MODEL_JAKETOWN: { cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0; @@ -1332,11 +1332,11 @@ { switch (Platform.CPU.Model) { - case CPU_MODEL_DOTHAN: - case CPU_MODEL_YONAH: // Yonah - case CPU_MODEL_MEROM: // Merom - case CPU_MODEL_PENRYN: // Penryn - case CPU_MODEL_ATOM: // Intel Atom (45nm) + case CPUID_MODEL_DOTHAN: + case CPUID_MODEL_YONAH: // Yonah + case CPUID_MODEL_MEROM: // Merom + case CPUID_MODEL_PENRYN: // Penryn + case CPUID_MODEL_ATOM: // Intel Atom (45nm) { bool cpu_dynamic_fsb = false; @@ -1455,15 +1455,15 @@ } break; } - case CPU_MODEL_FIELDS: - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: - case CPU_MODEL_NEHALEM: - case CPU_MODEL_NEHALEM_EX: - case CPU_MODEL_WESTMERE: - case CPU_MODEL_WESTMERE_EX: - case CPU_MODEL_SANDYBRIDGE: - case CPU_MODEL_JAKETOWN: + case CPUID_MODEL_FIELDS: + case CPUID_MODEL_DALES: + case CPUID_MODEL_DALES_32NM: + case CPUID_MODEL_NEHALEM: + case CPUID_MODEL_NEHALEM_EX: + case CPUID_MODEL_WESTMERE: + case CPUID_MODEL_WESTMERE_EX: + case CPUID_MODEL_SANDYBRIDGE: + case CPUID_MODEL_JAKETOWN: { maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)... Index: branches/ErmaC/Enoch/CHANGES =================================================================== --- branches/ErmaC/Enoch/CHANGES (revision 2469) +++ branches/ErmaC/Enoch/CHANGES (revision 2470) @@ -1,3 +1,4 @@ +- ErmaC : Rename CPU_MODEL_xxx into CPUID_MODEL_xxx follow Apple source name - ErmaC : Rename decompress_lzvn function to lzvn_decode follow Apple source name. - ErmaC : Add more chameleon UI stuff (default) made by blackosx - ErmaC : Rollback changes for msdos.c (2327) thx to bltz @@ -23,7 +24,7 @@ Special thanks: Alex J, viv xix, zenith432 from http://forge.voodooprojects.org/p/chameleon/issues/375/ Testing and improvements: Pike R. Alpha, ErmaC, Bungo, blackosx, Micky1979, crazybirdy, oldnapalm, janek202, MinusZwei and Andy Vandijck. -- Pike R. Alpha : dinamic "random-seed" implementation ( http://www.insanelymac.com/forum/topic/301350-lets-make-random-seed-really-random/ ) +- Pike R. Alpha : dynamic "random-seed" implementation ( http://www.insanelymac.com/forum/topic/301350-lets-make-random-seed-really-random/ ) - ErmaC : getCPUTick() helper function ( http://www.insanelymac.com/forum/topic/301350-lets-make-random-seed-really-random/ ) - ErmaC : Add Yosemite Icons detection for chameleon UI - blackosx : Add chameleon UI Icons for Yosemite @@ -119,7 +120,6 @@ - cparm : Added a Sata module, known as YellowIconFixer in my branch, useful to fix yellow icon issue (can also fix an issue with the apple's dvd player application in moutain lion) - cparm : Ported the nvidia plist helper (less time to spend on the device id more time to code :-) ) - Added Recovery Icon for Default Theme (TODO) (credits to blackosx). -- Merge Intel Graphics 4000 device IDs from Chimera (Commit 1999). - Merge more cparm's (security, stability, bugs fixes) improvements from his branch. http://forge.voodooprojects.org/p/chameleon/source/tree/HEAD/branches/cparm - Merge "Restart fix Removed" from trunk r1992 by Slice's patch @@ -134,7 +134,6 @@ - Added ID and correct FB for: http://forge.voodooprojects.org/p/chameleon/issues/238/ - Added next coming CHIPSET and ID definition (Mosts of it commented) ML? (found via netkas.org): http://lists.freedesktop.org/archives/dri-devel/2012-March/020388.html -- Merge IVY Bridge stuff from Chimera Branch. - Added boot support for Mountain Lion 10.8 (credits to ErmaC) & updated the default theme (credits to blackosx) - cparm : Fixed naming convention for raid hfs devices in gui - Added support for using UUIDs with ext2 filesystems (credits to bitz): http://forge.voodooprojects.org/p/chameleon/issues/208/