Index: branches/zenith432/Chameleon.xcodeproj/project.pbxproj =================================================================== --- branches/zenith432/Chameleon.xcodeproj/project.pbxproj (revision 2804) +++ branches/zenith432/Chameleon.xcodeproj/project.pbxproj (revision 2805) @@ -10,6 +10,8 @@ 019DFBAF11FB94090013E8CC /* MEMTEST86_LICENSE */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = MEMTEST86_LICENSE; sourceTree = ""; }; 361BC70214BD977700236488 /* Changes.txt */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = Changes.txt; sourceTree = ""; }; 361BC70B14BD97C800236488 /* pkg.zip */ = {isa = PBXFileReference; lastKnownFileType = archive.zip; name = pkg.zip; path = Icons/pkg.zip; sourceTree = ""; }; + 36414DD01B065F880064E39A /* networking.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = networking.c; sourceTree = ""; }; + 36414DD11B065F880064E39A /* networking.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = networking.h; sourceTree = ""; }; 364B195E1A029963009A30BA /* background.png */ = {isa = PBXFileReference; lastKnownFileType = image.png; path = background.png; sourceTree = ""; }; 364B195F1A029963009A30BA /* boot.png */ = {isa = PBXFileReference; lastKnownFileType = image.png; path = boot.png; sourceTree = ""; }; 364B19601A029963009A30BA /* device_cdrom.png */ = {isa = PBXFileReference; lastKnownFileType = image.png; path = device_cdrom.png; sourceTree = ""; }; @@ -3298,6 +3300,8 @@ 3685F4181A1D60CF0036A800 /* msdos.h */, 3685F4191A1D60CF0036A800 /* nbp_cmd.h */, 3685F41A1A1D60CF0036A800 /* nbp.c */, + 36414DD01B065F880064E39A /* networking.c */, + 36414DD11B065F880064E39A /* networking.h */, 3685F41B1A1D60CF0036A800 /* ntfs_private.h */, 3685F41C1A1D60CF0036A800 /* ntfs.c */, 3685F41D1A1D60CF0036A800 /* ntfs.h */, Index: branches/zenith432/i386/libsaio/smbios_getters.h =================================================================== --- branches/zenith432/i386/libsaio/smbios_getters.h (revision 2804) +++ branches/zenith432/i386/libsaio/smbios_getters.h (revision 2805) @@ -33,6 +33,7 @@ extern bool getProcessorInformationExternalClock(returnType *value); extern bool getProcessorInformationMaximumClock(returnType *value); extern bool getSMBOemProcessorBusSpeed(returnType *value); +//extern bool getSMBOemPlatformFeature(returnType *value); extern bool getSMBOemProcessorType(returnType *value); extern bool getSMBMemoryDeviceMemoryType(returnType *value); extern bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value); Index: branches/zenith432/i386/libsaio/xml.c =================================================================== --- branches/zenith432/i386/libsaio/xml.c (revision 2804) +++ branches/zenith432/i386/libsaio/xml.c (revision 2805) @@ -27,7 +27,18 @@ #include "sl.h" #include "xml.h" +#ifndef DEBUG_XML + #define DEBUG_XML 0 +#endif + +#if DEBUG_XML + #define DBG(x...) printf(x) +#else + #define DBG(x...) +#endif + string_ref *ref_strings = NULL; +string_ref *ref_integer = NULL; /// TODO: remove below static char *buffer_start = NULL; @@ -55,6 +66,27 @@ ref_strings = new_ref; } +void SaveRefInteger(int integer, int id) +{ + //printf("Adding Ref Integer %d (%s)\n", id, integer); + string_ref *tmp = ref_integer; + while(tmp) + { + if(tmp->id == id) + { + tmp->string = (char*)integer; + return; + } + tmp = tmp->next; + } + + string_ref *new_ref = malloc(sizeof(string_ref)); + new_ref->string = (char*)integer; + new_ref->id = id; + new_ref->next = ref_integer; + ref_integer = new_ref; +} + char *GetRefString(int id) { string_ref *tmp = ref_strings; @@ -67,6 +99,18 @@ return "Unknown"; } +int GetRefInteger(int id) +{ + string_ref *tmp = ref_integer; + while(tmp) + { + if(tmp->id == id) return (int)tmp->string; + tmp = tmp->next; + } + //verbose("Unable to locate Ref String %d\n", id); + return 0; +} + struct Module { struct Module *nextModule; long willLoad; @@ -123,10 +167,8 @@ static void FreeSymbol(char *string); #endif - //========================================================================== // XMLGetProperty - TagPtr XMLGetProperty(TagPtr dict, const char *key) { TagPtr tagList, tag; @@ -157,7 +199,6 @@ //========================================================================== // XMLGetProperty - TagPtr XMLGetKey( TagPtr dict, int id ) { TagPtr tagList, tag; @@ -200,7 +241,6 @@ return key->tag; } - // XMLGetTag(int index) // XMLTagCount( TagPtr dict ) @@ -266,10 +306,10 @@ #define _e(str,c) {str,sizeof(str)-1,c} const XMLEntity ents[] = { _e("quot;",'"'), // double quotation mark - _e("apos;",'\''), // ampersand - _e("lt;", '<'), // apostrophe (apostrophe-quote) - _e("gt;", '>'), // less-than sign - _e("amp;", '&') // greater-than sign + _e("apos;",'\''), // apostrophe (apostrophe-quote) + _e("lt;", '<'), // less-than sign + _e("gt;", '>'), // greater-than sign + _e("amp;", '&') // ampersand }; /* Function for basic XML character entities parsing */ @@ -386,8 +426,8 @@ if (!strncmp(tagName, kXMLTagPList, 6)) { length = 0; - // just a header; nothing to parse - // return-via-reference tag should be left alone + // just a header; nothing to parse + // return-via-reference tag should be left alone } /***** dict ****/ else if (!strncmp(tagName, kXMLTagDict, sizeof(kXMLTagDict))) @@ -507,7 +547,7 @@ } length = ParseTagInteger(buffer + pos, tag); - SaveRefString((*tag)->string, id); + SaveRefInteger((int)(*tag)->string, id); } else if(!strncmp(tagName + strlen(kXMLTagInteger " "), kXMLStringIDRef, strlen(kXMLStringIDRef))) { @@ -530,7 +570,7 @@ return -1; } } - int integer = (int)GetRefString(id); + int integer = GetRefInteger(id); TagPtr tmpTag = NewTag(); if (tmpTag == 0) @@ -626,7 +666,6 @@ //========================================================================== // ParseTagList - static long ParseTagList( char *buffer, TagPtr *tag, long type, long empty ) { long pos = 0; @@ -683,7 +722,6 @@ //========================================================================== // ParseTagKey - static long ParseTagKey( char *buffer, TagPtr *tag ) { long length = 0; @@ -732,7 +770,6 @@ //========================================================================== // ParseTagString - static long ParseTagString( char *buffer, TagPtr *tag ) { long length = 0; @@ -769,7 +806,6 @@ //========================================================================== // ParseTagInteger - static long ParseTagInteger( char *buffer, TagPtr *tag ) { long length, integer; @@ -812,7 +848,7 @@ { val += 2; while(*val) - { + { if ((*val >= '0' && *val <= '9')) // 0 - 9 { integer = (integer * 16) + (*val++ - '0'); @@ -876,7 +912,6 @@ //========================================================================== // ParseTagData - static long ParseTagData( char *buffer, TagPtr *tag ) { int actuallen = 0; @@ -916,7 +951,6 @@ //========================================================================== // ParseTagDate - static long ParseTagDate( char *buffer, TagPtr *tag ) { long length = 0; @@ -950,7 +984,6 @@ //========================================================================== // ParseTagBoolean - long ParseTagBoolean( char *buffer, TagPtr *tag, long type ) { TagPtr tmpTag; @@ -975,7 +1008,6 @@ //========================================================================== // GetNextTag - static long GetNextTag( char *buffer, char **tag, long *start ) { long cnt; @@ -1025,7 +1057,6 @@ // Modifies 'buffer' to add a '\0' at the end of the tag matching 'tag'. // Returns the length of the data found, counting the end tag, // or -1 if the end tag was not found. - static long FixDataMatchingTag( char *buffer, char *tag ) { long length; @@ -1057,7 +1088,6 @@ //========================================================================== // NewTag - #define kTagsPerBlock (0x1000) static TagPtr gTagsFree = NULL; @@ -1095,7 +1125,6 @@ //========================================================================== // XMLFreeTag - void XMLFreeTag( TagPtr tag ) { #if DOFREE @@ -1126,7 +1155,6 @@ //========================================================================== // Symbol object. - struct Symbol { long refCount; @@ -1141,7 +1169,6 @@ //========================================================================== // NewSymbol - static char *NewSymbol( char *string ) { static SymbolPtr lastGuy = 0; @@ -1182,7 +1209,6 @@ //========================================================================== // FreeSymbol - #if DOFREE static void FreeSymbol( char *string ) { @@ -1221,7 +1247,6 @@ //========================================================================== // FindSymbol - static SymbolPtr FindSymbol( char *string, SymbolPtr *prevSymbol ) { SymbolPtr symbol, prev; Index: branches/zenith432/i386/libsaio/xml.h =================================================================== --- branches/zenith432/i386/libsaio/xml.h (revision 2804) +++ branches/zenith432/i386/libsaio/xml.h (revision 2805) @@ -83,12 +83,12 @@ bool XMLIsType(TagPtr dict, enum xmltype type); bool XMLCastBoolean( TagPtr dict ); -char* XMLCastString( TagPtr dict ); +char *XMLCastString( TagPtr dict ); long XMLCastStringOffset(TagPtr dict); int XMLCastInteger ( TagPtr dict ); TagPtr XMLCastDict ( TagPtr dict ); TagPtr XMLCastArray( TagPtr dict ); -char* XMLCastData( TagPtr dict, int *length ); +char *XMLCastData( TagPtr dict, int *length ); bool XMLIsBoolean(TagPtr entry); bool XMLIsString (TagPtr entry); @@ -102,7 +102,7 @@ long XMLParseNextTag(char *buffer, TagPtr *tag); void XMLFreeTag(TagPtr tag); -char* XMLDecode(const char *in); +char *XMLDecode(const char *in); //========================================================================== // XMLParseFile // Expects to see one dictionary in the XML file. Index: branches/zenith432/i386/libsaio/bootstruct.c =================================================================== --- branches/zenith432/i386/libsaio/bootstruct.c (revision 2804) +++ branches/zenith432/i386/libsaio/bootstruct.c (revision 2805) @@ -31,13 +31,13 @@ #include "bootstruct.h" #ifndef DEBUG_BOOTSTRUCT -#define DEBUG_BOOTSTRUCT 0 + #define DEBUG_BOOTSTRUCT 0 #endif #if DEBUG_BOOTSTRUCT -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) msglog(x) + #define DBG(x...) msglog(x) #endif /*========================================================================== @@ -45,9 +45,10 @@ * the kernel by the booter. */ -boot_args *bootArgs; -boot_args_pre_lion *bootArgsPreLion; -PrivateBootInfo_t *bootInfo; +boot_args *bootArgs = NULL; +boot_args_legacy *bootArgsLegacy = NULL; + +PrivateBootInfo_t *bootInfo = NULL; Node *gMemoryMapNode; static char platformName[64]; @@ -56,23 +57,27 @@ { Node *node; int nameLen; + static int init_done = 0; if ( !init_done ) { bootArgs = (boot_args *)malloc(sizeof(boot_args)); - bootArgsPreLion = (boot_args_pre_lion *)malloc(sizeof(boot_args_pre_lion)); + bootArgsLegacy = (boot_args_legacy *)malloc(sizeof(boot_args_legacy)); bootInfo = (PrivateBootInfo_t *)malloc(sizeof(PrivateBootInfo_t)); - if (bootArgs == 0 || bootArgsPreLion == 0 || bootInfo == 0) + + if (bootArgs == 0 || bootArgsLegacy == 0 || bootInfo == 0) + { stop("Couldn't allocate boot info\n"); + } bzero(bootArgs, sizeof(boot_args)); - bzero(bootArgsPreLion, sizeof(boot_args_pre_lion)); + bzero(bootArgsLegacy, sizeof(boot_args_legacy)); bzero(bootInfo, sizeof(PrivateBootInfo_t)); // Get system memory map. Also update the size of the // conventional/extended memory for backwards compatibility. - + bootInfo->memoryMapCount = getMemoryMap( bootInfo->memoryMap, kMemoryMapCountMax, (unsigned long *) &bootInfo->convmem, @@ -94,11 +99,13 @@ DT__Initialize(); node = DT__FindNode("/", true); - if (node == 0) { + if (node == 0) + { stop("Couldn't create root node"); } - getPlatformName(platformName); + getPlatformName(platformName, sizeof(platformName)); + nameLen = strlen(platformName) + 1; DT__AddProperty(node, "compatible", nameLen, platformName); DT__AddProperty(node, "model", nameLen, platformName); @@ -108,8 +115,8 @@ bootArgs->Version = kBootArgsVersion; bootArgs->Revision = kBootArgsRevision; - bootArgsPreLion->Version = kBootArgsPreLionVersion; - bootArgsPreLion->Revision = kBootArgsPreLionRevision; + bootArgsLegacy->Version = kBootArgsLegacyVersion; + bootArgsLegacy->Revision = kBootArgsLegacyRevision; init_done = 1; } @@ -119,16 +126,16 @@ void reserveKernBootStruct(void) { - if ( TIGER || LEOPARD || SNOW_LEOPARD ) + if ( MacOSVerCurrent < MacOSVer2Int("10.7") ) { // for 10.4 10.5 10.6 - void *oldAddr = bootArgsPreLion; - bootArgsPreLion = (boot_args_pre_lion *)AllocateKernelMemory(sizeof(boot_args_pre_lion)); - bcopy(oldAddr, bootArgsPreLion, sizeof(boot_args_pre_lion)); + void *oldAddr = bootArgsLegacy; + bootArgsLegacy = (boot_args_legacy *)AllocateKernelMemory(sizeof(boot_args_legacy)); + bcopy(oldAddr, bootArgsLegacy, sizeof(boot_args_legacy)); } else { - // for 10.7 10.8 10.9 10.10 + // for 10.7 10.8 10.9 10.10 10.11 void *oldAddr = bootArgs; bootArgs = (boot_args *)AllocateKernelMemory(sizeof(boot_args)); bcopy(oldAddr, bootArgs, sizeof(boot_args)); @@ -142,28 +149,41 @@ uint32_t size; void *addr; int i; - EfiMemoryRange *memoryMap; - MemoryRange *range; + + EfiMemoryRange *memoryMap = NULL; + MemoryRange *range = NULL; int memoryMapCount = bootInfo->memoryMapCount; if (memoryMapCount == 0) { // XXX could make a two-part map here - stop("Unable to convert memory map into proper format\n"); + stop("No memory map found!\n"); + return; } // convert memory map to boot_args memory map memoryMap = (EfiMemoryRange *)AllocateKernelMemory(sizeof(EfiMemoryRange) * memoryMapCount); + if (memoryMap == NULL) + { + stop("Unable to allocate kernel space for the memory map!\n"); + return; + } - bootArgs->MemoryMap = (uint32_t)memoryMap; - bootArgs->MemoryMapSize = sizeof(EfiMemoryRange) * memoryMapCount; - bootArgs->MemoryMapDescriptorSize = sizeof(EfiMemoryRange); - bootArgs->MemoryMapDescriptorVersion = 0; + bootArgs->MemoryMap = (uint32_t)memoryMap; + bootArgs->MemoryMapSize = sizeof(EfiMemoryRange) * memoryMapCount; + bootArgs->MemoryMapDescriptorSize = sizeof(EfiMemoryRange); + bootArgs->MemoryMapDescriptorVersion = 0; for (i = 0; i < memoryMapCount; i++, memoryMap++) { range = &bootInfo->memoryMap[i]; + if (!range || !memoryMap) + { + stop("Error while computing kernel memory map\n"); + return; + } + switch(range->type) { case kMemoryRangeACPI: @@ -200,39 +220,44 @@ // Flatten device tree DT__FlattenDeviceTree(0, &size); addr = (void *)AllocateKernelMemory(size); - if (addr == 0) { stop("Couldn't allocate device tree\n"); + return; } DT__FlattenDeviceTree((void **)&addr, &size); + if (!size) + { + stop("Couldn't get flatten device tree\n"); + return; + } bootArgs->deviceTreeP = (uint32_t)addr; bootArgs->deviceTreeLength = size; // Copy BootArgs values to older structure - memcpy(&bootArgsPreLion->CommandLine, &bootArgs->CommandLine, BOOT_LINE_LENGTH); - memcpy(&bootArgsPreLion->Video, &bootArgs->Video, sizeof(Boot_Video)); + memcpy(&bootArgsLegacy->CommandLine, &bootArgs->CommandLine, BOOT_LINE_LENGTH); + memcpy(&bootArgsLegacy->Video, &bootArgs->Video, sizeof(Boot_Video)); - bootArgsPreLion->MemoryMap = bootArgs->MemoryMap; - bootArgsPreLion->MemoryMapSize = bootArgs->MemoryMapSize; - bootArgsPreLion->MemoryMapDescriptorSize = bootArgs->MemoryMapDescriptorSize; - bootArgsPreLion->MemoryMapDescriptorVersion = bootArgs->MemoryMapDescriptorVersion; - - bootArgsPreLion->deviceTreeP = bootArgs->deviceTreeP; - bootArgsPreLion->deviceTreeLength = bootArgs->deviceTreeLength; + bootArgsLegacy->MemoryMap = bootArgs->MemoryMap; + bootArgsLegacy->MemoryMapSize = bootArgs->MemoryMapSize; + bootArgsLegacy->MemoryMapDescriptorSize = bootArgs->MemoryMapDescriptorSize; + bootArgsLegacy->MemoryMapDescriptorVersion = bootArgs->MemoryMapDescriptorVersion; - bootArgsPreLion->kaddr = bootArgs->kaddr; - bootArgsPreLion->ksize = bootArgs->ksize; + bootArgsLegacy->deviceTreeP = bootArgs->deviceTreeP; + bootArgsLegacy->deviceTreeLength = bootArgs->deviceTreeLength; - bootArgsPreLion->efiRuntimeServicesPageStart = bootArgs->efiRuntimeServicesPageStart; - bootArgsPreLion->efiRuntimeServicesPageCount = bootArgs->efiRuntimeServicesPageCount; - bootArgsPreLion->efiSystemTable = bootArgs->efiSystemTable; + bootArgsLegacy->kaddr = bootArgs->kaddr; + bootArgsLegacy->ksize = bootArgs->ksize; - bootArgsPreLion->efiMode = bootArgs->efiMode; + bootArgsLegacy->efiRuntimeServicesPageStart = bootArgs->efiRuntimeServicesPageStart; + bootArgsLegacy->efiRuntimeServicesPageCount = bootArgs->efiRuntimeServicesPageCount; + bootArgsLegacy->efiSystemTable = bootArgs->efiSystemTable; - bootArgsPreLion->performanceDataStart = bootArgs->performanceDataStart; - bootArgsPreLion->performanceDataSize = bootArgs->performanceDataSize; - bootArgsPreLion->efiRuntimeServicesVirtualPageStart = bootArgs->efiRuntimeServicesVirtualPageStart; + bootArgsLegacy->efiMode = bootArgs->efiMode; + + bootArgsLegacy->performanceDataStart = bootArgs->performanceDataStart; + bootArgsLegacy->performanceDataSize = bootArgs->performanceDataSize; + bootArgsLegacy->efiRuntimeServicesVirtualPageStart = bootArgs->efiRuntimeServicesVirtualPageStart; } Index: branches/zenith432/i386/libsaio/efi.h =================================================================== --- branches/zenith432/i386/libsaio/efi.h (revision 2804) +++ branches/zenith432/i386/libsaio/efi.h (revision 2805) @@ -140,11 +140,33 @@ } EFI_GUID; #define APPLE_VENDOR_GUID \ - {0xAC39C713, 0x7E50, 0x423D, {0x88, 0x9D, 0x27,0x8F, 0xCC, 0x34, 0x22, 0xB6} } + {0xAC39C713, 0x7E50, 0x423D, {0x88, 0x9D, 0x27, 0x8F, 0xCC, 0x34, 0x22, 0xB6} } #define EFI_GLOBAL_VARIABLE_GUID \ {0x8BE4DF61, 0x93CA, 0x11D2, {0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C} } +#define EFI_SMBIOS_TABLE_GUID \ + {0xEB9D2D31, 0x2D88, 0x11D3, {0x9A, 0x16, 0x0, 0x90, 0x27, 0x3F, 0xC1, 0x4D} } + +// ACPI 1.0 Table GUID in EFI System Table +#define EFI_ACPI_TABLE_GUID \ + {0xEB9D2D30, 0x2D88, 0x11D3, {0x9A, 0x16, 0x0, 0x90, 0x27, 0x3F, 0xC1, 0x4D} } + +// ACPI 2.0 Table GUID in EFI System Table +#define EFI_ACPI_20_TABLE_GUID \ + {0x8868E871, 0xE4f1, 0x11D3, {0xBC, 0x22, 0x0, 0x80, 0xC7, 0x3C, 0x88, 0x81} } + +// ACPI 3.0 Table GUID in EFI System Table +#define EFI_ACPI_30_TABLE_GUID EFI_ACPI_20_TABLE_GUID + +// The EFI variable GUID for the 'FirmwareFeatures' and friends. Also known as AppleFirmwareVariableGuid in other sources. +#define APPLE_FIRMWARE_VARIABLE_GUID \ + {0x4D1EDE05, 0x38C7, 0x4A6A, {0x9C, 0xC6, 0x4B, 0xCC, 0xA8, 0xB3, 0x8C, 0x14 } } + +// The EFI variable GUID for the 'boot-args' variable and others. Also known as AppleNVRAMVariableGuid in other sources. +#define APPLE_NVRAM_VARIABLE_GUID \ + {0x7C436110, 0xAB2A, 0x4BBB, {0xA8, 0x80, 0xFE, 0x41, 0x99, 0x5C, 0x9F, 0x82 } } + typedef union { EFI_GUID Guid; EFI_UINT8 Raw[16]; @@ -187,7 +209,7 @@ #define EFI_UNSPECIFIED_TIMEZONE 0x07FF typedef enum { - EfiReservedMemoryType, + EfiReservedMemoryType, // 0 EfiLoaderCode, EfiLoaderData, EfiBootServicesCode, @@ -201,7 +223,7 @@ EfiMemoryMappedIO, EfiMemoryMappedIOPortSpace, EfiPalCode, - EfiMaxMemoryType + EfiMaxMemoryType // 14 } EFI_MEMORY_TYPE; typedef struct { @@ -213,21 +235,18 @@ } __attribute__((aligned(8))) EFI_TABLE_HEADER; // possible caching types for the memory range +#define EFI_MEMORY_UC 0x0000000000000001ULL /* uncached */ +#define EFI_MEMORY_WC 0x0000000000000002ULL /* write-coalescing */ +#define EFI_MEMORY_WT 0x0000000000000004ULL /* write-through */ +#define EFI_MEMORY_WB 0x0000000000000008ULL /* write-back */ +#define EFI_MEMORY_UCE 0x0000000000000010ULL /* uncached, exported */ -#define EFI_MEMORY_UC 0x0000000000000001ULL -#define EFI_MEMORY_WC 0x0000000000000002ULL -#define EFI_MEMORY_WT 0x0000000000000004ULL -#define EFI_MEMORY_WB 0x0000000000000008ULL -#define EFI_MEMORY_UCE 0x0000000000000010ULL - - // physical memory protection on range -#define EFI_MEMORY_WP 0x0000000000001000ULL -#define EFI_MEMORY_RP 0x0000000000002000ULL -#define EFI_MEMORY_XP 0x0000000000004000ULL +#define EFI_MEMORY_WP 0x0000000000001000ULL /* write-protect */ +#define EFI_MEMORY_RP 0x0000000000002000ULL /* read-protect */ +#define EFI_MEMORY_XP 0x0000000000004000ULL /* execute-protect */ - // range requires a runtime mapping #define EFI_MEMORY_RUNTIME 0x8000000000000000ULL @@ -491,9 +510,12 @@ #define EFI_SYSTEM_TABLE_SIGNATURE 0x5453595320494249ULL #define EFI_SYSTEM_TABLE_REVISION ((EFI_SPECIFICATION_MAJOR_REVISION << 16) | (EFI_SPECIFICATION_MINOR_REVISION)) -#define EFI_2_00_SYSTEM_TABLE_REVISION ((2 << 16) | 00) -#define EFI_1_02_SYSTEM_TABLE_REVISION ((1 << 16) | 02) -#define EFI_1_10_SYSTEM_TABLE_REVISION ((1 << 16) | 10) +#define EFI_2_30_SYSTEM_TABLE_REVISION ((2 << 16) | (30)) +#define EFI_2_20_SYSTEM_TABLE_REVISION ((2 << 16) | (20)) +#define EFI_2_10_SYSTEM_TABLE_REVISION ((2 << 16) | (10)) +#define EFI_2_00_SYSTEM_TABLE_REVISION ((2 << 16) | (00)) +#define EFI_1_10_SYSTEM_TABLE_REVISION ((1 << 16) | (10)) +#define EFI_1_02_SYSTEM_TABLE_REVISION ((1 << 16) | (02)) typedef struct EFI_SYSTEM_TABLE_32 { EFI_TABLE_HEADER Hdr; Index: branches/zenith432/i386/libsaio/hfs_CaseTables.h =================================================================== --- branches/zenith432/i386/libsaio/hfs_CaseTables.h (revision 2804) +++ branches/zenith432/i386/libsaio/hfs_CaseTables.h (revision 2805) @@ -245,8 +245,8 @@ /* RelString case folding table */ -unsigned short gCompareTable[] = { - +unsigned short gCompareTable[] = +{ /* 0 */ 0x0000, 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700, 0x0800, 0x0900, 0x0A00, 0x0B00, 0x0C00, 0x0D00, 0x0E00, 0x0F00, /* 1 */ 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500, 0x1600, 0x1700, 0x1800, 0x1900, 0x1A00, 0x1B00, 0x1C00, 0x1D00, 0x1E00, 0x1F00, /* 2 */ 0x2000, 0x2100, 0x2200, 0x2300, 0x2400, 0x2500, 0x2600, 0x2700, 0x2800, 0x2900, 0x2A00, 0x2B00, 0x2C00, 0x2D00, 0x2E00, 0x2F00, @@ -261,7 +261,7 @@ /* 7 */ 0x5000, 0x5100, 0x5200, 0x5300, 0x5400, 0x5500, 0x5600, 0x5700, 0x5800, 0x5900, 0x5A00, 0x7B00, 0x7C00, 0x7D00, 0x7E00, 0x7F00, // range 0x80 to 0xd8 gets mapped... - + /* 8 */ 0x4108, 0x410C, 0x4310, 0x4502, 0x4E0A, 0x4F08, 0x5508, 0x4182, 0x4104, 0x4186, 0x4108, 0x410A, 0x410C, 0x4310, 0x4502, 0x4584, /* 9 */ 0x4586, 0x4588, 0x4982, 0x4984, 0x4986, 0x4988, 0x4E0A, 0x4F82, 0x4F84, 0x4F86, 0x4F08, 0x4F0A, 0x5582, 0x5584, 0x5586, 0x5508, /* A */ 0xA000, 0xA100, 0xA200, 0xA300, 0xA400, 0xA500, 0xA600, 0x5382, 0xA800, 0xA900, 0xAA00, 0xAB00, 0xAC00, 0xAD00, 0x4114, 0x4F0E, @@ -271,20 +271,21 @@ /* E */ 0xE000, 0xE100, 0xE200, 0xE300, 0xE400, 0xE500, 0xE600, 0xE700, 0xE800, 0xE900, 0xEA00, 0xEB00, 0xEC00, 0xED00, 0xEE00, 0xEF00, /* F */ 0xF000, 0xF100, 0xF200, 0xF300, 0xF400, 0xF500, 0xF600, 0xF700, 0xF800, 0xF900, 0xFA00, 0xFB00, 0xFC00, 0xFD00, 0xFE00, 0xFF00, - }; #else /* ! UNCOMPRESSED */ -enum { - kTypeLiteral = 0, - kTypeAscending = 1, - kTypeAscending256 = 2 +enum +{ + kTypeLiteral = 0, + kTypeAscending = 1, + kTypeAscending256 = 2 }; -struct compressed_block { - unsigned char type; - unsigned char count; - unsigned short data; +struct compressed_block +{ + unsigned char type; + unsigned char count; + unsigned short data; }; unsigned short *gLowerCaseTable; Index: branches/zenith432/i386/libsaio/bootstruct.h =================================================================== --- branches/zenith432/i386/libsaio/bootstruct.h (revision 2804) +++ branches/zenith432/i386/libsaio/bootstruct.h (revision 2805) @@ -33,9 +33,9 @@ /* * Kernel boot args global also used by booter for its own data. */ -extern boot_args *bootArgs; -extern boot_args_pre_lion *bootArgsPreLion; -extern Node *gMemoryMapNode; +extern boot_args *bootArgs; +extern boot_args_legacy *bootArgsLegacy; +extern Node *gMemoryMapNode; #define VGA_TEXT_MODE 0 //defined in /usr/../boot.h @@ -135,6 +135,7 @@ config_file_t smbiosConfig; // smbios.plist config_file_t helperConfig; // boot helper partition's boot.plist config_file_t ramdiskConfig; // RAMDisk.plist + config_file_t kernelConfig; // kernel.plist bool memDetect; } PrivateBootInfo_t; Index: branches/zenith432/i386/libsaio/device_tree.c =================================================================== --- branches/zenith432/i386/libsaio/device_tree.c (revision 2804) +++ branches/zenith432/i386/libsaio/device_tree.c (revision 2805) @@ -27,14 +27,16 @@ #define kPropNameLength 32 -typedef struct DeviceTreeNodeProperty { +typedef struct DeviceTreeNodeProperty +{ char name[kPropNameLength]; // NUL terminated property name unsigned long length; // Length (bytes) of folloing prop value // unsigned long value[1]; // Variable length value of property // Padded to a multiple of a longword? } DeviceTreeNodeProperty; -typedef struct OpaqueDTEntry { +typedef struct OpaqueDTEntry +{ unsigned long nProperties; // Number of props[] elements (0 => end) unsigned long nChildren; // Number of children[] elements // DeviceTreeNodeProperty props[];// array size == nProperties @@ -66,7 +68,8 @@ #define RoundToLong(x) (((x) + 3) & ~3) -static struct _DTSizeInfo { +static struct _DTSizeInfo +{ uint32_t numNodes; uint32_t numProperties; uint32_t totalPropertySize; @@ -122,9 +125,12 @@ prop->value = value; // Always add to end of list - if (node->properties == 0) { + if (node->properties == 0) + { node->properties = prop; - } else { + } + else + { node->last_prop->next = prop; } @@ -196,6 +202,7 @@ } DTInfo.numNodes++; + DT__AddProperty(node, "name", strlen(name) + 1, (void *) name); return node; @@ -281,7 +288,8 @@ DeviceTreeNodeProperty *flatProp; int count; - if (node == 0) { + if (node == 0) + { return buffer; } @@ -326,7 +334,8 @@ DPRINTF("DT__FlattenDeviceTree(0x%x, 0x%x)\n", buffer_p, length); #if DEBUG - if (buffer_p) { + if (buffer_p) + { DT__PrintTree(rootNode); } #endif @@ -421,7 +430,7 @@ int i; DPRINTF("DT__FindNode('%s', %d)\n", path, createIfMissing); - + // Start at root node = rootNode; @@ -547,20 +556,28 @@ void *prop; int propSize; - if (level > 9) level = 9; - while (level--) *cp++ = ' '; - *cp = '\0'; + if (level > 9) + { + level = 9; + } + while (level--) + { + *cp++ = ' '; + } + *cp = '\0'; printf("%s===Entry %p===\n", spaces, entry); - if (kSuccess != DTCreatePropertyIterator(entry, &propIter)) + if (kSuccess != DTCreatePropertyIterator(entry, &propIter)) + { + printf("Couldn't create property iterator\n"); + return; + } + while( kSuccess == DTIterateProperties( propIter, &name)) + { + if( kSuccess != DTGetProperty( entry, name, &prop, &propSize )) { - printf("Couldn't create property iterator\n"); - return; + continue; } - while( kSuccess == DTIterateProperties( propIter, &name)) - { - if( kSuccess != DTGetProperty( entry, name, &prop, &propSize )) - continue; printf("%s Property %s = %s\n", spaces, name, prop); } DTDisposePropertyIterator(propIter); Index: branches/zenith432/i386/libsaio/hfs.c =================================================================== --- branches/zenith432/i386/libsaio/hfs.c (revision 2804) +++ branches/zenith432/i386/libsaio/hfs.c (revision 2805) @@ -105,9 +105,9 @@ static long CompareHFSPlusExtentsKeys(void *key, void *testKey); extern long FastRelString(u_int8_t *str1, u_int8_t *str2); -extern long BinaryUnicodeCompare(u_int16_t *uniStr1, u_int32_t len1, - u_int16_t *uniStr2, u_int32_t len2); +extern long BinaryUnicodeCompare(u_int16_t *uniStr1, u_int32_t len1, u_int16_t *uniStr2, u_int32_t len2); + //============================================================================== static void SwapFinderInfo(FndrFileInfo *dst, FndrFileInfo *src) @@ -133,12 +133,11 @@ bool HFSProbe (const void *buf) { - const HFSMasterDirectoryBlock *mdb; - const HFSPlusVolumeHeader *header; - mdb = (const HFSMasterDirectoryBlock *)(((const char*)buf)+kMDBBaseOffset); - header = (const HFSPlusVolumeHeader *)(((const char*)buf)+kMDBBaseOffset); + const HFSMasterDirectoryBlock *mdb = (const HFSMasterDirectoryBlock *)(((const char*)buf)+kMDBBaseOffset); + const HFSPlusVolumeHeader *header = (const HFSPlusVolumeHeader *)(((const char*)buf)+kMDBBaseOffset); - if ( SWAP_BE16(mdb->drSigWord) == kHFSSigWord ) { + if ( SWAP_BE16(mdb->drSigWord) == kHFSSigWord ) + { return true; } @@ -162,7 +161,7 @@ #ifdef __i386__ CacheInit(ih, gCacheBlockSize); #endif - return 0; + return 0L; } #ifdef __i386__ @@ -170,24 +169,29 @@ { gTempStr = (char *)malloc(4096); } + if (!gLinkTemp) { gLinkTemp = (char *)malloc(64); } + if (!gBTreeHeaderBuffer) { gBTreeHeaderBuffer = (char *)malloc(512); } + if (!gHFSMdbVib) { gHFSMdbVib = (char *)malloc(kBlockSize); gHFSMDB = (HFSMasterDirectoryBlock *)gHFSMdbVib; } + if (!gHFSPlusHeader) { gHFSPlusHeader = (char *)malloc(kBlockSize); gHFSPlus = (HFSPlusVolumeHeader *)gHFSPlusHeader; } + if (!gTempStr || !gLinkTemp || !gBTreeHeaderBuffer || !gHFSMdbVib || !gHFSPlusHeader) { return -1; @@ -251,7 +255,8 @@ { verbose("HFS signature was not present.\n"); gCurrentIH = 0; - return -1; + + return -1L; } gIsHFSPlus = 1; @@ -280,7 +285,7 @@ CacheInit(ih, gCacheBlockSize); } - return 0; + return 0L; } //============================================================================== @@ -319,7 +324,7 @@ if (dirID == 0) { - return -1; + return -1L; } filePath++; @@ -332,7 +337,7 @@ if ((result == -1) || ((flags & kFileTypeMask) != kFileTypeFlat)) { - return -1; + return -1L; } #if UNUSED @@ -340,14 +345,14 @@ // Check file owner and permissions. if (flags & (kOwnerNotRoot | kPermGroupWrite | kPermOtherWrite)) { - return -1; + return -1L; } #endif result = ReadFile(entry, &length, base, offset); if (result == -1) { - return -1; + return -1L; } getDeviceDescription(ih, devStr); @@ -469,12 +474,13 @@ long result, flags; u_int32_t dirID; void *extents; + HFSCatalogFile *hfsFile = (void *)entry; HFSPlusCatalogFile *hfsPlusFile = (void *)entry; if (HFSInitPartition(ih) == -1) { - return -1; + return -1L; } dirID = kHFSRootFolderID; @@ -506,12 +512,15 @@ if ((result == -1) || ((flags & kFileTypeMask) != kFileTypeFlat)) { printf("HFS: Resolve path '%s' failed\n", filePath); - return -1; + return -1L; } - if (gIsHFSPlus) { + if (gIsHFSPlus) + { extents = &hfsPlusFile->dataFork.extents; - } else { + } + else + { extents = &hfsFile->dataExtents; } @@ -521,7 +530,7 @@ printf("Allocation offset 0x%x\n", (unsigned long)gAllocationOffset); #endif *firstBlock = ((u_int64_t) GetExtentStart(extents, 0) * (u_int64_t) gBlockSize + gAllocationOffset) / 512ULL; - return 0; + return 0L; } @@ -570,7 +579,7 @@ { printf("ReadFile(HFS%s): Offset is too large.\n", gIsHFSPlus ? "+" : ""); - return -1; + return -1L; } if ((*length == 0) || ((offset + *length) > fileLength)) @@ -588,18 +597,18 @@ *length = ReadExtent((char *)extents, fileLength, fileID, offset, *length, (char *)base, 0); - return 0; + return 0L; } //============================================================================== static long GetCatalogEntryInfo(void * entry, long * flags, u_int32_t * time, FinderInfo * finderInfo, long * infoValid) { - u_int32_t tmpTime = 0; - long valid = 0; + u_int32_t tmpTime = 0L; + long valid = 0L; // Get information about the file. - + switch ( SWAP_BE16(*(short *)entry) ) { case kHFSFolderRecord : @@ -609,6 +618,7 @@ case kHFSPlusFolderRecord : *flags = kFileTypeDirectory | (SWAP_BE16(((HFSPlusCatalogFolder *)entry)->bsdInfo.fileMode) & kPermMask); + if (SWAP_BE32(((HFSPlusCatalogFolder *)entry)->bsdInfo.ownerID) != 0) { *flags |= kOwnerNotRoot; @@ -662,7 +672,7 @@ *infoValid = valid; } - return 0; + return 0L; } //============================================================================== @@ -677,6 +687,7 @@ // Copy the file name to gTempStr cnt = 0; + while ((filePath[cnt] != '/') && (filePath[cnt] != '\0')) { cnt++; @@ -784,6 +795,7 @@ gTempStr[((HFSCatalogKey *)testKey)->nodeName[0]] = '\0'; } + *name = gTempStr; // Update dirIndex. @@ -794,6 +806,7 @@ index = 0; curNode = SWAP_BE32(node->fLink); } + *dirIndex = (long long) curNode * nodeSize + index; free(nodeBuf); @@ -987,7 +1000,7 @@ index = upperBound; GetBTreeRecord(index, nodeBuf, nodeSize, &testKey, &recordData); } - + // Found the closest key... Recurse on it if this is an index node. if (node->kind == kBTIndexNode) { @@ -1048,11 +1061,13 @@ if (dirIndex != 0) { index++; + if (index == SWAP_BE16(node->numRecords)) { index = 0; curNode = SWAP_BE32(node->fLink); } + *dirIndex = (long long) curNode * nodeSize + index; } @@ -1162,7 +1177,6 @@ readOffset = ((blockNumber - countedBlocks) * gBlockSize) + (offset % gBlockSize); - // MacWen: fix overflow in multiplication by forcing 64bit multiplication readSize = (long long)GetExtentSize(currentExtent, 0) * gBlockSize - readOffset; if (readSize > (size - sizeRead)) @@ -1212,7 +1226,7 @@ static u_int32_t GetExtentSize(void * extents, u_int32_t index) { - u_int32_t size = 0; + u_int32_t size = 0L; HFSExtentDescriptor *hfsExtents = extents; HFSPlusExtentDescriptor *hfsPlusExtents = extents; @@ -1278,7 +1292,7 @@ { result = 1; } - else if (searchParentID < trialParentID) + else if (searchParentID < trialParentID) { result = -1; } @@ -1369,14 +1383,11 @@ { HFSPlusExtentKey *searchKey, *trialKey; - long result; + long result = -1; // assume searchKey < trialKey searchKey = key; trialKey = testKey; - // assume searchKey < trialKey - result = -1; - if (searchKey->fileID == trialKey->fileID) { // FileNum's are equal; compare fork types @@ -1415,6 +1426,6 @@ } } - return result; + return result; } Index: branches/zenith432/i386/libsaio/vbe.h =================================================================== --- branches/zenith432/i386/libsaio/vbe.h (revision 2804) +++ branches/zenith432/i386/libsaio/vbe.h (revision 2805) @@ -211,6 +211,23 @@ mode1280x1024x555 = 0x119, mode1280x1024x565 = 0x11A, mode1280x1024x888 = 0x11B, + mode1600x1200x8 = 0x11C, + mode1600x1200x1555= 0x11D, + mode1600x1200x565 = 0x11E, + mode1600x1200x888 = 0x11F, + mode320X200X8888 = 0x140, + mode640X400X8888 = 0x141, + mode640X480X8888 = 0x142, + mode800X600X8888 = 0x143, + mode1024X768X8888 = 0x144, + mode1280X1024X8888= 0x145, + mode320X200X8 = 0x146, + mode1600X1200X8888= 0x147, + mode1152X864X8 = 0x148, + mode1152X864X1555 = 0x149, + mode1152X864X565 = 0x14A, + mode1152X864X888 = 0x14B, + mode1152X864X8888 = 0x14C, modeSpecial = 0x81FF, modeEndOfList = 0xFFFF }; Index: branches/zenith432/i386/libsaio/acpi_patcher.c =================================================================== --- branches/zenith432/i386/libsaio/acpi_patcher.c (revision 2804) +++ branches/zenith432/i386/libsaio/acpi_patcher.c (revision 2805) @@ -17,14 +17,14 @@ #ifndef DEBUG_ACPI #define DEBUG_ACPI 0 -#endif + #endif #if DEBUG_ACPI==2 -#define DBG(x...) {printf(x); sleep(1);} + #define DBG(x...) {printf(x); sleep(1);} #elif DEBUG_ACPI==1 -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) msglog(x) + #define DBG(x...) msglog(x) #endif // Slice: New signature compare function @@ -33,7 +33,7 @@ int i; for (i = 0; i < 4; i++) { - if ((table[i] &~0x20) != (sgn[i] &~0x20)) + if ((table[i] & ~0x20) != (sgn[i] & ~0x20)) { return false; } @@ -53,7 +53,7 @@ if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE) { uint8_t csum = checksum8(acpi_addr, 20); - if(csum == 0) + if (csum == 0) { // Only return the table if it is a true version 1.0 table (Revision 0) if(((struct acpi_2_rsdp*)acpi_addr)->Revision == 0) @@ -117,7 +117,7 @@ if (fd < 0) { // NOT FOUND: - DBG("ACPI Table not found: %s\n", filename); + DBG("\tACPI Table not found: %s\n", filename); *dirSpec = '\0'; } } @@ -135,86 +135,28 @@ if (fd >= 0) { - void *tableAddr = (void*)AllocateKernelMemory(file_size(fd)); + void *tableAddr = (void *)AllocateKernelMemory(file_size(fd)); if (tableAddr) { if (read(fd, tableAddr, file_size(fd)) != file_size(fd)) { - DBG("Couldn't read table %s\n",dirspec); + DBG("\tCouldn't read table %s\n", dirspec); free(tableAddr); close(fd); return NULL; } - DBG("Table %s read and stored at: %x\n", dirspec, tableAddr); + DBG("\tTable %s read and stored at: %x\n", dirspec, tableAddr); close(fd); return tableAddr; } close(fd); - DBG("Couldn't allocate memory for table \n", dirspec); - } + DBG("\tCouldn't allocate memory for table: %s.\n", dirspec); + } //printf("Couldn't find table %s\n", filename); return NULL; } -uint8_t acpi_cpu_count = 0; -uint32_t acpi_cpu_p_blk = 0; -char *acpi_cpu_name[32]; - -void get_acpi_cpu_names(unsigned char *dsdt, uint32_t length) -{ - uint32_t i; - - DBG("ACPIpatcher: start finding cpu names. Length %d\n", length); - - for (i=0; i> 6); - - bool add_name = true; - - uint8_t j; - - for (j=0; j<4; j++) - { - char c = dsdt[offset+j]; - - if (!aml_isvalidchar(c)) - { - add_name = false; - DBG("ACPIpatcher: invalid character found in ProcessorOP '0x%X'!\n", c); - break; - } - } - - if (add_name) - { - acpi_cpu_name[acpi_cpu_count] = malloc(4); - memcpy(acpi_cpu_name[acpi_cpu_count], dsdt+offset, 4); - i = offset + 5; - - if (acpi_cpu_count == 0) - { - acpi_cpu_p_blk = dsdt[i] | (dsdt[i+1] << 8); - } - - DBG("ACPIpatcher: found ACPI CPU [%c%c%c%c]\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]); - - if (++acpi_cpu_count == 32) - { - return; - } - } - } - } - - DBG("ACPIpatcher: finished finding cpu names. Found: %d.\n", acpi_cpu_count); -} - struct acpi_2_fadt *patch_fadt(struct acpi_2_fadt *fadt, struct acpi_2_dsdt *new_dsdt) { extern void setupSystemType(); @@ -241,7 +183,7 @@ } else { - DBG("Not an Intel platform: Restart Fix not applied !!!\n"); + DBG("\tNot an Intel platform, FACP Restart Fix will not be applied!\n"); fix_restart = false; } @@ -251,12 +193,12 @@ } // Allocate new fadt table - if (fadt->Length < 0x84 && fadt_rev2_needed) + if ((fadt->Length < 0x84) && fadt_rev2_needed) { fadt_mod = (struct acpi_2_fadt *)AllocateKernelMemory(0x84); memcpy(fadt_mod, fadt, fadt->Length); fadt_mod->Length = 0x84; - fadt_mod->Revision = 0x02; // FADT rev 2 (ACPI 1.0B MS extensions) + fadt_mod->Revision = 0x02; // FACP rev 2 (ACPI 1.0B MS extensions) } else { @@ -276,7 +218,7 @@ { Platform.Type = 1; /* Set a fixed value (Desktop) */ } - DBG("Error: system-type must be 0..6. Defaulting to %d !\n", Platform.Type); + DBG("\tError: system-type must be 0..6. Defaulting to %d !\n", Platform.Type); } else { @@ -289,7 +231,7 @@ if (value) { // user has overriden the SystemType so take care of it in FACP - DBG("FADT: changing PM_Profile from 0x%02x to 0x%02x\n", fadt_mod->PM_Profile, Platform.Type); + DBG("\tFADT: changing PM_Profile from 0x%02x to 0x%02x\n", fadt_mod->PM_Profile, Platform.Type); fadt_mod->PM_Profile = Platform.Type; } else @@ -302,7 +244,7 @@ // because we need to take care of FACP original content, if it is correct. setupSystemType(); - // Patch FADT to fix restart + // Patch FACP to fix restart if (fix_restart) { if (fix_restart_ps2) @@ -314,7 +256,7 @@ fadt_mod->Reset_AccessWidth = 0x01; // Byte access fadt_mod->Reset_Address = 0x64; // Address of the register fadt_mod->Reset_Value = 0xfe; // Value to write to reset the system - DBG("FADT: PS2 Restart Fix applied!\n"); + DBG("\tFACP PS2 Restart Fix applied!\n"); } else { @@ -325,25 +267,37 @@ fadt_mod->Reset_AccessWidth = 0x01; // Byte access fadt_mod->Reset_Address = 0x0cf9; // Address of the register fadt_mod->Reset_Value = 0x06; // Value to write to reset the system - DBG("FADT: ACPI Restart Fix applied!\n"); + DBG("\tFACP Restart Fix applied!\n"); } } - // Patch DSDT Address if we have loaded DSDT.aml - if(new_dsdt) + // Bungo: Save Hardware Signature (machine-signature) + if ((fadt_mod->FACS > 0) && (fadt_mod->FACS < 0xFFFFFFFF) && (((struct acpi_2_facs *)fadt_mod->FACS)->Length >= 64)) { - DBG("DSDT: Old @%x,%x, ",fadt_mod->DSDT,fadt_mod->X_DSDT); + Platform.HWSignature = ((struct acpi_2_facs *)fadt_mod->FACS)->HWSignature; + DBG("\tHardware Signature=0x%08X: using.\n", Platform.HWSignature); + } + else + { + Platform.HWSignature = 0; + DBG("\tFixing Hardware Signature=0x%08X.\n", Platform.HWSignature); + } - fadt_mod->DSDT=(uint32_t)new_dsdt; - if ((uint32_t)(&(fadt_mod->X_DSDT))-(uint32_t)fadt_mod+8<=fadt_mod->Length) + // Patch DSDT address if we have loaded DSDT.aml + if (new_dsdt) + { + DBG("\tDSDT: Old @%x,%x, ",fadt_mod->DSDT,fadt_mod->X_DSDT); + + fadt_mod->DSDT = (uint32_t)new_dsdt; + if ((uint32_t)(&(fadt_mod->X_DSDT)) - (uint32_t)fadt_mod + 8<=fadt_mod->Length) { - fadt_mod->X_DSDT=(uint32_t)new_dsdt; + fadt_mod->X_DSDT = (uint32_t)new_dsdt; } - DBG("New @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT); + DBG("\tNew @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT); - DBG("FADT: Using custom DSDT!\n"); + DBG("\tFADT: Using custom DSDT!\n"); } // Correct the checksum @@ -368,7 +322,7 @@ } else { - DBG("No ACPI 2.\n"); + DBG("\tNo ACPI 2.\n"); } return 1; } @@ -376,6 +330,7 @@ /* Setup ACPI. Replace DSDT if DSDT.aml is found */ int setupAcpi(void) { + verbose("[ ACPI PATCHER ]\n"); int version; void *new_dsdt = NULL; @@ -417,9 +372,11 @@ getBoolForKey(kDropSSDT, &drop_ssdt, &bootInfo->chameleonConfig); getBoolForKey(kGeneratePStates, &generate_pstates, &bootInfo->chameleonConfig); getBoolForKey(kGenerateCStates, &generate_cstates, &bootInfo->chameleonConfig); + //getBoolForKey(kGenerateTStates, &generate_tstates, &bootInfo->chameleonConfig); - DBG("Generating P-States config: %s\n", generate_pstates ? "YES" : "NO"); - DBG("Generating C-States config: %s\n", generate_cstates ? "YES" : "NO"); + DBG("\tGenerating P-States config: %s\n", generate_pstates ? "Yes" : "No"); + DBG("\tGenerating C-States config: %s\n", generate_cstates ? "Yes" : "No"); + //DBG("Generating T-States config: %s\n", generate_tstates ? "Yes" : "No"); { int i; @@ -459,7 +416,7 @@ rsdp = (struct acpi_2_rsdp *)(version ? getAddressOfAcpi20Table() : getAddressOfAcpiTable()); if (!rsdp) { - DBG("No ACPI version %d found. Ignoring\n", version+1); + DBG("\tNo ACPI version %d found. Ignoring\n", version+1); if (version) { addConfigurationTable(&gEfiAcpi20TableGuid, NULL, "ACPI_20"); @@ -472,7 +429,7 @@ } rsdplength = version ? rsdp->Length : 20; - DBG("RSDP version %d found @%x. Length=%d\n",version+1,rsdp,rsdplength); + DBG("\tRSDP version %d found @%x. Length=%d\n",version+1,rsdp,rsdplength); /* FIXME: no check that memory allocation succeeded * Copy and patch RSDP,RSDT, XSDT and FADT @@ -484,13 +441,13 @@ rsdt = (struct acpi_2_rsdt *)rsdp->RsdtAddress; - DBG("RSDT @%x, Length %d\n",rsdt, rsdt ? rsdt->Length : 0); + DBG("\tRSDT @%x, Length %d\n",rsdt, rsdt ? rsdt->Length : 0); if (rsdt && (uint32_t)rsdt !=0xffffffff && rsdt->Length < 0x10000) { uint32_t *rsdt_entries; int rsdt_entries_num; - int dropoffset=0, i; + int dropoffset = 0, i; // mozo: using malloc cos I didn't found how to free already allocated kernel memory rsdt_mod = (struct acpi_2_rsdt *)malloc(rsdt->Length); @@ -498,7 +455,7 @@ rsdp_mod->RsdtAddress = (uint32_t)rsdt_mod; rsdt_entries_num = (rsdt_mod->Length - sizeof(struct acpi_2_rsdt)) / 4; rsdt_entries = (uint32_t *)(rsdt_mod + 1); - for (i = 0;i < rsdt_entries_num;i++) + for (i = 0; i < rsdt_entries_num; i++) { char *table=(char *)(rsdt_entries[i]); if (!table) @@ -506,24 +463,24 @@ continue; } - DBG("TABLE %c%c%c%c,",table[0],table[1],table[2],table[3]); + DBG("\tTABLE %c%c%c%c,",table[0],table[1],table[2],table[3]); rsdt_entries[i-dropoffset]=rsdt_entries[i]; if (drop_ssdt && tableSign(table, "SSDT")) { - DBG("OEM SSDT tables was dropped\n"); + DBG("\tOEM SSDT tables was dropped\n"); dropoffset++; continue; } if (tableSign(table, "DSDT")) { - DBG("DSDT found\n"); - verbose("Custom DSDT table was found\n"); + DBG("\tDSDT found\n"); + DBG("\tCustom DSDT table was found\n"); if(new_dsdt) { - rsdt_entries[i-dropoffset]=(uint32_t)new_dsdt; + rsdt_entries[i-dropoffset] = (uint32_t)new_dsdt; } continue; @@ -534,11 +491,11 @@ struct acpi_2_fadt *fadt, *fadt_mod; fadt=(struct acpi_2_fadt *)rsdt_entries[i]; - DBG("FADT found @%x, Length %d\n",fadt, fadt->Length); + DBG("\tFADT found @%x, Length %d\n",fadt, fadt->Length); if (!fadt || (uint32_t)fadt == 0xffffffff || fadt->Length>0x10000) { - DBG("FADT incorrect. Not modified\n"); + DBG("\tFADT incorrect. Not modified\n"); continue; } @@ -548,7 +505,7 @@ // Generate _CST SSDT if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod))) { - DBG("C-States generated\n"); + DBG("\tC-States generated.\n"); generate_cstates = false; // Generate SSDT only once! ssdt_count++; } @@ -556,7 +513,7 @@ // Generating _PSS SSDT if (generate_pstates && (new_ssdt[ssdt_count] = generate_pss_ssdt((void*)fadt_mod->DSDT))) { - DBG("P-States generated\n"); + DBG("\tP-States generated.\n"); generate_pstates = false; // Generate SSDT only once! ssdt_count++; } @@ -582,25 +539,25 @@ for (j=0; jChecksum); + DBG("\tRSDT: Original checksum %d, ", rsdt_mod->Checksum); rsdt_mod->Checksum=0; rsdt_mod->Checksum=256-checksum8(rsdt_mod,rsdt_mod->Length); - DBG("New checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod); + DBG("\tNew checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod); } else { rsdp_mod->RsdtAddress=0; - DBG("RSDT not found or RSDT incorrect\n"); + DBG("\tRSDT not found or RSDT incorrect\n"); } DBG("\n"); @@ -611,22 +568,22 @@ // FIXME: handle 64-bit address correctly xsdt=(struct acpi_2_xsdt*) ((uint32_t)rsdp->XsdtAddress); - DBG("XSDT @%x;%x, Length=%d\n", (uint32_t)(rsdp->XsdtAddress>>32),(uint32_t)rsdp->XsdtAddress, xsdt->Length); + DBG("\tXSDT @%x;%x, Length=%d\n", (uint32_t)(rsdp->XsdtAddress>>32),(uint32_t)rsdp->XsdtAddress, xsdt->Length); if (xsdt && (uint64_t)rsdp->XsdtAddress<0xffffffff && xsdt->Length<0x10000) { uint64_t *xsdt_entries; int xsdt_entries_num, i; - int dropoffset=0; + int dropoffset = 0; // mozo: using malloc cos I didn't found how to free already allocated kernel memory - xsdt_mod=(struct acpi_2_xsdt*)malloc(xsdt->Length); + xsdt_mod = (struct acpi_2_xsdt *)malloc(xsdt->Length); memcpy(xsdt_mod, xsdt, xsdt->Length); rsdp_mod->XsdtAddress = (uint32_t)xsdt_mod; xsdt_entries_num = (xsdt_mod->Length - sizeof(struct acpi_2_xsdt)) / 8; xsdt_entries = (uint64_t *)(xsdt_mod + 1); - for (i = 0;i < xsdt_entries_num;i++) + for (i = 0;i < xsdt_entries_num; i++) { char *table = (char *)((uint32_t)(xsdt_entries[i])); if (!table) @@ -637,21 +594,21 @@ if (drop_ssdt && tableSign(table, "SSDT")) { - DBG("dropped (OEM)\n"); + DBG("\tOEM SSDT tables was dropped\n"); dropoffset++; continue; } if (tableSign(table, "DSDT")) { - DBG("DSDT found\n"); + DBG("\tDSDT found\n"); if (new_dsdt) { xsdt_entries[i-dropoffset] = (uint32_t)new_dsdt; - DBG("custom table added\n"); + DBG("\tcustom table added.\n"); } - DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]); + DBG("\tTABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]); continue; } @@ -660,24 +617,24 @@ struct acpi_2_fadt *fadt, *fadt_mod; fadt=(struct acpi_2_fadt *)(uint32_t)xsdt_entries[i]; - DBG("FADT found @%x%x, Length %d\n",(uint32_t)(xsdt_entries[i]>>32),fadt, + DBG("\tFADT found @%x%x, Length %d\n",(uint32_t)(xsdt_entries[i]>>32),fadt, fadt->Length); if (!fadt || (uint64_t)xsdt_entries[i] >= 0xffffffff || fadt->Length>0x10000) { - DBG("FADT incorrect or after 4GB. Dropping XSDT\n"); + DBG("\tFADT incorrect or after 4GB. Dropping XSDT\n"); goto drop_xsdt; } fadt_mod = patch_fadt(fadt, new_dsdt); - xsdt_entries[i-dropoffset]=(uint32_t)fadt_mod; + xsdt_entries[i - dropoffset] = (uint32_t)fadt_mod; - // DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]); + // DBG("\tTABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]); // Generate _CST SSDT if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod))) { - DBG("C-States generated\n"); + DBG("\tC-States generated.\n"); generate_cstates = false; // Generate SSDT only once! ssdt_count++; } @@ -685,15 +642,21 @@ // Generating _PSS SSDT if (generate_pstates && (new_ssdt[ssdt_count] = generate_pss_ssdt((void*)fadt_mod->DSDT))) { - DBG("P-States generated\n"); + DBG("\tP-States generated.\n"); generate_pstates = false; // Generate SSDT only once! ssdt_count++; } + // Generating _TSS SSDT + /*if (generate_tstates && (new_ssdt[ssdt_count] = generate_tss_ssdt((void*)fadt_mod->DSDT))) + { + generate_tstates = false; // Generate SSDT only once! + ssdt_count++; + }*/ continue; } - DBG("copied (OEM)\n"); - // DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]); + DBG("\tcopied (OEM)\n"); + // DBG("\tTABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]); } // Allocate xsdt in Kernel memory area @@ -713,10 +676,10 @@ for (j=0; jXsdtAddress=0xffffffffffffffffLL; - verbose("XSDT not found or XSDT incorrect\n"); + verbose("\tXSDT not found or XSDT incorrect\n"); } } DBG("\n"); // Correct the checksum of RSDP - DBG("RSDP: Original checksum %d, ", rsdp_mod->Checksum); + DBG("\tRSDP: Original checksum %d, ", rsdp_mod->Checksum); rsdp_mod->Checksum=0; rsdp_mod->Checksum=256-checksum8(rsdp_mod,20); - DBG("New checksum %d\n", rsdp_mod->Checksum); + DBG("\tNew checksum %d\n", rsdp_mod->Checksum); if (version) { - DBG("RSDP: Original extended checksum %d, ", rsdp_mod->ExtendedChecksum); + DBG("\tRSDP: Original extended checksum %d, ", rsdp_mod->ExtendedChecksum); rsdp_mod->ExtendedChecksum=0; rsdp_mod->ExtendedChecksum=256-checksum8(rsdp_mod,rsdp_mod->Length); - DBG("New extended checksum %d\n", rsdp_mod->ExtendedChecksum); + DBG("\tNew extended checksum %d\n", rsdp_mod->ExtendedChecksum); } @@ -772,7 +735,7 @@ acpi10_p = (uint64_t)(uint32_t)rsdp_mod; addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI"); } - DBG("ACPI version %d patching finished\n\n", version+1); + DBG("\tACPI version %d patching finished\n\n", version + 1); } #if DEBUG_ACPI printf("Press a key to continue... (DEBUG_ACPI)\n"); Index: branches/zenith432/i386/libsaio/device_tree.h =================================================================== --- branches/zenith432/i386/libsaio/device_tree.h (revision 2804) +++ branches/zenith432/i386/libsaio/device_tree.h (revision 2805) @@ -31,7 +31,8 @@ //============================================================================== -typedef struct _Property { +typedef struct _Property +{ const char * name; uint32_t length; void * value; @@ -41,46 +42,33 @@ //============================================================================== -typedef struct _Node { +typedef struct _Node +{ struct _Property * properties; struct _Property * last_prop; struct _Node * children; struct _Node * next; } Node; +extern Property *DT__AddProperty(Node *node, const char *name, uint32_t length, void *value); -extern Property * -DT__AddProperty(Node *node, const char *name, uint32_t length, void *value); +extern Node *DT__AddChild(Node *parent, const char *name); -extern Node * -DT__AddChild(Node *parent, const char *name); +Node *DT__FindNode(const char *path, bool createIfMissing); -Node * -DT__FindNode(const char *path, bool createIfMissing); +extern void DT__FreeProperty(Property *prop); -extern void -DT__FreeProperty(Property *prop); +extern void DT__FreeNode(Node *node); -extern void -DT__FreeNode(Node *node); +extern char *DT__GetName(Node *node); -extern char * -DT__GetName(Node *node); +extern Property *DT__GetProperty(Node *node, const char *name); -extern Property * -DT__GetProperty(Node *node, const char *name); +void DT__Initialize(void); -void -DT__Initialize(void); - - // Free up memory used by in-memory representation of device tree. +extern void DT__Finalize(void); -extern void -DT__Finalize(void); +void DT__FlattenDeviceTree(void **result, uint32_t *length); -void -DT__FlattenDeviceTree(void **result, uint32_t *length); - - #endif /* __DEVICE_TREE_H */ Index: branches/zenith432/i386/libsaio/allocate.c =================================================================== --- branches/zenith432/i386/libsaio/allocate.c (revision 2804) +++ branches/zenith432/i386/libsaio/allocate.c (revision 2805) @@ -35,8 +35,7 @@ //============================================================================== -long -AllocateMemoryRange(char * rangeName, long start, long length, long type) +long AllocateMemoryRange(char * rangeName, long start, long length, long type) { char *nameBuf; uint32_t *buffer; @@ -67,8 +66,7 @@ //============================================================================== -long -AllocateKernelMemory(long inSize) +long AllocateKernelMemory(long inSize) { long addr; Index: branches/zenith432/i386/libsaio/bootargs.h =================================================================== --- branches/zenith432/i386/libsaio/bootargs.h (revision 2804) +++ branches/zenith432/i386/libsaio/bootargs.h (revision 2805) @@ -116,8 +116,8 @@ #define kBootArgsVersion 2 // Snow Leopard and older -#define kBootArgsPreLionRevision 6 -#define kBootArgsPreLionVersion 1 +#define kBootArgsLegacyVersion 1 +#define kBootArgsLegacyRevision 6 /* Snapshot constants of previous revisions that are supported */ #define kBootArgsVersion1 1 @@ -187,7 +187,7 @@ } boot_args; -typedef struct boot_args_pre_lion +typedef struct boot_args_legacy { uint16_t Revision; /* Revision of boot_args structure */ uint16_t Version; /* Version of boot_args structure */ @@ -220,6 +220,6 @@ uint64_t efiRuntimeServicesVirtualPageStart; /* virtual address of defragmented runtime pages */ uint32_t __reserved3[2]; -} boot_args_pre_lion; +} boot_args_legacy; #endif /* _PEXPERT_I386_BOOT_H */ Index: branches/zenith432/i386/libsaio/hfs_compare.c =================================================================== --- branches/zenith432/i386/libsaio/hfs_compare.c (revision 2804) +++ branches/zenith432/i386/libsaio/hfs_compare.c (revision 2805) @@ -18,13 +18,12 @@ * under the License. * * @APPLE_LICENSE_HEADER_END@ - */ -/* - * HFSCompare.c - Functions for working with and comparing HFS nams. * - * Copyright (c) 1999-2000 Apple Computer, Inc. + * HFSCompare.c - Functions for working with and comparing HFS nams. * - * DRI: Josh de Cesare + * Copyright (c) 1999-2000 Apple Computer, Inc. + * + * DRI: Josh de Cesare */ #include @@ -32,54 +31,72 @@ #if ! UNCOMPRESSED -static unsigned short * -UncompressStructure(struct compressed_block *bp, int count, int size) +static unsigned short *UncompressStructure(struct compressed_block *bp, int count, int size) { - unsigned short *out = malloc(size); - unsigned short *op = out; - unsigned short data; - int i, j; + int i, j; - for (i=0; icount) - { - stop("HFS+ Unicode tables are malformed\n"); - } - data = bp->data; - for (j=0; jcount; j++) { - *op++ = data; - if (bp->type == kTypeAscending) data++; - else if (bp->type == kTypeAscending256) data += 256; - } - } - return out; + unsigned short *out = malloc(size); + + if (out) + { + unsigned short *op = out; + unsigned short data; + + for (i = 0; i < count; i++, bp++) + { + // If this happens (it shouldn't) please fix size and/or double check that count really is + // the number of elements in the array. + // This was a very hard bug to find, so please leave this code here. + if(out + size <= op + bp->count) + { + stop("HFS+ Unicode tables are malformed\n"); + } + + data = bp->data; + + for (j = 0; j < bp->count; j++) + { + *op++ = data; + + if (bp->type == kTypeAscending) + { + data++; + } + else if (bp->type == kTypeAscending256) + { + data += 256; + } + } + } + + return out; + } + + return NULL; } -static void -InitCompareTables(void) +static void InitCompareTables(void) { - if (gCompareTable == 0) { - gCompareTable = UncompressStructure(gCompareTableCompressed, + if (gCompareTable == 0) + { + gCompareTable = UncompressStructure(gCompareTableCompressed, kCompareTableNBlocks, kCompareTableDataSize); - gLowerCaseTable = UncompressStructure(gLowerCaseTableCompressed, + gLowerCaseTable = UncompressStructure(gLowerCaseTableCompressed, kLowerCaseTableNBlocks, kLowerCaseTableDataSize); - } + } } #endif /* ! UNCOMPRESSED */ -//_______________________________________________________________________ // +// // Routine: FastRelString // // Output: returns -1 if str1 < str2 // returns 1 if str1 > str2 // return 0 if equal // -//_______________________________________________________________________ +// int32_t FastRelString(u_int8_t * str1, u_int8_t * str2) { @@ -94,9 +111,13 @@ length2 = *(str2++); if (length == length2) + { bestGuess = 0; + } else if (length < length2) + { bestGuess = -1; + } else { bestGuess = 1; @@ -118,10 +139,14 @@ bSortWord = gCompareTable[bChar]; if (aSortWord > bSortWord) + { return 1; + } if (aSortWord < bSortWord) + { return -1; + } } /* @@ -192,8 +217,7 @@ // return 1; // -int32_t FastUnicodeCompare( u_int16_t * str1, register u_int32_t length1, - u_int16_t * str2, register u_int32_t length2, int byte_order ) +int32_t FastUnicodeCompare( u_int16_t * str1, register u_int32_t length1, u_int16_t * str2, register u_int32_t length2, int byte_order ) { register u_int16_t c1,c2; register u_int16_t temp; @@ -202,44 +226,66 @@ InitCompareTables(); #endif - while (1) { + while (1) + { /* Set default values for c1, c2 in case there are no more valid chars */ c1 = 0; c2 = 0; /* Find next non-ignorable char from str1, or zero if no more */ - while (length1 && c1 == 0) { + while (length1 && c1 == 0) + { if (byte_order == OSBigEndian) + { c1 = SWAP_BE16(*(str1++)); + } else + { c1 = SWAP_LE16(*(str1++)); + } + --length1; if ((temp = gLowerCaseTable[c1>>8]) != 0) // is there a subtable for this upper byte? c1 = gLowerCaseTable[temp + (c1 & 0x00FF)]; // yes, so fold the char } /* Find next non-ignorable char from str2, or zero if no more */ - while (length2 && c2 == 0) { + while (length2 && c2 == 0) + { if (byte_order == OSBigEndian) + { c2 = SWAP_BE16(*(str2++)); + } else + { c2 = SWAP_LE16(*(str2++)); + } --length2; - if ((temp = gLowerCaseTable[c2>>8]) != 0) // is there a subtable for this upper byte? - c2 = gLowerCaseTable[temp + (c2 & 0x00FF)]; // yes, so fold the char + if ((temp = gLowerCaseTable[c2>>8]) != 0) // Is there a subtable for this upper byte? + { + c2 = gLowerCaseTable[temp + (c2 & 0x00FF)]; // Yes, so fold the char + } } - if (c1 != c2) /* found a difference, so stop looping */ + if (c1 != c2) /* Found a difference, so stop looping */ + { break; - - if (c1 == 0) /* did we reach the end of both strings at the same time? */ - return 0; /* yes, so strings are equal */ + } + + if (c1 == 0) /* Did we reach the end of both strings at the same time? */ + { + return 0; /* Yes, so strings are equal */ + } } if (c1 < c2) + { return -1; + } else + { return 1; + } } @@ -247,36 +293,44 @@ // BinaryUnicodeCompare - Compare two Unicode strings; produce a relative ordering // Compared using a 16-bit binary comparison (no case folding) // -int32_t BinaryUnicodeCompare (u_int16_t * str1, u_int32_t length1, - u_int16_t * str2, u_int32_t length2) +int32_t BinaryUnicodeCompare(u_int16_t * str1, u_int32_t length1, u_int16_t * str2, u_int32_t length2) { - register u_int16_t c1, c2; - int32_t bestGuess; - u_int32_t length; + register u_int16_t c1, c2; + int32_t bestGuess = 0; + u_int32_t length; - bestGuess = 0; + if (length1 < length2) + { + length = length1; + --bestGuess; + } + else if (length1 > length2) + { + length = length2; + ++bestGuess; + } + else + { + length = length1; + } - if (length1 < length2) { - length = length1; - --bestGuess; - } else if (length1 > length2) { - length = length2; - ++bestGuess; - } else { - length = length1; - } + while (length--) + { + c1 = *(str1++); + c2 = *(str2++); - while (length--) { - c1 = *(str1++); - c2 = *(str2++); + if (c1 > c2) + { + return (1); + } - if (c1 > c2) - return (1); - if (c1 < c2) - return (-1); - } + if (c1 < c2) + { + return (-1); + } + } - return (bestGuess); + return (bestGuess); } @@ -287,7 +341,7 @@ * requires a maximum of three 3 bytes per UCS-2 character. Only the * shortest encoding required to represent the significant UCS-2 bits * is legal. - * + * * UTF-8 Multibyte Codes * * Bytes Bits UCS-2 Min UCS-2 Max UTF-8 Byte Sequence (binary) @@ -307,39 +361,59 @@ * bufsize is the size of the output buffer in bytes */ void -utf_encodestr( const u_int16_t * ucsp, int ucslen, - u_int8_t * utf8p, u_int32_t bufsize, int byte_order ) +utf_encodestr( const u_int16_t * ucsp, int ucslen, u_int8_t * utf8p, u_int32_t bufsize, int byte_order ) { u_int8_t *bufend; u_int16_t ucs_ch; bufend = utf8p + bufsize; - while (ucslen-- > 0) { + while (ucslen-- > 0) + { if (byte_order == OSBigEndian) + { ucs_ch = SWAP_BE16(*ucsp++); - else + } + else + { ucs_ch = SWAP_LE16(*ucsp++); + } - if (ucs_ch < 0x0080) { + if (ucs_ch < 0x0080) + { if (utf8p >= bufend) + { break; + } + if (ucs_ch == '\0') - continue; /* skip over embedded NULLs */ + { + continue; /* Skip over embedded NULLs */ + } + *utf8p++ = ucs_ch; - } else if (ucs_ch < 0x800) { + } + else if (ucs_ch < 0x800) + { if ((utf8p + 1) >= bufend) + { break; - *utf8p++ = (ucs_ch >> 6) | 0xc0; - *utf8p++ = (ucs_ch & 0x3f) | 0x80; + } - } else { + *utf8p++ = ((ucs_ch >> 6) | 0xc0); + *utf8p++ = ((ucs_ch & 0x3f) | 0x80); + } + else + { if ((utf8p + 2) >= bufend) + { break; - *utf8p++ = (ucs_ch >> 12) | 0xe0; - *utf8p++ = ((ucs_ch >> 6) & 0x3f) | 0x80; - *utf8p++ = ((ucs_ch) & 0x3f) | 0x80; + } + + *utf8p++ = ((ucs_ch >> 12) | 0xe0); + *utf8p++ = (((ucs_ch >> 6) & 0x3f) | 0x80); + *utf8p++ = ((ucs_ch & 0x3f) | 0x80); } } @@ -364,58 +438,79 @@ bufstart = ucsp; bufend = (u_int16_t *)((u_int8_t *)ucsp + bufsize); - while ((byte = *utf8p++) != '\0') { + while ((byte = *utf8p++) != '\0') + { if (ucsp >= bufend) + { break; + } - /* check for ascii */ - if (byte < 0x80) { + /* Check for ASCII */ + if (byte < 0x80) + { ucs_ch = byte; - + if (byte_order == OSBigEndian) - *ucsp++ = SWAP_BE16(ucs_ch); - else - *ucsp++ = SWAP_LE16(ucs_ch); - + { + *ucsp++ = SWAP_BE16(ucs_ch); + } + else + { + *ucsp++ = SWAP_LE16(ucs_ch); + } + continue; } - switch (byte & 0xf0) { - /* 2 byte sequence*/ - case 0xc0: - case 0xd0: - /* extract bits 6 - 10 from first byte */ - ucs_ch = (byte & 0x1F) << 6; - break; - /* 3 byte sequence*/ - case 0xe0: - /* extract bits 12 - 15 from first byte */ - ucs_ch = (byte & 0x0F) << 6; + switch (byte & 0xf0) + { + /* 2 byte sequence */ + case 0xc0: + case 0xd0: /* Extract bits 6 - 10 from first byte */ + ucs_ch = ((byte & 0x1F) << 6); + break; + /* 3 byte sequence */ + case 0xe0: + /* Extract bits 12 - 15 from first byte */ + ucs_ch = ((byte & 0x0F) << 6); - /* extract bits 6 - 11 from second byte */ - if (((byte = *utf8p++) & 0xc0) != 0x80) - goto stop; + /* Extract bits 6 - 11 from second byte */ + if (((byte = *utf8p++) & 0xc0) != 0x80) + { + goto stop; + } - ucs_ch += (byte & 0x3F); - ucs_ch <<= 6; - break; - default: - goto stop; + ucs_ch += (byte & 0x3F); + ucs_ch <<= 6; + break; + default: + goto stop; } - /* extract bits 0 - 5 from final byte */ + /* Extract bits 0 - 5 from final byte */ if (((byte = *utf8p++) & 0xc0) != 0x80) + { goto stop; - ucs_ch += (byte & 0x3F); + } + ucs_ch += (byte & 0x3F); + if (byte_order == OSBigEndian) - *ucsp++ = SWAP_BE16(ucs_ch); - else - *ucsp++ = SWAP_LE16(ucs_ch); + { + *ucsp++ = SWAP_BE16(ucs_ch); + } + else + { + *ucsp++ = SWAP_LE16(ucs_ch); + } } stop: - if (byte_order == OSBigEndian) - *ucslen = SWAP_BE16(ucsp - bufstart); - else - *ucslen = SWAP_LE16(ucsp - bufstart); + if (byte_order == OSBigEndian) + { + *ucslen = SWAP_BE16(ucsp - bufstart); + } + else + { + *ucslen = SWAP_LE16(ucsp - bufstart); + } } Index: branches/zenith432/i386/libsaio/spd.c =================================================================== --- branches/zenith432/i386/libsaio/spd.c (revision 2804) +++ branches/zenith432/i386/libsaio/spd.c (revision 2805) @@ -16,13 +16,13 @@ #include "memvendors.h" #ifndef DEBUG_SPD -#define DEBUG_SPD 0 + #define DEBUG_SPD 0 #endif #if DEBUG_SPD -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) msglog(x) + #define DBG(x...) msglog(x) #endif static const char *spd_memory_types[] = @@ -33,7 +33,7 @@ "PIPE NIBBLE", /* 03h PIPELINE NIBBLE */ "SDRAM", /* 04h SDRAM */ "ROM", /* 05h MULTIPLEXED ROM */ - "DDR SGRAM" /* 06h SGRAM DDR */ + "DDR SGRAM", /* 06h SGRAM DDR */ "DDR SDRAM", /* 07h SDRAM DDR */ "DDR2 SDRAM", /* 08h SDRAM DDR 2 */ "DDR2 SDRAM FB-DIMM", /* 09h Undefined */ @@ -56,7 +56,8 @@ SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */ UNKNOWN_MEM_TYPE, /* 09h Undefined */ UNKNOWN_MEM_TYPE, /* 0Ah Undefined */ - SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */ + SMB_MEM_TYPE_DDR3, /* 0Bh SDRAM DDR 3 */ + SMB_MEM_TYPE_DDR4 /* 0Ch SDRAM DDR 4 */ }; #define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t)) @@ -137,12 +138,12 @@ // Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, // have different formats, always return a valid ptr. -const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num) +const char *getVendorName(RamSlotInfo_t *slot, uint32_t base, int slot_num) { uint8_t bank = 0; uint8_t code = 0; int i = 0; - uint8_t * spd = (uint8_t *) slot->spd; + uint8_t *spd = (uint8_t *) slot->spd; if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3 { @@ -400,9 +401,10 @@ case 99: freq++; break; } slot->Frequency = freq; + DBG("RAM speed %dMHz \n", freq); } - verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", + verbose("\tSlot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n\t\tPartNo=%s SerialNo=%s\n", i, (int)slot->Type, slot->ModuleSize, @@ -411,7 +413,7 @@ slot->Vendor, slot->PartNo, slot->SerialNo); - slot->InUse = true; + slot->InUse = true; } // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so: @@ -425,35 +427,40 @@ static struct smbus_controllers_t smbus_controllers[] = { - {0x8086, 0x1C22, "P67", read_smb_intel }, // Z68, Q67 - {0x8086, 0x1D22, "X79", read_smb_intel }, - {0x8086, 0x1D70, "X79", read_smb_intel }, - {0x8086, 0x1D71, "X79", read_smb_intel }, - {0x8086, 0x1D72, "C608", read_smb_intel }, - {0x8086, 0x1E22, "Z77", read_smb_intel }, // H77, Q77 - {0x8086, 0x2330, "DH89xxCC", read_smb_intel }, - {0x8086, 0x2413, "82801AA", read_smb_intel }, - {0x8086, 0x2423, "BAM", read_smb_intel }, - {0x8086, 0x2443, "BAM", read_smb_intel }, - {0x8086, 0x2483, "CAM", read_smb_intel }, - {0x8086, 0x24C3, "ICH4", read_smb_intel }, - {0x8086, 0x24D3, "ICH5", read_smb_intel }, - {0x8086, 0x25A4, "6300ESB", read_smb_intel }, - {0x8086, 0x266A, "ICH6", read_smb_intel }, - {0x8086, 0x269B, "ESB", read_smb_intel }, - {0x8086, 0x27DA, "ICH7", read_smb_intel }, - {0x8086, 0x283E, "ICH8", read_smb_intel }, - {0x8086, 0x2930, "ICH9", read_smb_intel }, - {0x8086, 0x3A30, "ICH10", read_smb_intel }, - {0x8086, 0x3A60, "ICH10", read_smb_intel }, - {0x8086, 0x3B30, "P55", read_smb_intel }, - {0x8086, 0x5032, "EP80579", read_smb_intel }, - {0x8086, 0x8119, "US15W", read_smb_intel }, - {0x8086, 0x8C22, "HSW", read_smb_intel }, // Z87, H87, Q87, H81 - {0x8086, 0x8CA2, "Z97/H97", read_smb_intel }, // new - {0x8086, 0x8D22, "X99", read_smb_intel }, // new - {0x8086, 0x9C22, "HSW-ULT", read_smb_intel } + // Intel + {0x8086, 0x1C22, "P67", read_smb_intel }, + {0x8086, 0x1D22, "X79", read_smb_intel }, + {0x8086, 0x1D70, "X79", read_smb_intel }, + {0x8086, 0x1D71, "X79", read_smb_intel }, + {0x8086, 0x1D72, "C608", read_smb_intel }, + {0x8086, 0x1E22, "Z77", read_smb_intel }, + {0x8086, 0x2330, "DH89xxCC", read_smb_intel }, + {0x8086, 0x2413, "82801AA", read_smb_intel }, + {0x8086, 0x2423, "BAM", read_smb_intel }, + {0x8086, 0x2443, "BAM", read_smb_intel }, + {0x8086, 0x2483, "CAM", read_smb_intel }, + {0x8086, 0x24C3, "ICH4", read_smb_intel }, + {0x8086, 0x24D3, "ICH5", read_smb_intel }, + {0x8086, 0x25A4, "6300ESB", read_smb_intel }, + {0x8086, 0x266A, "ICH6", read_smb_intel }, + {0x8086, 0x269B, "ESB", read_smb_intel }, + {0x8086, 0x27DA, "ICH7", read_smb_intel }, + {0x8086, 0x283E, "ICH8", read_smb_intel }, + {0x8086, 0x2930, "ICH9", read_smb_intel }, + {0x8086, 0x3A30, "ICH10", read_smb_intel }, + {0x8086, 0x3A60, "ICH10", read_smb_intel }, + {0x8086, 0x3B30, "P55", read_smb_intel }, + {0x8086, 0x5032, "EP80579", read_smb_intel }, + {0x8086, 0x8119, "US15W", read_smb_intel }, + {0x8086, 0x8C22, "HSW", read_smb_intel }, + {0x8086, 0x8CA2, "Z97/H97", read_smb_intel }, + {0x8086, 0x8D22, "X99", read_smb_intel }, + {0x8086, 0x9C22, "HSW-ULT", read_smb_intel } + // AMD +// {0x1002, 0x4385, "AMD SB600/700", ... }, +// {0x1022, 0x780B, "AMD SB800/900", ... } + }; // initial call : pci_dt = root_pci_dev; Index: branches/zenith432/i386/libsaio/libsaio.h =================================================================== --- branches/zenith432/i386/libsaio/libsaio.h (revision 2804) +++ branches/zenith432/i386/libsaio/libsaio.h (revision 2805) @@ -21,7 +21,6 @@ * * @APPLE_LICENSE_HEADER_END@ */ -/* libsaio.h */ #ifndef __LIBSAIO_LIBSAIO_H #define __LIBSAIO_LIBSAIO_H Index: branches/zenith432/i386/libsaio/networking.c =================================================================== --- branches/zenith432/i386/libsaio/networking.c (revision 0) +++ branches/zenith432/i386/libsaio/networking.c (revision 2805) @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2009 Evan Lojewski. All rights reserved. + * + * Merge into file from module compcept by ErmaC and Marchrius + * + */ + +#include "boot.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +//#include "convert.h" +#include "device_inject.h" +#include "networking.h" + +#define STRINGIFY(x) #x +#define TOSTRING(x) STRINGIFY(x) + +#define HEADER __FILE__ " [" TOSTRING(__LINE__) "]: " + +#ifndef DEBUG_ETHERNET + #define DEBUG_ETHERNET 0 +#endif + +#if DEBUG_ETHERNET + #define DBG(x...) printf(x) +#else + #define DBG(x...) +#endif + +#ifndef DEBUG_WLAN + #define DEBUG_WLAN 0 +#endif + +#if DEBUG_WLAN + #define DBG(x...) printf(x) +#else + #define DBG(x...) +#endif + +uint32_t builtin_set = 0; +uint8_t builtin = 0; +extern uint32_t location_number; + +static network_device known_ethernet_cards[] = +{ + // Realtek + { PCI_VENDOR_ID_REALTEK, 0x8129, "8129 Gigabit Ethernet" }, + { PCI_VENDOR_ID_REALTEK, 0x8136, "RTL8101E/RTL8102E PCI-E Fast Ethernet Controller" }, + { PCI_VENDOR_ID_REALTEK, 0x8139, "RTL8139/810x Family Fast Ethernet" }, + { PCI_VENDOR_ID_REALTEK, 0x8167, "8169/8110 Gigabit Ethernet" }, + { PCI_VENDOR_ID_REALTEK, 0x8168, "RTL8111/8168 PCI-E Gigabit Ethernet" }, + { PCI_VENDOR_ID_REALTEK, 0x8169, "8169/8110 Gigabit Ethernet" }, + + { 0x1113, 0x1211, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x1500, 0x1360, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x4033, 0x1360, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x1186, 0x1300, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x1186, 0x1340, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x13d1, 0xab06, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x1259, 0xa117, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x1259, 0xa11e, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x14ea, 0xab06, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x14ea, 0xab07, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x11db, 0x1234, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x1432, 0x9130, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x02ac, 0x1012, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x018a, 0x0106, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x126c, 0x1211, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x1743, 0x8139, "Realtek RTL8139 Family Fast Ethernet" }, + { 0x021b, 0x8139, "Realtek RTL8139 Family Fast Ethernet" }, + + // Marvell + { PCI_VENDOR_ID_MARVELL, 0x4320, "Yukon Gigabit Adapter 88E8001 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4340, "Yukon Gigabit Adapter 88E8021 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4341, "Yukon Gigabit Adapter 88E8022 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4342, "Yukon Gigabit Adapter 88E8061 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4343, "Yukon Gigabit Adapter 88E8062 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4344, "Yukon Gigabit Adapter 88E8021 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4345, "Yukon Gigabit Adapter 88E8022 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4346, "Yukon Gigabit Adapter 88E8061 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4347, "Yukon Gigabit Adapter 88E8062 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4350, "Yukon Gigabit Adapter 88E8035 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4351, "Yukon Gigabit Adapter 88E8036 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4352, "Yukon Gigabit Adapter 88E8038 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4353, "Yukon Gigabit Adapter 88E8039 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4354, "Yukon Gigabit Adapter 88E8040 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4355, "Yukon Gigabit Adapter 88E8040T Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4356, "Yukon Gigabit Adapter 88EC033 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4357, "Yukon Gigabit Adapter 88E8042 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x435A, "Yukon Gigabit Adapter 88E8048 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4360, "Yukon Gigabit Adapter 88E8052 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4361, "Yukon Gigabit Adapter 88E8050 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4362, "Yukon Gigabit Adapter 88E8053 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4363, "Yukon Gigabit Adapter 88E8055 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4364, "Yukon Gigabit Adapter 88E8056 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4365, "Yukon Gigabit Adapter 8E8070 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4366, "Yukon Gigabit Adapter 88EC036 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4367, "Yukon Gigabit Adapter 88EC032 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4368, "Yukon Gigabit Adapter 88EC034 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4369, "Yukon Gigabit Adapter 88EC042 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x436A, "Yukon Gigabit Adapter 88E8058 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x436B, "Yukon Gigabit Adapter 88E8071 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x436C, "Yukon Gigabit Adapter 88E8072 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x436D, "Yukon Gigabit Adapter 88E8055 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4370, "Yukon Gigabit Adapter 88E8075 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4380, "Yukon Gigabit Adapter 88E8057 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4381, "Yukon Gigabit Adapter 88E8059 Singleport Copper SA" }, + { PCI_VENDOR_ID_MARVELL, 0x4382, "Yukon Gigabit Adapter 88E8079 Singleport Copper SA" }, +// { PCI_VENDOR_ID_MARVELL, 0x5005, "Belkin F5D5005 Gigabit Desktop Network PCI Card" }, + + // Broadcom + { PCI_VENDOR_ID_BROADCOM, 0x1600, "BCM5752 Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x1655, "BCM5717 Gigabit Ethernet PCIe" }, + { PCI_VENDOR_ID_BROADCOM, 0x1656, "BCM5718 Gigabit Ethernet PCIe" }, + { PCI_VENDOR_ID_BROADCOM, 0x1657, "BCM5719 Gigabit Ethernet PCIe" }, + { PCI_VENDOR_ID_BROADCOM, 0x1659, "BCM5721 Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x165A, "BCM5722 Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x166A, "BCM5780 Gigabit Ethernet" }, + { PCI_VENDOR_ID_BROADCOM, 0x1672, "BCM5754M Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x1673, "BCM5755M Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x167A, "BCM5754 Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x167B, "BCM5755 Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x1684, "BCM5764M Gigabit Ethernet PCIe" }, + { PCI_VENDOR_ID_BROADCOM, 0x1691, "BCM57788 Gigabit Ethernet PCIe" }, + { PCI_VENDOR_ID_BROADCOM, 0x1693, "BCM5787M Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x169B, "BCM5787 Gigabit Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x16B4, "BCM57765 Gigabit Ethernet PCIe" }, + { PCI_VENDOR_ID_BROADCOM, 0x16B5, "BCM57785 Gigabit Ethernet PCIe" }, + { PCI_VENDOR_ID_BROADCOM, 0x1712, "BCM5906 Fast Ethernet PCI Express" }, + { PCI_VENDOR_ID_BROADCOM, 0x1713, "BCM5906M Fast Ethernet PCI Express" }, + + // JMicron + { PCI_VENDOR_ID_JMICRON, 0x0250, "JMC250 PCI Express Gigabit Ethernet Controller" }, + { PCI_VENDOR_ID_JMICRON, 0x0260, "JMC260 PCI Express Gigabit Ethernet Controller" }, + + // Intel + { PCI_VENDOR_ID_INTEL, 0x1000, "82542" }, + { PCI_VENDOR_ID_INTEL, 0x1029, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1030, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1031, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1032, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1033, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1034, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1038, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1039, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x103A, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x103B, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x103C, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x103D, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x103E, "8255x" }, + { PCI_VENDOR_ID_INTEL, 0x1049, "82566MM" }, + { PCI_VENDOR_ID_INTEL, 0x104A, "82566DM" }, + { PCI_VENDOR_ID_INTEL, 0x104B, "82574L" }, + { PCI_VENDOR_ID_INTEL, 0x104C, "82562V" }, + { PCI_VENDOR_ID_INTEL, 0x104D, "82566MC" }, + { PCI_VENDOR_ID_INTEL, 0x1050, "82562EZ" }, + { PCI_VENDOR_ID_INTEL, 0x1051, "82801EB/ER" }, + { PCI_VENDOR_ID_INTEL, 0x1052, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1053, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1054, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1055, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1056, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1057, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1059, "82551QM" }, +// { PCI_VENDOR_ID_INTEL, 0x105b "82546GB" }, +// { PCI_VENDOR_ID_INTEL, 0x105E, "82546GB" }, +// { PCI_VENDOR_ID_INTEL, 0x105F, "82571EB" }, + { PCI_VENDOR_ID_INTEL, 0x1060, "82571EB" }, + { PCI_VENDOR_ID_INTEL, 0x1064, "82562ET/EZ/GT/GZ" }, + { PCI_VENDOR_ID_INTEL, 0x1065, "82562ET/EZ/GT/GZ" }, + { PCI_VENDOR_ID_INTEL, 0x1066, "82562 EM/EX/GX" }, + { PCI_VENDOR_ID_INTEL, 0x1067, "82562 EM/EX/GX" }, + { PCI_VENDOR_ID_INTEL, 0x1068, "82562ET/EZ/GT/GZ" }, + { PCI_VENDOR_ID_INTEL, 0x1069, "82562EM/EX/GX" }, + { PCI_VENDOR_ID_INTEL, 0x106A, "82562G" }, + { PCI_VENDOR_ID_INTEL, 0x106B, "82562G" }, + { PCI_VENDOR_ID_INTEL, 0x1075, "82547GI" }, + { PCI_VENDOR_ID_INTEL, 0x1076, "82541GI" }, + { PCI_VENDOR_ID_INTEL, 0x1077, "82541GI" }, + { PCI_VENDOR_ID_INTEL, 0x1078, "82541ER" }, + { PCI_VENDOR_ID_INTEL, 0x1079, "82546GB" }, + { PCI_VENDOR_ID_INTEL, 0x107a, "82546GB" }, + { PCI_VENDOR_ID_INTEL, 0x107b, "82546GB" }, + { PCI_VENDOR_ID_INTEL, 0x107c, "82541PI" }, +// { PCI_VENDOR_ID_INTEL, 0x107D, "82572EI" }, +// { PCI_VENDOR_ID_INTEL, 0x107E, "82572EI" }, +// { PCI_VENDOR_ID_INTEL, 0x107F, "82572EI Gigabit Ethernet Controller" }, +// { PCI_VENDOR_ID_INTEL, 0x108a, "82546GB Gigabit Ethernet Controller" }, +// { PCI_VENDOR_ID_INTEL, 0x108B, "82573V Gigabit Ethernet Controller (Copper)" }, +// { PCI_VENDOR_ID_INTEL, 0x108C, "82573E Gigabit Ethernet Controller (Copper)" }, + { PCI_VENDOR_ID_INTEL, 0x1091, "PRO/100 VM Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1092, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1093, "PRO/100 VM Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1094, "PRO/100 VE Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1095, "PRO/100 VE Network Connection" }, +// { PCI_VENDOR_ID_INTEL, 0x1096, "80003ES2LAN Gigabit Ethernet Controller (Copper)" }, +// { PCI_VENDOR_ID_INTEL, 0x1098, "80003ES2LAN Gigabit Ethernet Controller (Serdes)" }, +// { PCI_VENDOR_ID_INTEL, 0x109A, "82573L Gigabit Ethernet Controller" }, +// { PCI_VENDOR_ID_INTEL, 0x10A4, "82571EB Gigabit Ethernet Controller" }, +// { PCI_VENDOR_ID_INTEL, 0x10A5, "82571EB Gigabit Ethernet Controller (Fiber)" }, +// { PCI_VENDOR_ID_INTEL, 0x10BA, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10BC, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10B9, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10BB, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10BD, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10BF, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10C0, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10C2, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10C3, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10C4, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10C5, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10CB, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10CC, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10CD, "Intel " }, + { PCI_VENDOR_ID_INTEL, 0x10CE, "82567V-2 Gigabit Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x10D3, "82574L Gigabit Network Connection" }, +// { PCI_VENDOR_ID_INTEL, 0x10D5, "Intel " }, + { PCI_VENDOR_ID_INTEL, 0x10d6, "82575GB Gigabit Network Connection" }, +// { PCI_VENDOR_ID_INTEL, 0x10D9, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10DA, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10DE, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10DF, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10E5, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10EA, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10EB, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10EF, "Intel " }, +// { PCI_VENDOR_ID_INTEL, 0x10F5, "Intel " }, + { PCI_VENDOR_ID_INTEL, 0x10F6, "82574L" }, + { PCI_VENDOR_ID_INTEL, 0x10F0, "82578DC Gigabit Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x10FE, "82552 10/100 Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1209, "8255xER/82551IT Fast Ethernet Controller" }, + { PCI_VENDOR_ID_INTEL, 0x1227, "82865 EtherExpress PRO/100A" }, + { PCI_VENDOR_ID_INTEL, 0x1228, "82556 EtherExpress PRO/100 Smart" }, + { PCI_VENDOR_ID_INTEL, 0x1229, "82557/8/9/0/1 Ethernet Pro 100" }, +// { PCI_VENDOR_ID_INTEL, 0x1501, "82567V-3 Gigabit Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1502, "82579LM Gigabit Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x1503, "82579V Gigabit Network Controller" }, +// { PCI_VENDOR_ID_INTEL, 0x150C, "82583V Gigabit Network Connection" }, +// { PCI_VENDOR_ID_INTEL, 0x1525, "82567V-4 Gigabit Network Connection" }, + { PCI_VENDOR_ID_INTEL, 0x153A, "Ethernet Connection I217-LM" }, + { PCI_VENDOR_ID_INTEL, 0x153B, "Ethernet Connection I217-V" }, + { PCI_VENDOR_ID_INTEL, 0x1559, "Ethernet Connection I218-V" }, + { PCI_VENDOR_ID_INTEL, 0x155A, "Ethernet Connection I218-LM" }, + { PCI_VENDOR_ID_INTEL, 0x15A0, "Ethernet Connection (2) I218-LM" }, + { PCI_VENDOR_ID_INTEL, 0x15A1, "Ethernet Connection (2) I218-V" }, + { PCI_VENDOR_ID_INTEL, 0x15A2, "Ethernet Connection (3) I218-LM" }, + { PCI_VENDOR_ID_INTEL, 0x15A3, "Ethernet Connection (3) I218-V" }, + { PCI_VENDOR_ID_INTEL, 0x2449, "82801BA/BAM/CA/CAM Ethernet Controller" }, + { PCI_VENDOR_ID_INTEL, 0x2459, "82801E Ethernet Controller" }, + { PCI_VENDOR_ID_INTEL, 0x245D, "82801E Ethernet Controller" }, + { PCI_VENDOR_ID_INTEL, 0x27DC, "NM10/ICH7 Family LAN Controller" }, +// { PCI_VENDOR_ID_INTEL, 0x294C, "82566DC-2 Gigabit Network Connection" }, + +// Atheros (Qualcomm) + { PCI_VENDOR_ID_QUALCOMM, 0x1026, "AR8121/AR8113/AR8114 Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1062, "AR8132 Fast Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1063, "AR8131 Gigabit Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1066, "AR8121/AR8113/AR8114 Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1067, "L1c Gigabit Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1073, "AR8151 v1.0 Gigabit 1000" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1083, "GbE LAN chip (10/100/1000 Mbit)" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1090, "AR8162 Fast Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x1091, "AR8161 Gigabit Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x10a0, "QCA8172 Fast Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x10a1, "QCA8171 Gigabit Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x2048, "L2 Fast Ethernet" }, + { PCI_VENDOR_ID_QUALCOMM, 0x2060, "AR8152 v1.1 Fast 10/100" }, + { PCI_VENDOR_ID_QUALCOMM, 0x2062, "AR8152 v2.0 Fast 10/100" } +}; +#define ETH_DEVICES_LEN (sizeof(known_ethernet_cards) / sizeof(known_ethernet_cards[0])) + +static network_device known_wifi_cards[] = +{ + // Broadcom + {PCI_VENDOR_ID_BROADCOM, 0x4312, "BCM4311 802.11a/b/g"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4313, "BCM4311 802.11a" }, + {PCI_VENDOR_ID_BROADCOM, 0x4315, "BCM4312 802.11b/g Wireless LAN Controller"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4318, "BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller"}, + {PCI_VENDOR_ID_BROADCOM, 0x4319, "BCM4318 [AirForce 54g] 802.11a/b/g PCI Express Transceiver"}, + {PCI_VENDOR_ID_BROADCOM, 0x4320, "BCM4306 802.11b/g Wireless LAN Controller"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4321, "BCM4321 802.11a Wireless Network Controller"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4322, "BCM4322 802.11bgn Wireless Network Controller"}, + {PCI_VENDOR_ID_BROADCOM, 0x4324, "BCM4309 802.11abg Wireless Network Controller"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4325, "BCM4306 802.11bg Wireless Network Controller"}, + {PCI_VENDOR_ID_BROADCOM, 0x4328, "BCM4321 802.11a/b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4329, "BCM4321 802.11b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x432a, "BCM4321 802.11an Wireless Network Controller"}, + {PCI_VENDOR_ID_BROADCOM, 0x432b, "BCM4322 802.11a/b/g/n Wireless LAN Controller"}, + {PCI_VENDOR_ID_BROADCOM, 0x432c, "BCM4322 802.11b/g/n"}, + {PCI_VENDOR_ID_BROADCOM, 0x432d, "BCM4322 802.11an Wireless Network Controller"}, + {PCI_VENDOR_ID_BROADCOM, 0x4331, "BCM4331 802.11a/b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4350, "BCM43222 Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4351, "BCM43222 802.11abgn Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4353, "BCM43224 802.11a/b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4357, "BCM43225 802.11b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4358, "BCM43227 802.11b/g/n"}, + {PCI_VENDOR_ID_BROADCOM, 0x4359, "BCM43228 802.11a/b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x4360, "BCM4360 802.11ac Wireless Network Adapter"}, + {PCI_VENDOR_ID_BROADCOM, 0x4365, "BCM43142 802.11b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43a0, "BCM4360 802.11ac Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43a1, "BCM4360 802.11ac Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43a2, "BCM4360 802.11ac Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43a9, "BCM43217 802.11b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43aa, "BCM43131 802.11b/g/n"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43b1, "BCM4352 802.11ac Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43ba, "BCM43602 802.11ac Wireless LAN SoC"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43bb, "BCM43602 802.11ac Wireless LAN SoC"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43bc, "BCM43602 802.11ac Wireless LAN SoC"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43d3, "BCM43567 802.11ac Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43d9, "BCM43570 802.11ac Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43df, "BCM4354 802.11ac Wireless LAN SoC"}, +// {PCI_VENDOR_ID_BROADCOM, 0x43ec, "BCM4356 802.11ac Wireless Network Adapter"}, +// {PCI_VENDOR_ID_BROADCOM, 0xa8d8, "BCM43224/5 Wireless Network Adapter"}, + + // Atheros + {PCI_VENDOR_ID_ATHEROS, 0x0020, "AR5513 802.11abg Wireless NIC"}, + {PCI_VENDOR_ID_ATHEROS, 0x0023, "AR5416 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0024, "AR5418 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0027, "AR9160 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0029, "AR922X Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x002A, "AR928X Wireless Network Adapter"}, // "pci168c,2a" + {PCI_VENDOR_ID_ATHEROS, 0x002B, "AR9285 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x002C, "AR2427 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x002D, "AR9227 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x002E, "AR9287 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0030, "AR93xx Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0032, "AR9485 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0033, "AR9580 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0034, "AR9462 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0036, "AR9565 Wireless Network Adapter"}, + {PCI_VENDOR_ID_ATHEROS, 0x0037, "AR9485 Wireless Network Adapter"} +}; +#define WLAN_DEVICES_LEN (sizeof(known_wifi_cards) / sizeof(known_wifi_cards[0])) + +char *get_ethernet_model(uint32_t vendor_id, uint32_t device_id) +{ + static char desc[128]; + + const char *name_format = NULL; + int i; + + /* Get format for vendor ID */ + switch ( vendor_id ) + { + case PCI_VENDOR_ID_REALTEK: + name_format = "Realteck %s"; break; + + case PCI_VENDOR_ID_MARVELL: + name_format = "Marvell %s"; break; + + case PCI_VENDOR_ID_JMICRON: + name_format = "JMicron %s"; break; + + case PCI_VENDOR_ID_ATHEROS: + case PCI_VENDOR_ID_QUALCOMM: + name_format = "Atheros %s"; break; + + case PCI_VENDOR_ID_BROADCOM: + name_format = "Broadcom %s"; break; + + case PCI_VENDOR_ID_INTEL: + name_format = "Intel %s"; break; + + default: + break; + } + + for( i = 0 ; i < ETH_DEVICES_LEN; i++ ) + { + if ( ( vendor_id == known_ethernet_cards[i].vendor_id ) && ( device_id == known_ethernet_cards[i].device_id ) ) + { + snprintf( desc, sizeof(desc), name_format, known_ethernet_cards[i].model ); + return desc; + } + } + // NOT in know table... assign generic + /* Not in table */ + snprintf( desc, sizeof(desc), name_format, "Ethernet Controller" ); + return desc; +} + +char *get_wlan_model(uint32_t vendor_id, uint32_t device_id) +{ + + static char desc[128]; + + const char *name_format = NULL; + int i; + + /* Get format for vendor ID */ + switch ( vendor_id ) + { + case PCI_VENDOR_ID_REALTEK: + name_format = "Realteck %s"; break; + + case PCI_VENDOR_ID_ATHEROS: + case PCI_VENDOR_ID_QUALCOMM: + name_format = "Atheros %s"; break; + + case PCI_VENDOR_ID_BROADCOM: + name_format = "Broadcom %s"; break; + + default: + break; + } + + for( i = 0 ; i < WLAN_DEVICES_LEN; i++ ) + { + if ( ( vendor_id == known_wifi_cards[i].vendor_id ) && ( device_id == known_wifi_cards[i].device_id ) ) + { + snprintf( desc, sizeof(desc), name_format, known_wifi_cards[i].model ); + return desc; + } + } + // NOT in know table... assign generic + /* Not in table */ + snprintf( desc, sizeof(desc), name_format, "Wireless Controller" ); + return desc; +} + +void setup_eth_devdrop(pci_dt_t *eth_dev) +{ + char *devicepath = get_pci_dev_path(eth_dev); + char *name_model = NULL; + builtin = 0; + + bool do_eth_devprop = getBoolForKey(kEthernetBuiltIn, &do_eth_devprop, &bootInfo->chameleonConfig); + + DevPropDevice *device = (DevPropDevice *)malloc(sizeof(DevPropDevice)); + + verbose("\tClass code: [%04X]\n", eth_dev->class_id); + verbose("\tEthernetBuiltIn = %s\n", do_eth_devprop ? "Yes" : "No"); + + if (!string) + { + string = devprop_create_string(); + if (!string) + { + return; + } + } + + device = devprop_add_device(string, devicepath); + if(device) + { + name_model = get_ethernet_model(eth_dev->vendor_id, eth_dev->device_id); + + if ( do_eth_devprop ) + { + verbose("\tLocation number: %d\n", location_number); + verbose("\tSetting up lan keys\n"); + if( ( eth_dev->vendor_id != PCI_VENDOR_ID_ATHEROS ) && ( builtin_set == 0 )) + { + builtin_set = 1; + builtin = 0x01; + } + + devprop_add_value(device, "location", (uint8_t *)&location_number, 1); + +// devprop_add_value(device, "AAPL,slot-name", "Slot-x" +// devprop_add_value(device, "device-id", +// devprop_add_value(device, "revision-id", +// devprop_add_value(device, "subsystem-id", +// devprop_add_value(device, "subsystem-vendor-id", + + devprop_add_value(device, "built-in", (uint8_t *)&builtin, 1); + devprop_add_value(device, "model", (uint8_t *)name_model, (strlen(name_model) + 1)); + devprop_add_value(device, "device_type", (uint8_t *)"ethernet", sizeof("Ethernet")); + + stringdata = (uint8_t *)malloc(sizeof(uint8_t) * string->length); + if(stringdata) + { + memcpy(stringdata, (uint8_t *)devprop_generate_string(string), string->length); + stringlength = string->length; + } + + } + } + + verbose("\t%s [%04x:%04x]\n\t%s\n",name_model, eth_dev->vendor_id, eth_dev->device_id, devicepath); + + // location number + location_number++; +} + +void setup_wifi_devdrop(pci_dt_t *wlan_dev) // ARPT +{ + char *devicepath = get_pci_dev_path(wlan_dev); + char *name_model = NULL; + + builtin = 0; + + bool do_wifi_devprop = getBoolForKey(kEnableWifi, &do_wifi_devprop, &bootInfo->chameleonConfig); + + DevPropDevice *device = (DevPropDevice *)malloc(sizeof(DevPropDevice)); + + verbose("\tClass code: [%04X]\n", wlan_dev->class_id); + verbose("\tEnableWifi = %s\n", do_wifi_devprop ? "Yes" : "No"); + + if (!string) + { + string = devprop_create_string(); + if (!string) + { + return; + } + } + + device = devprop_add_device(string, devicepath); + if(device) + { + name_model = get_wlan_model(wlan_dev->vendor_id, wlan_dev->device_id); + + if ( do_wifi_devprop ) + { + verbose("\tSetting up wifi keys\n"); + devprop_add_value(device, "built-in", (uint8_t *)&builtin, 1); + devprop_add_value(device, "model", (uint8_t *)name_model, (strlen(name_model) + 1)); +// devprop_add_value(device, "name", (uint8_t *)"AirPort Extreme", sizeof("AirPort Extreme")); + +// devprop_add_value(device, "vendor-id", +// devprop_add_value(device, "device-id", +// devprop_add_value(device, "subsystem-id", +// devprop_add_value(device, "subsystem-vendor-id", + // NOTE: I would set the subsystem id and subsystem vendor id here, + // however, those values seem to be ovverriden in the boot process. + // A better method would be injecting the DTGP dsdt method + // and then injecting the subsystem id there. + + devprop_add_value(device, "device_type", (uint8_t *)"Airport", sizeof("Airport")); + devprop_add_value(device, "AAPL,slot-name", (uint8_t *)"Airport", sizeof("Airport")); + + stringdata = (uint8_t *)malloc(sizeof(uint8_t) *string->length); + if(stringdata) + { + memcpy(stringdata, (uint8_t *)devprop_generate_string(string), string->length); + stringlength = string->length; + } + } + } + + verbose("\t%s [%04x:%04x]\n\t%s\n", name_model, wlan_dev->vendor_id, wlan_dev->device_id, devicepath); +} Index: branches/zenith432/i386/libsaio/spd.h =================================================================== --- branches/zenith432/i386/libsaio/spd.h (revision 2804) +++ branches/zenith432/i386/libsaio/spd.h (revision 2805) @@ -121,7 +121,9 @@ #define SPD_MEMORY_TYPE_SDRAM_FB_DDR2 9 #define SPD_MEMORY_TYPE_SDRAM_FBP_DDR2 0xa #define SPD_MEMORY_TYPE_SDRAM_DDR3 0xb +#define SPD_MEMORY_TYPE_SDRAM_DDR4 0xc + /* SPD_MODULE_VOLTAGE values. */ #define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */ #define SPD_VOLTAGE_LVTTL 1 /* LVTTL */ Index: branches/zenith432/i386/libsaio/networking.h =================================================================== --- branches/zenith432/i386/libsaio/networking.h (revision 0) +++ branches/zenith432/i386/libsaio/networking.h (revision 2805) @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2009 Evan Lojewski. All rights reserved. + * + * Merge into file from module compcept by ErmaC and Marchrius + * + */ + +#ifndef __LIBSAIO_NETWORKING_H +#define __LIBSAIO_NETWORKING_H + +void setup_eth_devdrop(pci_dt_t *eth_dev); +void setup_wifi_devdrop(pci_dt_t *wlan_dev); + +char *get_ethernet_model(uint32_t vendor_id, uint32_t device_id); +char *get_wlan_model(uint32_t vendor_id, uint32_t device_id); + +struct network_device; +typedef struct { + uint16_t vendor_id; + uint16_t device_id; + char* model; +} network_device; + +#endif /* !__LIBSAIO_NETWORKING_H */ Index: branches/zenith432/i386/libsaio/Makefile =================================================================== --- branches/zenith432/i386/libsaio/Makefile (revision 2804) +++ branches/zenith432/i386/libsaio/Makefile (revision 2805) @@ -37,7 +37,7 @@ smbios.o smbios_getters.o smbios_decode.o \ fake_efi.o ext2fs.o \ hpet.o dram_controllers.o spd.o usb.o pci_setup.o \ - device_inject.o nvidia_helper.o nvidia.o ati.o gma.o hda.o pci_root.o \ + device_inject.o networking.o nvidia_helper.o nvidia.o ati.o gma.o hda.o pci_root.o \ convert.o aml_generator.o console.o exfat.o base64-decode.o SAIO_OBJS := $(addprefix $(OBJROOT)/, $(SAIO_OBJS)) Index: branches/zenith432/i386/libsaio/bios.h =================================================================== --- branches/zenith432/i386/libsaio/bios.h (revision 2804) +++ branches/zenith432/i386/libsaio/bios.h (revision 2805) @@ -31,45 +31,52 @@ #include "bootargs.h" -typedef union { - unsigned int rx; - unsigned short rr; - struct { - unsigned char l; - unsigned char h; +typedef union +{ + unsigned int rx; + unsigned short rr; + + struct + { + unsigned char l; + unsigned char h; } r; } machineRegister_t; -typedef struct { - unsigned short cf :1; - unsigned short :1; - unsigned short pf :1; - unsigned short :1; - unsigned short af :1; - unsigned short :1; - unsigned short zf :1; - unsigned short sf :1; - unsigned short tf :1; - unsigned short _if :1; - unsigned short df :1; - unsigned short of :1; - unsigned short iopl:2; - unsigned short nt :1; + +typedef struct +{ + unsigned short cf : 1; + unsigned short : 1; + unsigned short pf : 1; + unsigned short : 1; + unsigned short af : 1; + unsigned short : 1; + unsigned short zf : 1; + unsigned short sf : 1; + unsigned short tf : 1; + unsigned short _if : 1; + unsigned short df : 1; + unsigned short of : 1; + unsigned short iopl : 2; + unsigned short nt : 1; } machineFlags_t; -typedef struct { - unsigned int intno; - machineRegister_t eax; - machineRegister_t ebx; - machineRegister_t ecx; - machineRegister_t edx; - machineRegister_t edi; - machineRegister_t esi; - machineRegister_t ebp; - unsigned short cs; - unsigned short ds; - unsigned short es; - machineFlags_t flags; + +typedef struct +{ + unsigned int intno; + machineRegister_t eax; + machineRegister_t ebx; + machineRegister_t ecx; + machineRegister_t edx; + machineRegister_t edi; + machineRegister_t esi; + machineRegister_t ebp; + unsigned short cs; + unsigned short ds; + unsigned short es; + machineFlags_t flags; } biosBuf_t; #define EBIOS_FIXED_DISK_ACCESS 0x01 @@ -82,7 +89,8 @@ /* * ACPI defined memory range types. */ -enum { +enum +{ kMemoryRangeUsable = 1, // RAM usable by the OS. kMemoryRangeReserved = 2, // Reserved. (Do not use) kMemoryRangeACPI = 3, // ACPI tables. Can be reclaimed. @@ -95,11 +103,12 @@ /* * Memory range descriptor. */ -typedef struct MemoryRange { - unsigned long long base; // 64-bit base address - unsigned long long length; // 64-bit length in bytes - unsigned long type; // type of memory range - unsigned long reserved; +typedef struct MemoryRange +{ + unsigned long long base; // 64-bit base address + unsigned long long length; // 64-bit length in bytes + unsigned long type; // type of memory range + unsigned long reserved; } MemoryRange; #endif /* !__LIBSAIO_BIOS_H */ Index: branches/zenith432/i386/libsaio/gma.c =================================================================== --- branches/zenith432/i386/libsaio/gma.c (revision 2804) +++ branches/zenith432/i386/libsaio/gma.c (revision 2805) @@ -29,7 +29,7 @@ http://forum.voodooprojects.org/index.php/topic,1029.0.html Original Intel HDx000 code from valv - Intel Ivy Bridge and Haswell code from ErmaC: + Intel Ivy Bridge, Haswell and Broadwell code from ErmaC: - http://www.insanelymac.com/forum/topic/288241-intel-hd4000-inject-aaplig-platform-id/ */ @@ -39,26 +39,42 @@ #include "pci.h" #include "platform.h" #include "device_inject.h" +#include "convert.h" #include "gma.h" #include "vbe.h" #include "graphics.h" #ifndef DEBUG_GMA -#define DEBUG_GMA 0 + #define DEBUG_GMA 0 #endif +#ifndef REPLACE_DEVICE_ID + #define REPLACE_DEVICE_ID 0 +#endif + #if DEBUG_GMA -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) + #define DBG(x...) #endif static bool doit = false; + +static uint8_t default_aapl_snb[] = { 0x00,0x03,0x00,0x01 }; +#define AAPL_LEN_SNB ( sizeof(default_aapl_snb) / sizeof(uint8_t) ) + static uint8_t default_aapl_ivy[] = { 0x05,0x00,0x62,0x01 }; // ivy_bridge_ig_vals[5] #define AAPL_LEN_IVY ( sizeof(default_aapl_ivy) / sizeof(uint8_t) ) + static uint8_t default_aapl_haswell[] = { 0x00,0x00,0x26,0x0c }; // haswell_ig_vals[7] #define AAPL_LEN_HSW ( sizeof(default_aapl_haswell) / sizeof(uint8_t) ) +static uint8_t default_aapl_broadwell[] = { 0x00,0x00,0x1e,0x16 }; // broadwell_ig_vals[2] +#define AAPL_LEN_BDW ( sizeof(default_aapl_broadwell) / sizeof(uint8_t) ) + +static uint8_t default_aapl_skylake[] = { 0x00,0x00,0x16,0x19 }; // skylike_ig_vals[2] +#define AAPL_LEN_SKL ( sizeof(default_aapl_skylake) / sizeof(uint8_t) ) + uint8_t GMAX3100_vals[23][4] = { { 0x01,0x00,0x00,0x00 }, //0 "AAPL,HasPanel" { 0x01,0x00,0x00,0x00 }, //1 "AAPL,SelfRefreshSupported" @@ -100,7 +116,7 @@ { 0x0b,0x00,0x66,0x01 } //11 "AAPL,ig-platform-id" //FB: 32MB, Pipes: 2, Ports: 3, FBMem: 2 }; -uint8_t haswell_ig_vals[16][4] = { /* - TESTING DATA --*/ +uint8_t haswell_ig_vals[17][4] = { { 0x00,0x00,0x06,0x04 }, // 0 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - mobile GT1 { 0x00,0x00,0x06,0x0c }, // 1 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - SDV mobile GT1 { 0x00,0x00,0x16,0x04 }, // 2 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - mobile GT2 @@ -112,14 +128,54 @@ { 0x00,0x00,0x26,0x0d }, // 8 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - CRW mobile GT3 { 0x02,0x00,0x16,0x04 }, // 9 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 1, Ports: 1, FBMem: 1 - mobile GT2 { 0x03,0x00,0x22,0x0d }, // 10 "AAPL,ig-platform-id" //FB: 0MB, Pipes: 0, Ports: 0, FBMem: 0 - CRW Desktop GT3 -// { 0x04,0x00,0x12,0x04 }, // ?? "AAPL,ig-platform-id" //FB: 32MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3 { 0x05,0x00,0x26,0x0a }, // 11 "AAPL,ig-platform-id" //FB: 32MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3 { 0x06,0x00,0x26,0x0a }, // 12 "AAPL,ig-platform-id" //FB: 32MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3 { 0x07,0x00,0x26,0x0d }, // 13 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 4, FBMem: 3 - CRW mobile GT3 { 0x08,0x00,0x26,0x0a }, // 14 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3 { 0x08,0x00,0x2e,0x0a }, // 15 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT reserved GT3 + { 0x04,0x00,0x12,0x04 } // 16 "AAPL,ig-platform-id" //FB: 32MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3 + //0x0412000b + //0x0d260009 }; +uint8_t broadwell_ig_vals[20][4] = { + { 0x00,0x00,0x06,0x16 }, // 0 - 16060000 Broadwell GT1 (Intel HD Graphics) + { 0x00,0x00,0x0e,0x16 }, // 1 - 160e0000 Broadwell GT1 (Intel HD Graphics) + { 0x00,0x00,0x16,0x16 }, // 2 - 16160000 Broadwell GT2 (Intel HD Graphics 5500) + { 0x00,0x00,0x1e,0x16 }, // 3 - 161e0000 Broadwell GT2 (MacBook) (Intel HD Graphics 5300) + { 0x00,0x00,0x26,0x16 }, // 4 - 16260000 Broadwell GT3 (MacBook Air) (Intel HD Graphics 6000) + { 0x00,0x00,0x2b,0x16 }, // 5 - 162b0000 Broadwell GT3 (MacBook Pro) (Intel Iris Graphics 6100) + { 0x00,0x00,0x22,0x16 }, // 6 - 16220000 Broadwell GT3 (Intel Iris Pro Graphics 6200) + { 0x01,0x00,0x0e,0x16 }, // 7 - 160e0001 Broadwell GT1 (Intel HD Graphics) + { 0x01,0x00,0x1e,0x16 }, // 8 - 161e0001 Broadwell GT2 (MacBook) (Intel HD Graphics 5300) + { 0x02,0x00,0x06,0x16 }, // 9 - 16060002 Broadwell GT1 (Intel HD Graphics) + { 0x02,0x00,0x16,0x16 }, // 10 - 16160002 Broadwell GT2 (Intel HD Graphics 5500) + { 0x02,0x00,0x26,0x16 }, // 11 - 16260002 Broadwell GT3 (MacBook Air) (Intel HD Graphics 6000) + { 0x02,0x00,0x22,0x16 }, // 12 - 16220002 Broadwell GT3 (Intel Iris Pro Graphics 6200) + { 0x02,0x00,0x2b,0x16 }, // 13 - 162b0002 Broadwell GT3 (MacBook Pro) (Intel Iris Graphics 6100) + { 0x03,0x00,0x12,0x16 }, // 14 - 16120003 Broadwell GT2 (Intel HD Graphics 5600) + { 0x04,0x00,0x2b,0x16 }, // 15 - 162b0004 Broadwell GT3 (MacBook Pro) (Intel Iris Graphics 6100) + { 0x04,0x00,0x26,0x16 }, // 16 - 16260004 Broadwell GT3 (MacBook Air) (Intel HD Graphics 6000) + { 0x05,0x00,0x26,0x16 }, // 17 - 16260005 Broadwell GT3 (MacBook Air) (Intel HD Graphics 6000) + { 0x06,0x00,0x26,0x16 }, // 18 - 16260006 Broadwell GT3 (MacBook Air) (Intel HD Graphics 6000) + { 0x07,0x00,0x22,0x16 } // 19 - 16260006 Broadwell GT3 (iMac Retina 21") (Intel Iris Pro 6200) +}; + +uint8_t skylake_ig_vals[12][4] = { + { 0x00,0x00,0xe0,0x19 }, // 0 - 191e0000 – Skylake ULX GT2 + { 0x00,0x00,0x16,0x19 }, // 1 - 19160000 – Skylake ULT GT2 + { 0x00,0x00,0x26,0x19 }, // 2 - 19260000 – Skylake ULT GT3 + { 0x00,0x00,0x1b,0x19 }, // 3 - 191b0000 – Skylake HALO GT2 + { 0x00,0x00,0x12,0x19 }, // 4 - 19120000 – Skylake Desktop GT2 + { 0x01,0x00,0x02,0x19 }, // 5 - 19020001 – Skylake Desktop GT1 + { 0x01,0x00,0x17,0x19 }, // 6 - 19170001 – Skylake Desktop GT1.5 + { 0x01,0x00,0x12,0x19 }, // 7 - 19120001 – Skylake Desktop GT2 + { 0x01,0x00,0x32,0x19 }, // 8 - 19320001 – Skylake Desktop GT4 + { 0x02,0x00,0x16,0x19 }, // 9 - 19160002 – Skylake ULT GT2 + { 0x02,0x00,0x26,0x19 }, // 10 - 19260002 – Skylake ULT GT3 + { 0x03,0x00,0x1e,0x19 } // 11 - 191e0003 – Skylake ULX GT2 +}; + uint8_t HD2000_vals[16][4] = { { 0x00,0x00,0x00,0x00 }, //0 "AAPL00,PixelFormat" { 0x00,0x00,0x00,0x00 }, //1 "AAPL00,T1" @@ -267,7 +323,7 @@ {GMA_SANDYBRIDGE_M_GT1, HD_GRAPHICS_2000 }, {GMA_SANDYBRIDGE_M_GT2, HD_GRAPHICS_3000 }, {GMA_SANDYBRIDGE_M_GT2_PLUS, HD_GRAPHICS_3000 }, - {GMA_SANDYBRIDGE_S_GT, HD_GRAPHICS }, + {GMA_SANDYBRIDGE_S_GT, "HD Graphics P3000" }, /* 010a */ // 010B /* ??? */ // 010E /* ??? */ @@ -278,7 +334,7 @@ {GMA_IVYBRIDGE_D_GT2, HD_GRAPHICS_4000 }, /* 0162 */ {GMA_IVYBRIDGE_S_GT1, HD_GRAPHICS }, /* 015a */ {GMA_IVYBRIDGE_S_GT2, "HD Graphics P4000" }, /* 016a */ - {GMA_IVYBRIDGE_S_GT3, HD_GRAPHICS }, /* 015e */ + {GMA_IVYBRIDGE_S_GT3, HD_GRAPHICS }, /* 015e */ {GMA_IVYBRIDGE_S_GT4, HD_GRAPHICS_2500 }, /* 0172 */ {GMA_IVYBRIDGE_S_GT5, HD_GRAPHICS_2500 }, /* 0176 */ @@ -348,31 +404,59 @@ {GMA_HASWELL_CRW_M_GT2_PLUS_IG, HD_GRAPHICS }, /* 0d36 */ {GMA_HASWELL_CRW_S_GT2_PLUS_IG, HD_GRAPHICS }, /* 0d3a */ - /* Brodwell */ - {GMA_BRODWELL_BDW_1602, HD_GRAPHICS }, /* 1602 */ - {GMA_BRODWELL_BDW_U_GT1, HD_GRAPHICS }, /* 1606 */ - {GMA_BRODWELL_BDW_160B, HD_GRAPHICS }, /* 160b */ - {GMA_BRODWELL_BDW_160A, HD_GRAPHICS }, /* 160a */ - {GMA_BRODWELL_BDW_160D, HD_GRAPHICS }, /* 160d */ - {GMA_BRODWELL_BDW_160E, HD_GRAPHICS }, /* 160e */ - {GMA_BRODWELL_BDW_1612, HD_GRAPHICS_5600}, /* 1612 */ - {GMA_BRODWELL_BDW_U_GT2, HD_GRAPHICS_5500 }, /* 1616 */ - {GMA_BRODWELL_BDW_161B, HD_GRAPHICS }, /* 161b */ - {GMA_BRODWELL_BDW_161A, HD_GRAPHICS }, /* 161a */ - {GMA_BRODWELL_BDW_161D, HD_GRAPHICS }, /* 161d */ - {GMA_BRODWELL_BDW_Y_GT2, HD_GRAPHICS_5300 }, /* 161e */ - {GMA_BRODWELL_BDW_1622, IRIS_6200}, /* 1622 */ - {GMA_BRODWELL_BDW_U_GT3, HD_GRAPHICS_6000 }, /* 1626 */ - {GMA_BRODWELL_BDW_162A, IRIS_6300}, /* 162a */ - {GMA_BRODWELL_BDW_U_GT3_2, IRIS_6100 }, /* 162b */ - {GMA_BRODWELL_BDW_162D, HD_GRAPHICS }, /* 162d */ - {GMA_BRODWELL_BDW_162E, HD_GRAPHICS }, /* 162e */ - {GMA_BRODWELL_BDW_1632, HD_GRAPHICS }, /* 1632 */ - {GMA_BRODWELL_BDW_1636, HD_GRAPHICS }, /* 1636 */ - {GMA_BRODWELL_BDW_163B, HD_GRAPHICS }, /* 163b */ - {GMA_BRODWELL_BDW_163A, HD_GRAPHICS }, /* 163a */ - {GMA_BRODWELL_BDW_163D, HD_GRAPHICS }, /* 163d */ - {GMA_BRODWELL_BDW_163E, HD_GRAPHICS } /* 163e */ + /* Broadwell */ + {GMA_BROADWELL_BDW_0bd0, HD_GRAPHICS }, /* 0bd0 */ + {GMA_BROADWELL_BDW_0bd1, HD_GRAPHICS }, /* 0bd1 */ + {GMA_BROADWELL_BDW_0bd2, HD_GRAPHICS }, /* 0bd2 */ + {GMA_BROADWELL_BDW_0bd3, HD_GRAPHICS }, /* 0bd3 */ + {GMA_BROADWELL_BDW_0bd4, HD_GRAPHICS }, /* 0bd4 */ + + {GMA_BROADWELL_BDW_1602, HD_GRAPHICS }, /* 1602 */ + {GMA_BROADWELL_BDW_U_GT1, HD_GRAPHICS }, /* 1606 */ + {GMA_BROADWELL_BDW_160B, HD_GRAPHICS }, /* 160b */ + {GMA_BROADWELL_BDW_160A, HD_GRAPHICS }, /* 160a */ + {GMA_BROADWELL_BDW_160D, HD_GRAPHICS }, /* 160d */ + {GMA_BROADWELL_BDW_160E, HD_GRAPHICS }, /* 160e */ + {GMA_BROADWELL_BDW_1612, HD_GRAPHICS_5600}, /* 1612 */ + {GMA_BROADWELL_BDW_U_GT2, HD_GRAPHICS_5500 }, /* 1616 */ + {GMA_BROADWELL_BDW_161B, HD_GRAPHICS }, /* 161b */ + {GMA_BROADWELL_BDW_161A, HD_GRAPHICS }, /* 161a */ + {GMA_BROADWELL_BDW_161D, HD_GRAPHICS }, /* 161d */ + {GMA_BROADWELL_BDW_Y_GT2, HD_GRAPHICS_5300 }, /* 161e */ + {GMA_BROADWELL_BDW_1622, IRIS_6200}, /* 1622 */ + {GMA_BROADWELL_BDW_U_GT3, HD_GRAPHICS_6000 }, /* 1626 */ + {GMA_BROADWELL_BDW_162A, IRIS_6300}, /* 162a */ + {GMA_BROADWELL_BDW_U_GT3_2, IRIS_6100 }, /* 162b */ + {GMA_BROADWELL_BDW_162D, IRIS_6300 }, /* 162d */ + {GMA_BROADWELL_BDW_162E, HD_GRAPHICS }, /* 162e */ + {GMA_BROADWELL_BDW_1632, HD_GRAPHICS }, /* 1632 */ + {GMA_BROADWELL_BDW_1636, HD_GRAPHICS }, /* 1636 */ + {GMA_BROADWELL_BDW_163B, HD_GRAPHICS }, /* 163b */ + {GMA_BROADWELL_BDW_163A, HD_GRAPHICS }, /* 163a */ + {GMA_BROADWELL_BDW_163D, HD_GRAPHICS }, /* 163d */ + {GMA_BROADWELL_BDW_163E, HD_GRAPHICS }, /* 163e */ + + /* Skylake */ + {GMA_SKYLAKE_ULT_GT1, HD_GRAPHICS_510 }, /* 1906 */ + {GMA_SKYLAKE_ULT_GT15, HD_GRAPHICS_510 }, /* 1913 */ + {GMA_SKYLAKE_ULT_GT2, HD_GRAPHICS_520 }, /* 1916 */ + {GMA_SKYLAKE_ULX_GT1, HD_GRAPHICS }, /* 190E */ + {GMA_SKYLAKE_ULX_GT2, HD_GRAPHICS_515 }, /* 191E */ + {GMA_SKYLAKE_DT_GT2, HD_GRAPHICS_530 }, /* 1912 */ + {GMA_SKYLAKE_1921, HD_GRAPHICS_520 }, /* 1921 */ + {GMA_SKYLAKE_ULT_GT3_E, IRIS_540 }, /* 1926 */ + {GMA_SKYLAKE_ULT_GT3, HD_GRAPHICS_535 }, /* 1923 */ + {GMA_SKYLAKE_ULT_GT3_28W, HD_GRAPHICS_550 }, /* 1927 */ + {GMA_SKYLAKE_DT_GT15, HD_GRAPHICS_530 }, /* 1917 */ + {GMA_SKYLAKE_DT_GT1, HD_GRAPHICS_510 }, /* 1902 */ + {GMA_SKYLAKE_DT_GT4, IRIS_570_580 }, /* 1932 */ + {GMA_SKYLAKE_GT4, IRIS_580 }, /* 193B */ + {GMA_SKYLAKE_GT3_FE, IRIS }, /* 192B */ + {GMA_SKYLAKE_GT2, HD_GRAPHICS_530 }, /* 191B */ + {GMA_SKYLAKE_192A, IRIS_P580 }, /* 192A */ + {GMA_SKYLAKE_SRW_GT4, IRIS_P580 }, /* 193A */ + {GMA_SKYLAKE_WS_GT2, HD_GRAPHICS_P530 }, /* 191D */ + {GMA_SKYLAKE_WS_GT4, IRIS_P580 } /* 193D */ }; #define GFX_DEVICES_LEN (sizeof(intel_gfx_chipsets) / sizeof(intel_gfx_chipsets[0])) @@ -417,12 +501,11 @@ model = get_gma_controller_name(device_id, vendor_id); - verbose("---------------------------------------------\n"); - verbose("------------ INTEL DEVICE INFO --------------\n"); - verbose("---------------------------------------------\n"); - verbose("Class code: [%04x]\n%s [%04x:%04x] (rev %02x)\nSubsystem: [%04x:%04x] :: %s\n", - gma_dev->class_id, model, gma_dev->vendor_id, gma_dev->device_id, gma_dev->revision_id, gma_dev->subsys_id.subsys.vendor_id, gma_dev->subsys_id.subsys.device_id, devicepath); + verbose("\tClass code: [%04X]\n", gma_dev->class_id); + verbose("\t%s [%04x:%04x] (rev %02x)\nSubsystem: [%04x:%04x] :: %s\n", + model, gma_dev->vendor_id, gma_dev->device_id, gma_dev->revision_id, gma_dev->subsys_id.subsys.vendor_id, gma_dev->subsys_id.subsys.device_id, devicepath); + if (!string) { string = devprop_create_string(); @@ -431,7 +514,7 @@ struct DevPropDevice *device = devprop_add_device(string, devicepath); if (!device) { - printf("[setup_gma_devprop] Failed initializing dev-prop string dev-entry!\n"); + printf("\t[setup_gma_devprop] Failed initializing dev-prop string dev-entry!\n"); pause(); return false; } @@ -454,7 +537,6 @@ case GMA_IRONLAKE_M_G: // 0046 devprop_add_value(device, "built-in", &BuiltIn, 1); devprop_add_value(device, "class-code", ClassFix, 4); - //devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); devprop_add_value(device, "AAPL,os-info", HDx000_os_info, 20); break; /* 27A2, 27AE, 27A6, A001, A011, A012, */ @@ -512,8 +594,7 @@ /* 0106 */ case GMA_SANDYBRIDGE_M_GT1: // HD Graphics 2000 Mobile - devprop_add_value(device, "class-code", ClassFix, 4); - //devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); + devprop_add_value(device, "class-code", ClassFix, 4); devprop_add_value(device, "AAPL00,PixelFormat", HD2000_vals[0], 4); devprop_add_value(device, "AAPL00,T1", HD2000_vals[1], 4); devprop_add_value(device, "AAPL00,T2", HD2000_vals[2], 4); @@ -530,13 +611,31 @@ devprop_add_value(device, "graphic-options", HD2000_vals[13], 4); devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18); devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20); + if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_SNB * 2) + { + uint8_t new_aapl0[AAPL_LEN_SNB]; + + if (hex2bin(value, new_aapl0, AAPL_LEN_SNB) == 0) + { + memcpy(default_aapl_snb, new_aapl0, AAPL_LEN_SNB); + + verbose("\tUsing user supplied AAPL,snb-platform-id\n"); + verbose("\tAAPL,snb-platform-id: %02x%02x%02x%02x\n", + default_aapl_snb[0], default_aapl_snb[1], default_aapl_snb[2], default_aapl_snb[3]); + } + devprop_add_value(device, "AAPL,snb-platform-id", default_aapl_snb, AAPL_LEN_SNB); + } + else + { + uint32_t ig_platform_id = 0x00030010; // set the default platform ig + devprop_add_value(device, "AAPL,snb-platform-id", (uint8_t *)&ig_platform_id, 4); + } break; /* 0116, 0126 */ case GMA_SANDYBRIDGE_M_GT2: // HD Graphics 3000 Mobile case GMA_SANDYBRIDGE_M_GT2_PLUS: devprop_add_value(device, "class-code", ClassFix, 4); - //devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); devprop_add_value(device, "AAPL00,PixelFormat", HD3000_vals[0], 4); devprop_add_value(device, "AAPL00,T1", HD3000_vals[1], 4); devprop_add_value(device, "AAPL00,T2", HD3000_vals[2], 4); @@ -553,9 +652,29 @@ devprop_add_value(device, "graphic-options", HD3000_vals[13], 4); devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18); devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20); - devprop_add_value(device, "AAPL,snb-platform-id", HD3000_vals[16], 4);// previusly commented - break; + if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_SNB * 2) + { + uint8_t new_aapl0[AAPL_LEN_SNB]; + + if (hex2bin(value, new_aapl0, AAPL_LEN_SNB) == 0) + { + memcpy(default_aapl_snb, new_aapl0, AAPL_LEN_SNB); + + verbose("\tUsing user supplied AAPL,snb-platform-id\n"); + verbose("\tAAPL,snb-platform-id: %02x%02x%02x%02x\n", + default_aapl_snb[0], default_aapl_snb[1], default_aapl_snb[2], default_aapl_snb[3]); + } + devprop_add_value(device, "AAPL,snb-platform-id", default_aapl_snb, AAPL_LEN_SNB); + } + else + { + uint32_t ig_platform_id = 0x00010000; // set the default platform ig + devprop_add_value(device, "AAPL,snb-platform-id", (uint8_t *)&ig_platform_id, 4); + } + + break; + /* 0102 */ /* HD Graphics 2000 */ case GMA_SANDYBRIDGE_GT1: // 0102 @@ -563,9 +682,29 @@ devprop_add_value(device, "built-in", &BuiltIn, 1); devprop_add_value(device, "class-code", ClassFix, 4); devprop_add_value(device, "device-id", (uint8_t *)&device_id, sizeof(device_id)); - //devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); - devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18); - devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20); + devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18); + devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20); + + if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_SNB * 2) + { + uint8_t new_aapl0[AAPL_LEN_SNB]; + + if (hex2bin(value, new_aapl0, AAPL_LEN_SNB) == 0) + { + memcpy(default_aapl_snb, new_aapl0, AAPL_LEN_SNB); + + verbose("\tUsing user supplied AAPL,snb-platform-id\n"); + verbose("\tAAPL,snb-platform-id: %02x%02x%02x%02x\n", + default_aapl_snb[0], default_aapl_snb[1], default_aapl_snb[2], default_aapl_snb[3]); + } + devprop_add_value(device, "AAPL,snb-platform-id", default_aapl_snb, AAPL_LEN_SNB); + } + else + { + uint32_t ig_platform_id = 0x00030010; // set the default platform ig + devprop_add_value(device, "AAPL,snb-platform-id", (uint8_t *)&ig_platform_id, 4); + } + break; /* Sandy Bridge */ @@ -574,11 +713,42 @@ case GMA_SANDYBRIDGE_GT2_PLUS: // 0122 devprop_add_value(device, "built-in", &BuiltIn, 1); devprop_add_value(device, "class-code", ClassFix, 4); - device_id = 0x00000126; // Inject a valid mobile GPU device id instead of patching kexts - devprop_add_value(device, "device-id", (uint8_t *)&device_id, sizeof(device_id)); - //devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); - devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18); - devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20); + + // patch by ikunikun for i3-2125 and i5-2500K to enable HD3000. + if(((device_id << 16) | vendor_id) != GMA_SANDYBRIDGE_GT2) + { + devprop_add_value(device, "vendor-id", (uint8_t *)INTEL_VENDORID, 4); + } + else + { + device_id = 0x00000126; + devprop_add_value(device, "device-id", (uint8_t *)&device_id, sizeof(device_id)); + verbose("\tInjeting done: was [%04x:%04x] now is [%04x:%04x]\n", gma_dev->vendor_id, gma_dev->device_id, gma_dev->vendor_id, device_id); + } + + devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18); + devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20); + + if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_SNB * 2) + { + uint8_t new_aapl0[AAPL_LEN_SNB]; + + if (hex2bin(value, new_aapl0, AAPL_LEN_SNB) == 0) + { + memcpy(default_aapl_snb, new_aapl0, AAPL_LEN_SNB); + + verbose("\tUsing user supplied AAPL,snb-platform-id\n"); + verbose("\tAAPL,snb-platform-id: %02x%02x%02x%02x\n", + default_aapl_snb[0], default_aapl_snb[1], default_aapl_snb[2], default_aapl_snb[3]); + } + devprop_add_value(device, "AAPL,snb-platform-id", default_aapl_snb, AAPL_LEN_SNB); + } + else + { + uint32_t ig_platform_id = 0x00030010; // set the default platform ig + devprop_add_value(device, "AAPL,snb-platform-id", (uint8_t *)&ig_platform_id, 4); + } + break; /* Ivy Bridge */ @@ -601,8 +771,8 @@ { memcpy(default_aapl_ivy, new_aapl0, AAPL_LEN_IVY); - verbose("Using user supplied AAPL,ig-platform-id\n"); - verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n", + verbose("\tUsing user supplied AAPL,ig-platform-id\n"); + verbose("\tAAPL,ig-platform-id: %02x%02x%02x%02x\n", default_aapl_ivy[0], default_aapl_ivy[1], default_aapl_ivy[2], default_aapl_ivy[3]); } devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_ivy, AAPL_LEN_IVY); @@ -611,12 +781,12 @@ { if ((n_igs >= 0) || (n_igs <= 11)) { - verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs); + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs); devprop_add_value(device, "AAPL,ig-platform-id", ivy_bridge_ig_vals[n_igs], 4); } else { - verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 11.\n"); + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 11.\n"); } } else @@ -638,8 +808,8 @@ break; default: - printf("Please specify 96, 64, or 32MB RAM for the HD4000 in the bios.\n" - "The selected %dMB RAM configuration is not supported for the HD4000.\n", ram); + printf("\tPlease specify 96, 64, or 32MB RAM for the HD4000 in the bios.\n" + "\tThe selected %dMB RAM configuration is not supported for the HD4000.\n", ram); pause(); return false; // Exit early before the AAPL,ig-platform-id property is set. break; @@ -650,7 +820,7 @@ devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4); devprop_add_value(device, "built-in", &BuiltIn, 1); devprop_add_value(device, "class-code", ClassFix, 4); - //devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); + break; /* Haswell */ @@ -662,15 +832,13 @@ case GMA_HASWELL_E_GT2: // 041e case GMA_HASWELL_ULT_M_GT2: // 0a16 case GMA_HASWELL_ULT_E_GT2: // 0a1e - verbose("Injecting a valid desktop GPU device id (0x0412) instead of patching kexts.\n"); +#if REPLACE_DEVICE_ID + verbose("\tInjecting a valid desktop GPU device id (0x0412) instead of patching kexts.\n"); device_id = 0x00000412; // Inject a valid desktop GPU device id (0x0412) instead of patching kexts devprop_add_value(device, "vendor-id", (uint8_t *)INTEL_VENDORID, 4); devprop_add_value(device, "device-id", (uint8_t *)&device_id, sizeof(device_id)); - devprop_add_value(device, "compatible", (uint8_t *)"pci8086,0412", 13); // GT2 Desktop -// devprop_add_value(device, "IOName", (uint8_t *)"pci8086,0412", 13); // GT2 Desktop - devprop_add_value(device, "name", (uint8_t *)"pci8086,0412", 13); // GT2 Desktop - verbose("Injeting done: was [%04x:%04x] now is [%04x:%04x]\n", gma_dev->vendor_id, gma_dev->device_id, gma_dev->vendor_id, device_id); - + verbose("\tInjeting done: was [%04x:%04x] now is [%04x:%04x]\n", gma_dev->vendor_id, gma_dev->device_id, gma_dev->vendor_id, device_id); +#endif // REPLACE_DEVICE_ID case GMA_HASWELL_D_GT1: // 0402 case GMA_HASWELL_M_GT1: // 0406 case GMA_HASWELL_S_GT1: // 040a @@ -719,22 +887,22 @@ { memcpy(default_aapl_haswell, new_aapl0, AAPL_LEN_HSW); - verbose("Using user supplied AAPL,ig-platform-id\n"); - verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n", + verbose("\tUsing user supplied AAPL,ig-platform-id\n"); + verbose("\tAAPL,ig-platform-id: %02x%02x%02x%02x\n", default_aapl_haswell[0], default_aapl_haswell[1], default_aapl_haswell[2], default_aapl_haswell[3]); } devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_haswell, AAPL_LEN_HSW); } else if (getIntForKey(kIntelAzulFB, &n_igs, &bootInfo->chameleonConfig)) { - if ((n_igs >= 0) || (n_igs <= 15)) + if ((n_igs >= 0) || (n_igs <= 16)) { - verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs); + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs); devprop_add_value(device, "AAPL,ig-platform-id", haswell_ig_vals[n_igs], 4); } else { - verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 15.\n"); + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 16.\n"); } } else @@ -746,9 +914,148 @@ devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4); devprop_add_value(device, "built-in", &BuiltIn, 1); devprop_add_value(device, "class-code", ClassFix, 4); - //devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); + break; + /* Broadwell */ + /* HD Graphics 5300 Mobile, HD Graphics 6000 Mobile, HD Graphics 6100 Mobile */ + case GMA_BROADWELL_BDW_0bd0: // 0bd0 + case GMA_BROADWELL_BDW_0bd1: // 0bd1 + case GMA_BROADWELL_BDW_0bd2: // 0bd2 + case GMA_BROADWELL_BDW_0bd3: // 0bd3 + case GMA_BROADWELL_BDW_0bd4: // 0bd4 + case GMA_BROADWELL_BDW_1602: // 1602 + case GMA_BROADWELL_BDW_U_GT1: // 1606 + case GMA_BROADWELL_BDW_160B: // 160b + case GMA_BROADWELL_BDW_160A: // 160a + case GMA_BROADWELL_BDW_160D: // 160d + case GMA_BROADWELL_BDW_160E: // 160e + case GMA_BROADWELL_BDW_1612: // 1612 + case GMA_BROADWELL_BDW_U_GT2: // 1616 + case GMA_BROADWELL_BDW_161B: // 161b + case GMA_BROADWELL_BDW_161A: // 161a + case GMA_BROADWELL_BDW_161D: // 161d + case GMA_BROADWELL_BDW_Y_GT2: // 161e (MacBook) Intel HD Graphics 5300 + case GMA_BROADWELL_BDW_1622: // 1622 (iMac 21") Intel Iris Pro 6200 + case GMA_BROADWELL_BDW_U_GT3: // 1626 (MacBook Air) Intel HD Graphics 6000 + case GMA_BROADWELL_BDW_162A: // 162a + case GMA_BROADWELL_BDW_U_GT3_2: // 162b (MacBook Pro) Intel Iris Graphics 6100 + case GMA_BROADWELL_BDW_162D: // 162d + case GMA_BROADWELL_BDW_162E: // 162e + case GMA_BROADWELL_BDW_1632: // 1632 + case GMA_BROADWELL_BDW_1636: // 1636 + case GMA_BROADWELL_BDW_163B: // 163b + case GMA_BROADWELL_BDW_163A: // 163a + case GMA_BROADWELL_BDW_163D: // 163d + case GMA_BROADWELL_BDW_163E: // 163e + + if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_BDW * 2) + { + uint8_t new_aapl0[AAPL_LEN_BDW]; + + if (hex2bin(value, new_aapl0, AAPL_LEN_BDW) == 0) + { + memcpy(default_aapl_broadwell, new_aapl0, AAPL_LEN_BDW); + + verbose("\tUsing user supplied AAPL,ig-platform-id\n"); + verbose("\tAAPL,ig-platform-id: %02x%02x%02x%02x\n", + default_aapl_broadwell[0], default_aapl_broadwell[1], default_aapl_broadwell[2], default_aapl_broadwell[3]); + } + devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_broadwell, AAPL_LEN_BDW); + } + else if (getIntForKey(kIntelBdwFB, &n_igs, &bootInfo->chameleonConfig)) + { + if ((n_igs >= 0) || (n_igs <= 20)) + { + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs); + devprop_add_value(device, "AAPL,ig-platform-id", broadwell_ig_vals[n_igs], 4); + } + else + { + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 19.\n"); + } + } + else + { + uint32_t ig_platform_id; + if ( ( (device_id << 16) | vendor_id ) == GMA_BROADWELL_BDW_1622 ) + { + ig_platform_id = 0x16220007; // Iris Pro 6200 (i5 5675C & i7 5775C) + } + else + { + ig_platform_id = 0x16160000; // set the default platform ig + } + devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4); + } + + devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4); + devprop_add_value(device, "built-in", &BuiltIn, 1); + devprop_add_value(device, "class-code", ClassFix, 4); + + break; + + /* Skylake */ + /* HD Graphics */ + case GMA_SKYLAKE_ULT_GT1: // 1906 + case GMA_SKYLAKE_ULT_GT15: // 1913 + case GMA_SKYLAKE_ULT_GT2: // 1916 + case GMA_SKYLAKE_ULX_GT1: // 190E + case GMA_SKYLAKE_ULX_GT2: // 191E + case GMA_SKYLAKE_DT_GT2: // 1912 + case GMA_SKYLAKE_1921: // 1921 + case GMA_SKYLAKE_ULT_GT3_E: // 1926 + case GMA_SKYLAKE_ULT_GT3: // 1923 + case GMA_SKYLAKE_ULT_GT3_28W: // 1927 + case GMA_SKYLAKE_DT_GT15: // 1917 + case GMA_SKYLAKE_DT_GT1: // 1902 + case GMA_SKYLAKE_DT_GT4: // 1932 + case GMA_SKYLAKE_GT4: // 193B + case GMA_SKYLAKE_GT3_FE: // 192B + case GMA_SKYLAKE_GT2: // 191B + case GMA_SKYLAKE_192A: // 192A + case GMA_SKYLAKE_SRW_GT4: // 193A + case GMA_SKYLAKE_WS_GT2: // 191D + case GMA_SKYLAKE_WS_GT4: // 193D + + if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_SKL * 2) + { + uint8_t new_aapl0[AAPL_LEN_SKL]; + + if (hex2bin(value, new_aapl0, AAPL_LEN_SKL) == 0) + { + memcpy(default_aapl_skylake, new_aapl0, AAPL_LEN_SKL); + + verbose("\tUsing user supplied AAPL,ig-platform-id\n"); + verbose("\tAAPL,ig-platform-id: %02x%02x%02x%02x\n", + default_aapl_skylake[0], default_aapl_skylake[1], default_aapl_skylake[2], default_aapl_skylake[3]); + } + devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_skylake, AAPL_LEN_SKL); + } + else if (getIntForKey(kIntelSklFB, &n_igs, &bootInfo->chameleonConfig)) + { + if ((n_igs >= 0) || (n_igs <= 12)) + { + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs); + devprop_add_value(device, "AAPL,ig-platform-id", skylake_ig_vals[n_igs], 4); + } + else + { + verbose("\tAAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 12.\n"); + } + } + else + { + uint32_t ig_platform_id = 0x19260000; // set the default platform ig + devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4); + } + + devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4); + devprop_add_value(device, "built-in", &BuiltIn, 1); + devprop_add_value(device, "class-code", ClassFix, 4); + + break; + default: break; } @@ -756,12 +1063,11 @@ stringdata = malloc(sizeof(uint8_t) * string->length); if (!stringdata) { - printf("[setup_gma_devprop] No stringdata!\n"); + printf("\t[setup_gma_devprop] No stringdata!\n"); pause(); return false; } - verbose("---------------------------------------------\n"); memcpy(stringdata, (uint8_t *)devprop_generate_string(string), string->length); stringlength = string->length; Index: branches/zenith432/i386/libsaio/gma.h =================================================================== --- branches/zenith432/i386/libsaio/gma.h (revision 2804) +++ branches/zenith432/i386/libsaio/gma.h (revision 2805) @@ -24,13 +24,14 @@ */ /* - Original patch by Nawcom - http://forum.voodooprojects.org/index.php/topic,1029.0.html - - Original Intel HDx000 code from valv - Intel HD4xx and HD5xx code by ErmaC http://www.insanelymac.com/forum/topic/288241-intel-hd4000-inject-aaplig-platform-id/ - */ + Original patch by Nawcom + http://forum.voodooprojects.org/index.php/topic,1029.0.html + Original Intel HDx000 code from valv + Intel Ivy Bridge, Haswell and Broadwell code from ErmaC: + - http://www.insanelymac.com/forum/topic/288241-intel-hd4000-inject-aaplig-platform-id/ +*/ + #ifndef __LIBSAIO_GMA_H #define __LIBSAIO_GMA_H @@ -70,10 +71,22 @@ #define HD_GRAPHICS_5500 "HD Graphics 5500" #define HD_GRAPHICS_5600 "HD Graphics 5600" #define HD_GRAPHICS_6000 "HD Graphics 6000" -#define IRIS_6100 "Iris graphics 6100" +#define IRIS_6100 "Iris Graphics 6100" #define IRIS_6200 "Iris Pro Graphics 6200" #define IRIS_6300 "Iris Pro Graphics P6300" -#define INTEL_VENDORID 0x8086 +#define HD_GRAPHICS_510 "HD Graphics 510" +#define HD_GRAPHICS_515 "HD Graphics 515" +#define HD_GRAPHICS_520 "HD Graphics 520" +#define HD_GRAPHICS_P530 "HD Graphics P530" +#define HD_GRAPHICS_530 "HD Graphics 530" +#define HD_GRAPHICS_535 "HD Graphics 535" +#define HD_GRAPHICS_550 "HD Graphics 550" +#define IRIS_540 "Iris(TM) Graphics 540" +#define IRIS_570_580 "Iris(TM) Pro Graphics 570/580" +#define IRIS_580 "Iris(TM) Pro Graphics 580" +#define IRIS "Iris(TM) Graphics" +#define IRIS_P580 "Iris(TM) Pro Graphics P580" +#define INTEL_VENDORID PCI_VENDOR_ID_INTEL /* http://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/src/intel_driver.h */ /* http://people.redhat.com/agk/patches/linux/patches-3.6/git-update1.patch */ @@ -83,7 +96,14 @@ #define GMA_I810_E GFX_MODEL_CONSTRUCT(INTEL, 0x7125) #define GMA_I815 GFX_MODEL_CONSTRUCT(INTEL, 0x1132) /* ==================================== */ +// Cherryview (Braswell, Cherry Trail) +// #define GMA_ GFX_MODEL_CONSTRUCT(INTEL, 0x22B0) // Intel(R) HD Graphics +// #define GMA_ GFX_MODEL_CONSTRUCT(INTEL, 0x22B1) // Intel(R) HD Graphics +// #define GMA_ GFX_MODEL_CONSTRUCT(INTEL, 0x22B2) // Intel(R) HD Graphics +// #define GMA_ GFX_MODEL_CONSTRUCT(INTEL, 0x22B3) // Intel(R) HD Graphics +/* ==================================== */ + #define GMA_I830_M GFX_MODEL_CONSTRUCT(INTEL, 0x3577) #define GMA_845_G GFX_MODEL_CONSTRUCT(INTEL, 0x2562) #define GMA_I854 GFX_MODEL_CONSTRUCT(INTEL, 0x358E) @@ -170,15 +190,15 @@ #define GMA_IVYBRIDGE_S_GT5 GFX_MODEL_CONSTRUCT(INTEL, 0x0176) // HD Graphics 2500 Mobile // 3rd Gen Core processor Graphics Controller /* ==================================== */ -/* ====== Valleyview (Baytail) ======= */ +/* ====== Valleyview (Bay Trail) ======= */ -//#define GMA_VALLEYVIEW_HB GFX_MODEL_CONSTRUCT(INTEL, 0x0F00) /* VLV1 */ -//#define GMA_VALLEYVIEW_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0F30) /* "HD Graphics" */ -//#define GMA_VALLEYVIEW_?? GFX_MODEL_CONSTRUCT(INTEL, 0x0F31) /* "HD Graphics" */ -//#define GMA_VALLEYVIEW_?? GFX_MODEL_CONSTRUCT(INTEL, 0x0F32) /* "HD Graphics" */ -//#define GMA_VALLEYVIEW_?? GFX_MODEL_CONSTRUCT(INTEL, 0x0F33) /* "HD Graphics" */ -//#define GMA_VALLEYVIEW_?? GFX_MODEL_CONSTRUCT(INTEL, 0x0155) /* "HD Graphics" */ -//#define GMA_VALLEYVIEW_?? GFX_MODEL_CONSTRUCT(INTEL, 0x0157) /* "HD Graphics" */ +//#define GMA_VALLEYVIEW_0F00 GFX_MODEL_CONSTRUCT(INTEL, 0x0F00) /* VLV1 */ +//#define GMA_VALLEYVIEW_0F30 GFX_MODEL_CONSTRUCT(INTEL, 0x0F30) /* "HD Graphics" */ +//#define GMA_VALLEYVIEW_0F31 GFX_MODEL_CONSTRUCT(INTEL, 0x0F31) /* "HD Graphics" */ +//#define GMA_VALLEYVIEW_0F32 GFX_MODEL_CONSTRUCT(INTEL, 0x0F32) /* "HD Graphics" */ +//#define GMA_VALLEYVIEW_0F33 GFX_MODEL_CONSTRUCT(INTEL, 0x0F33) /* "HD Graphics" */ +//#define GMA_VALLEYVIEW_0155 GFX_MODEL_CONSTRUCT(INTEL, 0x0155) /* "HD Graphics" */ +//#define GMA_VALLEYVIEW_0157 GFX_MODEL_CONSTRUCT(INTEL, 0x0157) /* "HD Graphics" */ /* ==================================== */ /* ============ Haswell =============== */ @@ -216,6 +236,7 @@ #define GMA_HASWELL_ULT_B_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0A0B) #define GMA_HASWELL_ULT_B_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0A1B) #define GMA_HASWELL_ULT_B_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A2B) + #define GMA_HASWELL_ULT_E_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0A0E) // Intel(R) HD Graphics #define GMA_HASWELL_ULT_E_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0A1E) // Intel(R) HD Graphics 4400 #define GMA_HASWELL_ULT_E_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A2E) // Haswell ULT E GT3 @@ -250,61 +271,59 @@ #define GMA_HASWELL_CRW_M_GT2_PLUS_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0D36) // Crystal Well Integrated Graphics Controller #define GMA_HASWELL_CRW_S_GT2_PLUS_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0D3A) -/* Brodwell */ -#define GMA_BRODWELL_BDW_1602 GFX_MODEL_CONSTRUCT(INTEL, 0x1602) // Intel(R) HD Graphics Drivers -#define GMA_BRODWELL_BDW_U_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x1606) // BDW U GT1 -#define GMA_BRODWELL_BDW_160A GFX_MODEL_CONSTRUCT(INTEL, 0x160A) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_160B GFX_MODEL_CONSTRUCT(INTEL, 0x160B) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_160D GFX_MODEL_CONSTRUCT(INTEL, 0x160D) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_160E GFX_MODEL_CONSTRUCT(INTEL, 0x160E) // Intel(R) HD Graphics Drivers -#define GMA_BRODWELL_BDW_1612 GFX_MODEL_CONSTRUCT(INTEL, 0x1612) // Intel(R) HD Graphics 5600 Drivers -#define GMA_BRODWELL_BDW_U_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1616) // BDW U GT2 Intel(R) HD Graphics 5500 Drivers -#define GMA_BRODWELL_BDW_161B GFX_MODEL_CONSTRUCT(INTEL, 0x161B) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_161A GFX_MODEL_CONSTRUCT(INTEL, 0x161A) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_161D GFX_MODEL_CONSTRUCT(INTEL, 0x161D) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_Y_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161E) // BDW Y GT2 Intel(R) HD Graphics 5300 Drivers -#define GMA_BRODWELL_BDW_1622 GFX_MODEL_CONSTRUCT(INTEL, 0x1622) // Intel(R) Iris(TM) Pro Graphics 6200 Drivers -#define GMA_BRODWELL_BDW_162A GFX_MODEL_CONSTRUCT(INTEL, 0x162A) // Intel(R) Iris(TM) Pro Graphics 6300P Drivers -#define GMA_BRODWELL_BDW_U_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x1626) // BDW U GT3 15W Intel(R) HD Graphics 6000 Drivers -#define GMA_BRODWELL_BDW_U_GT3_2 GFX_MODEL_CONSTRUCT(INTEL, 0x162B) // BDW U GT3 28W Intel(R) Iris(TM) Pro Graphics 6100 Drivers -#define GMA_BRODWELL_BDW_162D GFX_MODEL_CONSTRUCT(INTEL, 0x162D) // Intel(R) Iris(TM) Pro Graphics 6300P Drivers -#define GMA_BRODWELL_BDW_162E GFX_MODEL_CONSTRUCT(INTEL, 0x162E) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_1632 GFX_MODEL_CONSTRUCT(INTEL, 0x1632) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_1636 GFX_MODEL_CONSTRUCT(INTEL, 0x1636) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_163A GFX_MODEL_CONSTRUCT(INTEL, 0x163A) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_163B GFX_MODEL_CONSTRUCT(INTEL, 0x163B) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_163D GFX_MODEL_CONSTRUCT(INTEL, 0x163D) // Broadwell-U Integrated Graphics -#define GMA_BRODWELL_BDW_163E GFX_MODEL_CONSTRUCT(INTEL, 0x163E) // Broadwell-U Integrated Graphics +/* Broadwell */ +#define GMA_BROADWELL_BDW_0bd0 GFX_MODEL_CONSTRUCT(INTEL, 0x0bd0) // Intel Broadwell HD Graphics HAS GT0 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_0bd1 GFX_MODEL_CONSTRUCT(INTEL, 0x0bd1) // Intel Broadwell HD Graphics HAS GT1 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_0bd2 GFX_MODEL_CONSTRUCT(INTEL, 0x0bd2) // Intel Broadwell HD Graphics HAS GT2 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_0bd3 GFX_MODEL_CONSTRUCT(INTEL, 0x0bd3) // Intel Broadwell HD Graphics HAS GT3 Drivers +#define GMA_BROADWELL_BDW_0bd4 GFX_MODEL_CONSTRUCT(INTEL, 0x0bd4) // Intel Broadwell HD Graphics HAS GT4 Drivers +#define GMA_BROADWELL_BDW_1602 GFX_MODEL_CONSTRUCT(INTEL, 0x1602) // Intel(R) HD Graphics Drivers // Halo // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_U_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x1606) // BDW U GT1 // ULT // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_160A GFX_MODEL_CONSTRUCT(INTEL, 0x160A) // Broadwell-U Integrated Graphics // Server // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_160B GFX_MODEL_CONSTRUCT(INTEL, 0x160B) // Broadwell-U Integrated Graphics // ULT // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_160D GFX_MODEL_CONSTRUCT(INTEL, 0x160D) // Broadwell-U Integrated Graphics // Workstation // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_160E GFX_MODEL_CONSTRUCT(INTEL, 0x160E) // Intel(R) HD Graphics Drivers // ULX // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_1612 GFX_MODEL_CONSTRUCT(INTEL, 0x1612) // Intel(R) HD Graphics 5600 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_U_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1616) // BDW U GT2 Intel(R) HD Graphics 5500 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_161B GFX_MODEL_CONSTRUCT(INTEL, 0x161B) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_161A GFX_MODEL_CONSTRUCT(INTEL, 0x161A) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_161D GFX_MODEL_CONSTRUCT(INTEL, 0x161D) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_Y_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161E) // BDW Y GT2 Intel(R) HD Graphics 5300 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_1622 GFX_MODEL_CONSTRUCT(INTEL, 0x1622) // Intel(R) Iris(TM) Pro Graphics 6200 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_162A GFX_MODEL_CONSTRUCT(INTEL, 0x162A) // Intel(R) Iris(TM) Pro Graphics 6300P Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_U_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x1626) // BDW U GT3 15W Intel(R) HD Graphics 6000 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_U_GT3_2 GFX_MODEL_CONSTRUCT(INTEL, 0x162B) // BDW U GT3 28W Intel(R) Iris(TM) Pro Graphics 6100 Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_162D GFX_MODEL_CONSTRUCT(INTEL, 0x162D) // Intel(R) Iris(TM) Pro Graphics 6300P Drivers // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_162E GFX_MODEL_CONSTRUCT(INTEL, 0x162E) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_1632 GFX_MODEL_CONSTRUCT(INTEL, 0x1632) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_1636 GFX_MODEL_CONSTRUCT(INTEL, 0x1636) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_163A GFX_MODEL_CONSTRUCT(INTEL, 0x163A) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_163B GFX_MODEL_CONSTRUCT(INTEL, 0x163B) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_163D GFX_MODEL_CONSTRUCT(INTEL, 0x163D) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext +#define GMA_BROADWELL_BDW_163E GFX_MODEL_CONSTRUCT(INTEL, 0x163E) // Broadwell-U Integrated Graphics // AppleIntelBDWGraphics.kext -/* -https://fossies.org/linux/MesaLib/include/pci_ids/i965_pci_ids.h -CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell GT1") -CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell GT1") -CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell GT1") -CHIPSET(0x160B, bdw_gt1, "Intel(R) Broadwell GT1") -CHIPSET(0x160D, bdw_gt1, "Intel(R) Broadwell GT1") -CHIPSET(0x160E, bdw_gt1, "Intel(R) Broadwell GT1") +/* Skylake */ +#define GMA_SKYLAKE_ULT_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x1906) // Intel(R) HD Graphics 510 +#define GMA_SKYLAKE_ULT_GT15 GFX_MODEL_CONSTRUCT(INTEL, 0x1913) // Intel(R) HD Graphics 510 +#define GMA_SKYLAKE_ULT_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1916) // Intel(R) HD Graphics 520 +#define GMA_SKYLAKE_ULX_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x190E) // Intel(R) HD Graphics +#define GMA_SKYLAKE_ULX_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x191E) // Intel(R) HD Graphics 515 +#define GMA_SKYLAKE_DT_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1912) // Intel(R) HD Graphics 530 +#define GMA_SKYLAKE_1921 GFX_MODEL_CONSTRUCT(INTEL, 0x1921) // Intel(R) HD Graphics 520 +#define GMA_SKYLAKE_ULT_GT3_E GFX_MODEL_CONSTRUCT(INTEL, 0x1926) // Intel(R) Iris(TM) Graphics 540 +#define GMA_SKYLAKE_ULT_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x1923) // Intel(R) HD Graphics 535 +#define GMA_SKYLAKE_ULT_GT3_28W GFX_MODEL_CONSTRUCT(INTEL, 0x1927) // Intel(R) Iris(TM) Graphics 550 +#define GMA_SKYLAKE_DT_GT15 GFX_MODEL_CONSTRUCT(INTEL, 0x1917) // Intel(R) HD Graphics 530 +#define GMA_SKYLAKE_DT_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x1902) // Intel(R) HD Graphics 510 +#define GMA_SKYLAKE_DT_GT4 GFX_MODEL_CONSTRUCT(INTEL, 0x1932) // Intel(R) Iris(TM) Pro Graphics 570/580 +#define GMA_SKYLAKE_GT4 GFX_MODEL_CONSTRUCT(INTEL, 0x193B) // Intel(R) Iris(TM) Pro Graphics 580 +#define GMA_SKYLAKE_GT3_FE GFX_MODEL_CONSTRUCT(INTEL, 0x192B) // Intel(R) Iris(TM) Graphics +#define GMA_SKYLAKE_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x191B) // Intel(R) HD Graphics 530 +#define GMA_SKYLAKE_192A GFX_MODEL_CONSTRUCT(INTEL, 0x192A) // Intel(R) Iris(TM) Pro Graphics P580 +#define GMA_SKYLAKE_SRW_GT4 GFX_MODEL_CONSTRUCT(INTEL, 0x193A) // Intel(R) Iris(TM) Pro Graphics P580 +#define GMA_SKYLAKE_WS_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x191D) // Intel(R) HD Graphics P530 +#define GMA_SKYLAKE_WS_GT4 GFX_MODEL_CONSTRUCT(INTEL, 0x193D) // Intel(R) Iris(TM) Pro Graphics P580 -CHIPSET(0x1612, bdw_gt2, "Intel(R) HD Graphics 5600 (Broadwell GT2)") -CHIPSET(0x1616, bdw_gt2, "Intel(R) HD Graphics 5500 (Broadwell GT2)") -CHIPSET(0x161A, bdw_gt2, "Intel(R) Broadwell GT2") -CHIPSET(0x161B, bdw_gt2, "Intel(R) Broadwell GT2") -CHIPSET(0x161D, bdw_gt2, "Intel(R) Broadwell GT2") -CHIPSET(0x161E, bdw_gt2, "Intel(R) HD Graphics 5300 (Broadwell GT2)") - -CHIPSET(0x1622, bdw_gt3, "Intel(R) Iris Pro 6200 (Broadwell GT3e)") -CHIPSET(0x1626, bdw_gt3, "Intel(R) HD Graphics 6000 (Broadwell GT3)") -CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)") -CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)") -CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3") -CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3") -*/ -// 0x0bd0 Intel Broadwell HD Graphics HAS GT0 Drivers -// 0x0bd1 Intel Broadwell HD Graphics HAS GT1 Drivers -// 0x0bd2 Intel Broadwell HD Graphics HAS GT2 Drivers -// 0x0bd3 Intel Broadwell HD Graphics HAS GT3 Drivers -// 0x0bd4 Intel Broadwell HD Graphics HAS GT4 Drivers - /* END */ #endif /* !__LIBSAIO_GMA_H */ Index: branches/zenith432/i386/libsaio/memvendors.h =================================================================== --- branches/zenith432/i386/libsaio/memvendors.h (revision 2804) +++ branches/zenith432/i386/libsaio/memvendors.h (revision 2805) @@ -11,7 +11,7 @@ { uint8_t bank; uint8_t code; - const char* name; + const char *name; } VenIdName; VenIdName vendorMap[] = { Index: branches/zenith432/i386/libsaio/usb.c =================================================================== --- branches/zenith432/i386/libsaio/usb.c (revision 2804) +++ branches/zenith432/i386/libsaio/usb.c (revision 2805) @@ -13,13 +13,13 @@ #include "pci.h" #ifndef DEBUG_USB -#define DEBUG_USB 0 + #define DEBUG_USB 0 #endif #if DEBUG_USB -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) + #define DBG(x...) #endif @@ -39,7 +39,7 @@ // Add usb device to the list void notify_usb_dev(pci_dt_t *pci_dev) { - struct pciList* current = usbList; + struct pciList *current = usbList; if(!usbList) { usbList = (struct pciList*)malloc(sizeof(struct pciList)); @@ -80,7 +80,7 @@ getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->chameleonConfig); } - struct pciList* current = usbList; + struct pciList *current = usbList; while(current) { @@ -124,7 +124,7 @@ int isOSowned; int isBIOSowned; - verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", + verbose("\tSetting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", pci_dev->vendor_id, pci_dev->device_id, pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func); @@ -138,13 +138,13 @@ // eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8 eecp=*((unsigned char*)(capaddr + 9)); - DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp); + DBG("\tcapaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp); usbcmd = *((unsigned int*)(opaddr)); // Command Register usbsts = *((unsigned int*)(opaddr + 4)); // Status Register usbintr = *((unsigned int*)(opaddr + 8)); // Interrupt Enable Register - DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr); + DBG("\tusbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr); // read PCI Config 32bit USBLEGSUP (eecp+0) usblegsup = pci_config_read32(pci_dev->dev.addr, eecp); @@ -156,10 +156,10 @@ // read PCI Config 32bit USBLEGCTLSTS (eecp+4) usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4); - DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts); + DBG("\tusblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts); // Reset registers to Legacy OFF - DBG("Clearing USBLEGCTLSTS\n"); + DBG("\tClearing USBLEGCTLSTS\n"); pci_config_write32(pci_dev->dev.addr, eecp + 4, 0); //usblegctlsts delay(100000); @@ -168,9 +168,9 @@ usbsts = *((unsigned int*)(opaddr + 4)); usbintr = *((unsigned int*)(opaddr + 8)); - DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr); + DBG("\tusbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr); - DBG("Clearing Registers\n"); + DBG("\tClearing Registers\n"); // clear registers to default usbcmd = (usbcmd & 0xffffff00); @@ -196,9 +196,9 @@ // read 32bit USBLEGCTLSTS (eecp+4) usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4); - DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts); + DBG("\tusblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts); - verbose("Legacy USB Off Done\n"); + verbose("\tLegacy USB Off Done\n"); return 1; } @@ -219,7 +219,7 @@ pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002); base = pci_config_read32(pci_dev->dev.addr, 0x10); - verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", + verbose("\tEHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", pci_dev->vendor_id, pci_dev->device_id, pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, base); @@ -235,13 +235,13 @@ return 1; } - DBG("eecp=%x\n",eecp); + DBG("\teecp=%x\n",eecp); // bad way to do it // pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001); for (j = 0; j < 8; j++) { legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); - DBG("%02x ", legacy[j]); + DBG("\t%02x ", legacy[j]); } DBG("\n"); @@ -251,8 +251,8 @@ isOwnershipConflict = (((legacy[3] & 1) != 0) && ((legacy[2] & 1) != 0)); if (!alwaysHardBIOSReset && isOwnershipConflict) { - DBG("EHCI - Ownership conflict - attempting soft reset ...\n"); - DBG("EHCI - toggle OS Ownership to 0\n"); + DBG("\tEHCI - Ownership conflict - attempting soft reset ...\n"); + DBG("\tEHCI - toggle OS Ownership to 0\n"); pci_config_write8(pci_dev->dev.addr, eecp + 3, 0); for (k = 0; k < 25; k++) { for (j = 0; j < 8; j++) { @@ -265,7 +265,7 @@ } } - DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]); + DBG("\tFound USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]); pci_config_write8(pci_dev->dev.addr, eecp + 3, 1); // wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear @@ -273,7 +273,7 @@ for (j = 0;j < 8; j++) { legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); } - DBG ("%x:%x,",legacy[3],legacy[2]); + DBG ("\t%x:%x,",legacy[3],legacy[2]); if (legacy[2] == 0) { break; } @@ -288,16 +288,16 @@ // Soft reset has failed. Assume SMI being ignored // Hard reset // Force Clear BIOS BIT - DBG("EHCI - Ownership conflict - attempting hard reset ...\n"); - DBG ("%x:%x\n",legacy[3],legacy[2]); - DBG("EHCI - Force BIOS Ownership to 0\n"); + DBG("\tEHCI - Ownership conflict - attempting hard reset ...\n"); + DBG ("\t%x:%x\n",legacy[3],legacy[2]); + DBG("\tEHCI - Force BIOS Ownership to 0\n"); pci_config_write8(pci_dev->dev.addr, eecp + 2, 0); for (k = 0; k < 25; k++) { for (j = 0; j < 8; j++) { legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); } - DBG ("%x:%x,",legacy[3],legacy[2]); + DBG ("\t%x:%x,",legacy[3],legacy[2]); if ((legacy[2]) == 0) { break; @@ -314,15 +314,15 @@ legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); } - DBG ("%x:%x\n",legacy[3],legacy[2]); + DBG ("\t%x:%x\n",legacy[3],legacy[2]); // Final Ownership Resolution Check... if (legacy[2] & 1) { - DBG("EHCI controller unable to take control from BIOS\n"); + DBG("\tEHCI controller unable to take control from BIOS\n"); return 0; } - DBG("EHCI Acquire OS Ownership done\n"); + DBG("\tEHCI Acquire OS Ownership done\n"); return 1; } @@ -333,7 +333,7 @@ base = pci_config_read32(pci_dev->dev.addr, 0x20); port_base = (base >> 5) & 0x07ff; - verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", + verbose("\tUHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", pci_dev->vendor_id, pci_dev->device_id, pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, port_base, base); @@ -353,7 +353,7 @@ uint32_t bar0, hccparams1, extendCap, value; int32_t timeOut; - verbose("Setting Legacy USB Off on xHC [%04x:%04x] at %02x:%2x.%x\n", + verbose("\tSetting Legacy USB Off on xHC [%04x:%04x] at %02x:%2x.%x\n", pci_dev->vendor_id, pci_dev->device_id, pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func); @@ -363,7 +363,7 @@ */ if (bar0 & 1) { - DBG("%s: BAR0 not a memory range\n", __FUNCTION__); + DBG("\t%s: BAR0 not a memory range\n", __FUNCTION__); return 0; } /* @@ -372,7 +372,7 @@ if (((bar0 & 6) == 4) && pci_config_read32(pci_dev->dev.addr, 20)) { - DBG("%s: BAR0 outside 32-bit physical address space\n", __FUNCTION__); + DBG("\t%s: BAR0 outside 32-bit physical address space\n", __FUNCTION__); return 0; } bar0 &= ~15; @@ -380,7 +380,7 @@ hccparams1 = *(uint32_t const volatile*) (bar0 + 16); if (hccparams1 == ~0) { - DBG("%s: hccparams1 invalid 0x%x\n", __FUNCTION__, hccparams1); + DBG("\t%s: hccparams1 invalid 0x%x\n", __FUNCTION__, hccparams1); return 0; } extendCap = (hccparams1 >> 14) & 0x3fffc; @@ -392,7 +392,7 @@ } if ((value & 0xff) == 1) { #if DEBUG_USB - verbose("%s: Found USBLEGSUP 0x%x, USBLEGCTLSTS 0x%x\n", __FUNCTION__, + verbose("\t%s: Found USBLEGSUP 0x%x, USBLEGCTLSTS 0x%x\n", __FUNCTION__, value, *(uint32_t const volatile*) (bar0 + extendCap + 4)); #endif value |= (1 << 24); @@ -414,7 +414,7 @@ } } #if DEBUG_USB - verbose("%s: USBLEGSUP 0x%x, USBLEGCTLSTS 0x%x\n", __FUNCTION__, + verbose("\t%s: USBLEGSUP 0x%x, USBLEGCTLSTS 0x%x\n", __FUNCTION__, value, *(uint32_t const volatile*) (bar0 + extendCap + 4)); #endif if (timeOut >= 0) @@ -438,6 +438,6 @@ break; extendCap += ((value >> 6) & 0x3fc); } - verbose("XHCI Legacy Off Done\n"); + verbose("\tXHCI Legacy Off Done\n"); return 1; } Index: branches/zenith432/i386/libsaio/device_inject.c =================================================================== --- branches/zenith432/i386/libsaio/device_inject.c (revision 2804) +++ branches/zenith432/i386/libsaio/device_inject.c (revision 2805) @@ -14,19 +14,20 @@ #include "convert.h" #ifndef DEBUG_INJECT -#define DEBUG_INJECT 0 + #define DEBUG_INJECT 0 #endif #if DEBUG_INJECT -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) msglog(x) + #define DBG(x...) msglog(x) #endif -uint32_t devices_number = 1; -uint32_t builtin_set = 0; -DevPropString *string = 0; -uint8_t *stringdata = 0; +uint32_t devices_number = 1; // nvidia.c +uint32_t location_number = 1; // networking.c + +DevPropString *string = NULL; +uint8_t *stringdata = NULL; uint32_t stringlength = 0; char *efi_inject_get_devprop_string(uint32_t *len) @@ -57,7 +58,7 @@ */ if (!getValueForKey(kDeviceProperties, &val, &cnt, &bootInfo->chameleonConfig) && string) { - val = (const char*)string; + val = (const char *)string; cnt = strlength * 2; } @@ -67,7 +68,7 @@ if (cnt2 > 0) { DT__AddProperty(node, DEVICE_PROPERTIES_PROP, cnt2, binStr); - DBG("Adding device-properties string to DT"); + DBG("Adding device-properties string to DT\n"); } } } @@ -230,7 +231,7 @@ memset(data, 0, length); uint32_t off = 0; - data[off+1] = ((strlen(nm) * 2) + 6) >> 8; + data[off+1] = (uint8_t)(((strlen(nm) * 2) + 6) >> 8); data[off] = ((strlen(nm) * 2) + 6) & 0x00FF; off += 4; @@ -290,8 +291,8 @@ // devprop_generate_string optimized by cparm char *devprop_generate_string(DevPropString *string) { - int len = string->length * 2; - char *buffer = (char*)malloc(len); + int len = ((string->length * 2) + 1); + char *buffer = (char *)malloc(len); char *ptr = buffer; if(!buffer) @@ -400,89 +401,6 @@ /* ======================================================= */ - -/******************************************************************* - * Decodes a sequence of 'len' hexadecimal chars from 'hex' into * - * a binary. returns -1 in case of error (i.e. badly formed chars) * - *******************************************************************/ -int hex2bin(const char *hex, uint8_t *bin, int len) -{ - char *p; - int i; - char buf[3]; - - if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) - { - printf("[ERROR] bin2hex input error\n"); - return -1; - } - - buf[2] = '\0'; - p = (char *) hex; - - for (i = 0; i < len; i++) - { - if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) - { - printf("[ERROR] bin2hex '%s' syntax error\n", hex); - return -2; - } - buf[0] = *p++; - buf[1] = *p++; - bin[i] = (unsigned char) strtoul(buf, NULL, 16); - } - return 0; -} - -/* ======================================================= */ - /* a fine place for this code */ -int devprop_add_network_template(DevPropDevice *device, uint16_t vendor_id) -{ - if(!device) - { - return 0; - } - - uint8_t builtin = 0x0; - if((vendor_id != 0x168c) && (builtin_set == 0)) - { - builtin_set = 1; - builtin = 0x01; - } - - if(!devprop_add_value(device, "built-in", (uint8_t*)&builtin, 1)) - { - return 0; - } - - devices_number++; - return 1; -} - -void set_eth_builtin(pci_dt_t *eth_dev) -{ - char *devicepath = get_pci_dev_path(eth_dev); - DevPropDevice *device = NULL; - - verbose("LAN Controller [%04x:%04x] :: %s\n", eth_dev->vendor_id, eth_dev->device_id, devicepath); - - if(!string) - { - string = devprop_create_string(); - } - - device = devprop_add_device(string, devicepath); - if(device) - { - verbose("Setting up lan keys\n"); - devprop_add_network_template(device, eth_dev->vendor_id); - stringdata = (uint8_t*)malloc(sizeof(uint8_t) * string->length); - if(stringdata) - { - memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); - stringlength = string->length; - } - } -} +// (devprop_add_network_template) and (setup_eth_builtin) moved to i386/libsaio/networking.c Index: branches/zenith432/i386/libsaio/hda.c =================================================================== --- branches/zenith432/i386/libsaio/hda.c (revision 2804) +++ branches/zenith432/i386/libsaio/hda.c (revision 2805) @@ -62,28 +62,49 @@ #include "boot.h" #include "bootstruct.h" +#include "cpu.h" #include "pci.h" #include "pci_root.h" #include "platform.h" #include "device_inject.h" +#include "convert.h" #include "hda.h" -//#include "aml_generator.h" +#define STRINGIFY(x) #x +#define TOSTRING(x) STRINGIFY(x) + +#define HEADER __FILE__ " [" TOSTRING(__LINE__) "]: " + #ifndef DEBUG_HDA -#define DEBUG_HDA 0 + #define DEBUG_HDA 0 #endif #if DEBUG_HDA -#define DBG(x...) verbose(x) + #define DBG(x...) verbose(x) #else -#define DBG(x...) + #define DBG(x...) #endif -extern uint32_t devices_number; +#ifndef DEBUG_CODEC + #define DEBUG_CODEC 0 +#endif +#if DEBUG_CODEC + #define CDBG(x...) verbose(x) +#else + #define CDBG(x...) +#endif + +#define UNKNOWN "Unknown " + +#define hdacc_lock(codec) snd_mtxlock((codec)->lock) +#define hdacc_unlock(codec) snd_mtxunlock((codec)->lock) +#define hdacc_lockassert(codec) snd_mtxassert((codec)->lock) +#define hdacc_lockowned(codec) mtx_owned((codec)->lock) + const char *hda_slot_name[] = { "AAPL,slot-name", "Built In" }; -uint8_t default_HDEF_layout_id[] = {0x0C, 0x00, 0x00, 0x00}; +uint8_t default_HDEF_layout_id[] = {0x01, 0x00, 0x00, 0x00}; #define HDEF_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) ) uint8_t default_HDAU_layout_id[] = {0x01, 0x00, 0x00, 0x00}; #define HDAU_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) ) @@ -93,31 +114,38 @@ static hda_controller_devices know_hda_controller[] = { //8086 Intel Corporation - { HDA_INTEL_OAK, "Oaktrail" /*, 0, 0 */ }, - { HDA_INTEL_BAY, "BayTrail" /*, 0, 0 */ }, - { HDA_INTEL_HSW1, "Haswell" /*, 0, 0 */ }, - { HDA_INTEL_HSW2, "Haswell" /*, 0, 0 */ }, - { HDA_INTEL_HSW3, "Haswell" /*, 0, 0 */ }, - { HDA_INTEL_CPT, "Cougar Point" /*, 0, 0 */ }, - { HDA_INTEL_PATSBURG, "Patsburg" /*, 0, 0 */ }, - { HDA_INTEL_PPT1, "Panther Point" /*, 0, 0 */ }, - { HDA_INTEL_LPT1, "Lynx Point" /*, 0, 0 */ }, - { HDA_INTEL_LPT2, "Lynx Point" /*, 0, 0 */ }, - { HDA_INTEL_WCPT, "Wildcat Point" /*, 0, 0 */ }, - { HDA_INTEL_WELLS1, "Wellsburg" /*, 0, 0 */ }, - { HDA_INTEL_WELLS2, "Wellsburg" /*, 0, 0 */ }, - { HDA_INTEL_LPTLP1, "Lynx Point-LP" /*, 0, 0 */ }, - { HDA_INTEL_LPTLP2, "Lynx Point-LP" /*, 0, 0 */ }, - { HDA_INTEL_82801F, "82801F" /*, 0, 0 */ }, - { HDA_INTEL_63XXESB, "631x/632xESB" /*, 0, 0 */ }, - { HDA_INTEL_82801G, "82801G" /*, 0, 0 */ }, - { HDA_INTEL_82801H, "82801H" /*, 0, 0 */ }, - { HDA_INTEL_82801I, "82801I" /*, 0, 0 */ }, - { HDA_INTEL_82801JI, "82801JI" /*, 0, 0 */ }, - { HDA_INTEL_82801JD, "82801JD" /*, 0, 0 */ }, - { HDA_INTEL_PCH, "5 Series/3400 Series" /*, 0, 0 */ }, - { HDA_INTEL_PCH2, "5 Series/3400 Series" /*, 0, 0 */ }, - { HDA_INTEL_SCH, "SCH" /*, 0, 0 */ }, + { HDA_INTEL_OAK, "Oaktrail" /*, 0, 0 */ }, + { HDA_INTEL_BAY, "BayTrail" /*, 0, 0 */ }, + { HDA_INTEL_HSW1, "Haswell" /*, 0, 0 */ }, + { HDA_INTEL_HSW2, "Haswell" /*, 0, 0 */ }, + { HDA_INTEL_HSW3, "Haswell" /*, 0, 0 */ }, + { HDA_INTEL_BDW, "Broadwell" /*, 0, 0 */ }, + { HDA_INTEL_CPT, "Cougar Point" /*, 0, 0 */ }, + { HDA_INTEL_PATSBURG, "Patsburg" /*, 0, 0 */ }, + { HDA_INTEL_PPT1, "Panther Point" /*, 0, 0 */ }, + { HDA_INTEL_BRASWELL, "Braswell" /*, 0, 0 */ }, + { HDA_INTEL_82801F, "82801F" /*, 0, 0 */ }, + { HDA_INTEL_63XXESB, "631x/632xESB" /*, 0, 0 */ }, + { HDA_INTEL_82801G, "82801G" /*, 0, 0 */ }, + { HDA_INTEL_82801H, "82801H" /*, 0, 0 */ }, + { HDA_INTEL_82801I, "82801I" /*, 0, 0 */ }, + { HDA_INTEL_ICH9, "ICH9" /*, 0, 0 */ }, + { HDA_INTEL_82801JI, "82801JI" /*, 0, 0 */ }, + { HDA_INTEL_82801JD, "82801JD" /*, 0, 0 */ }, + { HDA_INTEL_PCH, "5 Series/3400 Series" /*, 0, 0 */ }, + { HDA_INTEL_PCH2, "5 Series/3400 Series" /*, 0, 0 */ }, + { HDA_INTEL_SCH, "SCH" /*, 0, 0 */ }, + { HDA_INTEL_LPT1, "Lynx Point" /*, 0, 0 */ }, + { HDA_INTEL_LPT2, "Lynx Point" /*, 0, 0 */ }, + { HDA_INTEL_WCPT, "Wildcat Point" /*, 0, 0 */ }, + { HDA_INTEL_WELLS1, "Wellsburg" /*, 0, 0 */ }, + { HDA_INTEL_WELLS2, "Wellsburg" /*, 0, 0 */ }, + { HDA_INTEL_WCPTLP, "Wildcat Point-LP" /*, 0, 0 */ }, + { HDA_INTEL_LPTLP1, "Lynx Point-LP" /*, 0, 0 */ }, + { HDA_INTEL_LPTLP2, "Lynx Point-LP" /*, 0, 0 */ }, + { HDA_INTEL_SRSPLP, "Sunrise Point-LP" /*, 0, 0 */ }, + { HDA_INTEL_SRSP, "Sunrise Point" /*, 0, 0 */ }, + //10de NVIDIA Corporation { HDA_NVIDIA_MCP51, "MCP51" /*, 0, HDAC_QUIRK_MSI */ }, { HDA_NVIDIA_MCP55, "MCP55" /*, 0, HDAC_QUIRK_MSI */ }, @@ -156,10 +184,12 @@ { HDA_NVIDIA_GK106, "GK106" /*, 0, ? */ }, { HDA_NVIDIA_GK107, "GK107" /*, 0, ? */ }, { HDA_NVIDIA_GK104, "GK104" /*, 0, ? */ }, + //1002 Advanced Micro Devices [AMD] nee ATI Technologies Inc { HDA_ATI_SB450, "SB4x0" /*, 0, 0 */ }, { HDA_ATI_SB600, "SB600" /*, 0, 0 */ }, { HDA_ATI_RS600, "RS600" /*, 0, 0 */ }, + { HDA_ATI_HUDSON, "Hudson" /*, 0, 0 */ }, { HDA_ATI_RS690, "RS690" /*, 0, 0 */ }, { HDA_ATI_RS780, "RS780" /*, 0, 0 */ }, { HDA_ATI_RS880, "RS880" /*, 0, 0 */ }, @@ -182,15 +212,21 @@ { HDA_ATI_RV940, "RV940" /*, 0, 0 */ }, { HDA_ATI_RV970, "RV970" /*, 0, 0 */ }, { HDA_ATI_R1000, "R1000" /*, 0, 0 */ }, // HDMi + { HDA_ATI_SI, "SI" /*, 0, 0 */ }, { HDA_ATI_VERDE, "Cape Verde" /*, 0, ? */ }, // HDMi + //17f3 RDC Semiconductor, Inc. { HDA_RDC_M3010, "M3010" /*, 0, 0 */ }, + //1106 VIA Technologies, Inc. { HDA_VIA_VT82XX, "VT8251/8237A" /*, 0, 0 */ }, + //1039 Silicon Integrated Systems [SiS] { HDA_SIS_966, "966" /*, 0, 0 */ }, + //10b9 ULi Electronics Inc.(Split off ALi Corporation in 2003) { HDA_ULI_M5461, "M5461" /*, 0, 0 */ }, + /* Unknown */ { HDA_INTEL_ALL, "Unknown Intel device" /*, 0, 0 */ }, { HDA_NVIDIA_ALL, "Unknown NVIDIA device" /*, 0, 0 */ }, @@ -202,262 +238,349 @@ #define HDAC_DEVICES_LEN (sizeof(know_hda_controller) / sizeof(know_hda_controller[0])) /* CODECs */ +/* + * ErmaC: There's definitely a lot of different versions of the same audio codec variant out there... + * in the next struct you will find a "generic" but IMHO detailed list of + * possible codec... anyway to specific a new one or find difference beetween revision + * check it under linux enviroment with: + * $cat /proc/asound/Intel/codec#0 + * -------------------------------- + * Codec: Analog Devices AD1989B + * Address: 0 + * AFG Function Id: 0x1 (unsol 0) + * Vendor Id: 0x11d4989b + * Subsystem Id: 0x10438372 + * Revision Id: 0x100300 + * -------------------------------- + * or + * $cat /proc/asound/NVidia/codec#0 + * -------------------------------- + * Codec: Nvidia GPU 14 HDMI/DP + * Address: 0 + * AFG Function Id: 0x1 (unsol 0) + * Vendor Id: 0x10de0014 + * Subsystem Id: 0x10de0101 + * Revision Id: 0x100100 + * -------------------------------- + */ -// ErmaC: TODO build function to probe the codecID -/* static hdacc_codecs know_codecs[] = { - { HDA_CODEC_CS4206, 0, "Cirrus Logic CS4206" }, - { HDA_CODEC_CS4207, 0, "Cirrus Logic CS4207" }, - { HDA_CODEC_CS4210, 0, "Cirrus Logic CS4210" }, - { HDA_CODEC_ALC221, 0, "Realtek ALC221" }, - { HDA_CODEC_ALC260, 0, "Realtek ALC260" }, - { HDA_CODEC_ALC262, 0, "Realtek ALC262" }, - { HDA_CODEC_ALC267, 0, "Realtek ALC267" }, - { HDA_CODEC_ALC268, 0, "Realtek ALC268" }, - { HDA_CODEC_ALC269, 0, "Realtek ALC269" }, - { HDA_CODEC_ALC270, 0, "Realtek ALC270" }, - { HDA_CODEC_ALC272, 0, "Realtek ALC272" }, - { HDA_CODEC_ALC273, 0, "Realtek ALC273" }, - { HDA_CODEC_ALC275, 0, "Realtek ALC275" }, - { HDA_CODEC_ALC276, 0, "Realtek ALC276" }, - { HDA_CODEC_ALC660, 0, "Realtek ALC660-VD" }, - { HDA_CODEC_ALC662, 0x0002, "Realtek ALC662 rev2" }, - { HDA_CODEC_ALC662, 0, "Realtek ALC662" }, - { HDA_CODEC_ALC663, 0, "Realtek ALC663" }, - { HDA_CODEC_ALC665, 0, "Realtek ALC665" }, - { HDA_CODEC_ALC670, 0, "Realtek ALC670" }, - { HDA_CODEC_ALC680, 0, "Realtek ALC680" }, - { HDA_CODEC_ALC861, 0x0340, "Realtek ALC660" }, - { HDA_CODEC_ALC861, 0, "Realtek ALC861" }, - { HDA_CODEC_ALC861VD, 0, "Realtek ALC861-VD" }, - { HDA_CODEC_ALC880, 0, "Realtek ALC880" }, - { HDA_CODEC_ALC882, 0, "Realtek ALC882" }, - { HDA_CODEC_ALC883, 0, "Realtek ALC883" }, - { HDA_CODEC_ALC885, 0x0101, "Realtek ALC889A" }, - { HDA_CODEC_ALC885, 0x0103, "Realtek ALC889A" }, - { HDA_CODEC_ALC885, 0, "Realtek ALC885" }, - { HDA_CODEC_ALC887, 0, "Realtek ALC887" }, - { HDA_CODEC_ALC888, 0x0101, "Realtek ALC1200" }, - { HDA_CODEC_ALC888, 0, "Realtek ALC888" }, - { HDA_CODEC_ALC889, 0, "Realtek ALC889" }, - { HDA_CODEC_ALC892, 0, "Realtek ALC892" }, - { HDA_CODEC_ALC898, 0, "Realtek ALC898" }, - { HDA_CODEC_ALC899, 0, "Realtek ALC899" }, - { HDA_CODEC_ALC900, 0, "Realtek ALC1150" }, + { HDA_CODEC_CS4206, 0, "CS4206" }, + { HDA_CODEC_CS4207, 0, "CS4207" }, + { HDA_CODEC_CS4208, 0, "CS4208" }, + { HDA_CODEC_CS4210, 0, "CS4210" }, + { HDA_CODEC_CS4213, 0, "CS4213" }, - { HDA_CODEC_AD1882, 0, "Analog Devices AD1882" }, - { HDA_CODEC_AD1882A, 0, "Analog Devices AD1882A" }, - { HDA_CODEC_AD1883, 0, "Analog Devices AD1883" }, - { HDA_CODEC_AD1884, 0, "Analog Devices AD1884" }, - { HDA_CODEC_AD1884A, 0, "Analog Devices AD1884A" }, - { HDA_CODEC_AD1981HD, 0, "Analog Devices AD1981HD" }, - { HDA_CODEC_AD1983, 0, "Analog Devices AD1983" }, - { HDA_CODEC_AD1984, 0, "Analog Devices AD1984" }, - { HDA_CODEC_AD1984A, 0, "Analog Devices AD1984A" }, - { HDA_CODEC_AD1984B, 0, "Analog Devices AD1984B" }, - { HDA_CODEC_AD1986A, 0, "Analog Devices AD1986A" }, - { HDA_CODEC_AD1987, 0, "Analog Devices AD1987" }, - { HDA_CODEC_AD1988, 0, "Analog Devices AD1988A" }, - { HDA_CODEC_AD1988B, 0, "Analog Devices AD1988B" }, - { HDA_CODEC_AD1989A, 0, "Analog Devices AD1989A" }, - { HDA_CODEC_AD1989B, 0, "Analog Devices AD1989B" }, - { HDA_CODEC_CA0110, 0, "Creative CA0110-IBG" }, - { HDA_CODEC_CA0110_2, 0, "Creative CA0110-IBG" }, + { HDA_CODEC_ALC221, 0, "ALC221" }, + { HDA_CODEC_ALC231, 0, "ALC231" }, + { HDA_CODEC_ALC233, 0, "ALC233" }, + { HDA_CODEC_ALC235, 0, "ALC235" }, + { HDA_CODEC_ALC255, 0, "ALC255" }, + { HDA_CODEC_ALC256, 0, "ALC256" }, + { HDA_CODEC_ALC260, 0, "ALC260" }, +// { HDA_CODEC_ALC262, 0x0100, "ALC262" }, // Revision Id: 0x100100 + { HDA_CODEC_ALC262, 0, "ALC262" }, + { HDA_CODEC_ALC267, 0, "ALC267" }, + { HDA_CODEC_ALC268, 0, "ALC268" }, + { HDA_CODEC_ALC269, 0, "ALC269" }, + { HDA_CODEC_ALC270, 0, "ALC270" }, + { HDA_CODEC_ALC272, 0, "ALC272" }, + { HDA_CODEC_ALC273, 0, "ALC273" }, + { HDA_CODEC_ALC275, 0, "ALC275" }, + { HDA_CODEC_ALC276, 0, "ALC276" }, + { HDA_CODEC_ALC280, 0, "ALC280" }, + { HDA_CODEC_ALC282, 0, "ALC282" }, + { HDA_CODEC_ALC283, 0, "ALC283" }, + { HDA_CODEC_ALC284, 0, "ALC284" }, + { HDA_CODEC_ALC285, 0, "ALC285" }, + { HDA_CODEC_ALC286, 0, "ALC286" }, + { HDA_CODEC_ALC288, 0, "ALC288" }, + { HDA_CODEC_ALC290, 0, "ALC290" }, + { HDA_CODEC_ALC292, 0, "ALC292" }, + { HDA_CODEC_ALC293, 0, "ALC293" }, + { HDA_CODEC_ALC298, 0, "ALC298" }, + { HDA_CODEC_ALC660, 0, "ALC660-VD" }, + { HDA_CODEC_ALC662, 0, "ALC662" }, + { HDA_CODEC_ALC662, 0x0101, "ALC662 rev1" }, + { HDA_CODEC_ALC662, 0x0002, "ALC662 rev2" }, + { HDA_CODEC_ALC662, 0x0300, "ALC662 rev3" }, + { HDA_CODEC_ALC663, 0, "ALC663" }, + { HDA_CODEC_ALC665, 0, "ALC665" }, + { HDA_CODEC_ALC667, 0, "ALC667" }, + { HDA_CODEC_ALC668, 0, "ALC668" }, + { HDA_CODEC_ALC670, 0, "ALC670" }, + { HDA_CODEC_ALC671, 0, "ALC671" }, + { HDA_CODEC_ALC680, 0, "ALC680" }, + { HDA_CODEC_ALC861, 0x0340, "ALC660" }, + { HDA_CODEC_ALC861, 0, "ALC861" }, + { HDA_CODEC_ALC861VD, 0, "ALC861-VD" }, + { HDA_CODEC_ALC867, 0, "ALC891" }, +// { HDA_CODEC_ALC880, 0x0800, "ALC880" }, // Revision Id: 0x100800 + { HDA_CODEC_ALC880, 0, "ALC880" }, + { HDA_CODEC_ALC882, 0, "ALC882" }, + { HDA_CODEC_ALC883, 0, "ALC883" }, + { HDA_CODEC_ALC885, 0x0101, "ALC889A" }, // Revision Id: 0x100101 + { HDA_CODEC_ALC885, 0x0103, "ALC889A" }, // Revision Id: 0x100103 + { HDA_CODEC_ALC885, 0, "ALC885" }, + { HDA_CODEC_ALC886, 0, "ALC886" }, + { HDA_CODEC_ALC887, 0, "ALC887" }, + { HDA_CODEC_ALC888, 0x0101, "ALC1200" }, // Revision Id: 0x100101 + { HDA_CODEC_ALC888, 0, "ALC888" }, + { HDA_CODEC_ALC889, 0, "ALC889" }, + { HDA_CODEC_ALC892, 0, "ALC892" }, + { HDA_CODEC_ALC898, 0, "ALC898" }, + { HDA_CODEC_ALC899, 0, "ALC899" }, + { HDA_CODEC_ALC900, 0, "ALC1150" }, + + { HDA_CODEC_AD1882, 0, "AD1882" }, + { HDA_CODEC_AD1882A, 0, "AD1882A" }, + { HDA_CODEC_AD1883, 0, "AD1883" }, + { HDA_CODEC_AD1884, 0, "AD1884" }, + { HDA_CODEC_AD1884A, 0, "AD1884A" }, + { HDA_CODEC_AD1981HD, 0, "AD1981HD" }, + { HDA_CODEC_AD1983, 0, "AD1983" }, + { HDA_CODEC_AD1984, 0, "AD1984" }, + { HDA_CODEC_AD1984A, 0, "AD1984A" }, + { HDA_CODEC_AD1984B, 0, "AD1984B" }, + { HDA_CODEC_AD1986A, 0, "AD1986A" }, + { HDA_CODEC_AD1987, 0, "AD1987" }, + { HDA_CODEC_AD1988, 0, "AD1988A" }, + { HDA_CODEC_AD1988B, 0, "AD1988B" }, + { HDA_CODEC_AD1989A, 0, "AD1989A" }, + { HDA_CODEC_AD1989B, 0x0200, "AD2000B" }, // Revision Id: 0x100200 + { HDA_CODEC_AD1989B, 0x0300, "AD2000B" }, // Revision Id: 0x100300 + { HDA_CODEC_AD1989B, 0, "AD1989B" }, + + { HDA_CODEC_XFIEA, 0, "Creative X-Fi Extreme A" }, + { HDA_CODEC_XFIED, 0, "Creative X-Fi Extreme D" }, { HDA_CODEC_CA0132, 0, "Creative CA0132" }, { HDA_CODEC_SB0880, 0, "Creative SB0880 X-Fi" }, { HDA_CODEC_CMI9880, 0, "CMedia CMI9880" }, { HDA_CODEC_CMI98802, 0, "CMedia CMI9880" }, - { HDA_CODEC_CXD9872RDK, 0, "Sigmatel CXD9872RD/K" }, - { HDA_CODEC_CXD9872AKD, 0, "Sigmatel CXD9872AKD" }, - { HDA_CODEC_STAC9200D, 0, "Sigmatel STAC9200D" }, - { HDA_CODEC_STAC9204X, 0, "Sigmatel STAC9204X" }, - { HDA_CODEC_STAC9204D, 0, "Sigmatel STAC9204D" }, - { HDA_CODEC_STAC9205X, 0, "Sigmatel STAC9205X" }, - { HDA_CODEC_STAC9205D, 0, "Sigmatel STAC9205D" }, - { HDA_CODEC_STAC9220, 0, "Sigmatel STAC9220" }, - { HDA_CODEC_STAC9220_A1, 0, "Sigmatel STAC9220_A1" }, - { HDA_CODEC_STAC9220_A2, 0, "Sigmatel STAC9220_A2" }, - { HDA_CODEC_STAC9221, 0, "Sigmatel STAC9221" }, - { HDA_CODEC_STAC9221_A2, 0, "Sigmatel STAC9221_A2" }, - { HDA_CODEC_STAC9221D, 0, "Sigmatel STAC9221D" }, - { HDA_CODEC_STAC922XD, 0, "Sigmatel STAC9220D/9223D" }, - { HDA_CODEC_STAC9227X, 0, "Sigmatel STAC9227X" }, - { HDA_CODEC_STAC9227D, 0, "Sigmatel STAC9227D" }, - { HDA_CODEC_STAC9228X, 0, "Sigmatel STAC9228X" }, - { HDA_CODEC_STAC9228D, 0, "Sigmatel STAC9228D" }, - { HDA_CODEC_STAC9229X, 0, "Sigmatel STAC9229X" }, - { HDA_CODEC_STAC9229D, 0, "Sigmatel STAC9229D" }, - { HDA_CODEC_STAC9230X, 0, "Sigmatel STAC9230X" }, - { HDA_CODEC_STAC9230D, 0, "Sigmatel STAC9230D" }, - { HDA_CODEC_STAC9250, 0, "Sigmatel STAC9250" }, - { HDA_CODEC_STAC9251, 0, "Sigmatel STAC9251" }, - { HDA_CODEC_STAC9255, 0, "Sigmatel STAC9255" }, - { HDA_CODEC_STAC9255D, 0, "Sigmatel STAC9255D" }, - { HDA_CODEC_STAC9254, 0, "Sigmatel STAC9254" }, - { HDA_CODEC_STAC9254D, 0, "Sigmatel STAC9254D" }, - { HDA_CODEC_STAC9271X, 0, "Sigmatel STAC9271X" }, - { HDA_CODEC_STAC9271D, 0, "Sigmatel STAC9271D" }, - { HDA_CODEC_STAC9272X, 0, "Sigmatel STAC9272X" }, - { HDA_CODEC_STAC9272D, 0, "Sigmatel STAC9272D" }, - { HDA_CODEC_STAC9273X, 0, "Sigmatel STAC9273X" }, - { HDA_CODEC_STAC9273D, 0, "Sigmatel STAC9273D" }, - { HDA_CODEC_STAC9274, 0, "Sigmatel STAC9274" }, - { HDA_CODEC_STAC9274D, 0, "Sigmatel STAC9274D" }, - { HDA_CODEC_STAC9274X5NH, 0, "Sigmatel STAC9274X5NH" }, - { HDA_CODEC_STAC9274D5NH, 0, "Sigmatel STAC9274D5NH" }, - { HDA_CODEC_STAC9872AK, 0, "Sigmatel STAC9872AK" }, - { HDA_CODEC_IDT92HD005, 0, "IDT 92HD005" }, - { HDA_CODEC_IDT92HD005D, 0, "IDT 92HD005D" }, - { HDA_CODEC_IDT92HD206X, 0, "IDT 92HD206X" }, - { HDA_CODEC_IDT92HD206D, 0, "IDT 92HD206D" }, - { HDA_CODEC_IDT92HD66B1X5, 0, "IDT 92HD66B1X5" }, - { HDA_CODEC_IDT92HD66B2X5, 0, "IDT 92HD66B2X5" }, - { HDA_CODEC_IDT92HD66B3X5, 0, "IDT 92HD66B3X5" }, - { HDA_CODEC_IDT92HD66C1X5, 0, "IDT 92HD66C1X5" }, - { HDA_CODEC_IDT92HD66C2X5, 0, "IDT 92HD66C2X5" }, - { HDA_CODEC_IDT92HD66C3X5, 0, "IDT 92HD66C3X5" }, - { HDA_CODEC_IDT92HD66B1X3, 0, "IDT 92HD66B1X3" }, - { HDA_CODEC_IDT92HD66B2X3, 0, "IDT 92HD66B2X3" }, - { HDA_CODEC_IDT92HD66B3X3, 0, "IDT 92HD66B3X3" }, - { HDA_CODEC_IDT92HD66C1X3, 0, "IDT 92HD66C1X3" }, - { HDA_CODEC_IDT92HD66C2X3, 0, "IDT 92HD66C2X3" }, - { HDA_CODEC_IDT92HD66C3_65, 0, "IDT 92HD66C3_65" }, - { HDA_CODEC_IDT92HD700X, 0, "IDT 92HD700X" }, - { HDA_CODEC_IDT92HD700D, 0, "IDT 92HD700D" }, - { HDA_CODEC_IDT92HD71B5, 0, "IDT 92HD71B5" }, - { HDA_CODEC_IDT92HD71B5_2, 0, "IDT 92HD71B5" }, - { HDA_CODEC_IDT92HD71B6, 0, "IDT 92HD71B6" }, - { HDA_CODEC_IDT92HD71B6_2, 0, "IDT 92HD71B6" }, - { HDA_CODEC_IDT92HD71B7, 0, "IDT 92HD71B7" }, - { HDA_CODEC_IDT92HD71B7_2, 0, "IDT 92HD71B7" }, - { HDA_CODEC_IDT92HD71B8, 0, "IDT 92HD71B8" }, - { HDA_CODEC_IDT92HD71B8_2, 0, "IDT 92HD71B8" }, - { HDA_CODEC_IDT92HD73C1, 0, "IDT 92HD73C1" }, - { HDA_CODEC_IDT92HD73D1, 0, "IDT 92HD73D1" }, - { HDA_CODEC_IDT92HD73E1, 0, "IDT 92HD73E1" }, - { HDA_CODEC_IDT92HD75B3, 0, "IDT 92HD75B3" }, - { HDA_CODEC_IDT92HD75BX, 0, "IDT 92HD75BX" }, - { HDA_CODEC_IDT92HD81B1C, 0, "IDT 92HD81B1C" }, - { HDA_CODEC_IDT92HD81B1X, 0, "IDT 92HD81B1X" }, - { HDA_CODEC_IDT92HD83C1C, 0, "IDT 92HD83C1C" }, - { HDA_CODEC_IDT92HD83C1X, 0, "IDT 92HD83C1X" }, - { HDA_CODEC_IDT92HD87B1_3, 0, "IDT 92HD87B1/3" }, - { HDA_CODEC_IDT92HD87B2_4, 0, "IDT 92HD87B2/4" }, - { HDA_CODEC_IDT92HD89C3, 0, "IDT 92HD89C3" }, - { HDA_CODEC_IDT92HD89C2, 0, "IDT 92HD89C2" }, - { HDA_CODEC_IDT92HD89C1, 0, "IDT 92HD89C1" }, - { HDA_CODEC_IDT92HD89B3, 0, "IDT 92HD89B3" }, - { HDA_CODEC_IDT92HD89B2, 0, "IDT 92HD89B2" }, - { HDA_CODEC_IDT92HD89B1, 0, "IDT 92HD89B1" }, - { HDA_CODEC_IDT92HD89E3, 0, "IDT 92HD89E3" }, - { HDA_CODEC_IDT92HD89E2, 0, "IDT 92HD89E2" }, - { HDA_CODEC_IDT92HD89E1, 0, "IDT 92HD89E1" }, - { HDA_CODEC_IDT92HD89D3, 0, "IDT 92HD89D3" }, - { HDA_CODEC_IDT92HD89D2, 0, "IDT 92HD89D2" }, - { HDA_CODEC_IDT92HD89D1, 0, "IDT 92HD89D1" }, - { HDA_CODEC_IDT92HD89F3, 0, "IDT 92HD89F3" }, - { HDA_CODEC_IDT92HD89F2, 0, "IDT 92HD89F2" }, - { HDA_CODEC_IDT92HD89F1, 0, "IDT 92HD89F1" }, - { HDA_CODEC_IDT92HD90BXX, 0, "IDT 92HD90BXX" }, - { HDA_CODEC_IDT92HD91BXX, 0, "IDT 92HD91BXX" }, - { HDA_CODEC_IDT92HD93BXX, 0, "IDT 92HD93BXX" }, - { HDA_CODEC_IDT92HD98BXX, 0, "IDT 92HD98BXX" }, - { HDA_CODEC_IDT92HD99BXX, 0, "IDT 92HD99BXX" }, - { HDA_CODEC_CX20549, 0, "Conexant CX20549 (Venice)" }, - { HDA_CODEC_CX20551, 0, "Conexant CX20551 (Waikiki)" }, - { HDA_CODEC_CX20561, 0, "Conexant CX20561 (Hermosa)" }, - { HDA_CODEC_CX20582, 0, "Conexant CX20582 (Pebble)" }, - { HDA_CODEC_CX20583, 0, "Conexant CX20583 (Pebble HSF)" }, - { HDA_CODEC_CX20584, 0, "Conexant CX20584" }, - { HDA_CODEC_CX20585, 0, "Conexant CX20585" }, - { HDA_CODEC_CX20588, 0, "Conexant CX20588" }, - { HDA_CODEC_CX20590, 0, "Conexant CX20590" }, - { HDA_CODEC_CX20631, 0, "Conexant CX20631" }, - { HDA_CODEC_CX20632, 0, "Conexant CX20632" }, - { HDA_CODEC_CX20641, 0, "Conexant CX20641" }, - { HDA_CODEC_CX20642, 0, "Conexant CX20642" }, - { HDA_CODEC_CX20651, 0, "Conexant CX20651" }, - { HDA_CODEC_CX20652, 0, "Conexant CX20652" }, - { HDA_CODEC_CX20664, 0, "Conexant CX20664" }, - { HDA_CODEC_CX20665, 0, "Conexant CX20665" }, - { HDA_CODEC_VT1708_8, 0, "VIA VT1708_8" }, - { HDA_CODEC_VT1708_9, 0, "VIA VT1708_9" }, - { HDA_CODEC_VT1708_A, 0, "VIA VT1708_A" }, - { HDA_CODEC_VT1708_B, 0, "VIA VT1708_B" }, - { HDA_CODEC_VT1709_0, 0, "VIA VT1709_0" }, - { HDA_CODEC_VT1709_1, 0, "VIA VT1709_1" }, - { HDA_CODEC_VT1709_2, 0, "VIA VT1709_2" }, - { HDA_CODEC_VT1709_3, 0, "VIA VT1709_3" }, - { HDA_CODEC_VT1709_4, 0, "VIA VT1709_4" }, - { HDA_CODEC_VT1709_5, 0, "VIA VT1709_5" }, - { HDA_CODEC_VT1709_6, 0, "VIA VT1709_6" }, - { HDA_CODEC_VT1709_7, 0, "VIA VT1709_7" }, - { HDA_CODEC_VT1708B_0, 0, "VIA VT1708B_0" }, - { HDA_CODEC_VT1708B_1, 0, "VIA VT1708B_1" }, - { HDA_CODEC_VT1708B_2, 0, "VIA VT1708B_2" }, - { HDA_CODEC_VT1708B_3, 0, "VIA VT1708B_3" }, - { HDA_CODEC_VT1708B_4, 0, "VIA VT1708B_4" }, - { HDA_CODEC_VT1708B_5, 0, "VIA VT1708B_5" }, - { HDA_CODEC_VT1708B_6, 0, "VIA VT1708B_6" }, - { HDA_CODEC_VT1708B_7, 0, "VIA VT1708B_7" }, - { HDA_CODEC_VT1708S_0, 0, "VIA VT1708S_0" }, - { HDA_CODEC_VT1708S_1, 0, "VIA VT1708S_1" }, - { HDA_CODEC_VT1708S_2, 0, "VIA VT1708S_2" }, - { HDA_CODEC_VT1708S_3, 0, "VIA VT1708S_3" }, - { HDA_CODEC_VT1708S_4, 0, "VIA VT1708S_4" }, - { HDA_CODEC_VT1708S_5, 0, "VIA VT1708S_5" }, - { HDA_CODEC_VT1708S_6, 0, "VIA VT1708S_6" }, - { HDA_CODEC_VT1708S_7, 0, "VIA VT1708S_7" }, - { HDA_CODEC_VT1702_0, 0, "VIA VT1702_0" }, - { HDA_CODEC_VT1702_1, 0, "VIA VT1702_1" }, - { HDA_CODEC_VT1702_2, 0, "VIA VT1702_2" }, - { HDA_CODEC_VT1702_3, 0, "VIA VT1702_3" }, - { HDA_CODEC_VT1702_4, 0, "VIA VT1702_4" }, - { HDA_CODEC_VT1702_5, 0, "VIA VT1702_5" }, - { HDA_CODEC_VT1702_6, 0, "VIA VT1702_6" }, - { HDA_CODEC_VT1702_7, 0, "VIA VT1702_7" }, - { HDA_CODEC_VT1716S_0, 0, "VIA VT1716S_0" }, - { HDA_CODEC_VT1716S_1, 0, "VIA VT1716S_1" }, - { HDA_CODEC_VT1718S_0, 0, "VIA VT1718S_0" }, - { HDA_CODEC_VT1718S_1, 0, "VIA VT1718S_1" }, - { HDA_CODEC_VT1802_0, 0, "VIA VT1802_0" }, - { HDA_CODEC_VT1802_1, 0, "VIA VT1802_1" }, - { HDA_CODEC_VT1812, 0, "VIA VT1812" }, - { HDA_CODEC_VT1818S, 0, "VIA VT1818S" }, - { HDA_CODEC_VT1828S, 0, "VIA VT1828S" }, - { HDA_CODEC_VT2002P_0, 0, "VIA VT2002P_0" }, - { HDA_CODEC_VT2002P_1, 0, "VIA VT2002P_1" }, - { HDA_CODEC_VT2020, 0, "VIA VT2020" }, - { HDA_CODEC_ATIRS600_1, 0, "ATI RS600" }, - { HDA_CODEC_ATIRS600_2, 0, "ATI RS600" }, - { HDA_CODEC_ATIRS690, 0, "ATI RS690/780" }, - { HDA_CODEC_ATIR6XX, 0, "ATI R6xx" }, - { HDA_CODEC_NVIDIAMCP67, 0, "NVIDIA MCP67" }, - { HDA_CODEC_NVIDIAMCP73, 0, "NVIDIA MCP73" }, - { HDA_CODEC_NVIDIAMCP78, 0, "NVIDIA MCP78" }, - { HDA_CODEC_NVIDIAMCP78_2, 0, "NVIDIA MCP78" }, - { HDA_CODEC_NVIDIAMCP78_3, 0, "NVIDIA MCP78" }, - { HDA_CODEC_NVIDIAMCP78_4, 0, "NVIDIA MCP78" }, - { HDA_CODEC_NVIDIAMCP7A, 0, "NVIDIA MCP7A" }, - { HDA_CODEC_NVIDIAGT220, 0, "NVIDIA GT220" }, - { HDA_CODEC_NVIDIAGT21X, 0, "NVIDIA GT21x" }, - { HDA_CODEC_NVIDIAMCP89, 0, "NVIDIA MCP89" }, - { HDA_CODEC_NVIDIAGT240, 0, "NVIDIA GT240" }, - { HDA_CODEC_NVIDIAGTS450, 0, "NVIDIA GTS450" }, - { HDA_CODEC_NVIDIAGT440, 0, "NVIDIA GT440" }, - { HDA_CODEC_NVIDIAGTX550, 0, "NVIDIA GTX550" }, - { HDA_CODEC_NVIDIAGTX570, 0, "NVIDIA GTX570" }, - { HDA_CODEC_INTELIP, 0, "Intel Ibex Peak" }, - { HDA_CODEC_INTELBL, 0, "Intel Bearlake" }, - { HDA_CODEC_INTELCA, 0, "Intel Cantiga" }, - { HDA_CODEC_INTELEL, 0, "Intel Eaglelake" }, - { HDA_CODEC_INTELIP2, 0, "Intel Ibex Peak" }, - { HDA_CODEC_INTELCPT, 0, "Intel Cougar Point" }, - { HDA_CODEC_INTELPPT, 0, "Intel Panther Point" }, - { HDA_CODEC_INTELHSW, 0, "Intel Haswell" }, - { HDA_CODEC_INTELCL, 0, "Intel Crestline" }, - { HDA_CODEC_SII1390, 0, "Silicon Image SiI1390" }, - { HDA_CODEC_SII1392, 0, "Silicon Image SiI1392" }, + + { HDA_CODEC_CXD9872RDK, 0, "CXD9872RD/K" }, + { HDA_CODEC_CXD9872AKD, 0, "CXD9872AKD" }, + { HDA_CODEC_STAC9200D, 0, "STAC9200D" }, + { HDA_CODEC_STAC9204X, 0, "STAC9204X" }, + { HDA_CODEC_STAC9204D, 0, "STAC9204D" }, + { HDA_CODEC_STAC9205X, 0, "STAC9205X" }, + { HDA_CODEC_STAC9205D, 0, "STAC9205D" }, + { HDA_CODEC_STAC9220, 0, "STAC9220" }, + { HDA_CODEC_STAC9220_A1, 0, "STAC9220_A1" }, + { HDA_CODEC_STAC9220_A2, 0, "STAC9220_A2" }, + { HDA_CODEC_STAC9221, 0, "STAC9221" }, + { HDA_CODEC_STAC9221_A2, 0, "STAC9221_A2" }, + { HDA_CODEC_STAC9221D, 0, "STAC9221D" }, + { HDA_CODEC_STAC922XD, 0, "STAC9220D/9223D" }, + { HDA_CODEC_STAC9227X, 0, "STAC9227X" }, + { HDA_CODEC_STAC9227D, 0, "STAC9227D" }, + { HDA_CODEC_STAC9228X, 0, "STAC9228X" }, + { HDA_CODEC_STAC9228D, 0, "STAC9228D" }, + { HDA_CODEC_STAC9229X, 0, "STAC9229X" }, + { HDA_CODEC_STAC9229D, 0, "STAC9229D" }, + { HDA_CODEC_STAC9230X, 0, "STAC9230X" }, + { HDA_CODEC_STAC9230D, 0, "STAC9230D" }, + { HDA_CODEC_STAC9250, 0, "STAC9250" }, + { HDA_CODEC_STAC9250D, 0, "STAC9250D" }, + { HDA_CODEC_STAC9251, 0, "STAC9251" }, + { HDA_CODEC_STAC9250D_1, 0, "STAC9250D" }, + { HDA_CODEC_STAC9255, 0, "STAC9255" }, + { HDA_CODEC_STAC9255D, 0, "STAC9255D" }, + { HDA_CODEC_STAC9254, 0, "STAC9254" }, + { HDA_CODEC_STAC9254D, 0, "STAC9254D" }, + { HDA_CODEC_STAC9271X, 0, "STAC9271X" }, + { HDA_CODEC_STAC9271D, 0, "STAC9271D" }, + { HDA_CODEC_STAC9272X, 0, "STAC9272X" }, + { HDA_CODEC_STAC9272D, 0, "STAC9272D" }, + { HDA_CODEC_STAC9273X, 0, "STAC9273X" }, + { HDA_CODEC_STAC9273D, 0, "STAC9273D" }, + { HDA_CODEC_STAC9274, 0, "STAC9274" }, + { HDA_CODEC_STAC9274D, 0, "STAC9274D" }, + { HDA_CODEC_STAC9274X5NH, 0, "STAC9274X5NH" }, + { HDA_CODEC_STAC9274D5NH, 0, "STAC9274D5NH" }, + { HDA_CODEC_STAC9202, 0, "STAC9202" }, + { HDA_CODEC_STAC9202D, 0, "STAC9202D" }, + { HDA_CODEC_STAC9872AK, 0, "STAC9872AK" }, + + { HDA_CODEC_IDT92HD005, 0, "92HD005" }, + { HDA_CODEC_IDT92HD005D, 0, "92HD005D" }, + { HDA_CODEC_IDT92HD206X, 0, "92HD206X" }, + { HDA_CODEC_IDT92HD206D, 0, "92HD206D" }, + { HDA_CODEC_IDT92HD66B1X5, 0, "92HD66B1X5" }, + { HDA_CODEC_IDT92HD66B2X5, 0, "92HD66B2X5" }, + { HDA_CODEC_IDT92HD66B3X5, 0, "92HD66B3X5" }, + { HDA_CODEC_IDT92HD66C1X5, 0, "92HD66C1X5" }, + { HDA_CODEC_IDT92HD66C2X5, 0, "92HD66C2X5" }, + { HDA_CODEC_IDT92HD66C3X5, 0, "92HD66C3X5" }, + { HDA_CODEC_IDT92HD66B1X3, 0, "92HD66B1X3" }, + { HDA_CODEC_IDT92HD66B2X3, 0, "92HD66B2X3" }, + { HDA_CODEC_IDT92HD66B3X3, 0, "92HD66B3X3" }, + { HDA_CODEC_IDT92HD66C1X3, 0, "92HD66C1X3" }, + { HDA_CODEC_IDT92HD66C2X3, 0, "92HD66C2X3" }, + { HDA_CODEC_IDT92HD66C3_65, 0, "92HD66C3_65" }, + { HDA_CODEC_IDT92HD700X, 0, "92HD700X" }, + { HDA_CODEC_IDT92HD700D, 0, "92HD700D" }, + { HDA_CODEC_IDT92HD71B5, 0, "92HD71B5" }, + { HDA_CODEC_IDT92HD71B5_2, 0, "92HD71B5" }, + { HDA_CODEC_IDT92HD71B6, 0, "92HD71B6" }, + { HDA_CODEC_IDT92HD71B6_2, 0, "92HD71B6" }, + { HDA_CODEC_IDT92HD71B7, 0, "92HD71B7" }, + { HDA_CODEC_IDT92HD71B7_2, 0, "92HD71B7" }, + { HDA_CODEC_IDT92HD71B8, 0, "92HD71B8" }, + { HDA_CODEC_IDT92HD71B8_2, 0, "92HD71B8" }, + { HDA_CODEC_IDT92HD73C1, 0, "92HD73C1" }, + { HDA_CODEC_IDT92HD73D1, 0, "92HD73D1" }, + { HDA_CODEC_IDT92HD73E1, 0, "92HD73E1" }, + { HDA_CODEC_IDT92HD95, 0, "92HD95" }, + { HDA_CODEC_IDT92HD75B3, 0, "92HD75B3" }, + { HDA_CODEC_IDT92HD88B3, 0, "92HD88B3" }, + { HDA_CODEC_IDT92HD88B1, 0, "92HD88B1" }, + { HDA_CODEC_IDT92HD88B2, 0, "92HD88B2" }, + { HDA_CODEC_IDT92HD88B4, 0, "92HD88B4" }, + { HDA_CODEC_IDT92HD75BX, 0, "92HD75BX" }, + { HDA_CODEC_IDT92HD81B1C, 0, "92HD81B1C" }, + { HDA_CODEC_IDT92HD81B1X, 0, "92HD81B1X" }, + { HDA_CODEC_IDT92HD83C1C, 0, "92HD83C1C" }, + { HDA_CODEC_IDT92HD83C1X, 0, "92HD83C1X" }, + { HDA_CODEC_IDT92HD87B1_3, 0, "92HD87B1/3" }, + { HDA_CODEC_IDT92HD87B2_4, 0, "92HD87B2/4" }, + { HDA_CODEC_IDT92HD89C3, 0, "92HD89C3" }, + { HDA_CODEC_IDT92HD89C2, 0, "92HD89C2" }, + { HDA_CODEC_IDT92HD89C1, 0, "92HD89C1" }, + { HDA_CODEC_IDT92HD89B3, 0, "92HD89B3" }, + { HDA_CODEC_IDT92HD89B2, 0, "92HD89B2" }, + { HDA_CODEC_IDT92HD89B1, 0, "92HD89B1" }, + { HDA_CODEC_IDT92HD89E3, 0, "92HD89E3" }, + { HDA_CODEC_IDT92HD89E2, 0, "92HD89E2" }, + { HDA_CODEC_IDT92HD89E1, 0, "92HD89E1" }, + { HDA_CODEC_IDT92HD89D3, 0, "92HD89D3" }, + { HDA_CODEC_IDT92HD89D2, 0, "92HD89D2" }, + { HDA_CODEC_IDT92HD89D1, 0, "92HD89D1" }, + { HDA_CODEC_IDT92HD89F3, 0, "92HD89F3" }, + { HDA_CODEC_IDT92HD89F2, 0, "92HD89F2" }, + { HDA_CODEC_IDT92HD89F1, 0, "92HD89F1" }, + { HDA_CODEC_IDT92HD90BXX, 0, "92HD90BXX" }, + { HDA_CODEC_IDT92HD91BXX, 0, "92HD91BXX" }, + { HDA_CODEC_IDT92HD93BXX, 0, "92HD93BXX" }, + { HDA_CODEC_IDT92HD98BXX, 0, "92HD98BXX" }, + { HDA_CODEC_IDT92HD99BXX, 0, "92HD99BXX" }, + + { HDA_CODEC_CX20549, 0, "CX20549 (Venice)" }, + { HDA_CODEC_CX20551, 0, "CX20551 (Waikiki)" }, + { HDA_CODEC_CX20561, 0, "CX20561 (Hermosa)" }, + { HDA_CODEC_CX20582, 0, "CX20582 (Pebble)" }, + { HDA_CODEC_CX20583, 0, "CX20583 (Pebble HSF)" }, + { HDA_CODEC_CX20584, 0, "CX20584" }, + { HDA_CODEC_CX20585, 0, "CX20585" }, + { HDA_CODEC_CX20588, 0, "CX20588" }, + { HDA_CODEC_CX20590, 0, "CX20590" }, + { HDA_CODEC_CX20631, 0, "CX20631" }, + { HDA_CODEC_CX20632, 0, "CX20632" }, + { HDA_CODEC_CX20641, 0, "CX20641" }, + { HDA_CODEC_CX20642, 0, "CX20642" }, + { HDA_CODEC_CX20651, 0, "CX20651" }, + { HDA_CODEC_CX20652, 0, "CX20652" }, + { HDA_CODEC_CX20664, 0, "CX20664" }, + { HDA_CODEC_CX20665, 0, "CX20665" }, + { HDA_CODEC_CX20751, 0, "CX20751/2" }, + { HDA_CODEC_CX20751_2, 0, "CX20751/2" }, + { HDA_CODEC_CX20751_4, 0, "CX20753/4" }, + { HDA_CODEC_CX20755, 0, "CX20755" }, + { HDA_CODEC_CX20756, 0, "CX20756" }, + { HDA_CODEC_CX20757, 0, "CX20757" }, + { HDA_CODEC_CX20952, 0, "CX20952" }, + + { HDA_CODEC_VT1708_8, 0, "VT1708_8" }, + { HDA_CODEC_VT1708_9, 0, "VT1708_9" }, + { HDA_CODEC_VT1708_A, 0, "VT1708_A" }, + { HDA_CODEC_VT1708_B, 0, "VT1708_B" }, + { HDA_CODEC_VT1709_0, 0, "VT1709_0" }, + { HDA_CODEC_VT1709_1, 0, "VT1709_1" }, + { HDA_CODEC_VT1709_2, 0, "VT1709_2" }, + { HDA_CODEC_VT1709_3, 0, "VT1709_3" }, + { HDA_CODEC_VT1709_4, 0, "VT1709_4" }, + { HDA_CODEC_VT1709_5, 0, "VT1709_5" }, + { HDA_CODEC_VT1709_6, 0, "VT1709_6" }, + { HDA_CODEC_VT1709_7, 0, "VT1709_7" }, + { HDA_CODEC_VT1708B_0, 0, "VT1708B_0" }, + { HDA_CODEC_VT1708B_1, 0, "VT1708B_1" }, + { HDA_CODEC_VT1708B_2, 0, "VT1708B_2" }, + { HDA_CODEC_VT1708B_3, 0, "VT1708B_3" }, + { HDA_CODEC_VT1708B_4, 0, "VT1708B_4" }, + { HDA_CODEC_VT1708B_5, 0, "VT1708B_5" }, + { HDA_CODEC_VT1708B_6, 0, "VT1708B_6" }, + { HDA_CODEC_VT1708B_7, 0, "VT1708B_7" }, + { HDA_CODEC_VT1708S_0, 0, "VT1708S_0" }, + { HDA_CODEC_VT1708S_1, 0, "VT1708S_1" }, + { HDA_CODEC_VT1708S_2, 0, "VT1708S_2" }, + { HDA_CODEC_VT1708S_3, 0, "VT1708S_3" }, + { HDA_CODEC_VT1708S_4, 0, "VT1708S_4" }, + { HDA_CODEC_VT1708S_5, 0, "VT1708S_5" }, + { HDA_CODEC_VT1708S_6, 0, "VT1708S_6" }, + { HDA_CODEC_VT1708S_7, 0, "VT1708S_7" }, + { HDA_CODEC_VT1702_0, 0, "VT1702_0" }, + { HDA_CODEC_VT1702_1, 0, "VT1702_1" }, + { HDA_CODEC_VT1702_2, 0, "VT1702_2" }, + { HDA_CODEC_VT1702_3, 0, "VT1702_3" }, + { HDA_CODEC_VT1702_4, 0, "VT1702_4" }, + { HDA_CODEC_VT1702_5, 0, "VT1702_5" }, + { HDA_CODEC_VT1702_6, 0, "VT1702_6" }, + { HDA_CODEC_VT1702_7, 0, "VT1702_7" }, + { HDA_CODEC_VT1716S_0, 0, "VT1716S_0" }, + { HDA_CODEC_VT1716S_1, 0, "VT1716S_1" }, + { HDA_CODEC_VT1718S_0, 0, "VT1718S_0" }, + { HDA_CODEC_VT1718S_1, 0, "VT1718S_1" }, + { HDA_CODEC_VT1802_0, 0, "VT1802_0" }, + { HDA_CODEC_VT1802_1, 0, "VT1802_1" }, + { HDA_CODEC_VT1812, 0, "VT1812" }, + { HDA_CODEC_VT1818S, 0, "VT1818S" }, + { HDA_CODEC_VT1828S, 0, "VT1828S" }, + { HDA_CODEC_VT2002P_0, 0, "VT2002P_0" }, + { HDA_CODEC_VT2002P_1, 0, "VT2002P_1" }, + { HDA_CODEC_VT2020, 0, "VT2020" }, + + { HDA_CODEC_ATIRS600_1, 0, "RS600" }, + { HDA_CODEC_ATIRS600_2, 0, "RS600" }, + { HDA_CODEC_ATIRS690, 0, "RS690/780" }, + { HDA_CODEC_ATIR6XX, 0, "R6xx" }, + + { HDA_CODEC_NVIDIAMCP67, 0, "MCP67" }, + { HDA_CODEC_NVIDIAMCP73, 0, "MCP73" }, + { HDA_CODEC_NVIDIAMCP78, 0, "MCP78" }, + { HDA_CODEC_NVIDIAMCP78_2, 0, "MCP78" }, + { HDA_CODEC_NVIDIAMCP78_3, 0, "MCP78" }, + { HDA_CODEC_NVIDIAMCP78_4, 0, "MCP78" }, + { HDA_CODEC_NVIDIAMCP7A, 0, "MCP7A" }, + { HDA_CODEC_NVIDIAGT220, 0, "GT220" }, + { HDA_CODEC_NVIDIAGT21X, 0, "GT21x" }, + { HDA_CODEC_NVIDIAMCP89, 0, "MCP89" }, + { HDA_CODEC_NVIDIAGT240, 0, "GT240" }, + { HDA_CODEC_NVIDIAGTS450, 0, "GTS450" }, + { HDA_CODEC_NVIDIAGT440, 0, "GT440" }, // Revision Id: 0x100100 + { HDA_CODEC_NVIDIAGTX470, 0, "GT470" }, + { HDA_CODEC_NVIDIAGTX550, 0, "GTX550" }, + { HDA_CODEC_NVIDIAGTX570, 0, "GTX570" }, + { HDA_CODEC_NVIDIAGT610, 0, "GT610" }, + + + { HDA_CODEC_INTELIP, 0, "Ibex Peak" }, + { HDA_CODEC_INTELBL, 0, "Bearlake" }, + { HDA_CODEC_INTELCA, 0, "Cantiga" }, + { HDA_CODEC_INTELEL, 0, "Eaglelake" }, + { HDA_CODEC_INTELIP2, 0, "Ibex Peak" }, + { HDA_CODEC_INTELCPT, 0, "Cougar Point" }, + { HDA_CODEC_INTELPPT, 0, "Panther Point" }, + { HDA_CODEC_INTELLLP, 0, "Haswell" }, + { HDA_CODEC_INTELBRW, 0, "Broadwell" }, + { HDA_CODEC_INTELSKL, 0, "Skylake" }, + { HDA_CODEC_INTELCDT, 0, "CedarTrail" }, + { HDA_CODEC_INTELVLV, 0, "Valleyview2" }, + { HDA_CODEC_INTELBSW, 0, "Braswell" }, + { HDA_CODEC_INTELCL, 0, "Crestline" }, + + { HDA_CODEC_SII1390, 0, "SiI1390 HDMi" }, + { HDA_CODEC_SII1392, 0, "SiI1392 HDMi" }, + // Unknown CODECs { HDA_CODEC_ADXXXX, 0, "Analog Devices" }, { HDA_CODEC_AGEREXXXX, 0, "Lucent/Agere Systems" }, @@ -479,7 +602,6 @@ }; #define HDACC_CODECS_LEN (sizeof(know_codecs) / sizeof(know_codecs[0])) -*/ /***************** * Device Methods @@ -490,7 +612,7 @@ { static char desc[128]; - const char* name_format = "Unknown HD Audio device %s"; + const char *name_format = "Unknown HD Audio device %s"; uint32_t controller_model = ((controller_device_id << 16) | controller_vendor_id); int i; @@ -532,21 +654,101 @@ } /* Not in table */ - snprintf(desc, sizeof(desc), - "Unknown HD Audio device, vendor %04x, model %04x", + snprintf(desc, sizeof(desc), "Unknown HD Audio device, vendor %04x, model %04x", controller_vendor_id, controller_device_id); return desc; } -static int devprop_add_hda_template(struct DevPropDevice *device) +/* get Codec name */ +static char *get_hda_codec_name( uint16_t codec_vendor_id, uint16_t codec_device_id, uint8_t codec_revision_id, uint8_t codec_stepping_id ) { - if (!device) + static char desc[128]; + + char *lName_format = NULL; + uint32_t lCodec_model = ((uint32_t)(codec_vendor_id) << 16) + (codec_device_id); + uint32_t lCodec_rev = (((uint16_t)(codec_revision_id) << 8) + codec_stepping_id); + int i; + + // Get format for vendor ID + switch ( codec_vendor_id ) // uint16_t { - return 0; + case ANALOGDEVICES_VENDORID: + lName_format = "Analog Devices %s"; break; + + case AGERE_VENDORID: + lName_format = "Agere Systems %s "; break; + + case REALTEK_VENDORID: + lName_format = "Realtek %s"; break; + + case ATI_VENDORID: + lName_format = "ATI %s"; break; + + case CREATIVE_VENDORID: + lName_format = "Creative %s"; break; + + case CMEDIA_VENDORID: + case CMEDIA2_VENDORID: + lName_format = "CMedia %s"; break; + + case CIRRUSLOGIC_VENDORID: + lName_format = "Cirrus Logic %s"; break; + + case CONEXANT_VENDORID: + lName_format = "Conexant %s"; break; + + case CHRONTEL_VENDORID: + lName_format = "Chrontel %s"; break; + + case IDT_VENDORID: + lName_format = "IDT %s"; break; + + case INTEL_VENDORID: + lName_format = "Intel %s"; break; + + case MOTO_VENDORID: + lName_format = "Motorola %s"; break; + + case NVIDIA_VENDORID: + lName_format = "nVidia %s"; break; + + case SII_VENDORID: + lName_format = "Silicon Image %s"; break; + + case SIGMATEL_VENDORID: + lName_format = "Sigmatel %s"; break; + + case VIA_VENDORID: + lName_format = "VIA %s"; break; + + default: + lName_format = UNKNOWN; break; + break; } - devices_number++; - return 1; + for (i = 0; i < HDACC_CODECS_LEN; i++) + { + if ( know_codecs[i].id == lCodec_model ) + { + if ( ( know_codecs[i].rev == 0x00000000 ) || ( know_codecs[i].rev == lCodec_rev ) ) + { +// verbose("\tRevision in table (%06x) | burned chip revision (%06x).\n", know_codecs[i].rev, lCodec_rev ); + snprintf(desc, sizeof(desc), lName_format, know_codecs[i].name); + return desc; + } + } + } + + if ( ( lName_format != UNKNOWN ) && ( strstr(lName_format, "%s" ) != NULL ) ) + { + // Dirty way to remove '%s' from the end of the lName_format + int len = strlen(lName_format); + lName_format[len-2] = '\0'; + } + + // Not in table + snprintf(desc, sizeof(desc), "unknown %s Codec", lName_format); + return desc; } bool setup_hda_devprop(pci_dt_t *hda_dev) @@ -560,10 +762,14 @@ uint16_t controller_device_id = hda_dev->device_id; const char *value; - verbose("\n------------------------\n"); - verbose("\tAUDIO DEVICE INFO\n"); - verbose("-------------------------\n"); + // Skip keys + bool do_skip_n_devprop = false; + bool do_skip_a_devprop = false; + getBoolForKey(kSkipNvidiaGfx, &do_skip_n_devprop, &bootInfo->chameleonConfig); + getBoolForKey(kSkipAtiGfx, &do_skip_a_devprop, &bootInfo->chameleonConfig); + verbose("\tClass code: [%04X]\n", hda_dev->class_id); + devicepath = get_pci_dev_path(hda_dev); controller_name = get_hda_controller_name(controller_device_id, controller_vendor_id); @@ -586,8 +792,13 @@ { return 0; } - devprop_add_hda_template(device); + verbose("\tModel name: %s [%04x:%04x] (rev %02x)\n\tSubsystem: [%04x:%04x]\n\t%s\n", + controller_name, hda_dev->vendor_id, hda_dev->device_id, hda_dev->revision_id, + hda_dev->subsys_id.subsys.vendor_id, hda_dev->subsys_id.subsys.device_id, devicepath); + + probe_hda_bus(hda_dev->dev.addr); + switch ((controller_device_id << 16) | controller_vendor_id) { @@ -599,158 +810,513 @@ case HDA_INTEL_HSW1: case HDA_INTEL_HSW2: case HDA_INTEL_HSW3: + case HDA_INTEL_BDW: case HDA_INTEL_CPT: case HDA_INTEL_PATSBURG: case HDA_INTEL_PPT1: - case HDA_INTEL_LPT1: - case HDA_INTEL_LPT2: - case HDA_INTEL_WCPT: - case HDA_INTEL_WELLS1: - case HDA_INTEL_WELLS2: - case HDA_INTEL_LPTLP1: - case HDA_INTEL_LPTLP2: + case HDA_INTEL_BRASWELL: case HDA_INTEL_82801F: case HDA_INTEL_63XXESB: case HDA_INTEL_82801G: case HDA_INTEL_82801H: case HDA_INTEL_82801I: + case HDA_INTEL_ICH9: case HDA_INTEL_82801JI: case HDA_INTEL_82801JD: case HDA_INTEL_PCH: case HDA_INTEL_PCH2: case HDA_INTEL_SCH: + case HDA_INTEL_LPT1: + case HDA_INTEL_LPT2: + case HDA_INTEL_WCPT: + case HDA_INTEL_WELLS1: + case HDA_INTEL_WELLS2: + case HDA_INTEL_WCPTLP: + case HDA_INTEL_LPTLP1: + case HDA_INTEL_LPTLP2: + case HDA_INTEL_SRSPLP: + case HDA_INTEL_SRSP: - /* if the key value kHDEFLayoutID as a value set that value, if not will assign a default layout */ - if (getValueForKey(kHDEFLayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDEF_LEN * 2) + /* if the key value kHDEFLayoutID as a value set that value, if not will assign a default layout */ + if (getValueForKey(kHDEFLayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDEF_LEN * 2) + { + uint8_t new_HDEF_layout_id[HDEF_LEN]; + if (hex2bin(value, new_HDEF_layout_id, HDEF_LEN) == 0) + { + memcpy(default_HDEF_layout_id, new_HDEF_layout_id, HDEF_LEN); + verbose("\tUsing user supplied HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", + default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]); + } + } + else + { + verbose("\tUsing default HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", + default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]); + } + devprop_add_value(device, "layout-id", default_HDEF_layout_id, HDEF_LEN); + devprop_add_value(device, "AAPL,slot-name", (uint8_t *)"Built-in", sizeof("Built-in")); // 0x09 + devprop_add_value(device, "name", (uint8_t *)"audio", 6); // 0x06 + devprop_add_value(device, "device-type", (uint8_t *)"High Definition Audio Controller", sizeof("High Definition Audio Controller")); + devprop_add_value(device, "device_type", (uint8_t *)"Sound", sizeof("Sound")); + devprop_add_value(device, "built-in", &BuiltIn, 1); + devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", sizeof("onboard-1")); // 0x0a + // "AFGLowPowerState" = <03000000> + break; + + /***************************************************************************************************************** + * The above case are intended as for HDAU (NVIDIA) device onboard audio for GFX card with Audio controller HDMi * + *****************************************************************************************************************/ + case HDA_NVIDIA_GK107: + case HDA_NVIDIA_GF110_1: + case HDA_NVIDIA_GF110_2: + case HDA_NVIDIA_GK106: + case HDA_NVIDIA_GK104: + case HDA_NVIDIA_GF119: + case HDA_NVIDIA_GT116: + case HDA_NVIDIA_GT104: + case HDA_NVIDIA_GT108: + case HDA_NVIDIA_GT106: + case HDA_NVIDIA_GT100: + case HDA_NVIDIA_0BE4: + case HDA_NVIDIA_0BE3: + case HDA_NVIDIA_0BE2: + if ( do_skip_n_devprop ) + { + verbose("Skip Nvidia audio device!\n"); + } + else + { + /* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */ + if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2) + { + uint8_t new_HDAU_layout_id[HDAU_LEN]; + if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0) + { + memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN); + verbose("\tUsing user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", + default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); + } + } + else + { + verbose("\tUsing default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", + default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); + } + + devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/ + devprop_add_value(device, "@0,connector-type", connector_type_value, 4); + devprop_add_value(device, "@1,connector-type", connector_type_value, 4); + devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", sizeof("onboard-2")); + devprop_add_value(device, "built-in", &BuiltIn, 1); + } + break; + + /************************************************************************************************************** + * The above case are intended as for HDAU (ATi) device onboard audio for GFX card with Audio controller HDMi * + **************************************************************************************************************/ + case HDA_ATI_SB450: + case HDA_ATI_SB600: + case HDA_ATI_HUDSON: + case HDA_ATI_RS600: + case HDA_ATI_RS690: + case HDA_ATI_RS780: + case HDA_ATI_R600: + case HDA_ATI_RV630: + case HDA_ATI_RV610: + case HDA_ATI_RV670: + case HDA_ATI_RV635: + case HDA_ATI_RV620: + case HDA_ATI_RV770: + case HDA_ATI_RV730: + case HDA_ATI_RV710: + case HDA_ATI_RV740: + case HDA_ATI_RV870: + case HDA_ATI_RV840: + case HDA_ATI_RV830: + case HDA_ATI_RV810: + case HDA_ATI_RV970: + case HDA_ATI_RV940: + case HDA_ATI_RV930: + case HDA_ATI_RV910: + case HDA_ATI_R1000: + case HDA_ATI_SI: + case HDA_ATI_VERDE: + if ( do_skip_a_devprop ) + { + verbose("Skip ATi/AMD audio device!\n"); + } + else + { + /* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */ + if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2) + { + uint8_t new_HDAU_layout_id[HDAU_LEN]; + if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0) + { + memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN); + verbose("\tUsing user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", + default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); + } + } + else + { + verbose("\tUsing default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", + default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); + } + + devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/ + devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", 10); + devprop_add_value(device, "built-in", &BuiltIn, 1); + } + break; + + default: + break; + } + + stringdata = malloc(sizeof(uint8_t) * string->length); + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + + return true; +} + +/* + * Structure of HDA MMIO Region + */ +struct HDARegs +{ + uint16_t gcap; + uint8_t vmin; + uint8_t vmaj; + uint16_t outpay; + uint16_t inpay; + uint32_t gctl; + uint16_t wakeen; + uint16_t statests; + uint16_t gsts; + uint8_t rsvd0[6]; + uint16_t outstrmpay; + uint16_t instrmpay; + uint8_t rsvd1[4]; + uint32_t intctl; + uint32_t intsts; + uint8_t rsvd2[8]; + uint32_t walclk; + uint8_t rsvd3[4]; + uint32_t ssync; + uint8_t rsvd4[4]; + uint32_t corblbase; + uint32_t corbubase; + uint16_t corbwp; + uint16_t corbrp; + uint8_t corbctl; + uint8_t corbsts; + uint8_t corbsize; + uint8_t rsvd5; + uint32_t rirblbase; + uint32_t rirbubase; + uint16_t rirbwp; + uint16_t rintcnt; + uint8_t rirbctl; + uint8_t rirbsts; + uint8_t rirbsize; + uint8_t rsvd6; + uint32_t icoi; + uint32_t icii; + uint16_t icis; + uint8_t rsvd7[6]; + uint32_t dpiblbase; + uint32_t dpibubase; + uint8_t rsvd8[8]; +/* + * Stream Descriptors follow + */ +} __attribute__((aligned(16), packed)); + +/* + * Data to be discovered for HDA codecs + */ + +struct HDACodecInfo +{ + uint16_t vendor_id; + uint16_t device_id; + uint8_t revision_id; + uint8_t stepping_id; + uint8_t maj_rev; + uint8_t min_rev; + uint8_t num_function_groups; + const char *name; +}; + +/* + * Timing Functions + */ + +static int wait_for_register_state_16(uint16_t const volatile* reg, + uint16_t target_mask, + uint16_t target_value, + uint32_t timeout_us, + uint32_t tsc_ticks_per_us) +{ + uint64_t deadline = rdtsc64() + MultU32x32(timeout_us, tsc_ticks_per_us); + do { - uint8_t new_HDEF_layout_id[HDEF_LEN]; - if (hex2bin(value, new_HDEF_layout_id, HDEF_LEN) == 0) - { - memcpy(default_HDEF_layout_id, new_HDEF_layout_id, HDEF_LEN); - verbose("Using user supplied HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", - default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]); - } + uint16_t value = *reg; + if ((value & target_mask) == target_value) + return 0; + CpuPause(); } - else + while (rdtsc64() < deadline); + return -1; +} + +static void delay_us(uint32_t timeout_us, uint32_t tsc_ticks_per_us) +{ + uint64_t deadline = rdtsc64() + MultU32x32(timeout_us, tsc_ticks_per_us); + + do { - verbose("Using default HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", - default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]); + CpuPause(); } - devprop_add_value(device, "layout-id", default_HDEF_layout_id, HDEF_LEN); - devprop_add_value(device, "AAPL,slot-name", (uint8_t *)"Built-in", 9); // 0x09 - devprop_add_value(device, "name", (uint8_t *)"audio", 6); // 0x06 - devprop_add_value(device, "device_type", (uint8_t *)"High Definition Audio", 22); // 0x16 - devprop_add_value(device, "built-in", &BuiltIn, 1); - devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10); // 0x0a - // "AFGLowPowerState" = <03000000> - break; + while (rdtsc64() < deadline); +} - /**************************************************************************************************************** - * The above case are intended as for HDAU (NVIDIA) device onboard audio for GFX card with Audio controller HDMi - ****************************************************************************************************************/ - case HDA_NVIDIA_GK107: - case HDA_NVIDIA_GF110_1: - case HDA_NVIDIA_GF110_2: - case HDA_NVIDIA_GK106: - case HDA_NVIDIA_GK104: - case HDA_NVIDIA_GF119: - case HDA_NVIDIA_GT116: - case HDA_NVIDIA_GT104: - case HDA_NVIDIA_GT108: - case HDA_NVIDIA_GT106: - case HDA_NVIDIA_GT100: - case HDA_NVIDIA_0BE4: - case HDA_NVIDIA_0BE3: - case HDA_NVIDIA_0BE2: +static struct HDARegs volatile* hdaMemory = NULL; +static uint32_t tsc_ticks_per_us = 0U; - /* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */ - if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2) +#define ICIS_ICB 1U +#define ICIS_IRV 2U + +static int immediate_command(uint32_t command, uint32_t* response) +{ + /* + * Wait up to 1ms for for ICB 0 + */ + (void) wait_for_register_state_16(&hdaMemory->icis, ICIS_ICB, 0U, 1000U, tsc_ticks_per_us); + /* + * Ignore timeout and force ICB to 0 + * Clear IRV while at it + */ + hdaMemory->icis = ICIS_IRV; + /* + * Program command + */ + hdaMemory->icoi = command; + /* + * Trigger command + * Clear IRV again just in case + */ + hdaMemory->icis = ICIS_ICB | ICIS_IRV; + /* + * Wait up to 1ms for response + */ + if (wait_for_register_state_16(&hdaMemory->icis, ICIS_IRV, ICIS_IRV, 1000U, tsc_ticks_per_us) < 0) { - uint8_t new_HDAU_layout_id[HDAU_LEN]; - if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0) + /* + * response timed out + */ + return -1; + } + *response = hdaMemory->icii; + return 0; +} + +#define PACK_CID(x) ((x & 15U) << 28) +#define PACK_NID(x) ((x & 127U) << 20) +#define PACK_VERB_12BIT(x) ((x & 4095U) << 8) +#define PACK_PAYLOAD_8BIT(x) (x & UINT8_MAX) +#define VERB_GET_PARAMETER 0xF00U + +static uint32_t get_parameter(uint8_t codec_id, uint8_t node_id, uint8_t parameter_id) +{ + uint32_t command, response; + + command = PACK_CID(codec_id) | PACK_NID(node_id) | PACK_VERB_12BIT(VERB_GET_PARAMETER) | PACK_PAYLOAD_8BIT(parameter_id); + response = UINT32_MAX; + + /* + * Ignore timeout, return UINT32_MAX as error value + */ + (void) immediate_command(command, &response); + return response; +} + +#define PARAMETER_VID_DID 0U +#define PARAMETER_RID 2U +#define PARAMETER_NUM_NODES 4U + +static void probe_hda_codec(uint8_t codec_id, struct HDACodecInfo *codec_info) +{ + uint32_t response; + CDBG("\tprobing codec %d\n", codec_id); + response = get_parameter(codec_id, 0U, PARAMETER_VID_DID); + codec_info->vendor_id = (response >> 16) & UINT16_MAX; + codec_info->device_id = response & UINT16_MAX; + response = get_parameter(codec_id, 0U, PARAMETER_RID); + codec_info->revision_id = (response >> 8) & UINT8_MAX; + codec_info->stepping_id = response & UINT8_MAX; + codec_info->maj_rev = (response >> 20) & 15U; + codec_info->min_rev = (response >> 16) & 15U; + response = get_parameter(codec_id, 0U, PARAMETER_NUM_NODES); + codec_info->num_function_groups = response & UINT8_MAX; + codec_info->name = get_hda_codec_name(codec_info->vendor_id, codec_info->device_id, codec_info->revision_id, codec_info->stepping_id); + +} + +static int getHDABar(uint32_t pci_addr, uint32_t* bar_phys_addr) +{ + uint32_t barlow = pci_config_read32(pci_addr, PCI_BASE_ADDRESS_0); + + if ((barlow & PCI_BASE_ADDRESS_SPACE) != PCI_BASE_ADDRESS_SPACE_MEMORY) + { + CDBG("\tBAR0 for HDA Controller 0x%x is not an MMIO space\n", pci_addr); + return -1; + } + + if ((barlow & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) + { + uint32_t barhigh = pci_config_read32(pci_addr, PCI_BASE_ADDRESS_1); + + if (barhigh) { - memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN); - verbose("Using user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", - default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); + //verbose("\tBAR0 for HDA Controller 0x%x is located ouside 32-bit physical address space (0x%x%08x)\n", + //pci_addr, barhigh, barlow & PCI_BASE_ADDRESS_MEM_MASK); + return -1; } } - else + + if (bar_phys_addr) { - verbose("Using default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", - default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); + *bar_phys_addr = (barlow & PCI_BASE_ADDRESS_MEM_MASK); } + return 0; +} - devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/ - devprop_add_value(device, "@0,connector-type", connector_type_value, 4); - devprop_add_value(device, "@1,connector-type", connector_type_value, 4); - devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", 10); - devprop_add_value(device, "built-in", &BuiltIn, 1); - break; +void probe_hda_bus(uint32_t pci_addr) +{ + uint64_t tsc_frequency; + uint32_t bar_phys_addr; + uint16_t pci_cmd, statests; + uint16_t const pci_cmd_wanted = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + uint8_t codec_id, original_reset_state; + struct HDACodecInfo codec_info; - /************************************************************************************************************* - * The above case are intended as for HDAU (ATi) device onboard audio for GFX card with Audio controller HDMi - *************************************************************************************************************/ - case HDA_ATI_SB450: - case HDA_ATI_SB600: - case HDA_ATI_RS600: - case HDA_ATI_RS690: - case HDA_ATI_RS780: - case HDA_ATI_R600: - case HDA_ATI_RV630: - case HDA_ATI_RV610: - case HDA_ATI_RV670: - case HDA_ATI_RV635: - case HDA_ATI_RV620: - case HDA_ATI_RV770: - case HDA_ATI_RV730: - case HDA_ATI_RV710: - case HDA_ATI_RV740: - case HDA_ATI_RV870: - case HDA_ATI_RV840: - case HDA_ATI_RV830: - case HDA_ATI_RV810: - case HDA_ATI_RV970: - case HDA_ATI_RV940: - case HDA_ATI_RV930: - case HDA_ATI_RV910: - case HDA_ATI_R1000: - case HDA_ATI_VERDE: + CDBG("\tlooking for HDA bar0 on pci_addr 0x%x\n", pci_addr); + if (getHDABar(pci_addr, &bar_phys_addr) < 0) + { + return; + } - /* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */ - if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2) - { - uint8_t new_HDAU_layout_id[HDAU_LEN]; - if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0) - { - memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN); - verbose("Using user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", - default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); - } - } - else - { - verbose("Using default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", - default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]); - } + CDBG("\tfound HDA memory at 0x%x\n", bar_phys_addr); + hdaMemory = (struct HDARegs volatile*) bar_phys_addr; - devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/ - devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", 10); - devprop_add_value(device, "built-in", &BuiltIn, 1); - break; + tsc_frequency = Platform.CPU.TSCFrequency; + tsc_ticks_per_us = DivU64x32(tsc_frequency, 1000000U); // TSC ticks per microsecond + CDBG("\ttsc_ticks_per_us %d\n", tsc_ticks_per_us); - default: - break; + /* + * Enable Memory Space and Bus Mastering + */ + pci_cmd = pci_config_read16(pci_addr, PCI_COMMAND); + if ((pci_cmd & pci_cmd_wanted) != pci_cmd_wanted) + { + pci_cmd |= pci_cmd_wanted; + pci_config_write16(pci_addr, PCI_COMMAND, pci_cmd); } - verbose("Class code: [%04x]\nModel name: %s [%04x:%04x] (rev %02x)\nSubsystem: [%04x:%04x]\n%s\ndevice number: %d\n", - hda_dev->class_id, controller_name, hda_dev->vendor_id, hda_dev->device_id, hda_dev->revision_id, - hda_dev->subsys_id.subsys.vendor_id, hda_dev->subsys_id.subsys.device_id, devicepath, devices_number); + /* + * Remember entering reset state + */ + original_reset_state = (hdaMemory->gctl & HDAC_GCTL_CRST) ? 1U : 0U; - verbose("--------------------------------\n"); + /* + * Reset HDA Controller + */ + hdaMemory->wakeen = 0U; + hdaMemory->statests = UINT16_MAX; + hdaMemory->gsts = UINT16_MAX; + hdaMemory->intctl = 0U; + CDBG("\tStarting reset\n"); + hdaMemory->gctl = 0U; - stringdata = malloc(sizeof(uint8_t) * string->length); - memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); - stringlength = string->length; + /* + * Wait up to 10ms to enter Reset + */ + if (wait_for_register_state_16((uint16_t volatile const*) &hdaMemory->gctl, + HDAC_GCTL_CRST, + 0U, + 10000U, + tsc_ticks_per_us) < 0) + { + CDBG("\tHDA Controller 0x%x timed out 10ms entering reset\n", pci_addr); + return; + } + CDBG("\tReset asserted, delay 100us\n"); - return true; + /* + * Delay 2400 BCLK (100us) + */ + delay_us(100U, tsc_ticks_per_us); + CDBG("\tDeasserting reset\n"); + + /* + * Wait up to 10ms to exit Reset + */ + hdaMemory->gctl = HDAC_GCTL_CRST; + if (wait_for_register_state_16((uint16_t volatile const*) &hdaMemory->gctl, + HDAC_GCTL_CRST, + HDAC_GCTL_CRST, + 10000U, + tsc_ticks_per_us) < 0) + { + CDBG("\tHDA Controller 0x%x timed out 10ms exiting reset\n", pci_addr); + return; + } + CDBG("\tReset complete\n"); + + /* + * Wait 1ms for codecs to request enumeration (spec says 521us). + */ + delay_us(1000U, tsc_ticks_per_us); + + /* + * See which codecs want enumeration + */ + statests = hdaMemory->statests; + hdaMemory->statests = statests; // clear statests + CDBG("\tstatests is now 0x%x\n", statests); + codec_id = 0U; + while (statests) + { + if (statests & 1U) + { + probe_hda_codec(codec_id, &codec_info); + + verbose("\tFound %s (%04x%04x), rev(%04x)", + codec_info.name, + codec_info.vendor_id, + codec_info.device_id, + codec_info.revision_id); +#if DEBUG_CODEC + verbose(", stepping 0x%x, major rev 0x%x, minor rev 0x%x, %d function groups", + codec_info.stepping_id, + codec_info.maj_rev, + codec_info.min_rev, + codec_info.num_function_groups); +#endif + verbose("\n"); + } + ++codec_id; + statests >>= 1; + } + + /* + * Restore reset state entered with + */ + if (!original_reset_state) + { + hdaMemory->gctl = 0U; + } } Index: branches/zenith432/i386/libsaio/device_inject.h =================================================================== --- branches/zenith432/i386/libsaio/device_inject.h (revision 2804) +++ branches/zenith432/i386/libsaio/device_inject.h (revision 2805) @@ -79,6 +79,5 @@ void devprop_free_string(DevPropString *string); int devprop_add_network_template(DevPropDevice *device, uint16_t vendor_id); -int hex2bin(const char *hex, uint8_t *bin, int len); #endif /* !__LIBSAIO_DEVICE_INJECT_H */ Index: branches/zenith432/i386/libsaio/hda.h =================================================================== --- branches/zenith432/i386/libsaio/hda.h (revision 2804) +++ branches/zenith432/i386/libsaio/hda.h (revision 2805) @@ -62,7 +62,13 @@ #ifndef __LIBSAIO_HDA_H #define __LIBSAIO_HDA_H -bool setup_hda_devprop(pci_dt_t *hda_dev); +static char *get_hda_controller_name( uint16_t controller_device_id, uint16_t controller_vendor_id ); +static char *get_hda_codec_name( uint16_t codec_vendor_id, uint16_t codec_device_id, uint8_t codec_revision_id, uint8_t codec_stepping_id ); +bool setup_hda_devprop( pci_dt_t *hda_dev ); +static int immediate_command(uint32_t command, uint32_t* response); +static uint32_t get_parameter(uint8_t codec_id, uint8_t node_id, uint8_t parameter_id); +static int getHDABar(uint32_t pci_addr, uint32_t* bar_phys_addr); +void probe_hda_bus(uint32_t pci_addr); struct hda_controller_devices; typedef struct @@ -73,15 +79,13 @@ // char quirks_off; } hda_controller_devices; -/* struct hdacc_codecs; typedef struct { - uint32_t cid; - uint16_t revid; - char *name; + uint32_t id; + uint32_t rev; + const char *name; } hdacc_codecs; -*/ /**************************************************************************** * Miscellanious defines @@ -91,37 +95,43 @@ #define HDA_MODEL_CONSTRUCT(vendor, model) (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) /* Intel */ -#define INTEL_VENDORID 0x8086 -#define HDA_INTEL_OAK HDA_MODEL_CONSTRUCT(INTEL, 0x080a) // NEW -#define HDA_INTEL_BAY HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) // NEW +#define INTEL_VENDORID PCI_VENDOR_ID_INTEL +#define HDA_INTEL_OAK HDA_MODEL_CONSTRUCT(INTEL, 0x080a) +#define HDA_INTEL_BAY HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) #define HDA_INTEL_HSW1 HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c) #define HDA_INTEL_HSW2 HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c) #define HDA_INTEL_HSW3 HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c) +#define HDA_INTEL_BDW HDA_MODEL_CONSTRUCT(INTEL, 0x160c) #define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) #define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20) #define HDA_INTEL_PPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) // Macmini6,2 +#define HDA_INTEL_BRASWELL HDA_MODEL_CONSTRUCT(INTEL, 0x2284) #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) +#define HDA_INTEL_ICH9 HDA_MODEL_CONSTRUCT(INTEL, 0x293f) #define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) #define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) #define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57) -#define HDA_INTEL_MACBOOKPRO92 HDA_MODEL_CONSTRUCT(INTEL, 0x7270) // NEW +#define HDA_INTEL_MACBOOKPRO92 HDA_MODEL_CONSTRUCT(INTEL, 0x7270) #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) -#define HDA_INTEL_LPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) // NEW -#define HDA_INTEL_LPT2 HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) // NEW +#define HDA_INTEL_LPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) +#define HDA_INTEL_LPT2 HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) #define HDA_INTEL_WCPT HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0) #define HDA_INTEL_WELLS1 HDA_MODEL_CONSTRUCT(INTEL, 0x8d20) #define HDA_INTEL_WELLS2 HDA_MODEL_CONSTRUCT(INTEL, 0x8d21) +#define HDA_INTEL_WCPTLP HDA_MODEL_CONSTRUCT(INTEL, 0x9ca0) #define HDA_INTEL_LPTLP1 HDA_MODEL_CONSTRUCT(INTEL, 0x9c20) #define HDA_INTEL_LPTLP2 HDA_MODEL_CONSTRUCT(INTEL, 0x9c21) +#define HDA_INTEL_SRSPLP HDA_MODEL_CONSTRUCT(INTEL, 0x9d70) +#define HDA_INTEL_SRSP HDA_MODEL_CONSTRUCT(INTEL, 0xa170) #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) /* Nvidia */ -#define NVIDIA_VENDORID 0x10de +#define NVIDIA_VENDORID PCI_VENDOR_ID_NVIDIA // AppleHDA binary contain 0a00de10 (10de000a) // AppleHDAController binary contain de10ea0b (10de0bea) #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) @@ -164,9 +174,10 @@ #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) /* ATI */ -#define ATI_VENDORID 0x1002 +#define ATI_VENDORID PCI_VENDOR_ID_ATI #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) +#define HDA_ATI_HUDSON HDA_MODEL_CONSTRUCT(ATI, 0x780d) #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) @@ -191,6 +202,7 @@ #define HDA_ATI_RV930 HDA_MODEL_CONSTRUCT(ATI, 0xaa90) #define HDA_ATI_RV910 HDA_MODEL_CONSTRUCT(ATI, 0xaa98) #define HDA_ATI_R1000 HDA_MODEL_CONSTRUCT(ATI, 0xaaa0) +#define HDA_ATI_SI HDA_MODEL_CONSTRUCT(ATI, 0xaaa8) #define HDA_ATI_VERDE HDA_MODEL_CONSTRUCT(ATI, 0xaab0) #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) @@ -313,7 +325,7 @@ #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) /* Apple Computer Inc. */ -#define APPLE_VENDORID 0x106b +#define APPLE_VENDORID PCI_VENDOR_ID_APPLE #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) /* Sony */ @@ -326,8 +338,10 @@ * instead of their own, which is beyond my comprehension * (see HDA_CODEC_STAC9221 below). */ -#define APPLE_INTEL_MAC 0x76808384 -#define APPLE_MACBOOKPRO55 0xcb7910de +#define APPLE_INTEL_MAC 0x76808384 +#define APPLE_MACBOOKAIR31 0x0d9410de +#define APPLE_MACBOOKPRO55 0xcb7910de +#define APPLE_MACBOOKPRO71 0xcb8910de /* LG Electronics */ #define LG_VENDORID 0x1854 @@ -373,19 +387,27 @@ #define HDA0_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) ) #define HDA1_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) ) -/* codec information */ +/* =================== C O D E C I N F O R M A T I O N ===================== */ + #define HDA_CODEC_CONSTRUCT(vendor, id) (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) /* Cirrus Logic */ #define CIRRUSLOGIC_VENDORID 0x1013 #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) +#define HDA_CODEC_CS4208 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4208) #define HDA_CODEC_CS4210 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4210) +#define HDA_CODEC_CS4213 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4213) #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) /* Realtek */ -#define REALTEK_VENDORID 0x10ec +#define REALTEK_VENDORID PCI_VENDOR_ID_REALTEK #define HDA_CODEC_ALC221 HDA_CODEC_CONSTRUCT(REALTEK, 0x0221) +#define HDA_CODEC_ALC231 HDA_CODEC_CONSTRUCT(REALTEK, 0x0231) +#define HDA_CODEC_ALC233 HDA_CODEC_CONSTRUCT(REALTEK, 0x0233) +#define HDA_CODEC_ALC235 HDA_CODEC_CONSTRUCT(REALTEK, 0x0235) +#define HDA_CODEC_ALC255 HDA_CODEC_CONSTRUCT(REALTEK, 0x0255) +#define HDA_CODEC_ALC256 HDA_CODEC_CONSTRUCT(REALTEK, 0x0256) #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) @@ -396,18 +418,34 @@ #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) #define HDA_CODEC_ALC276 HDA_CODEC_CONSTRUCT(REALTEK, 0x0276) +#define HDA_CODEC_ALC280 HDA_CODEC_CONSTRUCT(REALTEK, 0x0280) +#define HDA_CODEC_ALC282 HDA_CODEC_CONSTRUCT(REALTEK, 0x0282) +#define HDA_CODEC_ALC283 HDA_CODEC_CONSTRUCT(REALTEK, 0x0283) +#define HDA_CODEC_ALC284 HDA_CODEC_CONSTRUCT(REALTEK, 0x0284) +#define HDA_CODEC_ALC285 HDA_CODEC_CONSTRUCT(REALTEK, 0x0285) +#define HDA_CODEC_ALC286 HDA_CODEC_CONSTRUCT(REALTEK, 0x0286) +#define HDA_CODEC_ALC288 HDA_CODEC_CONSTRUCT(REALTEK, 0x0288) +#define HDA_CODEC_ALC290 HDA_CODEC_CONSTRUCT(REALTEK, 0x0290) +#define HDA_CODEC_ALC292 HDA_CODEC_CONSTRUCT(REALTEK, 0x0292) +#define HDA_CODEC_ALC293 HDA_CODEC_CONSTRUCT(REALTEK, 0x0293) +#define HDA_CODEC_ALC298 HDA_CODEC_CONSTRUCT(REALTEK, 0x0298) #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) +#define HDA_CODEC_ALC667 HDA_CODEC_CONSTRUCT(REALTEK, 0x0667) +#define HDA_CODEC_ALC668 HDA_CODEC_CONSTRUCT(REALTEK, 0x0668) #define HDA_CODEC_ALC670 HDA_CODEC_CONSTRUCT(REALTEK, 0x0670) +#define HDA_CODEC_ALC671 HDA_CODEC_CONSTRUCT(REALTEK, 0x0671) #define HDA_CODEC_ALC680 HDA_CODEC_CONSTRUCT(REALTEK, 0x0680) #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) +#define HDA_CODEC_ALC867 HDA_CODEC_CONSTRUCT(REALTEK, 0x0867) #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) +#define HDA_CODEC_ALC886 HDA_CODEC_CONSTRUCT(REALTEK, 0x0886) #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) @@ -418,13 +456,13 @@ #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) /* Motorola */ -#define MOTO_VENDORID 0x1057 +#define MOTO_VENDORID PCI_VENDOR_ID_MOTOROLA #define HDA_CODEC_MOTOXXXX HDA_CODEC_CONSTRUCT(MOTO, 0xffff) /* Creative */ #define CREATIVE_VENDORID 0x1102 -#define HDA_CODEC_CA0110 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000a) -#define HDA_CODEC_CA0110_2 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000b) +#define HDA_CODEC_XFIEA HDA_CODEC_CONSTRUCT(CREATIVE, 0x000a) +#define HDA_CODEC_XFIED HDA_CODEC_CONSTRUCT(CREATIVE, 0x000b) #define HDA_CODEC_SB0880 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000d) #define HDA_CODEC_CA0132 HDA_CODEC_CONSTRUCT(CREATIVE, 0x0011) #define HDA_CODEC_CAXXXX HDA_CODEC_CONSTRUCT(CREATIVE, 0xffff) @@ -451,6 +489,7 @@ /* CMedia */ #define CMEDIA_VENDORID 0x13f6 +#define HDA_CODEC_CMI8880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x8880) #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x9880) #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) @@ -478,8 +517,12 @@ #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) +#define HDA_CODEC_STAC9202 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7632) +#define HDA_CODEC_STAC9202D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7633) #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) +#define HDA_CODEC_STAC9250D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7635) #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) +#define HDA_CODEC_STAC9250D_1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7637) #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) @@ -513,9 +556,14 @@ #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) +#define HDA_CODEC_IDT92HD88B3 HDA_CODEC_CONSTRUCT(IDT, 0x7666) +#define HDA_CODEC_IDT92HD88B1 HDA_CODEC_CONSTRUCT(IDT, 0x7667) +#define HDA_CODEC_IDT92HD88B2 HDA_CODEC_CONSTRUCT(IDT, 0x7668) +#define HDA_CODEC_IDT92HD88B4 HDA_CODEC_CONSTRUCT(IDT, 0x7669) #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) +#define HDA_CODEC_IDT92HD95 HDA_CODEC_CONSTRUCT(IDT, 0x7695) #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) #define HDA_CODEC_IDT92HD71B8_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b1) #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) @@ -591,6 +639,13 @@ #define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac) #define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8) #define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9) +#define HDA_CODEC_CX20751 HDA_CODEC_CONSTRUCT(CONEXANT, 0x510f) +#define HDA_CODEC_CX20751_2 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5110) +#define HDA_CODEC_CX20751_4 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5111) +#define HDA_CODEC_CX20755 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5113) +#define HDA_CODEC_CX20756 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5114) +#define HDA_CODEC_CX20757 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5115) +#define HDA_CODEC_CX20952 HDA_CODEC_CONSTRUCT(CONEXANT, 0x51d7) #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) /* VIA */ @@ -661,10 +716,12 @@ #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) +#define HDA_CODEC_NVIDIAGTX470 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0010) #define HDA_CODEC_NVIDIAGTS450 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0011) #define HDA_CODEC_NVIDIAGT440 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0014) #define HDA_CODEC_NVIDIAGTX550 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0015) #define HDA_CODEC_NVIDIAGTX570 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0018) +#define HDA_CODEC_NVIDIAGT610 HDA_CODEC_CONSTRUCT(NVIDIA, 0x001c) #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) @@ -680,9 +737,14 @@ #define HDA_CODEC_INTELEL HDA_CODEC_CONSTRUCT(INTEL, 0x2803) #define HDA_CODEC_INTELIP2 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) #define HDA_CODEC_INTELCPT HDA_CODEC_CONSTRUCT(INTEL, 0x2805) -#define HDA_CODEC_INTELPPT HDA_CODEC_CONSTRUCT(INTEL, 0x2806) -#define HDA_CODEC_INTELHSW HDA_CODEC_CONSTRUCT(INTEL, 0x2807) -#define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) +#define HDA_CODEC_INTELPPT HDA_CODEC_CONSTRUCT(INTEL, 0x2806) // Panther Point HDMI +#define HDA_CODEC_INTELLLP HDA_CODEC_CONSTRUCT(INTEL, 0x2807) // Haswell HDMI +#define HDA_CODEC_INTELBRW HDA_CODEC_CONSTRUCT(INTEL, 0x2808) // Broadwell HDMI +#define HDA_CODEC_INTELSKL HDA_CODEC_CONSTRUCT(INTEL, 0x2809) // Skylake HDMI +#define HDA_CODEC_INTELCDT HDA_CODEC_CONSTRUCT(INTEL, 0x2880) // CedarTrail HDMI +#define HDA_CODEC_INTELVLV HDA_CODEC_CONSTRUCT(INTEL, 0x2882) // Valleyview2 HDMI +#define HDA_CODEC_INTELBSW HDA_CODEC_CONSTRUCT(INTEL, 0x2883) // Braswell HDMI +#define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) // Crestline HDMI #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) /**************************************************************************** @@ -921,4 +983,50 @@ #define HDAC_SDSTS_FIFOE (1 << 3) #define HDAC_SDSTS_BCIS (1 << 2) +/**************************************************************************** + * Helper Macros + ****************************************************************************/ + +#define HDA_DMA_ALIGNMENT 128 + +#define HDA_BDL_MIN 2 +#define HDA_BDL_MAX 256 +#define HDA_BDL_DEFAULT HDA_BDL_MIN + +#define HDA_BLK_MIN HDA_DMA_ALIGNMENT +#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) + +#define HDA_BUFSZ_MIN (HDA_BDL_MIN * HDA_BLK_MIN) +#define HDA_BUFSZ_MAX 262144 +#define HDA_BUFSZ_DEFAULT 65536 + +#define HDA_GPIO_MAX 8 + +#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ +(fl) == 0xffffffff || \ +(((fl) & 0xffff0000) == 0xffff0000 && \ +((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ +(((fl) & 0x0000ffff) == 0x0000ffff && \ +((fl) & 0xffff0000) == ((v) & 0xffff0000))) + +#define HDA_MATCH_ALL 0xffffffff +#define HDA_INVALID 0xffffffff + +#define HDA_BOOTVERBOSE(stmt) do { \ + if (bootverbose != 0 || snd_verbose > 3) { \ + stmt \ + } \ +} while (0) + +#define HDA_BOOTHVERBOSE(stmt) do { \ + if (snd_verbose > 3) { \ + stmt \ + } \ +} while (0) + +#define hda_command(dev, verb) \ +HDAC_CODEC_COMMAND(device_get_parent(dev), (dev), (verb)) + +extern void probe_hda_bus(uint32_t pci_addr); + #endif /* !__LIBSAIO_HDA_H */ Index: branches/zenith432/i386/libsaio/dram_controllers.c =================================================================== --- branches/zenith432/i386/libsaio/dram_controllers.c (revision 2804) +++ branches/zenith432/i386/libsaio/dram_controllers.c (revision 2805) @@ -20,13 +20,13 @@ #include "dram_controllers.h" #ifndef DEBUG_DRAM -#define DEBUG_DRAM 0 + #define DEBUG_DRAM 0 #endif #if DEBUG_DRAM -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) + #define DBG(x...) #endif /* @@ -487,79 +487,58 @@ static struct mem_controller_t dram_controllers[] = { // Default unknown chipset - { 0, 0, "", NULL, NULL, NULL }, + { 0, 0, "", NULL, NULL, NULL }, // Intel -// { 0x8086, 0x0100, "2rd Gen Core processor", NULL, NULL, NULL }, -// { 0x8086, 0x0104, "2rd Gen Core processor", NULL, NULL, NULL }, -// { 0x8086, 0x010C, "Xeon E3-1200/2rd Gen Core processor", NULL, NULL, NULL }, -// { 0x8086, 0x0150, "Xeon E3-1200 v2/3rd Gen Core processor", NULL, NULL, NULL }, -// { 0x8086, 0x0154, "3rd Gen Core processor", NULL, NULL, NULL }, -// { 0x8086, 0x0158, "Xeon E3-1200 v2/Ivy Bridge", NULL, NULL, NULL }, -// { 0x8086, 0x015C, "Xeon E3-1200 v2/3rd Gen Core processor", NULL, NULL, NULL }, + { 0x8086, 0x7190, "VMWare", NULL, NULL, NULL }, -// { 0x8086, 0x0BF0, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, -// { 0x8086, 0x0BF1, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, -// { 0x8086, 0x0BF2, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, -// { 0x8086, 0x0BF3, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, -// { 0x8086, 0x0BF4, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, -// { 0x8086, 0x0BF5, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, -// { 0x8086, 0x0BF6, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, -// { 0x8086, 0x0BF7, "Atom Processor D2xxx/N2xxx", NULL, NULL, NULL }, - -// { 0x8086, 0x0C00, "Haswell", NULL, NULL, NULL }, -// { 0x8086, 0x0C04, "Haswell", NULL, NULL, NULL }, -// { 0x8086, 0x0C08, "Haswell", NULL, NULL, NULL }, - - { 0x8086, 0x7190, "VMWare", NULL, NULL, NULL }, - { 0x8086, 0x1A30, "82845 845 [Brookdale]", NULL, NULL, NULL }, { 0x8086, 0x2970, "82946GZ/PL/GL", setup_p35, get_fsb_i965, get_timings_i965 }, { 0x8086, 0x2990, "82Q963/Q965", setup_p35, get_fsb_i965, get_timings_i965 }, - { 0x8086, 0x29A0, "P965/G965", setup_p35, get_fsb_i965, get_timings_i965 }, + { 0x8086, 0x29A0, "P965/G965", setup_p35, get_fsb_i965, get_timings_i965 }, - { 0x8086, 0x2A00, "GM965/GL960", setup_p35, get_fsb_im965, get_timings_im965 }, - { 0x8086, 0x2A10, "GME965/GLE960", setup_p35, get_fsb_im965, get_timings_im965 }, - { 0x8086, 0x2A40, "PM/GM45/47", setup_p35, get_fsb_im965, get_timings_im965 }, + { 0x8086, 0x2A00, "GM965/GL960", setup_p35, get_fsb_im965, get_timings_im965 }, + { 0x8086, 0x2A10, "GME965/GLE960", setup_p35, get_fsb_im965, get_timings_im965 }, + { 0x8086, 0x2A40, "PM/GM45/47", setup_p35, get_fsb_im965, get_timings_im965 }, - { 0x8086, 0x29B0, "82Q35 Express", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0x29C0, "82G33/G31/P35/P31", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0x29D0, "82Q33 Express", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0x29E0, "82X38/X48 Express", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x29B0, "Q35", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x29C0, "P35/G33", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x29D0, "Q33", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x29E0, "X38/X48", setup_p35, get_fsb_i965, get_timings_p35 }, { 0x8086, 0x29F0, "3200/3210", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0x2E00, "Eaglelake", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0x2E10, "Q45/Q43", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0x2E20, "P45/G45", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0x2E30, "G41", setup_p35, get_fsb_i965, get_timings_p35 }, -// { 0x8086, 0x2E40, "4 Series Chipset", NULL, NULL, NULL }, -// { 0x8086, 0x2E90, "4 Series Chipset", NULL, NULL, NULL }, + { 0x8086, 0x2E00, "Eaglelake", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x2E10, "Q45/Q43", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x2E20, "P45/G45", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x2E30, "G41", setup_p35, get_fsb_i965, get_timings_p35 }, - { 0x8086, 0xD131, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, - { 0x8086, 0xD132, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0xD131, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0xD132, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, { 0x8086, 0x3400, "5520/5500/X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, { 0x8086, 0x3401, "5520/5500/X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, { 0x8086, 0x3402, "5520/5500/X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, - { 0x8086, 0x3403, "5500", setup_nhm, get_fsb_nhm, get_timings_nhm }, - { 0x8086, 0x3404, "5520/5500/X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, - { 0x8086, 0x3405, "5520/5500/X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, - { 0x8086, 0x3406, "5520", setup_nhm, get_fsb_nhm, get_timings_nhm }, - { 0x8086, 0x3407, "5520/5500/X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3403, "5500", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3404, "X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3405, "X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3406, "5520", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3407, "X58", setup_nhm, get_fsb_nhm, get_timings_nhm }, }; static const char *memory_channel_types[] = { - "Unknown", "Single", "Dual", "Triple" + "Unknown", "Single", "Dual", "Triple" /*, "Quad" */ }; void scan_dram_controller(pci_dt_t *dram_dev) { + verbose("[ DRAM CONTROLLER ]\n"); int i; - for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++) { + for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++) + { if ((dram_controllers[i].vendor == dram_dev->vendor_id) && (dram_controllers[i].device == dram_dev->device_id)) { - verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", - (dram_dev->vendor_id == 0x8086) ? "Intel Corporation " : "" , + verbose("\t%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", + (dram_dev->vendor_id == 0x8086) ? "Intel " : "" , dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id, dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func); @@ -575,7 +554,7 @@ dram_controllers[i].poll_speed(dram_dev); } - verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", + verbose("\tFrequency detected: %d MHz (%d) %s Channel \n\t\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", (uint32_t)Platform.RAM.Frequency / 1000000, (uint32_t)Platform.RAM.Frequency / 500000, memory_channel_types[Platform.RAM.Channels] @@ -584,4 +563,5 @@ // getchar(); } } + verbose("\n"); } Index: branches/zenith432/i386/libsaio/nvidia.c =================================================================== --- branches/zenith432/i386/libsaio/nvidia.c (revision 2804) +++ branches/zenith432/i386/libsaio/nvidia.c (revision 2805) @@ -52,17 +52,18 @@ #include "pci.h" #include "platform.h" #include "device_inject.h" +#include "convert.h" #include "nvidia.h" #include "nvidia_helper.h" #ifndef DEBUG_NVIDIA -#define DEBUG_NVIDIA 0 + #define DEBUG_NVIDIA 0 #endif #if DEBUG_NVIDIA -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) + #define DBG(x...) #endif #define NVIDIA_ROM_SIZE 0x20000 @@ -78,6 +79,7 @@ #define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16)) static bool showGeneric = false; +static bool nvidiaSingle = true; static bool doit = false; char generic_name[128]; extern uint32_t devices_number; @@ -90,11 +92,11 @@ const char *nvidia_device_type_child[] = { "device_type", "NVDA,Child" }; const char *nvidia_name_0[] = { "@0,name", "NVDA,Display-A" }; const char *nvidia_name_1[] = { "@1,name", "NVDA,Display-B" }; -const char *nvidia_slot_name[] = { "AAPL,slot-name", "Slot-1" }; +//const char *nvidia_slot_name[] = { "AAPL,slot-name", "Slot-1" }; static uint8_t default_NVCAP[]= { - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, + 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00 }; @@ -172,7 +174,8 @@ static nvidia_pci_info_t nvidia_card_generic[] = { // 0000 - 0040 { 0x10DE0000, "Unknown" }, - // 0040 - 004F + // 0040 - 004F +/* { 0x10DE0040, "GeForce 6800 Ultra" }, { 0x10DE0041, "GeForce 6800" }, { 0x10DE0042, "GeForce 6800 LE" }, @@ -185,6 +188,7 @@ { 0x10DE0049, "NV40GL" }, { 0x10DE004D, "Quadro FX 3400" }, { 0x10DE004E, "Quadro FX 4000" }, +*/ // 0050 - 005F // 0060 - 006F // 0070 - 007F @@ -199,9 +203,10 @@ { 0x10DE0098, "GeForce Go 7800" }, { 0x10DE0099, "GeForce Go 7800 GTX" }, { 0x10DE009D, "Quadro FX 4500" }, - // 00A0 - 00AF - // 00B0 - 00BF - // 00C0 - 00CF + // 00A0 - 00AF + // 00B0 - 00BF + // 00C0 - 00CF +/* { 0x10DE00C0, "GeForce 6800 GS" }, { 0x10DE00C1, "GeForce 6800" }, { 0x10DE00C2, "GeForce 6800 LE" }, @@ -222,11 +227,13 @@ { 0x10DE00F6, "GeForce 6800 GS/XT" }, { 0x10DE00F8, "Quadro FX 3400/4400" }, { 0x10DE00F9, "GeForce 6800 Series GPU" }, +*/ // 0100 - 010F // 0110 - 011F // 0120 - 012F // 0130 - 013F // 0140 - 014F +/* { 0x10DE0140, "GeForce 6600 GT" }, { 0x10DE0141, "GeForce 6600" }, { 0x10DE0142, "GeForce 6600 LE" }, @@ -258,6 +265,7 @@ { 0x10DE016A, "GeForce 7100 GS" }, { 0x10DE016C, "NVIDIA NV44GLM" }, { 0x10DE016D, "NVIDIA NV44GLM" }, +*/ // 0170 - 017F // 0180 - 018F // 0190 - 019F @@ -289,6 +297,7 @@ { 0x10DE01DF, "GeForce 7300 GS" }, // 01E0 - 01EF // 01F0 - 01FF +/* { 0x10DE01F0, "GeForce4 MX" }, // 0200 - 020F // 0210 - 021F @@ -311,6 +320,7 @@ { 0x10DE0247, "GeForce Go 6100" }, // 0250 - 025F { 0x10DE025B, "Quadro4 700 XGL" }, +*/ // 0260 - 026F // 0270 - 027F // 0280 - 028F @@ -343,6 +353,7 @@ { 0x10DE02E4, "GeForce 7950 GT" }, // 02F0 - 02FF // 0300 - 030F +/* { 0x10DE0301, "GeForce FX 5800 Ultra" }, { 0x10DE0302, "GeForce FX 5800" }, { 0x10DE0308, "Quadro FX 2000" }, @@ -390,6 +401,7 @@ { 0x10DE034C, "Quadro FX Go1000" }, { 0x10DE034E, "Quadro FX 1100" }, { 0x10DE034F, "NV36GL" }, +*/ // 0350 - 035F // 0360 - 036F // 0370 - 037F @@ -1161,6 +1173,7 @@ // 1100 - 110F // 1110 - 111F // 1120 - 112F + { 0x10DE1128, "GeForce GTX 970M" }, // 1130 - 113F // 1140 - 114F { 0x10DE1140, "GeForce GT 610M" }, @@ -1345,6 +1358,7 @@ // { 0x10DE1601, "Graphics Device" }, // // { 0x10DE1602, "Graphics Device" }, // // { 0x10DE1603, "Graphics Device" }, // + { 0x10DE1617, "GeForce GTX 980M" }, // // { 0x10DE1630, "Graphics Device" }, // // { 0x10DE1631, "Graphics Device" }, // // { 0x10DE1780, "Graphics Device" }, // @@ -1361,7 +1375,8 @@ // { 0x10DE17BD, "Graphics Device" }, // { 0x10DE17BE, "GM107 CS1" }, // GM107 // { 0x10DE17C1, "Graphics Device" }, // -// { 0x10DE17C2, "Graphics Device" }, // + { 0x10DE17C2, "GeForce GTX Titan X" }, // + { 0x10DE17C8, "GeForce GTX 980 TI" }, // { 0x10DE17EE, "Graphics Device" }, // // { 0x10DE17EF, "Graphics Device" }, // { 0x10DE17F0, "Quadro M6000" } @@ -1580,7 +1595,7 @@ { 0x10DE1248, 0x152D0930, "Quanta GeForce GT 635M" }, - { 0x10DE124D, 0x146210CC, "MSi GeForce GT 635M" }, + { 0x10DE124D, 0x146210CC, "MSi GeForce GT 635M" } }; static int patch_nvidia_rom(uint8_t *rom) @@ -1834,7 +1849,7 @@ int i, j; // First check in the plist, (for e.g this can override any hardcoded devices) - cardList_t * nvcard = FindCardWithIds(device_id, subsys_id); + cardList_t *nvcard = FindCardWithIds(device_id, subsys_id); if (nvcard) { if (nvcard->model) @@ -1846,8 +1861,8 @@ //ErmaC added selector for Chameleon "old" style in System Profiler if (getBoolForKey(kNvidiaGeneric, &showGeneric, &bootInfo->chameleonConfig)) { - verbose("NvidiaGeneric = Yes\n"); + for (i = 1; i < (sizeof(nvidia_card_generic) / sizeof(nvidia_card_generic[0])); i++) { if (nvidia_card_generic[i].device == device_id) @@ -1893,35 +1908,16 @@ return nvidia_card_generic[0].name; } -static uint32_t load_nvidia_bios_file(const char *filename, uint8_t **buf) +static int devprop_add_nvidia_template(DevPropDevice *device) { - int fd; - int size; + //char tmp[16]; + DBG("\tdevprop_add_nvidia_template\n"); - if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) + if (!device) { return 0; } - size = file_size(fd); - - if (size) - { - *buf = malloc(size); - size = read(fd, (char *)buf, size); - } - close(fd); - - return size > 0 ? size : 0; -} - -static int devprop_add_nvidia_template(struct DevPropDevice *device) -{ - char tmp[16]; - - if (!device) - return 0; - if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0)) { return 0; @@ -1937,19 +1933,28 @@ return 0; } - if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1)) + // Slice added selector for single nvidia card + if (!getBoolForKey(kNvidiaSingle, &nvidiaSingle, &bootInfo->chameleonConfig)) { - return 0; - } + if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1)) + { + return 0; + } - if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1)) - { - return 0; + if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1)) + { + return 0; + } + + if (!DP_ADD_TEMP_VAL(device, nvidia_name_1)) + { + return 0; + } + } - - if (!DP_ADD_TEMP_VAL(device, nvidia_name_1)) + else { - return 0; + DBG("\tNVidia: Injecting only device 0\n"); } if (devices_number == 1) @@ -1959,29 +1964,48 @@ return 0; } } - else + else if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child)) { - if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child)) - { return 0; - } } // Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0! // len = sprintf(tmp, "Slot-%x", devices_number); - snprintf(tmp, sizeof(tmp), "Slot-%x",devices_number); - devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp)); + //snprintf(tmp, sizeof(tmp), "Slot-%x",devices_number); + //devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, (uint32_t)strlen(tmp)); devices_number++; return 1; } -unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev, uint32_t device_id, uint32_t subsys_id) +static uint32_t load_nvidia_bios_file(const char *filename, uint8_t **buf) { + int fd; + int size; + + if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) + { + return 0; + } + + size = file_size(fd); + + if (size) + { + *buf = malloc(size); + size = read(fd, (char *)buf, size); + } + close(fd); + + return size > 0 ? size : 0; +} + +uint64_t mem_detect(volatile uint8_t *regs, uint16_t nvCardType, pci_dt_t *nvda_dev, uint32_t device_id, uint32_t subsys_id) +{ uint64_t vram_size = 0; // First check if any value exist in the plist - cardList_t * nvcard = FindCardWithIds(device_id, subsys_id); + cardList_t *nvcard = FindCardWithIds(device_id, subsys_id); if (nvcard) { if (nvcard->videoRam > 0) @@ -1992,6 +2016,24 @@ } } + // Finally, if vram_size still not set do the calculation with our own method + if (nvCardType < NV_ARCH_50) + { + vram_size = (uint64_t)(REG32( NV04_PFB_FIFO_DATA )); + vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; + } + else if (nvCardType < NV_ARCH_C0) + { + vram_size = (uint64_t)(REG32( NV04_PFB_FIFO_DATA )); + vram_size |= (vram_size & 0xff) << 32; + vram_size &= 0xffffffff00ll; + } + else + { // >= NV_ARCH_C0 + vram_size = REG32( NVC0_MEM_CTRLR_RAM_AMOUNT ) << 20; + vram_size *= REG32( NVC0_MEM_CTRLR_COUNT ); + } + // Then, Workaround for 9600M GT, GT 210/420/430/440/525M/540M & GTX 560M switch (nvda_dev->device_id) { @@ -2044,26 +2086,6 @@ break; } - if (!vram_size) - { - // Finally, if vram_size still not set do the calculation with our own method - if (nvCardType < NV_ARCH_50) - { - vram_size = (uint64_t)(REG32(NV04_PFB_FIFO_DATA)); - vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; - } - else if (nvCardType < NV_ARCH_C0) - { - vram_size = (uint64_t)(REG32(NV04_PFB_FIFO_DATA)); - vram_size |= (vram_size & 0xff) << 32; - vram_size &= 0xffffffff00ll; - } - else - { // >= NV_ARCH_C0 - vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20; - vram_size *= REG32(NVC0_MEM_CTRLR_COUNT); - } - } DBG("mem_detected %ld\n", vram_size); return vram_size; } @@ -2077,22 +2099,22 @@ bool setup_nvidia_devprop(pci_dt_t *nvda_dev) { - struct DevPropDevice *device = NULL; - char *devicepath = NULL; + DevPropDevice *device = NULL; + char *devicepath = NULL; + uint8_t *rom = NULL; + uint16_t nvCardType = 0; + uint64_t videoRam = 0; + uint32_t bar[7]; + uint32_t boot_display = 0; + int nvPatch = 0; + char *model = NULL; + char nvFilename[64]; option_rom_pci_header_t *rom_pci_header; volatile uint8_t *regs; - uint8_t *rom = NULL; - uint8_t nvCardType = 0; - uint64_t videoRam = 0; uint32_t nvBiosOveride; - uint32_t bar[7]; - uint32_t boot_display = 0; - int nvPatch = 0; int len; char biosVersion[64]; - char nvFilename[64]; char kNVCAP[12]; - char *model = NULL; const char *value; fill_card_list(); @@ -2104,6 +2126,8 @@ // get card type nvCardType = (REG32(0) >> 20) & 0x1ff; + verbose("\tClass code: [%04X]\n", nvda_dev->class_id); + model = get_nvidia_model(((nvda_dev->vendor_id << 16) | nvda_dev->device_id),((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id)); // Amount of VRAM in kilobytes @@ -2113,17 +2137,17 @@ if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit) { - verbose("Looking for nvidia video bios file %s\n", nvFilename); + verbose("\tLooking for nvidia video bios file %s\n", nvFilename); nvBiosOveride = load_nvidia_bios_file(nvFilename, &rom); if (nvBiosOveride > 0) { - verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride); + verbose("\tUsing nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride); DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride); } else { - printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename); + printf("\tERROR: unable to open nVidia Video BIOS File %s\n", nvFilename); free(rom); return false; } @@ -2145,7 +2169,7 @@ if (checkNvRomSig(nvRom)) { bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE); - DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + DBG("\tPROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); } else { @@ -2159,7 +2183,7 @@ if(checkNvRomSig(nvRom)) { bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE); - DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + DBG("\tPRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); } else { @@ -2169,12 +2193,12 @@ // Valid Signature ? if (!checkNvRomSig(rom)) { - printf("ERROR: Unable to locate nVidia Video BIOS\n"); + printf("\tERROR: Unable to locate nVidia Video BIOS\n"); return false; } else { - DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + DBG("\tROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); } }//end PRAM check }//end PROM check @@ -2182,7 +2206,7 @@ if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) { - printf("ERROR: nVidia ROM Patching Failed!\n"); + printf("\tERROR: nVidia ROM Patching Failed!\n"); free(rom); return false; } @@ -2203,15 +2227,18 @@ } else { - printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature); + printf("\tnVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature); } } - verbose("%s %dMB NV%02x [%04x:%04x]-[%04x:%04x] :: %s device number: %d\n", + verbose("\tdevice number: %d\n\t%s %dMB NV%02x [%04x:%04x]-[%04x:%04x]\n\t%s\n", + devices_number, model, (uint32_t)(videoRam / 1024 / 1024), (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id, nvda_dev->subsys_id.subsys.vendor_id, nvda_dev->subsys_id.subsys.device_id, - devicepath, devices_number); + devicepath); + verbose("\tNvidiaGeneric = %s\n", showGeneric ? "Yes" : "No"); + verbose("\tNvidiaSingle = %s\n", nvidiaSingle ? "Yes" : "No"); if (!string) { @@ -2222,10 +2249,7 @@ /* FIXME: for primary graphics card only */ boot_display = 1; - if (devices_number == 1) - { - devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t *)&boot_display, 4); - } + devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t *)&boot_display, 4); if (getBoolForKey(kUseIntelHDMI, &doit, &bootInfo->chameleonConfig) && doit) { @@ -2244,7 +2268,7 @@ // get bios version const int MAX_BIOS_VERSION_LENGTH = 32; - char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH); + char *version_str = (char *)malloc(MAX_BIOS_VERSION_LENGTH); memset(version_str, 0, MAX_BIOS_VERSION_LENGTH); @@ -2293,7 +2317,7 @@ if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) { - verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath); + verbose("\tUsing user supplied NVCAP for %s :: %s\n", model, devicepath); memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN); } } @@ -2306,7 +2330,7 @@ { memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN); - verbose("Using user supplied @0,display-cfg\n"); + verbose("\tUsing user supplied @0,display-cfg\n"); printf("@0,display-cfg: %02x%02x%02x%02x\n", default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]); } @@ -2321,7 +2345,7 @@ memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN); verbose("Using user supplied @1,display-cfg\n"); - printf("@1,display-cfg: %02x%02x%02x%02x\n", + printf("\t@1,display-cfg: %02x%02x%02x%02x\n", default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]); } } @@ -2337,10 +2361,12 @@ devprop_add_nvidia_template(device); devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN); + devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN); devprop_add_value(device, "VRAM,totalsize", (uint8_t *)&videoRam, 4); devprop_add_value(device, "model", (uint8_t *)model, strlen(model) + 1); devprop_add_value(device, "rom-revision", (uint8_t *)biosVersion, strlen(biosVersion) + 1); + devprop_add_value(device, "@0,display-cfg", (uint8_t *)&default_dcfg_0, DCFG0_LEN); devprop_add_value(device, "@1,display-cfg", (uint8_t *)&default_dcfg_1, DCFG1_LEN); Index: branches/zenith432/i386/libsaio/ntfs.c =================================================================== --- branches/zenith432/i386/libsaio/ntfs.c (revision 2804) +++ branches/zenith432/i386/libsaio/ntfs.c (revision 2805) @@ -155,7 +155,8 @@ int mftRecordSize; u_int64_t totalClusters; u_int64_t cluster, mftCluster; - size_t mftOffset; + // size_t mftOffset; + long long mftOffset; void *nameAttr; size_t nameSize; char *buf; Index: branches/zenith432/i386/libsaio/ati.c =================================================================== --- branches/zenith432/i386/libsaio/ati.c (revision 2804) +++ branches/zenith432/i386/libsaio/ati.c (revision 2805) @@ -6,7 +6,16 @@ */ #include "ati.h" +#ifndef DEBUG_ATI + #define DEBUG_ATI 0 +#endif +#if DEBUG_ATI + #define DBG(x...) printf(x) +#else + #define DBG(x...) msglog(x) +#endif + /* vals */ static value_t aty_name; static value_t aty_nameparent; @@ -54,10 +63,10 @@ {"Galago", 2}, {"Colobus", 2}, {"Mangabey", 2}, - {"Nomascus", 4}, + {"Nomascus", 4}, // 5 {"Orangutan", 2}, /* AMD6000Controller */ - {"Pithecia", 2}, + {"Pithecia", 2}, // 3 {"Bulrushes", 6}, {"Cattail", 4}, {"Hydrilla", 5}, @@ -98,7 +107,8 @@ /* AMD9000Controller */ {"Exmoor", 4}, {"Basset", 4}, - {"Greyhound", 6} + {"Greyhound", 6}, + {"Labrador", 6} }; static radeon_card_info_t radeon_cards[] = { @@ -1090,8 +1100,8 @@ { 0x6606, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon HD 8790M", kNull }, // Mobile { 0x6607, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon R5 M240", kNull }, // Mobile { 0x6608, 0x00000000, CHIP_FAMILY_OLAND, "AMD FirePro W2100", kNull }, - { 0x6610, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon R7 200 Series", kNull }, - { 0x6611, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon R7 200 Series", kNull }, + { 0x6610, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon R7 250", kFutomaki }, + { 0x6611, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon R7 340 Series", kNull }, { 0x6613, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon R7 240", kFutomaki }, // { 0x6620, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon", kNull }, // Mobile // { 0x6621, 0x00000000, CHIP_FAMILY_OLAND, "AMD Radeon", kNull }, // Mobile @@ -1100,23 +1110,24 @@ // BONAIRE { 0x6640, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon HD 8950", kNull }, // Mobile -// { 0x6641, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon", kNull }, // Mobile + { 0x6641, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon HD 8930M", kNull }, // Mobile { 0x6646, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon R9 M280X", kNull }, // Mobile { 0x6647, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon R9 M270X", kNull }, // Mobile { 0x6649, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD FirePro W5100", kNull }, // { 0x6650, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon", kNull }, // { 0x6651, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon", kNull }, - { 0x6658, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon R7 200", kNull }, + { 0x6658, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon R7 260X", kNull }, { 0x665C, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon HD 7790", kFutomaki }, { 0x665D, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon R9 260", kFutomaki }, + { 0x665F, 0x00000000, CHIP_FAMILY_BONAIRE, "AMD Radeon R9 360", kFutomaki }, // HAINAN - { 0x6660, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon HD 8600M", kNull }, // Mobile - { 0x6663, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon HD 8500M", kNull }, // Mobile - { 0x6664, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon R5 M200", kNull }, // Mobile - { 0x6665, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon R5 M200", kNull }, // Mobile - { 0x6667, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon R5 M200", kNull }, // Mobile - { 0x666F, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon HD 8500M", kNull }, // Mobile + { 0x6660, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon HD 8670M", kNull }, // Mobile + { 0x6663, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon HD 8570M", kNull }, // Mobile + { 0x6664, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon R5 M240", kNull }, // Mobile + { 0x6665, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon R5 M230", kNull }, // Mobile + { 0x6667, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon R5 M230", kNull }, // Mobile + { 0x666F, 0x00000000, CHIP_FAMILY_HAINAN, "AMD Radeon HD 8550M", kNull }, // Mobile // CAYMAN { 0x6701, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6xxx Series", kLotus }, @@ -1130,12 +1141,12 @@ { 0x6709, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6xxx Series", kLotus }, { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970 Series", kLotus }, { 0x6719, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950 Series", kLotus }, - { 0x671C, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970 Series", kLotus }, + { 0x671C, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6990 Series", kLotus }, { 0x671D, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6950 Series", kLotus }, { 0x671F, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6930 Series", kLotus }, // BARTS - { 0x6720, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6900M Series", kFanwort }, + { 0x6720, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6970M Series", kFanwort }, { 0x6722, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6900M Series", kFanwort }, { 0x6729, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6900M Series", kFanwort }, { 0x6738, 0x00000000, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870 Series", kDuckweed }, @@ -1145,7 +1156,7 @@ // TURKS { 0x6740, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6770M Series", kCattail }, { 0x6741, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6750M", kCattail }, - { 0x6742, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 7500/7600 Series", kCattail }, + { 0x6742, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 7500/7600", kCattail }, { 0x6745, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6600M Series", kCattail }, { 0x6749, 0x00000000, CHIP_FAMILY_TURKS, "ATI Radeon FirePro V4900", kPithecia }, { 0x674A, 0x00000000, CHIP_FAMILY_TURKS, "AMD FirePro V3900", kPithecia }, @@ -1170,17 +1181,17 @@ // TAHITI //Framebuffers: Aji - 4 Desktop, Buri - 4 Mobile, Chutoro - 5 Mobile, Dashimaki - 4, IkuraS - HMDI // Ebi - 5 Mobile, Gari - 5 M, Futomaki - 4 D, Hamachi - 4 D, OPM - 6 Server, Ikura - 6 - { 0x6780, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, + { 0x6780, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kIkuraS }, { 0x6784, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, { 0x6788, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, - { 0x678A, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, - { 0x6790, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, + { 0x678A, 0x00000000, CHIP_FAMILY_TAHITI, "AMD FirePro W8000", kFutomaki }, + { 0x6790, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7970" , kFutomaki }, { 0x6791, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, { 0x6792, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, { 0x6798, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7970X/8970/R9 280X", kFutomaki }, { 0x6799, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7990 Series", kAji }, { 0x679A, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7950/8950/R9 280", kFutomaki }, - { 0x679B, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7900 Series", kFutomaki }, + { 0x679B, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7990 Series", kChutoro }, { 0x679E, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7870 XT", kFutomaki }, { 0x679F, 0x00000000, CHIP_FAMILY_TAHITI, "AMD Radeon HD 7950 Series", kFutomaki }, @@ -1205,7 +1216,7 @@ { 0x6806, 0x00000000, CHIP_FAMILY_PITCAIRN, "AMD Radeon HD 7600 Series", kFutomaki }, { 0x6808, 0x00000000, CHIP_FAMILY_PITCAIRN, "AMD Radeon HD 7600 Series", kFutomaki }, { 0x6809, 0x00000000, CHIP_FAMILY_PITCAIRN, "ATI FirePro V", kNull }, - { 0x6810, 0x00000000, CHIP_FAMILY_PITCAIRN, "AMD Radeon R9 270X", kFutomaki }, + { 0x6810, 0x00000000, CHIP_FAMILY_PITCAIRN, "AMD Radeon R9 270X", kNamako }, { 0x6811, 0x00000000, CHIP_FAMILY_PITCAIRN, "AMD Radeon R9 270", kFutomaki }, // { 0x6816, 0x00000000, CHIP_FAMILY_PITCAIRN, "AMD Radeon", kFutomaki }, // { 0x6817, 0x00000000, CHIP_FAMILY_PITCAIRN, "AMD Radeon", kFutomaki }, @@ -1230,12 +1241,12 @@ { 0x6830, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7800M Series", kBuri }, // Mobile { 0x6831, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kBuri }, // Mobile { 0x6835, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD R7 Series", kBuri }, - { 0x6837, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kBuri }, - { 0x6838, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kBuri }, - { 0x6839, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kBuri }, - { 0x683B, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kBuri }, - { 0x683D, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7770 Series", kBuri }, - { 0x683F, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7750 Series", kBuri }, + { 0x6837, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7730 Series", kFutomaki }, + { 0x6838, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kFutomaki }, + { 0x6839, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kFutomaki }, + { 0x683B, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7700 Series", kFutomaki }, + { 0x683D, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7770 Series", kFutomaki }, //R7 250X + { 0x683F, 0x00000000, CHIP_FAMILY_VERDE, "AMD Radeon HD 7750 Series", kFutomaki }, // TURKS { 0x6840, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 7670M Series", kPondweed }, // Mobile @@ -1286,9 +1297,9 @@ { 0x68BF, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 6750 Series", kHoolock }, // REDWOOD - { 0x68C0, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730 Series", kBaboon }, // Mobile - { 0x68C1, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5650 Series", kBaboon }, // Mobile - { 0x68C7, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5570", kEulemur }, // Mobile + { 0x68C0, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730 Series", kGalago }, // Mobile + { 0x68C1, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5650 Series", kGalago }, // Mobile + { 0x68C7, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Mobility Radeon HD 5570", kGalago }, // Mobile { 0x68C8, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI FirePro v4800", kBaboon }, { 0x68C9, 0x00000000, CHIP_FAMILY_REDWOOD, "FirePro 3D V3800", kBaboon }, { 0x68D8, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670 Series", kBaboon }, @@ -1297,10 +1308,10 @@ { 0x68DE, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5000 Series", kNull }, // CEDAR - { 0x68E0, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470 Series", kEulemur }, - { 0x68E1, 0x00000000, CHIP_FAMILY_CEDAR, "AMD Radeon HD 6230", kEulemur }, - { 0x68E4, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 6370M Series", kEulemur }, - { 0x68E5, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 6300M Series", kEulemur }, + { 0x68E0, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470 Series", kGalago }, + { 0x68E1, 0x00000000, CHIP_FAMILY_CEDAR, "AMD Radeon HD 6230", kGalago }, + { 0x68E4, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 6370M Series", kGalago }, + { 0x68E5, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 6300M Series", kGalago }, // { 0x68E8, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD ??? Series", kNull }, // { 0x68E9, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD ??? Series", kNull }, { 0x68F1, 0x00000000, CHIP_FAMILY_CEDAR, "AMD FirePro 2460", kEulemur }, @@ -1310,6 +1321,15 @@ { 0x68FA, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 7300 Series", kEulemur }, // { 0x68FE, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD ??? Series", kNull }, + // + { 0x6900, 0x00000000, CHIP_FAMILY_TOPAS, "ATI Radeon R7 M260/M265", kExmoor }, + { 0x6901, 0x00000000, CHIP_FAMILY_TOPAS, "ATI Radeon R5 M255", kExmoor }, + { 0x6920, 0x00000000, CHIP_FAMILY_AMETHYST, "ATI Radeon R9 M395X", kLabrador }, + { 0x6921, 0x00000000, CHIP_FAMILY_AMETHYST, "ATI Radeon R9 M295X", kExmoor }, + { 0x692B, 0x00000000, CHIP_FAMILY_TONGA, "ATI Firepro W7100", kBaladi }, + { 0x6938, 0x00000000, CHIP_FAMILY_AMETHYST, "ATI Radeon R9 M295X", kExmoor }, + { 0x6939, 0x00000000, CHIP_FAMILY_TONGA, "ATI Radeon R9 285", kBaladi }, + // R520 { 0x7100, 0x00000000, CHIP_FAMILY_R520, "ATI Radeon HD Desktop ", kNull }, { 0x7101, 0x00000000, CHIP_FAMILY_R520, "ATI Radeon HD Mobile ", kNull }, @@ -1768,6 +1788,9 @@ "Hawaii", /* ... */ "Mullins", + "Topas", + "Amethyst", + "Tonga", "" }; @@ -2025,7 +2048,7 @@ { if (devprop_list[i].get_value(val)) { - devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii + devprop_list[i].name[1] = (uint8_t)(0x30 + pnum); // convert to ascii devprop_add_value(card->device, devprop_list[i].name, val->data, val->size); free_val(val); } @@ -2049,7 +2072,7 @@ { if (devprop_list[i].default_val.type != kNul) { - devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii + devprop_list[i].name[1] = (uint8_t)(0x30 + pnum); // convert to ascii devprop_add_value(card->device, devprop_list[i].name, devprop_list[i].default_val.type == kCst ? (uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, @@ -2388,32 +2411,32 @@ if (card->info == NULL) // Jief { - verbose("Unsupported ATI card! Device ID: [%04x:%04x] Subsystem ID: [%04x:%04x] \n", + DBG("Unsupported ATI card! Device ID: [%04x:%04x] Subsystem ID: [%04x:%04x] \n", pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys.vendor_id, pci_dev->subsys_id.subsys.device_id); return false; } - verbose("Found ATI card! Device ID:[%04X:%04X] Subsystem ID:[%08X] - Radeon [%04X:%08X] %s\n", + DBG("Found ATI card! Device ID:[%04X:%04X] Subsystem ID:[%08X] - Radeon [%04X:%08X] %s\n", pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id, card->info->device_id, card->info->subsys_id, card->info->model_name); card->fb = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_0) & ~0x0f); card->mmio = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f); card->io = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03); - verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n", + DBG("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n", (unsigned) card->fb, (unsigned) card->mmio, (unsigned) card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS)); card->posted = radeon_card_posted(); - verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed"); - verbose("\n"); + DBG("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed"); + DBG("\n"); get_vram_size(); getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->chameleonConfig); - + if (add_vbios) { if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id)) { - verbose("reading Video BIOS from %s", card->posted ? "legacy space" : "PCI ROM"); + DBG("reading Video BIOS from %s", card->posted ? "legacy space" : "PCI ROM"); if (card->posted) { read_vbios(false); @@ -2429,7 +2452,7 @@ if (card->info->chip_family >= CHIP_FAMILY_CEDAR) { - verbose("ATI Radeon EVERGREEN family\n"); + DBG("ATI Radeon EVERGREEN family\n"); card->flags |= EVERGREEN; } @@ -2444,7 +2467,7 @@ card->cfg_name = card_configs[card->info->cfg_name].name; // which means one of the fb's or kNull - verbose("Framebuffer set to device's default: %s\n", card->cfg_name); + DBG("Framebuffer set to device's default: %s\n", card->cfg_name); } else { @@ -2457,8 +2480,8 @@ // if a value bigger than 0 ?? is found, (do we need >= 0 ?? that's null FB on card_configs) if (n_ports > 0) { - card->ports = n_ports; // use it. - verbose("(AtiPorts) # of ports set to: %d\n", card->ports); + card->ports = (uint8_t)n_ports; // use it. + DBG("(AtiPorts) Nr of ports set to: %d\n", card->ports); } else { @@ -2471,7 +2494,7 @@ } } - verbose("# of ports set to framebuffer's default: %d\n", card->ports); + DBG("Nr of ports set to framebuffer's default: %d\n", card->ports); } @@ -2492,6 +2515,8 @@ { char *devicepath; + verbose("\tClass code: [%04X]\n", ati_dev->class_id ); + if (!init_card(ati_dev)) { return false; @@ -2539,15 +2564,13 @@ stringlength = string->length; // ------------------------------------------------- - verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n", + DBG("\tATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x])\n\t%s\n", chip_family_name[card->info->chip_family], card->info->model_name, (uint32_t)(card->vram_size / (1024 * 1024)), card->cfg_name, ati_dev->vendor_id, ati_dev->device_id, ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id, devicepath); - verbose("---------------------------------------------\n"); - free(card); return true; Index: branches/zenith432/i386/libsaio/sys.c =================================================================== --- branches/zenith432/i386/libsaio/sys.c (revision 2804) +++ branches/zenith432/i386/libsaio/sys.c (revision 2805) @@ -72,14 +72,18 @@ static unsigned char kFSUUIDNamespaceSHA1[] = {0xB3,0xE2,0x0F,0x39,0xF2,0x92,0x11,0xD6,0x97,0xA4,0x00,0x30,0x65,0x43,0xEC,0xAC}; #endif -#if DEBUG -#define DBG(x...) printf(x) +#ifndef DEBUG_SYS + #define DEBUG_SYS 0 +#endif + +#if DEBUG_SYS + #define DBG(x...) printf(x) #else -#define DBG(x...) msglog(x) + #define DBG(x...) msglog(x) #endif -#ifndef DEBUG_FEATURE_LAST_BOOT -#define DEBUG_FEATURE_LAST_BOOT 0 // AllocateKernelMemory error with feature from 2562 +#ifndef FEATURE_LAST_BOOT + #define FEATURE_LAST_BOOT 0 // AllocateKernelMemory error with feature from 2562 #endif extern int multiboot_partition; @@ -965,15 +969,12 @@ BVRef bvr1 = NULL; BVRef bvr2 = NULL; -#if DEBUG_FEATURE_LAST_BOOT +#if FEATURE_LAST_BOOT char dirSpec[] = "hd(%d,%d)/"; char fileSpec[] = "Volumes"; -#endif char *label; -#if DEBUG_FEATURE_LAST_BOOT u_int32_t time; u_int32_t lasttime = 0; - long flags; #endif @@ -993,13 +994,22 @@ if ( (bvr->part_no == multiboot_partition) && (bvr->biosdev == gBIOSDev) ) { +#if FEATURE_LAST_BOOT label = bvr->label[0] ? bvr->label : (bvr->altlabel[0] ? bvr->altlabel : (bvr->name[0] ? bvr->name : "Untitled")); DBG("Multiboot partition set: hd(%d,%d) '%s'\n", BIOS_DEV_UNIT(bvr), bvr->part_no, label); +#endif return bvr; } } } +#if 0 + DBG("multiboot_partition_set = %d\n", multiboot_partition_set); + DBG("multiboot_partition = %d\n", multiboot_partition); + DBG("multiboot_skip_partition_set = %d\n", multiboot_skip_partition_set); + DBG("multiboot_skip_partition = %d\n", multiboot_skip_partition); +#endif + /* * Checking "Default Partition" key in system configuration - use format: hd(x,y), the volume UUID or label - * to override the default selection. @@ -1018,15 +1028,17 @@ if (matchVolumeToString(bvr, val, false)) { free(val); +#if FEATURE_LAST_BOOT label = bvr->label[0] ? bvr->label : (bvr->altlabel[0] ? bvr->altlabel : (bvr->name[0] ? bvr->name : "Untitled")); DBG("User default partition set: hd(%d,%d) '%s'\n", BIOS_DEV_UNIT(bvr), bvr->part_no, label); +#endif return bvr; } } free(val); } -#if DEBUG_FEATURE_LAST_BOOT // the above code cause "AllocateKernelMemory error" +#if FEATURE_LAST_BOOT // the above code cause "AllocateKernelMemory error" // Bungo: select last booted partition as the boot volume // TODO: support other OSes (foreign boot) for (bvr = chain; bvr; bvr = bvr->next) @@ -1128,8 +1140,10 @@ } bvr = bvr2 ? bvr2 : (bvr1 ? bvr1 : chain); +#if FEATURE_LAST_BOOT label = bvr->label[0] ? bvr->label : (bvr->altlabel[0] ? bvr->altlabel : (bvr->name[0] ? bvr->name : "Untitled")); DBG("Default partition set: hd(%d,%d) '%s'\n", BIOS_DEV_UNIT(bvr), bvr->part_no, label); +#endif return bvr; } Index: branches/zenith432/i386/libsaio/load.c =================================================================== --- branches/zenith432/i386/libsaio/load.c (revision 2804) +++ branches/zenith432/i386/libsaio/load.c (revision 2805) @@ -32,9 +32,9 @@ #include #if DEBUG -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) msglog(x) + #define DBG(x...) msglog(x) #endif static long DecodeSegment(long cmdBase, unsigned int*load_addr, unsigned int *load_size); @@ -44,7 +44,7 @@ static unsigned long gBinaryAddress; bool gHaveKernelCache; /* XXX aserebln: uninitialized? and only set to true, never to false */ -cpu_type_t archCpuType=CPU_TYPE_I386; +cpu_type_t archCpuType = CPU_TYPE_I386; //============================================================================== @@ -182,8 +182,8 @@ switch (cmd) { + case LC_SEGMENT: case LC_SEGMENT_64: - case LC_SEGMENT: ret = DecodeSegment(cmdBase, &load_addr, &load_size); if (ret == 0 && load_size != 0 && load_addr >= KERNEL_ADDR) @@ -193,6 +193,7 @@ } break; + case LC_MAIN: /* Mountain Lion's replacement for LC_UNIXTHREAD */ case LC_UNIXTHREAD: ret = DecodeUnixThread(cmdBase, &entry); break; @@ -257,7 +258,7 @@ struct segment_command_64 *segCmd; segCmd = (struct segment_command_64 *)cmdBase; vmaddr = (segCmd->vmaddr & 0x3fffffff); - vmsize = segCmd->vmsize; + vmsize = segCmd->vmsize; fileaddr = (gBinaryAddress + segCmd->fileoff); filesize = segCmd->filesize; segname = segCmd->segname; @@ -288,6 +289,8 @@ #endif } +//=================================================== + if (vmsize == 0 || filesize == 0) { *load_addr = ~0; Index: branches/zenith432/i386/libsaio/acpi.h =================================================================== --- branches/zenith432/i386/libsaio/acpi.h (revision 2804) +++ branches/zenith432/i386/libsaio/acpi.h (revision 2805) @@ -3,6 +3,9 @@ #define ACPI_RANGE_START (0x0E0000) #define ACPI_RANGE_END (0x0FFFFF) +#define EBDA_RANGE_MIN (0x080000) +#define EBDA_RANGE_END (0x09FFFF) +#define BDA_EBDA_START (0x00040E) #define UINT64_LE_FROM_CHARS(a,b,c,d,e,f,g,h) \ ( ((uint64_t)h << 56) \ @@ -17,6 +20,14 @@ #define ACPI_SIGNATURE_UINT64_LE UINT64_LE_FROM_CHARS('R','S','D',' ','P','T','R',' ') +#define swapUint16(x) ((((uint16_t)x & 0xFF00) >> 8) | \ + (((uint16_t)x & 0x00FF) << 8)) + +#define swapUint32(x) ((((uint32_t)x & 0xFF000000) >> 24) | \ + (((uint32_t)x & 0x00FF0000) >> 16) | \ + (((uint32_t)x & 0x0000FF00) >> 8) | \ + (((uint32_t)x & 0x000000FF) << 24)) + /* Per ACPI 3.0a spec */ // TODO Migrate @@ -35,6 +46,19 @@ char Reserved[3]; } __attribute__((packed)); +struct acpi_2_header +{ + char Signature[4]; + uint32_t Length; + uint8_t Revision; + uint8_t Checksum; + char OEMID[6]; + char OEMTableId[8]; + uint32_t OEMRevision; + uint32_t CreatorId; + uint32_t CreatorRevision; +} __attribute__((packed)); + // TODO Migrate struct acpi_2_rsdt { @@ -77,6 +101,16 @@ uint32_t CreatorRevision; } __attribute__((packed)); +struct ssdt_pmref +{ + char oemTabID[9]; + char byte1; + uint32_t addr; + char byte2; + uint32_t length; + char byte3; +} __attribute__((packed)); + // TODO Migrate struct acpi_2_dsdt { @@ -103,7 +137,7 @@ uint32_t OEMRevision; uint32_t CreatorId; uint32_t CreatorRevision; - uint32_t FIRMWARE_CTRL; + uint32_t FACS; uint32_t DSDT; uint8_t Model; // JrCs uint8_t PM_Profile; // JrCs @@ -152,11 +186,24 @@ uint8_t Reset_Value; uint8_t Reserved[3]; - uint64_t X_FIRMWARE_CTRL; + uint64_t X_FACS; uint64_t X_DSDT; /* End Asere */ /*We absolutely don't care about theese fields*/ uint8_t notimp2[96]; } __attribute__((packed)); +struct acpi_2_facs +{ + char Signature[4]; + uint32_t Length; + uint32_t HWSignature; + uint32_t FWWakingVector32; + uint32_t GlobalLock; + uint32_t Flags; + uint64_t FWWakingVector64; + uint8_t Version; + uint8_t Reserved[31]; +} __attribute__((packed)); + #endif /* !__LIBSAIO_ACPI_H */ Index: branches/zenith432/i386/libsaio/ati.h =================================================================== --- branches/zenith432/i386/libsaio/ati.h (revision 2804) +++ branches/zenith432/i386/libsaio/ati.h (revision 2805) @@ -99,6 +99,9 @@ CHIP_FAMILY_HAWAII, /* ... */ CHIP_FAMILY_MULLINS, + CHIP_FAMILY_TOPAS, + CHIP_FAMILY_AMETHYST, + CHIP_FAMILY_TONGA, CHIP_FAMILY_LAST } ati_chip_family_t; @@ -193,10 +196,11 @@ kExmoor, kBasset, kGreyhound, + kLabrador, kCfgEnd } config_name_t; -//radeon card (includes teh AtiConfig) +//radeon card (includes the AtiConfig) typedef struct { uint16_t device_id; uint32_t subsys_id; Index: branches/zenith432/i386/libsaio/platform.c =================================================================== --- branches/zenith432/i386/libsaio/platform.c (revision 2804) +++ branches/zenith432/i386/libsaio/platform.c (revision 2805) @@ -40,14 +40,17 @@ void scan_mem() { static bool done = false; - if (done) { + if (done) + { return; } /* our code only works on Intel chipsets so make sure here */ if (pci_config_read16(PCIADDR(0, 0x00, 0), 0x00) != 0x8086) { bootInfo->memDetect = false; - } else { + } + else + { bootInfo->memDetect = true; } /* manually */ Index: branches/zenith432/i386/libsaio/cpu.c =================================================================== --- branches/zenith432/i386/libsaio/cpu.c (revision 2804) +++ branches/zenith432/i386/libsaio/cpu.c (revision 2805) @@ -1,6 +1,7 @@ /* * Copyright 2008 Islam Ahmed Zaid. All rights reserved. * AsereBLN: 2009: cleanup and bugfix + * Bronya: 2015 Improve AMD support, cleanup and bugfix */ #include "libsaio.h" @@ -10,15 +11,27 @@ #include "boot.h" #ifndef DEBUG_CPU -#define DEBUG_CPU 0 + #define DEBUG_CPU 0 #endif #if DEBUG_CPU -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) + #define DBG(x...) #endif + +#define UI_CPUFREQ_ROUNDING_FACTOR 10000000 + +clock_frequency_info_t gPEClockFrequencyInfo; + +static __unused uint64_t rdtsc32(void) +{ + unsigned int lo,hi; + __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi)); + return ((uint64_t)hi << 32) | lo; +} + /* * timeRDTSC() * This routine sets up PIT counter 2 to count down 1/20 of a second. @@ -28,7 +41,7 @@ static uint64_t timeRDTSC(void) { int attempts = 0; - uint64_t latchTime; + uint32_t latchTime; uint64_t saveTime,intermediate; unsigned int timerValue, lastValue; //boolean_t int_enabled; @@ -54,18 +67,18 @@ //int_enabled = ml_set_interrupts_enabled(false); restart: - if (attempts >= 9) // increase to up to 9 attempts. + if (attempts >= 3) // increase to up to 9 attempts. { // This will flash-reboot. TODO: Use tscPanic instead. - printf("Timestamp counter calibation failed with %d attempts\n", attempts); + //printf("Timestamp counter calibation failed with %d attempts\n", attempts); } attempts++; enable_PIT2(); // turn on PIT2 set_PIT2(0); // reset timer 2 to be zero - latchTime = rdtsc64(); // get the time stamp to time + latchTime = rdtsc32(); // get the time stamp to time latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes set_PIT2(SAMPLE_CLKS_INT); // set up the timer for (almost) 1/20th a second - saveTime = rdtsc64(); // now time how long a 20th a second is... + saveTime = rdtsc32(); // now time how long a 20th a second is... get_PIT2(&lastValue); get_PIT2(&lastValue); // read twice, first value may be unreliable do { @@ -79,9 +92,9 @@ } lastValue = timerValue; } while (timerValue > 5); - printf("timerValue %d\n",timerValue); - printf("intermediate 0x%016llX\n",intermediate); - printf("saveTime 0x%016llX\n",saveTime); + //printf("timerValue %d\n",timerValue); + //printf("intermediate 0x%016llX\n",intermediate); + //printf("saveTime 0x%016llX\n",saveTime); intermediate -= saveTime; // raw count for about 1/20 second intermediate *= scale[timerValue]; // rescale measured time spent @@ -98,7 +111,7 @@ /* * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer */ -static uint64_t measure_tsc_frequency(void) +static uint64_t __unused measure_tsc_frequency(void) { uint64_t tscStart; uint64_t tscEnd; @@ -167,164 +180,130 @@ return retval; } -/* - * Original comment/code: - * "DFE: Measures the Max Performance Frequency in Hz (64-bit)" - * - * Measures the Actual Performance Frequency in Hz (64-bit) - * (just a naming change, mperf --> aperf ) - */ -static uint64_t measure_aperf_frequency(void) +static uint64_t rtc_set_cyc_per_sec(uint64_t cycles); +#define RTC_FAST_DENOM 0xFFFFFFFF + +inline static uint32_t +create_mul_quant_GHZ(int shift, uint32_t quant) { - uint64_t aperfStart; - uint64_t aperfEnd; - uint64_t aperfDelta = 0xffffffffffffffffULL; - unsigned long pollCount; - uint64_t retval = 0; - int i; + return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant); +} - /* Time how many APERF ticks elapse in 30 msec using the 8254 PIT - * counter 2. We run this loop 3 times to make sure the cache - * is hot and we take the minimum delta from all of the runs. - * That is to say that we're biased towards measuring the minimum - * number of APERF ticks that occur while waiting for the timer to - * expire. - */ - for(i = 0; i < 10; ++i) +struct { + mach_timespec_t calend_offset; + boolean_t calend_is_set; + + int64_t calend_adjtotal; + int32_t calend_adjdelta; + + uint32_t boottime; + + mach_timebase_info_data_t timebase_const; + + decl_simple_lock_data(,lock) /* real-time clock device lock */ +} rtclock; + +uint32_t rtc_quant_shift; /* clock to nanos right shift */ +uint32_t rtc_quant_scale; /* clock to nanos multiplier */ +uint64_t rtc_cyc_per_sec; /* processor cycles per sec */ +uint64_t rtc_cycle_count; /* clocks in 1/20th second */ + +static uint64_t rtc_set_cyc_per_sec(uint64_t cycles) +{ + + if (cycles > (NSEC_PER_SEC/20)) { - enable_PIT2(); - set_PIT2_mode0(CALIBRATE_LATCH); - aperfStart = rdmsr64(MSR_AMD_APERF); - pollCount = poll_PIT2_gate(); - aperfEnd = rdmsr64(MSR_AMD_APERF); - /* The poll loop must have run at least a few times for accuracy */ - if (pollCount <= 1) - { - continue; - } - /* The TSC must increment at LEAST once every millisecond. - * We should have waited exactly 30 msec so the APERF delta should - * be >= 30. Anything less and the processor is way too slow. - */ - if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC) - { - continue; - } - // tscDelta = MIN(tscDelta, (tscEnd - tscStart)) - if ( (aperfEnd - aperfStart) < aperfDelta ) - { - aperfDelta = aperfEnd - aperfStart; - } + // we can use just a "fast" multiply to get nanos + rtc_quant_shift = 32; + rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles); + rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20 + rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM; } - /* mperfDelta is now the least number of MPERF ticks the processor made in - * a timespan of 0.03 s (e.g. 30 milliseconds) + else + { + rtc_quant_shift = 26; + rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles); + rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20 + rtclock.timebase_const.denom = (uint32_t)cycles; + } + rtc_cyc_per_sec = cycles*20; // multiply it by 20 and we are done.. + // BUT we also want to calculate... + + cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2)) + / UI_CPUFREQ_ROUNDING_FACTOR) + * UI_CPUFREQ_ROUNDING_FACTOR; + + /* + * Set current measured speed. */ - - if (aperfDelta > (1ULL<<32)) + if (cycles >= 0x100000000ULL) { - retval = 0; + gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL; } else { - retval = aperfDelta * 1000 / 30; + gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles; } - disable_PIT2(); - return retval; + gPEClockFrequencyInfo.cpu_frequency_hz = cycles; + + //printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20); + return(rtc_cyc_per_sec); } +// Bronya C1E fix +void post_startup_cpu_fixups(void) +{ + /* + * Some AMD processors support C1E state. Entering this state will + * cause the local APIC timer to stop, which we can't deal with at + * this time. + */ + + uint64_t reg; + verbose("\tLooking to disable C1E if is already enabled by the BIOS:\n"); + reg = rdmsr64(MSR_AMD_INT_PENDING_CMP_HALT); + /* Disable C1E state if it is enabled by the BIOS */ + if ((reg >> AMD_ACTONCMPHALT_SHIFT) & AMD_ACTONCMPHALT_MASK) + { + reg &= ~(AMD_ACTONCMPHALT_MASK << AMD_ACTONCMPHALT_SHIFT); + wrmsr64(MSR_AMD_INT_PENDING_CMP_HALT, reg); + verbose("\tC1E disabled!\n"); + } +} + /* * Calculates the FSB and CPU frequencies using specific MSRs for each CPU * - multi. is read from a specific MSR. In the case of Intel, there is: * a max multi. (used to calculate the FSB freq.), * and a current multi. (used to calculate the CPU freq.) - * - fsbFrequency = tscFrequency / multi - * - cpuFrequency = fsbFrequency * multi + * - busFrequency = tscFrequency / multi + * - cpuFrequency = busFrequency * multi */ -void scan_cpu(PlatformInfo_t *p) -{ - uint64_t tscFrequency = 0; - uint64_t fsbFrequency = 0; - uint64_t cpuFrequency = 0; - uint64_t msr = 0; - uint64_t flex_ratio = 0; - uint32_t max_ratio = 0; - uint32_t min_ratio = 0; - uint32_t reg[4]; // = {0, 0, 0, 0}; - uint32_t cores_per_package = 0; - uint32_t logical_per_package = 1; - uint32_t threads_per_core = 1; +/* Decimal powers: */ +#define kilo (1000ULL) +#define Mega (kilo * kilo) +#define Giga (kilo * Mega) +#define Tera (kilo * Giga) +#define Peta (kilo * Tera) - uint8_t bus_ratio_max = 0; - uint8_t bus_ratio_min = 0; - uint8_t currdiv = 0; - uint8_t currcoef = 0; - uint8_t maxdiv = 0; - uint8_t maxcoef = 0; - uint8_t pic0_mask; +#define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo)) - const char *newratio; +void get_cpuid(PlatformInfo_t *p) +{ + char str[128]; + uint32_t reg[4]; char *s = 0; - int len = 0; - int myfsb = 0; - int i = 0; - /* get cpuid values */ do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor - p->CPU.Vendor = p->CPU.CPUID[CPUID_0][ebx]; - do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features - - if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((bit(28) & p->CPU.CPUID[CPUID_1][edx]) != 0)) // Intel && HTT/Multicore - { - logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16); - } - do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N + do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); // Get the max extended cpuid - /* Based on Apple's XNU cpuid.c - Deterministic cache parameters */ - if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000)) - { - for (i = 0; i < 0xFF; i++) // safe loop - { - do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index - if (bitfield(reg[eax], 4, 0) == 0) - { - break; - } - //cores_per_package = bitfield(reg[eax], 31, 26) + 1; - } - } - - do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); - - if (i > 0) - { - cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index - threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1; - } - - if (cores_per_package == 0) - { - cores_per_package = 1; - } - - if (p->CPU.CPUID[CPUID_0][0] >= 0x5) // Monitor/Mwait - { - do_cpuid(5, p->CPU.CPUID[CPUID_5]); - } - - if (p->CPU.CPUID[CPUID_0][0] >= 6) // Thermal/Power - { - do_cpuid(6, p->CPU.CPUID[CPUID_6]); - } - - do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); - if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) { do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]); @@ -335,31 +314,8 @@ do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]); } -/* http://www.flounder.com/cpuid_explorer2.htm - EAX (Intel): - 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 - +--------+----------------+--------+----+----+--------+--------+--------+ - |########|Extended family |Extmodel|####|type|familyid| model |stepping| - +--------+----------------+--------+----+----+--------+--------+--------+ +// ============================================================== - EAX (AMD): - 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 - +--------+----------------+--------+----+----+--------+--------+--------+ - |########|Extended family |Extmodel|####|####|familyid| model |stepping| - +--------+----------------+--------+----+----+--------+--------+--------+ -*/ - - p->CPU.Vendor = p->CPU.CPUID[CPUID_0][1]; - p->CPU.Signature = p->CPU.CPUID[CPUID_1][0]; - p->CPU.Stepping = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); // stepping = cpu_feat_eax & 0xF; - p->CPU.Model = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); // model = (cpu_feat_eax >> 4) & 0xF; - p->CPU.Family = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); // family = (cpu_feat_eax >> 8) & 0xF; - //p->CPU.Type = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12); // type = (cpu_feat_eax >> 12) & 0x3; - p->CPU.ExtModel = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); // ext_model = (cpu_feat_eax >> 16) & 0xF; - p->CPU.ExtFamily = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20); // ext_family = (cpu_feat_eax >> 20) & 0xFF; - - p->CPU.Model += (p->CPU.ExtModel << 4); - /* get BrandString (if supported) */ /* Copyright: from Apple's XNU cpuid.c */ if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) @@ -393,44 +349,193 @@ p->CPU.BrandString[0] = '\0'; } p->CPU.BrandString[47] = '\0'; -// DBG("Brandstring = %s\n", p->CPU.BrandString); +// DBG("\tBrandstring = %s\n", p->CPU.BrandString); } - /* - * Find the number of enabled cores and threads - * (which determines whether SMT/Hyperthreading is active). - */ +// ============================================================== + + switch(p->CPU.BrandString[0]) + { + case 'A': + /* AMD Processors */ + // The cache information is only in ecx and edx so only save + // those registers + + do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait + + do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch + do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch + do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]); + + break; + + case 'G': + /* Intel Processors */ + do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); // Cache Index for Inte + + if (p->CPU.CPUID[CPUID_0][0] >= 0x5) // Monitor/Mwait + { + do_cpuid(5, p->CPU.CPUID[CPUID_5]); + } + + if (p->CPU.CPUID[CPUID_0][0] >= 6) // Thermal/Power + { + do_cpuid(6, p->CPU.CPUID[CPUID_6]); + } + + break; + } +} +void scan_cpu(PlatformInfo_t *p) +{ + verbose("[ CPU INFO ]\n"); + get_cpuid(p); + + uint64_t busFCvtt2n; + uint64_t tscFCvtt2n; + uint64_t tscFreq = 0; + uint64_t busFrequency = 0; + uint64_t cpuFrequency = 0; + uint64_t msr = 0; + uint64_t flex_ratio = 0; + uint64_t cpuid_features; + + uint32_t max_ratio = 0; + uint32_t min_ratio = 0; + uint32_t reg[4]; + uint32_t cores_per_package = 0; + uint32_t logical_per_package = 1; + uint32_t threads_per_core = 1; + + uint8_t bus_ratio_max = 0; + uint8_t bus_ratio_min = 0; + uint8_t currdiv = 0; + uint8_t currcoef = 0; + uint8_t maxdiv = 0; + uint8_t maxcoef = 0; + uint8_t pic0_mask; + uint8_t cpuMultN2 = 0; + + const char *newratio; + + int len = 0; + int myfsb = 0; + int i = 0; + + +/* http://www.flounder.com/cpuid_explorer2.htm + EAX (Intel): + 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 + +--------+----------------+--------+----+----+--------+--------+--------+ + |########|Extended family |Extmodel|####|type|familyid| model |stepping| + +--------+----------------+--------+----+----+--------+--------+--------+ + + EAX (AMD): + 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0 + +--------+----------------+--------+----+----+--------+--------+--------+ + |########|Extended family |Extmodel|####|####|familyid| model |stepping| + +--------+----------------+--------+----+----+--------+--------+--------+ +*/ + ///////////////////-- MaxFn,Vendor --//////////////////////// + p->CPU.Vendor = p->CPU.CPUID[CPUID_0][1]; + + ///////////////////-- Signature, stepping, features -- ////// + cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]); + if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore + { + logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16); + } + else + { + logical_per_package = 1; + } + + p->CPU.Signature = p->CPU.CPUID[CPUID_1][0]; + p->CPU.Stepping = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); // stepping = cpu_feat_eax & 0xF; + p->CPU.Model = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); // model = (cpu_feat_eax >> 4) & 0xF; + p->CPU.Family = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); // family = (cpu_feat_eax >> 8) & 0xF; + //p->CPU.Type = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12); // type = (cpu_feat_eax >> 12) & 0x3; + p->CPU.ExtModel = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); // ext_model = (cpu_feat_eax >> 16) & 0xF; + p->CPU.ExtFamily = (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20); // ext_family = (cpu_feat_eax >> 20) & 0xFF; + + if (p->CPU.Family == 0x0f) + { + p->CPU.Family += p->CPU.ExtFamily; + } + + if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06) + { + p->CPU.Model += (p->CPU.ExtModel << 4); + } + switch (p->CPU.Vendor) { case CPUID_VENDOR_INTEL: + { + /* Based on Apple's XNU cpuid.c - Deterministic cache parameters */ + if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000)) + { + for (i = 0; i < 0xFF; i++) // safe loop + { + do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index + if (bitfield(reg[eax], 4, 0) == 0) + { + break; + } + cores_per_package = bitfield(reg[eax], 31, 26) + 1; + } + } + + if (i > 0) + { + cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index + threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1; + } + + if (cores_per_package == 0) + { + cores_per_package = 1; + } + switch (p->CPU.Model) { - case CPUID_MODEL_NEHALEM: - case CPUID_MODEL_FIELDS: - case CPUID_MODEL_DALES: + case CPUID_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + case CPUID_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) + case CPUID_MODEL_CLARKDALE: // Intel Core i3, i5, i7 LGA1156 (32nm) case CPUID_MODEL_NEHALEM_EX: case CPUID_MODEL_JAKETOWN: case CPUID_MODEL_SANDYBRIDGE: case CPUID_MODEL_IVYBRIDGE: - + case CPUID_MODEL_HASWELL_U5: case CPUID_MODEL_HASWELL: case CPUID_MODEL_HASWELL_SVR: //case CPUID_MODEL_HASWELL_H: case CPUID_MODEL_HASWELL_ULT: - case CPUID_MODEL_CRYSTALWELL: + case CPUID_MODEL_HASWELL_ULX: + case CPUID_MODEL_BROADWELL_HQ: + case CPUID_MODEL_BRODWELL_SVR: + case CPUID_MODEL_SKYLAKE_S: //case CPUID_MODEL_: - msr = rdmsr64(MSR_CORE_THREAD_COUNT); + msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35 p->CPU.NoCores = (uint32_t)bitfield((uint32_t)msr, 31, 16); p->CPU.NoThreads = (uint32_t)bitfield((uint32_t)msr, 15, 0); break; - case CPUID_MODEL_DALES_32NM: - case CPUID_MODEL_WESTMERE: + case CPUID_MODEL_DALES: + case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core case CPUID_MODEL_WESTMERE_EX: msr = rdmsr64(MSR_CORE_THREAD_COUNT); p->CPU.NoCores = (uint32_t)bitfield((uint32_t)msr, 19, 16); p->CPU.NoThreads = (uint32_t)bitfield((uint32_t)msr, 15, 0); break; + case CPUID_MODEL_ATOM_3700: + case CPUID_MODEL_ATOM: + p->CPU.NoCores = 2; + p->CPU.NoThreads = 2; + break; + default: + p->CPU.NoCores = 0; + break; } if (p->CPU.NoCores == 0) @@ -438,35 +543,77 @@ p->CPU.NoCores = cores_per_package; p->CPU.NoThreads = logical_per_package; } - break; + // MSR is *NOT* available on the Intel Atom CPU + // workaround for N270. I don't know why it detected wrong + if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270"))) + { + p->CPU.NoCores = 1; + p->CPU.NoThreads = 2; + } + + + // workaround for Xeon Harpertown and Yorkfield + if ((p->CPU.Model == CPUID_MODEL_PENRYN) && + (p->CPU.NoCores == 0)) + { + if ((strstr(p->CPU.BrandString, "X54")) || + (strstr(p->CPU.BrandString, "E54")) || + (strstr(p->CPU.BrandString, "W35")) || + (strstr(p->CPU.BrandString, "X34")) || + (strstr(p->CPU.BrandString, "X33")) || + (strstr(p->CPU.BrandString, "L33")) || + (strstr(p->CPU.BrandString, "X32")) || + (strstr(p->CPU.BrandString, "L3426")) || + (strstr(p->CPU.BrandString, "L54"))) + { + p->CPU.NoCores = 4; + p->CPU.NoThreads = 4; + } else if (strstr(p->CPU.BrandString, "W36")) { + p->CPU.NoCores = 6; + p->CPU.NoThreads = 6; + } else { //other Penryn and Wolfdale + p->CPU.NoCores = 0; + p->CPU.NoThreads = 0; + } + } + + // workaround for Quad + if ( strstr(p->CPU.BrandString, "Quad") ) + { + p->CPU.NoCores = 4; + p->CPU.NoThreads = 4; + } + } + + break; + case CPUID_VENDOR_AMD: - p->CPU.NoCores = (uint32_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1; - p->CPU.NoThreads = (uint32_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16); - if (p->CPU.NoCores == 0) + { + post_startup_cpu_fixups(); + cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1; + threads_per_core = cores_per_package; + + if (cores_per_package == 0) { - p->CPU.NoCores = 1; + cores_per_package = 1; } - if (p->CPU.NoThreads < p->CPU.NoCores) + p->CPU.NoCores = cores_per_package; + p->CPU.NoThreads = logical_per_package; + + if (p->CPU.NoCores == 0) { - p->CPU.NoThreads = p->CPU.NoCores; + p->CPU.NoCores = 1; + p->CPU.NoThreads = 1; } + } + break; - break; - - default: + default : stop("Unsupported CPU detected! System halted."); } - //workaround for N270. I don't know why it detected wrong - // MSR is *NOT* available on the Intel Atom CPU - if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270"))) - { - p->CPU.NoCores = 1; - p->CPU.NoThreads = 2; - } - /* setup features */ if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) { @@ -508,7 +655,7 @@ p->CPU.Features |= CPU_FEATURE_MSR; } - if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && (p->CPU.NoThreads > p->CPU.NoCores)) + if ((p->CPU.NoThreads > p->CPU.NoCores)) { p->CPU.Features |= CPU_FEATURE_HTT; } @@ -516,23 +663,18 @@ pic0_mask = inb(0x21U); outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests - tscFrequency = measure_tsc_frequency(); - DBG("cpu freq classic = 0x%016llx\n", tscFrequency); + uint64_t cycles; + cycles = timeRDTSC(); + tscFreq = rtc_set_cyc_per_sec(cycles); + DBG("cpu freq classic = 0x%016llx\n", tscFreq); // if usual method failed - if ( tscFrequency < 1000 ) //TEST + if ( tscFreq < 1000 ) //TEST { - tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency(); + tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency(); // DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency); } - else - { - // DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20); - } - fsbFrequency = 0; - cpuFrequency = 0; - - if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))) + if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))) { int intelCPU = p->CPU.Model; if (p->CPU.Family == 0x06) @@ -542,8 +684,8 @@ { case CPUID_MODEL_NEHALEM: case CPUID_MODEL_FIELDS: + case CPUID_MODEL_CLARKDALE: case CPUID_MODEL_DALES: - case CPUID_MODEL_DALES_32NM: case CPUID_MODEL_WESTMERE: case CPUID_MODEL_NEHALEM_EX: case CPUID_MODEL_WESTMERE_EX: @@ -552,11 +694,15 @@ case CPUID_MODEL_JAKETOWN: case CPUID_MODEL_IVYBRIDGE_XEON: case CPUID_MODEL_IVYBRIDGE: + case CPUID_MODEL_ATOM_3700: case CPUID_MODEL_HASWELL: + case CPUID_MODEL_HASWELL_U5: case CPUID_MODEL_HASWELL_SVR: case CPUID_MODEL_HASWELL_ULT: - case CPUID_MODEL_CRYSTALWELL: + case CPUID_MODEL_HASWELL_ULX: + case CPUID_MODEL_BROADWELL_HQ: + case CPUID_MODEL_SKYLAKE_S: /* --------------------------------------------------------- */ msr = rdmsr64(MSR_PLATFORM_INFO); DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0)); @@ -593,7 +739,7 @@ if (bus_ratio_max) { - fsbFrequency = (tscFrequency / bus_ratio_max); + busFrequency = (tscFreq / bus_ratio_max); } //valv: Turbo Ratio Limit @@ -601,13 +747,14 @@ { msr = rdmsr64(MSR_TURBO_RATIO_LIMIT); - cpuFrequency = bus_ratio_max * fsbFrequency; + cpuFrequency = bus_ratio_max * busFrequency; max_ratio = bus_ratio_max * 10; } else { - cpuFrequency = tscFrequency; + cpuFrequency = tscFreq; } + if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) { max_ratio = atoi(newratio); @@ -617,12 +764,12 @@ max_ratio = (max_ratio + 5); } - verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio); + verbose("\tBus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio); // extreme overclockers may love 320 ;) if ((max_ratio >= min_ratio) && (max_ratio <= 320)) { - cpuFrequency = (fsbFrequency * max_ratio) / 10; + cpuFrequency = (busFrequency * max_ratio) / 10; if (len >= 3) { maxdiv = 1; @@ -642,8 +789,8 @@ p->CPU.MaxRatio = max_ratio; p->CPU.MinRatio = min_ratio; - myfsb = fsbFrequency / 1000000; - verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout + myfsb = busFrequency / 1000000; + verbose("\tSticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout currcoef = bus_ratio_max; break; @@ -679,20 +826,20 @@ { if (maxdiv) { - fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1)); + busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1)); } else { - fsbFrequency = (tscFrequency / maxcoef); + busFrequency = (tscFreq / maxcoef); } if (currdiv) { - cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2); + cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2); } else { - cpuFrequency = (fsbFrequency * currcoef); + cpuFrequency = (busFrequency * currcoef); } DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : ""); @@ -706,167 +853,297 @@ p->CPU.Features |= CPU_FEATURE_MOBILE; } } - else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f)) + + else if (p->CPU.Vendor==CPUID_VENDOR_AMD) { - switch(p->CPU.ExtFamily) + switch(p->CPU.Family) { - case 0x00: //* K8 *// - msr = rdmsr64(K8_FIDVID_STATUS); - maxcoef = bitfield(msr, 21, 16) / 2 + 4; - currcoef = bitfield(msr, 5, 0) / 2 + 4; + case 0xF: /* K8 */ + { + uint64_t fidvid = 0; + uint64_t cpuMult; + uint64_t fid; + + fidvid = rdmsr64(K8_FIDVID_STATUS); + fid = bitfield(fidvid, 5, 0); + + cpuMult = (fid + 8) / 2; + currcoef = cpuMult; + + cpuMultN2 = (fidvid & (uint64_t)bit(0)); + currdiv = cpuMultN2; + /****** Addon END ******/ + } break; - case 0x01: //* K10 *// - msr = rdmsr64(K10_COFVID_STATUS); - do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]); - // EffFreq: effective frequency interface - if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1) + case 0x10: /*** AMD Family 10h ***/ + { + uint64_t cofvid = 0; + uint64_t cpuMult; + uint64_t divisor = 0; + uint64_t did; + uint64_t fid; + + cofvid = rdmsr64(K10_COFVID_STATUS); + did = bitfield(cofvid, 8, 6); + fid = bitfield(cofvid, 5, 0); + if (did == 0) divisor = 2; + else if (did == 1) divisor = 4; + else if (did == 2) divisor = 8; + else if (did == 3) divisor = 16; + else if (did == 4) divisor = 32; + + cpuMult = (fid + 16) / divisor; + currcoef = cpuMult; + + cpuMultN2 = (cofvid & (uint64_t)bit(0)); + currdiv = cpuMultN2; + + /****** Addon END ******/ + } + break; + + case 0x11: /*** AMD Family 11h ***/ + { + uint64_t cofvid = 0; + uint64_t cpuMult; + uint64_t divisor = 0; + uint64_t did; + uint64_t fid; + + cofvid = rdmsr64(K10_COFVID_STATUS); + did = bitfield(cofvid, 8, 6); + fid = bitfield(cofvid, 5, 0); + if (did == 0) divisor = 2; + else if (did == 1) divisor = 4; + else if (did == 2) divisor = 8; + else if (did == 3) divisor = 16; + else if (did == 4) divisor = 32; + + cpuMult = (fid + 8) / divisor; + currcoef = cpuMult; + + cpuMultN2 = (cofvid & (uint64_t)bit(0)); + currdiv = cpuMultN2; + + /****** Addon END ******/ + } + break; + + case 0x12: /*** AMD Family 12h ***/ + { + // 8:4 CpuFid: current CPU core frequency ID + // 3:0 CpuDid: current CPU core divisor ID + uint64_t prfsts,CpuFid,CpuDid; + prfsts = rdmsr64(K10_COFVID_STATUS); + + CpuDid = bitfield(prfsts, 3, 0) ; + CpuFid = bitfield(prfsts, 8, 4) ; + uint64_t divisor; + switch (CpuDid) { - //uint64_t mperf = measure_mperf_frequency(); - uint64_t aperf = measure_aperf_frequency(); - cpuFrequency = aperf; + case 0: divisor = 1; break; + case 1: divisor = (3/2); break; + case 2: divisor = 2; break; + case 3: divisor = 3; break; + case 4: divisor = 4; break; + case 5: divisor = 6; break; + case 6: divisor = 8; break; + case 7: divisor = 12; break; + case 8: divisor = 16; break; + default: divisor = 1; break; } - // NOTE: tsc runs at the maccoeff (non turbo) - // *not* at the turbo frequency. - maxcoef = bitfield(msr, 54, 49) / 2 + 4; - currcoef = bitfield(msr, 5, 0) + 0x10; - currdiv = 2 << bitfield(msr, 8, 6); + currcoef = (CpuFid + 0x10) / divisor; + cpuMultN2 = (prfsts & (uint64_t)bit(0)); + currdiv = cpuMultN2; + + } break; - case 0x05: //* K14 *// - msr = rdmsr64(K10_COFVID_STATUS); - currcoef = (bitfield(msr, 54, 49) + 0x10) << 2; - currdiv = (bitfield(msr, 8, 4) + 1) << 2; + case 0x14: /* K14 */ + + { + // 8:4: current CPU core divisor ID most significant digit + // 3:0: current CPU core divisor ID least significant digit + uint64_t prfsts; + prfsts = rdmsr64(K10_COFVID_STATUS); + + uint64_t CpuDidMSD,CpuDidLSD; + CpuDidMSD = bitfield(prfsts, 8, 4) ; + CpuDidLSD = bitfield(prfsts, 3, 0) ; + + uint64_t frequencyId = 0x10; + currcoef = (frequencyId + 0x10) / + (CpuDidMSD + (CpuDidLSD * 0.25) + 1); + currdiv = ((CpuDidMSD) + 1) << 2; currdiv += bitfield(msr, 3, 0); + cpuMultN2 = (prfsts & (uint64_t)bit(0)); + currdiv = cpuMultN2; + } + break; - case 0x02: //* K11 *// - // not implimented + case 0x15: /*** AMD Family 15h ***/ + case 0x06: /*** AMD Family 06h ***/ + { + + uint64_t cofvid = 0; + uint64_t cpuMult; + uint64_t divisor = 0; + uint64_t did; + uint64_t fid; + + cofvid = rdmsr64(K10_COFVID_STATUS); + did = bitfield(cofvid, 8, 6); + fid = bitfield(cofvid, 5, 0); + if (did == 0) divisor = 2; + else if (did == 1) divisor = 4; + else if (did == 2) divisor = 8; + else if (did == 3) divisor = 16; + else if (did == 4) divisor = 32; + + cpuMult = (fid + 16) / divisor; + currcoef = cpuMult; + + cpuMultN2 = (cofvid & (uint64_t)bit(0)); + currdiv = cpuMultN2; + } break; - } - if (maxcoef) - { - if (currdiv) + case 0x16: /*** AMD Family 16h kabini ***/ { - if (!currcoef) - { - currcoef = maxcoef; - } + uint64_t cofvid = 0; + uint64_t cpuMult; + uint64_t divisor = 0; + uint64_t did; + uint64_t fid; - if (!cpuFrequency) - { - fsbFrequency = ((tscFrequency * currdiv) / currcoef); - } - else - { - fsbFrequency = ((cpuFrequency * currdiv) / currcoef); - } - DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv); + cofvid = rdmsr64(K10_COFVID_STATUS); + did = bitfield(cofvid, 8, 6); + fid = bitfield(cofvid, 5, 0); + if (did == 0) divisor = 1; + else if (did == 1) divisor = 2; + else if (did == 2) divisor = 4; + else if (did == 3) divisor = 8; + else if (did == 4) divisor = 16; + + cpuMult = (fid + 16) / divisor; + currcoef = cpuMult; + + cpuMultN2 = (cofvid & (uint64_t)bit(0)); + currdiv = cpuMultN2; + /****** Addon END ******/ } - else + break; + + default: { - if (!cpuFrequency) - { - fsbFrequency = (tscFrequency / maxcoef); - } - else - { - fsbFrequency = (cpuFrequency / maxcoef); - } - DBG("%d\n", currcoef); + typedef unsigned long long vlong; + uint64_t prfsts; + prfsts = rdmsr64(K10_COFVID_STATUS); + uint64_t r; + vlong hz; + r = (prfsts>>6) & 0x07; + hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<CPU.MaxCoef = maxcoef; - p->CPU.MaxDiv = maxdiv; + p->CPU.MaxCoef = maxcoef = currcoef; + p->CPU.MaxDiv = maxdiv = currdiv; p->CPU.CurrCoef = currcoef; p->CPU.CurrDiv = currdiv; - p->CPU.TSCFrequency = tscFrequency; - p->CPU.FSBFrequency = fsbFrequency; + p->CPU.TSCFrequency = tscFreq; + p->CPU.FSBFrequency = busFrequency; p->CPU.CPUFrequency = cpuFrequency; // keep formatted with spaces instead of tabs - DBG("\n------------------------------\n"); - DBG("\tCPU INFO\n"); - DBG("------------------------------\n"); - DBG("CPUID Raw Values:\n"); + DBG("\tCPUID Raw Values:\n"); for (i = 0; i < CPUID_MAX; i++) { - DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]); + DBG("\t%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]); } DBG("\n"); - DBG("Brand String: %s\n", p->CPU.BrandString); // Processor name (BIOS) - DBG("Vendor: 0x%X\n", p->CPU.Vendor); // Vendor ex: GenuineIntel - DBG("Family: 0x%X\n", p->CPU.Family); // Family ex: 6 (06h) - DBG("ExtFamily: 0x%X\n", p->CPU.ExtFamily); - DBG("Signature: 0x%08X\n", p->CPU.Signature); // CPUID signature + DBG("\tBrand String: %s\n", p->CPU.BrandString); // Processor name (BIOS) + DBG("\tVendor: 0x%X\n", p->CPU.Vendor); // Vendor ex: GenuineIntel + DBG("\tFamily: 0x%X\n", p->CPU.Family); // Family ex: 6 (06h) + DBG("\tExtFamily: 0x%X\n", p->CPU.ExtFamily); + DBG("\tSignature: 0x%08X\n", p->CPU.Signature); // CPUID signature /*switch (p->CPU.Type) { case PT_OEM: - DBG("Processor type: Intel Original OEM Processor\n"); + DBG("\tProcessor type: Intel Original OEM Processor\n"); break; case PT_OD: - DBG("Processor type: Intel Over Drive Processor\n"); + DBG("\tProcessor type: Intel Over Drive Processor\n"); break; case PT_DUAL: - DBG("Processor type: Intel Dual Processor\n"); + DBG("\tProcessor type: Intel Dual Processor\n"); break; case PT_RES: - DBG("Processor type: Intel Reserved\n"); + DBG("\tProcessor type: Intel Reserved\n"); break; default: break; }*/ - DBG("Model: 0x%X\n", p->CPU.Model); // Model ex: 37 (025h) - DBG("ExtModel: 0x%X\n", p->CPU.ExtModel); - DBG("Stepping: 0x%X\n", p->CPU.Stepping); // Stepping ex: 5 (05h) - DBG("MaxCoef: %d\n", p->CPU.MaxCoef); - DBG("CurrCoef: %d\n", p->CPU.CurrCoef); - DBG("MaxDiv: %d\n", p->CPU.MaxDiv); - DBG("CurrDiv: %d\n", p->CPU.CurrDiv); - DBG("TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000); - DBG("FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000); - DBG("CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000); - DBG("Cores: %d\n", p->CPU.NoCores); // Cores - DBG("Logical processor: %d\n", p->CPU.NoThreads); // Logical procesor - DBG("Features: 0x%08x\n", p->CPU.Features); + DBG("\tModel: 0x%X\n", p->CPU.Model); // Model ex: 37 (025h) + DBG("\tExtModel: 0x%X\n", p->CPU.ExtModel); + DBG("\tStepping: 0x%X\n", p->CPU.Stepping); // Stepping ex: 5 (05h) + DBG("\tMaxCoef: %d\n", p->CPU.MaxCoef); + DBG("\tCurrCoef: %d\n", p->CPU.CurrCoef); + DBG("\tMaxDiv: %d\n", p->CPU.MaxDiv); + DBG("\tCurrDiv: %d\n", p->CPU.CurrDiv); + DBG("\tTSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000); + DBG("\tFSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000); + DBG("\tCPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000); + DBG("\tCores: %d\n", p->CPU.NoCores); // Cores + DBG("\tLogical processor: %d\n", p->CPU.NoThreads); // Logical procesor + DBG("\tFeatures: 0x%08x\n", p->CPU.Features); - DBG("\n---------------------------------------------\n"); + verbose("\n"); #if DEBUG_CPU pause(); #endif Index: branches/zenith432/i386/libsaio/platform.h =================================================================== --- branches/zenith432/i386/libsaio/platform.h (revision 2804) +++ branches/zenith432/i386/libsaio/platform.h (revision 2805) @@ -23,8 +23,11 @@ #define CPUID_6 6 #define CPUID_80 7 #define CPUID_81 8 -#define CPUID_88 9 -#define CPUID_MAX 10 +#define CPUID_85 9 +#define CPUID_86 10 +#define CPUID_87 11 +#define CPUID_88 12 +#define CPUID_MAX 13 #define CPUID_MODEL_ANY 0x00 #define CPUID_MODEL_UNKNOWN 0x01 @@ -35,41 +38,47 @@ #define CPUID_MODEL_DOTHAN 0x0D // Dothan Pentium M, Celeron M (90nm) #define CPUID_MODEL_YONAH 0x0E // Sossaman, Yonah #define CPUID_MODEL_MEROM 0x0F // Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom -#define CPUID_MODEL_CONROE 0x0F // -#define CPUID_MODEL_CELERON 0x16 // Merom, Conroe (65nm), Celeron (45nm) +#define CPUID_MODEL_CONROE 0x16 // Merom, Conroe (65nm), Celeron (45nm) #define CPUID_MODEL_PENRYN 0x17 // Wolfdale, Yorkfield, Harpertown, Penryn #define CPUID_MODEL_WOLFDALE 0x17 // Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx #define CPUID_MODEL_NEHALEM 0x1A // Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown #define CPUID_MODEL_ATOM 0x1C // Pineview, Bonnell #define CPUID_MODEL_XEON_MP 0x1D // MP 7400 -#define CPUID_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper Forest -#define CPUID_MODEL_DALES 0x1F // Havendale, Auburndale -#define CPUID_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale +#define CPUID_MODEL_FIELDS 0x1E // Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest +#define CPUID_MODEL_CLARKDALE 0x1F // Core i7 and i5 Processor - Nehalem (Havendale, Auburndale) +#define CPUID_MODEL_DALES 0x25 // Westmere Client - Clarkdale, Arrandale #define CPUID_MODEL_ATOM_SAN 0x26 // Lincroft -#define CPUID_MODEL_LINCROFT 0x27 // Bonnell +#define CPUID_MODEL_LINCROFT 0x27 // Bonnell, penwell #define CPUID_MODEL_SANDYBRIDGE 0x2A // Sandy Bridge #define CPUID_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS #define CPUID_MODEL_JAKETOWN 0x2D // Sandy Bridge-E, Sandy Bridge-EP -#define CPUID_MODEL_NEHALEM_EX 0x2E // Beckton -#define CPUID_MODEL_WESTMERE_EX 0x2F // Westmere-EX -//#define CPUID_MODEL_BONNELL_ATOM 0x35 // Atom Family Bonnell +#define CPUID_MODEL_NEHALEM_EX 0x2E // Nehalem-EX Xeon - Beckton +#define CPUID_MODEL_WESTMERE_EX 0x2F // Westmere-EX Xeon - Eagleton +#define CPUID_MODEL_CLOVERVIEW 0x35 // Atom Family Bonnell, cloverview #define CPUID_MODEL_ATOM_2000 0x36 // Cedarview / Saltwell -#define CPUID_MODEL_SILVERMONT 0x37 // Atom E3000, Z3000 Atom Silvermont +#define CPUID_MODEL_ATOM_3700 0x37 // Atom E3000, Z3000 Atom Silvermont **BYT #define CPUID_MODEL_IVYBRIDGE 0x3A // Ivy Bridge -#define CPUID_MODEL_HASWELL 0x3C // Haswell DT -#define CPUID_MODEL_BROADWELL 0x3D // Core M, Broadwell / Core-AVX2 +#define CPUID_MODEL_HASWELL 0x3C // Haswell DT ex.i7 4790K +#define CPUID_MODEL_HASWELL_U5 0x3D // Haswell U5 5th generation Broadwell, Core M / Core-AVX2 #define CPUID_MODEL_IVYBRIDGE_XEON 0x3E // Ivy Bridge Xeon -#define CPUID_MODEL_HASWELL_SVR 0x3F // Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E) +#define CPUID_MODEL_HASWELL_SVR 0x3F // Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E) **HSX //#define CPUID_MODEL_HASWELL_H 0x?? // Haswell H -#define CPUID_MODEL_HASWELL_ULT 0x45 // Haswell ULT, 4th gen Core, Xeon E3-12xx v3 -#define CPUID_MODEL_CRYSTALWELL 0x46 // Crystal Well, 4th gen Core, Xeon E3-12xx v3 -//#define CPUID_MODEL_ 0x4A // Future Atom E3000, Z3000 silvermont / atom -#define CPUID_MODEL_AVOTON 0x4D // Silvermont/Avoton Atom C2000 -//#define CPUID_MODEL_ 0x4E // Future Core -#define CPUID_MODEL_BRODWELL_SVR 0x4F // Broadwell Server -#define CPUID_MODEL_BRODWELL_MSVR 0x56 // Broadwell Micro Server, Future Xeon -//#define CPUID_MODEL_ 0x5A // Silvermont, Future Atom E3000, Z3000 -//#define CPUID_MODEL_ 0x5D // Silvermont, Future Atom E3000, Z3000 +#define CPUID_MODEL_HASWELL_ULT 0x45 // Haswell ULT, 4th gen Core, Xeon E3-12xx v3 C8/C9/C10 +#define CPUID_MODEL_HASWELL_ULX 0x46 // Crystal Well, 4th gen Core, Xeon E3-12xx v3 +#define CPUID_MODEL_BROADWELL_HQ 0x47 // Broadwell BDW +#define CPUID_MODEL_MERRIFIELD 0x4A // Future Atom E3000, Z3000 silvermont / atom (Marrifield) +#define CPUID_MODEL_BRASWELL 0x4C // Atom (Braswell) +#define CPUID_MODEL_AVOTON 0x4D // Silvermont/Avoton Atom C2000 **AVN +#define CPUID_MODEL_SKYLAKE 0x4E // Future Core **SKL +#define CPUID_MODEL_BRODWELL_SVR 0x4F // Broadwell Server **BDX +#define CPUID_MODEL_SKYLAKE_AVX 0x55 // Skylake with AVX-512 support. +#define CPUID_MODEL_BRODWELL_MSVR 0x56 // Broadwell Micro Server, Future Xeon **BDX-DE +//#define CPUID_MODEL_KNIGHT 0x57 +#define CPUID_MODEL_ANNIDALE 0x5A // Silvermont, Future Atom E3000, Z3000 (Annidale) +//#define CPUID_MODEL_GOLDMONT 0x5C +#define CPUID_MODEL_VALLEYVIEW 0x5D // Silvermont, Future Atom E3000, Z3000 +#define CPUID_MODEL_SKYLAKE_S 0x5E // Skylake **SKL +//#define CPUID_MODEL_CANNONLAKE 0x66 /* CPUID Vendor */ #define CPUID_VID_INTEL "GenuineIntel" @@ -77,8 +86,17 @@ #define CPUID_VENDOR_INTEL 0x756E6547 #define CPUID_VENDOR_AMD 0x68747541 + +/* This spells out "GenuineIntel". */ +//#define is_intel \ +// ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69 + +/* This spells out "AuthenticAMD". */ +//#define is_amd \ +// ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65 + /* Unknown CPU */ -#define CPU_STRING_UNKNOWN "Unknown CPU Type" +#define CPU_STRING_UNKNOWN "Unknown CPU Typ" //definitions from Apple XNU @@ -185,7 +203,6 @@ #define CPUID_EXTFEATURE_EM64T bit(29) /* Extended Mem 64 Technology */ - #define CPUID_EXTFEATURE_LAHF hbit(0) /* LAFH/SAHF instructions */ /* @@ -213,6 +230,7 @@ #define MSR_IA32_BIOS_SIGN_ID 0x008B /* microcode version */ #define MSR_FSB_FREQ 0x00CD /* limited use - not for i7 */ #define MSR_PLATFORM_INFO 0x00CE /* limited use - MinRatio for i7 but Max for Yonah */ + /* turbo for penryn */ #define MSR_PKG_CST_CONFIG_CONTROL 0x00E2 // sandy and ivy #define MSR_PMG_IO_CAPTURE_BASE 0x00E4 @@ -235,6 +253,15 @@ #define IA32_PLATFORM_DCA_CAP 0x01F8 #define MSR_POWER_CTL 0x01FC // MSR 000001FC 0000-0000-0004-005F +// Nehalem (NHM) adds support for additional MSRs +#define MSR_SMI_COUNT 0x034 +#define MSR_NHM_PLATFORM_INFO 0x0ce +#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x0e2 +#define MSR_PKG_C3_RESIDENCY 0x3f8 +#define MSR_PKG_C6_RESIDENCY 0x3f9 +#define MSR_CORE_C3_RESIDENCY 0x3fc +#define MSR_CORE_C6_RESIDENCY 0x3fd + // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's. #define MSR_RAPL_POWER_UNIT 0x606 // R/O //MSR 00000606 0000-0000-000A-1003 @@ -245,6 +272,10 @@ //Valid + 010=1024ns + 0x54=84mks #define MSR_PKGC7_IRTL 0x60C // RW time limit to go C7 //MSR 0000060C 0000-0000-0000-8854 + +// Sandy Bridge (SNB) adds support for additional MSRs +#define MSR_PKG_C7_RESIDENCY 0x3FA +#define MSR_CORE_C7_RESIDENCY 0x3FE #define MSR_PKG_C2_RESIDENCY 0x60D // same as TSC but in C2 only #define MSR_PKG_RAPL_POWER_LIMIT 0x610 //MSR 00000610 0000-A580-0000-8960 @@ -259,8 +290,7 @@ // Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown). #define MSR_PP1_POWER_LIMIT 0x640 -#define MSR_PP1_ENERGY_STATUS 0x641 -//MSR 00000641 0000-0000-0000-0000 +#define MSR_PP1_ENERGY_STATUS 0x641 #define MSR_PP1_POLICY 0x642 // JakeTown only Memory MSR's. @@ -270,14 +300,39 @@ #define MSR_DRAM_PERF_STATUS 0x61B #define MSR_DRAM_POWER_INFO 0x61C -//IVY_BRIDGE +// Ivy Bridge #define MSR_CONFIG_TDP_NOMINAL 0x648 #define MSR_CONFIG_TDP_LEVEL1 0x649 #define MSR_CONFIG_TDP_LEVEL2 0x64A #define MSR_CONFIG_TDP_CONTROL 0x64B // write once to lock #define MSR_TURBO_ACTIVATION_RATIO 0x64C -//AMD +// Haswell (HSW) adds support for additional MSRs +#define MSR_PKG_C8_RESIDENCY 0x630 +#define MSR_PKG_C9_RESIDENCY 0x631 +#define MSR_PKG_C10_RESIDENCY 0x632 + +// Skylake (SKL) adds support for additional MSRs +#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x658 +#define MSR_PKG_ANY_CORE_C0_RES 0x659 +#define MSR_PKG_ANY_GFXE_C0_RES 0x65A +#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x65B + +/* AMD Defined MSRs */ +#define MSR_K6_EFER 0xC0000080 // extended feature register +#define MSR_K6_STAR 0xC0000081 // legacy mode SYSCALL target +#define MSR_K6_WHCR 0xC0000082 // long mode SYSCALL target +#define MSR_K6_UWCCR 0xC0000085 +#define MSR_K6_EPMR 0xC0000086 +#define MSR_K6_PSOR 0xC0000087 +#define MSR_K6_PFIR 0xC0000088 + +#define MSR_K7_EVNTSEL0 0xC0010000 +#define MSR_K7_PERFCTR0 0xC0010004 +#define MSR_K7_HWCR 0xC0010015 +#define MSR_K7_CLK_CTL 0xC001001b +#define MSR_K7_FID_VID_CTL 0xC0010041 + #define K8_FIDVID_STATUS 0xC0010042 #define K10_COFVID_LIMIT 0xC0010061 // max enabled p-state (msr >> 4) & 7 #define K10_COFVID_CONTROL 0xC0010062 // switch to p-state @@ -371,8 +426,8 @@ uint32_t LogicalPerPackage; uint32_t Signature; // Processor Signature uint32_t Stepping; // Stepping - //uint16_t Type; // Type uint32_t Model; // Model + //uint32_t Type; // Processor Type uint32_t ExtModel; // Extended Model uint32_t Family; // Family uint32_t ExtFamily; // Extended Family @@ -392,29 +447,31 @@ } CPU; - struct RAM { + struct DMI + { + int MaxMemorySlots; // number of memory slots populated by SMBIOS + int CntMemorySlots; // number of memory slots counted + int MemoryModules; // number of memory modules installed + int DIMM[MAX_RAM_SLOTS]; // Information and SPD mapping for each slot + } DMI; + + struct RAM + { uint64_t Frequency; // Ram Frequency uint32_t Divider; // Memory divider uint8_t CAS; // CAS 1/2/2.5/3/4/5/6/7 - uint8_t TRC; + uint8_t TRC; uint8_t TRP; uint8_t RAS; - uint8_t Channels; // Channel Configuration Single,Dual or Triple + uint8_t Channels; // Channel Configuration Single,Dual, Triple or Quad uint8_t NoSlots; // Maximum no of slots available uint8_t Type; // Standard SMBIOS v2.5 Memory Type RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot } RAM; - struct DMI { - int MaxMemorySlots; // number of memory slots populated by SMBIOS - int CntMemorySlots; // number of memory slots counted - int MemoryModules; // number of memory modules installed - int DIMM[MAX_RAM_SLOTS]; // Information and SPD mapping for each slot - } DMI; - uint8_t Type; // system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile) uint8_t *UUID; // system-id (SMBIOS Table 1: system uuid) -// uint32_t HWSignature; // machine-signature (FACS: Hardware Signature) + uint32_t HWSignature; // machine-signature (FACS: Hardware Signature) } PlatformInfo_t; extern PlatformInfo_t Platform; Index: branches/zenith432/i386/libsaio/disk.c =================================================================== --- branches/zenith432/i386/libsaio/disk.c (revision 2804) +++ branches/zenith432/i386/libsaio/disk.c (revision 2805) @@ -103,12 +103,12 @@ //========================================================================== // Maps (E)BIOS return codes to message strings. - struct NamedValue { unsigned char value; const char *name; }; +// ========================================================================= /* * Map a disk drive to bootable volumes contained within. */ @@ -126,8 +126,8 @@ * biosbuf points to a sector within the track cache, and is * updated by Biosread(). */ -static char * const trackbuf = (char *) ptov(BIOS_ADDR); -static char * biosbuf; +static char *const trackbuf = (char *) ptov(BIOS_ADDR); +static char *biosbuf; static struct DiskBVMap *gDiskBVMap = NULL; static struct disk_blk0 *gBootSector = NULL; @@ -141,6 +141,7 @@ static bool getOSVersion(BVRef bvr, char *str); static bool cache_valid = false; +// ============================================================================= static const struct NamedValue bios_errors[] = { { 0x10, "Media error" }, @@ -152,6 +153,7 @@ { 0x00, NULL } }; +// ============================================================================= static const struct NamedValue fdiskTypes[] = { { FDISK_DOS12, "DOS_FAT_12" }, // 0x01 @@ -180,11 +182,9 @@ }; //============================================================================== - extern void spinActivityIndicator(int sectors); -//========================================================================== - +//============================================================================== static int getDriveInfo( int biosdev, struct driveInfo *dip ) { static struct driveInfo cached_di; @@ -231,10 +231,8 @@ return 0; } -//========================================================================== - -static const char *getNameForValue( const struct NamedValue *nameTable, - unsigned char value ) +//============================================================================== +static const char *getNameForValue( const struct NamedValue *nameTable, unsigned char value ) { const struct NamedValue *np; @@ -250,8 +248,7 @@ } //============================================================================== - -static const char * bios_error(int errnum) +static const char *bios_error(int errnum) { static char errorstr[] = "Error 0x00"; const char * errname; @@ -328,7 +325,7 @@ { if (rc == ECC_CORRECTED_ERR) { - rc = 0; /* Ignore corrected ECC errors */ + rc = 0; // Ignore corrected ECC errors break; } @@ -368,9 +365,10 @@ { if (rc == ECC_CORRECTED_ERR) { - rc = 0; /* Ignore corrected ECC errors */ + rc = 0; // Ignore corrected ECC errors break; } + error(" BIOS read error: %s\n", bios_error(rc), rc); error(" Block %d, Cyl %d Head %d Sector %d\n", secno, cyl, head, sec); sleep(1); @@ -393,15 +391,13 @@ } //============================================================================== - int testBiosread(int biosdev, unsigned long long secno) { return Biosread(biosdev, secno); } //============================================================================== - -static int readBytes(int biosdev, unsigned long long blkno, unsigned int byteoff, unsigned int byteCount, void * buffer) +static int readBytes(int biosdev, unsigned long long blkno, unsigned int byteoff, unsigned int byteCount, void *buffer) { // ramdisks require completely different code for reading. if(p_ramdiskReadBytes != NULL && biosdev >= 0x100) @@ -438,7 +434,6 @@ } //============================================================================== - static int isExtendedFDiskPartition( const struct fdisk_part *part ) { static unsigned char extParts[] = @@ -461,7 +456,6 @@ } //============================================================================== - static int getNextFDiskPartition( int biosdev, int *partno, const struct fdisk_part **outPart ) { static int sBiosdev = -1; @@ -552,7 +546,6 @@ } //============================================================================== - /* * Trying to figure out the filsystem type of a given partition. * X = fdisk partition type @@ -569,6 +562,7 @@ const void *probeBuffer = malloc(PROBEFS_SIZE); if (probeBuffer == NULL) { + verbose("\t[probeFileSystem] Error: can't alloc memory for probe buffer.\n"); goto exit; } @@ -577,6 +571,7 @@ if (error) { + verbose("\t[probeFileSystem] Error: can't read from device=%02Xh.\n", biosdev); goto exit; } @@ -644,7 +639,6 @@ } //============================================================================== - static BVRef newFDiskBVRef( int biosdev, int partno, unsigned int blkoff, @@ -841,7 +835,7 @@ //EFI_GUID const GPT_RAID_OFFLINE_GUID = { 0x52414944, 0x5f4f, 0x11AA, { 0xAA, 0x11, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC } }; // 0xAF02 "Apple RAID offline" //EFI_GUID const GPT_LABEL_GUID = { 0x4C616265, 0x6C00, 0x11AA, { 0xAA, 0x11, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC } }; // 0xAF03 "Apple label" //EFI_GUID const GPT_APPLETV_GUID = { 0x5265636F, 0x7665, 0x11AA, { 0xAA, 0x11, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC } }; // 0xAF04 "Apple TV recovery" -//EFI_GUID const GPT_CORESTORAGE_GUID = { 0x53746F72, 0x6167, 0x11AA, { 0xAA, 0x11, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC } }; // 0xAF05 "Apple Core storage" +EFI_GUID const GPT_CORESTORAGE_GUID = { 0x53746F72, 0x6167, 0x11AA, { 0xAA, 0x11, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC } }; // 0xAF05 "Apple Core storage" // same as Apple ZFS //EFI_GUID const GPT_ZFS_GUID = { 0x6A898CC3, 0x1DD2, 0x11B2, { 0x99, 0xA6, 0x08, 0x00, 0x20, 0x73, 0x66, 0x31 } }; // 0xBF01 "Solaris /usr & Apple ZFS @@ -942,7 +936,6 @@ * So, for example, if you have two primary partitions and * one extended partition they will be numbered 1, 2, 5. */ - static BVRef diskScanFDiskBootVolumes( int biosdev, int *countPtr ) { const struct fdisk_part *part; @@ -956,6 +949,8 @@ struct driveInfo di; boot_drive_info_t *dp; + verbose("\tAttempting to scan FDISK boot volumes [biosdev=%02Xh]:\n", biosdev); + /* Initialize disk info */ if (getDriveInfo(biosdev, &di) != 0) @@ -1249,13 +1244,15 @@ } //============================================================================== - -static BVRef diskScanAPMBootVolumes( int biosdev, int * countPtr ) +static BVRef diskScanAPMBootVolumes( int biosdev, int *countPtr ) { struct DiskBVMap *map; struct Block0 *block0_p; unsigned int blksize; unsigned int factor; + + verbose("\tAttempting to scan APM boot volumes [biosdev=%02Xh]:\n", biosdev); + void *buffer = malloc(BPS); if (!buffer) @@ -1370,7 +1367,6 @@ } //============================================================================== - static bool isPartitionUsed(gpt_ent * partition) { @@ -1380,9 +1376,10 @@ } //============================================================================== - -static BVRef diskScanGPTBootVolumes(int biosdev, int * countPtr) +static BVRef diskScanGPTBootVolumes(int biosdev, int *countPtr) { + verbose("\tAttempting to scan GPT boot volumes [biosdev=%02Xh]:\n", biosdev); + struct DiskBVMap *map = NULL; void *buffer = malloc(BPS); @@ -1413,6 +1410,7 @@ // means the FDISK code will wind up parsing it. if ( fdiskID ) { + verbose("\t[diskScanGPTBootVolumes] Error! Two GPT protective MBR (fdisk=0xEE) partitions found on same device, skipping.\n"); goto scanErr; } @@ -1472,7 +1470,7 @@ UInt32 gptCheck = 0; UInt32 gptCount = 0; UInt32 gptID = 0; - gpt_ent *gptMap = 0; + gpt_ent *gptMap = NULL; UInt32 gptSize = 0; gptBlock = OSSwapLittleToHostInt64(headerMap->hdr_lba_table); @@ -1699,10 +1697,9 @@ } //============================================================================== - static bool getOSVersion(BVRef bvr, char *str) { - bool valid = false; + bool valid = false; config_file_t systemVersion; char dirSpec[512]; @@ -1774,7 +1771,7 @@ } } -// Mountain Lion ? +// if ( MOUNTAIN_LION ){} if ( MAVERICKS ) { @@ -1794,8 +1791,10 @@ } } -// Yosemite ? +// if ( YOSEMITE ){} +// if ( ELCAPITAN ){} + } if (valid) @@ -1803,8 +1802,13 @@ const char *val; int len; + // ProductVersion if (getValueForKey(kProductVersion, &val, &len, &systemVersion)) { + // Copy the complete value into OSFullVer + strncpy( bvr->OSFullVer, val, len ); + bvr->OSFullVer[len] = '\0'; /* null character manually added */ + // getValueForKey uses const char for val // so copy it and trim *str = '\0'; @@ -1824,7 +1828,6 @@ } //============================================================================== - static void scanFSLevelBVRSettings(BVRef chain) { BVRef bvr; @@ -1876,7 +1879,7 @@ } } - // Check for SystemVersion.plist or ServerVersion.plist to determine if a volume hosts an installed system. + // Check for SystemVersion.plist or ServerVersion.plist or com.apple.boot.plist to determine if a volume hosts an installed system. if (bvr->flags & kBVFlagNativeBoot) { @@ -1890,7 +1893,6 @@ } //============================================================================== - void rescanBIOSDevice(int biosdev) { struct DiskBVMap *oldMap = diskResetBootVolumes(biosdev); @@ -1906,7 +1908,6 @@ } //============================================================================== - struct DiskBVMap* diskResetBootVolumes(int biosdev) { struct DiskBVMap * map; @@ -1940,7 +1941,6 @@ } //============================================================================== - // Frees a DiskBVMap and all of its BootVolume's void diskFreeMap(struct DiskBVMap *map) { @@ -1958,8 +1958,7 @@ } //============================================================================== - -BVRef diskScanBootVolumes(int biosdev, int * countPtr) +BVRef diskScanBootVolumes(int biosdev, int *countPtr) { struct DiskBVMap *map; BVRef bvr; @@ -2008,7 +2007,6 @@ } //============================================================================== - BVRef getBVChainForBIOSDev(int biosdev) { BVRef chain = NULL; @@ -2027,7 +2025,6 @@ } //============================================================================== - BVRef newFilteredBVChain(int minBIOSDev, int maxBIOSDev, unsigned int allowFlags, unsigned int denyFlags, int *count) { BVRef chain = NULL; @@ -2153,7 +2150,6 @@ } //============================================================================== - int freeFilteredBVChain(const BVRef chain) { int ret = 1; @@ -2186,8 +2182,7 @@ } //============================================================================== - -bool matchVolumeToString( BVRef bvr, const char* match, long matchLen) +bool matchVolumeToString( BVRef bvr, const char *match, long matchLen) { char testStr[128]; @@ -2231,13 +2226,11 @@ } //============================================================================== - /* If Rename Partition has defined an alias, then extract it for description purpose. * The format for the rename string is the following: * hd(x,y)|uuid|"label" "alias";hd(m,n)|uuid|"label" "alias"; etc... */ - -static bool getVolumeLabelAlias(BVRef bvr, char* str, long strMaxLen) +static bool getVolumeLabelAlias(BVRef bvr, char *str, long strMaxLen) { char *aliasList, *entryStart, *entryNext; @@ -2291,7 +2284,6 @@ } //============================================================================== - void getBootVolumeDescription( BVRef bvr, char *str, long strMaxLen, bool useDeviceDescription ) { unsigned char type; @@ -2364,9 +2356,7 @@ strncpy(bvr->label, p, sizeof bvr->label); } - //============================================================================== - int readBootSector(int biosdev, unsigned int secno, void *buffer) { int error; @@ -2397,11 +2387,9 @@ } //============================================================================== - /* * Format of boot1f32 block. */ - #define BOOT1F32_MAGIC "BOOT " #define BOOT1F32_MAGICLEN 11 @@ -2442,27 +2430,22 @@ return 0; } - //============================================================================== // Handle seek request from filesystem modules. - void diskSeek(BVRef bvr, long long position) { bvr->fs_boff = position / BPS; bvr->fs_byteoff = position % BPS; } - //============================================================================== // Handle read request from filesystem modules. - int diskRead(BVRef bvr, long addr, long length) { return readBytes(bvr->biosdev, bvr->fs_boff + bvr->part_boff, bvr->fs_byteoff, length, (void *) addr); } //============================================================================== - int rawDiskRead( BVRef bvr, unsigned int secno, void *buffer, unsigned int len ) { int secs; @@ -2510,7 +2493,6 @@ } //============================================================================== - int rawDiskWrite( BVRef bvr, unsigned int secno, void *buffer, unsigned int len ) { int secs; @@ -2555,7 +2537,6 @@ } //============================================================================== - int diskIsCDROM(BVRef bvr) { struct driveInfo di; @@ -2568,7 +2549,6 @@ } //============================================================================== - int biosDevIsCDROM(int biosdev) { struct driveInfo di; Index: branches/zenith432/i386/libsaio/pci_setup.c =================================================================== --- branches/zenith432/i386/libsaio/pci_setup.c (revision 2804) +++ branches/zenith432/i386/libsaio/pci_setup.c (revision 2805) @@ -5,20 +5,22 @@ #include "modules.h" #ifndef DEBUG_PCI_SETUP -#define DEBUG_PCI_SETUP 0 + #define DEBUG_PCI_SETUP 0 #endif #if DEBUG_PCI_SETUP -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) + #define DBG(x...) #endif extern bool setup_ati_devprop(pci_dt_t *ati_dev); extern bool setup_nvidia_devprop(pci_dt_t *nvda_dev); extern bool setup_gma_devprop(pci_dt_t *gma_dev); extern bool setup_hda_devprop(pci_dt_t *hda_dev); -extern void set_eth_builtin(pci_dt_t *eth_dev); +extern void setup_eth_devdrop(pci_dt_t *eth_dev); +extern void setup_wifi_devdrop(pci_dt_t *wifi_dev); + extern void notify_usb_dev(pci_dt_t *pci_dev); extern void force_enable_hpet(pci_dt_t *lpc_dev); @@ -27,14 +29,29 @@ void setup_pci_devs(pci_dt_t *pci_dt) { char *devicepath; - bool doit, do_eth_devprop, do_gfx_devprop, do_enable_hpet, do_hda_devprop; + + bool do_gfx_devprop = false; + bool do_skip_n_devprop = false; + bool do_skip_a_devprop = false; + bool do_skip_i_devprop = false; + + bool do_enable_hpet = false; + bool do_hda_devprop = false; + pci_dt_t *current = pci_dt; - do_eth_devprop = do_gfx_devprop = do_enable_hpet = do_hda_devprop = false; + // GraphicsEnabler + getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->chameleonConfig); - getBoolForKey(kEthernetBuiltIn, &do_eth_devprop, &bootInfo->chameleonConfig); - getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->chameleonConfig); + // Skip keys + getBoolForKey(kSkipNvidiaGfx, &do_skip_n_devprop, &bootInfo->chameleonConfig); + getBoolForKey(kSkipAtiGfx, &do_skip_a_devprop, &bootInfo->chameleonConfig); + getBoolForKey(kSkipIntelGfx, &do_skip_i_devprop, &bootInfo->chameleonConfig); + + // HDAEnable getBoolForKey(kHDAEnabler, &do_hda_devprop, &bootInfo->chameleonConfig); + + // ForceHPET getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->chameleonConfig); while (current) @@ -53,12 +70,18 @@ case PCI_CLASS_NETWORK_ETHERNET: DBG("Setup ETHERNET %s enabled\n", do_eth_devprop? "is":"is not"); - if (do_eth_devprop) - { - set_eth_builtin(current); - } + verbose("[ ETHERNET DEVICE INFO ]\n"); + setup_eth_devdrop(current); + verbose("\n"); break; // PCI_CLASS_NETWORK_ETHERNET + case PCI_CLASS_NETWORK_OTHER: + DBG("Setup WIRELESS %s enabled\n", do_wifi_devprop? "is":"is not"); + verbose("[ WIRELESS DEVICE INFO ]\n"); + setup_wifi_devdrop(current); + verbose("\n"); + break; // PCI_CLASS_NETWORK_OTHER + case PCI_CLASS_DISPLAY_VGA: DBG("GraphicsEnabler %s enabled\n", do_gfx_devprop? "is":"is not"); if (do_gfx_devprop) @@ -66,35 +89,41 @@ switch (current->vendor_id) { case PCI_VENDOR_ID_ATI: - if (getBoolForKey(kSkipAtiGfx, &doit, &bootInfo->chameleonConfig) && doit) + if ( do_skip_a_devprop ) { verbose("Skip ATi/AMD gfx device!\n"); } else { + verbose("[ ATi GFX DEVICE INFO ]\n"); setup_ati_devprop(current); + verbose("\n"); } break; // PCI_VENDOR_ID_ATI case PCI_VENDOR_ID_INTEL: - if (getBoolForKey(kSkipIntelGfx, &doit, &bootInfo->chameleonConfig) && doit) + if ( do_skip_i_devprop ) { verbose("Skip Intel gfx device!\n"); } else { + verbose("[ INTEL GMA DEVICE INFO ]\n"); setup_gma_devprop(current); + verbose("\n"); } break; // PCI_VENDOR_ID_INTEL case PCI_VENDOR_ID_NVIDIA: - if (getBoolForKey(kSkipNvidiaGfx, &doit, &bootInfo->chameleonConfig) && doit) + if ( do_skip_n_devprop ) { verbose("Skip Nvidia gfx device!\n"); } else { + verbose("[ NVIDIA GFX DEVICE INFO ]\n"); setup_nvidia_devprop(current); + verbose("\n"); } break; // PCI_VENDOR_ID_NVIDIA @@ -105,10 +134,12 @@ break; // PCI_CLASS_DISPLAY_VGA case PCI_CLASS_MULTIMEDIA_AUDIO_DEV: - DBG("Setup HDEF %s enabled\n", do_hda_devprop? "is":"is not"); + DBG("Setup HDEF %s enabled\n", do_hda_devprop ? "is":"is not"); if (do_hda_devprop) { + verbose("[ AUDIO DEVICE INFO ]\n"); setup_hda_devprop(current); + verbose("\n"); } break; // PCI_CLASS_MULTIMEDIA_AUDIO_DEV @@ -117,11 +148,24 @@ notify_usb_dev(current); break; // PCI_CLASS_SERIAL_USB + case PCI_CLASS_SERIAL_FIREWIRE: + DBG("FireWire\n"); + verbose("[ FIREWIRE DEVICE INFO ]\n"); + verbose("\tClass code: [%04X]\n\tFireWire device [%04x:%04x]-[%04x:%04x]\n\t%s\n", + current->class_id,current->vendor_id, current->device_id, + current->subsys_id.subsys.vendor_id, + current->subsys_id.subsys.device_id, devicepath); +// set_fwr_devdrop(current); + verbose("\n"); + break; // PCI_CLASS_SERIAL_FIREWIRE + case PCI_CLASS_BRIDGE_ISA: - DBG("Force HPET %s enabled\n", do_enable_hpet? "is":"is not"); + DBG("Force HPET %s enabled\n", do_enable_hpet ? "is":"is not"); if (do_enable_hpet) { + verbose("[ HPET ]\n"); force_enable_hpet(current); + verbose("\n"); } break; // PCI_CLASS_BRIDGE_ISA Index: branches/zenith432/i386/libsaio/cpu.h =================================================================== --- branches/zenith432/i386/libsaio/cpu.h (revision 2804) +++ branches/zenith432/i386/libsaio/cpu.h (revision 2805) @@ -10,10 +10,130 @@ extern void scan_cpu(PlatformInfo_t *); +struct clock_frequency_info_t +{ + unsigned long bus_clock_rate_hz; + unsigned long cpu_clock_rate_hz; + unsigned long dec_clock_rate_hz; + unsigned long bus_clock_rate_num; + unsigned long bus_clock_rate_den; + unsigned long bus_to_cpu_rate_num; + unsigned long bus_to_cpu_rate_den; + unsigned long bus_to_dec_rate_num; + unsigned long bus_to_dec_rate_den; + unsigned long timebase_frequency_hz; + unsigned long timebase_frequency_num; + unsigned long timebase_frequency_den; + unsigned long long bus_frequency_hz; + unsigned long long bus_frequency_min_hz; + unsigned long long bus_frequency_max_hz; + unsigned long long cpu_frequency_hz; + unsigned long long cpu_frequency_min_hz; + unsigned long long cpu_frequency_max_hz; + unsigned long long prf_frequency_hz; + unsigned long long prf_frequency_min_hz; + unsigned long long prf_frequency_max_hz; + unsigned long long mem_frequency_hz; + unsigned long long mem_frequency_min_hz; + unsigned long long mem_frequency_max_hz; + unsigned long long fix_frequency_hz; +}; + +typedef struct clock_frequency_info_t clock_frequency_info_t; + +extern clock_frequency_info_t gPEClockFrequencyInfo; + + +struct mach_timebase_info +{ + uint32_t numer; + uint32_t denom; +}; + +struct hslock +{ + int lock_data; +}; +typedef struct hslock hw_lock_data_t, *hw_lock_t; + +#define hw_lock_addr(hwl) (&((hwl).lock_data)) + +typedef struct uslock_debug +{ + void *lock_pc; /* pc where lock operation began */ + void *lock_thread; /* thread that acquired lock */ + unsigned long duration[2]; + unsigned short state; + unsigned char lock_cpu; + void *unlock_thread; /* last thread to release lock */ + unsigned char unlock_cpu; + void *unlock_pc; /* pc where lock operation ended */ +} uslock_debug; + +typedef struct slock +{ + hw_lock_data_t interlock; /* must be first... see lock.c */ + unsigned short lock_type; /* must be second... see lock.c */ +#define USLOCK_TAG 0x5353 + uslock_debug debug; +} usimple_lock_data_t, *usimple_lock_t; + +#if !defined(decl_simple_lock_data) +typedef usimple_lock_data_t *simple_lock_t; +typedef usimple_lock_data_t simple_lock_data_t; + +#define decl_simple_lock_data(class,name) \ +class simple_lock_data_t name; +#endif /* !defined(decl_simple_lock_data) */ + +typedef struct mach_timebase_info *mach_timebase_info_t; +typedef struct mach_timebase_info mach_timebase_info_data_t; + // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM #define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ #define CALIBRATE_LATCH ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) +#define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 +#define AMD_ACTONCMPHALT_SHIFT 27 +#define AMD_ACTONCMPHALT_MASK 3 + +/* + * Control register 0 + */ + +typedef struct _cr0 { + unsigned int pe :1, + mp :1, + em :1, + ts :1, + :1, + ne :1, + :10, + wp :1, + :1, + am :1, + :10, + nw :1, + cd :1, + pg :1; +} cr0_t; + +/* + * Debugging register 6 + */ + +typedef struct _dr6 { + unsigned int b0 :1, + b1 :1, + b2 :1, + b3 :1, + :9, + bd :1, + bs :1, + bt :1, + :16; +} dr6_t; + static inline uint64_t rdtsc64(void) { uint64_t ret; @@ -164,7 +284,6 @@ : : "d"(value) : "%al"); } - inline static uint64_t get_PIT2(unsigned int *value) { @@ -205,4 +324,27 @@ return result; } +/* + * Timing Functions + */ + +/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ +static inline void CpuPause(void) +{ + __asm__ volatile ("rep; nop"); +} + +static inline uint32_t DivU64x32(uint64_t dividend, uint32_t divisor) +{ + __asm__ volatile ("divl %1" : "+A"(dividend) : "r"(divisor)); + return (uint32_t) dividend; +} + +static inline uint64_t MultU32x32(uint32_t multiplicand, uint32_t multiplier) +{ + uint64_t result; + __asm__ volatile ("mull %2" : "=A"(result) : "a"(multiplicand), "r"(multiplier)); + return result; +} + #endif /* !__LIBSAIO_CPU_H */ Index: branches/zenith432/i386/libsaio/smbios.c =================================================================== --- branches/zenith432/i386/libsaio/smbios.c (revision 2804) +++ branches/zenith432/i386/libsaio/smbios.c (revision 2805) @@ -368,9 +368,10 @@ {kSMBTypeMemoryDevice, kSMBString, getFieldOffset(SMBMemoryDevice, partNumber), kSMBMemoryDevicePartNumberKey, getSMBMemoryDevicePartNumber, NULL}, - //------------------------------------------------------------------------------------------------------------------------- - // Apple Specific - //------------------------------------------------------------------------------------------------------------------------- + /* ============ + Apple Specific + ============== */ + // OEM Processor Type (Apple Specific - Type 131) {kSMBTypeOemProcessorType, kSMBWord, getFieldOffset(SMBOemProcessorType, ProcessorType), kSMBOemProcessorTypeKey, getSMBOemProcessorType, NULL}, @@ -562,7 +563,7 @@ //=========== MacPro =========== #define kDefaultMacProFamily "MacPro" // MacPro's family = "MacPro" not "Mac Pro" //#define KDefauktMacProBoardAssetTagNumber "Pro-Enclosure" -//#define kDefaultMacProBoardType "0xB" // 11 +//#define kDefaultMacProBoardType "0x0B" // 11 #define kDefaultMacPro "MacPro3,1" #define kDefaultMacProBIOSVersion " MP31.88Z.006C.B05.0903051113" @@ -696,8 +697,8 @@ switch (Platform.CPU.Model) { case CPUID_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) - case CPUID_MODEL_DALES: - case CPUID_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPUID_MODEL_CLARKDALE: + case CPUID_MODEL_DALES: // Intel Core i3, i5 LGA1156 (32nm) defaultBIOSInfo.version = kDefaultiMacNehalemBIOSVersion; defaultBIOSInfo.releaseDate = kDefaultiMacNehalemBIOSReleaseDate; defaultSystemInfo.productName = kDefaultiMacNehalem; @@ -1042,8 +1043,8 @@ { case 0x19: // Intel Core i5 650 @3.20 Ghz case CPUID_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) - case CPUID_MODEL_DALES: - case CPUID_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPUID_MODEL_CLARKDALE: + case CPUID_MODEL_DALES: // Intel Core i3, i5 LGA1156 (32nm) case CPUID_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) case CPUID_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x case CPUID_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core @@ -1055,7 +1056,7 @@ case CPUID_MODEL_HASWELL: case CPUID_MODEL_HASWELL_SVR: case CPUID_MODEL_HASWELL_ULT: - case CPUID_MODEL_CRYSTALWELL: + case CPUID_MODEL_HASWELL_ULX: break; @@ -1096,9 +1097,10 @@ } */ -//------------------------------------------------------------------------------------------------------------------------- -// EndOfTable -//------------------------------------------------------------------------------------------------------------------------- + +/* ============================================== + EndOfTable + ================================================ */ void addSMBEndOfTable(SMBStructPtrs *structPtr) { structPtr->new->type = kSMBTypeEndOfTable; @@ -1238,6 +1240,7 @@ case kSMBTypeMemorySPD: case kSMBTypeOemProcessorType: case kSMBTypeOemProcessorBusSpeed: +// case kSMBTypeOemPlatformFeature: /* And this one too, to be added at the end */ case kSMBTypeEndOfTable: break; @@ -1265,7 +1268,7 @@ addSMBMemorySPD(structPtr); addSMBOemProcessorType(structPtr); addSMBOemProcessorBusSpeed(structPtr); - +// addSMBOemPlatformFeature(structPtr); addSMBEndOfTable(structPtr); } @@ -1274,10 +1277,11 @@ { uint8_t *ptr = (uint8_t *)neweps->dmi.tableAddress; SMBStructHeader *structHeader = (SMBStructHeader *)ptr; + uint8_t *ret = NULL; int i, isZero, isOnes; uint8_t fixedUUID[UUID_LEN] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF}; const char *sysId = getStringForKey(kSMBSystemInformationUUIDKey, SMBPlist); // try to get user's uuid from smbios.plist - uint8_t *ret = (uint8_t *)getUUIDFromString(sysId); // convert user's uuid from string + ret = (uint8_t *)getUUIDFromString(sysId); // convert user's uuid from string for (;(structHeader->type != kSMBTypeSystemInformation);) // find System Information Table (Type 1) in patched SMBIOS { Index: branches/zenith432/i386/libsaio/disk.h =================================================================== --- branches/zenith432/i386/libsaio/disk.h (revision 2804) +++ branches/zenith432/i386/libsaio/disk.h (revision 2805) @@ -9,6 +9,6 @@ #ifndef __LIBSAIO_DISK_H #define __LIBSAIO_DISK_H -bool matchVolumeToString( BVRef bvr, const char* match, long strMaxLen); +bool matchVolumeToString( BVRef bvr, const char *match, long strMaxLen); -#endif /* __LIBSAIO_DISK_H */ \ No newline at end of file +#endif /* __LIBSAIO_DISK_H */ Index: branches/zenith432/i386/libsaio/smbios_decode.c =================================================================== --- branches/zenith432/i386/libsaio/smbios_decode.c (revision 2804) +++ branches/zenith432/i386/libsaio/smbios_decode.c (revision 2805) @@ -659,7 +659,7 @@ decodeOemProcessorBusSpeed(structHeader); break; - //kSMBTypeOemPlatformFeature: // Type 133 + //case kSMBTypeOemPlatformFeature: // Type 133 // decodeOemPlatformFeature(structHeader); // break; Index: branches/zenith432/i386/libsaio/hpet.c =================================================================== --- branches/zenith432/i386/libsaio/hpet.c (revision 2804) +++ branches/zenith432/i386/libsaio/hpet.c (revision 2805) @@ -1,37 +1,154 @@ /* - * + * Copyright (c) 2009 Evan Lojewski. All rights reserved. */ +/* + * High Precision Event Timer (HPET) + */ + #include "libsaio.h" #include "pci.h" #include "hpet.h" #ifndef DEBUG_HPET -#define DEBUG_HPET 0 + #define DEBUG_HPET 0 #endif #if DEBUG_HPET -#define DBG(x...) printf(x) + #define DBG(x...) printf(x) #else -#define DBG(x...) + #define DBG(x...) #endif -static struct lpc_controller_t lpc_controllers[] = { +void force_enable_hpet_intel(pci_dt_t *lpc_dev); +void force_enable_hpet_nvidia(pci_dt_t *lpc_dev); +void force_enable_hpet_via(pci_dt_t *lpc_dev); +/* + * Force HPET enabled + * + * VIA fix from http://forum.voodooprojects.org/index.php/topic,1596.0.html + */ + +static struct lpc_controller_t lpc_controllers_intel[] = { + // Default unknown chipset { 0, 0, "" }, // Intel - { 0x8086, 0x24dc, "ICH5" }, - { 0x8086, 0x2640, "ICH6" }, - { 0x8086, 0x2641, "ICH6M" }, + { 0x8086, 0x0f1c, "Bay Trail SoC" }, - { 0x8086, 0x27b0, "ICH7 DH" }, - { 0x8086, 0x27b8, "ICH7" }, - { 0x8086, 0x27b9, "ICH7M" }, - { 0x8086, 0x27bd, "ICH7M DH" }, + { 0x8086, 0x1c41, "Cougar Point" }, + { 0x8086, 0x1c42, "Cougar Point Desktop" }, + { 0x8086, 0x1c43, "Cougar Point Mobile" }, + { 0x8086, 0x1c44, "Cougar Point" }, + { 0x8086, 0x1c45, "Cougar Point" }, + { 0x8086, 0x1c46, "Cougar Point" }, + { 0x8086, 0x1c47, "Cougar Point" }, + { 0x8086, 0x1c48, "Cougar Point" }, + { 0x8086, 0x1c49, "Cougar Point" }, + { 0x8086, 0x1c4a, "Cougar Point" }, + { 0x8086, 0x1c4b, "Cougar Point" }, + { 0x8086, 0x1c4c, "Cougar Point" }, + { 0x8086, 0x1c4d, "Cougar Point" }, + { 0x8086, 0x1c4e, "Cougar Point" }, + { 0x8086, 0x1c4f, "Cougar Point" }, + { 0x8086, 0x1c50, "Cougar Point" }, + { 0x8086, 0x1c51, "Cougar Point" }, + { 0x8086, 0x1c52, "Cougar Point" }, + { 0x8086, 0x1c53, "Cougar Point" }, + { 0x8086, 0x1c54, "Cougar Point" }, + { 0x8086, 0x1c55, "Cougar Point" }, + { 0x8086, 0x1c56, "Cougar Point" }, + { 0x8086, 0x1c57, "Cougar Point" }, + { 0x8086, 0x1c58, "Cougar Point" }, + { 0x8086, 0x1c59, "Cougar Point" }, + { 0x8086, 0x1c5a, "Cougar Point" }, + { 0x8086, 0x1c5b, "Cougar Point" }, + { 0x8086, 0x1c5c, "Cougar Point" }, + { 0x8086, 0x1c5d, "Cougar Point" }, + { 0x8086, 0x1c5e, "Cougar Point" }, + { 0x8086, 0x1c5f, "Cougar Point" }, + { 0x8086, 0x1d40, "Patsburg" }, + { 0x8086, 0x1d41, "Patsburg" }, + { 0x8086, 0x1e40, "Panther Point" }, + { 0x8086, 0x1e41, "Panther Point" }, + { 0x8086, 0x1e42, "Panther Point" }, + { 0x8086, 0x1e43, "Panther Point" }, + { 0x8086, 0x1e44, "Panther Point" }, + { 0x8086, 0x1e45, "Panther Point" }, + { 0x8086, 0x1e46, "Panther Point" }, + { 0x8086, 0x1e47, "Panther Point" }, + { 0x8086, 0x1e48, "Panther Point" }, + { 0x8086, 0x1e49, "Panther Point" }, + { 0x8086, 0x1e4a, "Panther Point" }, + { 0x8086, 0x1e4b, "Panther Point" }, + { 0x8086, 0x1e4c, "Panther Point" }, + { 0x8086, 0x1e4d, "Panther Point" }, + { 0x8086, 0x1e4e, "Panther Point" }, + { 0x8086, 0x1e4f, "Panther Point" }, + { 0x8086, 0x1e50, "Panther Point" }, + { 0x8086, 0x1e51, "Panther Point" }, + { 0x8086, 0x1e52, "Panther Point" }, + { 0x8086, 0x1e53, "Panther Point" }, + { 0x8086, 0x1e54, "Panther Point" }, + { 0x8086, 0x1e55, "Panther Point" }, + { 0x8086, 0x1e56, "Panther Point" }, + { 0x8086, 0x1e57, "Panther Point" }, + { 0x8086, 0x1e58, "Panther Point" }, + { 0x8086, 0x1e59, "Panther Point" }, + { 0x8086, 0x1e5a, "Panther Point" }, + { 0x8086, 0x1e5b, "Panther Point" }, + { 0x8086, 0x1e5c, "Panther Point" }, + { 0x8086, 0x1e5d, "Panther Point" }, + { 0x8086, 0x1e5e, "Panther Point" }, + { 0x8086, 0x1e5f, "Panther Point" }, + { 0x8086, 0x1f38, "Avoton SoC" }, + { 0x8086, 0x1f39, "Avoton SoC" }, + { 0x8086, 0x1f3a, "Avoton SoC" }, + { 0x8086, 0x1f3b, "Avoton SoC" }, - { 0x8086, 0x2810, "ICH8R" }, + { 0x8086, 0x229c, "Braswell SoC" }, + { 0x8086, 0x2390, "Coleto Creek" }, + { 0x8086, 0x2310, "DH89xxCC" }, + { 0x8086, 0x2410, "ICH" }, + { 0x8086, 0x2420, "ICH0" }, + { 0x8086, 0x2440, "ICH2" }, + { 0x8086, 0x244c, "ICH2-M" }, + { 0x8086, 0x2480, "ICH3-S" }, + { 0x8086, 0x248c, "ICH3-M" }, + { 0x8086, 0x24c0, "ICH4" }, + { 0x8086, 0x24cc, "ICH4-M" }, + { 0x8086, 0x2450, "C-ICH" }, + { 0x8086, 0x24d0, "ICH5/ICH5R" }, + { 0x8086, 0x25a1, "6300ESB" }, + { 0x8086, 0x2640, "ICH6/ICH6R" }, + { 0x8086, 0x2641, "ICH6-M" }, + { 0x8086, 0x2642, "ICH6W/ICH6RW" }, + { 0x8086, 0x2670, "631xESB/632xESB" }, + { 0x8086, 0x2671, "631xESB/632xESB" }, + { 0x8086, 0x2672, "631xESB/632xESB" }, + { 0x8086, 0x2673, "631xESB/632xESB" }, + { 0x8086, 0x2674, "631xESB/632xESB" }, + { 0x8086, 0x2675, "631xESB/632xESB" }, + { 0x8086, 0x2676, "631xESB/632xESB" }, + { 0x8086, 0x2677, "631xESB/632xESB" }, + { 0x8086, 0x2678, "631xESB/632xESB" }, + { 0x8086, 0x2679, "631xESB/632xESB" }, + { 0x8086, 0x267a, "631xESB/632xESB" }, + { 0x8086, 0x267b, "631xESB/632xESB" }, + { 0x8086, 0x267c, "631xESB/632xESB" }, + { 0x8086, 0x267d, "631xESB/632xESB" }, + { 0x8086, 0x267e, "631xESB/632xESB" }, + { 0x8086, 0x267f, "631xESB/632xESB" }, + { 0x8086, 0x27b0, "ICH7DH" }, + { 0x8086, 0x27b8, "ICH7/ICH7R" }, + { 0x8086, 0x27b9, "ICH7-M/ICH7-U" }, + { 0x8086, 0x27bc, "NM10" }, + { 0x8086, 0x27bd, "ICH7-M DH" }, + + + { 0x8086, 0x2810, "ICH8/ICH8R" }, { 0x8086, 0x2811, "ICH8M-E" }, { 0x8086, 0x2812, "ICH8DH" }, { 0x8086, 0x2814, "ICH8DO" }, @@ -48,28 +165,256 @@ { 0x8086, 0x3a16, "ICH10R" }, { 0x8086, 0x3a18, "ICH10" }, { 0x8086, 0x3a1a, "ICH10D" }, + { 0x8086, 0x3b00, "PCH Desktop Full Featured" }, + { 0x8086, 0x3b01, "PCH Mobile Full Featured" }, + { 0x8086, 0x3b02, "P55" }, + { 0x8086, 0x3b03, "PM55" }, + { 0x8086, 0x3b06, "H55" }, + { 0x8086, 0x3b07, "QM57" }, + { 0x8086, 0x3b08, "H57" }, + { 0x8086, 0x3b09, "HM55" }, + { 0x8086, 0x3b0a, "Q57" }, + { 0x8086, 0x3b0b, "HM57" }, + { 0x8086, 0x3b0d, "PCH Mobile SFF Full Featured" }, + { 0x8086, 0x3b0f, "QS57" }, + { 0x8086, 0x3b12, "3400" }, + { 0x8086, 0x3b14, "3420" }, + { 0x8086, 0x3b16, "3450" }, + { 0x8086, 0x5031, "EP80579" }, + + { 0x8086, 0x8c40, "Lynx Point" }, + { 0x8086, 0x8c41, "Lynx Point" }, + { 0x8086, 0x8c42, "Lynx Point" }, + { 0x8086, 0x8c43, "Lynx Point" }, + { 0x8086, 0x8c44, "Lynx Point" }, + { 0x8086, 0x8c45, "Lynx Point" }, + { 0x8086, 0x8c46, "Lynx Point" }, + { 0x8086, 0x8c47, "Lynx Point" }, + { 0x8086, 0x8c48, "Lynx Point" }, + { 0x8086, 0x8c49, "Lynx Point" }, + { 0x8086, 0x8c4a, "Lynx Point" }, + { 0x8086, 0x8c4b, "Lynx Point" }, + { 0x8086, 0x8c4c, "Lynx Point" }, + { 0x8086, 0x8c4d, "Lynx Point" }, + { 0x8086, 0x8c4e, "Lynx Point" }, + { 0x8086, 0x8c4f, "Lynx Point" }, + { 0x8086, 0x8c50, "Lynx Point" }, + { 0x8086, 0x8c51, "Lynx Point" }, + { 0x8086, 0x8c52, "Lynx Point" }, + { 0x8086, 0x8c53, "Lynx Point" }, + { 0x8086, 0x8c54, "Lynx Point" }, + { 0x8086, 0x8c55, "Lynx Point" }, + { 0x8086, 0x8c56, "Lynx Point" }, + { 0x8086, 0x8c57, "Lynx Point" }, + { 0x8086, 0x8c58, "Lynx Point" }, + { 0x8086, 0x8c59, "Lynx Point" }, + { 0x8086, 0x8c5a, "Lynx Point" }, + { 0x8086, 0x8c5b, "Lynx Point" }, + { 0x8086, 0x8c5c, "Lynx Point" }, + { 0x8086, 0x8c5d, "Lynx Point" }, + { 0x8086, 0x8c5e, "Lynx Point" }, + { 0x8086, 0x8c5f, "Lynx Point" }, + { 0x8086, 0x8cc1, "9 Series" }, + { 0x8086, 0x8cc2, "9 Series" }, + { 0x8086, 0x8cc3, "9 Series" }, + { 0x8086, 0x8cc4, "9 Series" }, + { 0x8086, 0x8cc6, "9 Series" }, + { 0x8086, 0x8d40, "Wellsburg" }, + { 0x8086, 0x8d41, "Wellsburg" }, + { 0x8086, 0x8d42, "Wellsburg" }, + { 0x8086, 0x8d43, "Wellsburg" }, + { 0x8086, 0x8d44, "Wellsburg" }, + { 0x8086, 0x8d45, "Wellsburg" }, + { 0x8086, 0x8d46, "Wellsburg" }, + { 0x8086, 0x8d47, "Wellsburg" }, + { 0x8086, 0x8d48, "Wellsburg" }, + { 0x8086, 0x8d49, "Wellsburg" }, + { 0x8086, 0x8d4a, "Wellsburg" }, + { 0x8086, 0x8d4b, "Wellsburg" }, + { 0x8086, 0x8d4c, "Wellsburg" }, + { 0x8086, 0x8d4d, "Wellsburg" }, + { 0x8086, 0x8d4e, "Wellsburg" }, + { 0x8086, 0x8d4f, "Wellsburg" }, + { 0x8086, 0x8d50, "Wellsburg" }, + { 0x8086, 0x8d51, "Wellsburg" }, + { 0x8086, 0x8d52, "Wellsburg" }, + { 0x8086, 0x8d53, "Wellsburg" }, + { 0x8086, 0x8d54, "Wellsburg" }, + { 0x8086, 0x8d55, "Wellsburg" }, + { 0x8086, 0x8d56, "Wellsburg" }, + { 0x8086, 0x8d57, "Wellsburg" }, + { 0x8086, 0x8d58, "Wellsburg" }, + { 0x8086, 0x8d59, "Wellsburg" }, + { 0x8086, 0x8d5a, "Wellsburg" }, + { 0x8086, 0x8d5b, "Wellsburg" }, + { 0x8086, 0x8d5c, "Wellsburg" }, + { 0x8086, 0x8d5d, "Wellsburg" }, + { 0x8086, 0x8d5e, "Wellsburg" }, + { 0x8086, 0x8d5f, "Wellsburg" }, + + { 0x8086, 0x9c40, "Lynx Point_LP" }, + { 0x8086, 0x9c41, "Lynx Point_LP" }, + { 0x8086, 0x9c42, "Lynx Point_LP" }, + { 0x8086, 0x9c43, "Lynx Point_LP" }, + { 0x8086, 0x9c44, "Lynx Point_LP" }, + { 0x8086, 0x9c45, "Lynx Point_LP" }, + { 0x8086, 0x9c46, "Lynx Point_LP" }, + { 0x8086, 0x9c47, "Lynx Point_LP" }, + { 0x8086, 0x9cc1, "Wildcat Point_LP" }, + { 0x8086, 0x9cc2, "Wildcat Point_LP" }, + { 0x8086, 0x9cc3, "Wildcat Point_LP" }, + { 0x8086, 0x9cc5, "Wildcat Point_LP" }, + { 0x8086, 0x9cc6, "Wildcat Point_LP" }, + { 0x8086, 0x9cc7, "Wildcat Point_LP" }, + { 0x8086, 0x9cc9, "Wildcat Point_LP" }, + }; -void force_enable_hpet(pci_dt_t *lpc_dev) +static struct lpc_controller_t lpc_controllers_nvidia[] = { + + // Default unknown chipset + { 0, 0, "" }, + + // nVidia + { 0x10de, 0x0aac, "MCP79" }, + { 0x10de, 0x0aae, "MCP79" }, + { 0x10de, 0x0aaf, "MCP79" }, + { 0x10de, 0x0d80, "MCP89" }, + { 0x10de, 0x0d81, "MCP89" }, + { 0x10de, 0x0d82, "MCP89" }, + { 0x10de, 0x0d83, "MCP89" }, + +}; + +static struct lpc_controller_t lpc_controllers_via[] = { + // Default unknown chipset + { 0, 0, "" }, + { 0x1106, 0x3050, "VT82C596A" }, + { 0x1106, 0x3051, "VT82C596B" }, + { 0x1106, 0x8235, "VT8231" }, + { 0x1106, 0x3074, "VT8233" }, + { 0x1106, 0x3147, "VT8233A" }, + { 0x1106, 0x3177, "VT8235" }, + { 0x1106, 0x3227, "VT8237R" }, + { 0x1106, 0x3337, "VT8237A" }, + { 0x1106, 0x3372, "VT8237S" }, + { 0x1106, 0x3287, "VT8251" }, + { 0x1106, 0x8324, "CX700" }, + { 0x1106, 0x8353, "VX800/VX820" }, + { 0x1106, 0x8409, "VX855/VX875" }, +}; + +/* ErmaC add lpc for nVidia */ +void force_enable_hpet_nvidia(pci_dt_t *lpc_dev) { + uint32_t val, hpet_address = 0xFED00000; int i; + void *rcba; + + for(i = 1; i < sizeof(lpc_controllers_nvidia) / sizeof(lpc_controllers_nvidia[0]); i++) + { + if ((lpc_controllers_nvidia[i].vendor == lpc_dev->vendor_id) && (lpc_controllers_nvidia[i].device == lpc_dev->device_id)) + { + + rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000); + + DBG("\tnVidia(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", + lpc_controllers_nvidia[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba); + + if (rcba == 0) + { + printf("\tRCBA disabled; cannot force enable HPET\n"); + } + else + { + val = REG32(rcba, 0x3404); + if (val & 0x80) + { + // HPET is enabled in HPTC. Just not reported by BIOS + DBG("\tHPET is enabled in HPTC, just not reported by BIOS\n"); + hpet_address |= (val & 3) << 12 ; + DBG("\tHPET MMIO @ 0x%lx\n", hpet_address); + } + else + { + // HPET disabled in HPTC. Trying to enable + DBG("\tHPET is disabled in HPTC, trying to enable\n"); + REG32(rcba, 0x3404) = val | 0x80; + hpet_address |= (val & 3) << 12 ; + DBG("\tForce enabled HPET, MMIO @ 0x%lx\n", hpet_address); + } + + // verify if the job is done + val = REG32(rcba, 0x3404); + if (!(val & 0x80)) + { + printf("\tFailed to force enable HPET\n"); + } + } + break; + } + } +} + +void force_enable_hpet_via(pci_dt_t *lpc_dev) +{ uint32_t val, hpet_address = 0xFED00000; + int i; + + for(i = 1; i < sizeof(lpc_controllers_via) / sizeof(lpc_controllers_via[0]); i++) + { + if ((lpc_controllers_via[i].vendor == lpc_dev->vendor_id) && (lpc_controllers_via[i].device == lpc_dev->device_id)) + { + val = pci_config_read32(lpc_dev->dev.addr, 0x68); + + DBG("\tVIA %s LPC Interface [%04x:%04x], MMIO\n", + lpc_controllers_via[i].name, lpc_dev->vendor_id, lpc_dev->device_id); + + if (val & 0x80) + { + hpet_address = (val & ~0x3ff); + DBG("HPET at 0x%lx\n", hpet_address); + } + else + { + val = 0xfed00000 | 0x80; + pci_config_write32(lpc_dev->dev.addr, 0x68, val); + val = pci_config_read32(lpc_dev->dev.addr, 0x68); + if (val & 0x80) + { + hpet_address = (val & ~0x3ff); + DBG("\tForce enabled HPET at 0x%lx\n", hpet_address); + } + else + { + DBG("\tUnable to enable HPET"); + } + } + } + } +} + +void force_enable_hpet_intel(pci_dt_t *lpc_dev) +{ + uint32_t val, hpet_address = 0xFED00000; + int i; void *rcba; /* LPC on Intel ICH is always (?) at 00:1f.0 */ - for(i = 1; i < sizeof(lpc_controllers) / sizeof(lpc_controllers[0]); i++) - if ((lpc_controllers[i].vendor == lpc_dev->vendor_id) - && (lpc_controllers[i].device == lpc_dev->device_id)) + for(i = 1; i < sizeof(lpc_controllers_intel) / sizeof(lpc_controllers_intel[0]); i++) + { + if ((lpc_controllers_intel[i].vendor == lpc_dev->vendor_id) && (lpc_controllers_intel[i].device == lpc_dev->device_id)) { + rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000); - DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", - lpc_controllers[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba); + DBG("\tIntel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", + lpc_controllers_intel[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba); if (rcba == 0) { - printf(" RCBA disabled; cannot force enable HPET\n"); + printf("\tRCBA disabled; cannot force enable HPET\n"); } else { @@ -77,31 +422,51 @@ if (val & 0x80) { // HPET is enabled in HPTC. Just not reported by BIOS - DBG(" HPET is enabled in HPTC, just not reported by BIOS\n"); + DBG("\tHPET is enabled in HPTC, just not reported by BIOS\n"); hpet_address |= (val & 3) << 12 ; - DBG(" HPET MMIO @ 0x%lx\n", hpet_address); + DBG("\tHPET MMIO @ 0x%lx\n", hpet_address); } else { // HPET disabled in HPTC. Trying to enable - DBG(" HPET is disabled in HPTC, trying to enable\n"); + DBG("\tHPET is disabled in HPTC, trying to enable\n"); REG32(rcba, 0x3404) = val | 0x80; hpet_address |= (val & 3) << 12 ; - DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address); + DBG("\tForce enabled HPET, MMIO @ 0x%lx\n", hpet_address); } // verify if the job is done val = REG32(rcba, 0x3404); if (!(val & 0x80)) { - printf(" Failed to force enable HPET\n"); + printf("\tFailed to force enable HPET\n"); } } break; } + } +} +void force_enable_hpet(pci_dt_t *lpc_dev) +{ + switch(lpc_dev->vendor_id) + { + case 0x8086: + force_enable_hpet_intel(lpc_dev); + break; + + case 0x10de: + force_enable_hpet_nvidia(lpc_dev); + break; + + case 0x1106: + force_enable_hpet_via(lpc_dev); + break; + } + #if DEBUG_HPET printf("Press [Enter] to continue...\n"); getchar(); #endif + } Index: branches/zenith432/i386/libsaio/smbios.h =================================================================== --- branches/zenith432/i386/libsaio/smbios.h (revision 2804) +++ branches/zenith432/i386/libsaio/smbios.h (revision 2805) @@ -849,10 +849,6 @@ //---------------------------------------------------------------------------------------------------------- -/* From Foundation/Efi/Guid/Smbios/SmBios.h */ -/* Modified to wrap Data4 array init with {} */ -#define EFI_SMBIOS_TABLE_GUID {0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} - #define SMBIOS_ORIGINAL 0 #define SMBIOS_PATCHED 1 Index: branches/zenith432/i386/libsaio/nvidia_helper.c =================================================================== --- branches/zenith432/i386/libsaio/nvidia_helper.c (revision 2804) +++ branches/zenith432/i386/libsaio/nvidia_helper.c (revision 2805) @@ -48,7 +48,7 @@ . . . - + */ Index: branches/zenith432/i386/libsaio/nvidia_helper.h =================================================================== --- branches/zenith432/i386/libsaio/nvidia_helper.h (revision 2804) +++ branches/zenith432/i386/libsaio/nvidia_helper.h (revision 2805) @@ -9,15 +9,15 @@ typedef struct cardList_t { - char* model; - uint32_t id; - uint32_t subid; - uint64_t videoRam; - struct cardList_t* next; + char *model; + uint32_t id; + uint32_t subid; + uint64_t videoRam; + struct cardList_t *next; } cardList_t; -void add_card(char* model, uint32_t id, uint32_t subid, uint64_t videoRam); +void add_card(char *model, uint32_t id, uint32_t subid, uint64_t videoRam); void fill_card_list(void); -cardList_t* FindCardWithIds(uint32_t id, uint32_t subid); +cardList_t *FindCardWithIds(uint32_t id, uint32_t subid); -#endif //__LIBSAIO_NVIDIA_HELPER_H \ No newline at end of file +#endif //__LIBSAIO_NVIDIA_HELPER_H Index: branches/zenith432/i386/libsaio/stringTable.c =================================================================== --- branches/zenith432/i386/libsaio/stringTable.c (revision 2804) +++ branches/zenith432/i386/libsaio/stringTable.c (revision 2805) @@ -41,8 +41,7 @@ /* * Compare a string to a key with quoted characters */ -static inline int -keyncmp(const char *str, const char *key, int n) +static inline int keyncmp(const char *str, const char *key, int n) { int c; while (n--) { @@ -90,9 +89,7 @@ } /* Remove key and its associated value from the table. */ - -bool -removeKeyFromTable(const char *key, char *table) +bool removeKeyFromTable(const char *key, char *table) { register int len; register char *tab; @@ -102,7 +99,7 @@ tab = (char *)table; buf = (char *)malloc(len + 3); - sprintf(buf, "\"%s\"", key); + snprintf(buf, len + 3,"\"%s\"", key); len = strlen(buf); while(*tab) { @@ -156,6 +153,10 @@ } bufsize = end - begin + 1; newstr = malloc(bufsize); + if (!newstr) + { + return 0; + } strlcpy(newstr, begin, bufsize); *list = end; *size = newsize; @@ -175,8 +176,11 @@ if (*table == '\\') { table += 2; ret += 1 + (compress ? 0 : 1); - } else { - if (*table == '\"') { + } + else + { + if (*table == '\"') + { return ret; } ret++; @@ -224,8 +228,13 @@ char *newstr, *p; int size; - if (getValueForConfigTableKey(config, key, &val, &size)) { + if (getValueForConfigTableKey(config, key, &val, &size)) + { newstr = (char *)malloc(size+1); + if (!newstr) + { + return 0; + } for (p = newstr; size; size--, p++, val++) { if ((*p = *val) == '\\') { switch (*++val) { @@ -254,8 +263,7 @@ #endif -char * -newStringForKey(char *key, config_file_t *config) +char *newStringForKey(char *key, config_file_t *config) { const char *val; char *newstr; @@ -263,6 +271,10 @@ if (getValueForKey(key, &val, &size, config) && size) { newstr = (char *)malloc(size + 1); + if (!newstr) + { + return 0; + } strlcpy(newstr, val, size + 1); return newstr; } else { @@ -275,7 +287,6 @@ * both