Index: branches/ErmaC/Enoch/i386/libsaio/cpu.c
===================================================================
--- branches/ErmaC/Enoch/i386/libsaio/cpu.c	(revision 2889)
+++ branches/ErmaC/Enoch/i386/libsaio/cpu.c	(revision 2890)
@@ -1112,6 +1112,7 @@
 				uint64_t cpuMult;
 				uint64_t divisor = 0;
 				uint64_t did;
+
 				uint64_t fid;
 
 				cofvid  = rdmsr64(K10_COFVID_STATUS);
@@ -1132,6 +1133,28 @@
 			}
 				break;
 
+			case 0x17: /*** Bronya: For AMD Family 17h Ryzen ***/
+			{
+				uint64_t cpuMult;
+				uint64_t CpuDfsId;
+				uint64_t CpuFid;
+
+				uint64_t prfsts = 0;
+
+				prfsts = rdmsr64(AMD_PSTATE0_STS);
+
+				CpuDfsId = bitfield(prfsts, 13, 8);
+				CpuFid = bitfield(prfsts, 7, 0);
+
+				cpuMult = (CpuFid  / CpuDfsId) * 2;
+
+				cpuMultN2 = (prfsts & (uint64_t)bit(0));
+				currdiv = cpuMultN2;
+
+				/****** Addon END ******/
+			}
+				break;
+
 			default:
 			{
 				typedef unsigned long long vlong;
Index: branches/ErmaC/Enoch/i386/libsaio/platform.h
===================================================================
--- branches/ErmaC/Enoch/i386/libsaio/platform.h	(revision 2889)
+++ branches/ErmaC/Enoch/i386/libsaio/platform.h	(revision 2890)
@@ -345,6 +345,7 @@
 
 #define MSR_AMD_MPERF			0x000000E7
 #define MSR_AMD_APERF			0x000000E8
+#define AMD_PSTATE0_STS			0xC0010064
 
 #define DEFAULT_FSB			100000          /* for now, hardcoding 100MHz for old CPUs */