Index: trunk/i386/libsaio/gma.c
===================================================================
--- trunk/i386/libsaio/gma.c	(revision 2898)
+++ trunk/i386/libsaio/gma.c	(revision 2899)
@@ -29,7 +29,7 @@
 	http://forum.voodooprojects.org/index.php/topic,1029.0.html
 
 	Original Intel HDx000 code from valv
-	Intel Ivy Bridge, Haswell and Broadwell code from ErmaC:
+	Intel Ivy Bridge, Haswell, Broadwell and Skylake code from ErmaC:
 	- http://www.insanelymac.com/forum/topic/288241-intel-hd4000-inject-aaplig-platform-id/
 */
 
Index: trunk/i386/libsaio/gfx_helper.c
===================================================================
--- trunk/i386/libsaio/gfx_helper.c	(revision 2898)
+++ trunk/i386/libsaio/gfx_helper.c	(revision 2899)
@@ -12,7 +12,7 @@
 
 /*
  
- NVIDIA card injection usage e.g (to be placed in the boot.plist): 
+ NVIDIA and ATI card injection usage e.g (to be placed in the boot.plist): 
  
  <key>NVIDIA</key>
 	<array>
@@ -49,7 +49,19 @@
  .
  .
 	</array>
- 
+
+ <key>ATI</key>
+	<array>
+		<dict>
+			<key>Chipset Name</key>
+			<string>ATI RADEON HD6670</string>
+			<key>IOPCIPrimaryMatch</key>
+			<string>0x10026758</string>
+			<key>VRam Size</key>
+			<string>2048</string>
+		</dict>
+	</array>
+
  */
 
 cardList_t *cardList = NULL;
@@ -109,6 +121,7 @@
 {
 	unsigned int	i, count;
 	TagPtr		NVDIATag;
+	TagPtr		ATITag;
 	char		*model_name = NULL;
 	char		*match_id = NULL;
 	char		*sub_id = NULL;
@@ -150,4 +163,39 @@
 			}
 		}
 	}
+
+	if ((ATITag = XMLCastArray(XMLGetProperty(bootInfo->chameleonConfig.dictionary, (const char *)"ATI"))))
+	{
+		count = XMLTagCount(ATITag);
+
+		for (i=0; i<count; i++)
+		{
+			TagPtr element = XMLGetElement( NVDIATag, i );
+			if (element)
+			{
+				match_id   = XMLCastString(XMLGetProperty(element, (const char*)"IOPCIPrimaryMatch")); //device-id
+				sub_id   = XMLCastString(XMLGetProperty(element, (const char*)"IOPCISubDevId")); //sub device-id
+				model_name  = XMLCastString(XMLGetProperty(element, (const char*)"Chipset Name"));
+				vram_size  = XMLCastString(XMLGetProperty(element, (const char*)"VRam Size"));
+
+				if (match_id)
+				{
+					dev_id = strtoul(match_id, NULL, 16);
+				}
+
+				if (sub_id)
+				{
+					subdev_id = strtoul(sub_id, NULL, 16);
+				}
+
+				if (vram_size)
+				{
+					VramSize = strtoul(vram_size, NULL, 10);
+				}
+
+				add_card(model_name, dev_id, subdev_id, VramSize);
+			}
+		}
+	}
+
 }
Index: trunk/i386/libsaio/cpu.c
===================================================================
--- trunk/i386/libsaio/cpu.c	(revision 2898)
+++ trunk/i386/libsaio/cpu.c	(revision 2899)
@@ -21,11 +21,30 @@
 
 clock_frequency_info_t gPEClockFrequencyInfo;
 
-static __unused uint64_t rdtsc32(void)
+//static __unused uint64_t rdtsc32(void)
+//{
+//	unsigned int lo,hi;
+//	__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
+//	return ((uint64_t)hi << 32) | lo;
+//}
+
+uint64_t getCycles(void)
 {
-	unsigned int lo,hi;
-	__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
-	return ((uint64_t)hi << 32) | lo;
+#if defined(__ARM_ARCH_7A__)
+    uint32_t r;
+    asm volatile("mrc p15, 0, %0, c9, c13, 0\t\n" : "=r" (r)); /* Read PMCCNTR       */
+    return ((uint64_t)r) << 6;                                 /* 1 tick = 64 clocks */
+#elif defined(__x86_64__)
+    unsigned a, d;
+    asm volatile("rdtsc" : "=a" (a), "=d" (d));
+    return ((uint64_t)a) | (((uint64_t)d) << 32);
+#elif defined(__i386__)
+    uint64_t ret;
+    asm volatile("rdtsc": "=A" (ret));
+    return ret;
+#else
+    return 0;
+#endif
 }
 
 /*
@@ -71,10 +90,10 @@
 	attempts++;
 	enable_PIT2();		// turn on PIT2
 	set_PIT2(0);		// reset timer 2 to be zero
-	latchTime = rdtsc32();	// get the time stamp to time
+	latchTime = getCycles();	// get the time stamp to time
 	latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes
 	set_PIT2(SAMPLE_CLKS_INT);	// set up the timer for (almost) 1/20th a second
-	saveTime = rdtsc32();	// now time how long a 20th a second is...
+	saveTime = getCycles();	// now time how long a 20th a second is...
 	get_PIT2(&lastValue);
 	get_PIT2(&lastValue);	// read twice, first value may be unreliable
 	do {
@@ -129,9 +148,9 @@
 	{
 		enable_PIT2();
 		set_PIT2_mode0(CALIBRATE_LATCH);
-		tscStart = rdtsc64();
+		tscStart = getCycles();
 		pollCount = poll_PIT2_gate();
-		tscEnd = rdtsc64();
+		tscEnd = getCycles();
 		/* The poll loop must have run at least a few times for accuracy */
 		if (pollCount <= 1)
 		{
@@ -330,18 +349,18 @@
 	 * Do the work
 	 */
 	offset = 0;
-	lastTsc = rdtsc64();
+	lastTsc = getCycles();
 	do
 	{
 		(void) memcpy((char*) dst + offset, (const char*) src + offset, chunk);
 		offset += (ptrdiff_t) chunk;
 		len -= chunk;
-		if ((rdtsc64() - lastTsc) < threshold)
+		if ((getCycles() - lastTsc) < threshold)
 		{
 			continue;
 		}
 		(void) readKeyboardStatus();	// visit real-mode
-		lastTsc = rdtsc64();
+		lastTsc = getCycles();
 	}
 	while (len > chunk);
 	if (len)
@@ -376,7 +395,6 @@
 	uint32_t	reg[4];
 	char		*s			= 0;
 
-
 	do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor
 	do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features
 	do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch
@@ -448,6 +466,7 @@
 			do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch
 			do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch
 			do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);
+			do_cpuid(0x8000001E, p->CPU.CPUID[CPUID_81E]);
 
 			break;
 
@@ -492,12 +511,12 @@
 
 	uint8_t		bus_ratio_max		= 0;
 	uint8_t		bus_ratio_min		= 0;
-	uint8_t		currdiv			= 0;
-	uint8_t		currcoef		= 0;
+	uint32_t	currdiv			= 0;
+	uint32_t	currcoef		= 0;
 	uint8_t		maxdiv			= 0;
 	uint8_t		maxcoef			= 0;
-	uint8_t		pic0_mask;
-	uint8_t		cpuMultN2		= 0;
+	uint8_t		pic0_mask		= 0;
+	uint32_t	cpuMultN2		= 0;
 
 	const char	*newratio;
 
@@ -685,9 +704,31 @@
 		case CPUID_VENDOR_AMD:
 		{
 			post_startup_cpu_fixups();
-			cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;
-			threads_per_core = cores_per_package;
 
+			if (p->CPU.ExtFamily < 0x8)
+			{
+				cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;
+				//threads_per_core = cores_per_package;
+			}
+			else
+
+			// Bronya : test for SMT
+			// Properly calculate number of cores on AMD Zen
+			// TODO: Check MSR for SMT
+			if (p->CPU.ExtFamily >= 0x8)
+			{
+				uint64_t cores = 0;
+				uint64_t logical = 0;
+
+				cores = bitfield(p->CPU.CPUID[CPUID_81E][ebx], 7, 0); // cores
+				logical = bitfield(p->CPU.CPUID[CPUID_81E][ebx], 15, 8) + 1; // 2
+
+				cores_per_package = (bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1) / logical; //8 cores
+
+				//threads_per_core = cores_per_package;
+
+			}
+
 			if (cores_per_package == 0)
 			{
 				cores_per_package = 1;
@@ -739,11 +780,6 @@
 		p->CPU.Features |= CPU_FEATURE_SSE42;
 	}
 
-	if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)
-	{
-		p->CPU.Features |= CPU_FEATURE_EM64T;
-	}
-
 	if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)
 	{
 		p->CPU.Features |= CPU_FEATURE_MSR;
@@ -754,6 +790,11 @@
 		p->CPU.Features |= CPU_FEATURE_HTT;
 	}
 
+	if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)
+	{
+		p->CPU.Features |= CPU_FEATURE_EM64T;
+	}
+
 	pic0_mask = inb(0x21U);
 	outb(0x21U, 0xFFU);     // mask PIC0 interrupts for duration of timing tests
 
@@ -799,11 +840,11 @@
 				case CPUID_MODEL_SKYLAKE_S:
 /* --------------------------------------------------------- */
 					msr = rdmsr64(MSR_PLATFORM_INFO);
-					DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));
+					DBG("msr(%d): platform_info %08llx\n", __LINE__, bitfield(msr, 31, 0));
 					bus_ratio_max = bitfield(msr, 15, 8);
 					bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)
 					msr = rdmsr64(MSR_FLEX_RATIO);
-					DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));
+					DBG("msr(%d): flex_ratio %08llx\n", __LINE__, bitfield(msr, 31, 0));
 					if (bitfield(msr, 16, 16))
 					{
 						flex_ratio = bitfield(msr, 15, 8);
@@ -820,7 +861,7 @@
 							// Clear bit 16 (evidently the presence bit)
 							wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));
 							msr = rdmsr64(MSR_FLEX_RATIO);
-							DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));
+							DBG("CPU: Unusable flex ratio detected. Patched MSR now %08llx\n", bitfield(msr, 31, 0));
 						}
 						else
 						{
@@ -891,7 +932,7 @@
 
 			default:
 				msr = rdmsr64(MSR_IA32_PERF_STATUS);
-				DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));
+				DBG("msr(%d): ia32_perf_stat 0x%08llx\n", __LINE__, bitfield(msr, 31, 0));
 				currcoef = bitfield(msr, 12, 8);  // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating
 				// Non-integer bus ratio for the max-multi
 				maxdiv = bitfield(msr, 46, 46);
@@ -956,12 +997,12 @@
 			{
 				uint64_t fidvid = 0;
 				uint64_t cpuMult;
-				uint64_t fid;
+				uint64_t cpuFid;
 
-				fidvid = rdmsr64(K8_FIDVID_STATUS);
-				fid = bitfield(fidvid, 5, 0);
+				fidvid = rdmsr64(AMD_K8_PERF_STS);
+				cpuFid = bitfield(fidvid, 5, 0);
 
-				cpuMult = (fid + 8) / 2;
+				cpuMult = (cpuFid + 0x8) * 10 / 2;
 				currcoef = cpuMult;
 
 				cpuMultN2 = (fidvid & (uint64_t)bit(0));
@@ -972,25 +1013,26 @@
 
 			case 0x10: /*** AMD Family 10h ***/
 			{
-				uint64_t cofvid = 0;
+
+				uint64_t prfsts = 0;
 				uint64_t cpuMult;
 				uint64_t divisor = 0;
-				uint64_t did;
-				uint64_t fid;
+				uint64_t cpuDid;
+				uint64_t cpuFid;
 
-				cofvid  = rdmsr64(K10_COFVID_STATUS);
-				did = bitfield(cofvid, 8, 6);
-				fid = bitfield(cofvid, 5, 0);
-				if (did == 0) divisor = 2;
-				else if (did == 1) divisor = 4;
-				else if (did == 2) divisor = 8;
-				else if (did == 3) divisor = 16;
-				else if (did == 4) divisor = 32;
+				prfsts  = rdmsr64(AMD_COFVID_STS);
+				cpuDid = bitfield(prfsts, 8, 6);
+				cpuFid = bitfield(prfsts, 5, 0);
+				if (cpuDid == 0) divisor = 2;
+				else if (cpuDid == 1) divisor = 4;
+				else if (cpuDid == 2) divisor = 8;
+				else if (cpuDid == 3) divisor = 16;
+				else if (cpuDid == 4) divisor = 32;
 
-				cpuMult = (fid + 16) / divisor;
+				cpuMult = ((cpuFid + 0x10) * 10) / (2^cpuDid);
 				currcoef = cpuMult;
 
-				cpuMultN2 = (cofvid & (uint64_t)bit(0));
+				cpuMultN2 = (prfsts & (uint64_t)bit(0));
 				currdiv = cpuMultN2;
 
 				/****** Addon END ******/
@@ -999,25 +1041,26 @@
 
 			case 0x11: /*** AMD Family 11h ***/
 			{
-				uint64_t cofvid = 0;
+
+				uint64_t prfsts;
 				uint64_t cpuMult;
 				uint64_t divisor = 0;
-				uint64_t did;
-				uint64_t fid;
+				uint64_t cpuDid;
+				uint64_t cpuFid;
 
-				cofvid  = rdmsr64(K10_COFVID_STATUS);
-				did = bitfield(cofvid, 8, 6);
-				fid = bitfield(cofvid, 5, 0);
-				if (did == 0) divisor = 2;
-				else if (did == 1) divisor = 4;
-				else if (did == 2) divisor = 8;
-				else if (did == 3) divisor = 16;
-				else if (did == 4) divisor = 32;
+				prfsts  = rdmsr64(AMD_COFVID_STS);
 
-				cpuMult = (fid + 8) / divisor;
+				cpuDid = bitfield(prfsts, 8, 6);
+				cpuFid = bitfield(prfsts, 5, 0);
+				if (cpuDid == 0) divisor = 2;
+				else if (cpuDid == 1) divisor = 4;
+				else if (cpuDid == 2) divisor = 8;
+				else if (cpuDid == 3) divisor = 16;
+				else if (cpuDid == 4) divisor = 0;
+				cpuMult = ((cpuFid + 0x8) * 10 ) / divisor;
 				currcoef = cpuMult;
 
-				cpuMultN2 = (cofvid & (uint64_t)bit(0));
+				cpuMultN2 = (prfsts & (uint64_t)bit(0));
 				currdiv = cpuMultN2;
 
 				/****** Addon END ******/
@@ -1029,7 +1072,7 @@
 				// 8:4 CpuFid: current CPU core frequency ID
 				// 3:0 CpuDid: current CPU core divisor ID
 				uint64_t prfsts,CpuFid,CpuDid;
-				prfsts = rdmsr64(K10_COFVID_STATUS);
+				prfsts = rdmsr64(AMD_COFVID_STS);
 
 				CpuDid = bitfield(prfsts, 3, 0) ;
 				CpuFid = bitfield(prfsts, 8, 4) ;
@@ -1047,7 +1090,7 @@
 					case 8: divisor = 16; break;
 					default: divisor = 1; break;
 				}
-				currcoef = (CpuFid + 0x10) / divisor;
+				currcoef = ((CpuFid + 0x10) * 10) / divisor;
 
 				cpuMultN2 = (prfsts & (uint64_t)bit(0));
 				currdiv = cpuMultN2;
@@ -1061,17 +1104,17 @@
 				// 8:4: current CPU core divisor ID most significant digit
 				// 3:0: current CPU core divisor ID least significant digit
 				uint64_t prfsts;
-				prfsts = rdmsr64(K10_COFVID_STATUS);
+				prfsts = rdmsr64(AMD_COFVID_STS);
 
 				uint64_t CpuDidMSD,CpuDidLSD;
 				CpuDidMSD = bitfield(prfsts, 8, 4) ;
 				CpuDidLSD  = bitfield(prfsts, 3, 0) ;
 
-				uint64_t frequencyId = 0x10;
-				currcoef = (frequencyId + 0x10) /
+				uint64_t frequencyId = tscFreq/Mega;
+				currcoef = (((frequencyId + 5) / 100) + 0x10) * 10 /
 					(CpuDidMSD + (CpuDidLSD  * 0.25) + 1);
 				currdiv = ((CpuDidMSD) + 1) << 2;
-				currdiv += bitfield(msr, 3, 0);
+				currdiv += bitfield(prfsts, 3, 0);
 
 				cpuMultN2 = (prfsts & (uint64_t)bit(0));
 				currdiv = cpuMultN2;
@@ -1083,62 +1126,56 @@
 			case 0x06: /*** AMD Family 06h ***/
 			{
 
-				uint64_t cofvid = 0;
+				uint64_t prfsts = 0;
 				uint64_t cpuMult;
-				uint64_t divisor = 0;
-				uint64_t did;
-				uint64_t fid;
+				//uint64_t divisor = 0;
+				uint64_t cpuDid;
+				uint64_t cpuFid;
 
-				cofvid  = rdmsr64(K10_COFVID_STATUS);
-				did = bitfield(cofvid, 8, 6);
-				fid = bitfield(cofvid, 5, 0);
-				if (did == 0) divisor = 2;
-				else if (did == 1) divisor = 4;
-				else if (did == 2) divisor = 8;
-				else if (did == 3) divisor = 16;
-				else if (did == 4) divisor = 32;
+				prfsts  = rdmsr64(AMD_COFVID_STS);
+				cpuDid = bitfield(prfsts, 8, 6);
+				cpuFid = bitfield(prfsts, 5, 0);
 
-				cpuMult = (fid + 16) / divisor;
+				cpuMult = ((cpuFid + 0x10) * 10) / (2^cpuDid);
 				currcoef = cpuMult;
 
-				cpuMultN2 = (cofvid & (uint64_t)bit(0));
+				cpuMultN2 = (prfsts & 0x01) * 1;//(prfsts & (uint64_t)bit(0));
 				currdiv = cpuMultN2;
 			}
 				break;
 
 			case 0x16: /*** AMD Family 16h kabini ***/
 			{
-				uint64_t cofvid = 0;
+				uint64_t prfsts = 0;
 				uint64_t cpuMult;
 				uint64_t divisor = 0;
-				uint64_t did;
+				uint64_t cpuDid;
+				uint64_t cpuFid;
+				prfsts  = rdmsr64(AMD_COFVID_STS);
+				cpuDid = bitfield(prfsts, 8, 6);
+				cpuFid = bitfield(prfsts, 5, 0);
+				if (cpuDid == 0) divisor = 1;
+				else if (cpuDid == 1) divisor = 2;
+				else if (cpuDid == 2) divisor = 4;
+				else if (cpuDid == 3) divisor = 8;
+				else if (cpuDid == 4) divisor = 16;
 
-				uint64_t fid;
-
-				cofvid  = rdmsr64(K10_COFVID_STATUS);
-				did = bitfield(cofvid, 8, 6);
-				fid = bitfield(cofvid, 5, 0);
-				if (did == 0) divisor = 1;
-				else if (did == 1) divisor = 2;
-				else if (did == 2) divisor = 4;
-				else if (did == 3) divisor = 8;
-				else if (did == 4) divisor = 16;
-
-				cpuMult = (fid + 16) / divisor;
+				cpuMult = ((cpuFid + 0x10) * 10) / divisor;
 				currcoef = cpuMult;
 
-				cpuMultN2 = (cofvid & (uint64_t)bit(0));
+				cpuMultN2 = (prfsts & (uint64_t)bit(0));
 				currdiv = cpuMultN2;
+
 				/****** Addon END ******/
 			}
 				break;
 
-			case 0x17: /*** Bronya: For AMD Family 17h Ryzen ***/
+			case 0x17: /*** AMD Family 17h Ryzen ***/
 			{
 				uint64_t cpuMult;
 				uint64_t CpuDfsId;
 				uint64_t CpuFid;
-
+				uint64_t fid = 0;
 				uint64_t prfsts = 0;
 
 				prfsts = rdmsr64(AMD_PSTATE0_STS);
@@ -1146,33 +1183,35 @@
 				CpuDfsId = bitfield(prfsts, 13, 8);
 				CpuFid = bitfield(prfsts, 7, 0);
 
-				cpuMult = (CpuFid  / CpuDfsId) * 2;
+				cpuMult = (CpuFid * 10 / CpuDfsId) * 2;
 
-				cpuMultN2 = (prfsts & (uint64_t)bit(0));
-				currdiv = cpuMultN2;
+				currcoef = cpuMult;
 
+				fid = (int)(cpuMult / 10);
+
+				uint8_t fdiv = cpuMult - (fid * 10);
+				if (fdiv > 0) {
+					currdiv = 1;
+				}
+
 				/****** Addon END ******/
 			}
 				break;
 
 			default:
 			{
-				typedef unsigned long long vlong;
-				uint64_t prfsts;
-				prfsts = rdmsr64(K10_COFVID_STATUS);
-				uint64_t r;
-				vlong hz;
-				r = (prfsts>>6) & 0x07;
-				hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);
-
-				currcoef = hz / (200 * Mega);
+				currcoef = tscFreq / (200 * Mega);
 			}
 		}
 
+		#define nya(x) x/10,x%10
+
 		if (currcoef)
 		{
 			if (currdiv)
 			{
+				currcoef = nya(currcoef);
+
 				busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));
 				busFCvtt2n = ((1 * Giga) << 32) / busFrequency;
 				tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));
@@ -1182,6 +1221,8 @@
 			}
 			else
 			{
+				currcoef = nya(currcoef);
+
 				busFrequency = (tscFreq / currcoef);
 				busFCvtt2n = ((1 * Giga) << 32) / busFrequency;
 				tscFCvtt2n = busFCvtt2n / currcoef;
Index: trunk/i386/libsaio/platform.h
===================================================================
--- trunk/i386/libsaio/platform.h	(revision 2898)
+++ trunk/i386/libsaio/platform.h	(revision 2899)
@@ -27,7 +27,8 @@
 #define CPUID_86			10
 #define CPUID_87			11
 #define CPUID_88			12
-#define CPUID_MAX			13
+#define CPUID_81E			13
+#define CPUID_MAX			14
 
 #define CPUID_MODEL_ANY			0x00
 #define CPUID_MODEL_UNKNOWN		0x01
@@ -337,16 +338,16 @@
 #define MSR_K7_CLK_CTL			0xC001001b
 #define MSR_K7_FID_VID_CTL		0xC0010041
 
-#define K8_FIDVID_STATUS		0xC0010042
-#define K10_COFVID_LIMIT		0xC0010061	// max enabled p-state (msr >> 4) & 7
-#define K10_COFVID_CONTROL		0xC0010062	// switch to p-state
-#define K10_PSTATE_STATUS		0xC0010064
-#define K10_COFVID_STATUS		0xC0010071	// current p-state (msr >> 16) & 7
+#define AMD_K8_PERF_STS 0xC0010042
+#define AMD_PSTATE_LIMIT 0xC0010061 // max enabled p-state (msr >> 4) & 7
+#define AMD_PSTATE_CONTROL 0xC0010062 // switch to p-state
+#define AMD_PSTATE0_STS 0xC0010064
+#define AMD_COFVID_STS 0xC0010071 // current p-state (msr >> 16) & 7
 
 #define MSR_AMD_MPERF			0x000000E7
 #define MSR_AMD_APERF			0x000000E8
-#define AMD_PSTATE0_STS			0xC0010064
 
+
 #define DEFAULT_FSB			100000          /* for now, hardcoding 100MHz for old CPUs */
 
 // DFE: This constant comes from older xnu:
Index: trunk/i386/libsaio/disk.c
===================================================================
--- trunk/i386/libsaio/disk.c	(revision 2898)
+++ trunk/i386/libsaio/disk.c	(revision 2899)
@@ -1712,6 +1712,7 @@
 	char *ECPattern     = "Install%20OS%20X%20El%20Capitan";
 	char *SierraPattern = "Install%20macOS%20Sierra";
 	char *HSierraPattern = "Install%20macOS%20High%20Sierra";
+	char *HSierraPatternB   = "Install%20macOS%2010.13";
 
 	/*
 	 * Only look for OS Version on HFS+
@@ -1817,6 +1818,12 @@
 				fakeOSVersionInt = 13;
 				valid = true;
 			}
+			else if(strstr(val, HSierraPatternB))
+			{
+				fakeOSVersion = "10.13";
+				fakeOSVersionInt = 13;
+				valid = true;
+			}
 			else
 			{
 				valid = false;
@@ -1932,9 +1939,32 @@
 			strncpy( bvr->OSBuildVer, "UPGRADE", strlen("UPGRADE") );
 			return true;
 		}
-		else
+	}
+
+	if (!valid)
+	{
+		len = 0; val = 0;
+		/*
+		 * Not valid? 10.13 and newer use "/macOS Install Data" folder..
+		 * and we have /macOS Install Data/Locked Files/Boot Files/SystemVersion.plist... thanks Apple!
+		 * NOTE: the stage 2 of this installation is already bootable (aug 13 2017)
+		 */
+		snprintf(dirSpec, sizeof(dirSpec),
+			"hd(%d,%d)/macOS Install Data/Locked Files/Boot Files/SystemVersion.plist",
+		BIOS_DEV_UNIT(bvr),
+		bvr->part_no);
+		if (!loadConfigFile(dirSpec, &configFile))
 		{
-			valid = false;
+			if  (getValueForKey(kProductVersion, &val, &len, &configFile))
+			{
+				// Copy the complete value into OSFullVer
+				strncpy( bvr->OSFullVer, val, len );
+				bvr->OSFullVer[len] = '\0';   /* null character manually added */
+
+				bvr->OSisOSXUpgrade = true;
+				strncpy( bvr->OSBuildVer, "UPGRADE", strlen("UPGRADE") );
+				return true;
+			}
 		}
 	}
 
Index: trunk/i386/boot2/Makefile
===================================================================
--- trunk/i386/boot2/Makefile	(revision 2898)
+++ trunk/i386/boot2/Makefile	(revision 2899)
@@ -56,7 +56,7 @@
 UTILDIR = $(SRCROOT)/i386/util
 DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
 BOOT2ADDR = 20200
-MAXBOOTSIZE = 458240
+MAXBOOTSIZE = 474624
 
 
 #
Index: trunk/i386/boot2/boot.c
===================================================================
--- trunk/i386/boot2/boot.c	(revision 2898)
+++ trunk/i386/boot2/boot.c	(revision 2899)
@@ -157,7 +157,6 @@
 // ===============================================================================
 
 	gMacOSVersion[0] = 0;
-	// TODO identify sierra as macOS
 	verbose("Booting on %s %s (%s)\n", (MacOSVerCurrent < MacOSVer2Int("10.8")) ? "Mac OS X" : (MacOSVerCurrent < MacOSVer2Int("10.12")) ? "OS X" : "macOS", gBootVolume->OSFullVer, gBootVolume->OSBuildVer );
 
 	setupBooterArgs();
@@ -420,7 +419,20 @@
 			// for 10.10 and 10.11
 			if (isOSXUpgrade)
 			{
-				snprintf(kernelCacheFile, sizeof(kernelCacheFile), "%sprelinkedkernel", "/OS X Install Data/");
+				if ( MacOSVerCurrent >= MacOSVer2Int("10.13") )
+				{
+					snprintf(kernelCacheFile, sizeof(kernelCacheFile),
+ 						"%sprelinkedkernel",
+						"/macOS Install Data/Locked Files/Boot Files/");
+				}
+				else
+				{
+					snprintf(kernelCacheFile,
+						sizeof(kernelCacheFile),
+						"%sprelinkedkernel",
+						"/OS X Install Data/");
+				}
+
 			}
 			else if (isInstaller)
 			{
@@ -488,17 +500,25 @@
 		}
 		else if (isOSXUpgrade)
 		{
-			strncpy(kernelCachePath, "/OS X Install Data/prelinkedkernel", sizeof(kernelCachePath) );
+			strncpy(kernelCachePath,
+				"/macOS Install Data/Locked Files/Boot Files/prelinkedkernel",
+				sizeof(kernelCachePath) );
 			ret = GetFileInfo(NULL, kernelCachePath, &flags, &cachetime);
 
 			if ((ret == -1) || ((flags & kFileTypeMask) != kFileTypeFlat))
 			{
-				strncpy(kernelCachePath, "/OS X Install Data/kernelcache", sizeof(kernelCachePath) );
+				strncpy(kernelCachePath, "/OS X Install Data/prelinkedkernel", sizeof(kernelCachePath) );
 				ret = GetFileInfo(NULL, kernelCachePath, &flags, &cachetime);
 
-				if ((flags & kFileTypeMask) != kFileTypeFlat)
+				if ((ret == -1) || ((flags & kFileTypeMask) != kFileTypeFlat))
 				{
-					ret = -1;
+					strncpy(kernelCachePath, "/OS X Install Data/kernelcache", sizeof(kernelCachePath) );
+					ret = GetFileInfo(NULL, kernelCachePath, &flags, &cachetime);
+
+					if ((flags & kFileTypeMask) != kFileTypeFlat)
+					{
+						ret = -1;
+					}
 				}
 			}
 		}
@@ -1149,11 +1169,11 @@
 		}
 		else
 		{
-			bootArgs->flags		|= kBootArgsFlagCSRActiveConfig;
+			bootArgs->flags	|= kBootArgsFlagCSRActiveConfig;
 		}
 
-		// Set limit to 7bit
-		if ( getIntForKey(kCsrActiveConfig, &csrValue, &bootInfo->chameleonConfig) && (csrValue >= 0 && csrValue <= 127) )
+		// Set limit to 8bit
+		if ( getIntForKey(kCsrActiveConfig, &csrValue, &bootInfo->chameleonConfig) && (csrValue >= 0 && csrValue <= 255) )
 		{
 			bootArgs->csrActiveConfig	= csrValue;
 			csrInfo(csrValue, 1);
@@ -1178,30 +1198,32 @@
 // ErmaC
 void csrInfo(int csrValue, bool custom)
 {
-	int mask = 0x20;
+#define CSR_BITS 0x080
+
+	int mask = CSR_BITS;
 	verbose("System Integrity Protection status: %s ", (csrValue == 0) ? "enabled":"disabled");
-	verbose("(%s Configuration).\nCsrActiveConfig = 0x%02x (", custom ? "Custom":"Default", csrValue);
+	verbose("(%s Configuration).\nCsrActiveConfig = 0x%02X (", custom ? "Custom":"Default", csrValue);
 
 	// Display integer number into binary using bitwise operator
-	((csrValue & 0x20) == 0) ? verbose("0"): verbose("1");
+	((csrValue & 0x020) == 0) ? verbose("0"): verbose("1");
 	while (mask != 0)
 	{
 		( ((csrValue & mask) == 0) ? verbose("0"): verbose("1") );
-		mask = mask >> 1;
+		mask = mask >> 1; // Right Shift
 	}
 	verbose(")\n");
 	if (csrValue != 0)
 	{
 		verbose("\nConfiguration:\n");
-		verbose("Kext Signing: %s\n", ((csrValue & 0x01) == 0) ? "enabled":"disabled");           /* (1 << 0) Allow untrusted kexts */
-		verbose("Filesystem Protections: %s\n", ((csrValue & 0x02) == 0) ? "enabled":"disabled"); /* (1 << 1) Allow unrestricted file system. */
-		verbose("Task for PID: %s\n", ((csrValue & 0x04) == 0) ? "enabled":"disabled");           /* (1 << 2) */
-		verbose("Debugging Restrictions: %s\n", ((csrValue & 0x08) == 0) ? "enabled":"disabled"); /* (1 << 3) */
-		verbose("Apple Internal: %s\n", ((csrValue & 0x10) == 0) ? "enabled":"disabled");         /* (1 << 4) */
-		verbose("DTrace Restrictions: %s\n", ((csrValue & 0x20) == 0) ? "enabled":"disabled");    /* (1 << 5) Allow unrestricted dtrace */
-		verbose("NVRAM Protections: %s\n", ((csrValue & 0x40) == 0) ? "enabled":"disabled");      /* (1 << 6) Allow unrestricted NVRAM */
-//		verbose("DEVICE configuration: %s\n", ((csrValue & 0x80) == 0) ? "enabled":"disabled");   /* (1 << 7) Allow device configuration */
-//		verbose("Disable BaseSystem Verification: %s\n", ((csrValue & 0x100) == 0) ? "enabled":"disabled");   /* (1 << 8) Disable BaseSystem Verification */
+		verbose("Kext Signing: %s\n", ((csrValue & 0x001) == 0) ? "enabled":"disabled");           /* (1 << 0) Allow untrusted kexts */
+		verbose("Filesystem Protections: %s\n", ((csrValue & 0x002) == 0) ? "enabled":"disabled"); /* (1 << 1) Allow unrestricted file system. */
+		verbose("Task for PID: %s\n", ((csrValue & 0x004) == 0) ? "enabled":"disabled");           /* (1 << 2) */
+		verbose("Debugging Restrictions: %s\n", ((csrValue & 0x008) == 0) ? "enabled":"disabled"); /* (1 << 3) */
+		verbose("Apple Internal: %s\n", ((csrValue & 0x010) == 0) ? "enabled":"disabled");         /* (1 << 4) */
+		verbose("DTrace Restrictions: %s\n", ((csrValue & 0x020) == 0) ? "enabled":"disabled");    /* (1 << 5) Allow unrestricted dtrace */
+		verbose("NVRAM Protections: %s\n", ((csrValue & 0x040) == 0) ? "enabled":"disabled");      /* (1 << 6) Allow unrestricted NVRAM */
+		verbose("Device configuration: %s\n", ((csrValue & 0x080) == 0) ? "enabled":"disabled");   /* (1 << 7) Allow device configuration */
+		verbose("BaseSystem Verification: %s\n", ((csrValue & 0x100) == 0) ? "enabled":"disabled");   /* (1 << 8) Allow any Recovery OS */
 	}
 	verbose("\n");
 }
Index: trunk/i386/boot2/options.c
===================================================================
--- trunk/i386/boot2/options.c	(revision 2898)
+++ trunk/i386/boot2/options.c	(revision 2899)
@@ -1401,7 +1401,10 @@
 
 		loadConfigFile(caBp, &ocBplist);
 		rval = getStringForKey(kKernelFlagsKey, &ocBplist);
-		addBootArg(rval);
+
+		if (rval) {
+			addBootArg(rval);
+		}
 	}
 
 	// Micky1979 (Vanilla Installer)
@@ -1416,7 +1419,10 @@
 
 		loadConfigFile(caBp, &ocBplist);
 		rval = getStringForKey(kKernelFlagsKey, &ocBplist);
-		addBootArg(rval);
+
+		if (rval) {
+			addBootArg(rval);
+		}
 	}
 
 	// Micky1979 (old Vanilla upgrade)
@@ -1430,21 +1436,41 @@
 
 		loadConfigFile(caBp, &ocBplist);
 		rval = getStringForKey(kKernelFlagsKey, &ocBplist);
-		addBootArg(rval);
+
+		if (rval) {
+			addBootArg(rval);
+		}
 	}
 
 	// Micky1979 (new Vanilla upgrade)
-	if (gBootVolume->OSisMacOSXUpgrade)
+	if (gBootVolume->OSisOSXUpgrade)
 	{
 		const char	*rval = 0;
 		config_file_t ocBplist;
 		char  caBp[2048];
+		bool found = false;
+		snprintf(caBp, sizeof(caBp), "/macOS Install Data/Locked Files/Boot Files/com.apple.Boot.plist");
 
-		snprintf(caBp, sizeof(caBp), "/OS X Install Data/com.apple.Boot.plist");
+		if (!loadConfigFile(caBp, &ocBplist))
+		{
+			found = true;
+		}
 
-		loadConfigFile(caBp, &ocBplist);
-		rval = getStringForKey(kKernelFlagsKey, &ocBplist);
-		addBootArg(rval);
+		if (!found) {
+			snprintf(caBp, sizeof(caBp), "/OS X Install Data/com.apple.Boot.plist");
+
+			if (!loadConfigFile(caBp, &ocBplist))
+			{
+				found = true;
+			}
+		}
+
+		if (found) {
+			rval = getStringForKey(kKernelFlagsKey, &ocBplist);
+			if (rval) {
+				addBootArg(rval);
+			}
+		}
 	}
 
 	cntRemaining = BOOT_STRING_LEN - 2;  // save 1 for NULL, 1 for space
Index: trunk/i386/cdboot/cdboot.s
===================================================================
--- trunk/i386/cdboot/cdboot.s	(revision 2898)
+++ trunk/i386/cdboot/cdboot.s	(revision 2899)
@@ -114,7 +114,7 @@
 										; at build time.     
 kSectorBytes  		 EQU  2048			; sector size in bytes
 kBoot2Size			 EQU  65024			; default load size for boot2
-kBoot2MaxSize	     EQU  458240		; max size for boot2
+kBoot2MaxSize	     EQU  474624		; max size for boot2
 kBoot2Address        EQU  0x0200        ; boot2 load address
 kBoot2Segment        EQU  0x2000        ; boot2 load segment
 	
Index: trunk/doc/BootHelp.txt
===================================================================
--- trunk/doc/BootHelp.txt	(revision 2898)
+++ trunk/doc/BootHelp.txt	(revision 2899)
@@ -77,7 +77,7 @@
   BlackMode=Yes|No        The new BlackMode loads the white Apple logo,
                              instead of the gray Apple logo, on a black background (disabled by default).
 
-  CsrActiveConfig=<value> Set CsrActiveConfig for OS 10.11.x, range 0..127 (default 0x67)
+  CsrActiveConfig=<value> Set CsrActiveConfig for OS 10.11.x, range 0..255 (default 0x67)
 
   PciRoot=<value>         Use an alternate value for PciRoot (default value 0).