Index: trunk/i386/libsaio/acpi_patcher.c =================================================================== --- trunk/i386/libsaio/acpi_patcher.c (revision 312) +++ trunk/i386/libsaio/acpi_patcher.c (revision 313) @@ -386,8 +386,7 @@ get_acpi_cpu_names((void*)dsdt, dsdt->Length); if (acpi_cpu_count > 0) - { - + { struct p_state initial, maximum, minimum, p_states[32]; uint8_t p_states_count = 0; @@ -397,9 +396,11 @@ { switch (Platform.CPU.Model) { - case 0x0F: // Intel Core (65nm) - case 0x17: // Intel Core (45nm) - case 0x1C: // Intel Atom (45nm) + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah + case CPU_MODEL_MEROM: // Merom + case CPU_MODEL_PENRYN: // Penryn + case CPU_MODEL_ATOM: // Intel Atom (45nm) { bool cpu_dynamic_fsb = false; @@ -515,12 +516,12 @@ p_states_count -= invalid; } } break; - case 0x1A: // Intel Core i7 LGA1366 (45nm) - case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) - case 0x1F: - case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) - case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core - case 0x2F: + case CPU_MODEL_FIELDS: + case CPU_MODEL_NEHALEM: + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: + case CPU_MODEL_WESTMERE: + case CPU_MODEL_WESTMERE_EX: default: verbose ("Unsupported CPU: P-States not generated !!!\n"); break; @@ -529,7 +530,6 @@ } // Generating SSDT - if (p_states_count > 0) { int i; Index: trunk/i386/libsaio/smbios_patcher.c =================================================================== --- trunk/i386/libsaio/smbios_patcher.c (revision 312) +++ trunk/i386/libsaio/smbios_patcher.c (revision 313) @@ -88,34 +88,49 @@ // defaults for a Mac Pro static const SMStrEntryPair const sm_macpro_defaults[]={ - {"SMbiosvendor", "Apple Computer, Inc." }, - {"SMbiosversion", "MP31.88Z.006C.B05.0802291410" }, - {"SMbiosdate", "04/01/2008" }, - {"SMmanufacter", "Apple Computer, Inc." }, - {"SMproductname", "MacPro3,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "MacPro" }, - {"SMboardmanufacter", "Apple Computer, Inc." }, - {"SMboardproduct", "Mac-F4208DC8" }, + {"SMbiosvendor", "Apple Computer, Inc." }, + {"SMbiosversion", "MP31.88Z.006C.B05.0802291410" }, + {"SMbiosdate", "04/01/2008" }, + {"SMmanufacter", "Apple Computer, Inc." }, + {"SMproductname", "MacPro3,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "MacPro" }, + {"SMboardmanufacter", "Apple Computer, Inc." }, + {"SMboardproduct", "Mac-F4208DC8" }, { "","" } }; -// defaults for an iMac11,1 core i5/i7 -static const SMStrEntryPair const sm_imacCore_i5_i7_defaults[]={ - {"SMbiosvendor", "Apple Inc." }, - {"SMbiosversion", "IM111.0034.B00" }, - {"SMbiosdate", "06/01/2009" }, - {"SMmanufacter", "Apple Inc." }, - {"SMproductname", "iMac11,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "iMac" }, - {"SMboardmanufacter","Apple Computer, Inc." }, - {"SMboardproduct", "Mac-F2268DAE" }, +// defaults for an iMac11,1 core i3/i5/i7 +static const SMStrEntryPair const sm_imac_core_defaults[]={ + {"SMbiosvendor", "Apple Inc." }, + {"SMbiosversion", "IM111.88Z.0034.B00.0802091538" }, + {"SMbiosdate", "06/01/2009" }, + {"SMmanufacter", "Apple Inc." }, + {"SMproductname", "iMac11,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "iMac" }, + {"SMboardmanufacter", "Apple Computer, Inc." }, + {"SMboardproduct", "Mac-F2268DAE" }, { "","" } }; +// defaults for a Mac Pro 4,1 core i7/Xeon +static const SMStrEntryPair const sm_macpro_core_defaults[]={ + {"SMbiosvendor", "Apple Computer, Inc." }, + {"SMbiosversion", "MP41.88Z.0081.B04.0903051113" }, + {"SMbiosdate", "11/06/2009" }, + {"SMmanufacter", "Apple Computer, Inc." }, + {"SMproductname", "MacPro4,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "MacPro" }, + {"SMboardmanufacter", "Apple Computer, Inc." }, + {"SMboardproduct", "Mac-F4208DC8" }, + { "","" } +}; + static const char* sm_get_defstr(const char * key, int table_num) { int i; @@ -144,11 +159,18 @@ { switch (Platform.CPU.Model) { - case 0x19: // Intel Core i5 650 - case 0x1E: // Intel Core i7 LGA1156 (45nm) - case 0x1F: // Intel Core i5 LGA1156 (45nm) - sm_defaults=sm_imacCore_i5_i7_defaults; + case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + case 0x19: // Intel Core i5 650 @3.20 Ghz + sm_defaults=sm_imac_core_defaults; break; + case CPU_MODEL_NEHALEM: + case CPU_MODEL_NEHALEM_EX: + case CPU_MODEL_WESTMERE: + case CPU_MODEL_WESTMERE_EX: + sm_defaults=sm_macpro_core_defaults; + break; default: sm_defaults=sm_macpro_defaults; break; @@ -210,21 +232,32 @@ { switch (Platform.CPU.Model) { - case 0x0F: // Intel Core (65nm) - case 0x17: // Intel Core (45nm) - case 0x1C: // Intel Atom (45nm) + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah + case CPU_MODEL_MEROM: // Merom + case CPU_MODEL_PENRYN: // Penryn + case CPU_MODEL_ATOM: // Intel Atom (45nm) return 0; // TODO: populate bus speed for these processors - case 0x19: // Intel Core i5 650 @3.20 Ghz - return 3600; // GT/s / 1000 - case 0x1A: // Intel Core i7 LGA1366 (45nm) - case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) - case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ??? + + case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + return 2500; // Core i5 + return 4800; // Core i7 + + case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + case CPU_MODEL_NEHALEM_EX: + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? return 4800; // GT/s / 1000 - case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) + + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) return 0; // TODO: populate bus speed for these processors - case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core - case 0x2E: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + + case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS) + case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? return 0; // TODO: populate bus speed for these processors + + case 0x19: // Intel Core i5 650 @3.20 Ghz + return 3600; // why? Intel spec says 2.5GT/s } } } @@ -239,7 +272,7 @@ if (Platform.CPU.Vendor == 0x756E6547) // Intel { if (!done) { - verbose("CPU is Intel, family 0x%x, model 0x%x, ext.model 0x%x\n", Platform.CPU.Family, Platform.CPU.Model, Platform.CPU.ExtModel); + verbose("CPU is %s, family 0x%x, model 0x%x, brand %s\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model); done = true; } @@ -249,23 +282,39 @@ { switch (Platform.CPU.Model) { - case 0x0F: // Intel Core (65nm) - case 0x17: // Intel Core (45nm) - case 0x1C: // Intel Atom (45nm) + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah + case CPU_MODEL_MEROM: // Merom + case CPU_MODEL_PENRYN: // Penryn + case CPU_MODEL_ATOM: // Intel Atom (45nm) return sm_get_simplecputype(); - case 0x1A: // Intel Core i7 LGA1366 (45nm) - return 0x0701; - case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) - // get this opportunity to fill the known processor interconnect speed for cor i5/i7 in GT/s - return 0x0701; + + case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + return 0x0701; // Core i7 + + case CPU_MODEL_FIELDS: // Lynnfield, Clarksfield, Jasper + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + return 0x601; // Core i5 + return 0x701; // Core i7 + + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale) + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + return 0x601; // Core i5 + return 0x0701; // Core i7 + + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) + return 0x301; // Core i3 + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + return 0x601; // Core i5 + return 0x0701; // Core i7 + + case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS) + case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + return 0x0701; // Core i7 + case 0x19: // Intel Core i5 650 @3.20 Ghz - case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ??? - return 0x0601; - case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) - return 0x0301; - case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core - case 0x2E: // Intel Core i7 LGA1366 (45nm) 6 Core ??? - return 0x0601; + return 0x601; // Core i5 } } } Index: trunk/i386/libsaio/cpu.c =================================================================== --- trunk/i386/libsaio/cpu.c (revision 312) +++ trunk/i386/libsaio/cpu.c (revision 313) @@ -120,6 +120,8 @@ } #endif p->CPU.Vendor = p->CPU.CPUID[CPUID_0][1]; + p->CPU.Signature = p->CPU.CPUID[CPUID_1][0]; + p->CPU.Stepping = bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); p->CPU.Model = bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); p->CPU.Family = bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); p->CPU.ExtModel = bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); @@ -128,7 +130,35 @@ p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1; p->CPU.Model += (p->CPU.ExtModel << 4); - + + /* get brand string (if supported) */ + /* Copyright: from Apple's XNU cpuid.c */ + if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) { + uint32_t reg[4]; + char str[128], *c; + /* + * The brand string 48 bytes (max), guaranteed to + * be NUL terminated. + */ + do_cpuid(0x80000002, reg); + bcopy((char *)reg, &p->CPU.BrandString[0], 16); + do_cpuid(0x80000003, reg); + bcopy((char *)reg, &p->CPU.BrandString[16], 16); + do_cpuid(0x80000004, reg); + bcopy((char *)reg, &p->CPU.BrandString[32], 16); + for (c = str; *c != '\0'; c++) { + if (*c != ' ') break; + } + + if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) { + /* + * This string means we have a firmware-programmable brand string, + * and the firmware couldn't figure out what sort of CPU we have. + */ + p->CPU.BrandString[0] = '\0'; + } + } + /* setup features */ if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) { p->CPU.Features |= CPU_FEATURE_MMX; Index: trunk/i386/libsaio/platform.h =================================================================== --- trunk/i386/libsaio/platform.h (revision 312) +++ trunk/i386/libsaio/platform.h (revision 313) @@ -23,6 +23,18 @@ #define CPUID_81 6 #define CPUID_MAX 7 +#define CPU_MODEL_YONAH 0x0E +#define CPU_MODEL_MEROM 0x0F +#define CPU_MODEL_PENRYN 0x17 +#define CPU_MODEL_NEHALEM 0x1A +#define CPU_MODEL_ATOM 0x1C +#define CPU_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield, Jasper */ +#define CPU_MODEL_DALES 0x1F /* Havendale, Auburndale */ +#define CPU_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */ +#define CPU_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP, Westmere-WS */ +#define CPU_MODEL_NEHALEM_EX 0x2E +#define CPU_MODEL_WESTMERE_EX 0x2F + /* CPU Features */ #define CPU_FEATURE_MMX 0x00000001 // MMX Instruction Set #define CPU_FEATURE_SSE 0x00000002 // SSE Instruction Set @@ -36,9 +48,9 @@ #define CPU_FEATURE_MSR 0x00000200 // MSR Support /* SMBIOS Memory Types */ -#define SMB_MEM_TYPE_UNDEFINED 0 +#define SMB_MEM_TYPE_UNDEFINED 0 #define SMB_MEM_TYPE_OTHER 1 -#define SMB_MEM_TYPE_UNKNOWN 2 +#define SMB_MEM_TYPE_UNKNOWN 2 #define SMB_MEM_TYPE_DRAM 3 #define SMB_MEM_TYPE_EDRAM 4 #define SMB_MEM_TYPE_VRAM 5 @@ -93,6 +105,8 @@ struct CPU { uint32_t Features; // CPU Features like MMX, SSE2, VT, MobileCPU uint32_t Vendor; // Vendor + uint32_t Signature; // Signature + uint32_t Stepping; // Stepping uint32_t Model; // Model uint32_t ExtModel; // Extended Model uint32_t Family; // Family @@ -106,7 +120,7 @@ uint64_t TSCFrequency; // TSC Frequency Hz uint64_t FSBFrequency; // FSB Frequency Hz uint64_t CPUFrequency; // CPU Frequency Hz - uint32_t BrandString[16]; // 48 Byte Branding String + char BrandString[48]; // 48 Byte Branding String uint32_t CPUID[CPUID_MAX][4]; // CPUID 0..4, 80..81 Raw Values } CPU; @@ -120,7 +134,7 @@ uint8_t Channels; // Channel Configuration Single,Dual or Triple uint8_t NoSlots; // Maximum no of slots available uint8_t Type; // Standard SMBIOS v2.5 Memory Type - RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot + RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot } RAM; struct DMI { Index: trunk/i386/libsaio/cpu.h =================================================================== --- trunk/i386/libsaio/cpu.h (revision 312) +++ trunk/i386/libsaio/cpu.h (revision 313) @@ -14,6 +14,8 @@ #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1)) #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l) +#define CPU_STRING_UNKNOWN "Unknown CPU Typ" + #define MSR_IA32_PERF_STATUS 0x198 #define MSR_IA32_PERF_CONTROL 0x199 #define MSR_IA32_EXT_CONFIG 0x00EE