Index: branches/azimutz/CleanCut/i386/libsaio/acpi_patcher.c =================================================================== --- branches/azimutz/CleanCut/i386/libsaio/acpi_patcher.c (revision 322) +++ branches/azimutz/CleanCut/i386/libsaio/acpi_patcher.c (revision 323) @@ -362,7 +362,7 @@ } struct acpi_2_ssdt *generate_pss_ssdt(struct acpi_2_dsdt* dsdt) -{ +{ char ssdt_header[] = { 0x53, 0x53, 0x44, 0x54, 0x7E, 0x00, 0x00, 0x00, /* SSDT.... */ @@ -386,8 +386,7 @@ get_acpi_cpu_names((void*)dsdt, dsdt->Length); if (acpi_cpu_count > 0) - { - + { struct p_state initial, maximum, minimum, p_states[32]; uint8_t p_states_count = 0; @@ -397,9 +396,11 @@ { switch (Platform.CPU.Model) { - case 0x0F: // Intel Core (65nm) - case 0x17: // Intel Core (45nm) - case 0x1C: // Intel Atom (45nm) + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah + case CPU_MODEL_MEROM: // Merom + case CPU_MODEL_PENRYN: // Penryn + case CPU_MODEL_ATOM: // Intel Atom (45nm) { bool cpu_dynamic_fsb = false; @@ -515,12 +516,12 @@ p_states_count -= invalid; } } break; - case 0x1A: // Intel Core i7 LGA1366 (45nm) - case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) - case 0x1F: - case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) - case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core - case 0x2F: + case CPU_MODEL_FIELDS: + case CPU_MODEL_NEHALEM: + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: + case CPU_MODEL_WESTMERE: + case CPU_MODEL_WESTMERE_EX: default: verbose ("Unsupported CPU: P-States not generated !!!\n"); break; @@ -529,7 +530,6 @@ } // Generating SSDT - if (p_states_count > 0) { int i; Index: branches/azimutz/CleanCut/i386/libsaio/smbios_patcher.c =================================================================== --- branches/azimutz/CleanCut/i386/libsaio/smbios_patcher.c (revision 322) +++ branches/azimutz/CleanCut/i386/libsaio/smbios_patcher.c (revision 323) @@ -10,6 +10,7 @@ #include "fake_efi.h" #include "platform.h" #include "smbios_patcher.h" +#include "pci.h" #ifndef DEBUG_SMBIOS #define DEBUG_SMBIOS 0 @@ -28,94 +29,109 @@ // defaults for a MacBook static const SMStrEntryPair const sm_macbook_defaults[]={ - {"SMbiosvendor", "Apple Inc." }, - {"SMbiosversion", "MB41.88Z.0073.B00.0809221748" }, - {"SMbiosdate", "04/01/2008" }, - {"SMmanufacter", "Apple Inc." }, - {"SMproductname", "MacBook4,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "MacBook" }, - {"SMboardmanufacter", "Apple Inc." }, - {"SMboardproduct", "Mac-F42D89C8" }, + {"SMbiosvendor", "Apple Inc." }, + {"SMbiosversion", "MB41.88Z.0073.B00.0809221748" }, + {"SMbiosdate", "04/01/2008" }, + {"SMmanufacter", "Apple Inc." }, + {"SMproductname", "MacBook4,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "MacBook" }, + {"SMboardmanufacter", "Apple Inc." }, + {"SMboardproduct", "Mac-F42D89C8" }, { "","" } }; // defaults for a MacBook Pro static const SMStrEntryPair const sm_macbookpro_defaults[]={ - {"SMbiosvendor", "Apple Inc." }, - {"SMbiosversion", "MBP41.88Z.0073.B00.0809221748" }, - {"SMbiosdate", "04/01/2008" }, - {"SMmanufacter", "Apple Inc." }, - {"SMproductname", "MacBookPro4,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "MacBookPro" }, - {"SMboardmanufacter", "Apple Inc." }, - {"SMboardproduct", "Mac-F42D89C8" }, + {"SMbiosvendor", "Apple Inc." }, + {"SMbiosversion", "MBP41.88Z.0073.B00.0809221748" }, + {"SMbiosdate", "04/01/2008" }, + {"SMmanufacter", "Apple Inc." }, + {"SMproductname", "MacBookPro4,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "MacBookPro" }, + {"SMboardmanufacter", "Apple Inc." }, + {"SMboardproduct", "Mac-F42D89C8" }, { "","" } }; // defaults for a Mac mini static const SMStrEntryPair const sm_macmini_defaults[]={ - {"SMbiosvendor", "Apple Inc." }, - {"SMbiosversion", "MM21.88Z.009A.B00.0706281359" }, - {"SMbiosdate", "04/01/2008" }, - {"SMmanufacter", "Apple Inc." }, - {"SMproductname", "Macmini2,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "Napa Mac" }, - {"SMboardmanufacter", "Apple Inc." }, - {"SMboardproduct", "Mac-F4208EAA" }, + {"SMbiosvendor", "Apple Inc." }, + {"SMbiosversion", "MM21.88Z.009A.B00.0706281359" }, + {"SMbiosdate", "04/01/2008" }, + {"SMmanufacter", "Apple Inc." }, + {"SMproductname", "Macmini2,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "Napa Mac" }, + {"SMboardmanufacter", "Apple Inc." }, + {"SMboardproduct", "Mac-F4208EAA" }, { "","" } }; // defaults for an iMac static const SMStrEntryPair const sm_imac_defaults[]={ - {"SMbiosvendor", "Apple Inc." }, - {"SMbiosversion", "IM81.88Z.00C1.B00.0802091538" }, - {"SMbiosdate", "04/01/2008" }, - {"SMmanufacter", "Apple Inc." }, - {"SMproductname", "iMac8,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "Mac" }, - {"SMboardmanufacter", "Apple Inc." }, - {"SMboardproduct", "Mac-F227BEC8" }, + {"SMbiosvendor", "Apple Inc." }, + {"SMbiosversion", "IM81.88Z.00C1.B00.0802091538" }, + {"SMbiosdate", "04/01/2008" }, + {"SMmanufacter", "Apple Inc." }, + {"SMproductname", "iMac8,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "Mac" }, + {"SMboardmanufacter", "Apple Inc." }, + {"SMboardproduct", "Mac-F227BEC8" }, { "","" } }; // defaults for a Mac Pro static const SMStrEntryPair const sm_macpro_defaults[]={ - {"SMbiosvendor", "Apple Computer, Inc." }, - {"SMbiosversion", "MP31.88Z.006C.B05.0802291410" }, - {"SMbiosdate", "04/01/2008" }, - {"SMmanufacter", "Apple Computer, Inc." }, - {"SMproductname", "MacPro3,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "MacPro" }, - {"SMboardmanufacter", "Apple Computer, Inc." }, - {"SMboardproduct", "Mac-F4208DC8" }, + {"SMbiosvendor", "Apple Computer, Inc." }, + {"SMbiosversion", "MP31.88Z.006C.B05.0802291410" }, + {"SMbiosdate", "04/01/2008" }, + {"SMmanufacter", "Apple Computer, Inc." }, + {"SMproductname", "MacPro3,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "MacPro" }, + {"SMboardmanufacter", "Apple Computer, Inc." }, + {"SMboardproduct", "Mac-F4208DC8" }, { "","" } }; -// defaults for an iMac11,1 core i5/i7 -static const SMStrEntryPair const sm_imacCore_i5_i7_defaults[]={ - {"SMbiosvendor", "Apple Inc." }, - {"SMbiosversion", "IM111.0034.B00" }, - {"SMbiosdate", "06/01/2009" }, - {"SMmanufacter", "Apple Inc." }, - {"SMproductname", "iMac11,1" }, - {"SMsystemversion", "1.0" }, - {"SMserial", "SOMESRLNMBR" }, - {"SMfamily", "iMac" }, - {"SMboardmanufacter","Apple Computer, Inc." }, - {"SMboardproduct", "Mac-F2268DAE" }, +// defaults for an iMac11,1 core i3/i5/i7 +static const SMStrEntryPair const sm_imac_core_defaults[]={ + {"SMbiosvendor", "Apple Inc." }, + {"SMbiosversion", "IM111.88Z.0034.B00.0802091538" }, + {"SMbiosdate", "06/01/2009" }, + {"SMmanufacter", "Apple Inc." }, + {"SMproductname", "iMac11,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "iMac" }, + {"SMboardmanufacter", "Apple Computer, Inc." }, + {"SMboardproduct", "Mac-F2268DAE" }, { "","" } }; +// defaults for a Mac Pro 4,1 core i7/Xeon +static const SMStrEntryPair const sm_macpro_core_defaults[]={ + {"SMbiosvendor", "Apple Computer, Inc." }, + {"SMbiosversion", "MP41.88Z.0081.B04.0903051113" }, + {"SMbiosdate", "11/06/2009" }, + {"SMmanufacter", "Apple Computer, Inc." }, + {"SMproductname", "MacPro4,1" }, + {"SMsystemversion", "1.0" }, + {"SMserial", "SOMESRLNMBR" }, + {"SMfamily", "MacPro" }, + {"SMboardmanufacter", "Apple Computer, Inc." }, + {"SMboardproduct", "Mac-F4208DC8" }, + { "","" } +}; + static const char* sm_get_defstr(const char * key, int table_num) { int i; @@ -144,11 +160,18 @@ { switch (Platform.CPU.Model) { - case 0x19: // Intel Core i5 650 - case 0x1E: // Intel Core i7 LGA1156 (45nm) - case 0x1F: // Intel Core i5 LGA1156 (45nm) - sm_defaults=sm_imacCore_i5_i7_defaults; + case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + case 0x19: // Intel Core i5 650 @3.20 Ghz + sm_defaults=sm_imac_core_defaults; break; + case CPU_MODEL_NEHALEM: + case CPU_MODEL_NEHALEM_EX: + case CPU_MODEL_WESTMERE: + case CPU_MODEL_WESTMERE_EX: + sm_defaults=sm_macpro_core_defaults; + break; default: sm_defaults=sm_macpro_defaults; break; @@ -200,7 +223,7 @@ return 0x0301; // Core 2 Duo } -static int sm_get_bus_speed (const char *name, int table_num) +static int sm_get_bus_speed(const char *name, int table_num) { if (Platform.CPU.Vendor == 0x756E6547) // Intel { @@ -210,21 +233,65 @@ { switch (Platform.CPU.Model) { - case 0x0F: // Intel Core (65nm) - case 0x17: // Intel Core (45nm) - case 0x1C: // Intel Atom (45nm) + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah 0x0E + case CPU_MODEL_MEROM: // Merom 0x0F + case CPU_MODEL_PENRYN: // Penryn 0x17 + case CPU_MODEL_ATOM: // Atom 45nm 0x1C return 0; // TODO: populate bus speed for these processors + +// case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) +// if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) +// return 2500; // Core i5 +// return 4800; // Core i7 + +// case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) +// case CPU_MODEL_NEHALEM_EX: +// case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? +// return 4800; // GT/s / 1000 +// + case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + return 0; // TODO: populate bus speed for these processors + +// case 0x19: // Intel Core i5 650 @3.20 Ghz +// return 2500; // why? Intel spec says 2.5GT/s + case 0x19: // Intel Core i5 650 @3.20 Ghz - return 3600; // GT/s / 1000 - case 0x1A: // Intel Core i7 LGA1366 (45nm) - case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) - case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ??? - return 4800; // GT/s / 1000 - case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) - return 0; // TODO: populate bus speed for these processors - case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core - case 0x2E: // Intel Core i7 LGA1366 (45nm) 6 Core ??? - return 0; // TODO: populate bus speed for these processors + case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) + case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core + case CPU_MODEL_NEHALEM_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + { // thanks to dgobe for i3/i5/i7 bus speed detection + int nhm_bus = 0x3F; + static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F}; + unsigned long did, vid; + int i; + + // Nehalem supports Scrubbing + // First, locate the PCI bus where the MCH is located + for(i = 0; i < sizeof(possible_nhm_bus); i++) + { + vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00); + did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02); + vid &= 0xFFFF; + did &= 0xFF00; + + if(vid == 0x8086 && did >= 0x2C00) + nhm_bus = possible_nhm_bus[i]; + } + + unsigned long qpimult, qpibusspeed; + qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50); + qpimult &= 0x7F; + DBG("qpimult %d\n", qpimult); + qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000)); + // Rek: rounding decimals to match original mac profile info + if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100; + DBG("qpibusspeed %d\n", qpibusspeed); + return qpibusspeed; + } } } } @@ -239,7 +306,7 @@ if (Platform.CPU.Vendor == 0x756E6547) // Intel { if (!done) { - verbose("CPU is Intel, family 0x%x, model 0x%x, ext.model 0x%x\n", Platform.CPU.Family, Platform.CPU.Model, Platform.CPU.ExtModel); + verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model); done = true; } @@ -249,23 +316,39 @@ { switch (Platform.CPU.Model) { - case 0x0F: // Intel Core (65nm) - case 0x17: // Intel Core (45nm) - case 0x1C: // Intel Atom (45nm) + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah + case CPU_MODEL_MEROM: // Merom + case CPU_MODEL_PENRYN: // Penryn + case CPU_MODEL_ATOM: // Intel Atom (45nm) return sm_get_simplecputype(); - case 0x1A: // Intel Core i7 LGA1366 (45nm) - return 0x0701; - case 0x1E: // Intel Core i5, i7 LGA1156 (45nm) - // get this opportunity to fill the known processor interconnect speed for cor i5/i7 in GT/s - return 0x0701; + + case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + return 0x0701; // Core i7 + + case CPU_MODEL_FIELDS: // Lynnfield, Clarksfield, Jasper + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + return 0x601; // Core i5 + return 0x701; // Core i7 + + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale) + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + return 0x601; // Core i5 + return 0x0701; // Core i7 + + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) + return 0x301; // Core i3 + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + return 0x601; // Core i5 + return 0x0701; // Core i7 + + case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS) + case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + return 0x0701; // Core i7 + case 0x19: // Intel Core i5 650 @3.20 Ghz - case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ??? - return 0x0601; - case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm) - return 0x0301; - case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core - case 0x2E: // Intel Core i7 LGA1366 (45nm) 6 Core ??? - return 0x0601; + return 0x601; // Core i5 } } } @@ -354,28 +437,28 @@ struct smbios_property smbios_properties[]= { - {.name="SMbiosvendor", .table_type= 0, .value_type=SMSTRING, .offset=0x04, .auto_str=sm_get_defstr }, - {.name="SMbiosversion", .table_type= 0, .value_type=SMSTRING, .offset=0x05, .auto_str=sm_get_defstr }, - {.name="SMbiosdate", .table_type= 0, .value_type=SMSTRING, .offset=0x08, .auto_str=sm_get_defstr }, - {.name="SMmanufacter", .table_type= 1, .value_type=SMSTRING, .offset=0x04, .auto_str=sm_get_defstr }, - {.name="SMproductname", .table_type= 1, .value_type=SMSTRING, .offset=0x05, .auto_str=sm_get_defstr }, - {.name="SMsystemversion", .table_type= 1, .value_type=SMSTRING, .offset=0x06, .auto_str=sm_get_defstr }, - {.name="SMserial", .table_type= 1, .value_type=SMSTRING, .offset=0x07, .auto_str=sm_get_defstr }, - {.name="SMUUID", .table_type= 1, .value_type=SMOWORD, .offset=0x08, .auto_oword=0 }, - {.name="SMfamily", .table_type= 1, .value_type=SMSTRING, .offset=0x1a, .auto_str=sm_get_defstr }, - {.name="SMboardmanufacter", .table_type= 2, .value_type=SMSTRING, .offset=0x04, .auto_str=sm_get_defstr }, - {.name="SMboardproduct", .table_type= 2, .value_type=SMSTRING, .offset=0x05, .auto_str=sm_get_defstr }, - {.name="SMexternalclock", .table_type= 4, .value_type=SMWORD, .offset=0x12, .auto_int=sm_get_fsb }, - {.name="SMmaximalclock", .table_type= 4, .value_type=SMWORD, .offset=0x14, .auto_int=sm_get_cpu }, - {.name="SMmemdevloc", .table_type=17, .value_type=SMSTRING, .offset=0x10, .auto_str=0 }, - {.name="SMmembankloc", .table_type=17, .value_type=SMSTRING, .offset=0x11, .auto_str=0 }, - {.name="SMmemtype", .table_type=17, .value_type=SMBYTE, .offset=0x12, .auto_int=sm_get_memtype}, - {.name="SMmemspeed", .table_type=17, .value_type=SMWORD, .offset=0x15, .auto_int=sm_get_memspeed}, - {.name="SMmemmanufacter", .table_type=17, .value_type=SMSTRING, .offset=0x17, .auto_str=sm_get_memvendor}, - {.name="SMmemserial", .table_type=17, .value_type=SMSTRING, .offset=0x18, .auto_str=sm_get_memserial}, - {.name="SMmempart", .table_type=17, .value_type=SMSTRING, .offset=0x1A, .auto_str=sm_get_mempartno}, - {.name="SMcputype", .table_type=131,.value_type=SMWORD, .offset=0x04, .auto_int=sm_get_cputype}, - {.name="SMbusspeed", .table_type=132,.value_type=SMWORD, .offset=0x04, .auto_int=sm_get_bus_speed} + {.name="SMbiosvendor", .table_type= 0, .value_type=SMSTRING, .offset=0x04, .auto_str=sm_get_defstr }, + {.name="SMbiosversion", .table_type= 0, .value_type=SMSTRING, .offset=0x05, .auto_str=sm_get_defstr }, + {.name="SMbiosdate", .table_type= 0, .value_type=SMSTRING, .offset=0x08, .auto_str=sm_get_defstr }, + {.name="SMmanufacter", .table_type= 1, .value_type=SMSTRING, .offset=0x04, .auto_str=sm_get_defstr }, + {.name="SMproductname", .table_type= 1, .value_type=SMSTRING, .offset=0x05, .auto_str=sm_get_defstr }, + {.name="SMsystemversion", .table_type= 1, .value_type=SMSTRING, .offset=0x06, .auto_str=sm_get_defstr }, + {.name="SMserial", .table_type= 1, .value_type=SMSTRING, .offset=0x07, .auto_str=sm_get_defstr }, + {.name="SMUUID", .table_type= 1, .value_type=SMOWORD, .offset=0x08, .auto_oword=0 }, + {.name="SMfamily", .table_type= 1, .value_type=SMSTRING, .offset=0x1a, .auto_str=sm_get_defstr }, + {.name="SMboardmanufacter", .table_type= 2, .value_type=SMSTRING, .offset=0x04, .auto_str=sm_get_defstr }, + {.name="SMboardproduct", .table_type= 2, .value_type=SMSTRING, .offset=0x05, .auto_str=sm_get_defstr }, + {.name="SMexternalclock", .table_type= 4, .value_type=SMWORD, .offset=0x12, .auto_int=sm_get_fsb }, + {.name="SMmaximalclock", .table_type= 4, .value_type=SMWORD, .offset=0x14, .auto_int=sm_get_cpu }, + {.name="SMmemdevloc", .table_type=17, .value_type=SMSTRING, .offset=0x10, .auto_str=0 }, + {.name="SMmembankloc", .table_type=17, .value_type=SMSTRING, .offset=0x11, .auto_str=0 }, + {.name="SMmemtype", .table_type=17, .value_type=SMBYTE, .offset=0x12, .auto_int=sm_get_memtype }, + {.name="SMmemspeed", .table_type=17, .value_type=SMWORD, .offset=0x15, .auto_int=sm_get_memspeed }, + {.name="SMmemmanufacter", .table_type=17, .value_type=SMSTRING, .offset=0x17, .auto_str=sm_get_memvendor }, + {.name="SMmemserial", .table_type=17, .value_type=SMSTRING, .offset=0x18, .auto_str=sm_get_memserial }, + {.name="SMmempart", .table_type=17, .value_type=SMSTRING, .offset=0x1A, .auto_str=sm_get_mempartno }, + {.name="SMcputype", .table_type=131,.value_type=SMWORD, .offset=0x04, .auto_int=sm_get_cputype }, + {.name="SMbusspeed", .table_type=132,.value_type=SMWORD, .offset=0x04, .auto_int=sm_get_bus_speed } }; struct smbios_table_description smbios_table_descriptions[]= Index: branches/azimutz/CleanCut/i386/libsaio/cpu.c =================================================================== --- branches/azimutz/CleanCut/i386/libsaio/cpu.c (revision 322) +++ branches/azimutz/CleanCut/i386/libsaio/cpu.c (revision 323) @@ -120,6 +120,8 @@ } #endif p->CPU.Vendor = p->CPU.CPUID[CPUID_0][1]; + p->CPU.Signature = p->CPU.CPUID[CPUID_1][0]; + p->CPU.Stepping = bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); p->CPU.Model = bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); p->CPU.Family = bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); p->CPU.ExtModel = bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); @@ -128,7 +130,37 @@ p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1; p->CPU.Model += (p->CPU.ExtModel << 4); - + + /* get brand string (if supported) */ + /* Copyright: from Apple's XNU cpuid.c */ + if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) { + uint32_t reg[4]; + char str[128], *s; + /* + * The brand string 48 bytes (max), guaranteed to + * be NUL terminated. + */ + do_cpuid(0x80000002, reg); + bcopy((char *)reg, &str[0], 16); + do_cpuid(0x80000003, reg); + bcopy((char *)reg, &str[16], 16); + do_cpuid(0x80000004, reg); + bcopy((char *)reg, &str[32], 16); + for (s = str; *s != '\0'; s++) { + if (*s != ' ') break; + } + + strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString)); + + if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) { + /* + * This string means we have a firmware-programmable brand string, + * and the firmware couldn't figure out what sort of CPU we have. + */ + p->CPU.BrandString[0] = '\0'; + } + } + /* setup features */ if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) { p->CPU.Features |= CPU_FEATURE_MMX; Index: branches/azimutz/CleanCut/i386/libsaio/platform.h =================================================================== --- branches/azimutz/CleanCut/i386/libsaio/platform.h (revision 322) +++ branches/azimutz/CleanCut/i386/libsaio/platform.h (revision 323) @@ -14,31 +14,43 @@ extern void dumpPhysAddr(const char * title, void * a, int len); /* CPUID index into cpuid_raw */ -#define CPUID_0 0 -#define CPUID_1 1 -#define CPUID_2 2 -#define CPUID_3 3 -#define CPUID_4 4 -#define CPUID_80 5 -#define CPUID_81 6 -#define CPUID_MAX 7 +#define CPUID_0 0 +#define CPUID_1 1 +#define CPUID_2 2 +#define CPUID_3 3 +#define CPUID_4 4 +#define CPUID_80 5 +#define CPUID_81 6 +#define CPUID_MAX 7 +#define CPU_MODEL_YONAH 0x0E +#define CPU_MODEL_MEROM 0x0F +#define CPU_MODEL_PENRYN 0x17 +#define CPU_MODEL_NEHALEM 0x1A +#define CPU_MODEL_ATOM 0x1C +#define CPU_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper +#define CPU_MODEL_DALES 0x1F // Havendale, Auburndale +#define CPU_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale +#define CPU_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS +#define CPU_MODEL_NEHALEM_EX 0x2E +#define CPU_MODEL_WESTMERE_EX 0x2F + /* CPU Features */ -#define CPU_FEATURE_MMX 0x00000001 // MMX Instruction Set -#define CPU_FEATURE_SSE 0x00000002 // SSE Instruction Set -#define CPU_FEATURE_SSE2 0x00000004 // SSE2 Instruction Set -#define CPU_FEATURE_SSE3 0x00000008 // SSE3 Instruction Set -#define CPU_FEATURE_SSE41 0x00000010 // SSE41 Instruction Set -#define CPU_FEATURE_SSE42 0x00000020 // SSE42 Instruction Set -#define CPU_FEATURE_EM64T 0x00000040 // 64Bit Support -#define CPU_FEATURE_HTT 0x00000080 // HyperThreading -#define CPU_FEATURE_MOBILE 0x00000100 // Mobile CPU -#define CPU_FEATURE_MSR 0x00000200 // MSR Support +#define CPU_FEATURE_MMX 0x00000001 // MMX Instruction Set +#define CPU_FEATURE_SSE 0x00000002 // SSE Instruction Set +#define CPU_FEATURE_SSE2 0x00000004 // SSE2 Instruction Set +#define CPU_FEATURE_SSE3 0x00000008 // SSE3 Instruction Set +#define CPU_FEATURE_SSE41 0x00000010 // SSE41 Instruction Set +#define CPU_FEATURE_SSE42 0x00000020 // SSE42 Instruction Set +#define CPU_FEATURE_EM64T 0x00000040 // 64Bit Support +#define CPU_FEATURE_HTT 0x00000080 // HyperThreading +#define CPU_FEATURE_MOBILE 0x00000100 // Mobile CPU +#define CPU_FEATURE_MSR 0x00000200 // MSR Support /* SMBIOS Memory Types */ -#define SMB_MEM_TYPE_UNDEFINED 0 +#define SMB_MEM_TYPE_UNDEFINED 0 #define SMB_MEM_TYPE_OTHER 1 -#define SMB_MEM_TYPE_UNKNOWN 2 +#define SMB_MEM_TYPE_UNKNOWN 2 #define SMB_MEM_TYPE_DRAM 3 #define SMB_MEM_TYPE_EDRAM 4 #define SMB_MEM_TYPE_VRAM 5 @@ -57,13 +69,13 @@ #define SMB_MEM_TYPE_DDR 18 #define SMB_MEM_TYPE_DDR2 19 #define SMB_MEM_TYPE_FBDIMM 20 -#define SMB_MEM_TYPE_DDR3 24 // Supported in 10.5.6+ AppleSMBIOS +#define SMB_MEM_TYPE_DDR3 24 // Supported in 10.5.6+ AppleSMBIOS /* Memory Configuration Types */ -#define SMB_MEM_CHANNEL_UNKNOWN 0 -#define SMB_MEM_CHANNEL_SINGLE 1 -#define SMB_MEM_CHANNEL_DUAL 2 -#define SMB_MEM_CHANNEL_TRIPLE 3 +#define SMB_MEM_CHANNEL_UNKNOWN 0 +#define SMB_MEM_CHANNEL_SINGLE 1 +#define SMB_MEM_CHANNEL_DUAL 2 +#define SMB_MEM_CHANNEL_TRIPLE 3 /* Maximum number of ram slots */ #define MAX_RAM_SLOTS 8 @@ -73,63 +85,69 @@ #define MAX_SPD_SIZE 256 /* Size of SMBIOS UUID in bytes */ -#define UUID_LEN 16 +#define UUID_LEN 16 -typedef struct _RamSlotInfo_t { - uint32_t ModuleSize; // Size of Module in MB - uint32_t Frequency; // in Mhz - const char* Vendor; - const char* PartNo; - const char* SerialNo; - char* spd; // SPD Dump - bool InUse; - uint8_t Type; - uint8_t BankConnections; // table type 6, see (3.3.7) - uint8_t BankConnCnt; - +typedef struct _RamSlotInfo_t +{ + uint32_t ModuleSize; // Size of Module in MB + uint32_t Frequency; // in Mhz + const char* Vendor; + const char* PartNo; + const char* SerialNo; + char* spd; // SPD Dump + bool InUse; + uint8_t Type; + uint8_t BankConnections; // table type 6, see (3.3.7) + uint8_t BankConnCnt; } RamSlotInfo_t; -typedef struct _PlatformInfo_t { - struct CPU { - uint32_t Features; // CPU Features like MMX, SSE2, VT, MobileCPU - uint32_t Vendor; // Vendor - uint32_t Model; // Model - uint32_t ExtModel; // Extended Model - uint32_t Family; // Family - uint32_t ExtFamily; // Extended Family - uint32_t NoCores; // No Cores per Package - uint32_t NoThreads; // Threads per Package - uint8_t MaxCoef; // Max Multiplier - uint8_t MaxDiv; - uint8_t CurrCoef; // Current Multiplier - uint8_t CurrDiv; - uint64_t TSCFrequency; // TSC Frequency Hz - uint64_t FSBFrequency; // FSB Frequency Hz - uint64_t CPUFrequency; // CPU Frequency Hz - uint32_t BrandString[16]; // 48 Byte Branding String - uint32_t CPUID[CPUID_MAX][4]; // CPUID 0..4, 80..81 Raw Values +typedef struct _PlatformInfo_t +{ + struct CPU + { + uint32_t Features; // CPU Features like MMX, SSE2, VT, MobileCPU + uint32_t Vendor; // Vendor + uint32_t Signature; // Signature + uint32_t Stepping; // Stepping + uint32_t Model; // Model + uint32_t ExtModel; // Extended Model + uint32_t Family; // Family + uint32_t ExtFamily; // Extended Family + uint32_t NoCores; // No Cores per Package + uint32_t NoThreads; // Threads per Package + uint8_t MaxCoef; // Max Multiplier + uint8_t MaxDiv; + uint8_t CurrCoef; // Current Multiplier + uint8_t CurrDiv; + uint64_t TSCFrequency; // TSC Frequency Hz + uint64_t FSBFrequency; // FSB Frequency Hz + uint64_t CPUFrequency; // CPU Frequency Hz + char BrandString[48]; // 48 Byte Branding String + uint32_t CPUID[CPUID_MAX][4]; // CPUID 0..4, 80..81 Raw Values } CPU; - struct RAM { - uint64_t Frequency; // Ram Frequency - uint32_t Divider; // Memory divider - uint8_t CAS; // CAS 1/2/2.5/3/4/5/6/7 - uint8_t TRC; - uint8_t TRP; - uint8_t RAS; - uint8_t Channels; // Channel Configuration Single,Dual or Triple - uint8_t NoSlots; // Maximum no of slots available - uint8_t Type; // Standard SMBIOS v2.5 Memory Type - RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot + struct RAM + { + uint64_t Frequency; // Ram Frequency + uint32_t Divider; // Memory divider + uint8_t CAS; // CAS 1/2/2.5/3/4/5/6/7 + uint8_t TRC; + uint8_t TRP; + uint8_t RAS; + uint8_t Channels; // Channel Configuration Single,Dual or Triple + uint8_t NoSlots; // Maximum no of slots available + uint8_t Type; // Standard SMBIOS v2.5 Memory Type + RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot } RAM; - struct DMI { - int MaxMemorySlots; // number of memory slots polulated by SMBIOS - int CntMemorySlots; // number of memory slots counted - int MemoryModules; // number of memory modules installed - int DIMM[MAX_RAM_SLOTS]; // Information and SPD mapping for each slot + struct DMI + { + int MaxMemorySlots; // number of memory slots polulated by SMBIOS + int CntMemorySlots; // number of memory slots counted + int MemoryModules; // number of memory modules installed + int DIMM[MAX_RAM_SLOTS]; // Information and SPD mapping for each slot } DMI; - uint8_t Type; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile) + uint8_t Type; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile) } PlatformInfo_t; extern PlatformInfo_t Platform; Index: branches/azimutz/CleanCut/i386/libsaio/cpu.h =================================================================== --- branches/azimutz/CleanCut/i386/libsaio/cpu.h (revision 322) +++ branches/azimutz/CleanCut/i386/libsaio/cpu.h (revision 323) @@ -14,6 +14,8 @@ #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1)) #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l) +#define CPU_STRING_UNKNOWN "Unknown CPU Type" + #define MSR_IA32_PERF_STATUS 0x198 #define MSR_IA32_PERF_CONTROL 0x199 #define MSR_IA32_EXT_CONFIG 0x00EE