Index: branches/meklort/i386/libsaio/platform.c
===================================================================
--- branches/meklort/i386/libsaio/platform.c	(revision 541)
+++ branches/meklort/i386/libsaio/platform.c	(revision 542)
@@ -22,17 +22,12 @@
 #define DBG(x...)
 #endif
 
-PlatformInfo_t    Platform;
-pci_dt_t * dram_controller_dev = NULL;
+PlatformInfo_t*    Platform;
 
 /** Return if a CPU feature specified by feature is activated (true) or not (false)  */
-bool platformCPUFeature(uint32_t feature)
+inline bool platformCPUFeature(uint32_t feature)
 {
-	if (Platform.CPU.Features & feature) {
-		return true;
-	} else {
-		return false;
-	}
+	return (Platform->CPU.Features & feature);
 }
 
 /** scan mem for memory autodection purpose */
@@ -56,7 +51,8 @@
     _before_ bootConfig xml parsing settings are loaded
 */
 void scan_platform(void)
-{
+{	
+	Platform = malloc(sizeof(Platform));
 	memset(&Platform, 0, sizeof(Platform));
 	build_pci_dt();
 	scan_cpu(&Platform);
Index: branches/meklort/i386/libsaio/cpu.c
===================================================================
--- branches/meklort/i386/libsaio/cpu.c	(revision 541)
+++ branches/meklort/i386/libsaio/cpu.c	(revision 542)
@@ -162,34 +162,16 @@
 	}
 	
 	/* setup features */
-	if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_MMX;
-	}
-	if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_SSE;
-	}
-	if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_SSE2;
-	}
-	if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_SSE3;
-	}
-	if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_SSE41;
-	}
-	if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_SSE42;
-	}
-	if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_EM64T;
-	}
-	if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {
-		p->CPU.Features |= CPU_FEATURE_MSR;
-	}
-	//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {
+	p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR) & p->CPU.CPUID[CPUID_1][3];
+	p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42) & p->CPU.CPUID[CPUID_1][2];	
+	p->CPU.Features |= (CPU_FEATURE_EM64T) & p->CPU.CPUID[CPUID_81][3];
+
+
+	//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {
 	if (p->CPU.NoThreads > p->CPU.NoCores) {
 		p->CPU.Features |= CPU_FEATURE_HTT;
 	}
+	 
 
 	tscFrequency = measure_tsc_frequency();
 	fsbFrequency = 0;
Index: branches/meklort/i386/libsaio/platform.h
===================================================================
--- branches/meklort/i386/libsaio/platform.h	(revision 541)
+++ branches/meklort/i386/libsaio/platform.h	(revision 542)
@@ -13,6 +13,11 @@
 extern void scan_platform(void);
 extern void dumpPhysAddr(const char * title, void * a, int len);
 
+#define bit(n)			(1UL << (n))
+#define bitmask(h,l)		((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
+#define bitfield(x,h,l)		(((x) & bitmask(h,l)) >> l)
+
+
 /* CPUID index into cpuid_raw */
 #define CPUID_0				0
 #define CPUID_1				1
@@ -36,17 +41,20 @@
 #define CPU_MODEL_WESTMERE_EX	0x2F
 
 /* CPU Features */
-#define CPU_FEATURE_MMX			0x00000001		// MMX Instruction Set
-#define CPU_FEATURE_SSE			0x00000002		// SSE Instruction Set
-#define CPU_FEATURE_SSE2		0x00000004		// SSE2 Instruction Set
-#define CPU_FEATURE_SSE3		0x00000008		// SSE3 Instruction Set
-#define CPU_FEATURE_SSE41		0x00000010		// SSE41 Instruction Set
-#define CPU_FEATURE_SSE42		0x00000020		// SSE42 Instruction Set
-#define CPU_FEATURE_EM64T		0x00000040		// 64Bit Support
-#define CPU_FEATURE_HTT			0x00000080		// HyperThreading
-#define CPU_FEATURE_MOBILE		0x00000100		// Mobile CPU
-#define CPU_FEATURE_MSR			0x00000200		// MSR Support
+// NOTE: Theses are currently mapped to the actual bit in the cpuid value
+#define CPU_FEATURE_MMX			bit(23)		// MMX Instruction Set
+#define CPU_FEATURE_SSE			bit(25)		// SSE Instruction Set
+#define CPU_FEATURE_SSE2		bit(26)		// SSE2 Instruction Set
+#define CPU_FEATURE_SSE3		bit(0)		// SSE3 Instruction Set
+#define CPU_FEATURE_SSE41		bit(19)		// SSE41 Instruction Set
+#define CPU_FEATURE_SSE42		bit(20)		// SSE42 Instruction Set
+#define CPU_FEATURE_EM64T		bit(29)		// 64Bit Support
+#define CPU_FEATURE_HTT			bit(28)		// HyperThreading
+#define CPU_FEATURE_MSR			bit(5)		// MSR Support
+// NOTE: Determine correc tbit for bellow
+#define CPU_FEATURE_MOBILE		bit(1)		// Mobile CPU
 
+
 /* SMBIOS Memory Types */ 
 #define SMB_MEM_TYPE_UNDEFINED	0
 #define SMB_MEM_TYPE_OTHER		1
@@ -146,6 +154,6 @@
 	uint8_t				Type;			// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
 } PlatformInfo_t;
 
-extern PlatformInfo_t Platform;
+extern PlatformInfo_t* Platform;
 
 #endif /* !__LIBSAIO_PLATFORM_H */