Index: branches/valv/i386/libsaio/hfs.c =================================================================== --- branches/valv/i386/libsaio/hfs.c (revision 697) +++ branches/valv/i386/libsaio/hfs.c (revision 698) @@ -303,7 +303,15 @@ /*if (strstr(filePath, ".plist")) verbose("LoadConfig: [%s/%s] %d bytes.\n", devStr, filePath, (uint32_t)length);*/ if (strstr(filePath, "com.apple.Boot.plist")) verbose("Config: [%s/%s] %d bytes.\n", devStr, filePath, (uint32_t)length); - if (strstr(filePath, "theme.plist")) verbose("Theme: [%s].\n", devStr); + if (strstr(filePath, "theme.plist")) + { + //valv: inspired from toitione's rtrim + int t_len = strlen(filePath) - 12; + char *themePath = strncpy(malloc(t_len + 1), filePath, t_len); + themePath[t_len+1] = '\0'; + verbose("Theme: [%s]/%s\n", devStr, themePath); + } +// if (strstr(filePath, "theme.plist")) verbose("Theme: [%s].\n", devStr); if (strstr(filePath, "smbios.plist")) verbose("SMBios: [%s/%s] %d bytes.\n", devStr, filePath, (uint32_t)length); if (strstr(filePath, ".aml")) verbose("ACPI: [%s/%s] %d bytes.\n", devStr, filePath, (uint32_t)length); return length; Index: branches/valv/i386/libsaio/acpi_patcher.c =================================================================== --- branches/valv/i386/libsaio/acpi_patcher.c (revision 697) +++ branches/valv/i386/libsaio/acpi_patcher.c (revision 698) @@ -318,6 +318,16 @@ struct aml_chunk* root = aml_create_node(NULL); aml_add_buffer(root, ssdt_header, sizeof(ssdt_header)); // SSDT header struct aml_chunk* scop = aml_add_scope(root, "\\_PR_"); + + struct aml_chunk* name_csd = aml_add_name(scop, "CSD_"); + struct aml_chunk* pack_csd = aml_add_package(name_csd); + struct aml_chunk* csd = aml_add_package(pack_csd); + aml_add_byte(csd, 0x05); + aml_add_byte(csd, 0x00); + aml_add_dword(csd, 0x00); + aml_add_dword(csd, 0xfd); + aml_add_dword(csd, Platform.CPU.NoCores); + struct aml_chunk* name = aml_add_name(scop, "CST_"); struct aml_chunk* pack = aml_add_package(name); aml_add_byte(pack, cstates_count); @@ -368,12 +378,13 @@ aml_add_word(tmpl, 0x015e); // Power verbose ("C6"); } - verbose("\n"); + //verbose("\n"); break; case 0x1C: // Atom (45nm) - case 0x26: // Atom Lincroft + //valv: was 0x26 ??? rely on cpu.c & smbios_patcher.c + case 0x27: // Atom Lincroft // C1 cstate_resource_template[11] = 0x00; // C1-Atom @@ -430,7 +441,7 @@ aml_add_word(tmpl, 0x0096); // Power verbose ("C6 "); } - verbose("\n"); + //verbose("\n"); break; @@ -492,7 +503,7 @@ aml_add_word(tmpl, 0x0096); // Power 150 verbose ("C6"); } - verbose("\n"); + //verbose("\n"); break; } @@ -521,12 +532,11 @@ ssdt->Checksum = 0; ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length); + verbose (" @ %x\n", ssdt); aml_destroy_node(root); //dumpPhysAddr("C-States SSDT content: ", ssdt, ssdt->Length); - //verbose ("SSDT with CPU C-States generated successfully\n"); - return ssdt; } else @@ -788,10 +798,10 @@ if (p_states_count > 0) { int i; - //valv: fix p-states number issue for some models. TODO: move to top + //valv: fix p-states number issue on some models. + verbose("Model detected: %s\n", MacProduct); if(!strstr(MacProduct, "applemac2010")) { - verbose("Model detected: %s\n", MacProduct); if(strstr(MacProduct, "MacBookPro4,1") && ((p_states_count > 9) && ((pstart == 0) && (pstates == 0)))) pstates = 8; if(strstr(MacProduct, "MacBookAir1,1") && ((p_states_count > 4) && ((pstart == 0) && (pstates == 0)))) pstates = 3; } @@ -808,12 +818,13 @@ aml_add_byte(psd, 0x05); aml_add_byte(psd, 0x00); aml_add_dword(psd, 0x00); - aml_add_dword(psd, 0xfc); + aml_add_dword(psd, 0xfd); aml_add_dword(psd, Platform.CPU.NoCores); struct aml_chunk* name_pss = aml_add_name(scop, "PSS_"); struct aml_chunk* pack_pss = aml_add_package(name_pss); + uint8_t p_states_num = 0; for (i = pstart; i < p_states_count; i++) { if ((p_states[i].Frequency <= freq_max) && (p_states[i].Frequency >= freq_min)) @@ -821,9 +832,9 @@ //valv: inspired from cparm's pss-drop; coded by me ;) if ((i > pstates) && (pstates > 0)) { - if(Platform.CPU.ISerie) verbose("P-State: [Frequency %d MHz, FID 0x%x] is the %dth state. Removed!\n", + if(Platform.CPU.ISerie) verbose("P-State: [Frequency %d MHz\tFID 0x%x] is the %dth state. Removed!\n", p_states[i].Frequency, p_states[i].FID, (i+1)); - else verbose("P-State: [Frequency %d MHz, FID 0x%x, VID 0x%x] is the %dth state. Removed!\n", + else verbose("P-State: [Frequency %d MHz\tFID 0x%x \tVID 0x%x] is the %dth state. Removed!\n", p_states[i].Frequency, p_states[i].FID, p_states[i].VID, (i+1)); } else @@ -838,23 +849,24 @@ { aml_add_dword(pstt, p_states[i].FID); aml_add_dword(pstt, p_states[i].FID); - verbose("P-State: Added [Frequency %d MHz, FID 0x%x]\n", p_states[i].Frequency, p_states[i].FID); + verbose("P-State: Added [Frequency %d MHz\tFID 0x%x]\n", p_states[i].Frequency, p_states[i].FID); } else { aml_add_dword(pstt, p_states[i].Control); aml_add_dword(pstt, p_states[i].Control); //aml_add_dword(pstt, i+1); // Status - verbose("P-State: Added [Frequency %d MHz, FID 0x%x, VID 0x%x]\n", + verbose("P-State: Added [Frequency %d MHz\tFID 0x%x \tVID 0x%x]\n", p_states[i].Frequency, p_states[i].FID, p_states[i].VID); } + p_states_num++; } } else { - if(Platform.CPU.ISerie) verbose("P-State: [Frequency %d MHz, FID 0x%x] is over the limit. Removed!\n", + if(Platform.CPU.ISerie) verbose("P-State: [Frequency %d MHz\tFID 0x%x] is over the limit. Removed!\n", p_states[i].Frequency, p_states[i].FID); - else verbose("P-State: [Frequency %d MHz, FID 0x%x, VID 0x%x] is over the limit. Removed!\n", + else verbose("P-State: [Frequency %d MHz\tFID 0x%x \tVID 0x%x] is over the limit. Removed!\n", p_states[i].Frequency, p_states[i].FID, p_states[i].VID); } } @@ -884,11 +896,10 @@ ssdt->Length = root->Size; ssdt->Checksum = 0; ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length); - - aml_destroy_node(root); - - //verbose ("SSDT with CPU P-States generated successfully\n"); + verbose ("P-States: %d states were succefully generated @ %x\n", p_states_num, ssdt); + aml_destroy_node(root); + return ssdt; } } @@ -952,27 +963,55 @@ struct t_state t_states[32]; uint8_t t_states_count = 0, ctrl0 = 0x10, j = 0x01; int i, step; + uint64_t msr; + uint32_t ext_mod; // *ret = 0; - if(!fadt->DUTY_WIDTH) + do_cpuid(6, Platform.CPU.CPUID[CPUID_81]); + ext_mod = bitfield(Platform.CPU.CPUID[CPUID_81][0], 5, 5); + + if(ext_mod == 1) { verbose("T-States: Unsupported CPU !!!\n"); return NULL; } - verbose("T-States: duty_offset=%d, duty_width=%d", fadt->DUTY_OFFSET, fadt->DUTY_WIDTH); + msr = rdmsr64(MSR_IA32_CLOCK_MODULATION); + t_states_count = msr & 0xE; + + //if(!fadt->DUTY_WIDTH) + if(t_states_count == 0) + { + verbose("T-States: Unsupported CPU !!!\n"); + return NULL; + } +/* + verbose("T-States: duty_offset=%d, duty_width=%d\n", fadt->DUTY_OFFSET, fadt->DUTY_WIDTH); uint8_t duty_cycle = fadt->DUTY_WIDTH + fadt->DUTY_OFFSET; - if (duty_cycle > 4) + if(duty_cycle > 4) { - verbose(", Spanning bit 4"); - //return NULL; - t_states_count = 8; + verbose("T-States: Spanning bit 4\n"); + for (i=2; i<21; i++) + { + if(duty_cycle > 4) + { + verbose("duty_cycle: %d\n", duty_cycle); + sleep(i); + i++; + } + //return NULL; + else + { + t_states_count = 8; + goto nrx; + } + } } else t_states_count = 1 << fadt->DUTY_WIDTH; - + + nrx: +*/ step = (1000 / t_states_count); - verbose("\nT-States: step=%d\n", step); - for (i = 1; i < t_states_count; i++) { t_states[i].perf = (1000 - (step * i)) / 10; @@ -1020,7 +1059,7 @@ aml_add_byte(tsd, 0x05); aml_add_byte(tsd, 0x00); aml_add_dword(tsd, 0x00); - aml_add_dword(tsd, 0xfc); + aml_add_dword(tsd, 0xfd); aml_add_dword(tsd, Platform.CPU.NoCores); // Add aliaces @@ -1045,10 +1084,10 @@ ssdt->Length = root->Size; ssdt->Checksum = 0; ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length); - - aml_destroy_node(root); - - verbose ("T-States: %d states were succefully generated\n"); + + verbose ("T-States: step=%d, %d states were succefully generated @ %x\n", step, t_states_count, ssdt); + + aml_destroy_node(root); return ssdt; } @@ -1114,7 +1153,7 @@ return NULL; } - DBG("Table %s read and stored at: %x\n", dirspec, tableAddr); + verbose("Table %s read and stored at: %x\n", dirspec, tableAddr); close (fd); return tableAddr; } @@ -1802,7 +1841,7 @@ else { rsdp_mod->RsdtAddress=0; - printf("RSDT not found or RSDT incorrect\n"); + printf("RSDT not found or incorrect\n"); } if (version) @@ -2154,7 +2193,7 @@ */ rsdp_mod->XsdtAddress=0xffffffffffffffffLL; - verbose("XSDT not found or XSDT incorrect\n"); + verbose("XSDT not found or incorrect\n"); } } Index: branches/valv/i386/libsaio/smbios_patcher.c =================================================================== --- branches/valv/i386/libsaio/smbios_patcher.c (revision 697) +++ branches/valv/i386/libsaio/smbios_patcher.c (revision 698) @@ -319,7 +319,8 @@ case 0x0e: // Core Solo/Duo, "Yonah", 65nm case 0x0f: // Pentium 4, Core 2, Xeon, "Merom", "Conroe", 65nm case 0x17: // Core 2 Extreme, Xeon, "Penryn", "Wolfdale", 45nm - case 0x1c: // Intel Atom, 45nm + case 0x1c: // Intel Atom + case 0x27: // Intel Atom, "Lincroft", 45nm return 0; // TODO: populate bus speed for these processors break; case 0x2f: // Core i7, "Westmere-Ex", 45nm, Hexa-Core @@ -445,7 +446,8 @@ break; case 0x0f: // Pentium 4, Core 2, Xeon, "Merom", "Conroe", 65nm case 0x17: // Core 2 Extreme, Xeon, "Penryn", "Wolfdale", 45nm - case 0x1c: // Intel Atom, 45nm + case 0x1c: // Intel Atom + case 0x27: // Intel Atom, "Lincroft", 45nm default: return sm_get_cores(); } Index: branches/valv/i386/libsaio/dram_controllers.c =================================================================== --- branches/valv/i386/libsaio/dram_controllers.c (revision 697) +++ branches/valv/i386/libsaio/dram_controllers.c (revision 698) @@ -159,7 +159,7 @@ DBG("mch_ratio %d\n", mch_ratio); // Compute RAM Frequency - Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000; + Platform.RAM.Frequency = (Platform.CPU.FSBIFrequency * mch_ratio) / 100000; DBG("ram_fsb %d\n", Platform.RAM.Frequency); @@ -231,7 +231,7 @@ } // Compute RAM Frequency - Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000; + Platform.RAM.Frequency = (Platform.CPU.FSBIFrequency * mch_ratio) / 100000; } @@ -245,7 +245,7 @@ mch_ratio = (mc_dimm_clk_ratio & 0x1F); // Compute RAM Frequency - Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2; + Platform.RAM.Frequency = Platform.CPU.FSBIFrequency * mch_ratio / 2; } /* Index: branches/valv/i386/libsaio/nvidia.c =================================================================== --- branches/valv/i386/libsaio/nvidia.c (revision 697) +++ branches/valv/i386/libsaio/nvidia.c (revision 698) @@ -335,6 +335,7 @@ { 0x10DE060B, "GeForce 9800M GT" }, { 0x10DE060C, "GeForce 8800M GTX" }, { 0x10DE060D, "GeForce 8800 GS" }, + { 0x10DE060F, "GeForce GTX 285M" }, { 0x10DE0610, "GeForce 9600 GSO" }, { 0x10DE0611, "GeForce 8800 GT" }, { 0x10DE0612, "GeForce 9800 GTX" }, @@ -359,9 +360,12 @@ { 0x10DE062C, "GeForce 9800M GTS" }, { 0x10DE062D, "GeForce 9600 GT" }, { 0x10DE062E, "GeForce 9600 GT" }, + { 0x10DE0631, "GeForce GTS 160M" }, + { 0x10DE0632, "GeForce GTS 150M" }, { 0x10DE0635, "GeForce 9600 GSO" }, { 0x10DE0637, "GeForce 9600 GT" }, { 0x10DE0638, "Quadro FX 1800" }, + { 0x10DE063A, "Quadro FX 2700M" }, { 0x10DE0640, "GeForce 9500 GT" }, { 0x10DE0641, "GeForce 9400 GT" }, { 0x10DE0642, "GeForce 8400 GS" }, @@ -375,13 +379,26 @@ { 0x10DE064A, "GeForce 9700M GT" }, { 0x10DE064B, "GeForce 9500M G" }, { 0x10DE064C, "GeForce 9650M GT" }, + { 0x10DE0651, "GeForce G 110M" }, { 0x10DE0652, "GeForce GT 130M" }, + { 0x10DE0653, "GeForce GT 120M" }, + { 0x10DE0654, "GeForce GT 220M" }, + { 0x10DE0656, "GeForce 9650 S" }, { 0x10DE0658, "Quadro FX 380" }, { 0x10DE0659, "Quadro FX 580" }, { 0x10DE065A, "Quadro FX 1700M" }, { 0x10DE065B, "GeForce 9400 GT" }, { 0x10DE065C, "Quadro FX 770M" }, { 0x10DE065F, "GeForce G210" }, + { 0x10DE06C0, "GeForce GTX 480" }, + { 0x10DE06C4, "GeForce GTX 465" }, + { 0x10DE06CA, "GeForce GTX 480M" }, + { 0x10DE06CD, "GeForce GTX 470" }, + { 0x10DE06D1, "Tesla C2050" }, // TODO: sub-device id: 0x0771 + { 0x10DE06D1, "Tesla C2070" }, // TODO: sub-device id: 0x0772 + { 0x10DE06DD, "Quadro 4000" }, + { 0x10DE06DE, "Tesla M2050" }, // TODO: sub-device id: 0x0846 + { 0x10DE06DE, "Tesla M2070" }, // TODO: sub-device id: ? { 0x10DE06E0, "GeForce 9300 GE" }, { 0x10DE06E1, "GeForce 9300 GS" }, { 0x10DE06E2, "GeForce 8400" }, @@ -399,12 +416,15 @@ { 0x10DE06F8, "Quadro NVS 420" }, { 0x10DE06F9, "Quadro FX 370 LP" }, { 0x10DE06FA, "Quadro NVS 450" }, + { 0x10DE06FB, "Quadro FX 370M" }, { 0x10DE06FD, "Quadro NVS 295" }, { 0x10DE07E0, "GeForce 7150 / nForce 630i" }, { 0x10DE07E1, "GeForce 7100 / nForce 630i" }, { 0x10DE07E2, "GeForce 7050 / nForce 630i" }, { 0x10DE07E3, "GeForce 7050 / nForce 610i" }, { 0x10DE07E5, "GeForce 7050 / nForce 620i" }, + { 0x10DE0844, "GeForce 9100M G" }, + { 0x10DE0845, "GeForce 8200M G" }, { 0x10DE0846, "GeForce 9200" }, { 0x10DE0847, "GeForce 9100" }, { 0x10DE0848, "GeForce 8300" }, @@ -416,13 +436,22 @@ { 0x10DE084F, "GeForce 8100 / nForce 720a" }, { 0x10DE0860, "GeForce 9400" }, { 0x10DE0861, "GeForce 9400" }, + { 0x10DE0862, "GeForce 9400M G" }, + { 0x10DE0863, "GeForce 9400M" }, { 0x10DE0864, "GeForce 9300" }, { 0x10DE0865, "ION" }, + { 0x10DE0866, "GeForce 9400M G" }, + { 0x10DE0867, "GeForce 9400" }, { 0x10DE0868, "nForce 760i SLI" }, { 0x10DE086A, "GeForce 9400" }, { 0x10DE086C, "GeForce 9300 / nForce 730i" }, { 0x10DE086D, "GeForce 9200" }, + { 0x10DE086E, "GeForce 9100M G" }, + { 0x10DE086F, "GeForce 8200M G" }, + { 0x10DE0870, "GeForce 9400M" }, { 0x10DE0871, "GeForce 9200" }, + { 0x10DE0872, "GeForce G102M" }, + { 0x10DE0873, "GeForce G102M" }, { 0x10DE0874, "ION" }, { 0x10DE0876, "ION" }, { 0x10DE087A, "GeForce 9400" }, @@ -430,18 +459,38 @@ { 0x10DE087E, "ION LE" }, { 0x10DE087F, "ION LE" }, { 0x10DE0A20, "GeForce GT220" }, + { 0x10DE0A22, "GeForce 315" }, { 0x10DE0A23, "GeForce 210" }, { 0x10DE0A28, "GeForce GT 230M" }, + { 0x10DE0A29, "GeForce GT 330M" }, { 0x10DE0A2A, "GeForce GT 230M" }, + { 0x10DE0A2B, "GeForce GT 330M" }, + { 0x10DE0A2C, "NVS 5100M" }, + { 0x10DE0A2D, "GeForce GT 320M" }, { 0x10DE0A34, "GeForce GT 240M" }, + { 0x10DE0A35, "GeForce GT 325M" }, + { 0x10DE0A3C, "Quadro FX 880M" }, { 0x10DE0A60, "GeForce G210" }, { 0x10DE0A62, "GeForce 205" }, { 0x10DE0A63, "GeForce 310" }, { 0x10DE0A64, "ION" }, { 0x10DE0A65, "GeForce 210" }, { 0x10DE0A66, "GeForce 310" }, + { 0x10DE0A67, "GeForce 315" }, + { 0x10DE0A68, "GeForce G105M" }, + { 0x10DE0A69, "GeForce G105M" }, + { 0x10DE0A6A, "NVS 2100M" }, + { 0x10DE0A6C, "NVS 3100M" }, + { 0x10DE0A6E, "GeForce 305M" }, + { 0x10DE0A6F, "ION" }, + { 0x10DE0A70, "GeForce 310M" }, + { 0x10DE0A71, "GeForce 305M" }, + { 0x10DE0A72, "GeForce 310M" }, + { 0x10DE0A73, "GeForce 305M" }, { 0x10DE0A74, "GeForce G210M" }, + { 0x10DE0A75, "GeForce G310M" }, { 0x10DE0A78, "Quadro FX 380 LP" }, + { 0x10DE0A7C, "Quadro FX 380M" }, { 0x10DE0CA0, "GeForce GT 330 " }, { 0x10DE0CA2, "GeForce GT 320" }, { 0x10DE0CA3, "GeForce GT 240" }, @@ -449,16 +498,11 @@ { 0x10DE0CA7, "GeForce GT 330" }, { 0x10DE0CA8, "GeForce GTS 260M" }, { 0x10DE0CA9, "GeForce GTS 250M" }, - { 0x10DE0CA3, "GeForce GT240" }, - { 0x10DE06C0, "GeForce GTX 480" }, - { 0x10DE06C4, "GeForce GTX 465" }, - { 0x10DE06CA, "GeForce GTX 480M" }, - { 0x10DE06CD, "GeForce GTX 470" }, - { 0x10DE06D1, "Tesla C2050" }, // TODO: sub-device id: 0x0771 - { 0x10DE06D1, "Tesla C2070" }, // TODO: sub-device id: 0x0772 - { 0x10DE06DD, "Quadro 4000" }, - { 0x10DE06DE, "Tesla M2050" }, // TODO: sub-device id: 0x0846 - { 0x10DE06DE, "Tesla M2070" }, // TODO: sub-device id: ? + { 0x10DE0CAC, "GeForce 315" }, + { 0x10DE0CAF, "GeForce GT 335M" }, + { 0x10DE0CB0, "GeForce GTS 350M" }, + { 0x10DE0CB1, "GeForce GT 360M" }, + { 0x10DE0CBC, "Quadro FX 1800M" }, { 0x10DE0DC4, "GeForce GTS 450" }, { 0x10DE0DE1, "GeForce GT 430" }, { 0x10DE0DF0, "GeForce GT 425M" }, Index: branches/valv/i386/libsaio/cpu.c =================================================================== --- branches/valv/i386/libsaio/cpu.c (revision 697) +++ branches/valv/i386/libsaio/cpu.c (revision 698) @@ -98,9 +98,9 @@ { const char *newratio, *newfsb; int len, myfsb, i; - uint64_t tscFrequency, fsbFrequency, cpuFrequency; + uint64_t tscFrequency, fsbFrequency, cpuFrequency, fsbi; uint64_t msr, flex_ratio = 0; - uint32_t tms, ida, max_ratio, min_ratio; + uint32_t tms, ida, amo, max_ratio, min_ratio; uint8_t bus_ratio_max, maxdiv, bus_ratio_min, currdiv; bool fix_fsb, did, core_i, turbo; @@ -187,6 +187,7 @@ tscFrequency = measure_tsc_frequency(); fsbFrequency = 0; cpuFrequency = 0; + fsbi = 0; fix_fsb = false; did = false; core_i = false; @@ -197,7 +198,7 @@ verbose("CPU: "); int tjmax = 0; msr = rdmsr64(MSR_IA32_PLATFORM_ID); - if (((msr >> 50) & 0x01) == 1) + if((((msr >> 50) & 0x01) == 1) || (rdmsr64(0x17) & (1<<28))) { p->CPU.Features |= CPU_FEATURE_MOBILE; verbose("Mobile "); @@ -277,8 +278,10 @@ p->CPU.MaxRatio = max_ratio; p->CPU.MinRatio = min_ratio; + fsbi = fsbFrequency; if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb; break; + case 0xd: // Pentium D; valv: is this the right place ? case 0xe: // Core Duo/Solo, Pentium M DC goto teleport; case 0xf: // Core Xeon, Core 2 DC, 65nm @@ -329,16 +332,21 @@ case 0x16: // Celeron, Core 2 SC, 65nm case 0x27: // Atom Lincroft, 45nm core_i = false; - + //valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2 + //also, if bit 3 of misc_enable is cleared the above would have no effect if(platformCPUFeature(CPU_FEATURE_TM1)) { msr_t msr32; msr32 = rdmsr(MSR_IA32_MISC_ENABLE); + //thermally-initiated on-die modulation of the stop-clock duty cycle if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3); verbose("CPU: Thermal Monitor: TM, "); + + //BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set if(platformCPUFeature(CPU_FEATURE_TM2)) { + //thermally-initiated frequency transitions msr32.lo |= (1 << 13); verbose("TM2, "); } @@ -358,7 +366,7 @@ getBoolForKey(kC2EEnable, &c2e, &bootInfo->bootConfig); if(c2e) msr32.lo |= (1 << 26); - + getBoolForKey(kC4EEnable, &c4e, &bootInfo->bootConfig); if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32)); getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig); @@ -368,6 +376,10 @@ msr32.hi |= (1 << (36 - 32)); // EMTTM wrmsr(MSR_IA32_MISC_ENABLE, msr32); + + msr32 = rdmsr(PIC_SENS_CFG); + msr32.lo |= (1 << 21); + wrmsr(PIC_SENS_CFG, msr32); } if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27)) @@ -490,6 +502,11 @@ if(fix_fsb) { + if (bus_ratio_max) + { + if (maxdiv) fsbi = ((tscFrequency * 2) / ((bus_ratio_max * 2) + 1)); + else fsbi = (tscFrequency / bus_ratio_max); + } ratio_gn: if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4)) { @@ -586,48 +603,88 @@ msr.hi |= (0 << (38-32)); wrmsr(MSR_IA32_MISC_ENABLE, msr); delay(1); - if(bitfield(p->CPU.CPUID[CPUID_81][0], 0, 1) == 0) verbose("Failed!\n"); + if(bitfield(p->CPU.CPUID[CPUID_81][0], 1, 1) == 0) verbose("Failed!\n"); else verbose("Succeded!\n"); } else verbose("CPU: IDA: Enabled!\n"); } } -#if 0 - else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) +//#if 0 + else if(p->CPU.Vendor == 0x68747541 /* AMD */) // valv: work in progress { - if(p->CPU.ExtFamily == 0x00 /* K8 */) + verbose("CPU: "); + // valv: very experimental mobility check + if (p->CPU.CPUID[0x80000000][0] >= 0x80000007) { - msr = rdmsr64(K8_FIDVID_STATUS); - bus_ratio_max = (msr & 0x3f) / 2 + 4; - currdiv = (msr & 0x01) * 2; + do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]); + amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6); + if (amo == 1) + { + p->CPU.Features |= CPU_FEATURE_MOBILE; + if (!strstr(p->CPU.BrandString, "obile")) verbose("Mobile "); + } } - else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) + //valv: 2nd attemp; just in case + if (!platformCPUFeature(CPU_FEATURE_MOBILE)) { - msr = rdmsr64(K10_COFVID_STATUS); - if(p->CPU.ExtFamily == 0x01 /* K10 */) - bus_ratio_max = (msr & 0x3f) + 0x10; - else /* K11+ */ - bus_ratio_max = (msr & 0x3f) + 0x08; - currdiv = (2 << ((msr >> 6) & 0x07)); - } - - p->CPU.MaxRatio = bus_ratio_max * 10; - - if (bus_ratio_max) - { - if (currdiv) + if (strstr(p->CPU.BrandString, "obile")) { - fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); - DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv); + p->CPU.Features |= CPU_FEATURE_MOBILE; } - else - { - fsbFrequency = (tscFrequency / bus_ratio_max); - DBG("%d\n", bus_ratio_max); - } - fsbFrequency = (tscFrequency / bus_ratio_max); - cpuFrequency = tscFrequency; } + verbose("%s\n", p->CPU.BrandString); + int amdCPU = p->CPU.Family; + + switch (amdCPU) + { + case 0x0f: + if(p->CPU.ExtFamily == 0x00 /* K8 */) + { + msr = rdmsr64(K8_FIDVID_STATUS); + bus_ratio_max = (msr & 0x3f) / 2 + 4; + currdiv = (msr & 0x01) * 2; + } + else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) + { + msr = rdmsr64(K10_COFVID_STATUS); + if(p->CPU.ExtFamily == 0x01 /* K10 */) + bus_ratio_max = (msr & 0x3f) + 0x10; + else /* K11+ */ + bus_ratio_max = (msr & 0x3f) + 0x08; + currdiv = (2 << ((msr >> 6) & 0x07)); + } + + p->CPU.MaxRatio = bus_ratio_max * 10; + + if (bus_ratio_max) + { + if (currdiv) + { + fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ? + DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv); + } + else + { + fsbFrequency = (tscFrequency / bus_ratio_max); + DBG("%d\n", bus_ratio_max); + } + fsbFrequency = (tscFrequency / bus_ratio_max); // ? + cpuFrequency = tscFrequency; // ? + } + break; + case 0x10: // phenom + msr = rdmsr64(AMD_10H_11H_CONFIG); + bus_ratio_max = ((msr) & 0x3F); + currdiv = (((msr) >> 6) & 0x07); + cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv); + break; + case 0x11: // shangai + msr = rdmsr64(AMD_10H_11H_CONFIG); + bus_ratio_max = ((msr) & 0x3F); + currdiv = (((msr) >> 6) & 0x07); + cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv); + break; + } } if (!fsbFrequency) @@ -636,8 +693,9 @@ cpuFrequency = tscFrequency; DBG("0 ! using the default value for FSB !\n"); } -#endif +//#endif + p->CPU.MaxDiv = maxdiv; p->CPU.CurrDiv = currdiv; p->CPU.TSCFrequency = tscFrequency; @@ -646,6 +704,9 @@ p->CPU.ISerie = false; p->CPU.Turbo = false; + if(fsbi == 0) p->CPU.FSBIFrequency = fsbFrequency; + else p->CPU.FSBIFrequency = fsbi; + if (platformCPUFeature(CPU_FEATURE_EST)) { msr_t msr32; Index: branches/valv/i386/libsaio/platform.h =================================================================== --- branches/valv/i386/libsaio/platform.h (revision 697) +++ branches/valv/i386/libsaio/platform.h (revision 698) @@ -124,6 +124,7 @@ uint8_t CurrDiv; // Current Halving ID uint64_t TSCFrequency; // TSC Frequency Hz uint64_t FSBFrequency; // FSB Frequency Hz + uint64_t FSBIFrequency; // FSB Frequency Hz (initial) uint64_t CPUFrequency; // CPU Frequency Hz uint32_t MaxRatio; // Max Bus Ratio uint32_t MinRatio; // Min Bus Ratio Index: branches/valv/i386/libsaio/cpu.h =================================================================== --- branches/valv/i386/libsaio/cpu.h (revision 697) +++ branches/valv/i386/libsaio/cpu.h (revision 698) @@ -17,19 +17,22 @@ #define CPU_STRING_UNKNOWN "Unknown CPU Typ" -#define MSR_FSB_FREQ 0xCD -#define MSR_TURBO_RATIO_LIMIT 0x1AD -#define MSR_IA32_PLATFORM_ID 0x17 -#define MSR_IA32_PERF_STATUS 0x198 -#define MSR_IA32_PERF_CONTROL 0x199 -#define MSR_IA32_EXT_CONFIG 0xEE -#define MSR_FLEX_RATIO 0x194 -#define MSR_PLATFORM_INFO 0xCE -#define MSR_IA32_MISC_ENABLE 0x1A0 -#define MSR_THERMAL_STATUS 0x19C -#define MSR_THERMAL_TARGET 0x01A2 -#define K8_FIDVID_STATUS 0xC0010042 -#define K10_COFVID_STATUS 0xC0010071 +#define MSR_FSB_FREQ 0xCD +#define MSR_TURBO_RATIO_LIMIT 0x1AD +#define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_IA32_PERF_STATUS 0x198 +#define MSR_IA32_PERF_CONTROL 0x199 +#define MSR_IA32_EXT_CONFIG 0xEE +#define MSR_FLEX_RATIO 0x194 +#define MSR_PLATFORM_INFO 0xCE +#define MSR_IA32_MISC_ENABLE 0x1A0 +#define MSR_THERMAL_STATUS 0x19C +#define MSR_IA32_CLOCK_MODULATION 0x19A +#define MSR_THERMAL_TARGET 0x01A2 +#define PIC_SENS_CFG 0x1aa +#define K8_FIDVID_STATUS 0xC0010042 +#define AMD_10H_11H_CONFIG 0xc0010064 +#define K10_COFVID_STATUS 0xC0010071 #define DEFAULT_FSB 100000 /* for now, hardcoding 100MHz for old CPUs */ Index: branches/valv/i386/boot2/boot.c =================================================================== --- branches/valv/i386/boot2/boot.c (revision 697) +++ branches/valv/i386/boot2/boot.c (revision 698) @@ -477,7 +477,7 @@ closeVbios(map); } - // Find out which version mac os we're booting. + // Find out which mac os version we're booting. getOSVersion(gMacOSVersion); if (platformCPUFeature(CPU_FEATURE_EM64T)) { Index: branches/valv/revision =================================================================== --- branches/valv/revision (revision 697) +++ branches/valv/revision (revision 698) @@ -1 +1 @@ -665:684 \ No newline at end of file +665:688 \ No newline at end of file