Index: trunk/i386/libsaio/pci.c
===================================================================
--- trunk/i386/libsaio/pci.c	(revision 784)
+++ trunk/i386/libsaio/pci.c	(revision 785)
@@ -84,10 +84,11 @@
 			}
 			new = (pci_dt_t*)malloc(sizeof(pci_dt_t));
 			bzero(new, sizeof(pci_dt_t));
-			new->dev.addr	= pci_addr;
-			new->vendor_id	= id & 0xffff;
-			new->device_id	= (id >> 16) & 0xffff;
-			new->class_id	= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);
+			new->dev.addr				= pci_addr;
+			new->vendor_id				= id & 0xffff;
+			new->device_id				= (id >> 16) & 0xffff;
+			new->subsys_id.subsys_id	= pci_config_read32(pci_addr, PCI_SUBSYSTEM_VENDOR_ID);
+			new->class_id				= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);
 			new->parent	= start;
 
 			header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);
@@ -134,6 +135,7 @@
 	bzero(root_pci_dev, sizeof(pci_dt_t));
 	enable_pci_devs();
 	scan_pci_bus(root_pci_dev, 0);
+
 #if DEBUG_PCI
 	dump_pci_dt(root_pci_dev->children);
 	pause();
@@ -176,9 +178,10 @@
 
 	current = pci_dt;
 	while (current) {
-		printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", 
+		printf("%02x:%02x.%x [%04x] [%04x:%04x] (subsys [%04x:%04x]):: %s\n", 
 			current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, 
 			current->class_id, current->vendor_id, current->device_id, 
+			current->subsys_id.subsys.vendor_id, current->subsys_id.subsys.device_id, 
 			get_pci_dev_path(current));
 		dump_pci_dt(current->children);
 		current = current->next;
Index: trunk/i386/libsaio/pci.h
===================================================================
--- trunk/i386/libsaio/pci.h	(revision 784)
+++ trunk/i386/libsaio/pci.h	(revision 785)
@@ -23,15 +23,24 @@
 } pci_dev_t;
 
 typedef struct pci_dt_t {
-	pci_dev_t		dev;
+	pci_dev_t				dev;
 
-	uint16_t	vendor_id;
-	uint16_t	device_id;
-	uint16_t	class_id;	
+	uint16_t				vendor_id;
+	uint16_t				device_id;
 
-	struct pci_dt_t	*parent;
-	struct pci_dt_t	*children;
-	struct pci_dt_t	*next;
+	union {
+		struct {
+			uint16_t	vendor_id;
+			uint16_t	device_id;
+		}			subsys;
+		uint32_t	subsys_id;
+	}						subsys_id;
+
+	uint16_t				class_id;	
+
+	struct pci_dt_t			*parent;
+	struct pci_dt_t			*children;
+	struct pci_dt_t			*next;
 } pci_dt_t;
 
 #define PCIADDR(bus, dev, func)	(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
@@ -42,32 +51,43 @@
 extern uint8_t		pci_config_read8(uint32_t, uint8_t);
 extern uint16_t		pci_config_read16(uint32_t, uint8_t);
 extern uint32_t		pci_config_read32(uint32_t, uint8_t);
-extern void		pci_config_write8(uint32_t, uint8_t, uint8_t);
-extern void		pci_config_write16(uint32_t, uint8_t, uint16_t);
-extern void		pci_config_write32(uint32_t, uint8_t, uint32_t);
-extern char		*get_pci_dev_path(pci_dt_t *);
-extern void		build_pci_dt(void);
-extern void		dump_pci_dt(pci_dt_t *);
+extern void			pci_config_write8(uint32_t, uint8_t, uint8_t);
+extern void			pci_config_write16(uint32_t, uint8_t, uint16_t);
+extern void			pci_config_write32(uint32_t, uint8_t, uint32_t);
+extern char			*get_pci_dev_path(pci_dt_t *);
+extern void			build_pci_dt(void);
+extern void			dump_pci_dt(pci_dt_t *);
 
+/* Option ROM header */
+typedef struct {
+	uint16_t	signature;		// 0xAA55
+	uint8_t		rom_size;
+	uint32_t	entry_point;
+	uint8_t		reserved[15];
+	uint16_t	pci_header_offset;
+	uint16_t	expansion_header_offset;
+} option_rom_header_t;
+
+/* Option ROM PCI Data Structure */
+typedef struct {
+	uint32_t	signature;		// 0x52494350	'PCIR'
+	uint16_t	vendor_id;
+	uint16_t	device_id;
+	uint16_t	vital_product_data_offset;
+	uint16_t	structure_length;
+	uint8_t		structure_revision;
+	uint8_t		class_code[3];
+	uint16_t	image_length;
+	uint16_t	image_revision;
+	uint8_t		code_type;
+	uint8_t		indicator;
+	uint16_t	reserved;
+} option_rom_pci_header_t;
+
 //-----------------------------------------------------------------------------
 // added by iNDi
 
-struct pci_rom_pci_header_t {
-	uint32_t	signature;			// 0x50434952 'PCIR'
-	uint16_t	vendor;
-	uint16_t	device;
-	uint16_t	product;
-	uint16_t	length;
-	uint8_t		revision;			// 0 = PCI 2.1
-	uint8_t		class[3];
-	uint16_t	rom_size;			
-	uint16_t	code_revision;
-	uint8_t		code_type;			// 0 = x86
-	uint8_t		last_image;			// 0x80
-	uint16_t	reserverd;
-};
-
-struct pci_rom_pnp_header_t {
+typedef struct {
 	uint32_t	signature;			// 0x24506E50 '$PnP'
 	uint8_t		revision;			//  1
 	uint8_t		length;				//
@@ -83,17 +103,8 @@
 	uint16_t	bootstrap_vector;
 	uint16_t	reserved;
 	uint16_t	resource_vector;
-};
+} option_rom_pnp_header_t;
 
-struct pci_rom_bios_t {
-	uint16_t	signature;			// 0x55AA
-	uint8_t		size;				// Multiples of 512
-	
-	uint8_t		checksum;			// 0x00
-	uint16_t	pci_header;
-	uint16_t	pnp_header;
-};
-
 /*
  * Under PCI, each device has 256 bytes of configuration address space,
  * of which the first 64 bytes are standardized as follows: