Index: branches/Chimera/Chameleon.xcodeproj/.svn/all-wcprops =================================================================== --- branches/Chimera/Chameleon.xcodeproj/.svn/all-wcprops (revision 0) +++ branches/Chimera/Chameleon.xcodeproj/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 53 +/svn/chameleon/!svn/ver/829/trunk/Chameleon.xcodeproj +END +project.pbxproj +K 25 +svn:wc:ra_dav:version-url +V 69 +/svn/chameleon/!svn/ver/829/trunk/Chameleon.xcodeproj/project.pbxproj +END Index: branches/Chimera/Chameleon.xcodeproj/.svn/entries =================================================================== --- branches/Chimera/Chameleon.xcodeproj/.svn/entries (revision 0) +++ branches/Chimera/Chameleon.xcodeproj/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/Chameleon.xcodeproj +http://forge.voodooprojects.org/svn/chameleon + + + +2011-05-18T03:13:43.402510Z +829 +mozodojo + + + + + + + + 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branches/Chimera/artwork/.svn/all-wcprops =================================================================== --- branches/Chimera/artwork/.svn/all-wcprops (revision 0) +++ branches/Chimera/artwork/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 41 +/svn/chameleon/!svn/ver/492/trunk/artwork +END Index: branches/Chimera/artwork/.svn/entries =================================================================== --- branches/Chimera/artwork/.svn/entries (revision 0) +++ branches/Chimera/artwork/.svn/entries (revision 850) @@ -0,0 +1,31 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/artwork +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-04T21:31:49.130872Z +492 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +themes +dir + Index: branches/Chimera/artwork/themes/.svn/all-wcprops =================================================================== --- branches/Chimera/artwork/themes/.svn/all-wcprops (revision 0) +++ branches/Chimera/artwork/themes/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 48 +/svn/chameleon/!svn/ver/492/trunk/artwork/themes +END Index: branches/Chimera/artwork/themes/.svn/entries =================================================================== --- branches/Chimera/artwork/themes/.svn/entries (revision 0) +++ branches/Chimera/artwork/themes/.svn/entries (revision 850) @@ -0,0 +1,49 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/artwork/themes +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-04T21:31:49.130872Z +492 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +default +dir + +legacy +dir + +bullet +dir + +pinktink +dir + +msi_netbook +dir + +twilight +dir + +embed +dir + Index: branches/Chimera/artwork/themes/default/.svn/all-wcprops =================================================================== --- branches/Chimera/artwork/themes/default/.svn/all-wcprops (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/all-wcprops (revision 850) @@ -0,0 +1,239 @@ +K 25 +svn:wc:ra_dav:version-url +V 56 +/svn/chameleon/!svn/ver/492/trunk/artwork/themes/default +END +text_scroll_prev.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/text_scroll_prev.png +END +device_hfsraid.png +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_hfsraid.png +END +logo.png +K 25 +svn:wc:ra_dav:version-url +V 65 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/logo.png +END +device_ext3.png +K 25 +svn:wc:ra_dav:version-url +V 72 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_ext3.png +END +menu_single_user.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_single_user.png +END +boot.png +K 25 +svn:wc:ra_dav:version-url +V 65 +/svn/chameleon/!svn/ver/412/trunk/artwork/themes/default/boot.png +END +device_fat_o.png +K 25 +svn:wc:ra_dav:version-url +V 73 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_fat_o.png +END +device_ntfs_o.png +K 25 +svn:wc:ra_dav:version-url +V 74 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_ntfs_o.png +END +device_scroll_prev.png +K 25 +svn:wc:ra_dav:version-url +V 79 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/device_scroll_prev.png +END +menu_ignore_caches.png +K 25 +svn:wc:ra_dav:version-url +V 79 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_ignore_caches.png +END +menu_verbose_disabled.png +K 25 +svn:wc:ra_dav:version-url +V 82 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_verbose_disabled.png +END +device_hfsplus_o.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_hfsplus_o.png +END +menu_boot.png +K 25 +svn:wc:ra_dav:version-url +V 70 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_boot.png +END +font_console.png +K 25 +svn:wc:ra_dav:version-url +V 73 +/svn/chameleon/!svn/ver/412/trunk/artwork/themes/default/font_console.png +END +device_fat.png +K 25 +svn:wc:ra_dav:version-url +V 71 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_fat.png +END +device_ntfs.png +K 25 +svn:wc:ra_dav:version-url +V 72 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_ntfs.png +END +menu_single_user_disabled.png +K 25 +svn:wc:ra_dav:version-url +V 86 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_single_user_disabled.png +END +font_small.png +K 25 +svn:wc:ra_dav:version-url +V 71 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/font_small.png +END +text_scroll_next.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/text_scroll_next.png +END +device_cdrom_o.png +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_cdrom_o.png +END +device_hfsplus.png +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_hfsplus.png +END +menu_ignore_caches_disabled.png +K 25 +svn:wc:ra_dav:version-url +V 88 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_ignore_caches_disabled.png +END +device_selection.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/device_selection.png +END +menu_video_info.png +K 25 +svn:wc:ra_dav:version-url +V 76 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_video_info.png +END +menu_memory_info.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_memory_info.png +END +menu_selection.png +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_selection.png +END +device_generic_o.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_generic_o.png +END +theme.plist +K 25 +svn:wc:ra_dav:version-url +V 68 +/svn/chameleon/!svn/ver/492/trunk/artwork/themes/default/theme.plist +END +device_scroll_next.png +K 25 +svn:wc:ra_dav:version-url +V 79 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/device_scroll_next.png +END +menu_help.png +K 25 +svn:wc:ra_dav:version-url +V 70 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_help.png +END +device_hfsraid_o.png +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_hfsraid_o.png +END +background.png +K 25 +svn:wc:ra_dav:version-url +V 69 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/default/background.png +END +thumb.png +K 25 +svn:wc:ra_dav:version-url +V 66 +/svn/chameleon/!svn/ver/473/trunk/artwork/themes/default/thumb.png +END +device_ext3_o.png +K 25 +svn:wc:ra_dav:version-url +V 74 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_ext3_o.png +END +device_cdrom.png +K 25 +svn:wc:ra_dav:version-url +V 73 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_cdrom.png +END +progress_bar_background.png +K 25 +svn:wc:ra_dav:version-url +V 84 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/progress_bar_background.png +END +progress_bar.png +K 25 +svn:wc:ra_dav:version-url +V 73 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/progress_bar.png +END +menu_verbose.png +K 25 +svn:wc:ra_dav:version-url +V 73 +/svn/chameleon/!svn/ver/405/trunk/artwork/themes/default/menu_verbose.png +END +device_generic.png +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/475/trunk/artwork/themes/default/device_generic.png +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_ext3_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_ext3_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_ext3_o.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsplus_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsplus_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsplus_o.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_boot.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_boot.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/progress_bar.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/progress_bar.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/progress_bar.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_fat.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_fat.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_fat.png.svn-base (revision 850) @@ -0,0 +1,9 @@ +K 14 +svn:executable +V 1 +* +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_ntfs.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_ntfs.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_ntfs.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/text_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/text_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/text_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/logo.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_cdrom_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_cdrom_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_cdrom_o.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_ext3.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_ext3.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_ext3.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsplus.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsplus.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsplus.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_video_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_video_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_video_info.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_memory_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_memory_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_memory_info.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_selection.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_generic_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_generic_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_generic_o.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_scroll_next.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_scroll_next.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_scroll_next.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsraid_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsraid_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsraid_o.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/thumb.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/thumb.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/thumb.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/background.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/background.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/background.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_verbose_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_verbose_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_verbose_disabled.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_cdrom.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_cdrom.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_cdrom.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/progress_bar_background.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/progress_bar_background.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/progress_bar_background.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/font_console.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/font_console.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/font_console.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_verbose.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_verbose.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_verbose.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_single_user_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_single_user_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_single_user_disabled.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_generic.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_generic.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_generic.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/font_small.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/font_small.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/font_small.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsraid.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsraid.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_hfsraid.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/text_scroll_next.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/text_scroll_next.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/text_scroll_next.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/boot.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/boot.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_single_user.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_single_user.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_single_user.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_ignore_caches_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/menu_ignore_caches_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/menu_ignore_caches_disabled.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_selection.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_fat_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_fat_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_fat_o.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_ntfs_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_ntfs_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_ntfs_o.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/device_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/prop-base/device_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/prop-base/device_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/default/.svn/prop-base/menu_help.png.svn-base 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YMC/%~*!kivkDiǸc +>f7 ^(!ԐD+%9($nsȏ[ KB¸WSSycQ-mBu 14G-nI8"*:X1e{~n5]9:ǢmBBd,lFyC1Wr)Lj1hֈ9>P[Sr{ޓF t >K4UhSgr㝪{aO13 +S8CɽO nE}ܫ "-}*2nldhGt/{jl9Vg̥2L;CZ~o⦄~!6ErSǜU;>r/qiF~Iדy"r)\24[ ++u3a#~5J2 )֪y!6 rG +2#=FK{2Lӥc(_}{YL ;ߴhBƽpm0>d ? 6?쳡Ʀ {aO;FJ2EXw%}SĞ\ȸsX +MRB{A;nt|?^A[SBƋ Bȸ2ktA_@ZIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/progress_bar_background.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/progress_bar_background.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/progress_bar_background.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRb2tEXtSoftwareAdobe ImageReadyqe<UIDATxб 1 CQ+d#Un:7lg"!>&t34)X #G2K< w"ن,t!5IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/font_console.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/font_console.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/font_console.png.svn-base (revision 850) @@ -0,0 +1,28 @@ +PNG + + +IHDRZvh +rIDATx]dIn#"XQ"**VTXUQQj*>+"VUEUUEUDDDDTEU\QQqEETD]=}gf6I;Ͻwf9yyhسAAAAAAmC -B -B -В7إ. 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8$c+&6L!hmyx;?Co6tM.Mn +S{;$`0n=OP_rAՕH{5]kPM0J- ,#h2,VH]<eA\s|028-M /y9k6K.C]?yfAD2RhFOM2/I@rBlͫ + Q0h)$ 090)2IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/menu_single_user.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/menu_single_user.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/menu_single_user.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<XIDATxb?!1ӿ@L?EW@`ƪ(dlC1MA~0c`aS`6Q,-"IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/menu_ignore_caches_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 850) @@ -0,0 +1,6 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<]IDATxb?A`jq~0#jJX~0 +fϊM q +W3€?1}e` f3~Ǧ )2GIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/device_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/device_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/device_selection.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDR3@ftEXtSoftwareAdobe ImageReadyqe<hIDATx10 {"NRp 0s`́90s`́90s`0s`́90s`́90s`s`́90`́90s`s`́90́90s`́9s`́90́90s`́90s`́90s90s`́90s`́90s`0s`́90s`́90s`0s`́90`́90s`s`́90`́90s`́9<7IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/device_fat_o.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/device_fat_o.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/device_fat_o.png.svn-base (revision 850) @@ -0,0 +1,184 @@ +PNG + + +IHDRftEXtSoftwareAdobe ImageReadyqe<_IDATx[-yU}Y93΍áP$%KLÆ;@V`CH")@^hF1"!D%ґJ4iFexsf{JU{9իJ)8dBD /`<ǹoMʻ*sgOcqd\kTu{p׈3!Y(7d!{Y{ NudĽhU <ޯ́=iGץ+x7wYfwP[$-Gz߯9OtIO*(@m??j38Č/|n_gdQXHQ@SBKo${:r dž "j]z_/?^G%_tAw!Bǰ$7z%'ǿ駿b 6&qCqX%Bȕ_^Ԃnv+o;w'Q_<SwC?v\gGG$_F5zFϟ/g?Lx8)[0*K&,GEIQ(D'ZB3`9BO4 DWT~}Q7] +{:(B{OA3GIw޽SlluM`Ʃhj +h#ݮ.dRi) 1D=K18 2 3Ƞ1ZCf<ɰ ޤ)+-?SwVo%$40,GٶmPk +RcJY@}`npd #txH0C1j]bĈ=Ɖ>saXG?nPi@TE\."z011F0gJZ(Ȳ8*!`! o3tF1FTIFTuy: #&oڻTusr"g(&on8r:$ ))BTU%‰MOX њR1bD1bҌ3!͈8a1dFtAFdaQ:^b'Mu Xʟ˪*wTUt"G|YRV>#pߑBaS  W31s~,Uy>P, =Cn&6r"58\,J~5jQҼ++(!U2-ǀS?dQq_r1nw_ZcE)UYݹ{)FT"f})"V5NPKYd阱xcV VRY1"@btujЏ~2 jS֓8%/YqȂ3hEYkT+BBR쭩0i!iݞAۃ g@fDŽ!r#~Č8}׈HJ?TZuiԙ;߈n|YEa3t_`푎:sL&Wb +/1Ir:b/2fw +qIcL +F<Ǿ9ra +)6 +QZkdfrNI+k`g$"oǠeeؔ:"~(GyfZ +o`Do9V̉5b^Jl,ɚJ0=gf5VД4ie0X)7JU +m-{^53C,Z7?5c'Ge)E(HDwm*JEΓghGQVZ_D!ؔS3:\svٞ bt>CzǣϜ\Iơ衔Z9ɽ9B5Gչ +{DF$ ٯGY +>,dIU +HحH=!V޷bP)spYVeج$ +P-7]\q@6WwF7Rٍ~QI@qV tD$t^xӱ"tkfWq }~PyZ${ (O눼R.z^-j΄:5ŽGuH33˜(>5^P-Z=ƹnfGJF6 @TҟBL +CsHK1R헐<uNL 0pnwpGL錐:#8,V557-.b@|tFdCiSeAŨcRe?T}H=(#r~Bbk,G0!E/{:-*Ϗ5=f(zZmViNml=X1P(,So} l +C&г +f_&F%7պ<G d8:_Đ)1~h\Zуj,gnbлSqrݨ%1)zŚ2Ʃ7*Y]ɍ~q1[W{2O{+?W)^5#i~jJD9;?P(㲪ц27xp=W8%J`.W+J2ԯ}YM f1f޲kc]|;++D +#NQ]6kMX]WmYxŲ*zXTrJT K]7pG\˲\PjPo|]1 =:{]-pWBK[{:`~<0.?`^bj|^Mi??(D:as:cZp,Q]UՈǬe/nT RQ)EJQug$kjFaARՈ!_ &U-W Yk!RC|LQn?ZfUhQ'oLj_2ڳZYQ3?_ywZ_ + +HQjWo* Vu_K/}D3 +BRI8cPzi!9zp&j dʽqS{m +DEԅMΨΘ\e-e]߫ɚ,Pj&ӌ +a:@t_/ÿr+͈|o~:;&nuLUqju,K$u7ZUfa>1HX\VW.bꔆ&9q"%[kѴ/XYV%&cdȸ=ZOh@XHHW8RA\t~3lw4f՝*3ik>?S\2y{Ex뭷t ޲Vw*m]0}\Fg =a<V3^WSv-u5!?gSs> +ԧ Ϳ g@g*|s߿"YCiZ3!k2H}Yװ٬HgJIƱKG$#A0TU|6Se潚ұX5ΌscԜcZ/WWN,6f~B|L,h~~aO 4hL:#FطD߇جck_ʟ:QgO|G׿ +d"?׿g<} +gg=YmZ4Sown ڛ1XN AŢ7+%s 1goÇlt!zs?? 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@CGhTUbPZ'6hв5xEjD@M+&P-e 4qC$JMcQ?p0( hmD[oC̨U8wQL`pALz9J =fa?][lF=VEMIN9V8@D(e$$ra\v?i'kSҋmH +_[^R"9WHr#(FCUQ83eTcC: 1VSqX( +55z]DbmGBA̔!dF0Ls^s(uxO f4¶&K,Hhc +cd;6ۆ1bԼzNgc#3od*0RC#hb}̾),*xDQE6E%8&DtPΠ{1_XHi#'8+L+28p2pԁ#'-ԡunW ў wDg:aҼh:GSX\[ "2c /dC6ik2 gI`ЈW:|`TMVRkuy#ҙ:E* Iʂ>SH +EJi JSv)n=9pV’?_ d5WHA@Jh뿾G~w_3Jaj~\ъ嵡bm#ZҠm/|.k<3u)9lpa,aQMH4 =X)߮3>}.T죀/o+aC!Iӡ3:ay)4brj)M;LRYH8^t=š zr4/j|(+a&DY'C!$4ԂX +glMWCaJ9/Q[Fp>Y39KNOx şPIXg)9}jk1ML᨞広J28QdöZ$lnA.=Da\FAZgcJ!;q'(M9L=t-Z;цlN+Fxz:I01m+[]|ϫ˼l +N#4a%4!1oRIΝ+a\WJ#.I !ewzuЅjgLcl]vZzG^Ⱦ~viT#'`n$rN f^7bGY77s?ۆjd_>7^}6N +VD>ß{.W +)6ÖDem(6ƐlAɮĶj}yE{#,lv[-+S V2}lEρs']C^eѰ[!RFL#r3Xp!^(En64Ƒҷ9]Co!jkәiv(DŽE"Wa+[9\o'dz+]og_1oqawbpV:jpڣ"B^.ނt Ҷ`"hXP>9@M܄POwb-NhY߇ ڽ}>g TS!r؋PM=8C^CumxPΚ`uЁs8-S/ ty]kHZs PGJӡ0N +kLHbeBJJUK*ײfj}:Aƴ0<+,N6n(8V-$RH^IEfŪJ>HHfxu\B=OH[owWBw!A >dD~y`SzhH畱1E5IO͞^WiUJ? +%0ixmGO|lٌ߼0,&e>(0 ihN2*Qcg}T׵3Nn͂iH*3;82=[[vCn[L:d_T8Lxex2<\ۭQ#orӱ~irWE2wg^Y,Nz + 5{~Va"+*>*q(H Tbkݮ\VC.&V O}*>f_ +#Ya$S \^Yܭ:3lT"YEdZLD_666&?\帠V*QQzt{DSkϫ7"seAEU< [np&7vrc +erbQ6ˉmC▆Q^~zA?{9|MfxdfbHzb+Ymmk'ݔwv׭,+B; td}b>TYRam|Oܼt]3x<{k xJLg*䜊Ji1[Tҭ !8*Hߟy߾|R#WϘ:GxpDH:%Xc/{t_[kтńhDe1K\ϙ +Zq&FMXrRNxtdɝ~‹Vِa̸<)9E18 ?+FiNR9g~%@NU ,mes&DMgwXN,wxK^ H'I0RE (7 U0 +)u^ˁ+ׂ"@9WӍ=-Dآh +Sp +*kY/wo}6(y(GY4REwlʡ߾#qk Ș\ޘJj*W-LU7dګӡ7'XN~B@uTuW <_tFv55R`?9Sq֙pWQ5䩱{Y4ۏ<‹l;i)f2jpИ$#?zՉY+2=ZݺR3U+h%DqPd 52`Z>5 +wR6udua:kCOhiEim>/)~-==,fڱŪ؁w?Ǿ>~kx핮ޣ1]XnP$LIL&SP[3ϝ]0F|LMUUD~_M@k>zĪaDy9L>5=_ĘwM/qg=,# +ذ +<oe'#e* #vl ;U Y0} +(Y~ J" +l"{M $(}o8TA<@QxdaU9Heu*( +&Sd.GyA!Blnk+Jsd}P*88Ņ +%E>3 , +PǨ0_xEMpp}PP?>|Z +Pa`D!+(8J_!K|. >ϯ +)L5Wx c +tU@JGG=(PTUTA)I`_ҮX B*tt_Z.K4U*KX i.Q3J@4yJ:^:(B +p' +(`α *hp2@ +KAF +A!(6B,ACE!(4BCP + +A!(4BCP + +A!(BCPh +A!(BCPh +A!(4BPh + +A!(4BPh + +A!(4BCP + +A!(BCP + +A!(B+_tF;IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/menu_help.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/menu_help.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/menu_help.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<VIDATxb?!sFF&._wŪHaa  +ᆩyab  e35_gbǦ IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/default/.svn/text-base/menu_ignore_caches.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/default/.svn/text-base/menu_ignore_caches.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/default/.svn/text-base/menu_ignore_caches.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<XIDATxb?!1ӿ@L?EW@`ƪ(dlC1MA~0c`aS`6Q,-"IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/all-wcprops =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/all-wcprops (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/all-wcprops (revision 850) @@ -0,0 +1,185 @@ +K 25 +svn:wc:ra_dav:version-url +V 55 +/svn/chameleon/!svn/ver/327/trunk/artwork/themes/legacy +END +font_small.png +K 25 +svn:wc:ra_dav:version-url +V 70 +/svn/chameleon/!svn/ver/327/trunk/artwork/themes/legacy/font_small.png +END +text_scroll_prev.png +K 25 +svn:wc:ra_dav:version-url +V 76 +/svn/chameleon/!svn/ver/327/trunk/artwork/themes/legacy/text_scroll_prev.png +END +logo.png +K 25 +svn:wc:ra_dav:version-url +V 64 +/svn/chameleon/!svn/ver/327/trunk/artwork/themes/legacy/logo.png +END +text_scroll_next.png +K 25 +svn:wc:ra_dav:version-url +V 76 +/svn/chameleon/!svn/ver/327/trunk/artwork/themes/legacy/text_scroll_next.png +END +device_ext3.png +K 25 +svn:wc:ra_dav:version-url +V 71 +/svn/chameleon/!svn/ver/327/trunk/artwork/themes/legacy/device_ext3.png +END +device_hfsplus.png +K 25 +svn:wc:ra_dav:version-url +V 74 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branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_verbose_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_verbose_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_verbose_disabled.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_cdrom.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_cdrom.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_cdrom.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/progress_bar_background.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/progress_bar_background.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/progress_bar_background.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_boot.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_boot.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/progress_bar.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/progress_bar.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/progress_bar.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/font_console.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/font_console.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/font_console.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_verbose.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_verbose.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_verbose.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_fat.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_fat.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_fat.png.svn-base (revision 850) @@ -0,0 +1,9 @@ +K 14 +svn:executable +V 1 +* +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_ntfs.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_ntfs.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_ntfs.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 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branches/Chimera/artwork/themes/legacy/.svn/prop-base/text_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/text_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/text_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/font_small.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/font_small.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/font_small.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/text_scroll_next.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/text_scroll_next.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/text_scroll_next.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/logo.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_ext3.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_ext3.png.svn-base (revision 0) +++ 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Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_single_user.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_single_user.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_single_user.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_selection.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_ignore_caches_disabled.png.svn-base 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branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_memory_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_memory_info.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/prop-base/device_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/prop-base/menu_selection.png.svn-base (revision 0) +++ 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@@ +PNG + + +IHDRw= pHYs  >IDATHǝklSek~1FDCL@cHf"6AЭӉD!G-#UNv[i kt뺮=휮;6wmy9i!Hsa/z=z]VtZTZQpcIV< #°pz5*oUO7p}N`rr? 1 ņE& 'ҡ#hfDġ䷒6(Q6%] D΀2^;OǒhUawc9>y!y(,ڃAw=9J!PY6{9d| +ŋA;~‚k楍X"ی%nO0*h_ +v$=TLLMc49Cxr]/ʚ"|\%>)꺭8'޽ A:AC-ALi"Dya1GcuDN}QRB|ݔ|@xro, vP,D1b#aQ*ANFlo-^e`{!LܼLMA(58rh+{m`){0x_'9rucSSNt^"q~.J5d6"łA*aD>c%\+}`7=}τM8E@aNh  :M.uMN8^ +s$2 /<55 |6)8ZBxQa"fĂ`;<9FV~?k ߺGR L72_8ٱ?O `ћpbwAKoWȃS + +!&U0̐ ‹ \gLtb}^0guP:Xʭ +lro#mQx-B-bxYNhn+˛ڵk6jۖd|fyTsqFʴPٕ2b)f' +-4gMm5Ydt"9$37~vPJ\bqvPjM$}t +$Z8 +'IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/device_cdrom.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/device_cdrom.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/device_cdrom.png.svn-base (revision 850) @@ -0,0 +1,133 @@ +PNG + + +IHDR``w8tEXtSoftwareAdobe ImageReadyqe<4IDATx}i\u޽om{g߰0I)("ՎT'Qe+*)UpJd[X.Gbd )4A@b'A$ 0={}NA`^{_w;9ۜ1aՙwf4\DŽeI%0fjUPBZ,ʳ鹹sΝ8vՙ鱅R~+ +_&L]1:cѭ[6ھaкB.L.sm$eIi!g!B0 xaq]MٮTrZ9w~3gΜx79 ^Q5>oQF K7ǝ[7wn)dT•QJ\XC +P6{fqlI6a-BVV^?p{ĉ4q`xx/ߣ{[Ed"asv_ߓHZ AǗ6Vg tV +A;(tGE@+lǑ-T +lp, +OL\=z{>o{+S?M~K~nզe f(a(x0A:X|*-*@@< [*‘{wᱍxb?y'~055y3]wK R>z՟;|wow +W>4dgd PR–W5 1 +qϥ]e.=[~,wvq3J8y&or|_ѯfv0o^W +YdƦx F3_2~|?'g~t`D12`˱T\X)3.a4߾}d2Y8~ LAq~KJ7 ,'# nazL +t> +q +L εwش_-d׍_ᾣ Ҙc]l@R)kuvv=zxR}7=v_t2,cY1(=|&ŏ :H̉IevH=Xe⾶!D'u[@?R^q϶?[O.nX +0Xؐ%[H=AiH8E1@*D *A8 !-%Ek?+|KU@+EgƍT*UvCB(FcizźS?~?l4WEKy㋔FI=L +\+Hn e2PŚ[%[-˧tLހ{ (aܫzʖ}'Ӷ.鑅Zc!V3a3" X@رH 1A17fX-ס1.'N4[yb~'O<{7nnt# +'LOU>8!!BAl <‘G$ D=U-]7rxxcYZ3>Gvߟ /X,/aeXhiE +$;l.O,2?'Q̇Z -:D7]+J +hߠ׵6ZVK>ρR-߈܁o~sd<8X2)4Rn\A!;BE"gYQH{VlpVj0qVy5uQcFK_ +x:)l*A Z  暇>7nL豺 =|~;֤X?7(!pâZ)z;0!||)3V]ׄs>(#!`h!hlc_ŽV5VQ + yMMMq-Zj_#­@fKF}G((R톩kXb( l+G&a}6=鳫3!y!QTtu}#qجfgܬ1x\o|> K~ +(Rf-0?oKкO]\Q0U֭O1@(H2O::\TȚ5N +[tخptMHIjuΣ/ShH@H{Lp-řqd2 + X;Zj~T@;Gk<$P)AD5KVh`l|r.Y +[G +NҲ/6'\m_\]|633֪ۨA \ 'ě("zR)`To0ZZAf~rrtС}eJpa:|y0zC.{{; ¡A{˝TJlU"@fxĂK$ZOyUNjNpɫ9l'H{z:WXѷiӦ5kVg3xP0`z{{Gv1ϙq|~zp-m.i6DqBPՃt0x2XSn%t:ν1Q{gN:ƉcBaUlttdLi +xx~(0_,tu5:Ng|tT*$q*v6Č&\fa&^rQXry~ * c*FƇM/@#j +?X^88;;zܴ+-smO|qRq_xK) +&Bnn G虝al%<9 W?w`WgaO nVѨ!&{h$A<\s:&(Gd=: +ГH7*+_mB 7qO:uX<_A, +7iֻ:]`"b0e <*`<(%"dxoW,2x +' ڻgz `{``%U-29&=8'T)8\'UukK[Ӄcx }\-- @ov[bܳg(=1Ϧk7mm)HDTWuG$a_.c7!n|M27h+dy_9<4<<x^GH/KiPb ߸i聣"YRrl6 +]Pܫbzw+CZHT8m=p[ifz߰aƁ/ѠnaؔZ|G?x W ૲VF5ngh`[b<2P ɦov1b=22eMq rqJBF-LP=K ޱUss>pa06( k, מ~dVzn AHZ:YmHla1B,urU(t&@ Q|r:jB33ӯ߿Ҵd\.hM_ރ* 4,XjzP:")}##Fy`،mJV 9r<&E:b  +TN҅Dha:pBWa,?먃pA ||p@)d9n-{>K6*D@ @ePl s<0sW\ +uY'j]՘Bo<>6(~FG 0Pn)!J![ښMss|ջ9T0Y,]s%=(8 ISUY> +-\CzCV^k+#ym<ע8( +7{=vyZVz;az|pphPZh#D5+JyLY\ +Žfh_r&`/^  \7რz}ʼi8QZ8\_413>>\ze' ܯ,G$ WO Jz;t>$x l +un Ty'[s3huyC.]P".Xa'k[q jF +r$ +L)8K%'4Tl zV&@ +2oVhh"ȱ 2q&_{ RB"ǀx*^/(.Bܹe, +xwpi!`M 0{|a׈Rp i8nt*Kץ#űS5dhEs,b$FMrEb/zzM +K +X ?LJ-UlFȰ6yԩ!x﷔l 0W^9yv5BMRs,ȯC A?;`sP"* "4<830'o!UFG +p{{(ihݲbXVߩ'Fb܊'irrAACR94(T[@EBZ?}ed5Ξ=3 R BXyx"(EJ|) +UtwɞՐ Z?JRrIdϩTb\V[PdfNjN-#㰂BՇP +:JI6:QMGI i$.nFHsQ^" e1BRW +)Z;됕8ZS S a- +PJ +FQoԗnbY㡦(ֽ5q1 *j2[u4r7eߧ .AUk6`ժUsO?Aڵ g|B +ټBD]W@𘓀܄ I Y AGV +á^(@LK +A!`Um,'!jmwmq+wI T[sZbdkc2@%"ʸكoHz/_>N 5u^n + `,NO\ +eؾعll +yha>G8!)6{yRTrz,'V)t[ +8r\<9Pq[d"ɚ4FۓOeT:Xkg&P0F8e J4/؂zx衇m|rp8 kb88R΂U AFa8?:QASSR2xi*@b** A +J!QP^G%RIt ^Qrq6}CC{կNa.TgvL9i恂F@[w=`;:;d)a`@= +b|FI3`G +m!5+(RG ( !&]Z=l .-]km< +k׫_--,Tk(8J=6R5`cyQhmttJyύ.;|G>/R*rN8?G0 2[d,Mx%ܴi3֭: + ǾSCA8%a;IUB)t/w&U(`HrUCY$BDȫZ]/KMԕ+W +rls"xo1;Ѧ[1D"0 +X| +jЩU(bcHFT { +a%h1j o6pGEɯ AZˀ,m970 *B1,xZD +a#*D,f!>Lw8~4$}5h@\ +X#ۻZK +QOpg?V4%p]qX,FfddL:U{P(dv^Az텊`\!Kfi}ull|B-kQkeZWMwL&$㘫\re~7ĂDQ+ xԔps3_CoCk'sN@jUWOag1ٹl]=+u`?LrvG:]`{bS+@cA!crp{(B)t"8Fj7 0<4xjchyQ㢅.dwQJf;v6R?Hg0+[ +[1Ng!)-A(FAW*`zBxkod7-d?k<ON.c50`#F1x6Azv:3;s蒎:P.vm߾-7 7(m-fO\H*GmP~:80SQ+>}k4Z!`CpU\g]7,v!@ +|J}ꭷwsDu#';imR̴43Gm04 a4He9z ,Wy-w-$3aVhvyo7p-@%C /8~`YŗA1 PJ|>PH6^x}/|8?0_. <{Rh +L$UA{Wn@Kt3;7[9 BِwԞ)U^ያEqE{o<'~6vx) WO̻vzTjvr1t \ΕYS +WS%܃Qs p"=/2(A5 ^q$>Nx +nMFXȺ='YPT]&BZ%t)pTyz@HNBr<5Qcjv0uGe27nا0Lnn7=^mp"T^d_q(Vtot/ +| +ZRiv]`};mtr5LH"K2fpZ*,GE +AҜ!謂!Ŏ;xf}߁ +vJ(quw,ڴ7ܥίj7 +)VzG___>Nm;%1^鳥氪)WL;osVkW޷fHw*%Df,;dX XZ|bzM?| +r'hD/[V4B{5<<7ǜ)xޠ2*H3#=&\wS^[QTXd ֐XAء{nk}Յ-.?zpÐv9SN +4cN&-b"A=D*3Z6Wfכ*v~SG*={[S):K?{-8>L8ٙs=zԑ`k֬I + +_ `8Z͒Ǝ<O6$ϹBn0ّfI96Ձ+B:z,'WlK.QYz莖Ӵ}UdP}rr(s>PT=c9g(G?'>;vȤM^7pqnUEs H{`(Uׂ%1 m9x;,?aN!<;dUѐ|!U&dE0"8 -r!)T7Դ, +[J@;{C\RvTU膝;wi7 I(@865KE?mqn[q\*F[BB07-XW@ [oz# (N(f2UBN8("S{o|\3LJMkBҒJzX}x: +SjP4K|هrn(H;`Dpe$T+}H+GɵH苧80 r(&pZX=*\6}T7!r:St`HoKڄ"K^pf_H،A4_ŅH^\+,ZvhU?pp_m~e+ƅ cqe)={m^K oxuh(roN#ȤLIn#QlG + +X O\G`aQ\_S'_$[9F +b uwntn6^+TSQIf(x>d9g:{dAWeh,!UjK@%( GjCK +gc_o^c@O*)7fٛ#̙7.]607^k)XuAnճuP C + + A[1]XYd0AJ}nCJSY)竟6O5]LW^yR*OXaNYEi.T>?R,I6Nc + :a4VLfSj +5[x)86g_@#_3.~ĉ+klך-/_%nx g'Pjr%TF|x4.)W D͐o0"BP7g_&ZVo: Gz}Wlܸ&s&LHpÍ|x&ЧVQPc\2 6baMH[LI +otլiwwNIU.fm `n.zM7'W}/PCde!q2】hQL<>OA\pO_W"7`7~􍲠?WVq #7oԋ\\kv\?ګ|ի$x?gY(~~ xt1(V%,i7QEDS&g=~1_6jXR~T5^:o߾drb0oZx"5Mt͏0 I7C +CBP$XHXQADSi9n^b$kNYkT_z9={[OP_O8;33XjՊB`;AOJ9T`p?bAv`j˜(0 !7$q|,ڻI]8>ij8[ v<_QjU@Hks!0vޑё}5T50\\zP30/2Fk +CUM:d-['#g/;nK*iH{!w[n$,b;mg,tFA'娽̀Q x ΄QEko0./"gȀI^.~3p4Y}]]‘[^?B3u$?F)EPAOױ 4 +qhtaTWS>&\axw (&nuɓW?z٧| Ir7#V8|c3ϼvB/.^9ZY; U+,PZ+*, +ܬ YƨyZgv;;<׿oLMALet.vvuvph5O!F}8?$V[hzM\d0$7Nem0x7P@3 ANԠ_'uh-!F2|㵭Bp+%*6i7\c/ߡi=C1^55.KM6vsX_c-hM@SRޟ_C)aV +`-[i;&#/ AIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/progress_bar_background.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/progress_bar_background.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/progress_bar_background.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +PNG + + +IHDRЭtEXtSoftwareAdobe ImageReadyqe<IDAT(ϝ!0 w  +\hmtҁk5ʑ#z0TU6Ilw`$-!loγ2urT6QsL_t|yGf+Yi&IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_boot.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_boot.png.svn-base (revision 850) @@ -0,0 +1,20 @@ +PNG + + +IHDRw=tEXtSoftwareAdobe ImageReadyqe<uIDATH}kWe3;03{cYօeb+(!Rlml*i4H_i(J j{1bjjna-t]v6;;?,^Or7G|4:@^# +#(eGˆΤMn7F +LTttc1zXY(e+ i)Tk?4ʹW r=n2n +Bc qLٯpyzf/î +;wZ>y[!;[ڏ>sOp^iL€0ccZkasezk^G_J8'bEQl;G^\;d c +T" +l_CLL +}ٲ114zt85k;,IddqE0FڄLIvAP\];=p;aq u$B˕[>GuO:oBH0{> 嵑k܄; +@Daeٛr}a-'P kCneY[ɑ(<,:QJ[;CLԯPĕS)nvd쌖˥~\h4 B?˲PEŀ\sJ9Zy@ &+' iR0 :d67IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/progress_bar.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/progress_bar.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/progress_bar.png.svn-base (revision 850) @@ -0,0 +1,8 @@ +PNG + + +IHDRЭtEXtSoftwareAdobe ImageReadyqe<IDAT(uQ=lYPaX1;C xMCW7Ch(aHp~ +aXI f +$"  +TB/`2,-J +dzxMRBz}>38$ɀv$'wF&x2ɴ% &gl +wHSEs\&cdZ@$20Z2F 6%"rS B!+  UJ,0C%޾=϶H$mO rIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/font_console.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/font_console.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/font_console.png.svn-base (revision 850) @@ -0,0 +1,28 @@ +PNG + + +IHDRZvh +rIDATx]dIn#"XQ"**VTXUQQj*>+"VUEUUEUDDDDTEU\QQqEETD]=}gf6I;Ͻwf9yyhسAAAAAAmC -B -B -В7إ. Zh65'@kB * ciȚۼ&ڱF+><ȆrgޡW`@{!^' -yWxp{1ZdV3߫AQC{ T)cH`2$cZ"+? ฃHm(pc += +c [ӿX_1s в|XhU0-8SXЊ?` ߐlxI4db!x$Z&gXnX屍s_.?L-a}WU.}} xX`,_?KaأȵW%Ms5$6yг~GG;GYCv$:q1FYKJubW$3f&\)msuN7JITm`ʹy2,۬*q1dX6v%̿X9i?F8.gpfN}t_@)F8PEP>ŀ| ?yo[G,y ,X9 +!$gn]u ٜ974yd7,_g:Ga/)TzL*t(܏&4 0ȓMQgAo7i_P$187gG<pi$<)F : vATyJ 2]Pa9(w99R朖a>8ƵY3 t"A ?[}f㌟D]U +aN5BG\U՟tP\`Yf c@FV\Ӿ[Yʹ:a/)~b*x~͊ep $R +To"9F'&11J8SPixDO#:(QaT GK@n&C >mRTAM/ ʕYo'dhF^}7A1R)* ^k?_@O"St6!?xic&-1Գqa6bW,UV= s40wJA#u0m R? <"Y| +4 N WlL0j<|p1z7Nb,E d.8+cNLl/CeBCYa{1-)T:D Soqmoz~i׷H{-a +5h +XPA gevc8W(uF J?dks-=d2Tևd3?u\W*gw.gɀ38M!pW_42a `5~ޫ t +G, n3k ʄ~#kc]ȆI,=~RW xF>e<I&aGzޒeΑ@fY IojXc.І\sCxJ2]ᦜY߬fF?DJt4Piy]o̱# +{\],0"_pǨd8B +G^_5+ntfjQwlF&?͇VkI[ ݥ_0h̴S=\yk=^-Wur!K6ޟ_}_&#< +W<4k5S[c|x +n#!_^c[M<#F?5 +\5>p=hƫ\{hr +_=>σ +@77˓HmwdZ0Hyb{m!e$;4&nX[-75 UEpR؁6oǮ/5 +Vn +ͱWfl=5)-_^\kԚ!)ϱj×/btZhSۙ?K~yffw%>Yή󑙇LKϗFjk{ZhڷTX޽BV6 9IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_verbose.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_verbose.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_verbose.png.svn-base (revision 850) @@ -0,0 +1,10 @@ +PNG + + +IHDRw= pHYs  1IDATHǝile'~1ш(ĀAD`lkX-"#m%)Vzv{vnH}=;ZMly +3EL8$ |4ӐTY#.ꗩzsg" '`uzzmOfXB,B"Lj ^ k/Wx,6d*AeCJ(Qr-V_̐=!N LVo]"9uK8HJxg`6E>T*ajz3'@62u-j+(Zt3/B$R$}nN"ӂ +DBZ-wDb \qRP,&c7{A8Fmf Bq1(\'N|e2wݗ/$RF:n#E.bfrA)[B!GHHs)MD +VT)=kpװh8svYe+l{c_qHtb*/QrJIW,s J3g >K/m[J~ށeKQ/=3T=FW6>_(l.{w&@1[@Cxy=؅umFGx +ov|s?+m +J}աg%Sf%}Wb7:l܅{Q_/D5w:ĕ9)MMLI>L#>$QVvl)&n'zd5`2..#IF87ǕUd6"C<`t̬2aD>,c&܈ +`a(<7{πݽ[q^FT$øcnẫ /!{8xȔq<lTl8CFpcIgߟuEXѬَt)AZƮaoR8Hl%5}a&Ll.^V\!N68B -ЅP728,Z#UǣfQ O`қevך,`ӝ-8L G^qsܳK;M8nwqltJU~'uҍ:)YФيWРZm o}sNܥwW+a*Ih58_HD2(OحL5L'dX1>vJ:+mٰIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/device_fat.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/device_fat.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/device_fat.png.svn-base (revision 850) @@ -0,0 +1,95 @@ +PNG + + +IHDR``w8tEXtSoftwareAdobe ImageReadyqe<1KIDATx}i$}߫sݝwyryMƊ@( FK| A #@kd)F"`"L٢"i%J=s=WU~{ݡ,ŮsTcw{9ԩS311j5g``]^^v{{{Z|i6N6rǢ o)zyvóxvy_\\ t[@g Auu %>.=zYXX@tP(^2RbM$nAUTkuuy͗뺡eFz9<{cM|.M0%oJ%) +?"Ç]\}|8 s>{aB0J1nISxbV~ؕ!'$ѱ3˃MH~` SyAo8N zg쌍y49$642LD]'pSd$BFȋ a+%nnHx>94L㙚xox&w[f>55{j4ALX]S|*ZzB|H{ + +@4n.EF󄹞G„nĿYoIҸ=5;> 0EOՄHQ#? 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X*5s4}qSH2Cye@>qOxoLa/:~ϿC@=p:oZ,(N5klOq:#I~Ζ744jРSN]EvgŁO7FNJGK~L%{KӦM[&L^xX= (a\tXV3 ]˶?o=4;|f2K/={챕ŷo&c;ɖ޶u򀣢ZjtAbgK"A +kH|HKv=7,X?GG֣U3GA/f>,WЍ[K"mowB_@4B\RG`c߹DЈFf/˿E~5p_<J>dfK Fōqe2 :LxAx{ +篭UyEj[ =F};IvOJ(WgІ?3:f +IϞ=;{A< Ƃ2#iOx?Cq@OMGƑS +z.tK7:8Nz^B pw +@O1R^ [G}t?VH34K_0EУ0umdA[7ʔmWI?$A<5j'tz&1U"h w= DH&Q:u&Ϙ1;#~>a{6w +cǎVVMy+"%uݑ#G~9gΜ͐Tp`Rn85O?Z:0]s~CauLݷa3ܿ.0ņMN%Ma+`ȚLt~Iʦ1c|Ty@˖-hӦlZJ x|oQ';?|AhmjԨqXή0 +|M2^Cƕ".ȋ]>i-hb5qĥ.(%(Џ~zeᣤ3Y ]`"k1B *K]xu-S-7B@@WX7~u=EHؾ:g}0|}nOi$ G.:jz|>;I)j8'5n1z"7jժ3ޅ;G%X(U.IIf]"Mjf[f^%DH#;X6P* 1z9e[<_z_Yv?IjCd<lEHǺ JVV֙4Ʃu뽵!FgtI?<1%2!0#X d ɛ_RxD4!3 tlA㟒$F(| Hr'c"(0@YJS:wHLpe,72((r]x+aDӎKY2.p,,Ю)4h)@}x:?#CQ=@xHi܏;H}QE(Jg·x%R"7\rp^i-vnj75j)jfЋZ'ۑޛTdi{nxdu^}W|Q@ +=N܇:8;g奄7@DdYPͣ8{pҸs{`@aj gãK;##wِQa3<7|`wlTnSl+x|XL> x4Koʕ+MzbR} #]4Q@'r;>862IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_single_user.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_single_user.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_single_user.png.svn-base (revision 850) @@ -0,0 +1,14 @@ +PNG + + +IHDRw= pHYs  1IDATHǝklSe?hD` h @bb@0n3h@p"K(F2 SҮvl]/ivO/v[w;6tM~44}<huH#c>p4Ec~֯Wv)mJУ +灍]< XSSD2ȩxa`zz_"R2<aZFOvL؀=*A3G,'a?mS\25` Qq$_(~[ܔ Z<̛A0$gr\pR|NУߔmr9ٝ +?=G}}=oa۸ eR)x1&jyC*h#;-Q,"M +Oe@'S@|s + +smH$`rrƑ/BǙ4 T.eD"JLL`t C,F$@5`_'H#E#s"r(2$x>C6(P6%]`bUvYIKK /pFEH#iapPz26.*895$PI]?`uXziVa/۰=/+xvWn`ѕ5оwV_Jki{nr-S@"7b ,#nS*GP|,!#̠w76m*W |Alv˄x? +:Hxqi1$Hp[ȃ8݀?l!vqTYvfɨg6㘦F Y@LÄ$A)z\1]s;ܿBVٵh6 v2ጁ 0= ]b< MQUUPNsgf!>y5N(W^ij%u`N^3XL# JBpS +!.ٳhoEpfU^Qz|Ŀ<A 6 +v#ytEXtSoftwareAdobe ImageReadyqe<PLTEBBBCCCEEEBBBDDDBBBFFFCCCEEEBBBDDDFFFDDDEEEGGGPPPQQQYYY>[WtRNS 16CEXahxzͱIDAThYV@4(HG ߉x<, O +|fK,l\=dke" Kuw }pח`9/? >n[Hh>}:ğ(YIfȗn ++ +,n{~"wv";ED is.XVN.41nb>o,Gpo뢊uEm p*fO:tS`mKG>G{5G]w_GIP2R_X;<ϓ avh@eM¦i;/]xdAdAdAdAdAdAdAdA3H-yDagf!y*HCA+yK%ga9}:O@-צIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_ignore_caches_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 850) @@ -0,0 +1,14 @@ +PNG + + +IHDRw= pHYs  IDATHDž[lTUϙL;mi)-Ek +&FI0JL#'}h'mo`b|EMDM*-RI(#1XWf{/3Pp%eN׿V"/_( Js9,Q;Lf'X\Nj4|WK8ִ6wnuB) TѴ?)GwgWmcٳ +2E^PSSSS^} 6݃R +ȝ/TbXvw%4(H:sb֭yb8J\.O$9ru.e022 /<@__Zֈ@,EkMh,h _<,Jik]ͧH#֗pB + +j, Ke v088ph*-9Z3~se[*QXc( +:Bs~trXͼuSJ}/1pj:BUuơ@T|'ď_C7$|ETCַ-+fy=wODgpR]g}k"?MFL d:ֱeC̔ }fǚZZn30#"ޢ5Yы3KӤ,iGo$"ߍ}Bcw},;fHo_404I 鸰{čMIp`WNNcEr&? obxXDţ\ +kFTl~Wxd \"r76 +k + +$6YoJ%TrjV(Cʕ1p}jNNGǞ$WB)]h%(<мsXRTGc,YrY gO˹8:8N0GW&VhSИ@YWAl{'_f2fs@ٲ+_gƆ@~y |ִpݭߒ/gʧ)Iڶ\q:t_aWËE0 N|*ГδH(sI< t*x%,P(/t詗V8{!IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_video_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_video_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_video_info.png.svn-base (revision 850) @@ -0,0 +1,10 @@ +PNG + + +IHDRw=tEXtSoftwareAdobe ImageReadyqe<IDATHǵˏWu %O02B`?lXBVfCdqytL|[,fKmN::*d;O?|Ա\t8Q?LFժ4 +YckD(<#"DUz=剹ߦ]^X7l rVE2[m\XC+fd=Ǝ|a|CcՑADpB̶Ɩ˼7MY:J.t{)V1ذ|aI+^tȍjөa|3!j_8UijIssӥСo230T$^.6.hٜdm>,^ƣbꩋ=Y5kt^OeH̚f' .DM1!L+ ̆$j82+"#4eC9%^HM`w2o8 ZbLvs +h< MŌXʥeP@Bs-v+{($MH[-IN3H6&y/+W@kzRg +|CI?|KKK,..RU"2έVDHeIǖCIOIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_memory_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_memory_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_memory_info.png.svn-base (revision 850) @@ -0,0 +1,10 @@ +PNG + + +IHDRw=tEXtSoftwareAdobe ImageReadyqe<IDATHuMlG̼z8 %=IJ"HSz( BD@[$=7jTJU!B[Chs=$Nb7~pX7N)yьfF<4#Kv{$qVm i0hߟֺ28zί·az.u!Ib$FkL6/@FigţkhUh4~q]o4[Ik4M +o;]ϾJRR`(Nt“3;^{W~֛=&ajNZiX4s8t`R+ofs-sG7fvL}̥/crbȕG%q}N"D j8X]iR3qWwE MS# <a/d}϶^c' '~}+7nWS"0 ]^vۆ JDjM( s=VXQc-Fթ9ڲk0?aMN:˴(AiF /u_ ݈V>2k$18V`~~|_`S7j'UC+p(Ok3BF)7jܨ5YZk|21 +jE2@e}} 3>RQ>Oh(Ҋnb)d|N@[ϼMkdV4Ea]Jv̕Jla +mÔpAhZQ\&q"BcڢމAkD)\KbR\ƟUXW#(ϠE"Q,Z\_m SRlɃs(JZH)T @86_xt@kP wUНP +|iJ#(ȹ"%r!KZRXX*@=> +hmRHd~aT!<00HA&r;z;8˗v ye8llX 6ô[*Jrְ2y&x1ľlodmAz'a4kaDݏc 9`#M6uG:ZMs^ƆͲQĎRp^b!NrgEO+4B<%s-q"D:yYhJZuu=l>wR?u߀Z+EݘJ&:HN=ݫK?m|&Vz/[ٟDe%E S#9^9غ73@$ISo~nw!LEp|u}my_Eֆ > H +F|`~ZN\j۝Rc{v1Uյnr$$QZM@ˣ~Y+o=v|s&b(࿌Wgd[] IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/device_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/device_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/device_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,7 @@ +PNG + + +IHDRw=tEXtSoftwareAdobe ImageReadyqe<IDATHŖ + Ep7`FrFԄ(~/^wHD7=s5 +N2Y+2P5jl$e[vd+miK>P+p+d$d xdHĥu/S^d6GŔa>,)+srR +f1IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_selection.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +PNG + + +IHDR UNPLTE000>>>AAABBB:::;;;<<<===;;;EEEGGG⽽ǐtRNSdkҾA pHYs  uIDATX CQPPQFCf +|lzy#YΥ;ip԰P-qqlBKlԄZhZhZhMyl)eb1~eϔIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/theme.plist.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/theme.plist.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/theme.plist.svn-base (revision 850) @@ -0,0 +1,106 @@ + + + + + Enabled + no + screen_width + 1024 + screen_height + 768 + screen_textmargin_h + 10 + screen_textmargin_v + 10 + screen_bgcolor + #222334 + background_pos_x + 50% + background_pos_y + 0 + logo_pos_x + + logo_pos_y + 3% + logo_bgcolor + #000000 + logo_transparency + 255 + devices_pos_x + + devices_pos_y + + devices_bgcolor + #222334 + devices_transparency + 0 + devices_max_visible + 5 + devices_iconspacing + 20 + devices_layout + horizontal + bootprompt_pos_x + %50 + bootprompt_pos_y + -2 + bootprompt_width + 50% + bootprompt_height + 20 + bootprompt_textmargin_h + 10 + bootprompt_textmargin_v + 5 + bootprompt_bgcolor + #222334 + bootprompt_transparency + 1 + infobox_pos_x + + infobox_pos_y + + infobox_width + 650 + infobox_height + 406 + infobox_textmargin_h + 10 + infobox_textmargin_v + 10 + infobox_bgcolor + #222334 + infobox_transparency + 10 + menu_pos_x + + menu_pos_y + -5% + menu_textmargin_h + 10 + menu_textmargin_v + 5 + menu_bgcolor + #222334 + menu_transparency + 1 + progressbar_pos_x + + progressbar_pos_y + -30% + progressbar_width + 100 + progressbar_height + 40 + countdown_pos_x + + countdown_pos_y + -20% + boot_width + 1024 + boot_height + 768 + boot_bgcolor + #AAAAAA + + Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/device_scroll_next.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/device_scroll_next.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/device_scroll_next.png.svn-base (revision 850) @@ -0,0 +1,6 @@ +PNG + + +IHDRw=tEXtSoftwareAdobe ImageReadyqe<IDATHŖ @l6hGjG!< >W ! 8<D`E|/1A9N$"pq 9Iy +q\+"M I 4u)FAZI*hY pI~L?""f~U,̯%g\2gܪ +f{7IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_help.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_help.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_help.png.svn-base (revision 850) @@ -0,0 +1,15 @@ +PNG + + +IHDRw=tEXtSoftwareAdobe ImageReadyqe<QIDATHK}iWw{٘2c)cЀӘZci41.M*$Ekh&D#6_l `Tʄ)-0f;,w]?lIΗ<{^1rmZN(PZ>GܕJ%cH16 +q +*  Q! W B*.3}3eO9W$R +L:ΪZXtRØt,]Q޲ey7'9T1XAJA.Z׷M{elOi'~AZC q<(s:F!pc%8–w΅B#vƛog< sw_-+hh +[YdZ+3GލkƉEԉ7myET![hT=oơO IJ2pXF3%uLSLV=[R%WHo]4]Z65ŌܚfWi)d ɨv_/Љ;sJRKCl={mi]h]y\7S|gߞLi!ڭcoV0* +=K9J6wGrjlL#!ym$-ޞX7/NqWO_G3óMc eqO7 ]%Ns|x\+*¿^H{\֦16:]PZ! + LJcXyk IVwCc ,=RRHGtJ"R(ZQ}讛%{*!up)xA !ͧ℡!4 +U# )PݝY[۱[ΐ<,Q5 +AH9 +W~P\ӕKik(]*.( H$ dWߞBKR?~dZC0G19_ԕ{|sO'S]o!(A3<,^xS"݄Qgo|cXݖg:w\ߚ6vcU6n5(we8c;77{yzC5]n{Cb}-~ؚH,ZɥQL8묅GK.-3U*OK!$7xpE6d{x>ALch`M'PRc_ټR=/ +6hPi(%%l/@mlmc:9/195@^G+\{k~ǯO^/ +26Un$*q( Zo Xľ/gG[<<~7vg,G{O.AqwK~d_8xjQEg/md=ҙpqjoRJF/4Z;Q|97ʓWK+.0[69iKە%.\y\J}@iH)GkGalq¸*o {M{hIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_ignore_caches.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_ignore_caches.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/legacy/.svn/text-base/menu_ignore_caches.png.svn-base (revision 850) @@ -0,0 +1,18 @@ +PNG + + +IHDRw= pHYs  IDATHDž[h\Uϙm6N/&%F`/hԪ֪ +(4>O(T +R1ZР--\;{/&3Mڴ.X/sX__[?*n] +Xũ!sq?c0/,9>2K+.hjldv?aEL&:&&so~z9r +0RN5s/^޵]9R +%PaPCH 4V 3=lYJXgPy@je'b\R +QTBȠE"j ; +(֭[Gkka!Q_TbwcA, xZHh%SWI +~dYtwwW "JUZe3f__N)TX@f);5!rb*Rc4 'Ϡ~n=PFa%&BjN z +y@U3@DHtSwzh5+c +a*:P ,)/l{V- }E\ChҵKnfACl_|kwCM_W%8zQ瓋 +0%5(B&+Yd=㥐_-MM--㈌oM::)?cqXk(6݄,LD#I!GQNN3'2U헓?_Yd:9 G0A7 }w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  3IDATH +ŕKUAX(.HE+h#T"jզ?(.ZM-,@m2 jkPdAC\Ͻ"̜oy=̜[*m~xCa`X1 a +cnKA54ns[S{}AգPD'OƥVzmY"?hAp|=ϩ;Mdwt-xKpi<_?F0@jE8NKϊnK +kW.@, +3׳ |N8 a(܅ +;xBI@9p 9Z¿ %x7X(C%y} +^uPX/9ϢEFa\ .[`5ı؆E&dm}8b0"Yh;xKϊ4']=Pp; f95Љxb i)d:@UʩIWs5 +us?.rѓzOB8Ehka?*sIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/device_cdrom.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_cdrom.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_cdrom.png.svn-base (revision 850) @@ -0,0 +1,31 @@ +PNG + + +IHDR``w8 +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs   lIDATx]U,(sMLm%JR&%bj|Ąsj & +MH +LP|Wk3=q?{Z>w}M 4h2d@&M L LgJb.q8W-K_xE=<*qZ|@\$y"SqGRk:M eD?.׈^ฌ|.wL52Tl;3w%jWoe'ݳo4e`"}^dMSu=ZЄ,nUdψU'?/ᖢyI|Vlpl/O\ϊUHMCdu2# yO*>&ą,mia,6SYW/EJ};"Oq-lvD|Ճvb)N).ŢmŲ|MSI,4%X$oȲQ5o4JLSKx7tQyQoC]_\)>$"sER1Od/ۙ?9YO:"O~6A|_?yJ>a,65KMhmXkRSd_Vdob*6bnA Vb +)D~] K-CE>ЈV4s-T|+zbY_oS`yPƗUO|V4OWM@fBe +4<v';DO|9&`~[̍ +-CN 9ˋF9RUqf\.ظltBܣ m@,Mr@.*by+zxL("O3<{OωO?SG[Go-5 Ē{s&2v=#S!>*N(a,6R:4#b"6o\e{$b(#MY95"&Q%֣5VLlo(rS:CpjGv_B3c&?f b#Fo )Kd ؜Ng[U{ARMW]ьv bƐrT6ɲQfLu^} +g]nb$Vo&DքWxC=Oc2Y@ +9*A>8Zv_/h~߱=1K b%TrDz-rH]'᭭:i[Us꠳Q]hWrSp8 G|Jk̸~рX'{LnR&Wg#w\L9cxZE޼.@KЕ 1 fbO'W+ftqj]8}9_i۠}b.>ߣMb3@YWx +ff}(8?֏j)b"b&9 +/v*[sB?ұf@<Űm+2̺gZ~R;M]\<㊚ܣ mb;9HşTwY;/R;j=61~z>Q*4u{0llNR g."d; +f5Mf+jTF',L|YX ro>njxFva3rE + pzcG+»/[*'g."DC)ogcR64zHŖAH"52Pd.eB?̴ mbK đH`WB\o3euj@7BWC*TOR6v 8޾ٗccʌ ΫO/|Ima,=Q̘`%(4+!G4{Do& h9 +{¦֣f29!7yy 6$TpfqfC`xXe cա1uCL#'a<=1 &ܭO3<{5f}Rl3U>rFb}yt4`&IH>g"uhB1gl(!z¨]LfG|" 9hCKjA;1|EKl<ەX&rK ++OK^[~2ډa8eOi 8q[ĖȲ2>-1ݢW4T jn_yə ՜ERGŸ +NOvF\,VmhC?ٱU'4m^EMd%z|-mqxF,;W[w_Q՗p gjqqF\&e}K/^:MMƠ*VkE&"g1voyȱDRu,Xd{$p4[ "gzRdB4h2d@&M 4h2dv?QYUYvIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/progress_bar_background.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/progress_bar_background.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/progress_bar_background.png.svn-base (revision 850) @@ -0,0 +1,25 @@ +PNG + + +IHDRЭ pHYs   +OiCCPPhotoshop ICC profilexڝSgTS=BKKoR RB&*! J!QEEȠQ, +!{kּ> H3Q5 B.@ +$pd!s#~<<+"x M0B\t8K@zB@F&S`cbP-`'{[! eDh;VEX0fK9-0IWfH  0Q){`##xFW<+*x<$9E[-qWW.(I+6aa@.y24x6_-"bbϫp@t~,/;m%h^ uf@Wp~<5j>{-]cK'Xto(hw?G%fIq^D$.Tʳ?D*A, `6B$BB +dr`)B(Ͱ*`/@4Qhp.U=pa( Aa!ڈbX#!H$ ɈQ"K5H1RT UH=r9\F;2G1Q= C7F dt1r=6Ыhڏ>C03l0.B8, c˱" VcϱwE 6wB aAHXLXNH $4 7 Q'"K&b21XH,#/{C7$C2'ITFnR#,4H#dk9, +ȅ3![ +b@qS(RjJ4e2AURݨT5ZBRQ4u9̓IKhhitݕNWGw +Ljg(gwLӋT071oUX**| +J&*/Tު UUT^S}FU3S ԖUPSSg;goT?~YYLOCQ_ cx,!k +u5&|v*=9C3J3WRf?qtN (~))4L1e\kXHQG6EYAJ'\'GgSSݧ +M=:.kDwn^Loy}/TmG X $ <5qo</QC]@Caaᄑ.ȽJtq]zۯ6iܟ4)Y3sCQ? 0k߬~OCOg#/c/Wװwa>>r><72Y_7ȷOo_C#dz%gA[z|!?:eAAA!h쐭!ΑiP~aa~ 'W?pX15wCsDDDޛg1O9-J5*>.j<74?.fYXXIlK9.*6nl {/]py.,:@LN8A*%w% +yg"/6шC\*NH*Mz쑼5y$3,幄'L +Lݛ:v m2=:1qB!Mggfvˬen/kY- +BTZ(*geWf͉9+̳ې7ᒶKW-X潬j9(xoʿܔĹdff-[n +ڴ +VE/(ۻCɾUUMfeI?m]Nmq#׹=TR+Gw- +6 +U#pDy  +:v{vg/jBFS[b[O>zG499?rCd&ˮ/~јѡ򗓿m|x31^VwwO| (hSЧc3- cHRMz%u0`:o_FIDATxb` '3,""IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_boot.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_boot.png.svn-base (revision 850) @@ -0,0 +1,25 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDATH +/AAA h"(QtpBC"rB9 + + +B%t:BAq|{;ٹٻC%7ΏMl +UC dycOMSWN@9ؚIn\cUڊF6 @}JkMD3PX8iH̦.<pv.ɗbJܢsbIpo^œb14WdNbpA 5F7jHZjӜcy(17ϞҎ-h 4Z,:`MXCKXbƍi-x/ L^ ݠh⦕4#K:h*IZ=0v4 +S7zEx[=}UA,2 EFH^51#\ +ŮWmu du(3}2}Gߞ}{??NBވ IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/progress_bar.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/progress_bar.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/progress_bar.png.svn-base (revision 850) @@ -0,0 +1,25 @@ +PNG + + +IHDRЭ pHYs   +OiCCPPhotoshop ICC profilexڝSgTS=BKKoR RB&*! J!QEEȠQ, +!{kּ> H3Q5 B.@ +$pd!s#~<<+"x M0B\t8K@zB@F&S`cbP-`'{[! eDh;VEX0fK9-0IWfH  0Q){`##xFW<+*x<$9E[-qWW.(I+6aa@.y24x6_-"bbϫp@t~,/;m%h^ uf@Wp~<5j>{-]cK'Xto(hw?G%fIq^D$.Tʳ?D*A, `6B$BB +dr`)B(Ͱ*`/@4Qhp.U=pa( Aa!ڈbX#!H$ ɈQ"K5H1RT UH=r9\F;2G1Q= C7F dt1r=6Ыhڏ>C03l0.B8, c˱" VcϱwE 6wB aAHXLXNH $4 7 Q'"K&b21XH,#/{C7$C2'ITFnR#,4H#dk9, +ȅ3![ +b@qS(RjJ4e2AURݨT5ZBRQ4u9̓IKhhitݕNWGw +Ljg(gwLӋT071oUX**| +J&*/Tު UUT^S}FU3S ԖUPSSg;goT?~YYLOCQ_ cx,!k +u5&|v*=9C3J3WRf?qtN (~))4L1e\kXHQG6EYAJ'\'GgSSݧ +M=:.kDwn^Loy}/TmG X $ <5qo</QC]@Caaᄑ.ȽJtq]zۯ6iܟ4)Y3sCQ? 0k߬~OCOg#/c/Wװwa>>r><72Y_7ȷOo_C#dz%gA[z|!?:eAAA!h쐭!ΑiP~aa~ 'W?pX15wCsDDDޛg1O9-J5*>.j<74?.fYXXIlK9.*6nl {/]py.,:@LN8A*%w% +yg"/6шC\*NH*Mz쑼5y$3,幄'L +Lݛ:v m2=:1qB!Mggfvˬen/kY- +BTZ(*geWf͉9+̳ې7ᒶKW-X潬j9(xoʿܔĹdff-[n +ڴ +VE/(ۻCɾUUMfeI?m]Nmq#׹=TR+Gw- +6 +U#pDy  +:v{vg/jBFS[b[O>zG499?rCd&ˮ/~јѡ򗓿m|x31^VwwO| (hSЧc3- cHRMz%u0`:o_F IDATxb` 0aa蕮;ŌIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/font_console.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/font_console.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/font_console.png.svn-base (revision 850) @@ -0,0 +1,55 @@ +PNG + + +IHDRZvh pHYs   +OiCCPPhotoshop ICC profilexڝSgTS=BKKoR RB&*! J!QEEȠQ, +!{kּ> H3Q5 B.@ +$pd!s#~<<+"x M0B\t8K@zB@F&S`cbP-`'{[! eDh;VEX0fK9-0IWfH  0Q){`##xFW<+*x<$9E[-qWW.(I+6aa@.y24x6_-"bbϫp@t~,/;m%h^ uf@Wp~<5j>{-]cK'Xto(hw?G%fIq^D$.Tʳ?D*A, `6B$BB +dr`)B(Ͱ*`/@4Qhp.U=pa( Aa!ڈbX#!H$ ɈQ"K5H1RT UH=r9\F;2G1Q= C7F dt1r=6Ыhڏ>C03l0.B8, c˱" VcϱwE 6wB aAHXLXNH $4 7 Q'"K&b21XH,#/{C7$C2'ITFnR#,4H#dk9, +ȅ3![ +b@qS(RjJ4e2AURݨT5ZBRQ4u9̓IKhhitݕNWGw +Ljg(gwLӋT071oUX**| +J&*/Tު UUT^S}FU3S ԖUPSSg;goT?~YYLOCQ_ cx,!k +u5&|v*=9C3J3WRf?qtN (~))4L1e\kXHQG6EYAJ'\'GgSSݧ +M=:.kDwn^Loy}/TmG X $ <5qo</QC]@Caaᄑ.ȽJtq]zۯ6iܟ4)Y3sCQ? 0k߬~OCOg#/c/Wװwa>>r><72Y_7ȷOo_C#dz%gA[z|!?:eAAA!h쐭!ΑiP~aa~ 'W?pX15wCsDDDޛg1O9-J5*>.j<74?.fYXXIlK9.*6nl {/]py.,:@LN8A*%w% +yg"/6шC\*NH*Mz쑼5y$3,幄'L +Lݛ:v m2=:1qB!Mggfvˬen/kY- +BTZ(*geWf͉9+̳ې7ᒶKW-X潬j9(xoʿܔĹdff-[n +ڴ +VE/(ۻCɾUUMfeI?m]Nmq#׹=TR+Gw- +6 +U#pDy  +:v{vg/jBFS[b[O>zG499?rCd&ˮ/~јѡ򗓿m|x31^VwwO| (hSЧc3- cHRMz%u0`:o_FIDATxVי?Td0l2+CVDdX+& +A nfg]q6 +Zk~dC!HpC(!dlZc5fL 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btEgι7R?J3k~p]7<<u]9ݥ_G|O3"Y.Fo8~q]vWs|bHX?\*UGo{,Ym7H5- )9ꜻغ9j񶢗 +||W4 +|S}M}=U+4o0Eo{S\nmԛ s>5MflfE ˀw3 p+O%>\,qd?/xWoD)Ojߔ@NY!쑎{LQ"6޿Wgnl.}UА>$Zwc3,7*@S`CFלs9t3x~&k(zx=?%G߀'O#o*|Wok$>D"]qkt.<>=<;[u`S=';>qνo8[tFe`TplIo"JRt2]YodT)9Yg6Efk̯Wւ9c9a~N5[K9Q$p`|*-Ҷ4GΦ7ͱoT6zl4>f[9ZiXA:du0P걶hR +6GOHJo8 >G +[ȑϓ_z#srx"#z~gEM^B Z7fo{8:ۧ0uP +<"@|)yG&F:Rv+Ԟ+ۀ~x32o һ`԰z*}!Zi9 !B>nXvM)8{wA_?Tdkf./=Ϟ"rsk ιGsCEe$'sIXIۿf&9QEJ?ιTҸm"U.D/Q?c&CE_q+w9!|'Wl͓ +ONlsmuNEUTїFtE%@ +S5]J[hk}< + }V!OKws?~EUTQEU6BE]Zl:ŸIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_verbose.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_verbose.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_verbose.png.svn-base (revision 850) @@ -0,0 +1,23 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDATH +JA1``%PB4My_@ADVQl2Ub}er|wf9ݹgfk6[ ]` hpp +p %3ܖ%2\8zn@QձsHZ'ebj9jd\ACF`5 aWCfdIZ+%1~(RnB-eGVSK+9x3~1T-ZjxGw[C0)4JmyO# +eeiyfsrTYX"Bߧ [d$m2ͰTFI ++}TaάA'_;QЬo?H3_ͺX`|_3q9]&xuwV,l_ +x':~) z]Gc <^jus[ +2oѶ}n9%H먓IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/device_ntfs.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_ntfs.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_ntfs.png.svn-base (revision 850) @@ -0,0 +1,37 @@ +PNG + + +IHDR``w8 +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k 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@1,g}e&|s`2Xb\UnEg@!n0S?saN:v''<2n)|c0\́܅9Ǵ_݊[v<|)+ӗx ߍ9Hhk +#Rv5$<ބ\v[%>10vs0:߅ޢt ezY;c\wvE,V~EL%6p$}ײ?0^ozOJzrE=7}g?8FN~ +\aۡp2:g.#Z/gmþFAIrvc4֖hDKz΃ԋاm& B-,H8#&3DZ _5XyerRouGD]+/B;" $c:>טmf( (-Y8-p7/XZWGN! %΅`h>c1{~P9b&FS%eOãPk9v<%Lgt>hDQ;F5Z@8vfC5wlj$ >OύL9on:7}lvд5]Wk-}ҷF*X u![:,:C6b8cc:p"LI +ɘ^ DO!n#MVCש/@,^qE.6z0.1^ܻE=2@/ 2@/ 2@/×K?ioIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_single_user_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_single_user_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_single_user_disabled.png.svn-base (revision 850) @@ -0,0 +1,24 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC 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=================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_generic.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_generic.png.svn-base (revision 850) @@ -0,0 +1,31 @@ +PNG + + +IHDR``w8 +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs   IDATx͏TU@a`"+@0qA$1 ]!゘…K&ndHtj3&DI0IÀJ7_3眺TݾU7y:_<Թ76m h3f@6mn "` . #W@0F6`e ) 38`4Κ4 Ȏ~lA?;|}Z#kA c }]( A'=rMckPpMN%zIn#k Qp-;UMre48$ +_[ +6յ6xCom`իw1ab2q>U*gOw]UEC] U/ӗ>wcT#w5,CePX7rWEMCa*?Fen3PWJ`y7`G_o{p?uc@s$8΄#ς[@ާp6ieE)̸䞜ͅ9rb|oq98r-GjR[om;!1!:m٤5?Ģ^b}Wsbnn;/i;/1ئ941 =ugAtS,ԘlnlSж*懙1)_M{ĬF8nm ^wH*TaWChjM7Gy.>\WRE|ՠU1\Uz鏼,OVW'uXTZʦV5JVuVcfYOK%51(Yz ?>4E5lr[Tg=/~MP7 +E5lj713g;&';Q)raއnbf]֪ͦ~D ʣT =uر|T,5] +<]z.(R1Ԧp(3s*Ɉ]d̰TŴrsfVer=F KUL[,\TY: TKLd{SL[,\T^)<eg"uRˁzYlfȈ 3FMV6|89ɌK^nr M-jJ0V{hA{-0RWYj\)|5%ͽn"fk x>[v_y^䶥Wi Ď<:o;&qmƖ\BՐS{~"y6Af|[oLcLr{*QM +i >)7'\Lrs.f)f<}aA\c0 r 6} bk=S&79xz\nЋ!Ğ]]^oC_A$OXVclwll]J|>oW8ș{p?uKHgIp| xh|< bOSxxNX* X܅u1-NM?XP)90Vc+d[*^բ2w +.^wx2}s0F/Eհ = +.಑0>C_ߪr@m@O;e4XfcjN_σIS摁u+~3OAի~rl/6@uuԝTR7Κ<aLjIh . `ݦ΀Z6m h3f@6m߮^Z|IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/text_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/text_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/text_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,20 @@ +PNG + + +IHDRa +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDAT8NQF +֐XTב'0Rc  +[ 0D~7Ľֹ5{7H\nnw`*_)ެڸ,O5XIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/device_fat32.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_fat32.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_fat32.png.svn-base (revision 850) @@ -0,0 +1,31 @@ +PNG + + +IHDR``w8 +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs   IDATx͏TU@a`"+@0qA$1 ]!゘…K&ndHtj3&DI0IÀJ7_3眺TݾU7y:_<Թ76m h3f@6mn "` . #W@0F6`e ) 38`4Κ4 Ȏ~lA?;|}Z#kA c }]( A'=rMckPpMN%zIn#k Qp-;UMre48$ +_[ +6յ6xCom`իw1ab2q>U*gOw]UEC] U/ӗ>wcT#w5,CePX7rWEMCa*?Fen3PWJ`y7`G_o{p?uc@s$8΄#ς[@ާp6ieE)̸䞜ͅ9rb|oq98r-GjR[om;!1!:m٤5?Ģ^b}Wsbnn;/i;/1ئ941 =ugAtS,ԘlnlSж*懙1)_M{ĬF8nm ^wH*TaWChjM7Gy.>\WRE|ՠU1\Uz鏼,OVW'uXTZʦV5JVuVcfYOK%51(Yz ?>4E5lr[Tg=/~MP7 +E5lj713g;&';Q)raއnbf]֪ͦ~D ʣT =uر|T,5] +<]z.(R1Ԧp(3s*Ɉ]d̰TŴrsfVer=F KUL[,\TY: TKLd{SL[,\T^)<eg"uRˁzYlfȈ 3FMV6|89ɌK^nr M-jJ0V{hA{-0RWYj\)|5%ͽn"fk x>[v_y^䶥Wi Ď<:o;&qmƖ\BՐS{~"y6Af|[oLcLr{*QM +i >)7'\Lrs.f)f<}aA\c0 r 6} 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|>rO/ݿ8? +䎻Tp$a?Gkl)?ʞ5 +.L|hɗn(ӟ?PPȹ1B[g^%U؋c[Sk*|Z=_eAn~ڍPGmL4}\<υ> nq1}4r}{pKaMֶϑ[{:l/ʐ*"PJ'g4/ek +G &<!BBkqGdl/@,ڃZ=1?,!N");a5,4qO*xsm˰,Y[n.-Þ5e}>7n*Ie'akqW:(Ԓ{sKAʧ=k .fp*P;q?6Isk a Ϟ*7z~>xRAJ83O0Y%BOb؃{fJQ!wAX8][GojATm˞Uƍ$7P]KʠAߵ׽f U[EԹVݻ_ۂ -un[%RKؚл zl&pMMFjK]ֻ^:7cB+o _ +PןTmӞnf܀7Xզ]9/m}M$ o>?qmnRgun\svcl(²:J5tFcx;H +ĵY=HٻRԹ^x<2ek"IQEZ\ۃYjL +ͬ6]x5vTjV]ʁk xlaMA +ޕ +A8q3p~Uo v#=5BĵczP~C=8,CkuS?jMاO2z +ax%< ~>hk=kr^>up"u ݔ}!Fr۾?ΣàcL@69k +a֞cY`Qa*w;W|(sIX(>FVuJ~rbM!S6*5BK3XoXx||}F?'mujn00͡|8SkcZs.gM!xs/"r=OPfn'mVyr1l11ggoQK~.%i sh_b|)ggoZ DXsI\o=7|)k ߊ6\Sߧ-=7mED%YB,ANh2lS1T kB/>ړa 8iƺ8*+ˎ_Avin_XS./{aOڊӈ撺Y,g7PrsJ5%=mۻ0rgq >5:f.eܭ̯=hپߥfԭW.w1缩5o`.1ܭ!w D|1 }]%9[*7S0Ws6\kA]`C|O\͒X.^V=ۺ٘ZۿkaUnAg߼uZXSk=^9VVkTpp3J~:duX7F[}k{Xs2O|m]Hc0 p,;P +a*| ." t/Csa7P8;K♓]hn-YS]NgBQo6` cyGk +.\B/; +fA_QG1n0n83ۊ`vMa7t({:N7F[}[hR mMλ9 ]**d~W:otv#.7ù,lc躺 xbN`o*ݯj\Y^p%luӍahEu8x,< 8q}΁ 8L7 nFs H跘xo' +gF?R: 7ˆn/ ~[p +nS_U߀PӁN:tӁN:tӁN:h#؈ IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/device_hfsplus.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_hfsplus.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_hfsplus.png.svn-base (revision 850) @@ -0,0 +1,42 @@ +PNG + + +IHDR``w8 +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs   +nIDATx[Ui-Zh +E$j@&Cl0`#|1X-4&n&=Ahm[[(V#C+k}Ξ9OYZ7׬`PAT`PAT`PA +LD OC3p&<΀ ߂]`ς“ eX +O;Ju,Lρ';:wiys}M9Imess4׾ Yg܉ć +09 sˈX\͹oN!'ڽmX2B0}01cPZ՜g} PLu + cpyx7e7cP՞o>%雪L!\݅ S[ +烚n)ށw'+`Jv~&:|C?_\{6csk0!/jؤCAEbc?W_ ˿YvGMj ac +E8h(2"L̼u$7E0sJ֤5HN_lOܻ,5o,v|Ƹ vWȜ-Ϛc2SBn +kN|U$ʮ[Zk8!%b}GX~Hmx:507sLi6b.z,Dw)ؖUeL +WQ"U_ja5ExN_G_0m̜*/Aa g`|Vӯ55}j +4U1u;G5=1ptyc9_ey/8 +$=\gc{61>%^Vx'~ }x/,.8/4Wo=-i̥ s5bLhs,c9P|y$pf|ynqmsp~%tΥaq9!cHͷV=U0p7Kh3h{7l~Yhy)7\̩ s6kezra,yAshL}m|\s12|l[+k3Զn%}SH4V]hT9aZYJLgqH }(0FVi{~ +`Yp7bWZۂ ɴe~N`nM X{4's+SYOU2.ʸUԹˆPKݶѡa +bYe~ +U>nχhg?疰M,$uf kfs4_ao^a(hO:O;ܭA eQH‹w@x[6KP6p>3N+@šKOu.aGXck&MqaˢQ2smbmXn~sSz}o1ճ r٭s>D= WgiE6ilgXnarSԗbEoP٪A=k3[f :@5kOcƦ=ٳ/f{ndz +s3wk5vYԹ~40RtVϮo8>;Fan~u.??<C-?7o'N,ܭA ,d5p^4={l hŰE0's+ܭA ֬rU +S n coFF9]Ϩ?~BO)5p>}sẓP|9-įeL=k- ̨;ǹt |'${1i+`Uw2;|x:X|AznE2taU0[ +ᶲ{wNqBaLc!-Snp(R<$}\ZHʽӤK;"㫌]/`/}.ƨQI QV$y+RvFajc:9Շ +ujV{Ҩ=; Xf }K~2p_? N{Ǐuv7nX3]8q7 Ss:.p*ZԤ}Ǒ2~=UVZY^Umtэaah E[:INeЩ|x<{8q}kn8 c),9a&[L7]guB?RŲG@^̀Z|êo@ `PAT`PAT`PAhO'`=UIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/boot.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/boot.png.svn-base (revision 850) @@ -0,0 +1,42 @@ +PNG + + +IHDR``w8 +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs   +nIDATx[Ui-Zh +E$j@&Cl0`#|1X-4&n&=Ahm[[(V#C+k}Ξ9OYZ7׬`PAT`PAT`PA +LD OC3p&<΀ ߂]`ς“ eX +O;Ju,Lρ';:wiys}M9Imess4׾ Yg܉ć +09 sˈX\͹oN!'ڽmX2B0}01cPZ՜g} PLu + cpyx7e7cP՞o>%雪L!\݅ S[ +烚n)ށw'+`Jv~&:|C?_\{6csk0!/jؤCAEbc?W_ ˿YvGMj ac +E8h(2"L̼u$7E0sJ֤5HN_lOܻ,5o,v|Ƹ vWȜ-Ϛc2SBn +kN|U$ʮ[Zk8!%b}GX~Hmx:507sLi6b.z,Dw)ؖUeL +WQ"U_ja5ExN_G_0m̜*/Aa g`|Vӯ55}j +4U1u;G5=1ptyc9_ey/8 +$=\gc{61>%^Vx'~ }x/,.8/4Wo=-i̥ s5bLhs,c9P|y$pf|ynqmsp~%tΥaq9!cHͷV=U0p7Kh3h{7l~Yhy)7\̩ s6kezra,yAshL}m|\s12|l[+k3Զn%}SH4V]hT9aZYJLgqH }(0FVi{~ +`Yp7bWZۂ ɴe~N`nM X{4's+SYOU2.ʸUԹˆPKݶѡa +bYe~ +U>nχhg?疰M,$uf kfs4_ao^a(hO:O;ܭA eQH‹w@x[6KP6p>3N+@šKOu.aGXck&MqaˢQ2smbmXn~sSz}o1ճ r٭s>D= WgiE6ilgXnarSԗbEoP٪A=k3[f :@5kOcƦ=ٳ/f{ndz +s3wk5vYԹ~40RtVϮo8>;Fan~u.??<C-?7o'N,ܭA ,d5p^4={l hŰE0's+ܭA ֬rU +S n coFF9]Ϩ?~BO)5p>}sẓP|9-įeL=k- ̨;ǹt |'${1i+`Uw2;|x:X|AznE2taU0[ +ᶲ{wNqBaLc!-Snp(R<$}\ZHʽӤK;"㫌]/`/}.ƨQI QV$y+RvFajc:9Շ +ujV{Ҩ=; Xf }K~2p_? N{Ǐuv7nX3]8q7 Ss:.p*ZԤ}Ǒ2~=UVZY^Umtэaah E[:INeЩ|x<{8q}kn8 c),9a&[L7]guB?RŲG@^̀Z|êo@ `PAT`PAT`PAhO'`=UIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_single_user.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_single_user.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_single_user.png.svn-base (revision 850) @@ -0,0 +1,19 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDATH +ŕ;/DAz&D-$"QFFlZ= +@R$BB㑍ͽ9;w%6Nsfݙ97UЯeFZAvp' hN1-ۚ\7HZ# W4Z5+&{iH+f@NhX!~g!$tNPiI3>_i -ifz`xǽqkLߺҒf@|q]cPcd׷Ni+q/2Opo XO U/6^ohcB_\SiSaŞ7f֍ӾW6s|tvZ7aYE#Je{ r2M.Jsk0 m ZhJcA*UT65\ ik- [N{'_?m~ bE}IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/device_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_selection.png.svn-base (revision 850) @@ -0,0 +1,69 @@ +PNG + + +IHDR``w8 +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDATx[sGhw][[& q q$%T(x!7bJ*µM +)$KٕV?;=ɒjgvWvҸ{rN9}wlV +C 0N2Lenb#͚ym{Dya(e[~*̎[F7m>bNkDu;6/YE E#։*l~qԚ5[K֜|{gmȷFu8_zWxn[&FbNGwb;pނ7j81`Mʯp;E1KK]fL[6Slvc[l'"r'ꖃ6kmG;]tjB7\{ȟ +u w۱y3":Ry'b-ir>kރ/WwcVP N"0oFo6nHp +$P-uFF$i&m ~ gm{9o~("{"#L&6&, @a +:' Z&8 Sܽ +#_ֺM]~7z@yjYR[ĽT.~>1@MB =2RN`ov9nWǜAs(xۏ`;mHn'a|hdBKQKϫ%% uoK5{+d~'&'#+@ &`(xna"O\>hLgq2slvsG_{l[eR  EUoů#\|=ƨxe{k6maX.ih +؍[mg4jw^>d.A,v~-}$W&~/؛g33,ievujv/CKX7`toCc`$C `~Wi۩w3~$ \+cv+ +.nnI_u+c}3o'1XЄƒNǾ{Mp$dLM2B:Srx m iJ,I݊i@ +o~̃^'<$ 2I6(Y#qQxl;+ +;@O!@:!֍$dU2_ +`oqma'6KpDmť</}H2JVl/'ǶY]{;KU{C_}PV!.:6+-' +@j:l'hx`fmieEw/!{99})@+5w!!= UdUPJ!n +Z⊭ܴ0b)d=`0vE_ +8~~-e܇c~S'%H(܃A +$)@)W~@{Ɉ6i9жfݞ&k)X#= K5@X +J2I-p + ގ^O]cO`*f5"[ +z)q?S.uz&EHSv7$ ZPR;&ШPB6u|ESGD/f^5'mW?O{CM_W~tV$ +H.sA`ڝH_\@Dގ}(AzKmv4PnRV t:q=@+@J Q&0t0Up}D DЕYPoWd8K0̎ϗ y9'"RХ˺0h".קSRBwܗ܆):m1N,xA`+Ѓ4rK +s@ w]ws +V3VG +H =„tgɑ+TBsLd/(ܬ"Eg4e>O;ҥ!yX +2:OpmP(^a"lҢK^ qb +ه%^z[@Y f鰚[q8麬 +hP'DAwEZi.ɘK}:76"xV[6> ?Sj𹪎@M\!/ ~a.hʥpAX{'_JjgI zz# cE1!l2bl;kJV7B5.@Vr'Uo\v<19h{LL7`w]ؐ8X_|OAY"OM$W^“N~W]R +hyY~S +>XY>ӹ՝",C{ +js|i0 +N uz! ɥ:a陖^C^~~Zr畡/M'I~3|#,t>R.`1Y ,Wbw?h0WIJz1i4Ń~|u:Dile3rb@go[<q&Ae *oelC}xZβA+{^F;JڬTrwlFv]9zmfU×ckPO% C{*S;UK˒P'GBfh;o\$sD +a =MV/4+9H 0$$&srVMiPP5_t#aW֨~UvUe K5"Ka7}e1/SV{s|\녕uS+諞v^LG$q֨Zv. +W=4ad[y.4]n ݓK*+NjLl^Z uz$^zD3raqrPȥvxzrՉzeB:C9Sm;`$Beexz<m[&MWV~W3,3.pVO~N/ C +<"3wD5F`Jh @7UX +&o)ěZvI<)L)m[8_aLw|,MG `zX], +t7Kat9!ޅ,_]&EhRxLu{=EG":-}2.a +_KRW`5rv +O0Y9E_o?T!h[uj+%J'q;RD_nG߹{EXHFTx>vx%qw ?Hݕb~ޢ~&)sկ۫?b(JGdtǎ8u3 ,D +(whzJNO8p$L+!E1d':. !ܗۨg鏌cwU*T70s + wybD9:JZmXw5cƙ9>>u֗$s΄e@^\Qs4]J hu͟WЖU_נ>g x'd:3d|Ǯ{|%T} +-!\ W7?z4IF*m"_w[n٥NNb)a/-_B,$dy +D8?fx5~UHdlQJA68DӜ n/_f%8 Y$d_4iUtcm>D[|/R%`B@_AH&ϯW,[ +򆠀.}kAX\{/Eíkkb +p始(ٗ^M .հ +57F>T&lg9NsEX]c%,c-)((((((((((((((.PEl +IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_ignore_caches_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 850) @@ -0,0 +1,24 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  3IDATH +ŕKUAX(.HE+h#T"jզ?(.ZM-,@m2 jkPdAC\Ͻ"̜oy=̜[*m~xCa`X1 a +cnKA54ns[S{}AգPD'OƥVzmY"?hAp|=ϩ;Mdwt-xKpi<_?F0@jE8NKϊnK +kW.@, +3׳ |N8 a(܅ +;xBI@9p 9Z¿ %x7X(C%y} +^uPX/9ϢEFa\ .[`5ı؆E&dm}8b0"Yh;xKϊ4']=Pp; f95Љxb i)d:@UʩIWs5 +us?.rѓzOB8Ehka?*sIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_video_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_video_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_video_info.png.svn-base (revision 850) @@ -0,0 +1,23 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDATH +=K\A׏5V),!uB + 6 DHaVK-B V6V`_s'5/<{9sf̽J0} +'\`962 +:Ʊ7+P,ШXkUEhXY5Ɖa1m7gc5)NC7:\9N@ka3 h̓dzo#9UiLCtC[˚v3Z?>ʕoc׷f<Ұт׺NAa +\ufovw۬rbEe19RqkYܰ ,c}2qsMZ˚58xrOX[;-W${9I#_dLLV3NS_1[}pb|2#7idwӒK2hIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_memory_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_memory_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_memory_info.png.svn-base (revision 850) @@ -0,0 +1,22 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  QIDATH +ŕK.A 03 #cL0#v` ޯ{uU5$<鮪m&6 +ZD=Eg}&ds[<~s6ksDO8Z6`U.Go}߫h?c Y& j-5|2dɬmYSJeɬ7t\L̺r E.ZX`?T'8n3d +<[ + SMdɬ: +^1,Kfv_r&C[uNNlɕn~=]IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/device_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,18 @@ +PNG + + +IHDRa +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDAT8= +@Pl%`#X3(Yh5#~/مu#̾&RAZfyK\Φ14մ&GI~#d;n~en<'Q\`}ǧ1oR>H]p=K\"=p3 emPOM[!< aWjvJ?sЦᗒ\_4@)#҃0ӉVA""IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_selection.png.svn-base (revision 850) @@ -0,0 +1,28 @@ +PNG + + +IHDR :Rg pHYs   +OiCCPPhotoshop ICC profilexڝSgTS=BKKoR RB&*! J!QEEȠQ, +!{kּ> H3Q5 B.@ +$pd!s#~<<+"x M0B\t8K@zB@F&S`cbP-`'{[! eDh;VEX0fK9-0IWfH  0Q){`##xFW<+*x<$9E[-qWW.(I+6aa@.y24x6_-"bbϫp@t~,/;m%h^ uf@Wp~<5j>{-]cK'Xto(hw?G%fIq^D$.Tʳ?D*A, `6B$BB +dr`)B(Ͱ*`/@4Qhp.U=pa( Aa!ڈbX#!H$ ɈQ"K5H1RT UH=r9\F;2G1Q= C7F dt1r=6Ыhڏ>C03l0.B8, c˱" VcϱwE 6wB aAHXLXNH $4 7 Q'"K&b21XH,#/{C7$C2'ITFnR#,4H#dk9, +ȅ3![ +b@qS(RjJ4e2AURݨT5ZBRQ4u9̓IKhhitݕNWGw +Ljg(gwLӋT071oUX**| +J&*/Tު UUT^S}FU3S ԖUPSSg;goT?~YYLOCQ_ cx,!k +u5&|v*=9C3J3WRf?qtN (~))4L1e\kXHQG6EYAJ'\'GgSSݧ +M=:.kDwn^Loy}/TmG X $ <5qo</QC]@Caaᄑ.ȽJtq]zۯ6iܟ4)Y3sCQ? 0k߬~OCOg#/c/Wװwa>>r><72Y_7ȷOo_C#dz%gA[z|!?:eAAA!h쐭!ΑiP~aa~ 'W?pX15wCsDDDޛg1O9-J5*>.j<74?.fYXXIlK9.*6nl {/]py.,:@LN8A*%w% +yg"/6шC\*NH*Mz쑼5y$3,幄'L +Lݛ:v m2=:1qB!Mggfvˬen/kY- +BTZ(*geWf͉9+̳ې7ᒶKW-X潬j9(xoʿܔĹdff-[n +ڴ +VE/(ۻCɾUUMfeI?m]Nmq#׹=TR+Gw- +6 +U#pDy  +:v{vg/jBFS[b[O>zG499?rCd&ˮ/~јѡ򗓿m|x31^VwwO| (hSЧc3- cHRMz%u0`:o_FIDATxܱ +0 @Q~7 +kAJ W_$GDЅEocL0tzW;bǨ.E\A? 2lR񒠩tB̧ +ACrБ4A/L'44~!3hh AS#XB2hQhqьiuvݎPIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/theme.plist.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/theme.plist.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/theme.plist.svn-base (revision 850) @@ -0,0 +1,116 @@ + + + + + Enabled + yes + + screen_width + 1024 + screen_height + 768 + screen_textmargin_h + 10 + screen_textmargin_v + 10 + screen_bgcolor + #aaaaaa + + background_pos_x + 50% + background_pos_y + 0 + + logo_pos_x + + logo_pos_y + 3% + logo_bgcolor + #aaaaaa + logo_transparency + 255 + + devices_pos_x + + devices_pos_y + + devices_bgcolor + #aaaaaa + devices_transparency + 0 + devices_max_visible + 5 + devices_iconspacing + 20 + devices_layout + horizontal + + bootprompt_pos_x + %50 + bootprompt_pos_y + -2 + bootprompt_width + 50% + bootprompt_height + 20 + bootprompt_textmargin_h + 10 + bootprompt_textmargin_v + 5 + bootprompt_bgcolor + #aaaaaa + bootprompt_transparency + 1 + + infobox_pos_x + + infobox_pos_y + + infobox_width + 650 + infobox_height + 406 + infobox_textmargin_h + 10 + infobox_textmargin_v + 10 + infobox_bgcolor + #aaaaaa + infobox_transparency + 10 + + menu_pos_x + + menu_pos_y + -5% + menu_textmargin_h + 10 + menu_textmargin_v + 5 + menu_bgcolor + #aaaaaa + menu_transparency + 1 + + progressbar_pos_x + + progressbar_pos_y + -37% + progressbar_width + 100 + progressbar_height + 40 + + countdown_pos_x + + countdown_pos_y + -30% + + boot_width + 1024 + boot_height + 768 + boot_bgcolor + #aaaaaa + + Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/device_scroll_next.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/device_scroll_next.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/device_scroll_next.png.svn-base (revision 850) @@ -0,0 +1,21 @@ +PNG + + +IHDRa +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDAT8= +@_W0x[KvH-x "~/Ⱥ@ȃٝ٤Ej}򞸅 +\\.3dpWr'S=գ/@OuhzIwVY͏ ~q7J2d4X莎`fId +nW0ut" +u6hgΐzK1nJHq)5#գTLǤc Us~sj4IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_help.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_help.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_help.png.svn-base (revision 850) @@ -0,0 +1,26 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  #IDATH +U=oP +A +H +jDapFJ*]Ul"Cj 20dZsLQ39S P +a0VA=y~~˻Ӟ{\jP˃װtAW"yzPxd{:^SZC+E:# +hWص,k4'jMټiN30Wp0V1z\:XRbOSԩ_EMIlƀ]p8N-jJ>zGJlm,Skg0 2\i +\.Rl+/`N fH&z}}?C~W(}"8:|Ԝ%"Zm:BcQ+q^lhl9h@?=rIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_ignore_caches.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_ignore_caches.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/bullet/.svn/text-base/menu_ignore_caches.png.svn-base (revision 850) @@ -0,0 +1,22 @@ +PNG + + +IHDRw= +DiCCPICC ProfilexwTl/]"e齷.H& +KYe7D"V$(bh(+X "J F;'Nw>}w(!a@P"f'0D6p(h@_63u_ -Z[3C+K;?r!YLD)c#c1 ʪ2N|bO h{yIHD.VV>RV:|{ [RF ”"MF1L1[Te'Jx%C%_%RJ#4GcӸu:(G73%Ie%e{SC add1T4UT*TTTUzUUUoScemUkS{Q7UPWߣ~A}b}9Հ5L5"5iјi<9Ъ:5MvhWh~Tfz1U.椎NTgNΌ|ݵͺHz,T +NI}mPw +,tӆF -5j4oL50^l\k|g24mr6u0M713fͱBZA EEŰ%2res+}VV(٬Ԗk[c{Îjgʮ=~mCNNb&q'}d]N,:+Uʺuv^|o]5˟[7wM׍mȝ}CǃQSϓY9eu빷ػ{^>*}7l6 8`k`f 7!p2)hEPW0%8*:Qi8# +z<ἶ0-AQ#p5#m"GvGѢG.7xt~g|LbLCtOlyPU܊|BLB}&:$%Zh`EꋲJO$O&&N~ rRSvLrgIsKۖ6^>!` /22fLge̜͊j&d'g* 3]9Z99"3Qhh'\(wanLHyy5yoc( z.ٴdloaqu.Yf +WB+SVv[UjtCkHk2zmWbuj.Y￾HH\4uލ6W|ĺ})76T}39usocٞ---zl=TX|d[ +fEqūI/WWA!1TRվS疝ӫox4صin={j-n`[k +k+x\S-ۆzEjpjh8qn6Ik:8w7ޜw[nn?uݼ3V/~ڟM~nr:53(ѽȳ_ry?ZrL{퓓~מ.x:LlfW_w=7~oLM˃_uNO=|zfڛCoYož_CgggI) cHRMz%z%z%z%z%r2` pHYs  IDATH +;N17$*( k4t@ r"$jDH-/~Y{mŐed +" ++~-;T'bQnm#qWjTYVQ{BO| (C\} ‚S|MKڌ|qx`w`z"qu&5ßwL٦g1Zoc/N}?-.qV +V3d'Ē<8} +}=0YF{SB6[av=7?V_{MVrtڃy0rT8+I#gu/刈Gb)Y5Ѝ;U,oc&Enei%;5 $IV2̸ _Jطxf6IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/pinktink/.svn/all-wcprops =================================================================== --- branches/Chimera/artwork/themes/pinktink/.svn/all-wcprops (revision 0) +++ branches/Chimera/artwork/themes/pinktink/.svn/all-wcprops (revision 850) @@ -0,0 +1,17 @@ +K 25 +svn:wc:ra_dav:version-url +V 55 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/pinktink +END +logo.png +K 25 +svn:wc:ra_dav:version-url +V 64 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/pinktink/logo.png +END +theme.plist +K 25 +svn:wc:ra_dav:version-url +V 67 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/pinktink/theme.plist +END Index: branches/Chimera/artwork/themes/pinktink/.svn/prop-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/pinktink/.svn/prop-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/pinktink/.svn/prop-base/logo.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/pinktink/.svn/entries =================================================================== --- branches/Chimera/artwork/themes/pinktink/.svn/entries (revision 0) +++ branches/Chimera/artwork/themes/pinktink/.svn/entries (revision 850) @@ -0,0 +1,96 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/artwork/themes/pinktink +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +logo.png +file + + + + +2011-05-19T21:52:33.000000Z +8c305ebc5405e5efebe30470e2e689f0 +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +37244 + +theme.plist +file + + + + +2011-05-19T21:52:33.000000Z +fc18fb7a70e76e59a790b1f3ff86df6c +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +2699 + Index: branches/Chimera/artwork/themes/pinktink/.svn/text-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/pinktink/.svn/text-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/pinktink/.svn/text-base/logo.png.svn-base (revision 850) @@ -0,0 +1,326 @@ +PNG + + +IHDRAo pHYs   IDATx]U?~߼7Of&=!!$PzYDTPV+?u-ww]7" +hB $$s,LB3n=ss|9B +Wz) +LQ`S(nѡ vywbwsGE\r…Y}9EQsǻg|{8<ٮBc Kn޴Q%:BYa=]$͑nQu~=sv][0mֳ)^kU|moZX} +s} G: ,\E-]+??ZD:+_zkcoۀz%>!-ʻaqwҾTWm>qU{fIe`Zu`rO}9ވ(|=ޱ+W^_st"Z2]?7L#SU)~bB ^Ģ;Ŧ*{k`G9D(r9 +;ڕ2WWI+LaKqdH"z#8? +u@D2 Cy󆱨KZ4 +ꬼ9D*&]*J !@oŋvospC~q>sï]EU}<˜t + Yjj (0#WoB_,|4ڠ ~$#Glǵ~2@@כX;- +=9= ̳_Jd>OrCSn/RSjx;miTYWZ}榻fC'"-GN'E.?_r@[BXֶo핗-1aSTHy|>ay|>:fqA`aJHuPWx^@;EvaEy✐kҕlǚ?> +b"כb@D>w5qs7X"d +ǖŁo\܂B1$GTqܼejH xww5#mm!SDPT- +j\Kzxxp> +Wض5E4F49'1{Nb&VZvm-E#'td.- / +vOG! +6=0X2 +Q] G؅h[4-ƶ] 4%D +o DaypoSI ++#Wg}Z4<$@C]1?n\X˜)nnB#z@gF3PI@E/N)P,UQt@:|ݛdСdšHXUUh˅m4FPq +>j-cLz8"{S GOty ߗ>/^_[Ujc_iD(p8Nk6X$| [jE+Ű R!B6 jE-CE鐒{z7_07E1G +,z +#b7\ _aŬ#Kq6nX*ӣA|"Nd 0)^_T`M@X?q!aE) xr@VXv -z&rŪ+:VA|wZO;.ҺrlE_$akȫc\)Ut`Caxoӓ_Fw䅍Jro)6 +vT}Yb{HÙ"K +X(xD,.pOK&\|䄰;:(hP4)a ? @WQ41 +&Nun`g@F7Fמ|)+?ibW|Z^EVrlD.>p@,$ͦ8D¯p@ +iʺfT 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+0z*2?3Rj +lfFB Lw/}UTϏ/YqKK;kU?䑪=tSϣzzYrǿino -3=.\%[ق+KY_.doXǓDŽxo"`ݼ34Q%iNDLFJL4(O=[3hzMo}wf`>`*w˼eCgS?}]7g:gMo>]+[g]*(Ǥ.m"E opu\o4Ul]l]ѻtvȵY"?8my6>uи"C\c$vGŬSf[n=8' +\n]k[s +uui4,v/wՍ߸6]9ZxNd+h(p>]^wT+ſy˾5?PݍݻB~V<ßZm*>5XͅLTSӢ -.Z9.g* +Es=Zc.L&.ѱOʛVb̛w& (^@[OA"kad~ -աmV\jGM{KTŰ/צ3=wF +f,Ed&(ޭ5-_q0bٲwBqL/|jh~dOg^,π:QLE3l_6Y:i +hg;|W<*fV13tW"2#2H3b>p4foF|c87Qhâ#ZQ5Eu]p;!'IYAo +oҢP⃯|3CUQ5Y45u5 +L8 X1NgD@сewx/,.۵){:n<NKG^`l x%D$εw^ʽe<9P|ٲDT;9(lWz~2(@gbccbj +ET޽5)v$0]ߺx6R`8lvbpbP"5m땱^i?~N?HNYV,$`d٥~L_xGd`zM8Ck. +#gFCְ?tBl Gz3@ cWu5nkl* % u:hBWN >;ξ1zhqU^z&)MnUW,,'(Q¨U%szkp+Q}`Ky[y_[~7yU־9O l֠ҪTVUsg~%4ٞuX,n{xw}a —:ɗ"_IĚ5M(uI6>+>tQbWySfN>ѵ ;ʤW#ѱ5Ph\.B a֍%pt_W+P XJw^-SЬjҢS +֕ltkӛ6Jنն R'tn~|o?uٜ{V` +qI(MhnbФKx,WXƋTG)^~`ÿwi2S`4tvW + + + + Enabled + no + screen_width + 1024 + screen_height + 768 + screen_textmargin_h + 10 + screen_textmargin_v + 10 + screen_bgcolor + #FF1493 + background_pos_x + + background_pos_y + + logo_pos_x + 20% + logo_pos_y + 20% + logo_bgcolor + #000000 + logo_transparency + 255 + devices_pos_x + + devices_pos_y + + devices_bgcolor + #FF1493 + devices_transparency + 0 + devices_max_visible + 5 + devices_iconspacing + 20 + devices_layout + horizontal + bootprompt_pos_x + %50 + bootprompt_pos_y + -2 + bootprompt_width + 50% + bootprompt_height + 20 + bootprompt_textmargin_h + 10 + bootprompt_textmargin_v + 5 + bootprompt_bgcolor + #FF1493 + bootprompt_transparency + 1 + infobox_pos_x + + infobox_pos_y + + infobox_width + 650 + infobox_height + 406 + infobox_textmargin_h + 10 + infobox_textmargin_v + 10 + infobox_bgcolor + #FF1493 + infobox_transparency + 10 + menu_pos_x + + menu_pos_y + -5% + menu_textmargin_h + 10 + menu_textmargin_v + 5 + menu_bgcolor + #FF1493 + menu_transparency + 1 + progressbar_pos_x + + progressbar_pos_y + -30% + progressbar_width + 100 + progressbar_height + 40 + countdown_pos_x + + countdown_pos_y + -20% + boot_width + 1024 + boot_height + 768 + boot_bgcolor + #AAAAAA + + Index: branches/Chimera/artwork/themes/msi_netbook/.svn/all-wcprops =================================================================== --- branches/Chimera/artwork/themes/msi_netbook/.svn/all-wcprops (revision 0) +++ branches/Chimera/artwork/themes/msi_netbook/.svn/all-wcprops (revision 850) @@ -0,0 +1,17 @@ +K 25 +svn:wc:ra_dav:version-url +V 58 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/msi_netbook +END +logo.png +K 25 +svn:wc:ra_dav:version-url +V 67 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/msi_netbook/logo.png +END +theme.plist +K 25 +svn:wc:ra_dav:version-url +V 70 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/msi_netbook/theme.plist +END Index: branches/Chimera/artwork/themes/msi_netbook/.svn/prop-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/msi_netbook/.svn/prop-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/msi_netbook/.svn/prop-base/logo.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/msi_netbook/.svn/entries =================================================================== --- branches/Chimera/artwork/themes/msi_netbook/.svn/entries (revision 0) +++ branches/Chimera/artwork/themes/msi_netbook/.svn/entries (revision 850) @@ -0,0 +1,96 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/artwork/themes/msi_netbook +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +logo.png +file + + + + +2011-05-19T21:52:33.000000Z +36e1b0499cb635023563b3382ab7a36b +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +12638 + +theme.plist +file + + + + +2011-05-19T21:52:33.000000Z +30bdb9221debab203e12ce9adc0be048 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +2700 + Index: branches/Chimera/artwork/themes/msi_netbook/.svn/text-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/msi_netbook/.svn/text-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/msi_netbook/.svn/text-base/logo.png.svn-base (revision 850) @@ -0,0 +1,110 @@ +PNG + + +IHDRO?miCCPICC ProfilexKqǿ3a,bVDC2{n{aEWvݕq݊]u+:t^$E/;(i$eDz.ߛyzK|px8ȈBM&$|7[(:Î&eO؍׍V:@UqFz$ZL~N6d*ޔ5Q{)z|\9Ce_ٴ׷ɣWCsa=Y3ͼ>e;F$co`s;:f]i+iax4 na:hUZZ{Egt:Dhs\gwk@O@.fW3M$-zRWyN.U)> aIX|IKhBƓTD3ɭOj-0wӰR{Ud +G- pHYs   IDATxw]Ub｀((VHt7D$b8#"*& (*B0FmTB +^y|s{{1o}^뻿k}=@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2%3p^Z׺f\:dtؼ.ZBe}]v6c_k_W].|)hjJZYѷK4"nhfrfY3"7}RPVG;zQ.]R}m 6}P *[`X +BE-cIRvd~Ң~.ȥ;Zk˽3P°j@-5(}K\~?+G?ǂm׿.괧#7.&7i}{ov7񍱉 Wk׮Og?Laj8(`v/bu{wҎ;$t0 +̗^z)?׿U%-Xe77l+0MQ3j`-xѢŋv[onu+9Xo)`s͚5?_~ER-4bv `e>OU_kmns_p +oxv ,-nt(w ' ko?qQo|'>|_ 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H +_&O2 +\ )6SdݠЎ.`b "hQFM4bq }kh҃vj0` I;ԧpӜ<N׬Ys׻UrE"Qa>ͦ63 +/l6qDrgg2H#Eef;8.J,8O9(07cܘ&M6CivnGvq;c)xAȬl 8^xf&$@x'xpW[ˈp1Lu\0 f;kt!Qȵ1@ +t00VET"eԠrw3f3e3{NI\XFP`G< +uu`IҗČn wNYo30TfP2ƍ}sLQ^S#]h +?r6vڳ:cy326 +TXFd j"doZ0 eG@&oHrp>ʤTs& + +;y؀ wf>7*~pgWЎ =4*ӗ{ro{B) +Q "\ǽQӂj XƗdԘ=٫>-5ywP5rn^98ڲ +^wy#U!Ykռ + +B +xx;܁we`wW5$'>do_xw!L_ Wb+I4:ygtƸ.NM9) ;SȠ%֠?\hlO>d#^x]tG\OHțsX4Mnh۲t%3Uyҥ0ۘ%,NPN1/)/~-#K,gEkݱI l-K.ud&N@$I JzSd\B7LZo[rq82*팙q]B}f9(r.9D>9x`~)&%udPFfv ˎW8g?~Ife;GZFJEl:(k{pLQc=VknO;-?a 0pBrG'=ꨣƒgLv)"Ї&ծ_& + +wjɫ)pCa}/7J8~1r8X|-xєK0 {enMT iy{M;/wqo!a*%LL#$NybB'*n:'.2# I_Ӆ֠&X;C͝혚^-1#`< +=:e/!lwMe _k +Jp2̴]ث˴i*IC[)dJfJ6""dV2r(Ddt7>M }/qg]Mg5$l줻x _7@q++D=ҝ;}C ͈pꄟ?gaYGp-G|S7\L K^.^* +9٠!yTBk8^ BDkٲeǼ"eHLمMz~z 3} +6 +5×OJS| L_%Z,frtk_cj +~Tm5 &h0V KcْMv@ll%6!l~Iqwy}Ċlȗj ː$B5_Y{,E|oɜz3~{ %bY(VO㥯ꎡ {  c$04 +vj8DrSXzPq<D3I1B̭=$eyNwfx,i(8śewX22O`W4 h:+!4xJ0RG0Y+Y|O߱<~S o<+ DCH^s[mSwdsZqؠ38qՍoU4vHMh_W"ڽdcJ%2;7ƣNu<凗Zx^O4BKc8@˩ii`YT rZ0@P<@xKuLJފe!1FZac{ AIq'OXv Z ыeM ]ziD{YLKb +VhKf8*o4AX ~"/*dv/"7FZG9SBH&"cIRFm?1x2}kYn)621W!93* +G?<.]p͆x"//;#F\πOAeZK:Y H# +b?*3ύ=|΢Il* +F i6mоg-~!A89zK_ QǽH& ?\r2P<\4>kJGx #`ߛjHxգT&ٜ(*273{j +τ)%f0x L~)kֆO8j_! vء_ً#OٝM2ʼ0,r4-\gsxiK]2c#2>RHkw&~Z 0SQ5AEփ᷆eDʵrGYx.Ll5W2<<;Fj +`;!/%Iyo\Z +#BH9c18諽%#m]6 ^{S=!TeuI` 91 +x)ر@)m]"q Rm6뮜O> + kx ʛ0 AEw}JHxsgT1ب2 +˥v92(~oL򋷥`PYmTtN66)͇zJűEv*bq1A/jvV9qewelVa$k^ tN)ƒu5fC?桨:>m8vPPI0D$98NvI7 %DW4y~JG5 +ҤbGpa? +H!8TN/Y^dsPIEyݺuޕp—/c +2ޥ%a@/>'0}'ál'̍.HS"ьv79QHҮ2<7!a?"Pw^, uXej(g3Q8sPNVXj_}#lyXgzr Q$݆m(-I`L-t&, ,Cy[IDAT]I + n,l!^re"@%)K. +<#@eS6m#üzS0 +*\LaVNB4Dm}e)T6mP?j3{~1 )P}T{9y<`{DԩnϤ{@8A?#*tbH)TfKu`j"Jky7plP2'~y6ێܛ!Շt:mp/_>9DZ2(f5k| + +0>;*%lF,1:֪YX{<?ˁ (c }v[=b;H'PNJ^iPu7&D'2bZa6CCpho`FHXp!9rk׮+9K@#fm|o +a^Í;Eҷ/6 +f`0WV4bzaG'0t\J2011xuojhYN +RfN:1(I)٨%.dzRHN:]N1.]#G!B; ^阣zkի0e ۶eݎv^)100LgaovF|C-A*sUFqSx;묳0)Qcy _2.7>rP.N䝎c}tl>U _sH3ve9DPx{x̲RT'Qbt8nuW +C!HD@B O4rd4$x3 ]eMe0,N:Ȩ)x-i?qя1A/t\ь`5ʴNp9ӎ O"pnn€!hҚowd|y*ao]e&6lDMjN ++lˮ.l2d߀I-~ $iL.`O~;]r8oӘR@yvJWޟ!B> M~i' ud0R Y3S6zԣ5*G"⟢a`c=,G %O +Bb{g8cbvqNlBq1eDfyݤKNݘlr*+n +X}9’=s +b6PdT!qm*S\"WM0E(!a+V}T&]}x)Qt( Iƫm^d&Y}㐩1oe-ǩ$#:mƐ=ܓdpeH-B[`vUN!MD!…^(* lA8v>w!*4h,EDz<[Vip-O9 +&_Ǵ.+0j -&xWA11@ F SMbP$*qj=g5ԟyܴ lwvY҂j} ~rJ.4T fUN"a ,rJcwycP,1v +1/ƽ+6Ƀ0Lr),\1iLͻ%v)>Ψvp7$Yʃc=xאM^؂A^)sXPWޘo{2_W$v?zPl; +>qNO4NZ52]H2 +\[N]k$s6f +d ڠwxewUz^'TL9h4J7 +$_ 8'u͸7i ` =#! (eKv ءCwÎ^mk"A`h_cJS%ľ.>o +Guv"kPzX0{]ftGyC_MIM 6`޹UjR$J_jTA#9 ADgN~N7C|q8+}Ͻ_TC %-<8Q )wS5 +s 2 +J 7=% +庹 06 R6wuGo!zXHk +} +[@CN?cP-xڵX2)=ѝ(җ~v Ɍt }Ҿ +qJk4&E#4%z~4 + .pٜ<`pq, *ϖ$ul߱ +=k`З2$,caoR ?gZ|*Uܵ9eCڌ9 +L +X/bʖ&StRZHGlvS1Noю5J7|Lx|6+@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e2P T*@e20?IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/msi_netbook/.svn/text-base/theme.plist.svn-base =================================================================== --- branches/Chimera/artwork/themes/msi_netbook/.svn/text-base/theme.plist.svn-base (revision 0) +++ branches/Chimera/artwork/themes/msi_netbook/.svn/text-base/theme.plist.svn-base (revision 850) @@ -0,0 +1,106 @@ + + + + + Enabled + no + screen_width + 1024 + screen_height + 768 + screen_textmargin_h + 10 + screen_textmargin_v + 10 + screen_bgcolor + #000000 + background_pos_x + 50% + background_pos_y + 0 + logo_pos_x + + logo_pos_y + 15% + logo_bgcolor + #000000 + logo_transparency + 255 + devices_pos_x + + devices_pos_y + + devices_bgcolor + #000000 + devices_transparency + 0 + devices_max_visible + 5 + devices_iconspacing + 20 + devices_layout + horizontal + bootprompt_pos_x + %50 + bootprompt_pos_y + -2 + bootprompt_width + 50% + bootprompt_height + 20 + bootprompt_textmargin_h + 10 + bootprompt_textmargin_v + 5 + bootprompt_bgcolor + #000000 + bootprompt_transparency + 1 + infobox_pos_x + + infobox_pos_y + + infobox_width + 650 + infobox_height + 406 + infobox_textmargin_h + 10 + infobox_textmargin_v + 10 + infobox_bgcolor + #000000 + infobox_transparency + 10 + menu_pos_x + + menu_pos_y + -5% + menu_textmargin_h + 10 + menu_textmargin_v + 5 + menu_bgcolor + #000000 + menu_transparency + 1 + progressbar_pos_x + + progressbar_pos_y + -30% + progressbar_width + 100 + progressbar_height + 40 + countdown_pos_x + + countdown_pos_y + -20% + boot_width + 1024 + boot_height + 768 + boot_bgcolor + #AAAAAA + + Index: branches/Chimera/artwork/themes/twilight/.svn/all-wcprops =================================================================== --- branches/Chimera/artwork/themes/twilight/.svn/all-wcprops (revision 0) +++ branches/Chimera/artwork/themes/twilight/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 55 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/twilight +END +font_small.png +K 25 +svn:wc:ra_dav:version-url +V 70 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/twilight/font_small.png +END +logo.png +K 25 +svn:wc:ra_dav:version-url +V 64 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/twilight/logo.png +END +theme.plist +K 25 +svn:wc:ra_dav:version-url +V 67 +/svn/chameleon/!svn/ver/1/trunk/artwork/themes/twilight/theme.plist +END Index: branches/Chimera/artwork/themes/twilight/.svn/prop-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/twilight/.svn/prop-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/twilight/.svn/prop-base/logo.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/twilight/.svn/prop-base/font_small.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/twilight/.svn/prop-base/font_small.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/twilight/.svn/prop-base/font_small.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/twilight/.svn/entries =================================================================== --- branches/Chimera/artwork/themes/twilight/.svn/entries (revision 0) +++ branches/Chimera/artwork/themes/twilight/.svn/entries (revision 850) @@ -0,0 +1,130 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/artwork/themes/twilight +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +font_small.png +file + + + + +2011-05-19T21:52:33.000000Z +3e3b7c960ac7b2ae2cee68a386e4d92f +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +9670 + +logo.png +file + + + + +2011-05-19T21:52:33.000000Z +5d635b494a87976a646cde66801bbcdb +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +68800 + +theme.plist +file + + + + +2011-05-19T21:52:33.000000Z +5fc990c3fc8b7ee7654b28cfeb5cf9a8 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +2699 + Index: branches/Chimera/artwork/themes/twilight/.svn/text-base/logo.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/twilight/.svn/text-base/logo.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/twilight/.svn/text-base/logo.png.svn-base (revision 850) @@ -0,0 +1,620 @@ +PNG + + +IHDR R( IDATx}|7{݌}3HH a!2Q֪uthk׫Wekm[VEeo !II.H<y;{~ +@aWoÛgDqQMMՊYfaŊS{ +{a^5)BX,]3O߯~~~ãZ0P ..:#ISRKϘ7M + [piIn?uuu+G28FgΗ\8q"D4b&2`<Uӝ0 p:n&<段OstEll,B)ZpJP + ;FA~^ +9BFd>533)p)`ZP]m' p(vS^ކ5k7|i:Ѩ7k?%W\vv y +#پmPjW̬Q`؁ [N֚u-3mmPAơC:ɎuTؿ?m>V(}|pR@,DÃq(XdRTvb\ȮߏTL;U0 +} +cXt/O@DXh:E$GO?^~c\ }5R +h`H)h&R}<8\d+,a^0)Jrr}8>}R|2l=unkM>o>4) Sf,7/ `uh,`R`؁ !`IsN-'G)Ў㍭[wBwnH!Cmީ$8{hktߤ9R_J6"Ne((07izGק``;չ*Hen*i1 +^o~3l݈7^_`!Y})5455H#0ISQCQc=ٕ%&0n8zv*BL + e +8C4jkϫXU)aO9aGdT(N٬e:WT ;Zp&Iss#:::hnDcv +EA*$ p݋*%΅C,訲f_[$A|?㈺fqp-O  (/c2ISP`XZ:jmm5hc>.>J59i$M +7K1C@lLښP[U ^"DM`CJf +NEiwcħ1&4%v*%d3pU +Kw%tժPL>}FX1ص;+V"q*z9S I}VX9?k6)`K]xkkb .}zw\GoZtcMCf9`W#6.?ὃ53kW\fMEDZq5W/@yZd`x* +mcxR@/ r|_!aX H.[nv)6zcǎ 3|)0,"҈2Px$ru@IG3] +GØynR`(PI7N&|%ʧw8d!88yV0~EMQq?|)-UlwװYӧ\8&Fxv1cW^S( + +f>57M +G0r4gN8veƝX`JQ\V$%%!/mێw&FQ)4oY +h ;ђx2U7nV:Cbf +<_/Ïd%K.V!|3A,k=NBcM + u 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+oe;bE";'W"_\#z\/qMcr(,[ +K!Xm'a E3joIn݌SQeAL t8 "@HOTוM`=8" y\F #2}uق2iWP"?Z#'_! +=R]SF + +gMQS['ťe7S#XK)D fT4|6 +qøܾ%ghwJN{5V)))X ++Q} +17L t` ƛDa*i>,.. +Ai`oZ,?nB1_ZqUr]%G9U9`O-)r4]|<$)էnK6֝-O5a N\4E(yLR,hՖmnܡ~&eq*bgq = +l 8A^Q[,` +R\XLd,:qU.BCC_ ,/yD*p6 lUuZ c9QY89Zk1?w 0˨s'g#$ cYhnJ)SZAD%h{鴖 9t޹fM 0%`JHPr;5*vv6hӃGEl̡MgL 0%`JKOncgvZ~ҲXMŢ=fsL 0% $s;Z[%tӳ>V- 2Ŕ)SL \H 0/*tڀb!` Ό*ølJ)SZ[NN +־\i"Fw;B):LKxgnM 0%`J@kK",!SZ.qns³B AnbJ)S.kku:B^ui89ȍ>ܚ0%`J)S@S.A"""īNXoL 0%`J/K)Z$ݻww疾)skJ)Sڀ:rAHMM[ +SL 0%!$ [T16o”)Sڒ:rc+JG[-L 0%`J=J)lll$4$0K+wskJ)SL :r!5uR´^4`J)SX%ew9lwIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/twilight/.svn/text-base/theme.plist.svn-base =================================================================== --- branches/Chimera/artwork/themes/twilight/.svn/text-base/theme.plist.svn-base (revision 0) +++ branches/Chimera/artwork/themes/twilight/.svn/text-base/theme.plist.svn-base (revision 850) @@ -0,0 +1,106 @@ + + + + + Enabled + no + screen_width + 1024 + screen_height + 768 + screen_textmargin_h + 10 + screen_textmargin_v + 10 + screen_bgcolor + #000000 + background_pos_x + 50% + background_pos_y + 0 + logo_pos_x + + logo_pos_y + 3% + logo_bgcolor + #000000 + logo_transparency + 255 + devices_pos_x + + devices_pos_y + + devices_bgcolor + #000000 + devices_transparency + 0 + devices_max_visible + 5 + devices_iconspacing + 20 + devices_layout + horizontal + bootprompt_pos_x + %50 + bootprompt_pos_y + -2 + bootprompt_width + 50% + bootprompt_height + 20 + bootprompt_textmargin_h + 10 + bootprompt_textmargin_v + 5 + bootprompt_bgcolor + #000000 + bootprompt_transparency + 1 + infobox_pos_x + + infobox_pos_y + + infobox_width + 650 + infobox_height + 406 + infobox_textmargin_h + 10 + infobox_textmargin_v + 10 + infobox_bgcolor + #000000 + infobox_transparency + 10 + menu_pos_x + + menu_pos_y + -5% + menu_textmargin_h + 10 + menu_textmargin_v + 5 + menu_bgcolor + #000000 + menu_transparency + 1 + progressbar_pos_x + + progressbar_pos_y + -30% + progressbar_width + 100 + progressbar_height + 40 + countdown_pos_x + + countdown_pos_y + -20% + boot_width + 1024 + boot_height + 768 + boot_bgcolor + #AAAAAA + + Index: branches/Chimera/artwork/themes/twilight/.svn/text-base/font_small.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/twilight/.svn/text-base/font_small.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/twilight/.svn/text-base/font_small.png.svn-base (revision 850) @@ -0,0 +1,73 @@ +PNG + + +IHDR9 IDATxWǿF2$I5$ZI$Idd%ZY+YJZ+YYId%YYYk$I$IFc1tsO&s=?:f? +\ K- ^yO}K 4X + k[Y/C`S~H[')pmo{ෙK$o]ߨlx|+83`,lR7Jum>żl-{p}7hf{pXƾdGWM>neEm[EkFm64Jno.3X\qm0O4QXEnNQN6:27ۼ3-w0ρ۳]k[n92m,~6s j7O'w;1=:oh@w;{ + WDڛ~?~>.Nm5%wxwNipJk7zۏdix^5pܚ5e͏<[ lHA}&]/pa uvV}#Rd,g|S0Qtmv',| i7(4Αy;&ZM˻-{?1O ?1~6A {yY-^cAP6-9*$2>I0ȳ)ކ]4oȻ[!@"1;ޠn(lwE!`u&/~rbs2a>DWE`ql)ڐ>lDٳu8yB/9}ۻ +RKk뀞4.g[;}H.1bxLY>YI̓K?蚜 NCWqL_Z[vXWcs@{owQ5ևQzFL^16'L+2;YH m?BM(k>Ur<RΞ@Ousg[] շPt/csҜ$0>FH~3b#F3npw1ېR$,=!"4 İO[ym +CCF%k<1`Ȼ)J7SD0K?@"?Z{\K26i#:b^ ў./BdkucmF)`K,1DkVZO-kywcW5["g!Jt +ׁn^/+޿GA}GDU~Q| 68OZi&l~C(H0nse7KmM{-H?Owsu!MЇhlB{9#|O )'ʊ*E* 3bvʰ|Nٻ{֗j8E+'wYݷu2yGt{7Q$|EY!Xx;5Y^ΕI[`$"um~'*䊿#(Y|k<FoTkX!h`yg͢G`^I1 <@ze,FVd?Na( +Y+׼_f8;e"do!"f{9zsq;^SHhe+-mzh˽#2yj\ J sJqJlϗK)xCfP9vKWi%RLY[ya$x@r.=70ha:K"G%۬n)ṋKQ*O7(b3Rj +:!랍ͭhvicJlBbs *RjJlظ_$NÏH +.ߒ 6* ez}jJL˗i+kA{@[ )Sҙ6%kϛavmJDh@V)ۑ|ۻmq3}l +q%fpSe ~2MUqM w'> ZJ2Eus/e~D,/ +AȻ%hOQw_qCJ&rמ -nߔ09uȲ VK7<4\ן$"vʈVZc?6ۅhݬAtjX']&o!4S/jB"`x.Dʴ/+_h}C>H֣=2#uX@ER#Xn};  ju7&hJk1֗&8hUIa%A髰/)~d6g조>).[ 0(͕gm>GLyކ6 K)!bL"EZ&;mu@`>}Aj\f[r nZ?B2]h>ݠZу$<Σͻ.n"g!3wsVt-zy Ciw Lj]8ޅ۱"#P/Z۟xZ{d s1"0Wu{5 m9e뷖8xWSsR׾HV PsSsnϷ{[CZ.E0ZWl .X=(*@zX +"&j>ݿC },Sb޽1ރb2 ܈Yw7]:5/o@%+ &DZn؍"HBrC>Ft*b^F&.yT D$XFmrG0Gd;B/< +kHA#iC3XH~bc`I>gĔ;,ƘGW96h:766*ڱ1ikڜk-"3@11=-AM佐?G?AHCc*O6Qēh8{RxyϖX_ck~yb³]w\ J@S']w¾}ƵǞ Ң~~1GS=,׾:g+bN!"oM"_ì 5yh +wYi` +1ٽ6Z:=|,4b>@ojl|BG +|3#wD}k.ѠHW| +fdsSLu11G[~-o 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=================================================================== --- branches/Chimera/artwork/themes/embed/.svn/prop-base/progress_bar_background.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/prop-base/progress_bar_background.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_boot.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_boot.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/embed/.svn/prop-base/progress_bar.png.svn-base =================================================================== --- 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=================================================================== --- branches/Chimera/artwork/themes/embed/.svn/prop-base/boot.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/prop-base/boot.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_single_user.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_single_user.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_single_user.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/embed/.svn/prop-base/device_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/prop-base/device_selection.png.svn-base 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(revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_memory_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_memory_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/prop-base/menu_memory_info.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/artwork/themes/embed/.svn/prop-base/device_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/prop-base/device_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/prop-base/device_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: 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` ` ` ` ` ` ` "` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` "` ` ` ` ` ` ` ` "` ` ` ` ` ` ` ` cIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_verbose_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_verbose_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_verbose_disabled.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<OIDATc?Alb~뿡K0a w?1MA C1MA}cl̞70 65ӷOj|IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/device_cdrom.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/device_cdrom.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/device_cdrom.png.svn-base (revision 850) @@ -0,0 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Zh65'@kB * ciȚۼ&ڱF+><ȆrgޡW`@{!^' -yWxp{1ZdV3߫AQC{ T)cH`2$cZ"+? ฃHm(pc += +c [ӿX_1s в|XhU0-8SXЊ?` ߐlxI4db!x$Z&gXnX屍s_.?L-a}WU.}} xX`,_?KaأȵW%Ms5$6yг~GG;GYCv$:q1FYKJubW$3f&\)msuN7JITm`ʹy2,۬*q1dX6v%̿X9i?F8.gpfN}t_@)F8PEP>ŀ| ?yo[G,y ,X9 +!$gn]u ٜ974yd7,_g:Ga/)TzL*t(܏&4 0ȓMQgAo7i_P$187gG<pi$<)F : vATyJ 2]Pa9(w99R朖a>8ƵY3 t"A ?[}f㌟D]U +aN5BG\U՟tP\`Yf c@FV\Ӿ[Yʹ:a/)~b*x~͊ep $R +To"9F'&11J8SPixDO#:(QaT GK@n&C >mRTAM/ ʕYo'dhF^}7A1R)* ^k?_@O"St6!?xic&-1Գqa6bW,UV= s40wJA#u0m R? <"Y| +4 N WlL0j<|p1z7Nb,E d.8+cNLl/CeBCYa{1-)T:D Soqmoz~i׷H{-a +5h +XPA gevc8W(uF J?dks-=d2Tևd3?u\W*gw.gɀ38M!pW_42a `5~ޫ t +G, n3k ʄ~#kc]ȆI,=~RW xF>e<I&aGzޒeΑ@fY IojXc.І\sCxJ2]ᦜY߬fF?DJt4Piy]o̱# +{\],0"_pǨd8B +G^_5+ntfjQwlF&?͇VkI[ ݥ_0h̴S=\yk=^-Wur!K6ޟ_}_&#< +W<4k5S[c|x +n#!_^c[M<#F?5 +\5>p=hƫ\{hr +_=>σ +@77˓HmwdZ0Hyb{m!e$;4&nX[-75 UEpR؁6oǮ/5 +Vn +ͱWfl=5)-_^\kԚ!)ϱj×/btZhSۙ?K~yffw%>Yή󑙇LKϗFjk{ZhڷTX޽BV6 9IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_verbose.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_verbose.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_verbose.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<PIDATc?!q 7@ƦyAlJ 4ؔhW6(K@Ʀ43ZIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/device_fat.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/device_fat.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/device_fat.png.svn-base (revision 850) @@ -0,0 +1,58 @@ +PNG + + +IHDRU^R2XtEXtSoftwareAdobe ImageReadyqe<%IDATx}[myc1\ر㺴iBJAJMKQ+JDK +* AwEF #HU4Q$!c;v{bc\{9?6\sq%mMyM"/1HB BwDžHH aE} *x^`/ٿ }9 A`}އmYd^"U!)IH-ztc5Dr!{ +̽y謻G S1 +y{vg=Vt2̓/@" + hl%O@H]%!b~|?rGLCh tA/@p9=?90ٻV߿qf=!bEx7FCP3@@1?ya~{7)JL?0P&( &ld$jsԭGt_{ f vS2qȀEEE$iϬ6X #絈 +]v`}YMEd21Q }J׿x:~# b!" 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#fJrr2-oݺyǎ xBm|9i7yS#L!e OKΞf>E,5E~H(#kE)b _h_z{㙃Fe.y)X6V#uEdG"TrPpc˖- +/XG y9r=!0{sCq +$iLzCŜ79|dxyh1GMAP#۞}ٵ_3Ɋ敾E&) 3g\Q\\4\<gO +e"8#MU(Ͻ ˁG؄p?܎@mqGy}+zVnAIdAwɓ3']hbxtHp̼_dOJJ^O +Wՠ^p* CZ۟y +{$!}@`ڰ1Y4 ĸhժUE>`.uU/0SƇs߾}Ɏ;Wixnaʩ@Hʚ:1`ܹs!Isbˇod6o|^̙3b*le裏4 _ƪsUTT4C_UVVo0 ( áP~; 998%{9駟`>I?t%? 8$c+&6L!hmyx;?Co6tM.Mn +S{;$`0n=OP_rAՕH{5]kPM0J- ,#h2,VH]<eA\s|028-M /y9k6K.C]?yfAD2RhFOM2/I@rBlͫ + Q0h)$ 090)2IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_single_user.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_single_user.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_single_user.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<PIDATc?!q 7@ƦyAlJ 4ؔhW6(K@Ʀ43ZIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/device_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/device_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/device_selection.png.svn-base (revision 850) @@ -0,0 +1,10 @@ +PNG + + +IHDRU0tEXtSoftwareAdobe ImageReadyqe<4IDATxQhg9y{$&Ml,uVj;۵`UЊ+›w(11v%t)nvZol/JE .uYgTgY%M}/޷y!$ yC<{ m Q9aG|0"By }К|'66* ֱ'oކڛ>ؑ}H ʼ?dֈ"nXݢ, +800V_mt[@$Bj#÷!YZ˟WjAabb03[:wDQ60`ĦO3;7nʚ_ Lj?10pPӑbrU?o sE̎j(bg|Ϯ{ v~~~Um*ͦ,:bx'>m3xk_p?e9YqWЮ޵cئB b0 wNq۹mPY<6٬.^a߾=X^^AJ [읜8&,PkVhbPWb_;7W*|;au3]H)E$f 1ӉHF#$~◿YI"vԤSӓ'ܳtس?-Khۃ65owknYbPUx Ӌӛ>vԗ]qN9}|q/=ELLcVM=(eNͷߺsNsW*3=4+'./'| +W,`ha1YP%^x O?,OM?V{U?Q-ߧ؉g|^~*=2ʲDCgϽ=BNg! RYRV32r3kJṈ•~Oūͽi + +1VU]e[XL)eR]s2<2~ WGkKK*eUaYMfH"~jUfLDAMK3EѫUwL]<5ˆ!s-k(żQU3rV."Rif!RS}""v#>ԐEuY +nfX-`JsNр@AUL2:!k3!LTɀ A"h=LoXD"fjX 3AD4C  2C@D_` S ̬A1A%vڤ<߼A"9!"63SRJ9kNTSͦk&,31Q[ +͊N#ߛVQ3esN5DX \H, Rvo"RSmYXV` ") +P }"uJMD"*u-)jh`}bJYcQ C`FSsV"-Hfef[fUM`2f_PmXS;UflBA*,s`3TĖ$UU߾蕺a2q2@)h`fRjF2 !TfUb1Re"fr1@dW3 EE}zQ㨎GuTG8:QQ㨎GuTG8:QQ=ꨎqTGuT:zQ㨎ꨎqTGuT:zQ㨎GuTG8:QQ=ꨎqTGuTG8:QQ=ꨎqTGuT:zQ㨎GuTG8:zQ㨎GuTG8:QQ=E#iJIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_ignore_caches_disabled.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_ignore_caches_disabled.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<OIDATc?Alb~뿡K0a w?1MA C1MA}cl̞70 65ӷOj|IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_video_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_video_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_video_info.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<HIDATc?!sw?0 b  A7uѝW@>0MA n^ܸM +< V1IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_memory_info.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_memory_info.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_memory_info.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<HIDATc?!sw?0 b  A7uѝW@>0MA n^ܸM +< V1IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/device_scroll_prev.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/device_scroll_prev.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/device_scroll_prev.png.svn-base (revision 850) @@ -0,0 +1,17 @@ +PNG + + +IHDR+wLtEXtSoftwareAdobe ImageReadyqe<;IDATxylE>h)mBˣjB"  #P-(Pn @m}vwm}&#~3}1G ++++++[Ju LϲJ5K&s;u-_ׯy +K<}3?*x[nx>_b(V{̚;ձ&yѲ u@-t,W{ +NvNL2okGJ2*<"0M !Ks|?z7ZmosUU +dC@*.\{~ +srx"20nΰ 70(^_r#1Xyb*cm~"B;Y+ (QWPo@ +B;"$<Qa/X4@@ps3j]u>Ce2I"fX``C! +<>g^; +CM6Ts'?s/zo-ó*[V1dPqn uj*yߝb35}cB (]59)A]0شiĴ)5r8,˂eY!" KQ&v %R +J?r]-Œ#Ȱ+K)3n$Csi0 +YJ(<8tn߁uYJ)ʪ*T?߰ij.pgerjyk x3^}E*t'~˗@@P`Q;`D!̴S<6oZ.@YSF'O\xb`7׫'t]5B( ̥'0f0gVO +4uċb䆆|k 2τϿ p4,]fe&8x-:BhԘ]{ٺW4Iǂ*eTW};ͅkn9a86"n +QGj\5\6~ƹx$<չ3 +p]]d!b"TlfswE*TTtė=e?D'ݫmgxC~hCtyC]\}Ą>)Q;ΞY=X5Z['8A3$Vk8`[hn3ո:E7ym섥r1Xڔ->Auh[x !,5{)o 6%YA`E`_FJoԇN{\!N3BX''Eƃ`"NIm"<؆U{?u@CHٚX8`jĶhc/+++++++++++++++++++O}IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_selection.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_selection.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_selection.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +PNG + + +IHDR⓴>tEXtSoftwareAdobe ImageReadyqe<pIDAThۡ1 tG u4 1+ɺ0SRYT,b*b11 + !A d sC3"0)d1lqFCqLC!BCħEx>hIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/theme.plist.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/theme.plist.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/theme.plist.svn-base (revision 850) @@ -0,0 +1,121 @@ + + + + + Author + Blackosx + Version + 1.0 + + Enabled + no + + screen_width + 1024 + screen_height + 768 + screen_textmargin_h + 10 + screen_textmargin_v + 10 + screen_bgcolor + #767f73 + + background_pos_x + 50% + background_pos_y + 0 + + logo_pos_x + + logo_pos_y + 5% + logo_bgcolor + #000000 + logo_transparency + 255 + + devices_pos_x + + devices_pos_y + + devices_bgcolor + #767f73 + devices_transparency + 0 + devices_max_visible + 5 + devices_iconspacing + 35 + devices_layout + horizontal + + bootprompt_pos_x + + bootprompt_pos_y + -6 + bootprompt_width + 40% + bootprompt_height + 20 + bootprompt_textmargin_h + 10 + bootprompt_textmargin_v + 5 + bootprompt_bgcolor + #3e3e3e + bootprompt_transparency + 1 + + infobox_pos_x + + infobox_pos_y + 30% + infobox_width + 660 + infobox_height + 320 + infobox_textmargin_h + 10 + infobox_textmargin_v + 10 + infobox_bgcolor + #3e3e3e + infobox_transparency + 35 + + menu_pos_x + + menu_pos_y + -5% + menu_textmargin_h + 10 + menu_textmargin_v + 5 + menu_bgcolor + #3e3e3e + menu_transparency + 1 + + progressbar_pos_x + + progressbar_pos_y + -30% + progressbar_width + 100 + progressbar_height + 40 + + countdown_pos_x + + countdown_pos_y + -20% + + boot_width + 1024 + boot_height + 768 + boot_bgcolor + #AAAAAA + + Index: branches/Chimera/artwork/themes/embed/.svn/text-base/device_scroll_next.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/device_scroll_next.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/device_scroll_next.png.svn-base (revision 850) @@ -0,0 +1,17 @@ +PNG + + +IHDR+wLtEXtSoftwareAdobe ImageReadyqe<5IDATx[LWwffM4Zh4j*lO}.Z5Iէ}ňD V㪈((h23a]VX&g?0˃$Vb%Vb%Vb%Vb%Vb%Vb%Į߾.dltQQĨUם-ҷr'F$ Fy׊Wf/ v۞!/lv:0u gMM*9V~j鶌^cG?kR0D#Np-kk񆵛u/<صꥢ5qS>\аPp"@UTTﭩKܩ,$&-N=1r\ ƍ{DPͭ-Zu|ζA7"}(P<É`ݭ!-n 8Ӧ Ӂ]p8RJ+$y̝<(ؽv +^0=:tpO-zv0ipy_׳A1_>]SWhkFVKٻƌN=vρD(;n*hiiE”թ +yhwoA7`;{ C +F P}_}e[֌ Z4 $:a +n( +Lğ'O);6]vfNw.Ď3A!N&L +uz@5UFdaÆLq^aƳQ#TV|>vhh 0 h3cIPTλְCs堢2S'x2 ƱYsHpr)'^͆4/=-&:9:1(<44>:Zp|CC}!@X(VK Cg'&[>0mޥ:w'ݼ߳sazK;/Y +e2W&/[4:USԂ# +pJ^XTt ݁}a%hPl[<΅CshyPCGrqNW.+yulXaf1E P>lٷ3R?J^4Af-棦[4ۄawI +0M)',KN?7o©3gQdtC `MkM lރ~;L' +:hAiPdݖv Ê'`1="*TQ*[[[Maú{ +kI MޗX2f24?װZS׀5afӶ 5Uk5- / +v)*6c-+Ԯee=A6_I(jk_X\"`>&*,D}B_FՏ=ZM>/ q\ClV-D +}?`&df3H}ulYfIU@볯:lZhn`SdP"t >^?|Pn%6+i'++++++++++++++++++<zŢOIENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_help.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_help.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_help.png.svn-base (revision 850) @@ -0,0 +1,5 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<HIDATc?!sw?0 b  A7uѝW@>0MA n^ܸM +< V1IENDB` \ No newline at end of file Index: branches/Chimera/artwork/themes/embed/.svn/text-base/menu_ignore_caches.png.svn-base =================================================================== --- branches/Chimera/artwork/themes/embed/.svn/text-base/menu_ignore_caches.png.svn-base (revision 0) +++ branches/Chimera/artwork/themes/embed/.svn/text-base/menu_ignore_caches.png.svn-base (revision 850) @@ -0,0 +1,4 @@ +PNG + + +IHDRHttEXtSoftwareAdobe ImageReadyqe<PIDATc?!q 7@ƦyAlJ 4ؔhW6(K@Ʀ43ZIENDB` \ No newline at end of file Index: branches/Chimera/i386/libsaio/smbios_getters.h =================================================================== --- branches/Chimera/i386/libsaio/smbios_getters.h (revision 0) +++ branches/Chimera/i386/libsaio/smbios_getters.h (revision 850) @@ -0,0 +1,43 @@ + +#include "libsaio.h" +#include "smbios.h" +#include "platform.h" +#include "pci.h" + +#ifndef __LIBSAIO_SMBIOS_GETTERS_H +#define __LIBSAIO_SMBIOS_GETTERS_H + +#define SMBIOS_RANGE_START 0x000F0000 +#define SMBIOS_RANGE_END 0x000FFFFF + +#define NOT_AVAILABLE "N/A" + +typedef enum { + kSMBString, + kSMBByte, + kSMBWord, + kSMBDWord +// kSMBQWord +} SMBValueType; + +typedef union { + const char *string; + uint8_t byte; + uint16_t word; + uint32_t dword; +// uint64_t qword; +} returnType; + +extern bool getProcessorInformationExternalClock(returnType *value); +extern bool getProcessorInformationMaximumClock(returnType *value); +extern bool getSMBOemProcessorBusSpeed(returnType *value); +extern bool getSMBOemProcessorType(returnType *value); +extern bool getSMBMemoryDeviceMemoryType(returnType *value); +extern bool getSMBMemoryDeviceMemorySpeed(returnType *value); +extern bool getSMBMemoryDeviceManufacturer(returnType *value); +extern bool getSMBMemoryDeviceSerialNumber(returnType *value); +extern bool getSMBMemoryDevicePartNumber(returnType *value); + +SMBEntryPoint *getAddressOfSmbiosTable(void); + +#endif /* !__LIBSAIO_SMBIOS_GETTERS_H */ Index: branches/Chimera/i386/libsaio/.svn/all-wcprops =================================================================== --- branches/Chimera/i386/libsaio/.svn/all-wcprops (revision 0) +++ branches/Chimera/i386/libsaio/.svn/all-wcprops (revision 850) @@ -0,0 +1,527 @@ +K 25 +svn:wc:ra_dav:version-url +V 46 +/svn/chameleon/!svn/ver/829/trunk/i386/libsaio +END +fake_efi.h +K 25 +svn:wc:ra_dav:version-url +V 57 +/svn/chameleon/!svn/ver/450/trunk/i386/libsaio/fake_efi.h +END +smbios_getters.h +K 25 +svn:wc:ra_dav:version-url +V 63 +/svn/chameleon/!svn/ver/828/trunk/i386/libsaio/smbios_getters.h +END +asm.s +K 25 +svn:wc:ra_dav:version-url +V 50 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/asm.s +END +xml.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/796/trunk/i386/libsaio/xml.c +END +console.c +K 25 +svn:wc:ra_dav:version-url +V 56 +/svn/chameleon/!svn/ver/616/trunk/i386/libsaio/console.c +END +xml.h +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/796/trunk/i386/libsaio/xml.h +END +bootstruct.c +K 25 +svn:wc:ra_dav:version-url +V 59 +/svn/chameleon/!svn/ver/760/trunk/i386/libsaio/bootstruct.c +END +efi.h +K 25 +svn:wc:ra_dav:version-url +V 50 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/efi.h +END +ntfs_private.h +K 25 +svn:wc:ra_dav:version-url +V 61 +/svn/chameleon/!svn/ver/413/trunk/i386/libsaio/ntfs_private.h +END +io_inline.h +K 25 +svn:wc:ra_dav:version-url +V 56 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/io_inline.h +END +hfs_CaseTables.h +K 25 +svn:wc:ra_dav:version-url +V 61 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/hfs_CaseTables.h +END +ext2fs.c +K 25 +svn:wc:ra_dav:version-url +V 54 +/svn/chameleon/!svn/ver/23/trunk/i386/libsaio/ext2fs.c +END +vbe.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/128/trunk/i386/libsaio/vbe.c +END +bootstruct.h +K 25 +svn:wc:ra_dav:version-url +V 59 +/svn/chameleon/!svn/ver/758/trunk/i386/libsaio/bootstruct.h +END +device_tree.c +K 25 +svn:wc:ra_dav:version-url +V 59 +/svn/chameleon/!svn/ver/23/trunk/i386/libsaio/device_tree.c +END +hfs.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/254/trunk/i386/libsaio/hfs.c +END +ext2fs.h +K 25 +svn:wc:ra_dav:version-url +V 54 +/svn/chameleon/!svn/ver/23/trunk/i386/libsaio/ext2fs.h +END +vbe.h +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/128/trunk/i386/libsaio/vbe.h +END +acpi_patcher.c +K 25 +svn:wc:ra_dav:version-url +V 61 +/svn/chameleon/!svn/ver/829/trunk/i386/libsaio/acpi_patcher.c +END +device_tree.h +K 25 +svn:wc:ra_dav:version-url +V 59 +/svn/chameleon/!svn/ver/23/trunk/i386/libsaio/device_tree.h +END +allocate.c +K 25 +svn:wc:ra_dav:version-url +V 56 +/svn/chameleon/!svn/ver/23/trunk/i386/libsaio/allocate.c +END +hfs.h +K 25 +svn:wc:ra_dav:version-url +V 52 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+svn:wc:ra_dav:version-url +V 62 +/svn/chameleon/!svn/ver/243/trunk/i386/libsaio/aml_generator.h +END +table.c +K 25 +svn:wc:ra_dav:version-url +V 54 +/svn/chameleon/!svn/ver/779/trunk/i386/libsaio/table.c +END +usb.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/258/trunk/i386/libsaio/usb.c +END +device_inject.c +K 25 +svn:wc:ra_dav:version-url +V 61 +/svn/chameleon/!svn/ver/44/trunk/i386/libsaio/device_inject.c +END +device_inject.h +K 25 +svn:wc:ra_dav:version-url +V 61 +/svn/chameleon/!svn/ver/44/trunk/i386/libsaio/device_inject.h +END +fdisk.h +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/fdisk.h +END +dram_controllers.c +K 25 +svn:wc:ra_dav:version-url +V 65 +/svn/chameleon/!svn/ver/517/trunk/i386/libsaio/dram_controllers.c +END +nvidia.c +K 25 +svn:wc:ra_dav:version-url +V 55 +/svn/chameleon/!svn/ver/786/trunk/i386/libsaio/nvidia.c +END +ntfs.c +K 25 +svn:wc:ra_dav:version-url +V 53 +/svn/chameleon/!svn/ver/416/trunk/i386/libsaio/ntfs.c +END +ufs_byteorder.c +K 25 +svn:wc:ra_dav:version-url +V 60 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/ufs_byteorder.c +END +ati.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/811/trunk/i386/libsaio/ati.c +END +dram_controllers.h +K 25 +svn:wc:ra_dav:version-url +V 65 +/svn/chameleon/!svn/ver/255/trunk/i386/libsaio/dram_controllers.h +END +sys.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/413/trunk/i386/libsaio/sys.c +END +nvidia.h +K 25 +svn:wc:ra_dav:version-url +V 55 +/svn/chameleon/!svn/ver/352/trunk/i386/libsaio/nvidia.h +END +ntfs.h +K 25 +svn:wc:ra_dav:version-url +V 53 +/svn/chameleon/!svn/ver/413/trunk/i386/libsaio/ntfs.h +END +nbp.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/151/trunk/i386/libsaio/nbp.c +END +load.c +K 25 +svn:wc:ra_dav:version-url +V 53 +/svn/chameleon/!svn/ver/758/trunk/i386/libsaio/load.c +END +acpi.h +K 25 +svn:wc:ra_dav:version-url +V 53 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+/svn/chameleon/!svn/ver/829/trunk/i386/libsaio/smbios.c +END +disk.h +K 25 +svn:wc:ra_dav:version-url +V 53 +/svn/chameleon/!svn/ver/432/trunk/i386/libsaio/disk.h +END +smbios_decode.c +K 25 +svn:wc:ra_dav:version-url +V 62 +/svn/chameleon/!svn/ver/782/trunk/i386/libsaio/smbios_decode.c +END +hpet.c +K 25 +svn:wc:ra_dav:version-url +V 51 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/hpet.c +END +smbios.h +K 25 +svn:wc:ra_dav:version-url +V 55 +/svn/chameleon/!svn/ver/826/trunk/i386/libsaio/smbios.h +END +cache.c +K 25 +svn:wc:ra_dav:version-url +V 54 +/svn/chameleon/!svn/ver/292/trunk/i386/libsaio/cache.c +END +hpet.h +K 25 +svn:wc:ra_dav:version-url +V 51 +/svn/chameleon/!svn/ver/1/trunk/i386/libsaio/hpet.h +END +pci.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/785/trunk/i386/libsaio/pci.c +END +stringTable.c +K 25 +svn:wc:ra_dav:version-url +V 59 +/svn/chameleon/!svn/ver/23/trunk/i386/libsaio/stringTable.c +END +ati_reg.h +K 25 +svn:wc:ra_dav:version-url +V 56 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+svn:wc:ra_dav:version-url +V 63 +/svn/chameleon/!svn/ver/829/trunk/i386/libsaio/smbios_getters.c +END +msdos.h +K 25 +svn:wc:ra_dav:version-url +V 54 +/svn/chameleon/!svn/ver/151/trunk/i386/libsaio/msdos.h +END +misc.c +K 25 +svn:wc:ra_dav:version-url +V 52 +/svn/chameleon/!svn/ver/23/trunk/i386/libsaio/misc.c +END +saio_internal.h +K 25 +svn:wc:ra_dav:version-url +V 62 +/svn/chameleon/!svn/ver/760/trunk/i386/libsaio/saio_internal.h +END Index: branches/Chimera/i386/libsaio/.svn/prop-base/smbios.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/prop-base/smbios.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/prop-base/smbios.h.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mergeinfo +V 45 +/branches/rekursor/i386/libsaio/SMBIOS.h:3-22 +END Index: branches/Chimera/i386/libsaio/.svn/prop-base/disk.h.svn-base =================================================================== --- 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All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +// Copyright 1997 by Apple Computer, Inc., all rights reserved. +/* Copyright 1996-1997 NeXT Software, Inc. + * + * vesa.h - mode info obtained via int10 + * + * Revision History + * ---------------- + * 30 Jul 1996 Doug Mitchell at NeXT + * Created. + */ + +#ifndef __LIBSAIO_VBE_H +#define __LIBSAIO_VBE_H + +#define MIN_VESA_VERSION 0x200 + +#define SEG(address) \ + ((unsigned short)(((unsigned long)address & 0xffff0000) >> 4)) + +#define OFF(address) \ + ((unsigned short)((unsigned long)address & 0x0000ffff)) + +#define VBEMakeUInt32(x) \ + (((unsigned long)x##_high << 24) | \ + ((unsigned long)x##_2 << 16) | \ + ((unsigned long)x##_1 << 8) | \ + (unsigned long)x##_low) + +#define VBEDecodeFP(t, fp) \ + ((t)(((fp ## _low) | ((fp ## _1 ) << 8)) + \ + (((fp ## _2) << 4) | ((fp ## _high ) << 12)))) + +/* + * Functions + */ +enum { + funcGetControllerInfo = 0x4F00, + funcGetModeInfo = 0x4F01, + funcSetMode = 0x4F02, + funcGetCurrentMode = 0x4F03, + funcSaveRestoreState = 0x4F04, + funcWindowControl = 0x4F05, + funcGetSetScanLineLength = 0x4F06, + funcGetSetDisplayStart = 0x4F07, + funcGetSetPaletteFormat = 0x4F08, + funcGetSetPaletteData = 0x4F09, + funcGetProtModeInterdace = 0x4F0A, + funcGetSetPixelClock = 0x4F0B +}; + +enum { + subfuncSet = 0x00, + subfuncGet = 0x01, + subfuncSetSecondary = 0x02, + subfuncGetSecondary = 0x03 +}; + +/* + * errors. + */ +enum { + errSuccess = 0, + errFuncFailed = 1, + errFuncNotSupported = 2, + errFuncInvalid = 3 +}; + +/* + * Per-controller info, returned in function 4f00. + */ +typedef struct { + unsigned char VESASignature[4]; + unsigned short VESAVersion; + /* + * Avoid packing problem... + */ + unsigned char OEMStringPtr_low; + unsigned char OEMStringPtr_1; + unsigned char OEMStringPtr_2; + unsigned char OEMStringPtr_high; + unsigned char Capabilities_low; + unsigned char Capabilities_1; + unsigned char Capabilities_2; + unsigned char Capabilities_high; + unsigned char VideoModePtr_low; + unsigned char VideoModePtr_1; + unsigned char VideoModePtr_2; + unsigned char VideoModePtr_high; + unsigned short TotalMemory; + unsigned char Reserved[236]; + unsigned char OEMData[256]; +} VBEInfoBlock; + +/* + * Capabilites + */ +enum { + capDACWidthIsSwitchableBit = (1 << 0), /* 1 = yes; 0 = no */ + capControllerIsNotVGACompatableBit = (1 << 1), /* 1 = no; 0 = yes */ + capOldRAMDAC = (1 << 2) /* 1 = yes; 0 = no */ +}; + +/* + * Per-mode info, returned in function 4f02. + */ +typedef struct { + unsigned short ModeAttributes; + unsigned char WinAAttributes; + unsigned char WinBAttributes; + unsigned short WinGranularity; + unsigned short WinSize; + unsigned short WinASegment; + unsigned short WinABegment; + void * WinFuncPtr; + unsigned short BytesPerScanline; + unsigned short XResolution; + unsigned short YResolution; + unsigned char XCharSize; + unsigned char YCharSize; + unsigned char NumberOfPlanes; + unsigned char BitsPerPixel; + unsigned char NumberOfBanks; + unsigned char MemoryModel; + unsigned char BankSize; + unsigned char NumberOfImagePages; + unsigned char Reserved; + unsigned char RedMaskSize; + unsigned char RedFieldPosition; + unsigned char GreenMaskSize; + unsigned char GreenFieldPosition; + unsigned char BlueMaskSize; + unsigned char BlueFieldPosition; + unsigned char RsvdMaskSize; + unsigned char RsvdFieldPosition; + unsigned char DirectColorModeInfo; + unsigned char PhysBasePtr_low; + unsigned char PhysBasePtr_1; + unsigned char PhysBasePtr_2; + unsigned char PhysBasePtr_high; + void * OffScreenMemOffset; + unsigned short OffScreenMemSize; + unsigned char Reserved1[206]; +} VBEModeInfoBlock; + +/* + * ModeAttributes bits + */ +enum { + maModeIsSupportedBit = (1 << 0), /* mode is supported */ + maExtendedInfoAvailableBit = (1 << 1), /* extended info available */ + maOutputFuncSupportedBit = (1 << 2), /* output functions supported */ + maColorModeBit = (1 << 3), /* 1 = color; 0 = mono */ + maGraphicsModeBit = (1 << 4), /* 1 = graphics; 0 = text */ + maModeIsNotVGACompatableBit = (1 << 5), /* 1 = not compat; 0 = compat */ + maVGAMemoryModeNotAvailBit = (1 << 6), /* 1 = not avail; 0 = avail */ + maLinearFrameBufferAvailBit = (1 << 7) /* 1 = avail; 0 = not avail */ +}; + +/* + * Modes + */ +enum { + mode640x400x256 = 0x100, + mode640x480x256 = 0x101, + mode800x600x16 = 0x102, + mode800x600x256 = 0x103, + mode1024x768x16 = 0x104, + mode1024x768x256 = 0x105, + mode1280x1024x16 = 0x106, + mode1280x1024x256 = 0x107, + mode80Cx60R = 0x108, + mode132Cx25R = 0x109, + mode132Cx43R = 0x10A, + mode132Cx50R = 0x10B, + mode132Cx60R = 0x10C, + mode320x200x555 = 0x10D, + mode320x200x565 = 0x10E, + mode320x200x888 = 0x10F, + mode640x480x555 = 0x110, + mode640x480x565 = 0x111, + mode640x480x888 = 0x112, + mode800x600x555 = 0x113, + mode800x600x565 = 0x114, + mode800x600x888 = 0x115, + mode1024x768x555 = 0x116, + mode1024x768x565 = 0x117, + mode1024x768x888 = 0x118, + mode1280x1024x555 = 0x119, + mode1280x1024x565 = 0x11A, + mode1280x1024x888 = 0x11B, + modeSpecial = 0x81FF, + modeEndOfList = 0xFFFF +}; + +/* + * Get/Set VBE Mode parameters + */ +enum { + kCustomRefreshRateBit = (1 << 11), + kLinearFrameBufferBit = (1 << 14), + kPreserveMemoryBit = (1 << 15) +}; + +/* + * CRTC information block passed to function 4F02 + * to override default refresh rate. + */ +#pragma pack(1) + +typedef struct { + unsigned short HTotal; + unsigned short HSyncStart; + unsigned short HSyncEnd; + unsigned short VTotal; + unsigned short VSyncStart; + unsigned short VSyncEnd; + unsigned char Flags; + unsigned long PixelClock; /* in Hz */ + unsigned short RefreshRate; /* units of 0.01 Hz */ + unsigned char Reserved[40]; +} VBECRTCInfoBlock; + +#pragma pack() + +/* + * Defined flags for 'Flags' field in VBECRTCInfoBlock. + */ +enum { + kCRTCDoubleScannedMode = (1 << 0), + kCRTCInterlacedMode = (1 << 1), + kCRTCNegativeHorizontalSync = (1 << 2), + kCRTCNegativeVerticalSync = (1 << 3) +}; + +/* + * The type of paramter passed to generateCRTCTimings(). + */ +enum { + kCRTCParamRefreshRate, + kCRTCParamPixelClock +}; + +/* + * Palette + */ +typedef unsigned long VBEPalette[256]; + +extern int getVBEInfo(void *vinfo_p); +extern int getVBEModeInfo(int mode, void *minfo_p); +extern int getVBEDACFormat(unsigned char *format); +extern int setVBEDACFormat(unsigned char format); +extern int setVBEPalette(void *palette); +extern int getVBEPalette(void *palette); +extern int setVBEMode(unsigned short mode, const VBECRTCInfoBlock *timing); +extern int getVBECurrentMode(unsigned short *mode); +extern int getVBEPixelClock(unsigned short mode, unsigned long *pixelClock); +extern int generateCRTCTiming(unsigned short width, + unsigned short height, + unsigned long paramValue, + int paramType, + VBECRTCInfoBlock * timing); + +#endif /* !__LIBSAIO_VBE_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/sl.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/sl.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/sl.h.svn-base (revision 850) @@ -0,0 +1,67 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#ifndef __LIBSAIO_SL_H +#define __LIBSAIO_SL_H + +#include +#include +#include +#include "libsaio.h" + +#define SWAP_BE16(x) OSSwapBigToHostInt16(x) +#define SWAP_LE16(x) OSSwapLittleToHostInt16(x) +#define SWAP_BE32(x) OSSwapBigToHostInt32(x) +#define SWAP_LE32(x) OSSwapLittleToHostInt32(x) +#define SWAP_BE64(x) OSSwapBigToHostInt64(x) +#define SWAP_LE64(x) OSSwapLittleToHostInt64(x) + +// File Permissions and Types +enum { + kPermOtherExecute = 1 << 0, + kPermOtherWrite = 1 << 1, + kPermOtherRead = 1 << 2, + kPermGroupExecute = 1 << 3, + kPermGroupWrite = 1 << 4, + kPermGroupRead = 1 << 5, + kPermOwnerExecute = 1 << 6, + kPermOwnerWrite = 1 << 7, + kPermOwnerRead = 1 << 8, + kPermMask = 0x1FF, + kOwnerNotRoot = 1 << 9, + kFileTypeUnknown = 0x0 << 16, + kFileTypeFlat = 0x1 << 16, + kFileTypeDirectory = 0x2 << 16, + kFileTypeLink = 0x3 << 16, + kFileTypeMask = 0x3 << 16 +}; + +#define Seek(c, p) diskSeek(c, p); +#define Read(c, a, l) diskRead(c, a, l); + +extern void * gFSLoadAddress; +extern cpu_type_t archCpuType; +cpu_type_t detectCpuType (); + +#endif /* !__LIBSAIO_SL_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/aml_generator.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/aml_generator.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/aml_generator.h.svn-base (revision 850) @@ -0,0 +1,61 @@ +/* + * aml_generator.h + * Chameleon + * + * Created by Mozodojo on 20/07/10. + * Copyright 2010 mozo. All rights reserved. + * + */ + +#ifndef __LIBSAIO_AML_GENERATOR_H +#define __LIBSAIO_AML_GENERATOR_H + +#include "libsaio.h" + +#define AML_CHUNK_NONE 0xff +#define AML_CHUNK_ZERO 0x00 +#define AML_CHUNK_ONE 0x01 +#define AML_CHUNK_ALIAS 0x06 +#define AML_CHUNK_NAME 0x08 +#define AML_CHUNK_BYTE 0x0A +#define AML_CHUNK_WORD 0x0B +#define AML_CHUNK_DWORD 0x0C +#define AML_CHUNK_STRING 0x0D +#define AML_CHUNK_QWORD 0x0E +#define AML_CHUNK_SCOPE 0x10 +#define AML_CHUNK_PACKAGE 0x12 + +struct aml_chunk +{ + unsigned char Type; + unsigned int Length; + char* Buffer; + + unsigned int Size; + + struct aml_chunk* Next; + struct aml_chunk* First; + struct aml_chunk* Last; +}; + +static inline bool aml_isvalidchar(char c) +{ + return isupper(c) || isdigit(c) || c == '_'; +}; + +bool aml_add_to_parent(struct aml_chunk* parent, struct aml_chunk* node); +struct aml_chunk* aml_create_node(struct aml_chunk* parent); +void aml_destroy_node(struct aml_chunk* node); +struct aml_chunk* aml_add_buffer(struct aml_chunk* parent, const char* buffer, unsigned int size); +struct aml_chunk* aml_add_byte(struct aml_chunk* parent, unsigned char value); +struct aml_chunk* aml_add_word(struct aml_chunk* parent, unsigned int value); +struct aml_chunk* aml_add_dword(struct aml_chunk* parent, unsigned long value); +struct aml_chunk* aml_add_qword(struct aml_chunk* parent, unsigned long long value); +struct aml_chunk* aml_add_scope(struct aml_chunk* parent, const char* name); +struct aml_chunk* aml_add_name(struct aml_chunk* parent, const char* name); +struct aml_chunk* aml_add_package(struct aml_chunk* parent); +struct aml_chunk* aml_add_alias(struct aml_chunk* parent, const char* name1, const char* name2); +unsigned int aml_calculate_size(struct aml_chunk* node); +unsigned int aml_write_node(struct aml_chunk* node, char* buffer, unsigned int offset); + +#endif /* !__LIBSAIO_AML_GENERATOR_H */ \ No newline at end of file Index: branches/Chimera/i386/libsaio/.svn/text-base/memvendors.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/memvendors.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/memvendors.h.svn-base (revision 850) @@ -0,0 +1,894 @@ +/* + * Memory module vendors as published by JEDEC 106AA + * + * Special thanks to indi, memtest and theking for the table + * + */ +#ifndef __MEMVEN_H +#define __MEMVEN_H + +typedef struct _vidTag { + uint8_t bank; + uint8_t code; + const char* name; +} VenIdName; + +VenIdName vendorMap[] = { + { 0, 0x01, "AMD"}, + { 0, 0x02, "AMI"}, + { 0, 0x83, "Fairchild"}, + { 0, 0x04, "Fujitsu"}, + { 0, 0x85, "GTE"}, + { 0, 0x86, "Harris"}, + { 0, 0x07, "Hitachi"}, + { 0, 0x08, "Inmos"}, + { 0, 0x89, "Intel"}, + { 0, 0x8a, "I.T.T."}, + { 0, 0x0b, "Intersil"}, + { 0, 0x8c, "Monolithic Memories"}, + { 0, 0x0d, "Mostek"}, + { 0, 0x0e, "Freescale (Motorola)"}, + { 0, 0x8f, "National"}, + { 0, 0x10, "NEC"}, + { 0, 0x91, "RCA"}, + { 0, 0x92, "Raytheon"}, + { 0, 0x13, "Conexant (Rockwell)"}, + { 0, 0x94, "Seeq"}, + { 0, 0x15, "NXP (Philips)"}, + { 0, 0x16, "Synertek"}, + { 0, 0x97, "Texas Instruments"}, + { 0, 0x98, "Toshiba"}, + { 0, 0x19, "Xicor"}, + { 0, 0x1a, "Zilog"}, + { 0, 0x9b, "Eurotechnique"}, + { 0, 0x1c, "Mitsubishi"}, + { 0, 0x9d, "Lucent (AT&T)"}, + { 0, 0x9e, "Exel"}, + { 0, 0x1f, "Atmel"}, + { 0, 0x20, "SGS/Thomson"}, + { 0, 0xa1, "Lattice Semi."}, + { 0, 0xa2, "NCR"}, + { 0, 0x23, "Wafer Scale Integration"}, + { 0, 0xa4, "IBM"}, + { 0, 0x25, "Tristar"}, + { 0, 0x26, "Visic"}, + { 0, 0xa7, "Intl. CMOS Technology"}, + { 0, 0xa8, "SSSI"}, + { 0, 0x29, "MicrochipTechnology"}, + { 0, 0x2a, "Ricoh"}, + { 0, 0xab, "VLSI"}, + { 0, 0x2c, "Micron Technology"}, + { 0, 0xad, "Hynix Semiconductor"}, + { 0, 0xae, "OKI Semiconductor"}, + { 0, 0x2f, "ACTEL"}, + { 0, 0xb0, "Sharp"}, + { 0, 0x31, "Catalyst"}, + { 0, 0x32, "Panasonic"}, + { 0, 0xb3, "IDT"}, + { 0, 0x34, "Cypress"}, + { 0, 0xb5, "DEC"}, + { 0, 0xb6, "LSI Logic"}, + { 0, 0x37, "Zarlink (Plessey)"}, + { 0, 0x38, "UTMC"}, + { 0, 0xb9, "Thinking Machine"}, + { 0, 0xba, "Thomson CSF"}, + { 0, 0x3b, "Integrated CMOS (Vertex)"}, + { 0, 0xbc, "Honeywell"}, + { 0, 0x3d, "Tektronix"}, + { 0, 0x3e, "Sun Microsystems"}, + { 0, 0xbf, "SST"}, + { 0, 0x40, "ProMos/Mosel Vitelic"}, + { 0, 0xc1, "Infineon (Siemens)"}, + { 0, 0xc2, "Macronix"}, + { 0, 0x43, "Xerox"}, + { 0, 0xc4, "Plus Logic"}, + { 0, 0x45, "SanDisk"}, + { 0, 0x46, "Elan Circuit Tech."}, + { 0, 0xc7, "European Silicon Str."}, + { 0, 0xc8, "Apple Computer"}, + { 0, 0x49, "Xilinx"}, + { 0, 0x4a, "Compaq"}, + { 0, 0xcb, "Protocol Engines"}, + { 0, 0x4c, "SCI"}, + { 0, 0xcd, "Seiko Instruments"}, + { 0, 0xce, "Samsung"}, + { 0, 0x4f, "I3 Design System"}, + { 0, 0xd0, "Klic"}, + { 0, 0x51, "Crosspoint Solutions"}, + { 0, 0x52, "Alliance Semiconductor"}, + { 0, 0xd3, "Tandem"}, + { 0, 0x54, "Hewlett-Packard"}, + { 0, 0xd5, "Intg. Silicon Solutions"}, + { 0, 0xd6, "Brooktree"}, + { 0, 0x57, "New Media"}, + { 0, 0x58, "MHS Electronic"}, + { 0, 0xd9, "Performance Semi."}, + { 0, 0xda, "Winbond Electronic"}, + { 0, 0x5b, "Kawasaki Steel"}, + { 0, 0xdc, "Bright Micro"}, + { 0, 0x5d, "TECMAR"}, + { 0, 0x5e, "Exar"}, + { 0, 0xdf, "PCMCIA"}, + { 0, 0xe0, "LG Semi (Goldstar)"}, + { 0, 0x61, "Northern Telecom"}, + { 0, 0x62, "Sanyo"}, + { 0, 0xe3, "Array Microsystems"}, + { 0, 0x64, "Crystal Semiconductor"}, + { 0, 0xe5, "Analog Devices"}, + { 0, 0xe6, "PMC-Sierra"}, + { 0, 0x67, "Asparix"}, + { 0, 0x68, "Convex Computer"}, + { 0, 0xe9, "Quality Semiconductor"}, + { 0, 0xea, "Nimbus Technology"}, + { 0, 0x6b, "Transwitch"}, + { 0, 0xec, "Micronas (ITT Intermetall)"}, + { 0, 0x6d, "Cannon"}, + { 0, 0x6e, "Altera"}, + { 0, 0xef, "NEXCOM"}, + { 0, 0x70, "QUALCOMM"}, + { 0, 0xf1, "Sony"}, + { 0, 0xf2, "Cray Research"}, + { 0, 0x73, "AMS(Austria Micro)"}, + { 0, 0xf4, "Vitesse"}, + { 0, 0x75, "Aster Electronics"}, + { 0, 0x76, "Bay Networks (Synoptic)"}, + { 0, 0xf7, "Zentrum/ZMD"}, + { 0, 0xf8, "TRW"}, + { 0, 0x79, "Thesys"}, + { 0, 0x7a, "Solbourne Computer"}, + { 0, 0xfb, "Allied-Signal"}, + { 0, 0x7c, "Dialog"}, + { 0, 0xfd, "Media Vision"}, + { 0, 0xfe, "Numonyx"}, + { 1, 0x01, "Cirrus Logic"}, + { 1, 0x02, "National Instruments"}, + { 1, 0x83, "ILC Data Device"}, + { 1, 0x04, "Alcatel Mietec"}, + { 1, 0x85, "Micro Linear"}, + { 1, 0x86, "Univ. of NC"}, + { 1, 0x07, "JTAG Technologies"}, + { 1, 0x08, "BAE Systems (Loral)"}, + { 1, 0x89, "Nchip"}, + { 1, 0x8a, "Galileo Tech"}, + { 1, 0x0b, "Bestlink Systems"}, + { 1, 0x8c, "Graychip"}, + { 1, 0x0d, "GENNUM"}, + { 1, 0x0e, "VideoLogic"}, + { 1, 0x8f, "Robert Bosch"}, + { 1, 0x10, "Chip Express"}, + { 1, 0x91, "DATARAM"}, + { 1, 0x92, "United Microelectronics Corp."}, + { 1, 0x13, "TCSI"}, + { 1, 0x94, "Smart Modular"}, + { 1, 0x15, "Hughes Aircraft"}, + { 1, 0x16, "Lanstar Semiconductor"}, + { 1, 0x97, "Qlogic"}, + { 1, 0x98, "Kingston"}, + { 1, 0x19, "Music Semi"}, + { 1, 0x1a, "Ericsson Components"}, + { 1, 0x9b, "SpaSE"}, + { 1, 0x1c, "Eon Silicon Devices"}, + { 1, 0x9d, "Programmable Micro Corp"}, + { 1, 0x9e, "DoD"}, + { 1, 0x1f, "Integ. Memories Tech."}, + { 1, 0x20, "Corollary"}, + { 1, 0xa1, "Dallas Semiconductor"}, + { 1, 0xa2, "Omnivision"}, + { 1, 0x23, "EIV(Switzerland)"}, + { 1, 0xa4, "Novatel Wireless"}, + { 1, 0x25, "Zarlink (Mitel)"}, + { 1, 0x26, "Clearpoint"}, + { 1, 0xa7, "Cabletron"}, + { 1, 0xa8, "STEC (Silicon Tech)"}, + { 1, 0x29, "Vanguard"}, + { 1, 0x2a, "Hagiwara Sys-Com"}, + { 1, 0xab, "Vantis"}, + { 1, 0x2c, "Celestica"}, + { 1, 0xad, "Century"}, + { 1, 0xae, "Hal Computers"}, + { 1, 0x2f, "Rohm Company"}, + { 1, 0xb0, "Juniper Networks"}, + { 1, 0x31, "Libit Signal Processing"}, + { 1, 0x32, "Mushkin Enhanced Memory"}, + { 1, 0xb3, "Tundra Semiconductor"}, + { 1, 0x34, "Adaptec"}, + { 1, 0xb5, "LightSpeed Semi."}, + { 1, 0xb6, "ZSP Corp."}, + { 1, 0x37, "AMIC Technology"}, + { 1, 0x38, "Adobe Systems"}, + { 1, 0xb9, "Dynachip"}, + { 1, 0xba, "PNY Electronics"}, + { 1, 0x3b, "Newport Digital"}, + { 1, 0xbc, "MMC Networks"}, + { 1, 0x3d, "T Square"}, + { 1, 0x3e, "Seiko Epson"}, + { 1, 0xbf, "Broadcom"}, + { 1, 0x40, "Viking Components"}, + { 1, 0xc1, "V3 Semiconductor"}, + { 1, 0xc2, "Flextronics (Orbit Semiconductor)"}, + { 1, 0x43, "Suwa Electronics"}, + { 1, 0xc4, "Transmeta"}, + { 1, 0x45, "Micron CMS"}, + { 1, 0x46, "American Computer & Digital Components"}, + { 1, 0xc7, "Enhance 3000"}, + { 1, 0xc8, "Tower Semiconductor"}, + { 1, 0x49, "CPU Design"}, + { 1, 0x4a, "Price Point"}, + { 1, 0xcb, "Maxim Integrated Product"}, + { 1, 0x4c, "Tellabs"}, + { 1, 0xcd, "Centaur Technology"}, + { 1, 0xce, "Unigen"}, + { 1, 0x4f, "Transcend Information"}, + { 1, 0xd0, "Memory Card Technology"}, + { 1, 0x51, "CKD"}, + { 1, 0x52, "Capital Instruments"}, + { 1, 0xd3, "Aica Kogyo"}, + { 1, 0x54, "Linvex Technology"}, + { 1, 0xd5, "MSC Vertriebs"}, + { 1, 0xd6, "AKM Company"}, + { 1, 0x57, "Dynamem"}, + { 1, 0x58, "NERA ASA"}, + { 1, 0xd9, "GSI Technology"}, + { 1, 0xda, "Dane-Elec (C Memory)"}, + { 1, 0x5b, "Acorn Computers"}, + { 1, 0xdc, "Lara Technology"}, + { 1, 0x5d, "Oak Technology"}, + { 1, 0x5e, "Itec Memory"}, + { 1, 0xdf, "Tanisys Technology"}, + { 1, 0xe0, "Truevision"}, + { 1, 0x61, "Wintec Industries"}, + { 1, 0x62, "Super PC Memory"}, + { 1, 0xe3, "MGV Memory"}, + { 1, 0x64, "Galvantech"}, + { 1, 0xe5, "Gadzoox Networks"}, + { 1, 0xe6, "Multi Dimensional Cons."}, + { 1, 0x67, "GateField"}, + { 1, 0x68, "Integrated Memory System"}, + { 1, 0xe9, "Triscend"}, + { 1, 0xea, "XaQti"}, + { 1, 0x6b, "Goldenram"}, + { 1, 0xec, "Clear Logic"}, + { 1, 0x6d, "Cimaron Communications"}, + { 1, 0x6e, "Nippon Steel Semi. Corp."}, + { 1, 0xef, "Advantage Memory"}, + { 1, 0x70, "AMCC"}, + { 1, 0xf1, "LeCroy"}, + { 1, 0xf2, "Yamaha"}, + { 1, 0x73, "Digital Microwave"}, + { 1, 0xf4, "NetLogic Microsystems"}, + { 1, 0x75, "MIMOS Semiconductor"}, + { 1, 0x76, "Advanced Fibre"}, + { 1, 0xf7, "BF Goodrich Data."}, + { 1, 0xf8, "Epigram"}, + { 1, 0x79, "Acbel Polytech"}, + { 1, 0x7a, "Apacer Technology"}, + { 1, 0xfb, "Admor Memory"}, + { 1, 0x7c, "FOXCONN"}, + { 1, 0xfd, "Quadratics Superconductor"}, + { 1, 0xfe, "3COM"}, + { 2, 0x01, "Camintonn"}, + { 2, 0x02, "ISOA"}, + { 2, 0x83, "Agate Semiconductor"}, + { 2, 0x04, "ADMtek"}, + { 2, 0x85, "HYPERTEC"}, + { 2, 0x86, "Adhoc Technologies"}, + { 2, 0x07, "MOSAID Technologies"}, + { 2, 0x08, "Ardent Technologies"}, + { 2, 0x89, "Switchcore"}, + { 2, 0x8a, "Cisco Systems"}, + { 2, 0x0b, "Allayer Technologies"}, + { 2, 0x8c, "WorkX AG (Wichman)"}, + { 2, 0x0d, "Oasis Semiconductor"}, + { 2, 0x0e, "Novanet Semiconductor"}, + { 2, 0x8f, "E-M Solutions"}, + { 2, 0x10, "Power General"}, + { 2, 0x91, "Advanced Hardware Arch."}, + { 2, 0x92, "Inova Semiconductors"}, + { 2, 0x13, "Telocity"}, + { 2, 0x94, "Delkin Devices"}, + { 2, 0x15, "Symagery Microsystems"}, + { 2, 0x16, "C-Port"}, + { 2, 0x97, "SiberCore Technologies"}, + { 2, 0x98, "Southland Microsystems"}, + { 2, 0x19, "Malleable Technologies"}, + { 2, 0x1a, "Kendin Communications"}, + { 2, 0x9b, "Great Technology Microcomputer"}, + { 2, 0x1c, "Sanmina"}, + { 2, 0x9d, "HADCO"}, + { 2, 0x9e, "Corsair"}, + { 2, 0x1f, "Actrans System"}, + { 2, 0x20, "ALPHA Technologies"}, + { 2, 0xa1, "Silicon Laboratories (Cygnal)"}, + { 2, 0xa2, "Artesyn Technologies"}, + { 2, 0x23, "Align Manufacturing"}, + { 2, 0xa4, "Peregrine Semiconductor"}, + { 2, 0x25, "Chameleon Systems"}, + { 2, 0x26, "Aplus Flash Technology"}, + { 2, 0xa7, "MIPS Technologies"}, + { 2, 0xa8, "Chrysalis ITS"}, + { 2, 0x29, "ADTEC"}, + { 2, 0x2a, "Kentron Technologies"}, + { 2, 0xab, "Win Technologies"}, + { 2, 0x2c, "Tachyon Semiconductor (ASIC)"}, + { 2, 0xad, "Extreme Packet Devices"}, + { 2, 0xae, "RF Micro Devices"}, + { 2, 0x2f, "Siemens AG"}, + { 2, 0xb0, "Sarnoff"}, + { 2, 0x31, "Itautec SA"}, + { 2, 0x32, "Radiata"}, + { 2, 0xb3, "Benchmark Elect. (AVEX)"}, + { 2, 0x34, "Legend"}, + { 2, 0xb5, "SpecTek"}, + { 2, 0xb6, "Hi/fn"}, + { 2, 0x37, "Enikia"}, + { 2, 0x38, "SwitchOn Networks"}, + { 2, 0xb9, "AANetcom"}, + { 2, 0xba, "Micro Memory Bank"}, + { 2, 0x3b, "ESS Technology"}, + { 2, 0xbc, "Virata"}, + { 2, 0x3d, "Excess Bandwidth"}, + { 2, 0x3e, "West Bay Semiconductor"}, + { 2, 0xbf, "DSP Group"}, + { 2, 0x40, "Newport Communications"}, + { 2, 0xc1, "Chip2Chip"}, + { 2, 0xc2, "Phobos"}, + { 2, 0x43, "Intellitech"}, + { 2, 0xc4, "Nordic VLSI ASA"}, + { 2, 0x45, "Ishoni Networks"}, + { 2, 0x46, "Silicon Spice"}, + { 2, 0xc7, "Alchemy Semiconductor"}, + { 2, 0xc8, "Agilent Technologies"}, + { 2, 0x49, "Centillium Communications"}, + { 2, 0x4a, "W.L. Gore"}, + { 2, 0xcb, "HanBit Electronics"}, + { 2, 0x4c, "GlobeSpan"}, + { 2, 0xcd, "Element 14"}, + { 2, 0xce, "Pycon"}, + { 2, 0x4f, "Saifun Semiconductors"}, + { 2, 0xd0, "Sibyte,"}, + { 2, 0x51, "MetaLink Technologies"}, + { 2, 0x52, "Feiya Technology"}, + { 2, 0xd3, "I & C Technology"}, + { 2, 0x54, "Shikatronics"}, + { 2, 0xd5, "Elektrobit"}, + { 2, 0xd6, "Megic"}, + { 2, 0x57, "Com-Tier"}, + { 2, 0x58, "Malaysia Micro Solutions"}, + { 2, 0xd9, "Hyperchip"}, + { 2, 0xda, "Gemstone Communications"}, + { 2, 0x5b, "Anadigm (Anadyne)"}, + { 2, 0xdc, "3ParData"}, + { 2, 0x5d, "Mellanox Technologies"}, + { 2, 0x5e, "Tenx Technologies"}, + { 2, 0xdf, "Helix AG"}, + { 2, 0xe0, "Domosys"}, + { 2, 0x61, "Skyup Technology"}, + { 2, 0x62, "HiNT"}, + { 2, 0xe3, "Chiaro"}, + { 2, 0x64, "MDT Technologies"}, + { 2, 0xe5, "Exbit Technology A/S"}, + { 2, 0xe6, "Integrated Technology Express"}, + { 2, 0x67, "AVED Memory"}, + { 2, 0x68, "Legerity"}, + { 2, 0xe9, "Jasmine Networks"}, + { 2, 0xea, "Caspian Networks"}, + { 2, 0x6b, "nCUBE"}, + { 2, 0xec, "Silicon Access Networks"}, + { 2, 0x6d, "FDK"}, + { 2, 0x6e, "High Bandwidth Access"}, + { 2, 0xef, "MultiLink Technology"}, + { 2, 0x70, "BRECIS"}, + { 2, 0xf1, "World Wide Packets"}, + { 2, 0xf2, "APW"}, + { 2, 0x73, "Chicory Systems"}, + { 2, 0xf4, "Xstream Logic"}, + { 2, 0x75, "Fast-Chip"}, + { 2, 0x76, "Zucotto Wireless"}, + { 2, 0xf7, "Realchip"}, + { 2, 0xf8, "Galaxy Power"}, + { 2, 0x79, "eSilicon"}, + { 2, 0x7a, "Morphics Technology"}, + { 2, 0xfb, "Accelerant Networks"}, + { 2, 0x7c, "Silicon Wave"}, + { 2, 0xfd, "SandCraft"}, + { 2, 0xfe, "Elpida"}, + { 3, 0x01, "Solectron"}, + { 3, 0x02, "Optosys Technologies"}, + { 3, 0x83, "Buffalo (Formerly Melco)"}, + { 3, 0x04, "TriMedia Technologies"}, + { 3, 0x85, "Cyan Technologies"}, + { 3, 0x86, "Global Locate"}, + { 3, 0x07, "Optillion"}, + { 3, 0x08, "Terago Communications"}, + { 3, 0x89, "Ikanos Communications"}, + { 3, 0x8a, "Preton Technology"}, + { 3, 0x0b, "Nanya Technology"}, + { 3, 0x8c, "Elite Flash Storage"}, + { 3, 0x0d, "Mysticom"}, + { 3, 0x0e, "LightSand Communications"}, + { 3, 0x8f, "ATI Technologies"}, + { 3, 0x10, "Agere Systems"}, + { 3, 0x91, "NeoMagic"}, + { 3, 0x92, "AuroraNetics"}, + { 3, 0x13, "Geil"}, + { 3, 0x94, "Mushkin"}, + { 3, 0x15, "Tioga Technologies"}, + { 3, 0x16, "Netlist"}, + { 3, 0x97, "TeraLogic"}, + { 3, 0x98, "Cicada Semiconductor"}, + { 3, 0x19, "Centon Electronics"}, + { 3, 0x1a, "Tyco Electronics"}, + { 3, 0x9b, "Magis Works"}, + { 3, 0x1c, "Zettacom"}, + { 3, 0x9d, "Cogency Semiconductor"}, + { 3, 0x9e, "Chipcon AS"}, + { 3, 0x1f, "Aspex Technology"}, + { 3, 0x20, "F5 Networks"}, + { 3, 0xa1, "Programmable Silicon Solutions"}, + { 3, 0xa2, "ChipWrights"}, + { 3, 0x23, "Acorn Networks"}, + { 3, 0xa4, "Quicklogic"}, + { 3, 0x25, "Kingmax Semiconductor"}, + { 3, 0x26, "BOPS"}, + { 3, 0xa7, "Flasys"}, + { 3, 0xa8, "BitBlitz Communications"}, + { 3, 0x29, "eMemory Technology"}, + { 3, 0x2a, "Procket Networks"}, + { 3, 0xab, "Purple Ray"}, + { 3, 0x2c, "Trebia Networks"}, + { 3, 0xad, "Delta Electronics"}, + { 3, 0xae, "Onex Communications"}, + { 3, 0x2f, "Ample Communications"}, + { 3, 0xb0, "Memory Experts Intl"}, + { 3, 0x31, "Astute Networks"}, + { 3, 0x32, "Azanda Network Devices"}, + { 3, 0xb3, "Dibcom"}, + { 3, 0x34, "Tekmos"}, + { 3, 0xb5, "API NetWorks"}, + { 3, 0xb6, "Bay Microsystems"}, + { 3, 0x37, "Firecron"}, + { 3, 0x38, "Resonext Communications"}, + { 3, 0xb9, "Tachys Technologies"}, + { 3, 0xba, "Equator Technology"}, + { 3, 0x3b, "Concept Computer"}, + { 3, 0xbc, "SILCOM"}, + { 3, 0x3d, "3Dlabs"}, + { 3, 0x3e, "c?t Magazine"}, + { 3, 0xbf, "Sanera Systems"}, + { 3, 0x40, "Silicon Packets"}, + { 3, 0xc1, "Viasystems Group"}, + { 3, 0xc2, "Simtek"}, + { 3, 0x43, "Semicon Devices Singapore"}, + { 3, 0xc4, "Satron Handelsges"}, + { 3, 0x45, "Improv Systems"}, + { 3, 0x46, "INDUSYS"}, + { 3, 0xc7, "Corrent"}, + { 3, 0xc8, "Infrant Technologies"}, + { 3, 0x49, "Ritek Corp"}, + { 3, 0x4a, "empowerTel Networks"}, + { 3, 0xcb, "Hypertec"}, + { 3, 0x4c, "Cavium Networks"}, + { 3, 0xcd, "PLX Technology"}, + { 3, 0xce, "Massana Design"}, + { 3, 0x4f, "Intrinsity"}, + { 3, 0xd0, "Valence Semiconductor"}, + { 3, 0x51, "Terawave Communications"}, + { 3, 0x52, "IceFyre Semiconductor"}, + { 3, 0xd3, "Primarion"}, + { 3, 0x54, "Picochip Designs"}, + { 3, 0xd5, "Silverback Systems"}, + { 3, 0xd6, "Jade Star Technologies"}, + { 3, 0x57, "Pijnenburg Securealink"}, + { 3, 0x58, "takeMS International AG"}, + { 3, 0xd9, "Cambridge Silicon Radio"}, + { 3, 0xda, "Swissbit"}, + { 3, 0x5b, "Nazomi Communications"}, + { 3, 0xdc, "eWave System"}, + { 3, 0x5d, "Rockwell Collins"}, + { 3, 0x5e, "Picocel Co. (Paion)"}, + { 3, 0xdf, "Alphamosaic"}, + { 3, 0xe0, "Sandburst"}, + { 3, 0x61, "SiCon Video"}, + { 3, 0x62, "NanoAmp Solutions"}, + { 3, 0xe3, "Ericsson Technology"}, + { 3, 0x64, "PrairieComm"}, + { 3, 0xe5, "Mitac International"}, + { 3, 0xe6, "Layer N Networks"}, + { 3, 0x67, "MtekVision (Atsana)"}, + { 3, 0x68, "Allegro Networks"}, + { 3, 0xe9, "Marvell Semiconductors"}, + { 3, 0xea, "Netergy Microelectronic"}, + { 3, 0x6b, "NVIDIA"}, + { 3, 0xec, "Internet Machines"}, + { 3, 0x6d, "Peak Electronics"}, + { 3, 0x6e, "Litchfield Communication"}, + { 3, 0xef, "Accton Technology"}, + { 3, 0x70, "Teradiant Networks"}, + { 3, 0xf1, "Scaleo Chip"}, + { 3, 0xf2, "Cortina Systems"}, + { 3, 0x73, "RAM Components"}, + { 3, 0xf4, "Raqia Networks"}, + { 3, 0x75, "ClearSpeed"}, + { 3, 0x76, "Matsushita Battery"}, + { 3, 0xf7, "Xelerated"}, + { 3, 0xf8, "SimpleTech"}, + { 3, 0x79, "Utron Technology"}, + { 3, 0x7a, "Astec International"}, + { 3, 0xfb, "AVM"}, + { 3, 0x7c, "Redux Communications"}, + { 3, 0xfd, "Dot Hill Systems"}, + { 3, 0xfe, "TeraChip"}, + { 4, 0x01, "T-RAM"}, + { 4, 0x02, "Innovics Wireless"}, + { 4, 0x83, "Teknovus"}, + { 4, 0x04, "KeyEye Communications"}, + { 4, 0x85, "Runcom Technologies"}, + { 4, 0x86, "RedSwitch"}, + { 4, 0x07, "Dotcast"}, + { 4, 0x08, "Silicon Mountain Memory"}, + { 4, 0x89, "Signia Technologies"}, + { 4, 0x8a, "Pixim"}, + { 4, 0x0b, "Galazar Networks"}, + { 4, 0x8c, "White Electronic Designs"}, + { 4, 0x0d, "Patriot Scientific"}, + { 4, 0x0e, "Neoaxiom"}, + { 4, 0x8f, "3Y Power Technology"}, + { 4, 0x10, "Scaleo Chip"}, + { 4, 0x91, "Potentia Power Systems"}, + { 4, 0x92, "C-guys"}, + { 4, 0x13, "Digital Communications Technology"}, + { 4, 0x94, "Silicon-Based Technology"}, + { 4, 0x15, "Fulcrum Microsystems"}, + { 4, 0x16, "Positivo Informatica"}, + { 4, 0x97, "XIOtech"}, + { 4, 0x98, "PortalPlayer"}, + { 4, 0x19, "Zhiying Software"}, + { 4, 0x1a, "ParkerVision"}, + { 4, 0x9b, "Phonex Broadband"}, + { 4, 0x1c, "Skyworks Solutions"}, + { 4, 0x9d, "Entropic Communications"}, + { 4, 0x9e, "Pacific Force Technology"}, + { 4, 0x1f, "Zensys A/S"}, + { 4, 0x20, "Legend Silicon Corp."}, + { 4, 0xa1, "Sci-worx"}, + { 4, 0xa2, "SMSC (Standard Microsystems)"}, + { 4, 0x23, "Renesas Technology"}, + { 4, 0xa4, "Raza Microelectronics"}, + { 4, 0x25, "Phyworks"}, + { 4, 0x26, "MediaTek"}, + { 4, 0xa7, "Non-cents Productions"}, + { 4, 0xa8, "US Modular"}, + { 4, 0x29, "Wintegra"}, + { 4, 0x2a, "Mathstar"}, + { 4, 0xab, "StarCore"}, + { 4, 0x2c, "Oplus Technologies"}, + { 4, 0xad, "Mindspeed"}, + { 4, 0xae, "Just Young Computer"}, + { 4, 0x2f, "Radia Communications"}, + { 4, 0xb0, "OCZ"}, + { 4, 0x31, "Emuzed"}, + { 4, 0x32, "LOGIC Devices"}, + { 4, 0xb3, "Inphi"}, + { 4, 0x34, "Quake Technologies"}, + { 4, 0xb5, "Vixel"}, + { 4, 0xb6, "SolusTek"}, + { 4, 0x37, "Kongsberg Maritime"}, + { 4, 0x38, "Faraday Technology"}, + { 4, 0xb9, "Altium"}, + { 4, 0xba, "Insyte"}, + { 4, 0x3b, "ARM"}, + { 4, 0xbc, "DigiVision"}, + { 4, 0x3d, "Vativ Technologies"}, + { 4, 0x3e, "Endicott Interconnect Technologies"}, + { 4, 0xbf, "Pericom"}, + { 4, 0x40, "Bandspeed"}, + { 4, 0xc1, "LeWiz Communications"}, + { 4, 0xc2, "CPU Technology"}, + { 4, 0x43, "Ramaxel Technology"}, + { 4, 0xc4, "DSP Group"}, + { 4, 0x45, "Axis Communications"}, + { 4, 0x46, "Legacy Electronics"}, + { 4, 0xc7, "Chrontel"}, + { 4, 0xc8, "Powerchip Semiconductor"}, + { 4, 0x49, "MobilEye Technologies"}, + { 4, 0x4a, "Excel Semiconductor"}, + { 4, 0xcb, "A-DATA Technology"}, + { 4, 0x4c, "VirtualDigm"}, + { 4, 0xcd, "G Skill Intl"}, + { 4, 0xce, "Quanta Computer"}, + { 4, 0x4f, "Yield Microelectronics"}, + { 4, 0xd0, "Afa Technologies"}, + { 4, 0x51, "KINGBOX Technology Co."}, + { 4, 0x52, "Ceva"}, + { 4, 0xd3, "iStor Networks"}, + { 4, 0x54, "Advance Modules"}, + { 4, 0xd5, "Microsoft"}, + { 4, 0xd6, "Open-Silicon"}, + { 4, 0x57, "Goal Semiconductor"}, + { 4, 0x58, "ARC International"}, + { 4, 0xd9, "Simmtec"}, + { 4, 0xda, "Metanoia"}, + { 4, 0x5b, "Key Stream"}, + { 4, 0xdc, "Lowrance Electronics"}, + { 4, 0x5d, "Adimos"}, + { 4, 0x5e, "SiGe Semiconductor"}, + { 4, 0xdf, "Fodus Communications"}, + { 4, 0xe0, "Credence Systems Corp."}, + { 4, 0x61, "Genesis Microchip"}, + { 4, 0x62, "Vihana"}, + { 4, 0xe3, "WIS Technologies"}, + { 4, 0x64, "GateChange Technologies"}, + { 4, 0xe5, "High Density Devices AS"}, + { 4, 0xe6, "Synopsys"}, + { 4, 0x67, "Gigaram"}, + { 4, 0x68, "Enigma Semiconductor"}, + { 4, 0xe9, "Century Micro"}, + { 4, 0xea, "Icera Semiconductor"}, + { 4, 0x6b, "Mediaworks Integrated Systems"}, + { 4, 0xec, "O?Neil Product Development"}, + { 4, 0x6d, "Supreme Top Technology"}, + { 4, 0x6e, "MicroDisplay"}, + { 4, 0xef, "Team Group"}, + { 4, 0x70, "Sinett"}, + { 4, 0xf1, "Toshiba"}, + { 4, 0xf2, "Tensilica"}, + { 4, 0x73, "SiRF Technology"}, + { 4, 0xf4, "Bacoc"}, + { 4, 0x75, "SMaL Camera Technologies"}, + { 4, 0x76, "Thomson SC"}, + { 4, 0xf7, "Airgo Networks"}, + { 4, 0xf8, "Wisair"}, + { 4, 0x79, "SigmaTel"}, + { 4, 0x7a, "Arkados"}, + { 4, 0xfb, "Compete IT Co. KG"}, + { 4, 0x7c, "Eudar Technology"}, + { 4, 0xfd, "Focus Enhancements"}, + { 4, 0xfe, "Xyratex"}, + { 5, 0x01, "Specular Networks"}, + { 5, 0x02, "PDP Systems"}, + { 5, 0x83, "U-Chip Technology Corp."}, + { 5, 0x04, "Silicon Optix"}, + { 5, 0x85, "Greenfield Networks"}, + { 5, 0x86, "CompuRAM"}, + { 5, 0x07, "Stargen"}, + { 5, 0x08, "NetCell"}, + { 5, 0x89, "Excalibrus Technologies"}, + { 5, 0x8a, "SCM Microsystems"}, + { 5, 0x0b, "Xsigo Systems"}, + { 5, 0x8c, "CHIPS & Systems"}, + { 5, 0x0d, "Tier"}, + { 5, 0x0e, "CWRL Labs"}, + { 5, 0x8f, "Teradici"}, + { 5, 0x10, "Gigaram"}, + { 5, 0x91, "g2 Microsystems"}, + { 5, 0x92, "PowerFlash Semiconductor"}, + { 5, 0x13, "P.A. Semi"}, + { 5, 0x94, "NovaTech Solutions, S.A."}, + { 5, 0x15, "c2 Microsystems"}, + { 5, 0x16, "Level5 Networks"}, + { 5, 0x97, "COS Memory AG"}, + { 5, 0x98, "Innovasic Semiconductor"}, + { 5, 0x19, "02IC Co."}, + { 5, 0x1a, "Tabula,"}, + { 5, 0x9b, "Crucial Technology"}, + { 5, 0x1c, "Chelsio Communications"}, + { 5, 0x9d, "Solarflare Communications"}, + { 5, 0x9e, "Xambala"}, + { 5, 0x1f, "EADS Astrium"}, + { 5, 0x20, "Terra Semiconductor"}, + { 5, 0xa1, "Imaging Works"}, + { 5, 0xa2, "Astute Networks"}, + { 5, 0x23, "Tzero"}, + { 5, 0xa4, "Emulex"}, + { 5, 0x25, "Power-One"}, + { 5, 0x26, "Pulse~LINK"}, + { 5, 0xa7, "Hon Hai Precision Industry"}, + { 5, 0xa8, "White Rock Networks"}, + { 5, 0x29, "Telegent Systems USA"}, + { 5, 0x2a, "Atrua Technologies"}, + { 5, 0xab, "Acbel Polytech"}, + { 5, 0x2c, "eRide"}, + { 5, 0xad, "ULi Electronics"}, + { 5, 0xae, "Magnum Semiconductor"}, + { 5, 0x2f, "neoOne Technology"}, + { 5, 0xb0, "Connex Technology"}, + { 5, 0x31, "Stream Processors"}, + { 5, 0x32, "Focus Enhancements"}, + { 5, 0xb3, "Telecis Wireless"}, + { 5, 0x34, "uNav Microelectronics"}, + { 5, 0xb5, "Tarari"}, + { 5, 0xb6, "Ambric"}, + { 5, 0x37, "Newport Media"}, + { 5, 0x38, "VMTS"}, + { 5, 0xb9, "Enuclia Semiconductor"}, + { 5, 0xba, "Virtium Technology"}, + { 5, 0x3b, "Solid State System Co."}, + { 5, 0xbc, "Kian Tech LLC"}, + { 5, 0x3d, "Artimi"}, + { 5, 0x3e, "Power Quotient International"}, + { 5, 0xbf, "Avago Technologies"}, + { 5, 0x40, "ADTechnology"}, + { 5, 0xc1, "Sigma Designs"}, + { 5, 0xc2, "SiCortex"}, + { 5, 0x43, "Ventura Technology Group"}, + { 5, 0xc4, "eASIC"}, + { 5, 0x45, "M.H.S. SAS"}, + { 5, 0x46, "Micro Star International"}, + { 5, 0xc7, "Rapport"}, + { 5, 0xc8, "Makway International"}, + { 5, 0x49, "Broad Reach Engineering Co."}, + { 5, 0x4a, "Semiconductor Mfg Intl Corp"}, + { 5, 0xcb, "SiConnect"}, + { 5, 0x4c, "FCI USA"}, + { 5, 0xcd, "Validity Sensors"}, + { 5, 0xce, "Coney Technology Co."}, + { 5, 0x4f, "Spans Logic"}, + { 5, 0xd0, "Neterion"}, + { 5, 0x51, "Qimonda"}, + { 5, 0x52, "New Japan Radio Co."}, + { 5, 0xd3, "Velogix"}, + { 5, 0x54, "Montalvo Systems"}, + { 5, 0xd5, "iVivity"}, + { 5, 0xd6, "Walton Chaintech"}, + { 5, 0x57, "AENEON"}, + { 5, 0x58, "Lorom Industrial Co."}, + { 5, 0xd9, "Radiospire Networks"}, + { 5, 0xda, "Sensio Technologies"}, + { 5, 0x5b, "Nethra Imaging"}, + { 5, 0xdc, "Hexon Technology Pte"}, + { 5, 0x5d, "CompuStocx (CSX)"}, + { 5, 0x5e, "Methode Electronics"}, + { 5, 0xdf, "Connect One"}, + { 5, 0xe0, "Opulan Technologies"}, + { 5, 0x61, "Septentrio NV"}, + { 5, 0x62, "Goldenmars Technology"}, + { 5, 0xe3, "Kreton"}, + { 5, 0x64, "Cochlear"}, + { 5, 0xe5, "Altair Semiconductor"}, + { 5, 0xe6, "NetEffect"}, + { 5, 0x67, "Spansion"}, + { 5, 0x68, "Taiwan Semiconductor Mfg"}, + { 5, 0xe9, "Emphany Systems"}, + { 5, 0xea, "ApaceWave Technologies"}, + { 5, 0x6b, "Mobilygen"}, + { 5, 0xec, "Tego"}, + { 5, 0x6d, "Cswitch"}, + { 5, 0x6e, "Haier (Beijing) IC Design Co."}, + { 5, 0xef, "MetaRAM"}, + { 5, 0x70, "Axel Electronics Co."}, + { 5, 0xf1, "Tilera"}, + { 5, 0xf2, "Aquantia"}, + { 5, 0x73, "Vivace Semiconductor"}, + { 5, 0xf4, "Redpine Signals"}, + { 5, 0x75, "Octalica"}, + { 5, 0x76, "InterDigital Communications"}, + { 5, 0xf7, "Avant Technology"}, + { 5, 0xf8, "Asrock"}, + { 5, 0x79, "Availink"}, + { 5, 0x7a, "Quartics"}, + { 5, 0xfb, "Element CXI"}, + { 5, 0x7c, "Innovaciones Microelectronicas"}, + { 5, 0xfd, "VeriSilicon Microelectronics"}, + { 5, 0xfe, "W5 Networks"}, + { 6, 0x01, "MOVEKING"}, + { 6, 0x02, "Mavrix Technology"}, + { 6, 0x83, "CellGuide"}, + { 6, 0x04, "Faraday Technology"}, + { 6, 0x85, "Diablo Technologies"}, + { 6, 0x86, "Jennic"}, + { 6, 0x07, "Octasic"}, + { 6, 0x08, "Molex"}, + { 6, 0x89, "3Leaf Networks"}, + { 6, 0x8a, "Bright Micron Technology"}, + { 6, 0x0b, "Netxen"}, + { 6, 0x8c, "NextWave Broadband"}, + { 6, 0x0d, "DisplayLink"}, + { 6, 0x0e, "ZMOS Technology"}, + { 6, 0x8f, "Tec-Hill"}, + { 6, 0x10, "Multigig"}, + { 6, 0x91, "Amimon"}, + { 6, 0x92, "Euphonic Technologies"}, + { 6, 0x13, "BRN Phoenix"}, + { 6, 0x94, "InSilica"}, + { 6, 0x15, "Ember"}, + { 6, 0x16, "Avexir Technologies"}, + { 6, 0x97, "Echelon"}, + { 6, 0x98, "Edgewater Computer Systems"}, + { 6, 0x19, "XMOS Semiconductor"}, + { 6, 0x1a, "GENUSION"}, + { 6, 0x9b, "Memory Corp NV"}, + { 6, 0x1c, "SiliconBlue Technologies"}, + { 6, 0x9d, "Rambus"}, + { 6, 0x9e, "Andes Technology"}, + { 6, 0x1f, "Coronis Systems"}, + { 6, 0x20, "Achronix Semiconductor"}, + { 6, 0xa1, "Siano Mobile Silicon"}, + { 6, 0xa2, "Semtech"}, + { 6, 0x23, "Pixelworks"}, + { 6, 0xa4, "Gaisler Research AB"}, + { 6, 0x25, "Teranetics"}, + { 6, 0x26, "Toppan Printing Co."}, + { 6, 0xa7, "Kingxcon"}, + { 6, 0xa8, "Silicon Integrated Systems"}, + { 6, 0x29, "I-O Data Device"}, + { 6, 0x2a, "NDS Americas"}, + { 6, 0xab, "Solomon Systech Limited"}, + { 6, 0x2c, "On Demand Microelectronics"}, + { 6, 0xad, "Amicus Wireless"}, + { 6, 0xae, "SMARDTV SNC"}, + { 6, 0x2f, "Comsys Communication"}, + { 6, 0xb0, "Movidia"}, + { 6, 0x31, "Javad GNSS"}, + { 6, 0x32, "Montage Technology Group"}, + { 6, 0xb3, "Trident Microsystems"}, + { 6, 0x34, "Super Talent"}, + { 6, 0xb5, "Optichron"}, + { 6, 0xb6, "Future Waves UK"}, + { 6, 0x37, "SiBEAM"}, + { 6, 0x38, "Inicore,"}, + { 6, 0xb9, "Virident Systems"}, + { 6, 0xba, "M2000"}, + { 6, 0x3b, "ZeroG Wireless"}, + { 6, 0xbc, "Gingle Technology Co."}, + { 6, 0x3d, "Space Micro"}, + { 6, 0x3e, "Wilocity"}, + { 6, 0xbf, "Novafora, Ic."}, + { 6, 0x40, "iKoa"}, + { 6, 0xc1, "ASint Technology"}, + { 6, 0xc2, "Ramtron"}, + { 6, 0x43, "Plato Networks"}, + { 6, 0xc4, "IPtronics AS"}, + { 6, 0x45, "Infinite-Memories"}, + { 6, 0x46, "Parade Technologies"}, + { 6, 0xc7, "Dune Networks"}, + { 6, 0xc8, "GigaDevice Semiconductor"}, + { 6, 0x49, "Modu"}, + { 6, 0x4a, "CEITEC"}, + { 6, 0xcb, "Northrop Grumman"}, + { 6, 0x4c, "XRONET"}, + { 6, 0xcd, "Sicon Semiconductor AB"}, + { 6, 0xce, "Atla Electronics Co."}, + { 6, 0x4f, "TOPRAM Technology"}, + { 6, 0xd0, "Silego Technology"}, + { 6, 0x51, "Kinglife"}, + { 6, 0x52, "Ability Industries"}, + { 6, 0xd3, "Silicon Power Computer & Communications"}, + { 6, 0x54, "Augusta Technology"}, + { 6, 0xd5, "Nantronics Semiconductors"}, + { 6, 0xd6, "Hilscher Gesellschaft"}, + { 6, 0x57, "Quixant"}, + { 6, 0x58, "Percello"}, + { 6, 0xd9, "NextIO"}, + { 6, 0xda, "Scanimetrics"}, + { 6, 0x5b, "FS-Semi Company"}, + { 6, 0xdc, "Infinera"}, + { 6, 0x5d, "SandForce"}, + { 6, 0x5e, "Lexar Media"}, + { 6, 0xdf, "Teradyne"}, + { 6, 0xe0, "Memory Exchange Corp."}, + { 6, 0x61, "Suzhou Smartek Electronics"}, + { 6, 0x62, "Avantium"}, + { 6, 0xe3, "ATP Electronics"}, + { 6, 0x64, "Valens Semiconductor"}, + { 6, 0xe5, "Agate Logic"}, + { 6, 0xe6, "Netronome"}, + { 6, 0x67, "Zenverge"}, + { 6, 0x68, "N-trig"}, + { 6, 0xe9, "SanMax Technologies"}, + { 6, 0xea, "Contour Semiconductor"}, + { 6, 0x6b, "TwinMOS"}, + { 6, 0xec, "Silicon Systems"}, + { 6, 0x6d, "V-Color Technology"}, + { 6, 0x6e, "Certicom"}, + { 6, 0xef, "JSC ICC Milandr"}, + { 6, 0x70, "PhotoFast Global"}, + { 6, 0xf1, "InnoDisk"}, + { 6, 0xf2, "Muscle Power"}, + { 6, 0x73, "Energy Micro"}, + { 6, 0xf4, "Innofidei"}, + { 9, 0xff, ""} +}; + +#define VEN_MAP_SIZE (sizeof(vendorMap)/sizeof(VenIdName)) + +#endif Index: branches/Chimera/i386/libsaio/.svn/text-base/msdos_private.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/msdos_private.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/msdos_private.h.svn-base (revision 850) @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2004 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Written by Paul Popelka (paulp@uts.amdahl.com) + * + * You can do anything you want with this software, just don't say you wrote + * it, and don't remove this notice. + * + * This software is provided "as is". + * + * The author supplies this software to be publicly redistributed on the + * understanding that the author is not responsible for the correct + * functioning of this software in any circumstances and is not liable for + * any damages caused by this software. + * + * October 1992 + */ + +/* + * Format of a boot sector. This is the first sector on a DOS floppy disk + * or the fist sector of a partition on a hard disk. But, it is not the + * first sector of a partitioned hard disk. + */ +struct bootsector33 { + u_int8_t bsJump[3]; /* jump inst E9xxxx or EBxx90 */ + int8_t bsOemName[8]; /* OEM name and version */ + int8_t bsBPB[19]; /* BIOS parameter block */ + int8_t bsDriveNumber; /* drive number (0x80) */ + int8_t bsBootCode[479]; /* pad so struct is 512b */ + u_int8_t bsBootSectSig0; + u_int8_t bsBootSectSig1; +#define BOOTSIG0 0x55 +#define BOOTSIG1 0xaa +}; + +struct extboot { + int8_t exDriveNumber; /* drive number (0x80) */ + int8_t exReserved1; /* reserved */ + int8_t exBootSignature; /* ext. boot signature (0x29) */ +#define EXBOOTSIG 0x29 + int8_t exVolumeID[4]; /* volume ID number */ + int8_t exVolumeLabel[11]; /* volume label */ + int8_t exFileSysType[8]; /* fs type (FAT12 or FAT16) */ +}; + +struct bootsector50 { + u_int8_t bsJump[3]; /* jump inst E9xxxx or EBxx90 */ + int8_t bsOemName[8]; /* OEM name and version */ + int8_t bsBPB[25]; /* BIOS parameter block */ + int8_t bsExt[26]; /* Bootsector Extension */ + int8_t bsBootCode[448]; /* pad so structure is 512b */ + u_int8_t bsBootSectSig0; + u_int8_t bsBootSectSig1; +#define BOOTSIG0 0x55 +#define BOOTSIG1 0xaa +}; + +struct bootsector710 { + u_int8_t bsJump[3]; /* jump inst E9xxxx or EBxx90 */ + int8_t bsOEMName[8]; /* OEM name and version */ + int8_t bsBPB[53]; /* BIOS parameter block */ + int8_t bsExt[26]; /* Bootsector Extension */ + int8_t bsBootCode[420]; /* pad so structure is 512b */ + u_int8_t bsBootSectSig0; + u_int8_t bsBootSectSig1; +#define BOOTSIG0 0x55 +#define BOOTSIG1 0xaa +}; + +union bootsector { + struct bootsector33 bs33; + struct bootsector50 bs50; + struct bootsector710 bs710; +}; + + +/* BPB */ + +/* + * BIOS Parameter Block (BPB) for DOS 3.3 + */ +struct bpb33 { + u_int16_t bpbBytesPerSec; /* bytes per sector */ + u_int8_t bpbSecPerClust; /* sectors per cluster */ + u_int16_t bpbResSectors; /* number of reserved sectors */ + u_int8_t bpbFATs; /* number of FATs */ + u_int16_t bpbRootDirEnts; /* number of root directory entries */ + u_int16_t bpbSectors; /* total number of sectors */ + u_int8_t bpbMedia; /* media descriptor */ + u_int16_t bpbFATsecs; /* number of sectors per FAT */ + u_int16_t bpbSecPerTrack; /* sectors per track */ + u_int16_t bpbHeads; /* number of heads */ + u_int16_t bpbHiddenSecs; /* number of hidden sectors */ +} __attribute__((packed)); + +/* + * BPB for DOS 5.0 The difference is bpbHiddenSecs is a short for DOS 3.3, + * and bpbHugeSectors is not in the 3.3 bpb. + */ +struct bpb50 { + u_int16_t bpbBytesPerSec; /* bytes per sector */ + u_int8_t bpbSecPerClust; /* sectors per cluster */ + u_int16_t bpbResSectors; /* number of reserved sectors */ + u_int8_t bpbFATs; /* number of FATs */ + u_int16_t bpbRootDirEnts; /* number of root directory entries */ + u_int16_t bpbSectors; /* total number of sectors */ + u_int8_t bpbMedia; /* media descriptor */ + u_int16_t bpbFATsecs; /* number of sectors per FAT */ + u_int16_t bpbSecPerTrack; /* sectors per track */ + u_int16_t bpbHeads; /* number of heads */ + u_int32_t bpbHiddenSecs; /* # of hidden sectors */ + u_int32_t bpbHugeSectors; /* # of sectors if bpbSectors == 0 */ +} __attribute__((packed)); + +/* + * BPB for DOS 7.10 (FAT32). This one has a few extensions to bpb50. + */ +struct bpb710 { + u_int16_t bpbBytesPerSec; /* bytes per sector */ + u_int8_t bpbSecPerClust; /* sectors per cluster */ + u_int16_t bpbResSectors; /* number of reserved sectors */ + u_int8_t bpbFATs; /* number of FATs */ + u_int16_t bpbRootDirEnts; /* number of root directory entries */ + u_int16_t bpbSectors; /* total number of sectors */ + u_int8_t bpbMedia; /* media descriptor */ + u_int16_t bpbFATsecs; /* number of sectors per FAT */ + u_int16_t bpbSecPerTrack; /* sectors per track */ + u_int16_t bpbHeads; /* number of heads */ + u_int32_t bpbHiddenSecs; /* # of hidden sectors */ + u_int32_t bpbHugeSectors; /* # of sectors if bpbSectors == 0 */ + u_int32_t bpbBigFATsecs; /* like bpbFATsecs for FAT32 */ + u_int16_t bpbExtFlags; /* extended flags: */ +#define FATNUM 0xf /* mask for numbering active FAT */ +#define FATMIRROR 0x80 /* FAT is mirrored (like it always was) */ + u_int16_t bpbFSVers; /* filesystem version */ +#define FSVERS 0 /* currently only 0 is understood */ + u_int32_t bpbRootClust; /* start cluster for root directory */ + u_int16_t bpbFSInfo; /* filesystem info structure sector */ + u_int16_t bpbBackup; /* backup boot sector */ + /* There is a 12 byte filler here, but we ignore it */ +} __attribute__((packed)); + +#if 0 +/* + * BIOS Parameter Block (BPB) for DOS 3.3 + */ +struct byte_bpb33 { + int8_t bpbBytesPerSec[2]; /* bytes per sector */ + int8_t bpbSecPerClust; /* sectors per cluster */ + int8_t bpbResSectors[2]; /* number of reserved sectors */ + int8_t bpbFATs; /* number of FATs */ + int8_t bpbRootDirEnts[2]; /* number of root directory entries */ + int8_t bpbSectors[2]; /* total number of sectors */ + int8_t bpbMedia; /* media descriptor */ + int8_t bpbFATsecs[2]; /* number of sectors per FAT */ + int8_t bpbSecPerTrack[2]; /* sectors per track */ + int8_t bpbHeads[2]; /* number of heads */ + int8_t bpbHiddenSecs[2]; /* number of hidden sectors */ +}; + +/* + * BPB for DOS 5.0 The difference is bpbHiddenSecs is a short for DOS 3.3, + * and bpbHugeSectors is not in the 3.3 bpb. + */ +struct byte_bpb50 { + int8_t bpbBytesPerSec[2]; /* bytes per sector */ + int8_t bpbSecPerClust; /* sectors per cluster */ + int8_t bpbResSectors[2]; /* number of reserved sectors */ + int8_t bpbFATs; /* number of FATs */ + int8_t bpbRootDirEnts[2]; /* number of root directory entries */ + int8_t bpbSectors[2]; /* total number of sectors */ + int8_t bpbMedia; /* media descriptor */ + int8_t bpbFATsecs[2]; /* number of sectors per FAT */ + int8_t bpbSecPerTrack[2]; /* sectors per track */ + int8_t bpbHeads[2]; /* number of heads */ + int8_t bpbHiddenSecs[4]; /* number of hidden sectors */ + int8_t bpbHugeSectors[4]; /* # of sectors if bpbSectors == 0 */ +}; + +/* + * BPB for DOS 7.10 (FAT32). This one has a few extensions to bpb50. + */ +struct byte_bpb710 { + u_int8_t bpbBytesPerSec[2]; /* bytes per sector */ + u_int8_t bpbSecPerClust; /* sectors per cluster */ + u_int8_t bpbResSectors[2]; /* number of reserved sectors */ + u_int8_t bpbFATs; /* number of FATs */ + u_int8_t bpbRootDirEnts[2]; /* number of root directory entries */ + u_int8_t bpbSectors[2]; /* total number of sectors */ + u_int8_t bpbMedia; /* media descriptor */ + u_int8_t bpbFATsecs[2]; /* number of sectors per FAT */ + u_int8_t bpbSecPerTrack[2]; /* sectors per track */ + u_int8_t bpbHeads[2]; /* number of heads */ + u_int8_t bpbHiddenSecs[4]; /* # of hidden sectors */ + u_int8_t bpbHugeSectors[4]; /* # of sectors if bpbSectors == 0 */ + u_int8_t bpbBigFATsecs[4]; /* like bpbFATsecs for FAT32 */ + u_int8_t bpbExtFlags[2]; /* extended flags: */ + u_int8_t bpbFSVers[2]; /* filesystem version */ + u_int8_t bpbRootClust[4]; /* start cluster for root directory */ + u_int8_t bpbFSInfo[2]; /* filesystem info structure sector */ + u_int8_t bpbBackup[2]; /* backup boot sector */ + /* There is a 12 byte filler here, but we ignore it */ +}; +#endif + +/* + * FAT32 FSInfo block. + */ +struct fsinfo { + u_int8_t fsisig1[4]; + u_int8_t fsifill1[480]; + u_int8_t fsisig2[4]; + u_int8_t fsinfree[4]; + u_int8_t fsinxtfree[4]; + u_int8_t fsifill2[12]; + u_int8_t fsisig3[4]; +}; + + +/* direntry */ + +/*- + * Copyright (C) 1994, 1995, 1997 Wolfgang Solfrank. + * Copyright (C) 1994, 1995, 1997 TooLs GmbH. + * All rights reserved. + * Original code by Paul Popelka (paulp@uts.amdahl.com) (see above). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Structure of a dos directory entry. + */ +struct direntry { + u_int8_t deName[8]; /* filename, blank filled */ +#define SLOT_EMPTY 0x00 /* slot has never been used */ +#define SLOT_E5 0x05 /* the real value is 0xe5 */ +#define SLOT_DELETED 0xe5 /* file in this slot deleted */ + u_int8_t deExtension[3]; /* extension, blank filled */ + u_int8_t deAttributes; /* file attributes */ +#define ATTR_NORMAL 0x00 /* normal file */ +#define ATTR_READONLY 0x01 /* file is read-only (immutable) */ +#define ATTR_HIDDEN 0x02 /* file is hidden */ +#define ATTR_SYSTEM 0x04 /* file is a system file */ +#define ATTR_VOLUME 0x08 /* entry is a volume label */ +#define ATTR_DIRECTORY 0x10 /* entry is a directory name */ +#define ATTR_ARCHIVE 0x20 /* file is new or modified */ + u_int8_t deLowerCase; /* NT VFAT lower case flags */ +#define LCASE_BASE 0x08 /* filename base in lower case */ +#define LCASE_EXT 0x10 /* filename extension in lower case */ + u_int8_t deCHundredth; /* hundredth of seconds in CTime */ + u_int8_t deCTime[2]; /* create time */ + u_int8_t deCDate[2]; /* create date */ + u_int8_t deADate[2]; /* access date */ + u_int8_t deHighClust[2]; /* high bytes of cluster number */ + u_int16_t deMTime; /* last update time */ + u_int16_t deMDate; /* last update date */ + u_int8_t deStartCluster[2]; /* starting cluster of file */ + u_int8_t deFileSize[4]; /* size of file in bytes */ +}; + +/* + * Structure of a Win95 long name directory entry + */ +struct winentry { + u_int8_t weCnt; +#define WIN_LAST 0x40 +#define WIN_CNT 0x3f + u_int8_t wePart1[10]; + u_int8_t weAttributes; +#define ATTR_WIN95 0x0f + u_int8_t weReserved1; + u_int8_t weChksum; + u_int8_t wePart2[12]; + u_int16_t weReserved2; + u_int8_t wePart3[4]; +}; +#define WIN_CHARS 13 /* Number of chars per winentry */ + +/* + * Maximum filename length in Win95 + * Note: Must be < sizeof(dirent.d_name) + */ +#define WIN_MAXLEN 255 + +/* + * This is the format of the contents of the deTime field in the direntry + * structure. + * We don't use bitfields because we don't know how compilers for + * arbitrary machines will lay them out. + */ +#define DT_2SECONDS_MASK 0x1F /* seconds divided by 2 */ +#define DT_2SECONDS_SHIFT 0 +#define DT_MINUTES_MASK 0x7E0 /* minutes */ +#define DT_MINUTES_SHIFT 5 +#define DT_HOURS_MASK 0xF800 /* hours */ +#define DT_HOURS_SHIFT 11 + +/* + * This is the format of the contents of the deDate field in the direntry + * structure. + */ +#define DD_DAY_MASK 0x1F /* day of month */ +#define DD_DAY_SHIFT 0 +#define DD_MONTH_MASK 0x1E0 /* month */ +#define DD_MONTH_SHIFT 5 +#define DD_YEAR_MASK 0xFE00 /* year - 1980 */ +#define DD_YEAR_SHIFT 9 + Index: branches/Chimera/i386/libsaio/.svn/text-base/bootargs.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/bootargs.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/bootargs.h.svn-base (revision 850) @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2000 Apple Computer, Inc. All rights reserved. + * + * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ + * + * This file contains Original Code and/or Modifications of Original Code + * as defined in and that are subject to the Apple Public Source License + * Version 2.0 (the 'License'). You may not use this file except in + * compliance with the License. The rights granted to you under the License + * may not be used to create, or enable the creation or redistribution of, + * unlawful or unlicensed copies of an Apple operating system, or to + * circumvent, violate, or enable the circumvention or violation of, any + * terms of an Apple operating system software license agreement. + * + * Please obtain a copy of the License at + * http://www.opensource.apple.com/apsl/ and read it before using this file. + * + * The Original Code and all software distributed under the License are + * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. + * Please see the License for the specific language governing rights and + * limitations under the License. + * + * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ + */ +#ifndef _PEXPERT_I386_BOOT_H +#define _PEXPERT_I386_BOOT_H + +#include + +/* + * What the booter leaves behind for the kernel. + */ + +/* + * Types of boot driver that may be loaded by the booter. + */ +enum { + kBootDriverTypeInvalid = 0, + kBootDriverTypeKEXT = 1, + kBootDriverTypeMKEXT = 2 +}; + +enum { + kEfiReservedMemoryType = 0, + kEfiLoaderCode = 1, + kEfiLoaderData = 2, + kEfiBootServicesCode = 3, + kEfiBootServicesData = 4, + kEfiRuntimeServicesCode = 5, + kEfiRuntimeServicesData = 6, + kEfiConventionalMemory = 7, + kEfiUnusableMemory = 8, + kEfiACPIReclaimMemory = 9, + kEfiACPIMemoryNVS = 10, + kEfiMemoryMappedIO = 11, + kEfiMemoryMappedIOPortSpace = 12, + kEfiPalCode = 13, + kEfiMaxMemoryType = 14 +}; + +/* + * Memory range descriptor. + */ +typedef struct EfiMemoryRange { + uint32_t Type; + uint32_t Pad; + uint64_t PhysicalStart; + uint64_t VirtualStart; + uint64_t NumberOfPages; + uint64_t Attribute; +} EfiMemoryRange; + +#define BOOT_LINE_LENGTH 1024 +#define BOOT_STRING_LEN BOOT_LINE_LENGTH + +/* + * Video information.. + */ + +struct Boot_Video { + uint32_t v_baseAddr; /* Base address of video memory */ + uint32_t v_display; /* Display Code (if Applicable */ + uint32_t v_rowBytes; /* Number of bytes per pixel row */ + uint32_t v_width; /* Width */ + uint32_t v_height; /* Height */ + uint32_t v_depth; /* Pixel Depth */ +}; + +typedef struct Boot_Video Boot_Video; + +/* Values for v_display */ + +#define GRAPHICS_MODE 1 +#define FB_TEXT_MODE 2 + +/* Boot argument structure - passed into Mach kernel at boot time. + * "Revision" can be incremented for compatible changes + */ +// Lion +#define kBootArgsRevision 0 +#define kBootArgsVersion 2 + +// Snow Leopard and older +#define kBootArgsPreLionRevision 6 +#define kBootArgsPreLionVersion 1 + +/* Snapshot constants of previous revisions that are supported */ + +#define kBootArgsEfiMode32 32 +#define kBootArgsEfiMode64 64 + +typedef struct boot_args { + uint16_t Revision; /* Revision of boot_args structure */ + uint16_t Version; /* Version of boot_args structure */ + + uint8_t efiMode; /* 32 = 32-bit, 64 = 64-bit */ + uint8_t debugMode; /* Bit field with behavior changes */ + uint8_t __reserved1[2]; + + char CommandLine[BOOT_LINE_LENGTH]; /* Passed in command line */ + + uint32_t MemoryMap; /* Physical address of memory map */ + uint32_t MemoryMapSize; + uint32_t MemoryMapDescriptorSize; + uint32_t MemoryMapDescriptorVersion; + + Boot_Video Video; /* Video Information */ + + uint32_t deviceTreeP; /* Physical address of flattened device tree */ + uint32_t deviceTreeLength; /* Length of flattened tree */ + + uint32_t kaddr; /* Physical address of beginning of kernel text */ + uint32_t ksize; /* Size of combined kernel text+data+efi */ + + uint32_t efiRuntimeServicesPageStart; /* physical address of defragmented runtime pages */ + uint32_t efiRuntimeServicesPageCount; + uint64_t efiRuntimeServicesVirtualPageStart; /* virtual address of defragmented runtime pages */ + + uint32_t efiSystemTable; /* physical address of system table in runtime area */ + uint32_t __reserved2; + + uint32_t performanceDataStart; /* physical address of log */ + uint32_t performanceDataSize; + + uint32_t keyStoreDataStart; /* physical address of key store data */ + uint32_t keyStoreDataSize; + uint64_t bootMemStart; + uint64_t bootMemSize; + uint64_t PhysicalMemorySize; + uint64_t FSBFrequency; + uint32_t __reserved4[734]; + +} boot_args; + +typedef struct boot_args_pre_lion { + uint16_t Revision; /* Revision of boot_args structure */ + uint16_t Version; /* Version of boot_args structure */ + + char CommandLine[BOOT_LINE_LENGTH]; /* Passed in command line */ + + uint32_t MemoryMap; /* Physical address of memory map */ + uint32_t MemoryMapSize; + uint32_t MemoryMapDescriptorSize; + uint32_t MemoryMapDescriptorVersion; + + Boot_Video Video; /* Video Information */ + + uint32_t deviceTreeP; /* Physical address of flattened device tree */ + uint32_t deviceTreeLength; /* Length of flattened tree */ + + uint32_t kaddr; /* Physical address of beginning of kernel text */ + uint32_t ksize; /* Size of combined kernel text+data+efi */ + + uint32_t efiRuntimeServicesPageStart; /* physical address of defragmented runtime pages */ + uint32_t efiRuntimeServicesPageCount; + uint32_t efiSystemTable; /* physical address of system table in runtime area */ + + uint8_t efiMode; /* 32 = 32-bit, 64 = 64-bit */ + uint8_t __reserved1[3]; + uint32_t __reserved2[1]; + uint32_t performanceDataStart; /* physical address of log */ + uint32_t performanceDataSize; + uint64_t efiRuntimeServicesVirtualPageStart; /* virtual address of defragmented runtime pages */ + uint32_t __reserved3[2]; + +} boot_args_pre_lion; + +extern char gMacOSVersion[8]; + +#endif /* _PEXPERT_I386_BOOT_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/hfs.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/hfs.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/hfs.h.svn-base (revision 850) @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +extern long HFSInitPartition(CICell ih); +extern long HFSLoadFile(CICell ih, char * filePath); +extern long HFSReadFile(CICell ih, char * filePath, void *base, uint64_t offset, uint64_t length); +extern long HFSGetDirEntry(CICell ih, char * dirPath, long long * dirIndex, + char ** name, long * flags, long * time, + FinderInfo * finderInfo, long * infoValid); +extern void HFSGetDescription(CICell ih, char *str, long strMaxLen); +extern long HFSGetFileBlock(CICell ih, char *str, unsigned long long *firstBlock); +extern long HFSGetUUID(CICell ih, char *uuidStr); +extern void HFSFree(CICell ih); +extern bool HFSProbe (const void *buf); Index: branches/Chimera/i386/libsaio/.svn/text-base/cpu.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/cpu.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/cpu.c.svn-base (revision 850) @@ -0,0 +1,383 @@ +/* + * Copyright 2008 Islam Ahmed Zaid. All rights reserved. + * AsereBLN: 2009: cleanup and bugfix + */ + +#include "libsaio.h" +#include "platform.h" +#include "cpu.h" +#include "bootstruct.h" +#include "boot.h" + +#ifndef DEBUG_CPU +#define DEBUG_CPU 0 +#endif + +#if DEBUG_CPU +#define DBG(x...) printf(x) +#else +#define DBG(x...) msglog(x) +#endif + +/* + * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer + */ +static uint64_t measure_tsc_frequency(void) +{ + uint64_t tscStart; + uint64_t tscEnd; + uint64_t tscDelta = 0xffffffffffffffffULL; + unsigned long pollCount; + uint64_t retval = 0; + int i; + + /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT + * counter 2. We run this loop 3 times to make sure the cache + * is hot and we take the minimum delta from all of the runs. + * That is to say that we're biased towards measuring the minimum + * number of TSC ticks that occur while waiting for the timer to + * expire. That theoretically helps avoid inconsistencies when + * running under a VM if the TSC is not virtualized and the host + * steals time. The TSC is normally virtualized for VMware. + */ + for(i = 0; i < 10; ++i) + { + enable_PIT2(); + set_PIT2_mode0(CALIBRATE_LATCH); + tscStart = rdtsc64(); + pollCount = poll_PIT2_gate(); + tscEnd = rdtsc64(); + /* The poll loop must have run at least a few times for accuracy */ + if(pollCount <= 1) + continue; + /* The TSC must increment at LEAST once every millisecond. We + * should have waited exactly 30 msec so the TSC delta should + * be >= 30. Anything less and the processor is way too slow. + */ + if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) + continue; + // tscDelta = min(tscDelta, (tscEnd - tscStart)) + if( (tscEnd - tscStart) < tscDelta ) + tscDelta = tscEnd - tscStart; + } + /* tscDelta is now the least number of TSC ticks the processor made in + * a timespan of 0.03 s (e.g. 30 milliseconds) + * Linux thus divides by 30 which gives the answer in kiloHertz because + * 1 / ms = kHz. But we're xnu and most of the rest of the code uses + * Hz so we need to convert our milliseconds to seconds. Since we're + * dividing by the milliseconds, we simply multiply by 1000. + */ + + /* Unlike linux, we're not limited to 32-bit, but we do need to take care + * that we're going to multiply by 1000 first so we do need at least some + * arithmetic headroom. For now, 32-bit should be enough. + * Also unlike Linux, our compiler can do 64-bit integer arithmetic. + */ + if(tscDelta > (1ULL<<32)) + retval = 0; + else + { + retval = tscDelta * 1000 / 30; + } + disable_PIT2(); + return retval; +} + +/* + * Calculates the FSB and CPU frequencies using specific MSRs for each CPU + * - multi. is read from a specific MSR. In the case of Intel, there is: + * a max multi. (used to calculate the FSB freq.), + * and a current multi. (used to calculate the CPU freq.) + * - fsbFrequency = tscFrequency / multi + * - cpuFrequency = fsbFrequency * multi + */ + +void scan_cpu(PlatformInfo_t *p) +{ + uint64_t tscFrequency, fsbFrequency, cpuFrequency; + uint64_t msr, flex_ratio; + uint8_t maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv; + const char *newratio; + int len, myfsb; + uint8_t bus_ratio_min; + uint32_t max_ratio, min_ratio; + + max_ratio = min_ratio = myfsb = bus_ratio_min = 0; + maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0; + + /* get cpuid values */ + do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); + do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); + do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); + do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); + do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); + do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); + if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) { + do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]); + } +#if DEBUG_CPU + { + int i; + printf("CPUID Raw Values:\n"); + for (i=0; iCPU.CPUID[i][0], p->CPU.CPUID[i][1], + p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]); + } + } +#endif + p->CPU.Vendor = p->CPU.CPUID[CPUID_0][1]; + p->CPU.Signature = p->CPU.CPUID[CPUID_1][0]; + p->CPU.Stepping = bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); + p->CPU.Model = bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); + p->CPU.Family = bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); + p->CPU.ExtModel = bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); + p->CPU.ExtFamily = bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20); + + p->CPU.Model += (p->CPU.ExtModel << 4); + + if (p->CPU.Vendor == 0x756E6547 /* Intel */ && p->CPU.Family == 0x06 && p->CPU.Model >= 0x1a){ + msr = rdmsr64(MSR_CORE_THREAD_COUNT); // Undocumented MSR in Nehalem and newer CPUs + p->CPU.NoCores = bitfield((uint32_t)msr, 31, 16); // Using undocumented MSR to get actual values + p->CPU.NoThreads = bitfield((uint32_t)msr, 15, 0); // Using undocumented MSR to get actual values + } else { + p->CPU.NoThreads = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16); // Use previous method for Cores and Threads + p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1; + } + + /* get brand string (if supported) */ + /* Copyright: from Apple's XNU cpuid.c */ + if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) { + uint32_t reg[4]; + char str[128], *s; + /* + * The brand string 48 bytes (max), guaranteed to + * be NUL terminated. + */ + do_cpuid(0x80000002, reg); + bcopy((char *)reg, &str[0], 16); + do_cpuid(0x80000003, reg); + bcopy((char *)reg, &str[16], 16); + do_cpuid(0x80000004, reg); + bcopy((char *)reg, &str[32], 16); + for (s = str; *s != '\0'; s++) { + if (*s != ' ') break; + } + + strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString)); + + if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) { + /* + * This string means we have a firmware-programmable brand string, + * and the firmware couldn't figure out what sort of CPU we have. + */ + p->CPU.BrandString[0] = '\0'; + } + } + + /* setup features */ + if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_MMX; + } + if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE; + } + if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE2; + } + if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE3; + } + if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE41; + } + if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) { + p->CPU.Features |= CPU_FEATURE_SSE42; + } + if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_EM64T; + } + if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) { + p->CPU.Features |= CPU_FEATURE_MSR; + } + //if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) { + if (p->CPU.NoThreads > p->CPU.NoCores) { + p->CPU.Features |= CPU_FEATURE_HTT; + } + + tscFrequency = measure_tsc_frequency(); + fsbFrequency = 0; + cpuFrequency = 0; + + if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) { + int intelCPU = p->CPU.Model; + if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) { + /* Nehalem CPU model */ + if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || + p->CPU.Model == CPU_MODEL_FIELDS || + p->CPU.Model == CPU_MODEL_DALES || + p->CPU.Model == CPU_MODEL_DALES_32NM || + p->CPU.Model == CPU_MODEL_WESTMERE || + p->CPU.Model == CPU_MODEL_NEHALEM_EX || + p->CPU.Model == CPU_MODEL_WESTMERE_EX || + p->CPU.Model == CPU_MODEL_SANDY || + p->CPU.Model == CPU_MODEL_SANDY_XEON)) { + msr = rdmsr64(MSR_PLATFORM_INFO); + DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff); + bus_ratio_max = (msr >> 8) & 0xff; + bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1) + msr = rdmsr64(MSR_FLEX_RATIO); + DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff); + if ((msr >> 16) & 0x01) { + flex_ratio = (msr >> 8) & 0xff; + /* bcc9: at least on the gigabyte h67ma-ud2h, + where the cpu multipler can't be changed to + allow overclocking, the flex_ratio msr has unexpected (to OSX) + contents. These contents cause mach_kernel to + fail to compute the bus ratio correctly, instead + causing the system to crash since tscGranularity + is inadvertently set to 0. + */ + if (flex_ratio == 0) { + /* Clear bit 16 (evidently the + presence bit) */ + wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL)); + msr = rdmsr64(MSR_FLEX_RATIO); + verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff); + } else { + if (bus_ratio_max > flex_ratio) { + bus_ratio_max = flex_ratio; + } + } + } + + if (bus_ratio_max) { + fsbFrequency = (tscFrequency / bus_ratio_max); + } + //valv: Turbo Ratio Limit + if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) { + msr = rdmsr64(MSR_TURBO_RATIO_LIMIT); + cpuFrequency = bus_ratio_max * fsbFrequency; + max_ratio = bus_ratio_max * 10; + } else { + cpuFrequency = tscFrequency; + } + if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4)) { + max_ratio = atoi(newratio); + max_ratio = (max_ratio * 10); + if (len >= 3) max_ratio = (max_ratio + 5); + + verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio); + + // extreme overclockers may love 320 ;) + if ((max_ratio >= min_ratio) && (max_ratio <= 320)) { + cpuFrequency = (fsbFrequency * max_ratio) / 10; + if (len >= 3) maxdiv = 1; + else maxdiv = 0; + } else { + max_ratio = (bus_ratio_max * 10); + } + } + //valv: to be uncommented if Remarq.1 didn't stick + /*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/ + p->CPU.MaxRatio = max_ratio; + p->CPU.MinRatio = min_ratio; + + myfsb = fsbFrequency / 1000000; + verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio); + currcoef = bus_ratio_max; + } else { + msr = rdmsr64(MSR_IA32_PERF_STATUS); + DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff); + currcoef = (msr >> 8) & 0x1f; + /* Non-integer bus ratio for the max-multi*/ + maxdiv = (msr >> 46) & 0x01; + /* Non-integer bus ratio for the current-multi (undocumented)*/ + currdiv = (msr >> 14) & 0x01; + + if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3 + { + /* On these models, maxcoef defines TSC freq */ + maxcoef = (msr >> 40) & 0x1f; + } else { + /* On lower models, currcoef defines TSC freq */ + /* XXX */ + maxcoef = currcoef; + } + + if (maxcoef) { + if (maxdiv) { + fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1)); + } else { + fsbFrequency = (tscFrequency / maxcoef); + } + if (currdiv) { + cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2); + } else { + cpuFrequency = (fsbFrequency * currcoef); + } + DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : ""); + } + } + } + /* Mobile CPU ? */ + if (rdmsr64(0x17) & (1<<28)) { + p->CPU.Features |= CPU_FEATURE_MOBILE; + } + } +#if 0 + else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) { + if(p->CPU.ExtFamily == 0x00 /* K8 */) { + msr = rdmsr64(K8_FIDVID_STATUS); + currcoef = (msr & 0x3f) / 2 + 4; + currdiv = (msr & 0x01) * 2; + } else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) { + msr = rdmsr64(K10_COFVID_STATUS); + if(p->CPU.ExtFamily == 0x01 /* K10 */) + currcoef = (msr & 0x3f) + 0x10; + else /* K11+ */ + currcoef = (msr & 0x3f) + 0x08; + currdiv = (2 << ((msr >> 6) & 0x07)); + } + + if (currcoef) { + if (currdiv) { + fsbFrequency = ((tscFrequency * currdiv) / currcoef); + DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv); + } else { + fsbFrequency = (tscFrequency / currcoef); + DBG("%d\n", currcoef); + } + fsbFrequency = (tscFrequency / currcoef); + cpuFrequency = tscFrequency; + } + } + + if (!fsbFrequency) { + fsbFrequency = (DEFAULT_FSB * 1000); + cpuFrequency = tscFrequency; + DBG("0 ! using the default value for FSB !\n"); + } +#endif + + p->CPU.MaxCoef = maxcoef; + p->CPU.MaxDiv = maxdiv; + p->CPU.CurrCoef = currcoef; + p->CPU.CurrDiv = currdiv; + p->CPU.TSCFrequency = tscFrequency; + p->CPU.FSBFrequency = fsbFrequency; + p->CPU.CPUFrequency = cpuFrequency; + + DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel); + DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily); + DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef); + DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv); + DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000); + DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000); + DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000); + DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads); + DBG("CPU: Features: 0x%08x\n", p->CPU.Features); +#if DEBUG_CPU + pause(); +#endif +} Index: branches/Chimera/i386/libsaio/.svn/text-base/msdos.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/msdos.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/msdos.h.svn-base (revision 850) @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2004 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +extern void MSDOSGetDescription(CICell ih, char *str, long strMaxLen); +extern long MSDOSInitPartition(CICell ih); +extern long MSDOSLoadFile(CICell ih, char * filePath); +extern long MSDOSReadFile(CICell ih, char * filePath, void *base, uint64_t offset, uint64_t length); +extern long MSDOSGetDirEntry(CICell ih, char * dirPath, long long * dirIndex, + char ** name, long * flags, long * time, + FinderInfo * finderInfo, long * infoValid); +extern long MSDOSGetFileBlock(CICell ih, char *str, unsigned long long *firstBlock); +extern long MSDOSGetUUID(CICell ih, char *uuidStr); +extern void MSDOSFree(CICell ih); +extern int MSDOSProbe (const void *buf); Index: branches/Chimera/i386/libsaio/.svn/text-base/pci_setup.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/pci_setup.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/pci_setup.c.svn-base (revision 850) @@ -0,0 +1,75 @@ +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "pci.h" +#include "nvidia.h" + + +extern bool setup_ati_devprop(pci_dt_t *ati_dev); +extern void set_eth_builtin(pci_dt_t *eth_dev); +extern void notify_usb_dev(pci_dt_t *pci_dev); +extern void force_enable_hpet(pci_dt_t *lpc_dev); + +extern pci_dt_t *dram_controller_dev; + +void setup_pci_devs(pci_dt_t *pci_dt) +{ + char *devicepath; + bool do_eth_devprop, do_gfx_devprop, do_enable_hpet; + pci_dt_t *current = pci_dt; + + do_eth_devprop = do_gfx_devprop = do_enable_hpet = false; + + getBoolForKey(kEthernetBuiltIn, &do_eth_devprop, &bootInfo->bootConfig); + getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->bootConfig); + getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->bootConfig); + + while (current) + { + devicepath = get_pci_dev_path(current); + + switch (current->class_id) + { + case PCI_CLASS_BRIDGE_HOST: + dram_controller_dev = current; + break; + + case PCI_CLASS_NETWORK_ETHERNET: + if (do_eth_devprop) + set_eth_builtin(current); + break; + + case PCI_CLASS_DISPLAY_VGA: + if (do_gfx_devprop) + switch (current->vendor_id) + { + case PCI_VENDOR_ID_ATI: + setup_ati_devprop(current); + break; + + case PCI_VENDOR_ID_INTEL: + /* message to be removed once support for these cards is added */ + verbose("Intel VGA Controller [%04x:%04x] :: %s (currently NOT SUPPORTED)\n", + current->vendor_id, current->device_id, devicepath); + break; + + case PCI_VENDOR_ID_NVIDIA: + setup_nvidia_devprop(current); + break; + } + break; + + case PCI_CLASS_SERIAL_USB: + notify_usb_dev(current); + break; + + case PCI_CLASS_BRIDGE_ISA: + if (do_enable_hpet) + force_enable_hpet(current); + break; + } + + setup_pci_devs(current->children); + current = current->next; + } +} Index: branches/Chimera/i386/libsaio/.svn/text-base/ufs.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ufs.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ufs.c.svn-base (revision 850) @@ -0,0 +1,535 @@ +/* + * Copyright (c) 2000-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * ufs.c - File System Module for UFS. + * + * Copyright (c) 1998-2002 Apple Computer, Inc. + * + * DRI: Josh de Cesare + */ + +#include + +#include "ufs.h" +#include "ufs_byteorder.h" + +#if !defined(MAXNAMLEN) && defined(UFSMAXNAMLEN) +#define MAXNAMLEN UFSMAXNAMLEN +#endif + +typedef struct dinode Inode, *InodePtr; + +// Private function prototypes + +static char *ReadBlock(long fragNum, long fragOffset, long length, + char *buffer, long cache); +static long ReadInode(long inodeNum, InodePtr inode, long *flags, long *time); +static long ResolvePathToInode(char *filePath, long *flags, + InodePtr fileInode, InodePtr dirInode); +static long ReadDirEntry(InodePtr dirInode, long *fileInodeNum, + long long *dirIndex, char **name); +static long FindFileInDir(char *fileName, long *flags, + InodePtr fileInode, InodePtr dirInode); +static char *ReadFileBlock(InodePtr fileInode, long fragNum, long blockOffset, + long length, char *buffer, long cache); +static long ReadFile(InodePtr fileInode, uint64_t *length, void *base, uint64_t offset); + +#define kDevBlockSize (0x200) // Size of each disk block. +#define kDiskLabelBlock (15) // Block the DL is in. + +#ifdef __i386__ + +static CICell gCurrentIH; +static long long gPartitionBase; +static char *gULBuf; +static char *gFSBuf; +static struct fs *gFS; +#if !BOOT1 +static struct ufslabel gUFSLabel; // for UUID +#endif +static long gBlockSize; +static long gFragSize; +static long gFragsPerBlock; +static char *gTempBlock; +static char *gTempName; +static char *gTempName2; +static InodePtr gRootInodePtr; +static InodePtr gFileInodePtr; + +#else /* !__i386__ */ + +static CICell gCurrentIH; +static long long gPartitionBase; +static char gDLBuf[8192]; +static char gFSBuf[SBSIZE]; +static struct fs *gFS; +#if !BOOT1 +static struct ufslabel gUFSLabel; // for UUID +#endif +static long gBlockSize; +static long gFragSize; +static long gFragsPerBlock; +static char *gTempBlock; +static char gTempName[MAXNAMLEN + 1]; +static char gTempName2[MAXNAMLEN + 1]; +static Inode _gRootInode; +static Inode _gFileInode; +static InodePtr gRootInodePtr = &_gRootInode; +static InodePtr gFileInodePtr = &_gFileInode; + +#endif /* !__i386__ */ + +// Public functions + +void UFSFree(CICell ih) +{ + if(gCurrentIH == ih) + gCurrentIH = 0; + free(ih); +} + +long UFSInitPartition( CICell ih ) +{ +#if !BOOT1 + long ret; +#endif + + if (ih == gCurrentIH) { +#ifdef __i386__ + CacheInit(ih, gBlockSize); +#endif + return 0; + } + +#if !BOOT1 + verbose("UFSInitPartition: %x\n", ih); +#endif + + gCurrentIH = 0; + +#ifdef __i386__ + if (!gULBuf) gULBuf = (char *) malloc(UFS_LABEL_SIZE); + if (!gFSBuf) gFSBuf = (char *) malloc(SBSIZE); + if (!gTempName) gTempName = (char *) malloc(MAXNAMLEN + 1); + if (!gTempName2) gTempName2 = (char *) malloc(MAXNAMLEN + 1); + if (!gRootInodePtr) gRootInodePtr = (InodePtr) malloc(sizeof(Inode)); + if (!gFileInodePtr) gFileInodePtr = (InodePtr) malloc(sizeof(Inode)); + if (!gULBuf || !gFSBuf || !gTempName || !gTempName2 || + !gRootInodePtr || !gFileInodePtr) return -1; +#endif + + // Assume there is no Disk Label + gPartitionBase = 0; + +#if !BOOT1 + // read the disk label to get the UUID + // (rumor has it that UFS headers can be either-endian on disk; hopefully + // that isn't true for this UUID field). + Seek(ih, gPartitionBase + UFS_LABEL_OFFSET); + ret = Read(ih, (long)&gUFSLabel, UFS_LABEL_SIZE); + if(ret != 0) + bzero(&gUFSLabel, UFS_LABEL_SIZE); +#endif /* !BOOT1 */ + + // Look for the Super Block + Seek(ih, gPartitionBase + SBOFF); + Read(ih, (long)gFSBuf, SBSIZE); + + gFS = (struct fs *)gFSBuf; + byte_swap_superblock(gFS); + + if (gFS->fs_magic != FS_MAGIC) { + return -1; + } + + ih->modTime = gFS->fs_time; + + // Calculate the block size and set up the block cache. + gBlockSize = gFS->fs_bsize; + gFragSize = gFS->fs_fsize; + gFragsPerBlock = gBlockSize / gFragSize; + if (gTempBlock != 0) free(gTempBlock); + gTempBlock = malloc(gBlockSize); + CacheInit(ih, gBlockSize); + + gCurrentIH = ih; + + // Read the Root Inode + ReadInode(ROOTINO, gRootInodePtr, 0, 0); + + return 0; +} + +#if !BOOT1 + +long UFSGetUUID(CICell ih, char *uuidStr) +{ + long long uuid = gUFSLabel.ul_uuid; + + if (UFSInitPartition(ih) == -1) return -1; + if (uuid == 0LL) return -1; + + return CreateUUIDString((uint8_t*)(&uuid), sizeof(uuid), uuidStr); +} + +#endif /* !BOOT1 */ + +long UFSLoadFile( CICell ih, char * filePath ) +{ + return UFSReadFile(ih, filePath, (void *)gFSLoadAddress, 0, 0); +} + +long UFSReadFile( CICell ih, char * filePath, void * base, uint64_t offset, uint64_t length ) +{ + long ret, flags; + +#if !BOOT1 + verbose("Loading UFS file: [%s] from %x.\n", filePath, (unsigned)ih); +#endif + + if (UFSInitPartition(ih) == -1) return -1; + + // Skip one or two leading '/'. + if (*filePath == '/') filePath++; + if (*filePath == '/') filePath++; + + ret = ResolvePathToInode(filePath, &flags, gFileInodePtr, gRootInodePtr); + if ((ret == -1) || ((flags & kFileTypeMask) != kFileTypeFlat)) return -1; + + ret = ReadFile(gFileInodePtr, &length, base, offset); + if (ret == -1) return -1; + + return length; +} + +#ifndef BOOT1 + +long UFSGetDirEntry( CICell ih, char * dirPath, long long * dirIndex, + char ** name, long * flags, long * time, + FinderInfo * finderInfo, long * infoValid) +{ + long ret, fileInodeNum, dirFlags; + Inode tmpInode; + + if (UFSInitPartition(ih) == -1) return -1; + + if (infoValid) *infoValid = 0; + + // Skip a leading '/' if present + if (*dirPath == '/') dirPath++; + if (*dirPath == '/') dirPath++; + + ret = ResolvePathToInode(dirPath, &dirFlags, gFileInodePtr, gRootInodePtr); + if ((ret == -1) || ((dirFlags & kFileTypeMask) != kFileTypeDirectory)) + return -1; + + ret = ReadDirEntry(gFileInodePtr, &fileInodeNum, dirIndex, name); + if (ret != 0) return ret; + + ReadInode(fileInodeNum, &tmpInode, flags, time); + + return 0; +} + +void +UFSGetDescription(CICell ih, char *str, long strMaxLen) +{ + if (UFSInitPartition(ih) == -1) { return; } + + struct ufslabel *ul; + + // Look for the Disk Label + Seek(ih, 1ULL * UFS_LABEL_OFFSET); + Read(ih, (long)gULBuf, UFS_LABEL_SIZE); + + ul = (struct ufslabel *)gULBuf; + + unsigned char magic_bytes[] = UFS_LABEL_MAGIC; + int i; + unsigned char *p = (unsigned char *)&ul->ul_magic; + + for (i=0; iul_name, strMaxLen); +} + +long +UFSGetFileBlock(CICell ih, char *filePath, unsigned long long *firstBlock) +{ + long ret, flags; + + if (UFSInitPartition(ih) == -1) return -1; + + // Skip one or two leading '/'. + if (*filePath == '/') filePath++; + if (*filePath == '/') filePath++; + + ret = ResolvePathToInode(filePath, &flags, gFileInodePtr, gRootInodePtr); + if ((ret == -1) || ((flags & kFileTypeMask) != kFileTypeFlat)) return -1; + + *firstBlock = (gPartitionBase + 1ULL * gFileInodePtr->di_db[0] * gBlockSize) / 512ULL; + + return 0; +} + + +#endif /* !BOOT1 */ + +// Private functions + +static char * ReadBlock( long fragNum, long blockOffset, long length, + char * buffer, long cache ) +{ + long long offset; + long blockNum; + + blockNum = fragNum / gFragsPerBlock; + fragNum -= blockNum * gFragsPerBlock; + + blockOffset += fragNum * gFragSize; + + offset = gPartitionBase + 1ULL * blockNum * gBlockSize; + + if (cache && ((blockOffset + length) <= gBlockSize)) { + CacheRead(gCurrentIH, gTempBlock, offset, gBlockSize, 1); + if (buffer != 0) bcopy(gTempBlock + blockOffset, buffer, length); + else buffer = gTempBlock + blockOffset; + } else { + offset += blockOffset; + CacheRead(gCurrentIH, buffer, offset, length, 0); + } + + return buffer; +} + +static long ReadInode( long inodeNum, InodePtr inode, long * flags, long * time ) +{ + long fragNum = ino_to_fsba(gFS, inodeNum); + long blockOffset = ino_to_fsbo(gFS, inodeNum) * sizeof(Inode); + + ReadBlock(fragNum, blockOffset, sizeof(Inode), (char *)inode, 1); + byte_swap_dinode_in(inode); + + if (time != 0) *time = inode->di_mtime; + + if (flags != 0) { + switch (inode->di_mode & IFMT) { + case IFREG: *flags = kFileTypeFlat; break; + case IFDIR: *flags = kFileTypeDirectory; break; + case IFLNK: *flags = kFileTypeLink; break; + default : *flags = kFileTypeUnknown; break; + } + + *flags |= inode->di_mode & kPermMask; + + if (inode->di_uid != 0) *flags |= kOwnerNotRoot; + } + + return 0; +} + +static long ResolvePathToInode( char * filePath, long * flags, + InodePtr fileInode, InodePtr dirInode ) +{ + char * restPath; + long ret, cnt; + + // if filePath is empty the we want this directory. + if (*filePath == '\0') { + bcopy((char *)dirInode, (char *)fileInode, sizeof(Inode)); + return 0; + } + + // Copy the file name to gTempName + cnt = 0; + while ((filePath[cnt] != '/') && (filePath[cnt] != '\0')) cnt++; + strlcpy(gTempName, filePath, cnt+1); + + // Move restPath to the right place. + if (filePath[cnt] != '\0') cnt++; + restPath = filePath + cnt; + + // gTempName is a name in the current Dir. + // restPath is the rest of the path if any. + + ret = FindFileInDir(gTempName, flags, fileInode, dirInode); + if (ret == -1) return -1; + + if ((*restPath != '\0') && ((*flags & kFileTypeMask) == kFileTypeDirectory)) + ret = ResolvePathToInode(restPath, flags, fileInode, fileInode); + + return ret; +} + +static long ReadDirEntry( InodePtr dirInode, long * fileInodeNum, + long long * dirIndex, char ** name ) +{ + struct direct *dir; + char *buffer; + long long index; + long dirBlockNum, dirBlockOffset; + + while (1) { + index = *dirIndex; + + dirBlockOffset = (long) (index % DIRBLKSIZ); + dirBlockNum = (long) (index / DIRBLKSIZ); + + buffer = ReadFileBlock(dirInode, dirBlockNum, 0, DIRBLKSIZ, 0, 1); + if (buffer == 0) return -1; + + dir = (struct direct *)(buffer + dirBlockOffset); + byte_swap_dir_block_in((char *)dir, 1); + + *dirIndex += dir->d_reclen; + + if (dir->d_ino != 0) break; + + if (dirBlockOffset != 0) return -1; + } + + *fileInodeNum = dir->d_ino; + *name = strlcpy(gTempName2, dir->d_name, dir->d_namlen+1); + + return 0; +} + +static long FindFileInDir( char * fileName, long * flags, + InodePtr fileInode, InodePtr dirInode ) +{ + long ret, inodeNum; + long long index = 0; + char *name; + + while (1) { + ret = ReadDirEntry(dirInode, &inodeNum, &index, &name); + if (ret == -1) return -1; + + if (strcmp(fileName, name) == 0) break; + } + + ReadInode(inodeNum, fileInode, flags, 0); + + return 0; +} + +static char * ReadFileBlock( InodePtr fileInode, long fragNum, long blockOffset, + long length, char * buffer, long cache ) +{ + long fragCount, blockNum; + long diskFragNum, indFragNum, indBlockOff, refsPerBlock; + char *indBlock; + + fragCount = (fileInode->di_size + gFragSize - 1) / gFragSize; + if (fragNum >= fragCount) return 0; + + refsPerBlock = gBlockSize / sizeof(ufs_daddr_t); + + blockNum = fragNum / gFragsPerBlock; + fragNum -= blockNum * gFragsPerBlock; + + // Get Direct Block Number. + if (blockNum < NDADDR) { + diskFragNum = fileInode->di_db[blockNum]; + } else { + blockNum -= NDADDR; + + // Get Single Indirect Fragment Number. + if (blockNum < refsPerBlock) { + indFragNum = fileInode->di_ib[0]; + } else { + blockNum -= refsPerBlock; + + // Get Double Indirect Fragment Number. + if (blockNum < (refsPerBlock * refsPerBlock)) { + indFragNum = fileInode->di_ib[1]; + } else { + blockNum -= refsPerBlock * refsPerBlock; + + // Get Triple Indirect Fragment Number. + indFragNum = fileInode->di_ib[2]; + + indBlock = ReadBlock(indFragNum, 0, gBlockSize, 0, 1); + indBlockOff = blockNum / (refsPerBlock * refsPerBlock); + blockNum %= (refsPerBlock * refsPerBlock); + indFragNum = SWAP_BE32(((ufs_daddr_t *)indBlock)[indBlockOff]); + } + + indBlock = ReadBlock(indFragNum, 0, gBlockSize, 0, 1); + indBlockOff = blockNum / refsPerBlock; + blockNum %= refsPerBlock; + indFragNum = SWAP_BE32(((ufs_daddr_t *)indBlock)[indBlockOff]); + } + + indBlock = ReadBlock(indFragNum, 0, gBlockSize, 0, 1); + diskFragNum = SWAP_BE32(((ufs_daddr_t *)indBlock)[blockNum]); + } + + buffer = ReadBlock(diskFragNum+fragNum, blockOffset, length, buffer, cache); + + return buffer; +} + +static long ReadFile( InodePtr fileInode, uint64_t * length, void * base, uint64_t offset ) +{ + long bytesLeft, curSize, curFrag; + char *buffer, *curAddr = (char *)base; + + bytesLeft = fileInode->di_size; + + if (offset > bytesLeft) { + printf("Offset is too large.\n"); + return -1; + } + + if ((*length == 0) || ((offset + *length) > bytesLeft)) { + *length = bytesLeft - offset; + } +/* + if (bytesLeft > kLoadSize) { + printf("File is too large.\n"); + return -1; + } +*/ + bytesLeft = *length; + curFrag = (offset / gBlockSize) * gFragsPerBlock; + offset %= gBlockSize; + + while (bytesLeft) { + curSize = gBlockSize; + if (curSize > bytesLeft) curSize = bytesLeft; + if ((offset + curSize) > gBlockSize) curSize = (gBlockSize - offset); + + buffer = ReadFileBlock(fileInode, curFrag, offset, curSize, curAddr, 0); + if (buffer == 0) break; + + if (offset != 0) offset = 0; + + curFrag += gFragsPerBlock; + curAddr += curSize; + bytesLeft -= curSize; + } + + return bytesLeft; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/smbios_getters.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/smbios_getters.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/smbios_getters.h.svn-base (revision 850) @@ -0,0 +1,43 @@ + +#include "libsaio.h" +#include "smbios.h" +#include "platform.h" +#include "pci.h" + +#ifndef __LIBSAIO_SMBIOS_GETTERS_H +#define __LIBSAIO_SMBIOS_GETTERS_H + +#define SMBIOS_RANGE_START 0x000F0000 +#define SMBIOS_RANGE_END 0x000FFFFF + +#define NOT_AVAILABLE "N/A" + +typedef enum { + kSMBString, + kSMBByte, + kSMBWord, + kSMBDWord +// kSMBQWord +} SMBValueType; + +typedef union { + const char *string; + uint8_t byte; + uint16_t word; + uint32_t dword; +// uint64_t qword; +} returnType; + +extern bool getProcessorInformationExternalClock(returnType *value); +extern bool getProcessorInformationMaximumClock(returnType *value); +extern bool getSMBOemProcessorBusSpeed(returnType *value); +extern bool getSMBOemProcessorType(returnType *value); +extern bool getSMBMemoryDeviceMemoryType(returnType *value); +extern bool getSMBMemoryDeviceMemorySpeed(returnType *value); +extern bool getSMBMemoryDeviceManufacturer(returnType *value); +extern bool getSMBMemoryDeviceSerialNumber(returnType *value); +extern bool getSMBMemoryDevicePartNumber(returnType *value); + +SMBEntryPoint *getAddressOfSmbiosTable(void); + +#endif /* !__LIBSAIO_SMBIOS_GETTERS_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/fake_efi.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/fake_efi.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/fake_efi.h.svn-base (revision 850) @@ -0,0 +1,13 @@ +/* + * Copyright 2007 David F. Elliott. All rights reserved. + */ + +#ifndef __LIBSAIO_FAKE_EFI_H +#define __LIBSAIO_FAKE_EFI_H + +/* Set up space for up to 10 configuration table entries */ +#define MAX_CONFIGURATION_TABLE_ENTRIES 10 + +extern void setupFakeEfi(void); + +#endif /* !__LIBSAIO_FAKE_EFI_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/smbios_decode.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/smbios_decode.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/smbios_decode.c.svn-base (revision 850) @@ -0,0 +1,232 @@ +/* + * A very simple SMBIOS Table decoder, part of the Chameleon Boot Loader Project + * + * Copyright 2010 by Islam M. Ahmed Zaid. All rights reserved. + * + */ + +#include "libsaio.h" +#include "smbios.h" + +#ifndef DEBUG_SMBIOS +#define DEBUG_SMBIOS 0 +#endif + +#if DEBUG_SMBIOS +#define DBG(x...) printf(x) +#else +#define DBG(x...) msglog(x) +#endif + + +static SMBWord minorVersion; + +extern char *getSMBStringForField(SMBStructHeader *structHeader, uint8_t field); + +//------------------------------------------------------------------------------------------------------------------------- +// BIOSInformation +//------------------------------------------------------------------------------------------------------------------------- +void decodeBIOSInformation(SMBBIOSInformation *structHeader) +{ + DBG("BIOSInformation:\n"); + DBG("\tvendor: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->vendor)); + DBG("\tversion: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->version)); + DBG("\treleaseDate: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->releaseDate)); + DBG("\n"); +} + +//------------------------------------------------------------------------------------------------------------------------- +// SystemInformation +//------------------------------------------------------------------------------------------------------------------------- +void decodeSystemInformation(SMBSystemInformation *structHeader) +{ + DBG("SystemInformation:\n"); + DBG("\tmanufacturer: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->manufacturer)); + DBG("\tproductName: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->productName)); + DBG("\tversion: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->version)); + DBG("\tserialNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber)); + + if (minorVersion < 1 || structHeader->header.length < 25) + return; + uint8_t *uuid = structHeader->uuid; + DBG("\tuuid: %02X%02X%02X%02X-%02X%02X-%02X%02X-%02x%02X-%02X%02X%02X%02X%02X%02X\n", + uuid[0], uuid[1], uuid[2], uuid[3], + uuid[4], uuid[5], + uuid[6], uuid[7], + uuid[8], uuid[9], + uuid[10], uuid[11], uuid[12], uuid[13], uuid[14], uuid[15]); + DBG("\twakeupReason: 0x%x\n", structHeader->wakeupReason); + + if (minorVersion < 4 || structHeader->header.length < 27) + return; + DBG("\tskuNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->skuNumber)); + DBG("\tfamily: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->family)); + DBG("\n"); +} + +//------------------------------------------------------------------------------------------------------------------------- +// BaseBoard +//------------------------------------------------------------------------------------------------------------------------- +void decodeBaseBoard(SMBBaseBoard *structHeader) +{ + DBG("BaseBoard:\n"); + DBG("\tmanufacturer: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->manufacturer)); + DBG("\tproduct: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->product)); + DBG("\tversion: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->version)); + DBG("\tserialNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber)); + DBG("\tassetTagNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->assetTagNumber)); + DBG("\tlocationInChassis: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->locationInChassis)); + DBG("\tboardType: 0x%X\n", structHeader->boardType); + DBG("\n"); +} + +//------------------------------------------------------------------------------------------------------------------------- +// SystemEnclosure +//------------------------------------------------------------------------------------------------------------------------- +void decodeSystemEnclosure(SMBSystemEnclosure *structHeader) +{ + DBG("SystemEnclosure:\n"); + DBG("\tmanufacturer: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->manufacturer)); + DBG("\ttype: %d\n", structHeader->type); + DBG("\tversion: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->version)); + DBG("\tserialNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber)); + DBG("\tassetTagNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->assetTagNumber)); + DBG("\n"); +} + +//------------------------------------------------------------------------------------------------------------------------- +// ProcessorInformation +//------------------------------------------------------------------------------------------------------------------------- +void decodeProcessorInformation(SMBProcessorInformation *structHeader) +{ + DBG("ProcessorInformation:\n"); + DBG("\tsocketDesignation: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->socketDesignation)); + DBG("\tprocessorType: %d\n", structHeader->processorType); + DBG("\tprocessorFamily: 0x%X\n", structHeader->processorFamily); + DBG("\tmanufacturer: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->manufacturer)); + DBG("\tprocessorID: 0x%llX\n", structHeader->processorID); + DBG("\tprocessorVersion: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->processorVersion)); + DBG("\texternalClock: %dMHz\n", structHeader->externalClock); + DBG("\tmaximumClock: %dMHz\n", structHeader->maximumClock); + DBG("\tcurrentClock: %dMHz\n", structHeader->currentClock); + + if (minorVersion < 3 || structHeader->header.length < 35) + return; + DBG("\tserialNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber)); + DBG("\tassetTag: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->assetTag)); + DBG("\tpartNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->partNumber)); + DBG("\n"); +} + +//------------------------------------------------------------------------------------------------------------------------- +// MemoryDevice +//------------------------------------------------------------------------------------------------------------------------- +void decodeMemoryDevice(SMBMemoryDevice *structHeader) +{ + DBG("MemoryDevice:\n"); + DBG("\tdeviceLocator: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->deviceLocator)); + DBG("\tbankLocator: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->bankLocator)); + DBG("\tmemoryType: %s\n", SMBMemoryDeviceTypes[structHeader->memoryType]); + + if (minorVersion < 3 || structHeader->header.length < 27) + return; + DBG("\tmemorySpeed: %dMHz\n", structHeader->memorySpeed); + DBG("\tmanufacturer: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->manufacturer)); + DBG("\tserialNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber)); + DBG("\tassetTag: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->assetTag)); + DBG("\tpartNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->partNumber)); + DBG("\n"); +} + +//------------------------------------------------------------------------------------------------------------------------- +// Apple Specific +//------------------------------------------------------------------------------------------------------------------------- +void decodeOemProcessorType(SMBOemProcessorType *structHeader) +{ + DBG("AppleProcessorType:\n"); + DBG("\tProcessorType: 0x%x\n", ((SMBOemProcessorType *)structHeader)->ProcessorType); + DBG("\n"); +} + +void decodeOemProcessorBusSpeed(SMBOemProcessorBusSpeed *structHeader) +{ + DBG("AppleProcessorBusSpeed:\n"); + DBG("\tProcessorBusSpeed (QPI): %d.%dGT/s\n", + ((SMBOemProcessorBusSpeed *)structHeader)->ProcessorBusSpeed / 1000, + (((SMBOemProcessorBusSpeed *)structHeader)->ProcessorBusSpeed / 100) % 10); + DBG("\n"); +} +//------------------------------------------------------------------------------------------------------------------------- + + +void decodeSMBIOSTable(SMBEntryPoint *eps) +{ + uint8_t *ptr = (uint8_t *)eps->dmi.tableAddress; + SMBStructHeader *structHeader = (SMBStructHeader *)ptr; + + minorVersion = eps->minorVersion; + + DBG("\n"); + for (;((eps->dmi.tableAddress + eps->dmi.tableLength) > ((uint32_t)(uint8_t *)structHeader + sizeof(SMBStructHeader)));) + { + DBG("Type: %d, Length: %d, Handle: 0x%x\n", + structHeader->type, structHeader->length, structHeader->handle); + + switch (structHeader->type) + { + case kSMBTypeBIOSInformation: + decodeBIOSInformation((SMBBIOSInformation *)structHeader); + break; + + case kSMBTypeSystemInformation: + decodeSystemInformation((SMBSystemInformation *)structHeader); + break; + + case kSMBTypeBaseBoard: + decodeBaseBoard((SMBBaseBoard *)structHeader); + break; + + case kSMBTypeSystemEnclosure: + decodeSystemEnclosure((SMBSystemEnclosure *)structHeader); + break; + + case kSMBTypeProcessorInformation: + decodeProcessorInformation((SMBProcessorInformation *)structHeader); + break; + + case kSMBTypeMemoryDevice: + decodeMemoryDevice((SMBMemoryDevice *)structHeader); + break; + + /* Skip all Apple Specific Structures */ + case kSMBTypeFirmwareVolume: + case kSMBTypeMemorySPD: + break; + + case kSMBTypeOemProcessorType: + decodeOemProcessorType((SMBOemProcessorType *)structHeader); + break; + + case kSMBTypeOemProcessorBusSpeed: + decodeOemProcessorBusSpeed((SMBOemProcessorBusSpeed *)structHeader); + break; + + case kSMBTypeEndOfTable: + /* Skip, to be added at the end */ + break; + + default: + break; + } + + ptr = (uint8_t *)((uint32_t)structHeader + structHeader->length); + for (; ((uint16_t *)ptr)[0] != 0; ptr++); + + if (((uint16_t *)ptr)[0] == 0) + ptr += 2; + + structHeader = (SMBStructHeader *)ptr; + } + DBG("\n"); +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/disk.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/disk.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/disk.h.svn-base (revision 850) @@ -0,0 +1,14 @@ +/* + * disk.h + * Chameleon + * + * Created by Daniel Miranda on 27/07/10. + * Copyright 2010 __MyCompanyName__. All rights reserved. + * + */ +#ifndef __LIBSAIO_DISK_H +#define __LIBSAIO_DISK_H + +bool matchVolumeToString( BVRef bvr, const char* match, long strMaxLen); + +#endif /* __LIBSAIO_DISK_H */ \ No newline at end of file Index: branches/Chimera/i386/libsaio/.svn/text-base/device_inject.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/device_inject.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/device_inject.h.svn-base (revision 850) @@ -0,0 +1,74 @@ +/* + * Copyright 2009 Jasmin Fazlic All rights reserved. + */ +/* + * Cleaned and merged by iNDi + */ + +#ifndef __LIBSAIO_DEVICE_INJECT_H +#define __LIBSAIO_DEVICE_INJECT_H + +#define DP_ADD_TEMP_VAL(dev, val) devprop_add_value(dev, (char*)val[0], (uint8_t*)val[1], strlen(val[1]) + 1) +#define DP_ADD_TEMP_VAL_DATA(dev, val) devprop_add_value(dev, (char*)val.name, (uint8_t*)val.data, val.size) +#define MAX_PCI_DEV_PATHS 4 + +extern struct DevPropString *string; +extern uint8_t *stringdata; +extern uint32_t stringlength; + +extern void setupDeviceProperties(Node *node); + +struct ACPIDevPath { + uint8_t type; // = 2 ACPI device-path + uint8_t subtype; // = 1 ACPI Device-path + uint16_t length; // = 0x0c + uint32_t _HID; // = 0xD041030A ? + uint32_t _UID; // = 0x00000000 PCI ROOT +}; + +struct PCIDevPath { + uint8_t type; // = 1 Hardware device-path + uint8_t subtype; // = 1 PCI + uint16_t length; // = 6 + uint8_t function; // pci func number + uint8_t device; // pci dev number +}; + +struct DevicePathEnd { + uint8_t type; // = 0x7f + uint8_t subtype; // = 0xff + uint16_t length; // = 4; +}; + +struct DevPropDevice { + uint32_t length; + uint16_t numentries; + uint16_t WHAT2; // 0x0000 ? + struct ACPIDevPath acpi_dev_path; // = 0x02010c00 0xd041030a + struct PCIDevPath pci_dev_path[MAX_PCI_DEV_PATHS]; // = 0x01010600 func dev + struct DevicePathEnd path_end; // = 0x7fff0400 + uint8_t *data; + + // ------------------------ + uint8_t num_pci_devpaths; + struct DevPropString *string; + // ------------------------ +}; + +struct DevPropString { + uint32_t length; + uint32_t WHAT2; // 0x01000000 ? + uint16_t numentries; + uint16_t WHAT3; // 0x0000 ? + struct DevPropDevice **entries; +}; + +char *efi_inject_get_devprop_string(uint32_t *len); +int devprop_add_network_template(struct DevPropDevice *device, uint16_t vendor_id); +struct DevPropString *devprop_create_string(void); +struct DevPropDevice *devprop_add_device(struct DevPropString *string, char *path); +int devprop_add_value(struct DevPropDevice *device, char *nm, uint8_t *vl, uint32_t len); +char *devprop_generate_string(struct DevPropString *string); +void devprop_free_string(struct DevPropString *string); + +#endif /* !__LIBSAIO_DEVICE_INJECT_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/bios.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/bios.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/bios.h.svn-base (revision 850) @@ -0,0 +1,105 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright 1994 NeXT Computer, Inc. + * All rights reserved. + */ + +#ifndef __LIBSAIO_BIOS_H +#define __LIBSAIO_BIOS_H + +#include "bootargs.h" + +typedef union { + unsigned int rx; + unsigned short rr; + struct { + unsigned char l; + unsigned char h; + } r; +} machineRegister_t; + +typedef struct { + unsigned short cf :1; + unsigned short :1; + unsigned short pf :1; + unsigned short :1; + unsigned short af :1; + unsigned short :1; + unsigned short zf :1; + unsigned short sf :1; + unsigned short tf :1; + unsigned short _if :1; + unsigned short df :1; + unsigned short of :1; + unsigned short iopl:2; + unsigned short nt :1; +} machineFlags_t; + +typedef struct { + unsigned int intno; + machineRegister_t eax; + machineRegister_t ebx; + machineRegister_t ecx; + machineRegister_t edx; + machineRegister_t edi; + machineRegister_t esi; + machineRegister_t ebp; + unsigned short cs; + unsigned short ds; + unsigned short es; + machineFlags_t flags; +} biosBuf_t; + +#define EBIOS_FIXED_DISK_ACCESS 0x01 +#define EBIOS_LOCKING_ACCESS 0x02 +#define EBIOS_ENHANCED_DRIVE_INFO 0x04 + +#define BASE_HD_DRIVE 0x80 + +#if 0 +/* + * ACPI defined memory range types. + */ +enum { + kMemoryRangeUsable = 1, // RAM usable by the OS. + kMemoryRangeReserved = 2, // Reserved. (Do not use) + kMemoryRangeACPI = 3, // ACPI tables. Can be reclaimed. + kMemoryRangeNVS = 4, // ACPI NVS memory. (Do not use) + + /* Undefined types should be treated as kMemoryRangeReserved */ +}; +#endif + +/* + * Memory range descriptor. + */ +typedef struct MemoryRange { + unsigned long long base; // 64-bit base address + unsigned long long length; // 64-bit length in bytes + unsigned long type; // type of memory range + unsigned long reserved; +} MemoryRange; + +#endif /* !__LIBSAIO_BIOS_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/console.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/console.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/console.c.svn-base (revision 850) @@ -0,0 +1,261 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Mach Operating System + * Copyright (c) 1990 Carnegie-Mellon University + * Copyright (c) 1989 Carnegie-Mellon University + * All rights reserved. The CMU software License Agreement specifies + * the terms and conditions for use and redistribution. + */ + +/* + * INTEL CORPORATION PROPRIETARY INFORMATION + * + * This software is supplied under the terms of a license agreement or + * nondisclosure agreement with Intel Corporation and may not be copied + * nor disclosed except in accordance with the terms of that agreement. + * + * Copyright 1988, 1989 Intel Corporation + */ + +/* + * Copyright 1993 NeXT, Inc. + * All rights reserved. + */ + +#include "libsaio.h" +#include "bootstruct.h" + +extern int vprf(const char * fmt, va_list ap); + +bool gVerboseMode; +bool gErrors; + +/* Kabyl: BooterLog */ +//Azi: Doubled log available size. +// 64kb are not enough to hold the full log while booting with -f argument (ignore caches). +// It also seems to fix some reported problems while booting with the mentioned argument. +// Note: 96kb are enough to hold full log, booting with -f; even so, this depends on how much +// we "play" at the boot prompt, with what patches we're playing and how much they print to the log, +// kexts loaded, etc... +// Please remove this comment when this gets checked by a "true" dev. +#define BOOTER_LOG_SIZE (128 * 1024) +#define SAFE_LOG_SIZE 134 + +char *msgbuf = 0; +char *cursor = 0; + +struct putc_info { + char * str; + char * last_str; +}; + +static void sputc(int c, struct putc_info * pi) +{ + if (pi->last_str) + if (pi->str == pi->last_str) + { + *(pi->str) = '\0'; + return; + } + *(pi->str)++ = c; +} + +void initBooterLog(void) +{ + msgbuf = malloc(BOOTER_LOG_SIZE); + bzero(msgbuf, BOOTER_LOG_SIZE); + cursor = msgbuf; +} + +void msglog(const char * fmt, ...) +{ + va_list ap; + struct putc_info pi; + + if (!msgbuf) + return; + + if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE))) + return; + + va_start(ap, fmt); + pi.str = cursor; + pi.last_str = 0; + prf(fmt, ap, sputc, &pi); + va_end(ap); + cursor += strlen((char *)cursor); +} + +void setupBooterLog(void) +{ + if (!msgbuf) + return; + + Node *node = DT__FindNode("/", false); + if (node) + DT__AddProperty(node, "boot-log", strlen((char *)msgbuf) + 1, msgbuf); +} +/* Kabyl: !BooterLog */ + + +/* + * write one character to console + */ +void putchar(int c) +{ + if ( c == '\t' ) + { + for (c = 0; c < 8; c++) putc(' '); + return; + } + + if ( c == '\n' ) + { + putc('\r'); + } + + putc(c); +} + +int getc() +{ + int c = bgetc(); + + if ((c & 0xff) == 0) + return c; + else + return (c & 0xff); +} + +// Read and echo a character from console. This doesn't echo backspace +// since that screws up higher level handling + +int getchar() +{ + register int c = getc(); + + if ( c == '\r' ) c = '\n'; + + if ( c >= ' ' && c < 0x7f) putchar(c); + + return (c); +} + +int printf(const char * fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + if (bootArgs->Video.v_display == VGA_TEXT_MODE) + prf(fmt, ap, putchar, 0); + else + vprf(fmt, ap); + + { + /* Kabyl: BooterLog */ + struct putc_info pi; + + if (!msgbuf) + return 0; + + if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE))) + return 0; + pi.str = cursor; + pi.last_str = 0; + prf(fmt, ap, sputc, &pi); + cursor += strlen((char *)cursor); + } + + va_end(ap); + return 0; +} + +int verbose(const char * fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + if (gVerboseMode) + { + if (bootArgs->Video.v_display == VGA_TEXT_MODE) + prf(fmt, ap, putchar, 0); + else + vprf(fmt, ap); + } + + { + /* Kabyl: BooterLog */ + struct putc_info pi; + + if (!msgbuf) + return 0; + + if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE))) + return 0; + pi.str = cursor; + pi.last_str = 0; + prf(fmt, ap, sputc, &pi); + cursor += strlen((char *)cursor); + } + + va_end(ap); + return(0); +} + +int error(const char * fmt, ...) +{ + va_list ap; + gErrors = true; + va_start(ap, fmt); + if (bootArgs->Video.v_display == VGA_TEXT_MODE) + prf(fmt, ap, putchar, 0); + else + vprf(fmt, ap); + va_end(ap); + return(0); +} + +void stop(const char * fmt, ...) +{ + va_list ap; + + printf("\n"); + va_start(ap, fmt); + if (bootArgs->Video.v_display == VGA_TEXT_MODE) { + prf(fmt, ap, putchar, 0); + } else { + vprf(fmt, ap); + } + va_end(ap); + printf("\nThis is a non recoverable error! System HALTED!!!"); + halt(); + while (1); +} + +/** Print a "Press a key to continue..." message and wait for a key press. */ +void pause() +{ + printf("Press a key to continue..."); + getc(); +} Index: branches/Chimera/i386/libsaio/.svn/text-base/cache.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/cache.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/cache.c.svn-base (revision 850) @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2000-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * cache.c - A simple cache for file systems meta-data. + * + * Copyright (c) 2000 Apple Computer, Inc. + * + * DRI: Josh de Cesare + */ + +#include +// #include + +struct CacheEntry { + CICell ih; + long time; + long long offset; +}; +typedef struct CacheEntry CacheEntry; + +#define kCacheSize (0x100000) +#define kCacheMinBlockSize (0x200) +#define kCacheMaxBlockSize (0x8000) +#define kCacheMaxEntries (kCacheSize / kCacheMinBlockSize) + +static CICell gCacheIH; +static long gCacheBlockSize; +static long gCacheNumEntries; +static long gCacheTime; + +#ifdef __i386__ +static CacheEntry *gCacheEntries; +static char *gCacheBuffer; +#else +static CacheEntry gCacheEntries[kCacheMaxEntries]; +static char gCacheBuffer[kCacheSize]; +#endif + +#if CACHE_STATS +unsigned long gCacheHits; +unsigned long gCacheMisses; +unsigned long gCacheEvicts; +#endif + +void CacheReset() +{ + gCacheIH = NULL; +} + +void CacheInit( CICell ih, long blockSize ) +{ +#ifdef __i386__ + if ((ih == gCacheIH) && (blockSize == gCacheBlockSize)) + return; +#endif + + if ((blockSize < kCacheMinBlockSize) || + (blockSize > kCacheMaxBlockSize)) + return; + + gCacheBlockSize = blockSize; + gCacheNumEntries = kCacheSize / gCacheBlockSize; + gCacheTime = 0; + +#if CACHE_STATS + gCacheHits = 0; + gCacheMisses = 0; + gCacheEvicts = 0; +#endif + + gCacheIH = ih; + +#ifdef __i386__ + if (!gCacheBuffer) gCacheBuffer = (char *) malloc(kCacheSize); + if (!gCacheEntries) gCacheEntries = (CacheEntry *) malloc(kCacheMaxEntries * sizeof(CacheEntry)); + if ( !gCacheBuffer || !gCacheEntries ) + { + gCacheIH = 0; // invalidate cache + return; + } +#endif + + bzero(gCacheEntries, kCacheMaxEntries * sizeof(CacheEntry)); +} + +long CacheRead( CICell ih, char * buffer, long long offset, + long length, long cache ) +{ + long cnt, oldestEntry = 0, oldestTime, loadCache = 0; + CacheEntry *entry; + + // See if the data can be cached. + if (cache && (gCacheIH == ih) && (length == gCacheBlockSize)) { + // Look for the data in the cache. + for (cnt = 0; cnt < gCacheNumEntries; cnt++) { + entry = &gCacheEntries[cnt]; + if ((entry->ih == ih) && (entry->offset == offset)) { + entry->time = ++gCacheTime; + break; + } + } + + // If the data was found copy it to the caller. + if (cnt != gCacheNumEntries) { + bcopy(gCacheBuffer + cnt * gCacheBlockSize, buffer, gCacheBlockSize); +#if CACHE_STATS + gCacheHits++; +#endif + return gCacheBlockSize; + } + + // Could not find the data in the cache. + loadCache = 1; + } + + // Read the data from the disk. + Seek(ih, offset); + Read(ih, (long)buffer, length); +#if CACHE_STATS + if (cache) gCacheMisses++; +#endif + + // Put the data from the disk in the cache if needed. + if (loadCache) { + // Find a free entry. + oldestTime = gCacheTime; + for (cnt = 0; cnt < gCacheNumEntries; cnt++) { + entry = &gCacheEntries[cnt]; + + // Found a free entry. + if (entry->ih == 0) break; + + if (entry->time < oldestTime) { + oldestTime = entry->time; + oldestEntry = cnt; + } + } + + // If no free entry was found, use the oldest. + if (cnt == gCacheNumEntries) { + cnt = oldestEntry; +#if CACHE_STATS + gCacheEvicts++; +#endif + } + + // Copy the data from disk to the new entry. + entry = &gCacheEntries[cnt]; + entry->ih = ih; + entry->time = ++gCacheTime; + entry->offset = offset; + bcopy(buffer, gCacheBuffer + cnt * gCacheBlockSize, gCacheBlockSize); + } + + return length; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/io_inline.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/io_inline.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/io_inline.h.svn-base (revision 850) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright (c) 1992 NeXT Computer, Inc. + * + * Inlines for io space access. + * + * HISTORY + * + * 20 May 1992 ? at NeXT + * Created. + */ + +#ifndef __LIBSAIO_IO_INLINE_H +#define __LIBSAIO_IO_INLINE_H + +/* + *############################################################################ + * + * x86 IN/OUT I/O inline functions. + * + * IN : inb, inw, inl + * IN(port) + * + * OUT: outb, outw, outl + * OUT(port, data) + * + *############################################################################ + */ + +#define __IN(s, u) \ +static inline unsigned u \ +in##s(unsigned short port) \ +{ \ + unsigned u data; \ + asm volatile ( \ + "in" #s " %1,%0" \ + : "=a" (data) \ + : "d" (port)); \ + return (data); \ +} + +#define __OUT(s, u) \ +static inline void \ +out##s(unsigned short port, unsigned u data) \ +{ \ + asm volatile ( \ + "out" #s " %1,%0" \ + : \ + : "d" (port), "a" (data)); \ +} + +__IN(b, char) /* inb() */ +__IN(w, short) /* inw() */ +__IN(l, long) /* inl() */ + +__OUT(b, char) /* outb() */ +__OUT(w, short) /* outw() */ +__OUT(l, long) /* outl() */ + +#endif /* !__LIBSAIO_IO_INLINE_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/pci.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/pci.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/pci.c.svn-base (revision 850) @@ -0,0 +1,189 @@ +/* + * + * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved. + * + */ + +#include "libsaio.h" +#include "bootstruct.h" +#include "pci.h" +#include "pci_root.h" + +#ifndef DEBUG_PCI +#define DEBUG_PCI 0 +#endif + +#if DEBUG_PCI +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +pci_dt_t *root_pci_dev; + + +uint8_t pci_config_read8(uint32_t pci_addr, uint8_t reg) +{ + pci_addr |= reg & ~3; + outl(PCI_ADDR_REG, pci_addr); + return inb(PCI_DATA_REG + (reg & 3)); +} + +uint16_t pci_config_read16(uint32_t pci_addr, uint8_t reg) +{ + pci_addr |= reg & ~3; + outl(PCI_ADDR_REG, pci_addr); + return inw(PCI_DATA_REG + (reg & 2)); +} + +uint32_t pci_config_read32(uint32_t pci_addr, uint8_t reg) +{ + pci_addr |= reg & ~3; + outl(PCI_ADDR_REG, pci_addr); + return inl(PCI_DATA_REG); +} + +void pci_config_write8(uint32_t pci_addr, uint8_t reg, uint8_t data) +{ + pci_addr |= reg & ~3; + outl(PCI_ADDR_REG, pci_addr); + outb(PCI_DATA_REG + (reg & 3), data); +} + +void pci_config_write16(uint32_t pci_addr, uint8_t reg, uint16_t data) +{ + pci_addr |= reg & ~3; + outl(PCI_ADDR_REG, pci_addr); + outw(PCI_DATA_REG + (reg & 2), data); +} + +void pci_config_write32(uint32_t pci_addr, uint8_t reg, uint32_t data) +{ + pci_addr |= reg & ~3; + outl(PCI_ADDR_REG, pci_addr); + outl(PCI_DATA_REG, data); +} + +void scan_pci_bus(pci_dt_t *start, uint8_t bus) +{ + pci_dt_t *new; + pci_dt_t **current = &start->children; + uint32_t id; + uint32_t pci_addr; + uint8_t dev; + uint8_t func; + uint8_t secondary_bus; + uint8_t header_type; + + for (dev = 0; dev < 32; dev++) { + for (func = 0; func < 8; func++) { + pci_addr = PCIADDR(bus, dev, func); + id = pci_config_read32(pci_addr, PCI_VENDOR_ID); + if (!id || id == 0xffffffff) { + continue; + } + new = (pci_dt_t*)malloc(sizeof(pci_dt_t)); + bzero(new, sizeof(pci_dt_t)); + new->dev.addr = pci_addr; + new->vendor_id = id & 0xffff; + new->device_id = (id >> 16) & 0xffff; + new->subsys_id.subsys_id = pci_config_read32(pci_addr, PCI_SUBSYSTEM_VENDOR_ID); + new->class_id = pci_config_read16(pci_addr, PCI_CLASS_DEVICE); + new->parent = start; + + header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE); + switch (header_type & 0x7f) { + case PCI_HEADER_TYPE_BRIDGE: + case PCI_HEADER_TYPE_CARDBUS: + secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS); + if (secondary_bus != 0) { + scan_pci_bus(new, secondary_bus); + } + break; + } + *current = new; + current = &new->next; + + if ((func == 0) && ((header_type & 0x80) == 0)) { + break; + } + } + } +} + +void enable_pci_devs(void) +{ + uint16_t id; + uint32_t rcba, *fd; + + id = pci_config_read16(PCIADDR(0, 0x00, 0), 0x00); + /* make sure we're on Intel chipset */ + if (id != 0x8086) + return; + rcba = pci_config_read32(PCIADDR(0, 0x1f, 0), 0xf0) & ~1; + fd = (uint32_t *)(rcba + 0x3418); + /* set SMBus Disable (SD) to 0 */ + *fd &= ~0x8; + /* and all devices? */ + //*fd = 0x1; +} + + +void build_pci_dt(void) +{ + root_pci_dev = malloc(sizeof(pci_dt_t)); + bzero(root_pci_dev, sizeof(pci_dt_t)); + enable_pci_devs(); + scan_pci_bus(root_pci_dev, 0); + +#if DEBUG_PCI + dump_pci_dt(root_pci_dev->children); + pause(); +#endif +} + +static char dev_path[256]; +char *get_pci_dev_path(pci_dt_t *pci_dt) +{ + pci_dt_t *current; + pci_dt_t *end; + char tmp[64]; + + dev_path[0] = 0; + end = root_pci_dev; + + int uid = getPciRootUID(); + while (end != pci_dt) + { + current = pci_dt; + while (current->parent != end) + current = current->parent; + end = current; + if (current->parent == root_pci_dev) + { + sprintf(tmp, "PciRoot(0x%x)/Pci(0x%x,0x%x)", uid, + current->dev.bits.dev, current->dev.bits.func); + } else { + sprintf(tmp, "/Pci(0x%x,0x%x)", + current->dev.bits.dev, current->dev.bits.func); + } + strcat(dev_path, tmp); + } + return dev_path; +} + +void dump_pci_dt(pci_dt_t *pci_dt) +{ + pci_dt_t *current; + + current = pci_dt; + while (current) { + printf("%02x:%02x.%x [%04x] [%04x:%04x] (subsys [%04x:%04x]):: %s\n", + current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, + current->class_id, current->vendor_id, current->device_id, + current->subsys_id.subsys.vendor_id, current->subsys_id.subsys.device_id, + get_pci_dev_path(current)); + dump_pci_dt(current->children); + current = current->next; + } +} Index: branches/Chimera/i386/libsaio/.svn/text-base/ufs_byteorder.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ufs_byteorder.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ufs_byteorder.c.svn-base (revision 850) @@ -0,0 +1,171 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright 1993 NeXT, Inc. + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ufs_byteorder.h" +#include "libsaio.h" + +#define swapBigLongToHost(thing) ((thing) = OSSwapBigToHostInt32(thing)) +#define swapBigShortToHost(thing) ((thing) = OSSwapBigToHostInt16(thing)) +#define byte_swap_longlong(thing) ((thing) = OSSwapBigToHostInt64(thing)) +#define byte_swap_int(thing) ((thing) = OSSwapBigToHostInt32(thing)) +#define byte_swap_short(thing) ((thing) = OSSwapBigToHostInt16(thing)) + +#if UNUSED +void +byte_swap_longlongs(unsigned long long *array, int count) +{ + register unsigned long long i; + + for (i = 0; i < (unsigned long long)count; i++) + byte_swap_longlong(array[i]); +} +#endif + +void +byte_swap_ints(unsigned int *array, int count) +{ + register int i; + + for (i = 0; i < count; i++) + byte_swap_int(array[i]); +} + +void +byte_swap_shorts(unsigned short *array, int count) +{ + register int i; + + for (i = 0; i < count; i++) + byte_swap_short(array[i]); +} + +#if UNUSED +static void +swapBigIntsToHost(unsigned int *array, int count) +{ + register int i; + + for (i = 0; i < count; i++) + swapBigLongToHost(array[i]); +} + +static void +swapBigShortToHosts(unsigned short *array, int count) +{ + register int i; + + for (i = 0; i < count; i++) + swapBigShortToHost(array[i]); +} +#endif + +void +byte_swap_superblock(struct fs *sb) +{ + u_int16_t * usptr; + unsigned long size; + + byte_swap_ints(((u_int32_t *)&sb->fs_firstfield), 52); + byte_swap_int(sb->fs_cgrotor); + byte_swap_int(sb->fs_cpc); + byte_swap_shorts((u_int16_t *)sb->fs_opostbl, 16 * 8); + byte_swap_ints((u_int32_t *)sb->fs_sparecon, 50); + byte_swap_ints((u_int32_t *)&sb->fs_contigsumsize, 3); +#if UNUSED + byte_swap_longlongs((u_int64_t *)&sb->fs_maxfilesize,3); +#endif + byte_swap_ints((u_int32_t *)&sb->fs_state, 6); + + /* Got these magic numbers from mkfs.c in newfs */ + if (sb->fs_nrpos != 8 || sb->fs_cpc > 16) { + usptr = (u_int16_t *)((u_int8_t *)(sb) + (sb)->fs_postbloff); + size = sb->fs_cpc * sb->fs_nrpos; + byte_swap_shorts(usptr,size); /* fs_postbloff */ + } +} + + +/* This value should correspond to the value set in the ffs_mounts */ + +#define RESYMLNKLEN 60 + +void +byte_swap_dinode_in(struct dinode *di) +{ + int i; + + di->di_mode = OSSwapInt16(di->di_mode); + di->di_nlink = OSSwapInt16(di->di_nlink); +#ifdef LFS + di->di_u.inumber = OSSwapInt32(di->di_u.inumber); +#else + di->di_u.oldids[0] = OSSwapInt16(di->di_u.oldids[0]); + di->di_u.oldids[1] = OSSwapInt16(di->di_u.oldids[1]); +#endif + di->di_size = OSSwapInt64(di->di_size); + di->di_atime = OSSwapInt32(di->di_atime); + di->di_atimensec = OSSwapInt32(di->di_atimensec); + di->di_mtime = OSSwapInt32(di->di_mtime); + di->di_mtimensec = OSSwapInt32(di->di_mtimensec); + di->di_ctime = OSSwapInt32(di->di_ctime); + di->di_ctimensec = OSSwapInt32(di->di_ctimensec); + if (((di->di_mode & IFMT) != IFLNK ) || (di->di_size > RESYMLNKLEN)) { + for (i=0; i < NDADDR; i++) /* direct blocks */ + di->di_db[i] = OSSwapInt32(di->di_db[i]); + for (i=0; i < NIADDR; i++) /* indirect blocks */ + di->di_ib[i] = OSSwapInt32(di->di_ib[i]); + } + di->di_flags = OSSwapInt32(di->di_flags); + di->di_blocks = OSSwapInt32(di->di_blocks); + di->di_gen = OSSwapInt32(di->di_gen); + di->di_uid = OSSwapInt32(di->di_uid); + di->di_gid = OSSwapInt32(di->di_gid); + di->di_spare[0] = OSSwapInt32(di->di_spare[0]); + di->di_spare[1] = OSSwapInt32(di->di_spare[1]); +} + +void +byte_swap_dir_block_in(char *addr, int count) +{ + register struct direct * ep = (struct direct *) addr; + register int entryoffsetinblk = 0; + + while (entryoffsetinblk < count) { + ep = (struct direct *) (entryoffsetinblk + addr); + swapBigLongToHost(ep->d_ino); + swapBigShortToHost(ep->d_reclen); + entryoffsetinblk += ep->d_reclen; + if (ep->d_reclen < 12) /* handle garbage in dirs */ + break; + } +} Index: branches/Chimera/i386/libsaio/.svn/text-base/device_tree.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/device_tree.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/device_tree.c.svn-base (revision 850) @@ -0,0 +1,540 @@ +/* + * Copyright (c) 2005 Apple Computer, Inc. All Rights Reserved. + */ + +#if 1 +/* + + Structures for a Flattened Device Tree + */ + +#define kPropNameLength 32 + +typedef struct DeviceTreeNodeProperty { + char name[kPropNameLength]; // NUL terminated property name + unsigned long length; // Length (bytes) of folloing prop value + // unsigned long value[1]; // Variable length value of property + // Padded to a multiple of a longword? +} DeviceTreeNodeProperty; + +typedef struct OpaqueDTEntry { + unsigned long nProperties; // Number of props[] elements (0 => end) + unsigned long nChildren; // Number of children[] elements + // DeviceTreeNodeProperty props[];// array size == nProperties + // DeviceTreeNode children[]; // array size == nChildren +} DeviceTreeNode; + +typedef char DTPropertyNameBuf[32]; +/* Entry Name Definitions (Entry Names are C-Strings)*/ +enum { + kDTMaxEntryNameLength = 31 /* Max length of a C-String Entry Name (terminator not included) */ +}; + +/* length of DTEntryNameBuf = kDTMaxEntryNameLength +1*/ +typedef char DTEntryNameBuf[32]; +#endif + +#include "libsaio.h" +#include "device_tree.h" + +#if DEBUG +#define DPRINTF(args...) printf(args) +void +DT__PrintTree(Node *node); +#else +#define DPRINTF(args...) +#endif + + +#define RoundToLong(x) (((x) + 3) & ~3) + +static struct _DTSizeInfo { + uint32_t numNodes; + uint32_t numProperties; + uint32_t totalPropertySize; +} DTInfo; + +#define kAllocSize 4096 + +static Node *rootNode; + +static Node *freeNodes, *allocedNodes; +static Property *freeProperties, *allocedProperties; + +Property * +DT__AddProperty(Node *node, const char *name, uint32_t length, void *value) +{ + Property *prop; + + DPRINTF("DT__AddProperty([Node '%s'], '%s', %d, 0x%x)\n", DT__GetName(node), name, length, value); + if (freeProperties == NULL) { + void *buf = malloc(kAllocSize); + int i; + + DPRINTF("Allocating more free properties\n"); + if (buf == 0) return 0; + bzero(buf, kAllocSize); + // Use the first property to record the allocated buffer + // for later freeing. + prop = (Property *)buf; + prop->next = allocedProperties; + allocedProperties = prop; + prop->value = buf; + prop++; + for (i=1; i<(kAllocSize / sizeof(Property)); i++) { + prop->next = freeProperties; + freeProperties = prop; + prop++; + } + } + prop = freeProperties; + freeProperties = prop->next; + + prop->name = name; + prop->length = length; + prop->value = value; + + // Always add to end of list + if (node->properties == 0) { + node->properties = prop; + } else { + node->last_prop->next = prop; + } + node->last_prop = prop; + prop->next = 0; + + DPRINTF("Done [0x%x]\n", prop); + + DTInfo.numProperties++; + DTInfo.totalPropertySize += RoundToLong(length); + + return prop; +} + +Node * +DT__AddChild(Node *parent, const char *name) +{ + Node *node; + + if (freeNodes == NULL) { + void *buf = malloc(kAllocSize); + int i; + + DPRINTF("Allocating more free nodes\n"); + if (buf == 0) return 0; + bzero(buf, kAllocSize); + node = (Node *)buf; + // Use the first node to record the allocated buffer + // for later freeing. + node->next = allocedNodes; + allocedNodes = node; + node->children = (Node *)buf; + node++; + for (i=1; i<(kAllocSize / sizeof(Node)); i++) { + node->next = freeNodes; + freeNodes = node; + node++; + } + } + DPRINTF("DT__AddChild(0x%x, '%s')\n", parent, name); + node = freeNodes; + freeNodes = node->next; + DPRINTF("Got free node 0x%x\n", node); + DPRINTF("prop = 0x%x, children = 0x%x, next = 0x%x\n", node->properties, node->children, node->next); + + if (parent == NULL) { + rootNode = node; + node->next = 0; + } else { + node->next = parent->children; + parent->children = node; + } + DTInfo.numNodes++; + DT__AddProperty(node, "name", strlen(name) + 1, (void *) name); + return node; +} + +void +DT__FreeProperty(Property *prop) +{ + prop->next = freeProperties; + freeProperties = prop; +} +void +DT__FreeNode(Node *node) +{ + node->next = freeNodes; + freeNodes = node; +} + +void +DT__Initialize(void) +{ + DPRINTF("DT__Initialize\n"); + + freeNodes = 0; + allocedNodes = 0; + freeProperties = 0; + allocedProperties = 0; + + DTInfo.numNodes = 0; + DTInfo.numProperties = 0; + DTInfo.totalPropertySize = 0; + + rootNode = DT__AddChild(NULL, "/"); + DPRINTF("DT__Initialize done\n"); +} + +/* + * Free up memory used by in-memory representation + * of device tree. + */ +void +DT__Finalize(void) +{ + Node *node; + Property *prop; + + DPRINTF("DT__Finalize\n"); + for (prop = allocedProperties; prop != NULL; prop = prop->next) { + free(prop->value); + } + allocedProperties = NULL; + freeProperties = NULL; + + for (node = allocedNodes; node != NULL; node = node->next) { + free((void *)node->children); + } + allocedNodes = NULL; + freeNodes = NULL; + rootNode = NULL; + + // XXX leaks any created strings + + DTInfo.numNodes = 0; + DTInfo.numProperties = 0; + DTInfo.totalPropertySize = 0; +} + +static void * +FlattenNodes(Node *node, void *buffer) +{ + Property *prop; + DeviceTreeNode *flatNode; + DeviceTreeNodeProperty *flatProp; + int count; + + if (node == 0) return buffer; + + flatNode = (DeviceTreeNode *)buffer; + buffer += sizeof(DeviceTreeNode); + + for (count = 0, prop = node->properties; prop != 0; count++, prop = prop->next) { + flatProp = (DeviceTreeNodeProperty *)buffer; + strcpy(flatProp->name, prop->name); + flatProp->length = prop->length; + buffer += sizeof(DeviceTreeNodeProperty); + bcopy(prop->value, buffer, prop->length); + buffer += RoundToLong(prop->length); + } + flatNode->nProperties = count; + + for (count = 0, node = node->children; node != 0; count++, node = node->next) { + buffer = FlattenNodes(node, buffer); + } + flatNode->nChildren = count; + + return buffer; +} + +/* + * Flatten the in-memory representation of the device tree + * into a binary DT block. + * To get the buffer size needed, call with result = 0. + * To have a buffer allocated for you, call with *result = 0. + * To use your own buffer, call with *result = &buffer. + */ + +void +DT__FlattenDeviceTree(void **buffer_p, uint32_t *length) +{ + uint32_t totalSize; + void *buf; + + DPRINTF("DT__FlattenDeviceTree(0x%x, 0x%x)\n", buffer_p, length); +#if DEBUG + if (buffer_p) DT__PrintTree(rootNode); +#endif + + totalSize = DTInfo.numNodes * sizeof(DeviceTreeNode) + + DTInfo.numProperties * sizeof(DeviceTreeNodeProperty) + + DTInfo.totalPropertySize; + + DPRINTF("Total size 0x%x\n", totalSize); + if (buffer_p != 0) { + if (totalSize == 0) { + buf = 0; + } else { + if (*buffer_p == 0) { + buf = malloc(totalSize); + } else { + buf = *buffer_p; + } + bzero(buf, totalSize); + + FlattenNodes(rootNode, buf); + } + *buffer_p = buf; + } + if (length) + *length = totalSize; +} + +char * +DT__GetName(Node *node) +{ + Property *prop; + + //DPRINTF("DT__GetName(0x%x)\n", node); + //DPRINTF("Node properties = 0x%x\n", node->properties); + for (prop = node->properties; prop; prop = prop->next) { + //DPRINTF("Prop '%s'\n", prop->name); + if (strcmp(prop->name, "name") == 0) { + return prop->value; + } + } + //DPRINTF("DT__GetName returns 0\n"); + return "(null)"; +} + +Node * +DT__FindNode(const char *path, bool createIfMissing) +{ + Node *node, *child; + DTPropertyNameBuf nameBuf; + char *bp; + int i; + + DPRINTF("DT__FindNode('%s', %d)\n", path, createIfMissing); + + // Start at root + node = rootNode; + DPRINTF("root = 0x%x\n", rootNode); + + while (node) { + // Skip leading slash + while (*path == '/') path++; + + for (i=0, bp = nameBuf; ++i < kDTMaxEntryNameLength && *path && *path != '/'; bp++, path++) *bp = *path; + *bp = '\0'; + + if (nameBuf[0] == '\0') { + // last path entry + break; + } + DPRINTF("Node '%s'\n", nameBuf); + + for (child = node->children; child != 0; child = child->next) { + DPRINTF("Child 0x%x\n", child); + if (strcmp(DT__GetName(child), nameBuf) == 0) { + break; + } + } + if (child == 0 && createIfMissing) { + DPRINTF("Creating node\n"); + char *str = malloc(strlen(nameBuf) + 1); + // XXX this will leak + strcpy(str, nameBuf); + + child = DT__AddChild(node, str); + } + node = child; + } + return node; +} + +#if DEBUG + +void +DT__PrintNode(Node *node, int level) +{ + char spaces[10], *cp = spaces; + Property *prop; + + if (level > 9) level = 9; + while (level--) *cp++ = ' '; + *cp = '\0'; + + printf("%s===Node===\n", spaces); + for (prop = node->properties; prop; prop = prop->next) { + char c = *((char *)prop->value); + if (prop->length < 64 && ( + strcmp(prop->name, "name") == 0 || + (c >= '0' && c <= '9') || + (c >= 'a' && c <= 'z') || + (c >= 'A' && c <= 'Z') || c == '_')) { + printf("%s Property '%s' [%d] = '%s'\n", spaces, prop->name, prop->length, prop->value); + } else { + printf("%s Property '%s' [%d] = (data)\n", spaces, prop->name, prop->length); + } + } + printf("%s==========\n", spaces); +} + +static void +_PrintTree(Node *node, int level) +{ + DT__PrintNode(node, level); + level++; + for (node = node->children; node; node = node->next) + _PrintTree(node, level); +} + +void +DT__PrintTree(Node *node) +{ + if (node == 0) node = rootNode; + _PrintTree(node, 0); +} + +void +DT__PrintFlattenedNode(DTEntry entry, int level) +{ + char spaces[10], *cp = spaces; + DTPropertyIterator propIter; + char *name; + void *prop; + int propSize; + + if (level > 9) level = 9; + while (level--) *cp++ = ' '; + *cp = '\0'; + + printf("%s===Entry %p===\n", spaces, entry); + if (kSuccess != DTCreatePropertyIterator(entry, &propIter)) { + printf("Couldn't create property iterator\n"); + return; + } + while( kSuccess == DTIterateProperties( propIter, &name)) { + if( kSuccess != DTGetProperty( entry, name, &prop, &propSize )) + continue; + printf("%s Property %s = %s\n", spaces, name, prop); + } + DTDisposePropertyIterator(propIter); + + printf("%s==========\n", spaces); +} + +static void +_PrintFlattenedTree(DTEntry entry, int level) +{ + DTEntryIterator entryIter; + + PrintFlattenedNode(entry, level); + + if (kSuccess != DTCreateEntryIterator(entry, &entryIter)) { + printf("Couldn't create entry iterator\n"); + return; + } + level++; + while (kSuccess == DTIterateEntries( entryIter, &entry )) { + _PrintFlattenedTree(entry, level); + } + DTDisposeEntryIterator(entryIter); +} + +void +DT__PrintFlattenedTree(DTEntry entry) +{ + _PrintFlattenedTree(entry, 0); +} + + +int +main(int argc, char **argv) +{ + DTEntry dtEntry; + DTPropertyIterator propIter; + DTEntryIterator entryIter; + void *prop; + int propSize; + char *name; + void *flatTree; + uint32_t flatSize; + + Node *node; + + node = AddChild(NULL, "device-tree"); + AddProperty(node, "potato", 4, "foo"); + AddProperty(node, "chemistry", 4, "bar"); + AddProperty(node, "physics", 4, "baz"); + + node = AddChild(node, "dev"); + AddProperty(node, "one", 4, "one"); + AddProperty(node, "two", 4, "two"); + AddProperty(node, "three", 6, "three"); + + node = AddChild(rootNode, "foo"); + AddProperty(node, "aaa", 4, "aab"); + AddProperty(node, "bbb", 4, "bbc"); + AddProperty(node, "cccc", 6, "ccccd"); + + node = FindNode("/this/is/a/test", 1); + AddProperty(node, "dddd", 12, "abcdefghijk"); + + printf("In-memory tree:\n\n"); + + PrintTree(rootNode); + + FlattenDeviceTree(&flatTree, &flatSize); + + printf("Flat tree = %p, size %d\n", flatTree, flatSize); + + dtEntry = (DTEntry)flatTree; + + printf("\n\nPrinting flat tree\n\n"); + + DTInit(dtEntry); + + PrintFlattenedTree((DTEntry)flatTree); +#if 0 + printf("=== Entry %p ===\n", dtEntry); + if (kSuccess != DTCreatePropertyIterator(dtEntry, &propIter)) { + printf("Couldn't create property iterator\n"); + return 1; + } + while( kSuccess == DTIterateProperties( propIter, &name)) { + if( kSuccess != DTGetProperty( dtEntry, name, &prop, &propSize )) + continue; + printf(" Property %s = %s\n", name, prop); + } + DTDisposePropertyIterator(propIter); + printf("========\n"); + + if (kSuccess != DTCreateEntryIterator(dtEntry, &entryIter)) { + printf("Couldn't create entry iterator\n"); + return 1; + } + while (kSuccess == DTIterateEntries( entryIter, &dtEntry )) { + printf("=== Entry %p ===\n", dtEntry); + + if (kSuccess != DTCreatePropertyIterator(dtEntry, &propIter)) { + printf("Couldn't create property iterator\n"); + return 1; + } + while( kSuccess == DTIterateProperties( propIter, &name)) { + if( kSuccess != DTGetProperty( dtEntry, name, &prop, &propSize )) + continue; + printf(" Property %s = %s\n", name, prop); + } + DTDisposePropertyIterator(propIter); + printf("========\n"); + } + DTDisposeEntryIterator(entryIter); +#endif + + return 0; +} + +#endif + Index: branches/Chimera/i386/libsaio/.svn/text-base/ati_reg.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ati_reg.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ati_reg.h.svn-base (revision 850) @@ -0,0 +1,5672 @@ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * !!!! FIXME !!!! + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + */ + +/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h + * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT + * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ + +#ifndef _ATI_REG_H_ +#define _ATI_REG_H_ + +#define ATI_DATATYPE_VQ 0 +#define ATI_DATATYPE_CI4 1 +#define ATI_DATATYPE_CI8 2 +#define ATI_DATATYPE_ARGB1555 3 +#define ATI_DATATYPE_RGB565 4 +#define ATI_DATATYPE_RGB888 5 +#define ATI_DATATYPE_ARGB8888 6 +#define ATI_DATATYPE_RGB332 7 +#define ATI_DATATYPE_Y8 8 +#define ATI_DATATYPE_RGB8 9 +#define ATI_DATATYPE_CI16 10 +#define ATI_DATATYPE_VYUY_422 11 +#define ATI_DATATYPE_YVYU_422 12 +#define ATI_DATATYPE_AYUV_444 14 +#define ATI_DATATYPE_ARGB4444 15 + + /* Registers for 2D/Video/Overlay */ +#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ +#define RADEON_AGP_BASE 0x0170 +#define RADEON_AGP_CNTL 0x0174 +# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) +# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) +# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) +# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) +# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) +# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) +# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) +# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) +#define RADEON_STATUS_PCI_CONFIG 0x06 +# define RADEON_CAP_LIST 0x100000 +#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ +# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ +# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ +# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ +# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ +#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ +#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +# define RADEON_AGP_ENABLE (1<<8) +#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ +#define RADEON_AGP_STATUS 0x0f5c /* PCI */ +# define RADEON_AGP_1X_MODE 0x01 +# define RADEON_AGP_2X_MODE 0x02 +# define RADEON_AGP_4X_MODE 0x04 +# define RADEON_AGP_FW_MODE 0x10 +# define RADEON_AGP_MODE_MASK 0x17 +# define RADEON_AGPv3_MODE 0x08 +# define RADEON_AGPv3_4X_MODE 0x01 +# define RADEON_AGPv3_8X_MODE 0x02 +#define RADEON_ATTRDR 0x03c1 /* VGA */ +#define RADEON_ATTRDW 0x03c0 /* VGA */ +#define RADEON_ATTRX 0x03c0 /* VGA */ +#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 +#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc + +#define RADEON_BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +# define RADEON_FP_PANEL_SCALABLE (1 << 16) +# define RADEON_FP_PANEL_SCALE_EN (1 << 17) +# define RADEON_FP_CHIP_SCALE_EN (1 << 18) +# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) +# define RADEON_DISPLAY_ROT_MASK (3 << 28) +# define RADEON_DISPLAY_ROT_00 (0 << 28) +# define RADEON_DISPLAY_ROT_90 (1 << 28) +# define RADEON_DISPLAY_ROT_180 (2 << 28) +# define RADEON_DISPLAY_ROT_270 (3 << 28) +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +# define RADEON_CRT1_ATTACHED_MASK (3 << 0) +# define RADEON_CRT1_ATTACHED_MONO (1 << 0) +# define RADEON_CRT1_ATTACHED_COLOR (2 << 0) +# define RADEON_LCD1_ATTACHED (1 << 2) +# define RADEON_DFP1_ATTACHED (1 << 3) +# define RADEON_TV1_ATTACHED_MASK (3 << 4) +# define RADEON_TV1_ATTACHED_COMP (1 << 4) +# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) +# define RADEON_CRT2_ATTACHED_MASK (3 << 8) +# define RADEON_CRT2_ATTACHED_MONO (1 << 8) +# define RADEON_CRT2_ATTACHED_COLOR (2 << 8) +# define RADEON_DFP2_ATTACHED (1 << 11) +#define RADEON_BIOS_5_SCRATCH 0x0024 +# define RADEON_LCD1_ON (1 << 0) +# define RADEON_CRT1_ON (1 << 1) +# define RADEON_TV1_ON (1 << 2) +# define RADEON_DFP1_ON (1 << 3) +# define RADEON_CRT2_ON (1 << 5) +# define RADEON_CV1_ON (1 << 6) +# define RADEON_DFP2_ON (1 << 7) +# define RADEON_LCD1_CRTC_MASK (1 << 8) +# define RADEON_LCD1_CRTC_SHIFT 8 +# define RADEON_CRT1_CRTC_MASK (1 << 9) +# define RADEON_CRT1_CRTC_SHIFT 9 +# define RADEON_TV1_CRTC_MASK (1 << 10) +# define RADEON_TV1_CRTC_SHIFT 10 +# define RADEON_DFP1_CRTC_MASK (1 << 11) +# define RADEON_DFP1_CRTC_SHIFT 11 +# define RADEON_CRT2_CRTC_MASK (1 << 12) +# define RADEON_CRT2_CRTC_SHIFT 12 +# define RADEON_CV1_CRTC_MASK (1 << 13) +# define RADEON_CV1_CRTC_SHIFT 13 +# define RADEON_DFP2_CRTC_MASK (1 << 14) +# define RADEON_DFP2_CRTC_SHIFT 14 +#define RADEON_BIOS_6_SCRATCH 0x0028 +# define RADEON_ACC_MODE_CHANGE (1 << 2) +# define RADEON_EXT_DESKTOP_MODE (1 << 3) +# define RADEON_LCD_DPMS_ON (1 << 20) +# define RADEON_CRT_DPMS_ON (1 << 21) +# define RADEON_TV_DPMS_ON (1 << 22) +# define RADEON_DFP_DPMS_ON (1 << 23) +# define RADEON_DPMS_MASK (3 << 24) +# define RADEON_DPMS_ON (0 << 24) +# define RADEON_DPMS_STANDBY (1 << 24) +# define RADEON_DPMS_SUSPEND (2 << 24) +# define RADEON_DPMS_OFF (3 << 24) +# define RADEON_SCREEN_BLANKING (1 << 26) +# define RADEON_DRIVER_CRITICAL (1 << 27) +# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) +#define RADEON_BIOS_7_SCRATCH 0x002c +# define RADEON_SYS_HOTKEY (1 << 10) +# define RADEON_DRV_LOADED (1 << 12) +#define RADEON_BIOS_ROM 0x0f30 /* PCI */ +#define RADEON_BIST 0x0f0f /* PCI */ +#define RADEON_BRUSH_DATA0 0x1480 +#define RADEON_BRUSH_DATA1 0x1484 +#define RADEON_BRUSH_DATA10 0x14a8 +#define RADEON_BRUSH_DATA11 0x14ac +#define RADEON_BRUSH_DATA12 0x14b0 +#define RADEON_BRUSH_DATA13 0x14b4 +#define RADEON_BRUSH_DATA14 0x14b8 +#define RADEON_BRUSH_DATA15 0x14bc +#define RADEON_BRUSH_DATA16 0x14c0 +#define RADEON_BRUSH_DATA17 0x14c4 +#define RADEON_BRUSH_DATA18 0x14c8 +#define RADEON_BRUSH_DATA19 0x14cc +#define RADEON_BRUSH_DATA2 0x1488 +#define RADEON_BRUSH_DATA20 0x14d0 +#define RADEON_BRUSH_DATA21 0x14d4 +#define RADEON_BRUSH_DATA22 0x14d8 +#define RADEON_BRUSH_DATA23 0x14dc +#define RADEON_BRUSH_DATA24 0x14e0 +#define RADEON_BRUSH_DATA25 0x14e4 +#define RADEON_BRUSH_DATA26 0x14e8 +#define RADEON_BRUSH_DATA27 0x14ec +#define RADEON_BRUSH_DATA28 0x14f0 +#define RADEON_BRUSH_DATA29 0x14f4 +#define RADEON_BRUSH_DATA3 0x148c +#define RADEON_BRUSH_DATA30 0x14f8 +#define RADEON_BRUSH_DATA31 0x14fc +#define RADEON_BRUSH_DATA32 0x1500 +#define RADEON_BRUSH_DATA33 0x1504 +#define RADEON_BRUSH_DATA34 0x1508 +#define RADEON_BRUSH_DATA35 0x150c +#define RADEON_BRUSH_DATA36 0x1510 +#define RADEON_BRUSH_DATA37 0x1514 +#define RADEON_BRUSH_DATA38 0x1518 +#define RADEON_BRUSH_DATA39 0x151c +#define RADEON_BRUSH_DATA4 0x1490 +#define RADEON_BRUSH_DATA40 0x1520 +#define RADEON_BRUSH_DATA41 0x1524 +#define RADEON_BRUSH_DATA42 0x1528 +#define RADEON_BRUSH_DATA43 0x152c +#define RADEON_BRUSH_DATA44 0x1530 +#define RADEON_BRUSH_DATA45 0x1534 +#define RADEON_BRUSH_DATA46 0x1538 +#define RADEON_BRUSH_DATA47 0x153c +#define RADEON_BRUSH_DATA48 0x1540 +#define RADEON_BRUSH_DATA49 0x1544 +#define RADEON_BRUSH_DATA5 0x1494 +#define RADEON_BRUSH_DATA50 0x1548 +#define RADEON_BRUSH_DATA51 0x154c +#define RADEON_BRUSH_DATA52 0x1550 +#define RADEON_BRUSH_DATA53 0x1554 +#define RADEON_BRUSH_DATA54 0x1558 +#define RADEON_BRUSH_DATA55 0x155c +#define RADEON_BRUSH_DATA56 0x1560 +#define RADEON_BRUSH_DATA57 0x1564 +#define RADEON_BRUSH_DATA58 0x1568 +#define RADEON_BRUSH_DATA59 0x156c +#define RADEON_BRUSH_DATA6 0x1498 +#define RADEON_BRUSH_DATA60 0x1570 +#define RADEON_BRUSH_DATA61 0x1574 +#define RADEON_BRUSH_DATA62 0x1578 +#define RADEON_BRUSH_DATA63 0x157c +#define RADEON_BRUSH_DATA7 0x149c +#define RADEON_BRUSH_DATA8 0x14a0 +#define RADEON_BRUSH_DATA9 0x14a4 +#define RADEON_BRUSH_SCALE 0x1470 +#define RADEON_BRUSH_Y_X 0x1474 +#define RADEON_BUS_CNTL 0x0030 +# define RADEON_BUS_MASTER_DIS (1 << 6) +# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) +# define RADEON_BUS_RD_DISCARD_EN (1 << 24) +# define RADEON_BUS_RD_ABORT_EN (1 << 25) +# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) +# define RADEON_BUS_WRT_BURST (1 << 29) +# define RADEON_BUS_READ_BURST (1 << 30) +#define RADEON_BUS_CNTL1 0x0034 +# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) + +#define RADEON_PCIE_INDEX 0x0030 +#define RADEON_PCIE_DATA 0x0034 +#define R600_PCIE_PORT_INDEX 0x0038 +#define R600_PCIE_PORT_DATA 0x003c +/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */ +#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */ +# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0 +# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7 +# define RADEON_PCIE_LC_LINK_WIDTH_X0 0 +# define RADEON_PCIE_LC_LINK_WIDTH_X1 1 +# define RADEON_PCIE_LC_LINK_WIDTH_X2 2 +# define RADEON_PCIE_LC_LINK_WIDTH_X4 3 +# define RADEON_PCIE_LC_LINK_WIDTH_X8 4 +# define RADEON_PCIE_LC_LINK_WIDTH_X12 5 +# define RADEON_PCIE_LC_LINK_WIDTH_X16 6 +# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 +# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 +# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) +# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) +# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) +# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) +# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10) +# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11) +#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c +#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c + +#define RADEON_CACHE_CNTL 0x1724 +#define RADEON_CACHE_LINE 0x0f0c /* PCI */ +#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ +#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ +#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ +# define RADEON_DONT_USE_XTALIN (1 << 4) +# define RADEON_SCLK_DYN_START_CNTL (1 << 15) +#define RADEON_CLOCK_CNTL_DATA 0x000c +#define RADEON_CLOCK_CNTL_INDEX 0x0008 +# define RADEON_PLL_WR_EN (1 << 7) +# define RADEON_PLL_DIV_SEL (3 << 8) +# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) +#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */ +# define RADEON_M_SPLL_REF_DIV_MASK 0xff +# define RADEON_M_SPLL_REF_DIV_SHIFT 0 +# define RADEON_MPLL_FB_DIV_MASK 0xff +# define RADEON_MPLL_FB_DIV_SHIFT 8 +# define RADEON_SPLL_FB_DIV_MASK 0xff +# define RADEON_SPLL_FB_DIV_SHIFT 16 +#define RADEON_SPLL_CNTL 0x000c /* PLL */ +# define RADEON_SPLL_SLEEP (1 << 0) +# define RADEON_SPLL_RESET (1 << 1) +# define RADEON_SPLL_PCP_MASK 0x7 +# define RADEON_SPLL_PCP_SHIFT 8 +# define RADEON_SPLL_PVG_MASK 0x7 +# define RADEON_SPLL_PVG_SHIFT 11 +# define RADEON_SPLL_PDC_MASK 0x3 +# define RADEON_SPLL_PDC_SHIFT 14 +#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */ +# define RADEON_ENGIN_DYNCLK_MODE (1 << 12) +# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) +# define RADEON_ACTIVE_HILO_LAT_SHIFT 13 +# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) +# define RADEON_MC_BUSY (1 << 16) +# define RADEON_DLL_READY (1 << 19) +# define RADEON_CG_NO1_DEBUG_0 (1 << 24) +# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) +# define RADEON_DYN_STOP_MODE_MASK (7 << 21) +# define RADEON_TVPLL_PWRMGT_OFF (1 << 30) +# define RADEON_TVCLK_TURNOFF (1 << 31) +#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ +# define RADEON_TCL_BYPASS_DISABLE (1 << 20) +#define RADEON_CLR_CMP_CLR_3D 0x1a24 +#define RADEON_CLR_CMP_CLR_DST 0x15c8 +#define RADEON_CLR_CMP_CLR_SRC 0x15c4 +#define RADEON_CLR_CMP_CNTL 0x15c0 +# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) +# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) +# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) +#define RADEON_CLR_CMP_MASK 0x15cc +# define RADEON_CLR_CMP_MSK 0xffffffff +#define RADEON_CLR_CMP_MASK_3D 0x1A28 +#define RADEON_COMMAND 0x0f04 /* PCI */ +#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c +#define RADEON_CONFIG_APER_0_BASE 0x0100 +#define RADEON_CONFIG_APER_1_BASE 0x0104 +#define RADEON_CONFIG_APER_SIZE 0x0108 +#define RADEON_CONFIG_BONDS 0x00e8 +#define RADEON_CONFIG_CNTL 0x00e0 +# define RADEON_CFG_ATI_REV_A11 (0 << 16) +# define RADEON_CFG_ATI_REV_A12 (1 << 16) +# define RADEON_CFG_ATI_REV_A13 (2 << 16) +# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) +#define RADEON_CONFIG_MEMSIZE 0x00f8 +#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 +#define RADEON_CONFIG_REG_1_BASE 0x010c +#define RADEON_CONFIG_REG_APER_SIZE 0x0110 +#define RADEON_CONFIG_XSTRAP 0x00e4 +#define RADEON_CONSTANT_COLOR_C 0x1d34 +# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff +# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff +# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 +#define RADEON_CRC_CMDFIFO_ADDR 0x0740 +#define RADEON_CRC_CMDFIFO_DOUT 0x0744 +#define RADEON_GRPH_BUFFER_CNTL 0x02f0 +# define RADEON_GRPH_START_REQ_MASK (0x7f) +# define RADEON_GRPH_START_REQ_SHIFT 0 +# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH_STOP_REQ_SHIFT 8 +# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH_BUFFER_SIZE (1<<29) +# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH_STOP_CNTL (1<<31) +#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 +# define RADEON_GRPH2_START_REQ_MASK (0x7f) +# define RADEON_GRPH2_START_REQ_SHIFT 0 +# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH2_STOP_REQ_SHIFT 8 +# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH2_BUFFER_SIZE (1<<29) +# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH2_STOP_CNTL (1<<31) +#define RADEON_CRTC_CRNT_FRAME 0x0214 +#define RADEON_CRTC_EXT_CNTL 0x0054 +# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) +# define RADEON_VGA_ATI_LINEAR (1 << 3) +# define RADEON_XCRT_CNT_EN (1 << 6) +# define RADEON_CRTC_HSYNC_DIS (1 << 8) +# define RADEON_CRTC_VSYNC_DIS (1 << 9) +# define RADEON_CRTC_DISPLAY_DIS (1 << 10) +# define RADEON_CRTC_SYNC_TRISTAT (1 << 11) +# define RADEON_CRTC_CRT_ON (1 << 15) +#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) +# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) +# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RADEON_CRTC_GEN_CNTL 0x0050 +# define RADEON_CRTC_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC_INTERLACE_EN (1 << 1) +# define RADEON_CRTC_CSYNC_EN (1 << 4) +# define RADEON_CRTC_ICON_EN (1 << 15) +# define RADEON_CRTC_CUR_EN (1 << 16) +# define RADEON_CRTC_CUR_MODE_MASK (7 << 20) +# define RADEON_CRTC_EXT_DISP_EN (1 << 24) +# define RADEON_CRTC_EN (1 << 25) +# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) +#define RADEON_CRTC2_GEN_CNTL 0x03f8 +# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC2_INTERLACE_EN (1 << 1) +# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) +# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) +# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) +# define RADEON_CRTC2_CRT2_ON (1 << 7) +# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 +# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) +# define RADEON_CRTC2_ICON_EN (1 << 15) +# define RADEON_CRTC2_CUR_EN (1 << 16) +# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) +# define RADEON_CRTC2_DISP_DIS (1 << 23) +# define RADEON_CRTC2_EN (1 << 25) +# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) +# define RADEON_CRTC2_CSYNC_EN (1 << 27) +# define RADEON_CRTC2_HSYNC_DIS (1 << 28) +# define RADEON_CRTC2_VSYNC_DIS (1 << 29) +#define RADEON_CRTC_MORE_CNTL 0x27c +# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) +# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) +# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 +# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0 +# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15) +# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16 +# define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30) +#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 +# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_H_SYNC_POL (1 << 23) +#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 +# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_H_SYNC_POL (1 << 23) +#define RADEON_CRTC_H_TOTAL_DISP 0x0200 +# define RADEON_CRTC_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC_H_TOTAL_SHIFT 0 +# define RADEON_CRTC_H_DISP (0x01ff << 16) +# define RADEON_CRTC_H_DISP_SHIFT 16 +#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 +# define RADEON_CRTC2_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC2_H_TOTAL_SHIFT 0 +# define RADEON_CRTC2_H_DISP (0x01ff << 16) +# define RADEON_CRTC2_H_DISP_SHIFT 16 + +#define RADEON_CRTC_OFFSET_RIGHT 0x0220 +#define RADEON_CRTC_OFFSET 0x0224 +# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) +# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) + +#define RADEON_CRTC2_OFFSET 0x0324 +# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) +# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) +#define RADEON_CRTC_OFFSET_CNTL 0x0228 +# define RADEON_CRTC_TILE_LINE_SHIFT 0 +# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 +# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) +# define R300_CRTC_X_Y_MODE_EN (1 << 9) +# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) +# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) +# define R300_CRTC_MICRO_TILE_EN (1 << 13) +# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) +# define R300_CRTC_MACRO_TILE_EN (1 << 15) +# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) +# define RADEON_CRTC_TILE_EN (1 << 15) +# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) +# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) + +#define R300_CRTC_TILE_X0_Y0 0x0350 +#define R300_CRTC2_TILE_X0_Y0 0x0358 + +#define RADEON_CRTC2_OFFSET_CNTL 0x0328 +# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) +# define RADEON_CRTC2_TILE_EN (1 << 15) +#define RADEON_CRTC_PITCH 0x022c +# define RADEON_CRTC_PITCH__SHIFT 0 +# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 + +#define RADEON_CRTC2_PITCH 0x032c +#define RADEON_CRTC_STATUS 0x005c +# define RADEON_CRTC_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC2_STATUS 0x03fc +# define RADEON_CRTC2_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c +# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_V_SYNC_POL (1 << 23) +#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c +# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_V_SYNC_POL (1 << 23) +#define RADEON_CRTC_V_TOTAL_DISP 0x0208 +# define RADEON_CRTC_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC_V_TOTAL_SHIFT 0 +# define RADEON_CRTC_V_DISP (0x07ff << 16) +# define RADEON_CRTC_V_DISP_SHIFT 16 +#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 +# define RADEON_CRTC2_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC2_V_TOTAL_SHIFT 0 +# define RADEON_CRTC2_V_DISP (0x07ff << 16) +# define RADEON_CRTC2_V_DISP_SHIFT 16 +#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 +# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define RADEON_CRTC2_CRNT_FRAME 0x0314 +#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 +#define RADEON_CRTC2_STATUS 0x03fc +#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 +#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ +#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ +#define RADEON_CUR_CLR0 0x026c +#define RADEON_CUR_CLR1 0x0270 +#define RADEON_CUR_HORZ_VERT_OFF 0x0268 +#define RADEON_CUR_HORZ_VERT_POSN 0x0264 +#define RADEON_CUR_OFFSET 0x0260 +# define RADEON_CUR_LOCK (1 << 31) +#define RADEON_CUR2_CLR0 0x036c +#define RADEON_CUR2_CLR1 0x0370 +#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 +#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 +#define RADEON_CUR2_OFFSET 0x0360 +# define RADEON_CUR2_LOCK (1 << 31) + +#define RADEON_DAC_CNTL 0x0058 +# define RADEON_DAC_RANGE_CNTL (3 << 0) +# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) +# define RADEON_DAC_RANGE_CNTL_MASK 0x03 +# define RADEON_DAC_BLANKING (1 << 2) +# define RADEON_DAC_CMP_EN (1 << 3) +# define RADEON_DAC_CMP_OUTPUT (1 << 7) +# define RADEON_DAC_8BIT_EN (1 << 8) +# define RADEON_DAC_TVO_EN (1 << 10) +# define RADEON_DAC_VGA_ADR_EN (1 << 13) +# define RADEON_DAC_PDWN (1 << 15) +# define RADEON_DAC_MASK_ALL (0xff << 24) +#define RADEON_DAC_CNTL2 0x007c +# define RADEON_DAC2_TV_CLK_SEL (0 << 1) +# define RADEON_DAC2_DAC_CLK_SEL (1 << 0) +# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) +# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) +# define RADEON_DAC2_CMP_EN (1 << 7) +# define RADEON_DAC2_CMP_OUT_R (1 << 8) +# define RADEON_DAC2_CMP_OUT_G (1 << 9) +# define RADEON_DAC2_CMP_OUT_B (1 << 10) +# define RADEON_DAC2_CMP_OUTPUT (1 << 11) +#define RADEON_DAC_EXT_CNTL 0x0280 +# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) +# define RADEON_DAC2_FORCE_DATA_EN (1 << 1) +# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) +# define RADEON_DAC_FORCE_DATA_EN (1 << 5) +# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) +# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 +# define RADEON_DAC_FORCE_DATA_SHIFT 8 +#define RADEON_DAC_MACRO_CNTL 0x0d04 +# define RADEON_DAC_PDWN_R (1 << 16) +# define RADEON_DAC_PDWN_G (1 << 17) +# define RADEON_DAC_PDWN_B (1 << 18) +#define RADEON_TV_DAC_CNTL 0x088c +# define RADEON_TV_DAC_NBLANK (1 << 0) +# define RADEON_TV_DAC_NHOLD (1 << 1) +# define RADEON_TV_DAC_PEDESTAL (1 << 2) +# define RADEON_TV_MONITOR_DETECT_EN (1 << 4) +# define RADEON_TV_DAC_CMPOUT (1 << 5) +# define RADEON_TV_DAC_STD_MASK (3 << 8) +# define RADEON_TV_DAC_STD_PAL (0 << 8) +# define RADEON_TV_DAC_STD_NTSC (1 << 8) +# define RADEON_TV_DAC_STD_PS2 (2 << 8) +# define RADEON_TV_DAC_STD_RS343 (3 << 8) +# define RADEON_TV_DAC_BGSLEEP (1 << 6) +# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) +# define RADEON_TV_DAC_BGADJ_SHIFT 16 +# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) +# define RADEON_TV_DAC_DACADJ_SHIFT 20 +# define RADEON_TV_DAC_RDACPD (1 << 24) +# define RADEON_TV_DAC_GDACPD (1 << 25) +# define RADEON_TV_DAC_BDACPD (1 << 26) +# define RADEON_TV_DAC_RDACDET (1 << 29) +# define RADEON_TV_DAC_GDACDET (1 << 30) +# define RADEON_TV_DAC_BDACDET (1 << 31) +# define R420_TV_DAC_DACADJ_MASK (0x1f << 20) +# define R420_TV_DAC_RDACPD (1 << 25) +# define R420_TV_DAC_GDACPD (1 << 26) +# define R420_TV_DAC_BDACPD (1 << 27) +# define R420_TV_DAC_TVENABLE (1 << 28) +#define RADEON_DISP_HW_DEBUG 0x0d14 +# define RADEON_CRT2_DISP1_SEL (1 << 5) +#define RADEON_DISP_OUTPUT_CNTL 0x0d64 +# define RADEON_DISP_DAC_SOURCE_MASK 0x03 +# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c +# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 +# define RADEON_DISP_DAC_SOURCE_RMX 0x02 +# define RADEON_DISP_DAC_SOURCE_LTU 0x03 +# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 +# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) +# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 +# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) +# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) +# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) +# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) +# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) +# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) +# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) +# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ +# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ +#define RADEON_DISP_TV_OUT_CNTL 0x0d6c +# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) +# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) +#define RADEON_DAC_CRC_SIG 0x02cc +#define RADEON_DAC_DATA 0x03c9 /* VGA */ +#define RADEON_DAC_MASK 0x03c6 /* VGA */ +#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ +#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ +#define RADEON_DDA_CONFIG 0x02e0 +#define RADEON_DDA_ON_OFF 0x02e4 +#define RADEON_DEFAULT_OFFSET 0x16e0 +#define RADEON_DEFAULT_PITCH 0x16e4 +#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 +#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 +#define RADEON_DEVICE_ID 0x0f02 /* PCI */ +#define RADEON_DISP_MISC_CNTL 0x0d00 +# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) +#define RADEON_DISP_MERGE_CNTL 0x0d60 +# define RADEON_DISP_ALPHA_MODE_MASK 0x03 +# define RADEON_DISP_ALPHA_MODE_KEY 0 +# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 +# define RADEON_DISP_ALPHA_MODE_GLOBAL 2 +# define RADEON_DISP_RGB_OFFSET_EN (1 << 8) +# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) +# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) +# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) +#define RADEON_DISP2_MERGE_CNTL 0x0d68 +# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) +#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 +#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 +#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 +#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c +#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 +#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 +#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 +#define RADEON_DP_BRUSH_FRGD_CLR 0x147c +#define RADEON_DP_CNTL 0x16c0 +# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) +# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) +# define RADEON_DP_DST_TILE_LINEAR (0 << 3) +# define RADEON_DP_DST_TILE_MACRO (1 << 3) +# define RADEON_DP_DST_TILE_MICRO (2 << 3) +# define RADEON_DP_DST_TILE_BOTH (3 << 3) +#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +# define RADEON_DST_Y_MAJOR (1 << 2) +# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) +# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) +#define RADEON_DP_DATATYPE 0x16c4 +# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) +#define RADEON_DP_GUI_MASTER_CNTL 0x146c +# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define RADEON_GMC_SRC_CLIPPING (1 << 2) +# define RADEON_GMC_DST_CLIPPING (1 << 3) +# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) +# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) +# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) +# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define RADEON_GMC_BRUSH_NONE (15 << 4) +# define RADEON_GMC_DST_8BPP_CI (2 << 8) +# define RADEON_GMC_DST_15BPP (3 << 8) +# define RADEON_GMC_DST_16BPP (4 << 8) +# define RADEON_GMC_DST_24BPP (5 << 8) +# define RADEON_GMC_DST_32BPP (6 << 8) +# define RADEON_GMC_DST_8BPP_RGB (7 << 8) +# define RADEON_GMC_DST_Y8 (8 << 8) +# define RADEON_GMC_DST_RGB8 (9 << 8) +# define RADEON_GMC_DST_VYUY (11 << 8) +# define RADEON_GMC_DST_YVYU (12 << 8) +# define RADEON_GMC_DST_AYUV444 (14 << 8) +# define RADEON_GMC_DST_ARGB4444 (15 << 8) +# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) +# define RADEON_GMC_DST_DATATYPE_SHIFT 8 +# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) +# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) +# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) +# define RADEON_GMC_CONVERSION_TEMP (1 << 15) +# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) +# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) +# define RADEON_GMC_ROP3_MASK (0xff << 16) +# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) +# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define RADEON_GMC_3D_FCN_EN (1 << 27) +# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) +# define RADEON_GMC_WR_MSK_DIS (1 << 30) +# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) +# define RADEON_ROP3_ZERO 0x00000000 +# define RADEON_ROP3_DSa 0x00880000 +# define RADEON_ROP3_SDna 0x00440000 +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_DSna 0x00220000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DSx 0x00660000 +# define RADEON_ROP3_DSo 0x00ee0000 +# define RADEON_ROP3_DSon 0x00110000 +# define RADEON_ROP3_DSxn 0x00990000 +# define RADEON_ROP3_Dn 0x00550000 +# define RADEON_ROP3_SDno 0x00dd0000 +# define RADEON_ROP3_Sn 0x00330000 +# define RADEON_ROP3_DSno 0x00bb0000 +# define RADEON_ROP3_DSan 0x00770000 +# define RADEON_ROP3_ONE 0x00ff0000 +# define RADEON_ROP3_DPa 0x00a00000 +# define RADEON_ROP3_PDna 0x00500000 +# define RADEON_ROP3_P 0x00f00000 +# define RADEON_ROP3_DPna 0x000a0000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DPx 0x005a0000 +# define RADEON_ROP3_DPo 0x00fa0000 +# define RADEON_ROP3_DPon 0x00050000 +# define RADEON_ROP3_PDxn 0x00a50000 +# define RADEON_ROP3_PDno 0x00f50000 +# define RADEON_ROP3_Pn 0x000f0000 +# define RADEON_ROP3_DPno 0x00af0000 +# define RADEON_ROP3_DPan 0x005f0000 +#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 +#define RADEON_DP_MIX 0x16c8 +#define RADEON_DP_SRC_BKGD_CLR 0x15dc +#define RADEON_DP_SRC_FRGD_CLR 0x15d8 +#define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_DST_BRES_DEC 0x1630 +#define RADEON_DST_BRES_ERR 0x1628 +#define RADEON_DST_BRES_INC 0x162c +#define RADEON_DST_BRES_LNTH 0x1634 +#define RADEON_DST_BRES_LNTH_SUB 0x1638 +#define RADEON_DST_HEIGHT 0x1410 +#define RADEON_DST_HEIGHT_WIDTH 0x143c +#define RADEON_DST_HEIGHT_WIDTH_8 0x158c +#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 +#define RADEON_DST_HEIGHT_Y 0x15a0 +#define RADEON_DST_LINE_START 0x1600 +#define RADEON_DST_LINE_END 0x1604 +#define RADEON_DST_LINE_PATCOUNT 0x1608 +# define RADEON_BRES_CNTL_SHIFT 8 +#define RADEON_DST_OFFSET 0x1404 +#define RADEON_DST_PITCH 0x1408 +#define RADEON_DST_PITCH_OFFSET 0x142c +#define RADEON_DST_PITCH_OFFSET_C 0x1c80 +# define RADEON_PITCH_SHIFT 21 +# define RADEON_DST_TILE_LINEAR (0 << 30) +# define RADEON_DST_TILE_MACRO (1 << 30) +# define RADEON_DST_TILE_MICRO (2 << 30) +# define RADEON_DST_TILE_BOTH (3 << 30) +#define RADEON_DST_WIDTH 0x140c +#define RADEON_DST_WIDTH_HEIGHT 0x1598 +#define RADEON_DST_WIDTH_X 0x1588 +#define RADEON_DST_WIDTH_X_INCY 0x159c +#define RADEON_DST_X 0x141c +#define RADEON_DST_X_SUB 0x15a4 +#define RADEON_DST_X_Y 0x1594 +#define RADEON_DST_Y 0x1420 +#define RADEON_DST_Y_SUB 0x15a8 +#define RADEON_DST_Y_X 0x1438 + +#define RADEON_FCP_CNTL 0x0910 +# define RADEON_FCP0_SRC_PCICLK 0 +# define RADEON_FCP0_SRC_PCLK 1 +# define RADEON_FCP0_SRC_PCLKb 2 +# define RADEON_FCP0_SRC_HREF 3 +# define RADEON_FCP0_SRC_GND 4 +# define RADEON_FCP0_SRC_HREFb 5 +#define RADEON_FLUSH_1 0x1704 +#define RADEON_FLUSH_2 0x1708 +#define RADEON_FLUSH_3 0x170c +#define RADEON_FLUSH_4 0x1710 +#define RADEON_FLUSH_5 0x1714 +#define RADEON_FLUSH_6 0x1718 +#define RADEON_FLUSH_7 0x171c +#define RADEON_FOG_3D_TABLE_START 0x1810 +#define RADEON_FOG_3D_TABLE_END 0x1814 +#define RADEON_FOG_3D_TABLE_DENSITY 0x181c +#define RADEON_FOG_TABLE_INDEX 0x1a14 +#define RADEON_FOG_TABLE_DATA 0x1a18 +#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 +#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 +# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff +# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 +# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff +# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 +# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 +# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff +# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 +# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 +# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 +# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 +# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 +# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 +#define RADEON_FP_GEN_CNTL 0x0284 +# define RADEON_FP_FPON (1 << 0) +# define RADEON_FP_BLANK_EN (1 << 1) +# define RADEON_FP_TMDS_EN (1 << 2) +# define RADEON_FP_PANEL_FORMAT (1 << 3) +# define RADEON_FP_EN_TMDS (1 << 7) +# define RADEON_FP_DETECT_SENSE (1 << 8) +# define R200_FP_SOURCE_SEL_MASK (3 << 10) +# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP_SOURCE_SEL_RMX (2 << 10) +# define R200_FP_SOURCE_SEL_TRANS (3 << 10) +# define RADEON_FP_SEL_CRTC1 (0 << 13) +# define RADEON_FP_SEL_CRTC2 (1 << 13) +# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define RADEON_FP_DFP_SYNC_SEL (1 << 21) +# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) +# define RADEON_FP_CRT_SYNC_SEL (1 << 23) +# define RADEON_FP_USE_SHADOW_EN (1 << 24) +# define RADEON_FP_CRT_SYNC_ALT (1 << 26) +#define RADEON_FP2_GEN_CNTL 0x0288 +# define RADEON_FP2_BLANK_EN (1 << 1) +# define RADEON_FP2_ON (1 << 2) +# define RADEON_FP2_PANEL_FORMAT (1 << 3) +# define RADEON_FP2_DETECT_SENSE (1 << 8) +# define R200_FP2_SOURCE_SEL_MASK (3 << 10) +# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP2_SOURCE_SEL_RMX (2 << 10) +# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) +# define RADEON_FP2_SRC_SEL_MASK (3 << 13) +# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) +# define RADEON_FP2_FP_POL (1 << 16) +# define RADEON_FP2_LP_POL (1 << 17) +# define RADEON_FP2_SCK_POL (1 << 18) +# define RADEON_FP2_LCD_CNTL_MASK (7 << 19) +# define RADEON_FP2_PAD_FLOP_EN (1 << 22) +# define RADEON_FP2_CRC_EN (1 << 23) +# define RADEON_FP2_CRC_READ_EN (1 << 24) +# define RADEON_FP2_DVO_EN (1 << 25) +# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) +# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) +# define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) +# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) +#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 +#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 +#define RADEON_FP_HORZ_STRETCH 0x028c +#define RADEON_FP_HORZ2_STRETCH 0x038c +# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff +# define RADEON_HORZ_STRETCH_RATIO_MAX 4096 +# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) +# define RADEON_HORZ_PANEL_SHIFT 16 +# define RADEON_HORZ_STRETCH_PIXREP (0 << 25) +# define RADEON_HORZ_STRETCH_BLEND (1 << 26) +# define RADEON_HORZ_STRETCH_ENABLE (1 << 25) +# define RADEON_HORZ_AUTO_RATIO (1 << 27) +# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) +#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 +#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 +#define RADEON_FP_VERT_STRETCH 0x0290 +#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 +#define RADEON_FP_VERT2_STRETCH 0x0390 +# define RADEON_VERT_PANEL_SIZE (0xfff << 12) +# define RADEON_VERT_PANEL_SHIFT 12 +# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff +# define RADEON_VERT_STRETCH_RATIO_SHIFT 0 +# define RADEON_VERT_STRETCH_RATIO_MAX 4096 +# define RADEON_VERT_STRETCH_ENABLE (1 << 25) +# define RADEON_VERT_STRETCH_LINEREP (0 << 26) +# define RADEON_VERT_STRETCH_BLEND (1 << 26) +# define RADEON_VERT_AUTO_RATIO_EN (1 << 27) +# define RADEON_VERT_AUTO_RATIO_INC (1 << 31) +# define RADEON_VERT_STRETCH_RESERVED 0x71000000 +#define RS400_FP_2ND_GEN_CNTL 0x0384 +# define RS400_FP_2ND_ON (1 << 0) +# define RS400_FP_2ND_BLANK_EN (1 << 1) +# define RS400_TMDS_2ND_EN (1 << 2) +# define RS400_PANEL_FORMAT_2ND (1 << 3) +# define RS400_FP_2ND_EN_TMDS (1 << 7) +# define RS400_FP_2ND_DETECT_SENSE (1 << 8) +# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) +# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) +# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) +# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) +# define RS400_FP_2ND_DETECT_EN (1 << 12) +# define RS400_HPD_2ND_SEL (1 << 13) +#define RS400_FP2_2_GEN_CNTL 0x0388 +# define RS400_FP2_2_BLANK_EN (1 << 1) +# define RS400_FP2_2_ON (1 << 2) +# define RS400_FP2_2_PANEL_FORMAT (1 << 3) +# define RS400_FP2_2_DETECT_SENSE (1 << 8) +# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) +# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) +# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) +# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) +# define RS400_FP2_2_DVO2_EN (1 << 25) +#define RS400_TMDS2_CNTL 0x0394 +#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 +# define RS400_TMDS2_PLLEN (1 << 0) +# define RS400_TMDS2_PLLRST (1 << 1) + +#define RADEON_GEN_INT_CNTL 0x0040 +#define RADEON_GEN_INT_STATUS 0x0044 +# define RADEON_VSYNC_INT_AK (1 << 2) +# define RADEON_VSYNC_INT (1 << 2) +# define RADEON_VSYNC2_INT_AK (1 << 6) +# define RADEON_VSYNC2_INT (1 << 6) +#define RADEON_GENENB 0x03c3 /* VGA */ +#define RADEON_GENFC_RD 0x03ca /* VGA */ +#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ +#define RADEON_GENMO_RD 0x03cc /* VGA */ +#define RADEON_GENMO_WT 0x03c2 /* VGA */ +#define RADEON_GENS0 0x03c2 /* VGA */ +#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ +#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */ +#define RADEON_GPIO_MONIDB 0x006c +#define RADEON_GPIO_CRT2_DDC 0x006c +#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */ +#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */ +# define RADEON_GPIO_A_0 (1 << 0) +# define RADEON_GPIO_A_1 (1 << 1) +# define RADEON_GPIO_Y_0 (1 << 8) +# define RADEON_GPIO_Y_1 (1 << 9) +# define RADEON_GPIO_Y_SHIFT_0 8 +# define RADEON_GPIO_Y_SHIFT_1 9 +# define RADEON_GPIO_EN_0 (1 << 16) +# define RADEON_GPIO_EN_1 (1 << 17) +# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ +# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ +#define RADEON_GRPH8_DATA 0x03cf /* VGA */ +#define RADEON_GRPH8_IDX 0x03ce /* VGA */ +#define RADEON_GUI_SCRATCH_REG0 0x15e0 +#define RADEON_GUI_SCRATCH_REG1 0x15e4 +#define RADEON_GUI_SCRATCH_REG2 0x15e8 +#define RADEON_GUI_SCRATCH_REG3 0x15ec +#define RADEON_GUI_SCRATCH_REG4 0x15f0 +#define RADEON_GUI_SCRATCH_REG5 0x15f4 + +#define RADEON_HEADER 0x0f0e /* PCI */ +#define RADEON_HOST_DATA0 0x17c0 +#define RADEON_HOST_DATA1 0x17c4 +#define RADEON_HOST_DATA2 0x17c8 +#define RADEON_HOST_DATA3 0x17cc +#define RADEON_HOST_DATA4 0x17d0 +#define RADEON_HOST_DATA5 0x17d4 +#define RADEON_HOST_DATA6 0x17d8 +#define RADEON_HOST_DATA7 0x17dc +#define RADEON_HOST_DATA_LAST 0x17e0 +#define RADEON_HOST_PATH_CNTL 0x0130 +# define RADEON_HDP_SOFT_RESET (1 << 26) +# define RADEON_HDP_APER_CNTL (1 << 23) +#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ +# define RADEON_HTOT_CNTL_VGA_EN (1 << 28) +#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ + + /* Multimedia I2C bus */ +#define RADEON_I2C_CNTL_0 0x0090 +#define RADEON_I2C_DONE (1 << 0) +#define RADEON_I2C_NACK (1 << 1) +#define RADEON_I2C_HALT (1 << 2) +#define RADEON_I2C_SOFT_RST (1 << 5) +#define RADEON_I2C_DRIVE_EN (1 << 6) +#define RADEON_I2C_DRIVE_SEL (1 << 7) +#define RADEON_I2C_START (1 << 8) +#define RADEON_I2C_STOP (1 << 9) +#define RADEON_I2C_RECEIVE (1 << 10) +#define RADEON_I2C_ABORT (1 << 11) +#define RADEON_I2C_GO (1 << 12) +#define RADEON_I2C_CNTL_1 0x0094 +#define RADEON_I2C_SEL (1 << 16) +#define RADEON_I2C_EN (1 << 17) +#define RADEON_I2C_DATA 0x0098 + +#define RADEON_DVI_I2C_CNTL_0 0x02e0 +# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) +# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */ +# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */ +# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */ +#define RADEON_DVI_I2C_CNTL_1 0x02e4 +#define RADEON_DVI_I2C_DATA 0x02e8 + +#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ +#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ +#define RADEON_IO_BASE 0x0f14 /* PCI */ + +#define RADEON_LATENCY 0x0f0d /* PCI */ +#define RADEON_LEAD_BRES_DEC 0x1608 +#define RADEON_LEAD_BRES_LNTH 0x161c +#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 +#define RADEON_LVDS_GEN_CNTL 0x02d0 +# define RADEON_LVDS_ON (1 << 0) +# define RADEON_LVDS_DISPLAY_DIS (1 << 1) +# define RADEON_LVDS_PANEL_TYPE (1 << 2) +# define RADEON_LVDS_PANEL_FORMAT (1 << 3) +# define RADEON_LVDS_RST_FM (1 << 6) +# define RADEON_LVDS_EN (1 << 7) +# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 +# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) +# define RADEON_LVDS_BL_MOD_EN (1 << 16) +# define RADEON_LVDS_DIGON (1 << 18) +# define RADEON_LVDS_BLON (1 << 19) +# define RADEON_LVDS_SEL_CRTC2 (1 << 23) +#define RADEON_LVDS_PLL_CNTL 0x02d4 +# define RADEON_HSYNC_DELAY_SHIFT 28 +# define RADEON_HSYNC_DELAY_MASK (0xf << 28) +# define RADEON_LVDS_PLL_EN (1 << 16) +# define RADEON_LVDS_PLL_RESET (1 << 17) +# define R300_LVDS_SRC_SEL_MASK (3 << 18) +# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) +# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) +# define R300_LVDS_SRC_SEL_RMX (2 << 18) + +#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ +#define RADEON_MC_AGP_LOCATION 0x014c +#define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_DISPLAY_BASE_ADDR 0x23c +#define RADEON_DISPLAY2_BASE_ADDR 0x33c +#define RADEON_OV0_BASE_ADDR 0x43c +#define RADEON_NB_TOM 0x15c +#define R300_MC_INIT_MISC_LAT_TIMER 0x180 +# define R300_MC_DISP0R_INIT_LAT_SHIFT 8 +# define R300_MC_DISP0R_INIT_LAT_MASK 0xf +# define R300_MC_DISP1R_INIT_LAT_SHIFT 12 +# define R300_MC_DISP1R_INIT_LAT_MASK 0xf +#define RADEON_MCLK_CNTL 0x0012 /* PLL */ +# define RADEON_FORCEON_MCLKA (1 << 16) +# define RADEON_FORCEON_MCLKB (1 << 17) +# define RADEON_FORCEON_YCLKA (1 << 18) +# define RADEON_FORCEON_YCLKB (1 << 19) +# define RADEON_FORCEON_MC (1 << 20) +# define RADEON_FORCEON_AIC (1 << 21) +# define R300_DISABLE_MC_MCLKA (1 << 21) +# define R300_DISABLE_MC_MCLKB (1 << 21) +#define RADEON_MCLK_MISC 0x001f /* PLL */ +# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) +# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) +# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) +# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) +#define RADEON_LCD_GPIO_MASK 0x01a0 +#define RADEON_GPIOPAD_EN 0x01a0 +#define RADEON_LCD_GPIO_Y_REG 0x01a4 +#define RADEON_MDGPIO_A_REG 0x01ac +#define RADEON_MDGPIO_EN_REG 0x01b0 +#define RADEON_MDGPIO_MASK 0x0198 +#define RADEON_GPIOPAD_MASK 0x0198 +#define RADEON_GPIOPAD_A 0x019c +#define RADEON_MDGPIO_Y_REG 0x01b4 +#define RADEON_MEM_ADDR_CONFIG 0x0148 +#define RADEON_MEM_BASE 0x0f10 /* PCI */ +#define RADEON_MEM_CNTL 0x0140 +# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 +# define RADEON_MEM_USE_B_CH_ONLY (1 << 1) +# define RV100_HALF_MODE (1 << 3) +# define R300_MEM_NUM_CHANNELS_MASK 0x03 +# define R300_MEM_USE_CD_CH_ONLY (1 << 2) +#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ +#define RADEON_MEM_INIT_LAT_TIMER 0x0154 +#define RADEON_MEM_INTF_CNTL 0x014c +#define RADEON_MEM_SDRAM_MODE_REG 0x0158 +# define RADEON_SDRAM_MODE_MASK 0xffff0000 +# define RADEON_B3MEM_RESET_MASK 0x6fffffff +# define RADEON_MEM_CFG_TYPE_DDR (1 << 30) +#define RADEON_MEM_STR_CNTL 0x0150 +# define RADEON_MEM_PWRUP_COMPL_A (1 << 0) +# define RADEON_MEM_PWRUP_COMPL_B (1 << 1) +# define R300_MEM_PWRUP_COMPL_C (1 << 2) +# define R300_MEM_PWRUP_COMPL_D (1 << 3) +# define RADEON_MEM_PWRUP_COMPLETE 0x03 +# define R300_MEM_PWRUP_COMPLETE 0x0f +#define RADEON_MC_STATUS 0x0150 +# define RADEON_MC_IDLE (1 << 2) +# define R300_MC_IDLE (1 << 4) +#define RADEON_MEM_VGA_RP_SEL 0x003c +#define RADEON_MEM_VGA_WP_SEL 0x0038 +#define RADEON_MIN_GRANT 0x0f3e /* PCI */ +#define RADEON_MM_DATA 0x0004 +#define RADEON_MM_INDEX 0x0000 +#define RADEON_MPLL_CNTL 0x000e /* PLL */ +#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ +#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ +#define RADEON_SEPROM_CNTL1 0x01c0 +# define RADEON_SCK_PRESCALE_SHIFT 24 +# define RADEON_SCK_PRESCALE_MASK (0xff << 24) +#define R300_MC_IND_INDEX 0x01f8 +# define R300_MC_IND_ADDR_MASK 0x3f +# define R300_MC_IND_WR_EN (1 << 8) +#define R300_MC_IND_DATA 0x01fc +#define R300_MC_READ_CNTL_AB 0x017c +# define R300_MEM_RBS_POSITION_A_MASK 0x03 +#define R300_MC_READ_CNTL_CD_mcind 0x24 +# define R300_MEM_RBS_POSITION_C_MASK 0x03 + +#define RADEON_N_VIF_COUNT 0x0248 + +#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 + +#define RADEON_OV0_COLOUR_CNTL 0x04E0 +#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 +#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 +# define RADEON_EXCL_HORZ_START_MASK 0x000000ff +# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 +# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define RADEON_OV0_EXCLUSIVE_VERT 0x040C +# define RADEON_EXCL_VERT_START_MASK 0x000003ff +# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 +#define RADEON_OV0_FILTER_CNTL 0x04A0 +# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 +# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 +# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 +# define RADEON_FILTER_HC_COEF_VERT_Y 0x4 +# define RADEON_FILTER_HC_COEF_VERT_UV 0x8 +# define RADEON_FILTER_HARDCODED_COEF 0xf +# define RADEON_FILTER_COEF_MASK 0xf + +#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 +#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 +#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 +#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC +#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 +#define RADEON_OV0_FLAG_CNTL 0x04DC +#define RADEON_OV0_GAMMA_000_00F 0x0d40 +#define RADEON_OV0_GAMMA_010_01F 0x0d44 +#define RADEON_OV0_GAMMA_020_03F 0x0d48 +#define RADEON_OV0_GAMMA_040_07F 0x0d4c +#define RADEON_OV0_GAMMA_080_0BF 0x0e00 +#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 +#define RADEON_OV0_GAMMA_100_13F 0x0e08 +#define RADEON_OV0_GAMMA_140_17F 0x0e0c +#define RADEON_OV0_GAMMA_180_1BF 0x0e10 +#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 +#define RADEON_OV0_GAMMA_200_23F 0x0e18 +#define RADEON_OV0_GAMMA_240_27F 0x0e1c +#define RADEON_OV0_GAMMA_280_2BF 0x0e20 +#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 +#define RADEON_OV0_GAMMA_300_33F 0x0e28 +#define RADEON_OV0_GAMMA_340_37F 0x0e2c +#define RADEON_OV0_GAMMA_380_3BF 0x0d50 +#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 +#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC +#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 +#define RADEON_OV0_H_INC 0x0480 +#define RADEON_OV0_KEY_CNTL 0x04F4 +# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L +# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L +# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L +# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L +# define RADEON_VIDEO_KEY_FN_NE 0x00000003L +# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L +# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L +# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L +# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L +# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L +# define RADEON_CMP_MIX_MASK 0x00000100L +# define RADEON_CMP_MIX_OR 0x00000000L +# define RADEON_CMP_MIX_AND 0x00000100L +#define RADEON_OV0_LIN_TRANS_A 0x0d20 +#define RADEON_OV0_LIN_TRANS_B 0x0d24 +#define RADEON_OV0_LIN_TRANS_C 0x0d28 +#define RADEON_OV0_LIN_TRANS_D 0x0d2c +#define RADEON_OV0_LIN_TRANS_E 0x0d30 +#define RADEON_OV0_LIN_TRANS_F 0x0d34 +#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L +#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 +#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 +# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define RADEON_OV0_P1_X_START_END 0x0494 +#define RADEON_OV0_P2_X_START_END 0x0498 +#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L +#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C +#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C +#define RADEON_OV0_P3_X_START_END 0x049C +#define RADEON_OV0_REG_LOAD_CNTL 0x0410 +# define RADEON_REG_LD_CTL_LOCK 0x00000001L +# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L +# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L +#define RADEON_OV0_SCALE_CNTL 0x0420 +# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L +# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L +# define RADEON_SCALER_SIGNED_UV 0x00000010L +# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L +# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L +# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L +# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L +# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L +# define RADEON_SCALER_SOURCE_15BPP 0x00000300L +# define RADEON_SCALER_SOURCE_16BPP 0x00000400L +# define RADEON_SCALER_SOURCE_32BPP 0x00000600L +# define RADEON_SCALER_SOURCE_YUV9 0x00000900L +# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L +# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L +# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L +# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L +# define RADEON_SCALER_CRTC_SEL 0x00004000L +# define RADEON_SCALER_SMART_SWITCH 0x00008000L +# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L +# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L +# define RADEON_SCALER_DIS_LIMIT 0x08000000L +# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L +# define RADEON_SCALER_INT_EMU 0x20000000L +# define RADEON_SCALER_ENABLE 0x40000000L +# define RADEON_SCALER_SOFT_RESET 0x80000000L +#define RADEON_OV0_STEP_BY 0x0484 +#define RADEON_OV0_TEST 0x04F8 +#define RADEON_OV0_V_INC 0x0424 +#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 +# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 +# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 +# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C +#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 +#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 +#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 +#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 +#define RADEON_OV0_Y_X_START 0x0400 +#define RADEON_OV0_Y_X_END 0x0404 +#define RADEON_OV1_Y_X_START 0x0600 +#define RADEON_OV1_Y_X_END 0x0604 +#define RADEON_OVR_CLR 0x0230 +#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 +#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 + +/* first capture unit */ + +#define RADEON_CAP0_BUF0_OFFSET 0x0920 +#define RADEON_CAP0_BUF1_OFFSET 0x0924 +#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 +#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C + +#define RADEON_CAP0_BUF_PITCH 0x0930 +#define RADEON_CAP0_V_WINDOW 0x0934 +#define RADEON_CAP0_H_WINDOW 0x0938 +#define RADEON_CAP0_VBI0_OFFSET 0x093C +#define RADEON_CAP0_VBI1_OFFSET 0x0940 +#define RADEON_CAP0_VBI_V_WINDOW 0x0944 +#define RADEON_CAP0_VBI_H_WINDOW 0x0948 +#define RADEON_CAP0_PORT_MODE_CNTL 0x094C +#define RADEON_CAP0_TRIG_CNTL 0x0950 +#define RADEON_CAP0_DEBUG 0x0954 +#define RADEON_CAP0_CONFIG 0x0958 +# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 +# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 +# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 +# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 +# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 +# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C +#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 +#define RADEON_CAP0_ANC_H_WINDOW 0x0964 +#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 +#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C +#define RADEON_CAP0_BUF_STATUS 0x0970 +/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ +/* #define RADEON_CAP0_XSHARPNESS 0x097C */ +#define RADEON_CAP0_VBI2_OFFSET 0x0980 +#define RADEON_CAP0_VBI3_OFFSET 0x0984 +#define RADEON_CAP0_ANC2_OFFSET 0x0988 +#define RADEON_CAP0_ANC3_OFFSET 0x098C +#define RADEON_VID_BUFFER_CONTROL 0x0900 + +/* second capture unit */ + +#define RADEON_CAP1_BUF0_OFFSET 0x0990 +#define RADEON_CAP1_BUF1_OFFSET 0x0994 +#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 +#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C + +#define RADEON_CAP1_BUF_PITCH 0x09A0 +#define RADEON_CAP1_V_WINDOW 0x09A4 +#define RADEON_CAP1_H_WINDOW 0x09A8 +#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC +#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 +#define RADEON_CAP1_VBI_V_WINDOW 0x09B4 +#define RADEON_CAP1_VBI_H_WINDOW 0x09B8 +#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC +#define RADEON_CAP1_TRIG_CNTL 0x09C0 +#define RADEON_CAP1_DEBUG 0x09C4 +#define RADEON_CAP1_CONFIG 0x09C8 +#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC +#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 +#define RADEON_CAP1_ANC_H_WINDOW 0x09D4 +#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 +#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define RADEON_CAP1_BUF_STATUS 0x09E0 +#define RADEON_CAP1_DWNSC_XRATIO 0x09E8 +#define RADEON_CAP1_XSHARPNESS 0x09EC + +/* misc multimedia registers */ + +#define RADEON_IDCT_RUNS 0x1F80 +#define RADEON_IDCT_LEVELS 0x1F84 +#define RADEON_IDCT_CONTROL 0x1FBC +#define RADEON_IDCT_AUTH_CONTROL 0x1F88 +#define RADEON_IDCT_AUTH 0x1F8C + +#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ +# define RADEON_P2PLL_RESET (1 << 0) +# define RADEON_P2PLL_SLEEP (1 << 1) +# define RADEON_P2PLL_PVG_MASK (7 << 11) +# define RADEON_P2PLL_PVG_SHIFT 11 +# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_P2PLL_DIV_0 0x002c +# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff +# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 +#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ +# define RADEON_P2PLL_REF_DIV_MASK 0x03ff +# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +# define R300_PPLL_REF_DIV_ACC_SHIFT 18 +#define RADEON_PALETTE_DATA 0x00b4 +#define RADEON_PALETTE_30_DATA 0x00b8 +#define RADEON_PALETTE_INDEX 0x00b0 +#define RADEON_PCI_GART_PAGE 0x017c +#define RADEON_PIXCLKS_CNTL 0x002d +# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 +# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) +# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) +# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) +# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +# define R300_DVOCLK_ALWAYS_ONb (1 << 10) +# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) +# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) +# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) +# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) +# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) +#define RADEON_PLANE_3D_MASK_C 0x1d44 +#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ +# define RADEON_PLL_MASK_READ_B (1 << 9) +#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ +#define RADEON_PMI_DATA 0x0f63 /* PCI */ +#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ +#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ +#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ +#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ +#define RADEON_PPLL_CNTL 0x0002 /* PLL */ +# define RADEON_PPLL_RESET (1 << 0) +# define RADEON_PPLL_SLEEP (1 << 1) +# define RADEON_PPLL_PVG_MASK (7 << 11) +# define RADEON_PPLL_PVG_SHIFT 11 +# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ +#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ +#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ +#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ +# define RADEON_PPLL_FB3_DIV_MASK 0x07ff +# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 +#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ +# define RADEON_PPLL_REF_DIV_MASK 0x03ff +# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ + +#define RADEON_RBBM_GUICNTL 0x172c +# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) +# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) +# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) +# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) +#define RADEON_RBBM_SOFT_RESET 0x00f0 +# define RADEON_SOFT_RESET_CP (1 << 0) +# define RADEON_SOFT_RESET_HI (1 << 1) +# define RADEON_SOFT_RESET_SE (1 << 2) +# define RADEON_SOFT_RESET_RE (1 << 3) +# define RADEON_SOFT_RESET_PP (1 << 4) +# define RADEON_SOFT_RESET_E2 (1 << 5) +# define RADEON_SOFT_RESET_RB (1 << 6) +# define RADEON_SOFT_RESET_HDP (1 << 7) +#define RADEON_RBBM_STATUS 0x0e40 +# define RADEON_RBBM_FIFOCNT_MASK 0x007f +# define RADEON_RBBM_ACTIVE (1 << 31) +#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c +# define RADEON_RB2D_DC_FLUSH (3 << 0) +# define RADEON_RB2D_DC_FREE (3 << 2) +# define RADEON_RB2D_DC_FLUSH_ALL 0xf +# define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB2D_DSTCACHE_MODE 0x3428 +#define RADEON_DSTCACHE_CTLSTAT 0x1714 + +#define RADEON_RB3D_ZCACHE_MODE 0x3250 +#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 +# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 +#define RADEON_RB3D_DSTCACHE_MODE 0x3258 +# define RADEON_RB3D_DC_CACHE_ENABLE (0) +# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) +# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) +# define RADEON_RB3D_DC_CACHE_DISABLE (3) +# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) +# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) +# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) +# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) +# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) +# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) +# define RADEON_RB3D_DC_FORCE_RMW (1 << 16) +# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) +# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) + +#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C +# define RADEON_RB3D_DC_FLUSH (3 << 0) +# define RADEON_RB3D_DC_FREE (3 << 2) +# define RADEON_RB3D_DC_FLUSH_ALL 0xf +# define RADEON_RB3D_DC_BUSY (1 << 31) + +#define RADEON_REG_BASE 0x0f18 /* PCI */ +#define RADEON_REGPROG_INF 0x0f09 /* PCI */ +#define RADEON_REVISION_ID 0x0f08 /* PCI */ + +#define RADEON_SC_BOTTOM 0x164c +#define RADEON_SC_BOTTOM_RIGHT 0x16f0 +#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c +#define RADEON_SC_LEFT 0x1640 +#define RADEON_SC_RIGHT 0x1644 +#define RADEON_SC_TOP 0x1648 +#define RADEON_SC_TOP_LEFT 0x16ec +#define RADEON_SC_TOP_LEFT_C 0x1c88 +# define RADEON_SC_SIGN_MASK_LO 0x8000 +# define RADEON_SC_SIGN_MASK_HI 0x80000000 +#define RADEON_SCLK_CNTL 0x000d /* PLL */ +# define RADEON_SCLK_SRC_SEL_MASK 0x0007 +# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 +# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 +# define RADEON_SCLK_FORCEON_MASK 0xffff8000 +# define RADEON_SCLK_FORCE_DISP2 (1<<15) +# define RADEON_SCLK_FORCE_CP (1<<16) +# define RADEON_SCLK_FORCE_HDP (1<<17) +# define RADEON_SCLK_FORCE_DISP1 (1<<18) +# define RADEON_SCLK_FORCE_TOP (1<<19) +# define RADEON_SCLK_FORCE_E2 (1<<20) +# define RADEON_SCLK_FORCE_SE (1<<21) +# define RADEON_SCLK_FORCE_IDCT (1<<22) +# define RADEON_SCLK_FORCE_VIP (1<<23) +# define RADEON_SCLK_FORCE_RE (1<<24) +# define RADEON_SCLK_FORCE_PB (1<<25) +# define RADEON_SCLK_FORCE_TAM (1<<26) +# define RADEON_SCLK_FORCE_TDM (1<<27) +# define RADEON_SCLK_FORCE_RB (1<<28) +# define RADEON_SCLK_FORCE_TV_SCLK (1<<29) +# define RADEON_SCLK_FORCE_SUBPIC (1<<30) +# define RADEON_SCLK_FORCE_OV0 (1<<31) +# define R300_SCLK_FORCE_VAP (1<<21) +# define R300_SCLK_FORCE_SR (1<<25) +# define R300_SCLK_FORCE_PX (1<<26) +# define R300_SCLK_FORCE_TX (1<<27) +# define R300_SCLK_FORCE_US (1<<28) +# define R300_SCLK_FORCE_SU (1<<30) +#define R300_SCLK_CNTL2 0x1e /* PLL */ +# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) +# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) +# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) +# define R300_SCLK_FORCE_TCL (1<<13) +# define R300_SCLK_FORCE_CBA (1<<14) +# define R300_SCLK_FORCE_GA (1<<15) +#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ +# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 +# define RADEON_SCLK_MORE_FORCEON 0x0700 +#define RADEON_SDRAM_MODE_REG 0x0158 +#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ +#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ +#define RADEON_SNAPSHOT_F_COUNT 0x0244 +#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 +#define RADEON_SNAPSHOT_VIF_COUNT 0x024c +#define RADEON_SRC_OFFSET 0x15ac +#define RADEON_SRC_PITCH 0x15b0 +#define RADEON_SRC_PITCH_OFFSET 0x1428 +#define RADEON_SRC_SC_BOTTOM 0x165c +#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 +#define RADEON_SRC_SC_RIGHT 0x1654 +#define RADEON_SRC_X 0x1414 +#define RADEON_SRC_X_Y 0x1590 +#define RADEON_SRC_Y 0x1418 +#define RADEON_SRC_Y_X 0x1434 +#define RADEON_STATUS 0x0f06 /* PCI */ +#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ +#define RADEON_SUB_CLASS 0x0f0a /* PCI */ +#define RADEON_SURFACE_CNTL 0x0b00 +# define RADEON_SURF_TRANSLATION_DIS (1 << 8) +# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) +# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) +# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) +# define R200_SURF_TILE_NONE (0 << 16) +# define R200_SURF_TILE_COLOR_MACRO (1 << 16) +# define R200_SURF_TILE_COLOR_MICRO (2 << 16) +# define R200_SURF_TILE_COLOR_BOTH (3 << 16) +# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +# define R300_SURF_TILE_NONE (0 << 16) +# define R300_SURF_TILE_COLOR_MACRO (1 << 16) +# define R300_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 +#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 +#define RADEON_SURFACE1_INFO 0x0b1c +#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 +#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 +#define RADEON_SURFACE2_INFO 0x0b2c +#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 +#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 +#define RADEON_SURFACE3_INFO 0x0b3c +#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 +#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 +#define RADEON_SURFACE4_INFO 0x0b4c +#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 +#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 +#define RADEON_SURFACE5_INFO 0x0b5c +#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 +#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 +#define RADEON_SURFACE6_INFO 0x0b6c +#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 +#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 +#define RADEON_SURFACE7_INFO 0x0b7c +#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 +#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 +#define RADEON_SW_SEMAPHORE 0x013c + +#define RADEON_TEST_DEBUG_CNTL 0x0120 +#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RADEON_TEST_DEBUG_MUX 0x0124 +#define RADEON_TEST_DEBUG_OUT 0x012c +#define RADEON_TMDS_PLL_CNTL 0x02a8 +#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 +# define RADEON_TMDS_TRANSMITTER_PLLEN 1 +# define RADEON_TMDS_TRANSMITTER_PLLRST 2 +#define RADEON_TRAIL_BRES_DEC 0x1614 +#define RADEON_TRAIL_BRES_ERR 0x160c +#define RADEON_TRAIL_BRES_INC 0x1610 +#define RADEON_TRAIL_X 0x1618 +#define RADEON_TRAIL_X_SUB 0x1620 + +#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ +# define RADEON_VCLK_SRC_SEL_MASK 0x03 +# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 +# define RADEON_PIXCLK_ALWAYS_ONb (1<<6) +# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) +# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + +#define RADEON_VENDOR_ID 0x0f00 /* PCI */ +#define RADEON_VGA_DDA_CONFIG 0x02e8 +#define RADEON_VGA_DDA_ON_OFF 0x02ec +#define RADEON_VID_BUFFER_CONTROL 0x0900 +#define RADEON_VIDEOMUX_CNTL 0x0190 + + /* VIP bus */ +#define RADEON_VIPH_CH0_DATA 0x0c00 +#define RADEON_VIPH_CH1_DATA 0x0c04 +#define RADEON_VIPH_CH2_DATA 0x0c08 +#define RADEON_VIPH_CH3_DATA 0x0c0c +#define RADEON_VIPH_CH0_ADDR 0x0c10 +#define RADEON_VIPH_CH1_ADDR 0x0c14 +#define RADEON_VIPH_CH2_ADDR 0x0c18 +#define RADEON_VIPH_CH3_ADDR 0x0c1c +#define RADEON_VIPH_CH0_SBCNT 0x0c20 +#define RADEON_VIPH_CH1_SBCNT 0x0c24 +#define RADEON_VIPH_CH2_SBCNT 0x0c28 +#define RADEON_VIPH_CH3_SBCNT 0x0c2c +#define RADEON_VIPH_CH0_ABCNT 0x0c30 +#define RADEON_VIPH_CH1_ABCNT 0x0c34 +#define RADEON_VIPH_CH2_ABCNT 0x0c38 +#define RADEON_VIPH_CH3_ABCNT 0x0c3c +#define RADEON_VIPH_CONTROL 0x0c40 +# define RADEON_VIP_BUSY 0 +# define RADEON_VIP_IDLE 1 +# define RADEON_VIP_RESET 2 +# define RADEON_VIPH_EN (1 << 21) +#define RADEON_VIPH_DV_LAT 0x0c44 +#define RADEON_VIPH_BM_CHUNK 0x0c48 +#define RADEON_VIPH_DV_INT 0x0c4c +#define RADEON_VIPH_TIMEOUT_STAT 0x0c50 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 + +#define RADEON_VIPH_REG_DATA 0x0084 +#define RADEON_VIPH_REG_ADDR 0x0080 + + +#define RADEON_WAIT_UNTIL 0x1720 +# define RADEON_WAIT_CRTC_PFLIP (1 << 0) +# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) +# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) +# define RADEON_WAIT_CRTC_VLINE (1 << 3) +# define RADEON_WAIT_DMA_VID_IDLE (1 << 8) +# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) +# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ +# define RADEON_WAIT_OV0_FLIP (1 << 11) +# define RADEON_WAIT_AGP_FLUSH (1 << 13) +# define RADEON_WAIT_2D_IDLE (1 << 14) +# define RADEON_WAIT_3D_IDLE (1 << 15) +# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) +# define RADEON_CMDFIFO_ENTRIES_SHIFT 10 +# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f +# define RADEON_WAIT_VAP_IDLE (1 << 28) +# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) +# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) +# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) + +#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ +#define RADEON_XCLK_CNTL 0x000d /* PLL */ +#define RADEON_XDLL_CNTL 0x000c /* PLL */ +#define RADEON_XPLL_CNTL 0x000b /* PLL */ + + + + /* Registers for 3D/TCL */ +#define RADEON_PP_BORDER_COLOR_0 0x1d40 +#define RADEON_PP_BORDER_COLOR_1 0x1d44 +#define RADEON_PP_BORDER_COLOR_2 0x1d48 +#define RADEON_PP_CNTL 0x1c38 +# define RADEON_STIPPLE_ENABLE (1 << 0) +# define RADEON_SCISSOR_ENABLE (1 << 1) +# define RADEON_PATTERN_ENABLE (1 << 2) +# define RADEON_SHADOW_ENABLE (1 << 3) +# define RADEON_TEX_ENABLE_MASK (0xf << 4) +# define RADEON_TEX_0_ENABLE (1 << 4) +# define RADEON_TEX_1_ENABLE (1 << 5) +# define RADEON_TEX_2_ENABLE (1 << 6) +# define RADEON_TEX_3_ENABLE (1 << 7) +# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) +# define RADEON_TEX_BLEND_0_ENABLE (1 << 12) +# define RADEON_TEX_BLEND_1_ENABLE (1 << 13) +# define RADEON_TEX_BLEND_2_ENABLE (1 << 14) +# define RADEON_TEX_BLEND_3_ENABLE (1 << 15) +# define RADEON_PLANAR_YUV_ENABLE (1 << 20) +# define RADEON_SPECULAR_ENABLE (1 << 21) +# define RADEON_FOG_ENABLE (1 << 22) +# define RADEON_ALPHA_TEST_ENABLE (1 << 23) +# define RADEON_ANTI_ALIAS_NONE (0 << 24) +# define RADEON_ANTI_ALIAS_LINE (1 << 24) +# define RADEON_ANTI_ALIAS_POLY (2 << 24) +# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) +# define RADEON_BUMP_MAP_ENABLE (1 << 26) +# define RADEON_BUMPED_MAP_T0 (0 << 27) +# define RADEON_BUMPED_MAP_T1 (1 << 27) +# define RADEON_BUMPED_MAP_T2 (2 << 27) +# define RADEON_TEX_3D_ENABLE_0 (1 << 29) +# define RADEON_TEX_3D_ENABLE_1 (1 << 30) +# define RADEON_MC_ENABLE (1 << 31) +#define RADEON_PP_FOG_COLOR 0x1c18 +# define RADEON_FOG_COLOR_MASK 0x00ffffff +# define RADEON_FOG_VERTEX (0 << 24) +# define RADEON_FOG_TABLE (1 << 24) +# define RADEON_FOG_USE_DEPTH (0 << 25) +# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) +# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +# define RADEON_REF_ALPHA_MASK 0x000000ff +# define RADEON_ALPHA_TEST_FAIL (0 << 8) +# define RADEON_ALPHA_TEST_LESS (1 << 8) +# define RADEON_ALPHA_TEST_LEQUAL (2 << 8) +# define RADEON_ALPHA_TEST_EQUAL (3 << 8) +# define RADEON_ALPHA_TEST_GEQUAL (4 << 8) +# define RADEON_ALPHA_TEST_GREATER (5 << 8) +# define RADEON_ALPHA_TEST_NEQUAL (6 << 8) +# define RADEON_ALPHA_TEST_PASS (7 << 8) +# define RADEON_ALPHA_TEST_OP_MASK (7 << 8) +# define RADEON_CHROMA_FUNC_FAIL (0 << 16) +# define RADEON_CHROMA_FUNC_PASS (1 << 16) +# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) +# define RADEON_CHROMA_FUNC_EQUAL (3 << 16) +# define RADEON_CHROMA_KEY_NEAREST (0 << 18) +# define RADEON_CHROMA_KEY_ZERO (1 << 18) +# define RADEON_SHADOW_ID_AUTO_INC (1 << 20) +# define RADEON_SHADOW_FUNC_EQUAL (0 << 21) +# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) +# define RADEON_SHADOW_PASS_1 (0 << 22) +# define RADEON_SHADOW_PASS_2 (1 << 22) +# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) +# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) +#define RADEON_PP_ROT_MATRIX_0 0x1d58 +#define RADEON_PP_ROT_MATRIX_1 0x1d5c +#define RADEON_PP_TXFILTER_0 0x1c54 +#define RADEON_PP_TXFILTER_1 0x1c6c +#define RADEON_PP_TXFILTER_2 0x1c84 +# define RADEON_MAG_FILTER_NEAREST (0 << 0) +# define RADEON_MAG_FILTER_LINEAR (1 << 0) +# define RADEON_MAG_FILTER_MASK (1 << 0) +# define RADEON_MIN_FILTER_NEAREST (0 << 1) +# define RADEON_MIN_FILTER_LINEAR (1 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define RADEON_MIN_FILTER_MASK (15 << 1) +# define RADEON_MAX_ANISO_1_TO_1 (0 << 5) +# define RADEON_MAX_ANISO_2_TO_1 (1 << 5) +# define RADEON_MAX_ANISO_4_TO_1 (2 << 5) +# define RADEON_MAX_ANISO_8_TO_1 (3 << 5) +# define RADEON_MAX_ANISO_16_TO_1 (4 << 5) +# define RADEON_MAX_ANISO_MASK (7 << 5) +# define RADEON_LOD_BIAS_MASK (0xff << 8) +# define RADEON_LOD_BIAS_SHIFT 8 +# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define RADEON_MAX_MIP_LEVEL_SHIFT 16 +# define RADEON_YUV_TO_RGB (1 << 20) +# define RADEON_YUV_TEMPERATURE_COOL (0 << 21) +# define RADEON_YUV_TEMPERATURE_HOT (1 << 21) +# define RADEON_YUV_TEMPERATURE_MASK (1 << 21) +# define RADEON_WRAPEN_S (1 << 22) +# define RADEON_CLAMP_S_WRAP (0 << 23) +# define RADEON_CLAMP_S_MIRROR (1 << 23) +# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define RADEON_CLAMP_S_CLAMP_GL (6 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define RADEON_CLAMP_S_MASK (7 << 23) +# define RADEON_WRAPEN_T (1 << 26) +# define RADEON_CLAMP_T_WRAP (0 << 27) +# define RADEON_CLAMP_T_MIRROR (1 << 27) +# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define RADEON_CLAMP_T_CLAMP_GL (6 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define RADEON_CLAMP_T_MASK (7 << 27) +# define RADEON_BORDER_MODE_OGL (0 << 31) +# define RADEON_BORDER_MODE_D3D (1 << 31) +#define RADEON_PP_TXFORMAT_0 0x1c58 +#define RADEON_PP_TXFORMAT_1 0x1c70 +#define RADEON_PP_TXFORMAT_2 0x1c88 +# define RADEON_TXFORMAT_I8 (0 << 0) +# define RADEON_TXFORMAT_AI88 (1 << 0) +# define RADEON_TXFORMAT_RGB332 (2 << 0) +# define RADEON_TXFORMAT_ARGB1555 (3 << 0) +# define RADEON_TXFORMAT_RGB565 (4 << 0) +# define RADEON_TXFORMAT_ARGB4444 (5 << 0) +# define RADEON_TXFORMAT_ARGB8888 (6 << 0) +# define RADEON_TXFORMAT_RGBA8888 (7 << 0) +# define RADEON_TXFORMAT_Y8 (8 << 0) +# define RADEON_TXFORMAT_VYUY422 (10 << 0) +# define RADEON_TXFORMAT_YVYU422 (11 << 0) +# define RADEON_TXFORMAT_DXT1 (12 << 0) +# define RADEON_TXFORMAT_DXT23 (14 << 0) +# define RADEON_TXFORMAT_DXT45 (15 << 0) +# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) +# define RADEON_TXFORMAT_FORMAT_SHIFT 0 +# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) +# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define RADEON_TXFORMAT_NON_POWER2 (1 << 7) +# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) +# define RADEON_TXFORMAT_WIDTH_SHIFT 8 +# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) +# define RADEON_TXFORMAT_HEIGHT_SHIFT 12 +# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) +# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 +# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) +# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) +# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) +# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) +# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) +#define RADEON_PP_CUBIC_FACES_0 0x1d24 +#define RADEON_PP_CUBIC_FACES_1 0x1d28 +#define RADEON_PP_CUBIC_FACES_2 0x1d2c +# define RADEON_FACE_WIDTH_1_SHIFT 0 +# define RADEON_FACE_HEIGHT_1_SHIFT 4 +# define RADEON_FACE_WIDTH_1_MASK (0xf << 0) +# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) +# define RADEON_FACE_WIDTH_2_SHIFT 8 +# define RADEON_FACE_HEIGHT_2_SHIFT 12 +# define RADEON_FACE_WIDTH_2_MASK (0xf << 8) +# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) +# define RADEON_FACE_WIDTH_3_SHIFT 16 +# define RADEON_FACE_HEIGHT_3_SHIFT 20 +# define RADEON_FACE_WIDTH_3_MASK (0xf << 16) +# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) +# define RADEON_FACE_WIDTH_4_SHIFT 24 +# define RADEON_FACE_HEIGHT_4_SHIFT 28 +# define RADEON_FACE_WIDTH_4_MASK (0xf << 24) +# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) + +#define RADEON_PP_TXOFFSET_0 0x1c5c +#define RADEON_PP_TXOFFSET_1 0x1c74 +#define RADEON_PP_TXOFFSET_2 0x1c8c +# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) +# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define RADEON_TXO_MACRO_LINEAR (0 << 2) +# define RADEON_TXO_MACRO_TILE (1 << 2) +# define RADEON_TXO_MICRO_LINEAR (0 << 3) +# define RADEON_TXO_MICRO_TILE_X2 (1 << 3) +# define RADEON_TXO_MICRO_TILE_OPT (2 << 3) +# define RADEON_TXO_OFFSET_MASK 0xffffffe0 +# define RADEON_TXO_OFFSET_SHIFT 5 + +#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 +#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 +#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc +#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 +#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 +#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 +#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 +#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c +#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 +#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 +#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 +#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c +#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 +#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 + +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_1 0x1d0c +#define RADEON_PP_TEX_SIZE_2 0x1d14 +# define RADEON_TEX_USIZE_MASK (0x7ff << 0) +# define RADEON_TEX_USIZE_SHIFT 0 +# define RADEON_TEX_VSIZE_MASK (0x7ff << 16) +# define RADEON_TEX_VSIZE_SHIFT 16 +# define RADEON_SIGNED_RGB_MASK (1 << 30) +# define RADEON_SIGNED_RGB_SHIFT 30 +# define RADEON_SIGNED_ALPHA_MASK (1 << 31) +# define RADEON_SIGNED_ALPHA_SHIFT 31 +#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ +#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ +#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ +/* note: bits 13-5: 32 byte aligned stride of texture map */ + +#define RADEON_PP_TXCBLEND_0 0x1c60 +#define RADEON_PP_TXCBLEND_1 0x1c78 +#define RADEON_PP_TXCBLEND_2 0x1c90 +# define RADEON_COLOR_ARG_A_SHIFT 0 +# define RADEON_COLOR_ARG_A_MASK (0x1f << 0) +# define RADEON_COLOR_ARG_A_ZERO (0 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) +# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) +# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) +# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) +# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) +# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) +# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) +# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) +# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) +# define RADEON_COLOR_ARG_B_SHIFT 5 +# define RADEON_COLOR_ARG_B_MASK (0x1f << 5) +# define RADEON_COLOR_ARG_B_ZERO (0 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) +# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) +# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) +# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) +# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) +# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) +# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) +# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) +# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) +# define RADEON_COLOR_ARG_C_SHIFT 10 +# define RADEON_COLOR_ARG_C_MASK (0x1f << 10) +# define RADEON_COLOR_ARG_C_ZERO (0 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) +# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) +# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) +# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) +# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) +# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) +# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) +# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) +# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) +# define RADEON_COMP_ARG_A (1 << 15) +# define RADEON_COMP_ARG_A_SHIFT 15 +# define RADEON_COMP_ARG_B (1 << 16) +# define RADEON_COMP_ARG_B_SHIFT 16 +# define RADEON_COMP_ARG_C (1 << 17) +# define RADEON_COMP_ARG_C_SHIFT 17 +# define RADEON_BLEND_CTL_MASK (7 << 18) +# define RADEON_BLEND_CTL_ADD (0 << 18) +# define RADEON_BLEND_CTL_SUBTRACT (1 << 18) +# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) +# define RADEON_BLEND_CTL_BLEND (3 << 18) +# define RADEON_BLEND_CTL_DOT3 (4 << 18) +# define RADEON_SCALE_SHIFT 21 +# define RADEON_SCALE_MASK (3 << 21) +# define RADEON_SCALE_1X (0 << 21) +# define RADEON_SCALE_2X (1 << 21) +# define RADEON_SCALE_4X (2 << 21) +# define RADEON_CLAMP_TX (1 << 23) +# define RADEON_T0_EQ_TCUR (1 << 24) +# define RADEON_T1_EQ_TCUR (1 << 25) +# define RADEON_T2_EQ_TCUR (1 << 26) +# define RADEON_T3_EQ_TCUR (1 << 27) +# define RADEON_COLOR_ARG_MASK 0x1f +# define RADEON_COMP_ARG_SHIFT 15 +#define RADEON_PP_TXABLEND_0 0x1c64 +#define RADEON_PP_TXABLEND_1 0x1c7c +#define RADEON_PP_TXABLEND_2 0x1c94 +# define RADEON_ALPHA_ARG_A_SHIFT 0 +# define RADEON_ALPHA_ARG_A_MASK (0xf << 0) +# define RADEON_ALPHA_ARG_A_ZERO (0 << 0) +# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) +# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) +# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) +# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) +# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) +# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) +# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) +# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) +# define RADEON_ALPHA_ARG_B_SHIFT 4 +# define RADEON_ALPHA_ARG_B_MASK (0xf << 4) +# define RADEON_ALPHA_ARG_B_ZERO (0 << 4) +# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) +# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) +# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) +# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) +# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) +# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) +# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) +# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) +# define RADEON_ALPHA_ARG_C_SHIFT 8 +# define RADEON_ALPHA_ARG_C_MASK (0xf << 8) +# define RADEON_ALPHA_ARG_C_ZERO (0 << 8) +# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) +# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) +# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) +# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) +# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) +# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) +# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) +# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) +# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) +# define RADEON_ALPHA_ARG_MASK 0xf + +#define RADEON_PP_TFACTOR_0 0x1c68 +#define RADEON_PP_TFACTOR_1 0x1c80 +#define RADEON_PP_TFACTOR_2 0x1c98 + +#define RADEON_RB3D_BLENDCNTL 0x1c20 +# define RADEON_COMB_FCN_MASK (3 << 12) +# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) +# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) +# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) +# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) +# define RADEON_SRC_BLEND_GL_ZERO (32 << 16) +# define RADEON_SRC_BLEND_GL_ONE (33 << 16) +# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) +# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) +# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) +# define RADEON_SRC_BLEND_MASK (63 << 16) +# define RADEON_DST_BLEND_GL_ZERO (32 << 24) +# define RADEON_DST_BLEND_GL_ONE (33 << 24) +# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) +# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) +# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) +# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) +# define RADEON_DST_BLEND_MASK (63 << 24) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_DITHER_ENABLE (1 << 2) +# define RADEON_ROUND_ENABLE (1 << 3) +# define RADEON_SCALE_DITHER_ENABLE (1 << 4) +# define RADEON_DITHER_INIT (1 << 5) +# define RADEON_ROP_ENABLE (1 << 6) +# define RADEON_STENCIL_ENABLE (1 << 7) +# define RADEON_Z_ENABLE (1 << 8) +# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) +# define RADEON_COLOR_FORMAT_RGB565 (4 << 10) +# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) +# define RADEON_COLOR_FORMAT_RGB332 (7 << 10) +# define RADEON_COLOR_FORMAT_Y8 (8 << 10) +# define RADEON_COLOR_FORMAT_RGB8 (9 << 10) +# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) +# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) +# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) +# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) +# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) +#define RADEON_RB3D_COLOROFFSET 0x1c40 +# define RADEON_COLOROFFSET_MASK 0xfffffff0 +#define RADEON_RB3D_COLORPITCH 0x1c48 +# define RADEON_COLORPITCH_MASK 0x000001ff8 +# define RADEON_COLOR_TILE_ENABLE (1 << 16) +# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) +# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_DEPTHPITCH 0x1c28 +# define RADEON_DEPTHPITCH_MASK 0x00001ff8 +# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_ROPCNTL 0x1d80 +# define RADEON_ROP_MASK (15 << 8) +# define RADEON_ROP_CLEAR (0 << 8) +# define RADEON_ROP_NOR (1 << 8) +# define RADEON_ROP_AND_INVERTED (2 << 8) +# define RADEON_ROP_COPY_INVERTED (3 << 8) +# define RADEON_ROP_AND_REVERSE (4 << 8) +# define RADEON_ROP_INVERT (5 << 8) +# define RADEON_ROP_XOR (6 << 8) +# define RADEON_ROP_NAND (7 << 8) +# define RADEON_ROP_AND (8 << 8) +# define RADEON_ROP_EQUIV (9 << 8) +# define RADEON_ROP_NOOP (10 << 8) +# define RADEON_ROP_OR_INVERTED (11 << 8) +# define RADEON_ROP_COPY (12 << 8) +# define RADEON_ROP_OR_REVERSE (13 << 8) +# define RADEON_ROP_OR (14 << 8) +# define RADEON_ROP_SET (15 << 8) +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +# define RADEON_STENCIL_REF_SHIFT 0 +# define RADEON_STENCIL_REF_MASK (0xff << 0) +# define RADEON_STENCIL_MASK_SHIFT 16 +# define RADEON_STENCIL_VALUE_MASK (0xff << 16) +# define RADEON_STENCIL_WRITEMASK_SHIFT 24 +# define RADEON_STENCIL_WRITE_MASK (0xff << 24) +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_DEPTH_FORMAT_MASK (0xf << 0) +# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) +# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) +# define RADEON_Z_TEST_NEVER (0 << 4) +# define RADEON_Z_TEST_LESS (1 << 4) +# define RADEON_Z_TEST_LEQUAL (2 << 4) +# define RADEON_Z_TEST_EQUAL (3 << 4) +# define RADEON_Z_TEST_GEQUAL (4 << 4) +# define RADEON_Z_TEST_GREATER (5 << 4) +# define RADEON_Z_TEST_NEQUAL (6 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_STENCIL_TEST_NEVER (0 << 12) +# define RADEON_STENCIL_TEST_LESS (1 << 12) +# define RADEON_STENCIL_TEST_LEQUAL (2 << 12) +# define RADEON_STENCIL_TEST_EQUAL (3 << 12) +# define RADEON_STENCIL_TEST_GEQUAL (4 << 12) +# define RADEON_STENCIL_TEST_GREATER (5 << 12) +# define RADEON_STENCIL_TEST_NEQUAL (6 << 12) +# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) +# define RADEON_STENCIL_TEST_MASK (0x7 << 12) +# define RADEON_STENCIL_FAIL_KEEP (0 << 16) +# define RADEON_STENCIL_FAIL_ZERO (1 << 16) +# define RADEON_STENCIL_FAIL_REPLACE (2 << 16) +# define RADEON_STENCIL_FAIL_INC (3 << 16) +# define RADEON_STENCIL_FAIL_DEC (4 << 16) +# define RADEON_STENCIL_FAIL_INVERT (5 << 16) +# define RADEON_STENCIL_FAIL_MASK (0x7 << 16) +# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) +# define RADEON_STENCIL_ZPASS_ZERO (1 << 20) +# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) +# define RADEON_STENCIL_ZPASS_INC (3 << 20) +# define RADEON_STENCIL_ZPASS_DEC (4 << 20) +# define RADEON_STENCIL_ZPASS_INVERT (5 << 20) +# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) +# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) +# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) +# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) +# define RADEON_STENCIL_ZFAIL_INC (3 << 24) +# define RADEON_STENCIL_ZFAIL_DEC (4 << 24) +# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) +# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) +# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) +# define RADEON_FORCE_Z_DIRTY (1 << 29) +# define RADEON_Z_WRITE_ENABLE (1 << 30) +#define RADEON_RE_LINE_PATTERN 0x1cd0 +# define RADEON_LINE_PATTERN_MASK 0x0000ffff +# define RADEON_LINE_REPEAT_COUNT_SHIFT 16 +# define RADEON_LINE_PATTERN_START_SHIFT 24 +# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) +# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) +# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) +#define RADEON_RE_LINE_STATE 0x1cd4 +# define RADEON_LINE_CURRENT_PTR_SHIFT 0 +# define RADEON_LINE_CURRENT_COUNT_SHIFT 8 +#define RADEON_RE_MISC 0x26c4 +# define RADEON_STIPPLE_COORD_MASK 0x1f +# define RADEON_STIPPLE_X_OFFSET_SHIFT 0 +# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) +# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 +# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) +# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) +# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) +#define RADEON_RE_SOLID_COLOR 0x1c1c +#define RADEON_RE_TOP_LEFT 0x26c0 +# define RADEON_RE_LEFT_SHIFT 0 +# define RADEON_RE_TOP_SHIFT 16 +#define RADEON_RE_WIDTH_HEIGHT 0x1c44 +# define RADEON_RE_WIDTH_SHIFT 0 +# define RADEON_RE_HEIGHT_SHIFT 16 + +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_FFACE_CULL_CW (0 << 0) +# define RADEON_FFACE_CULL_CCW (1 << 0) +# define RADEON_FFACE_CULL_DIR_MASK (1 << 0) +# define RADEON_BFACE_CULL (0 << 1) +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_FFACE_CULL (0 << 3) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FFACE_CULL_MASK (3 << 3) +# define RADEON_BADVTX_CULL_DISABLE (1 << 5) +# define RADEON_FLAT_SHADE_VTX_0 (0 << 6) +# define RADEON_FLAT_SHADE_VTX_1 (1 << 6) +# define RADEON_FLAT_SHADE_VTX_2 (2 << 6) +# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) +# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) +# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) +# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) +# define RADEON_DIFFUSE_SHADE_MASK (3 << 8) +# define RADEON_ALPHA_SHADE_SOLID (0 << 10) +# define RADEON_ALPHA_SHADE_FLAT (1 << 10) +# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) +# define RADEON_ALPHA_SHADE_MASK (3 << 10) +# define RADEON_SPECULAR_SHADE_SOLID (0 << 12) +# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) +# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) +# define RADEON_SPECULAR_SHADE_MASK (3 << 12) +# define RADEON_FOG_SHADE_SOLID (0 << 14) +# define RADEON_FOG_SHADE_FLAT (1 << 14) +# define RADEON_FOG_SHADE_GOURAUD (2 << 14) +# define RADEON_FOG_SHADE_MASK (3 << 14) +# define RADEON_ZBIAS_ENABLE_POINT (1 << 16) +# define RADEON_ZBIAS_ENABLE_LINE (1 << 17) +# define RADEON_ZBIAS_ENABLE_TRI (1 << 18) +# define RADEON_WIDELINE_ENABLE (1 << 20) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +# define RADEON_VTX_PIX_CENTER_D3D (0 << 27) +# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) +# define RADEON_ROUND_MODE_TRUNC (0 << 28) +# define RADEON_ROUND_MODE_ROUND (1 << 28) +# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) +# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) +# define RADEON_ROUND_PREC_16TH_PIX (0 << 30) +# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) +# define RADEON_ROUND_PREC_4TH_PIX (2 << 30) +# define RADEON_ROUND_PREC_HALF_PIX (3 << 30) +#define R200_RE_CNTL 0x1c50 +# define R200_STIPPLE_ENABLE 0x1 +# define R200_SCISSOR_ENABLE 0x2 +# define R200_PATTERN_ENABLE 0x4 +# define R200_PERSPECTIVE_ENABLE 0x8 +# define R200_POINT_SMOOTH 0x20 +# define R200_VTX_STQ0_D3D 0x00010000 +# define R200_VTX_STQ1_D3D 0x00040000 +# define R200_VTX_STQ2_D3D 0x00100000 +# define R200_VTX_STQ3_D3D 0x00400000 +# define R200_VTX_STQ4_D3D 0x01000000 +# define R200_VTX_STQ5_D3D 0x04000000 +#define R200_RE_SCISSOR_TL_0 0x1cd8 +#define R200_RE_SCISSOR_BR_0 0x1cdc +#define R200_RE_SCISSOR_TL_1 0x1ce0 +#define R200_RE_SCISSOR_BR_1 0x1ce4 +#define R200_RE_SCISSOR_TL_2 0x1ce8 +#define R200_RE_SCISSOR_BR_2 0x1cec +# define R200_SCISSOR_X_SHIFT 0 +# define R200_SCISSOR_Y_SHIFT 16 +#define RADEON_SE_CNTL_STATUS 0x2140 +# define RADEON_VC_NO_SWAP (0 << 0) +# define RADEON_VC_16BIT_SWAP (1 << 0) +# define RADEON_VC_32BIT_SWAP (2 << 0) +# define RADEON_VC_HALF_DWORD_SWAP (3 << 0) +# define RADEON_TCL_BYPASS (1 << 8) +#define RADEON_SE_COORD_FMT 0x1c50 +# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) +# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) +# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) +# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) +# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) +# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) +# define RADEON_VTX_W0_NORMALIZE (1 << 12) +# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) +# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) +# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) +# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) +# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) +# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) +# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c +# define RADEON_LIGHTING_ENABLE (1 << 0) +# define RADEON_LIGHT_IN_MODELSPACE (1 << 1) +# define RADEON_LOCAL_VIEWER (1 << 2) +# define RADEON_NORMALIZE_NORMALS (1 << 3) +# define RADEON_RESCALE_NORMALS (1 << 4) +# define RADEON_SPECULAR_LIGHTS (1 << 5) +# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) +# define RADEON_LIGHT_ALPHA (1 << 7) +# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) +# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) +# define RADEON_LM_SOURCE_STATE_PREMULT 0 +# define RADEON_LM_SOURCE_STATE_MULT 1 +# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 +# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 +# define RADEON_EMISSIVE_SOURCE_SHIFT 16 +# define RADEON_AMBIENT_SOURCE_SHIFT 18 +# define RADEON_DIFFUSE_SOURCE_SHIFT 20 +# define RADEON_SPECULAR_SOURCE_SHIFT 22 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c +#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c +#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c +# define RADEON_MODELVIEW_0_SHIFT 0 +# define RADEON_MODELVIEW_1_SHIFT 4 +# define RADEON_MODELVIEW_2_SHIFT 8 +# define RADEON_MODELVIEW_3_SHIFT 12 +# define RADEON_IT_MODELVIEW_0_SHIFT 16 +# define RADEON_IT_MODELVIEW_1_SHIFT 20 +# define RADEON_IT_MODELVIEW_2_SHIFT 24 +# define RADEON_IT_MODELVIEW_3_SHIFT 28 +#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 +# define RADEON_MODELPROJECT_0_SHIFT 0 +# define RADEON_MODELPROJECT_1_SHIFT 4 +# define RADEON_MODELPROJECT_2_SHIFT 8 +# define RADEON_MODELPROJECT_3_SHIFT 12 +# define RADEON_TEXMAT_0_SHIFT 16 +# define RADEON_TEXMAT_1_SHIFT 20 +# define RADEON_TEXMAT_2_SHIFT 24 +# define RADEON_TEXMAT_3_SHIFT 28 + + +#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 +# define RADEON_TCL_VTX_W0 (1 << 0) +# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) +# define RADEON_TCL_VTX_FP_ALPHA (1 << 2) +# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) +# define RADEON_TCL_VTX_FP_SPEC (1 << 4) +# define RADEON_TCL_VTX_FP_FOG (1 << 5) +# define RADEON_TCL_VTX_PK_SPEC (1 << 6) +# define RADEON_TCL_VTX_ST0 (1 << 7) +# define RADEON_TCL_VTX_ST1 (1 << 8) +# define RADEON_TCL_VTX_Q1 (1 << 9) +# define RADEON_TCL_VTX_ST2 (1 << 10) +# define RADEON_TCL_VTX_Q2 (1 << 11) +# define RADEON_TCL_VTX_ST3 (1 << 12) +# define RADEON_TCL_VTX_Q3 (1 << 13) +# define RADEON_TCL_VTX_Q0 (1 << 14) +# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 +# define RADEON_TCL_VTX_NORM0 (1 << 18) +# define RADEON_TCL_VTX_XY1 (1 << 27) +# define RADEON_TCL_VTX_Z1 (1 << 28) +# define RADEON_TCL_VTX_W1 (1 << 29) +# define RADEON_TCL_VTX_NORM1 (1 << 30) +# define RADEON_TCL_VTX_Z0 (1 << 31) + +#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 +# define RADEON_TCL_COMPUTE_XYZW (1 << 0) +# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) +# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) +# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) +# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) +# define RADEON_TCL_TEX_INPUT_TEX_0 0 +# define RADEON_TCL_TEX_INPUT_TEX_1 1 +# define RADEON_TCL_TEX_INPUT_TEX_2 2 +# define RADEON_TCL_TEX_INPUT_TEX_3 3 +# define RADEON_TCL_TEX_COMPUTED_TEX_0 8 +# define RADEON_TCL_TEX_COMPUTED_TEX_1 9 +# define RADEON_TCL_TEX_COMPUTED_TEX_2 10 +# define RADEON_TCL_TEX_COMPUTED_TEX_3 11 +# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 +# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 +# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 +# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 + +#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 +# define RADEON_LIGHT_0_ENABLE (1 << 0) +# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) +# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) +# define RADEON_LIGHT_0_IS_LOCAL (1 << 3) +# define RADEON_LIGHT_0_IS_SPOT (1 << 4) +# define RADEON_LIGHT_0_DUAL_CONE (1 << 5) +# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) +# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) +# define RADEON_LIGHT_0_SHIFT 0 +# define RADEON_LIGHT_1_ENABLE (1 << 16) +# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) +# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) +# define RADEON_LIGHT_1_IS_LOCAL (1 << 19) +# define RADEON_LIGHT_1_IS_SPOT (1 << 20) +# define RADEON_LIGHT_1_DUAL_CONE (1 << 21) +# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) +# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) +# define RADEON_LIGHT_1_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 +# define RADEON_LIGHT_2_SHIFT 0 +# define RADEON_LIGHT_3_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 +# define RADEON_LIGHT_4_SHIFT 0 +# define RADEON_LIGHT_5_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c +# define RADEON_LIGHT_6_SHIFT 0 +# define RADEON_LIGHT_7_SHIFT 16 + +#define RADEON_SE_TCL_SHININESS 0x2250 + +#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 +# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) +# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) +# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) +# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) +# define RADEON_TEXMAT_0_ENABLE (1 << 4) +# define RADEON_TEXMAT_1_ENABLE (1 << 5) +# define RADEON_TEXMAT_2_ENABLE (1 << 6) +# define RADEON_TEXMAT_3_ENABLE (1 << 7) +# define RADEON_TEXGEN_INPUT_MASK 0xf +# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 +# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 +# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 +# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 +# define RADEON_TEXGEN_INPUT_OBJ 4 +# define RADEON_TEXGEN_INPUT_EYE 5 +# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 +# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 +# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 +# define RADEON_TEXGEN_0_INPUT_SHIFT 16 +# define RADEON_TEXGEN_1_INPUT_SHIFT 20 +# define RADEON_TEXGEN_2_INPUT_SHIFT 24 +# define RADEON_TEXGEN_3_INPUT_SHIFT 28 + +#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 +# define RADEON_UCP_IN_CLIP_SPACE (1 << 0) +# define RADEON_UCP_IN_MODEL_SPACE (1 << 1) +# define RADEON_UCP_ENABLE_0 (1 << 2) +# define RADEON_UCP_ENABLE_1 (1 << 3) +# define RADEON_UCP_ENABLE_2 (1 << 4) +# define RADEON_UCP_ENABLE_3 (1 << 5) +# define RADEON_UCP_ENABLE_4 (1 << 6) +# define RADEON_UCP_ENABLE_5 (1 << 7) +# define RADEON_TCL_FOG_MASK (3 << 8) +# define RADEON_TCL_FOG_DISABLE (0 << 8) +# define RADEON_TCL_FOG_EXP (1 << 8) +# define RADEON_TCL_FOG_EXP2 (2 << 8) +# define RADEON_TCL_FOG_LINEAR (3 << 8) +# define RADEON_RNG_BASED_FOG (1 << 10) +# define RADEON_LIGHT_TWOSIDE (1 << 11) +# define RADEON_BLEND_OP_COUNT_MASK (7 << 12) +# define RADEON_BLEND_OP_COUNT_SHIFT 12 +# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) +# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) +# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) +# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) +# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) +# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) +# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) +# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) +# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) +# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) +# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) +# define RADEON_CULL_FRONT_IS_CW (0 << 28) +# define RADEON_CULL_FRONT_IS_CCW (1 << 28) +# define RADEON_CULL_FRONT (1 << 29) +# define RADEON_CULL_BACK (1 << 30) +# define RADEON_FORCE_W_TO_ONE (1 << 31) + +#define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SE_VPORT_XOFFSET 0x1d9c +#define RADEON_SE_VPORT_YSCALE 0x1da0 +#define RADEON_SE_VPORT_YOFFSET 0x1da4 +#define RADEON_SE_VPORT_ZSCALE 0x1da8 +#define RADEON_SE_VPORT_ZOFFSET 0x1dac +#define RADEON_SE_ZBIAS_FACTOR 0x1db0 +#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 + +#define RADEON_SE_VTX_FMT 0x2080 +# define RADEON_SE_VTX_FMT_XY 0x00000000 +# define RADEON_SE_VTX_FMT_W0 0x00000001 +# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 +# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 +# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 +# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 +# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 +# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 +# define RADEON_SE_VTX_FMT_ST0 0x00000080 +# define RADEON_SE_VTX_FMT_ST1 0x00000100 +# define RADEON_SE_VTX_FMT_Q1 0x00000200 +# define RADEON_SE_VTX_FMT_ST2 0x00000400 +# define RADEON_SE_VTX_FMT_Q2 0x00000800 +# define RADEON_SE_VTX_FMT_ST3 0x00001000 +# define RADEON_SE_VTX_FMT_Q3 0x00002000 +# define RADEON_SE_VTX_FMT_Q0 0x00004000 +# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +# define RADEON_SE_VTX_FMT_N0 0x00040000 +# define RADEON_SE_VTX_FMT_XY1 0x08000000 +# define RADEON_SE_VTX_FMT_Z1 0x10000000 +# define RADEON_SE_VTX_FMT_W1 0x20000000 +# define RADEON_SE_VTX_FMT_N1 0x40000000 +# define RADEON_SE_VTX_FMT_Z 0x80000000 + +#define RADEON_SE_VF_CNTL 0x2084 +# define RADEON_VF_PRIM_TYPE_POINT_LIST 1 +# define RADEON_VF_PRIM_TYPE_LINE_LIST 2 +# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 +# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 +# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 +# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 +# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 +# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 +# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 +# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 +# define RADEON_VF_PRIM_TYPE_POLYGON 15 +# define RADEON_VF_PRIM_WALK_STATE (0<<4) +# define RADEON_VF_PRIM_WALK_INDEX (1<<4) +# define RADEON_VF_PRIM_WALK_LIST (2<<4) +# define RADEON_VF_PRIM_WALK_DATA (3<<4) +# define RADEON_VF_COLOR_ORDER_RGBA (1<<6) +# define RADEON_VF_RADEON_MODE (1<<8) +# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) +# define RADEON_VF_PROG_STREAM_ENA (1<<10) +# define RADEON_VF_INDEX_SIZE_SHIFT 11 +# define RADEON_VF_NUM_VERTICES_SHIFT 16 + +#define RADEON_SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +# define R200_VAP_TCL_ENABLE 0x00000001 +# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 +# define R200_VAP_FORCE_W_TO_ONE 0x00010000 +# define R200_VAP_D3D_TEX_DEFAULT 0x00020000 +# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 +# define R200_VAP_VF_MAX_VTX_NUM (9 << 18) +# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +# define R200_VPORT_X_SCALE_ENA 0x00000001 +# define R200_VPORT_X_OFFSET_ENA 0x00000002 +# define R200_VPORT_Y_SCALE_ENA 0x00000004 +# define R200_VPORT_Y_OFFSET_ENA 0x00000008 +# define R200_VPORT_Z_SCALE_ENA 0x00000010 +# define R200_VPORT_Z_OFFSET_ENA 0x00000020 +# define R200_VTX_XY_FMT 0x00000100 +# define R200_VTX_Z_FMT 0x00000200 +# define R200_VTX_W0_FMT 0x00000400 +# define R200_VTX_W0_NORMALIZE 0x00000800 +# define R200_VTX_ST_DENORMALIZED 0x00001000 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +# define R200_VC_NO_SWAP (0 << 0) +# define R200_VC_16BIT_SWAP (1 << 0) +# define R200_VC_32BIT_SWAP (2 << 0) +#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 +# define R200_EXCLUSIVE_SCISSOR_0 0x01000000 +# define R200_EXCLUSIVE_SCISSOR_1 0x02000000 +# define R200_EXCLUSIVE_SCISSOR_2 0x04000000 +# define R200_SCISSOR_ENABLE_0 0x10000000 +# define R200_SCISSOR_ENABLE_1 0x20000000 +# define R200_SCISSOR_ENABLE_2 0x40000000 +#define R200_PP_TXFILTER_0 0x2c00 +#define R200_PP_TXFILTER_1 0x2c20 +#define R200_PP_TXFILTER_2 0x2c40 +#define R200_PP_TXFILTER_3 0x2c60 +#define R200_PP_TXFILTER_4 0x2c80 +#define R200_PP_TXFILTER_5 0x2ca0 +# define R200_MAG_FILTER_NEAREST (0 << 0) +# define R200_MAG_FILTER_LINEAR (1 << 0) +# define R200_MAG_FILTER_MASK (1 << 0) +# define R200_MIN_FILTER_NEAREST (0 << 1) +# define R200_MIN_FILTER_LINEAR (1 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define R200_MIN_FILTER_MASK (15 << 1) +# define R200_MAX_ANISO_1_TO_1 (0 << 5) +# define R200_MAX_ANISO_2_TO_1 (1 << 5) +# define R200_MAX_ANISO_4_TO_1 (2 << 5) +# define R200_MAX_ANISO_8_TO_1 (3 << 5) +# define R200_MAX_ANISO_16_TO_1 (4 << 5) +# define R200_MAX_ANISO_MASK (7 << 5) +# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define R200_MAX_MIP_LEVEL_SHIFT 16 +# define R200_YUV_TO_RGB (1 << 20) +# define R200_YUV_TEMPERATURE_COOL (0 << 21) +# define R200_YUV_TEMPERATURE_HOT (1 << 21) +# define R200_YUV_TEMPERATURE_MASK (1 << 21) +# define R200_WRAPEN_S (1 << 22) +# define R200_CLAMP_S_WRAP (0 << 23) +# define R200_CLAMP_S_MIRROR (1 << 23) +# define R200_CLAMP_S_CLAMP_LAST (2 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define R200_CLAMP_S_CLAMP_BORDER (4 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define R200_CLAMP_S_CLAMP_GL (6 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define R200_CLAMP_S_MASK (7 << 23) +# define R200_WRAPEN_T (1 << 26) +# define R200_CLAMP_T_WRAP (0 << 27) +# define R200_CLAMP_T_MIRROR (1 << 27) +# define R200_CLAMP_T_CLAMP_LAST (2 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define R200_CLAMP_T_CLAMP_BORDER (4 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define R200_CLAMP_T_CLAMP_GL (6 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define R200_CLAMP_T_MASK (7 << 27) +# define R200_KILL_LT_ZERO (1 << 30) +# define R200_BORDER_MODE_OGL (0 << 31) +# define R200_BORDER_MODE_D3D (1 << 31) +#define R200_PP_TXFORMAT_0 0x2c04 +#define R200_PP_TXFORMAT_1 0x2c24 +#define R200_PP_TXFORMAT_2 0x2c44 +#define R200_PP_TXFORMAT_3 0x2c64 +#define R200_PP_TXFORMAT_4 0x2c84 +#define R200_PP_TXFORMAT_5 0x2ca4 +# define R200_TXFORMAT_I8 (0 << 0) +# define R200_TXFORMAT_AI88 (1 << 0) +# define R200_TXFORMAT_RGB332 (2 << 0) +# define R200_TXFORMAT_ARGB1555 (3 << 0) +# define R200_TXFORMAT_RGB565 (4 << 0) +# define R200_TXFORMAT_ARGB4444 (5 << 0) +# define R200_TXFORMAT_ARGB8888 (6 << 0) +# define R200_TXFORMAT_RGBA8888 (7 << 0) +# define R200_TXFORMAT_Y8 (8 << 0) +# define R200_TXFORMAT_AVYU4444 (9 << 0) +# define R200_TXFORMAT_VYUY422 (10 << 0) +# define R200_TXFORMAT_YVYU422 (11 << 0) +# define R200_TXFORMAT_DXT1 (12 << 0) +# define R200_TXFORMAT_DXT23 (14 << 0) +# define R200_TXFORMAT_DXT45 (15 << 0) +# define R200_TXFORMAT_ABGR8888 (22 << 0) +# define R200_TXFORMAT_FORMAT_MASK (31 << 0) +# define R200_TXFORMAT_FORMAT_SHIFT 0 +# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define R200_TXFORMAT_NON_POWER2 (1 << 7) +# define R200_TXFORMAT_WIDTH_MASK (15 << 8) +# define R200_TXFORMAT_WIDTH_SHIFT 8 +# define R200_TXFORMAT_HEIGHT_MASK (15 << 12) +# define R200_TXFORMAT_HEIGHT_SHIFT 12 +# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ +# define R200_TXFORMAT_F5_WIDTH_SHIFT 16 +# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) +# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) +# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 +# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXFORMAT_X_1 0x2c28 +#define R200_PP_TXFORMAT_X_2 0x2c48 +#define R200_PP_TXFORMAT_X_3 0x2c68 +#define R200_PP_TXFORMAT_X_4 0x2c88 +#define R200_PP_TXFORMAT_X_5 0x2ca8 + +#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ +#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ +#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ +#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ +#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ + +#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ +#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ +#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ +#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ +#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ +#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ + +#define R200_PP_TXOFFSET_0 0x2d00 +# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) +# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define R200_TXO_MACRO_LINEAR (0 << 2) +# define R200_TXO_MACRO_TILE (1 << 2) +# define R200_TXO_MICRO_LINEAR (0 << 3) +# define R200_TXO_MICRO_TILE (1 << 3) +# define R200_TXO_OFFSET_MASK 0xffffffe0 +# define R200_TXO_OFFSET_SHIFT 5 +#define R200_PP_TXOFFSET_1 0x2d18 +#define R200_PP_TXOFFSET_2 0x2d30 +#define R200_PP_TXOFFSET_3 0x2d48 +#define R200_PP_TXOFFSET_4 0x2d60 +#define R200_PP_TXOFFSET_5 0x2d78 + +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_PP_TFACTOR_1 0x2ee4 +#define R200_PP_TFACTOR_2 0x2ee8 +#define R200_PP_TFACTOR_3 0x2eec +#define R200_PP_TFACTOR_4 0x2ef0 +#define R200_PP_TFACTOR_5 0x2ef4 + +#define R200_PP_TXCBLEND_0 0x2f00 +# define R200_TXC_ARG_A_ZERO (0) +# define R200_TXC_ARG_A_CURRENT_COLOR (2) +# define R200_TXC_ARG_A_CURRENT_ALPHA (3) +# define R200_TXC_ARG_A_DIFFUSE_COLOR (4) +# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) +# define R200_TXC_ARG_A_SPECULAR_COLOR (6) +# define R200_TXC_ARG_A_SPECULAR_ALPHA (7) +# define R200_TXC_ARG_A_TFACTOR_COLOR (8) +# define R200_TXC_ARG_A_TFACTOR_ALPHA (9) +# define R200_TXC_ARG_A_R0_COLOR (10) +# define R200_TXC_ARG_A_R0_ALPHA (11) +# define R200_TXC_ARG_A_R1_COLOR (12) +# define R200_TXC_ARG_A_R1_ALPHA (13) +# define R200_TXC_ARG_A_R2_COLOR (14) +# define R200_TXC_ARG_A_R2_ALPHA (15) +# define R200_TXC_ARG_A_R3_COLOR (16) +# define R200_TXC_ARG_A_R3_ALPHA (17) +# define R200_TXC_ARG_A_R4_COLOR (18) +# define R200_TXC_ARG_A_R4_ALPHA (19) +# define R200_TXC_ARG_A_R5_COLOR (20) +# define R200_TXC_ARG_A_R5_ALPHA (21) +# define R200_TXC_ARG_A_TFACTOR1_COLOR (26) +# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) +# define R200_TXC_ARG_A_MASK (31 << 0) +# define R200_TXC_ARG_A_SHIFT 0 +# define R200_TXC_ARG_B_ZERO (0 << 5) +# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) +# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) +# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) +# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) +# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) +# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) +# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) +# define R200_TXC_ARG_B_R0_COLOR (10 << 5) +# define R200_TXC_ARG_B_R0_ALPHA (11 << 5) +# define R200_TXC_ARG_B_R1_COLOR (12 << 5) +# define R200_TXC_ARG_B_R1_ALPHA (13 << 5) +# define R200_TXC_ARG_B_R2_COLOR (14 << 5) +# define R200_TXC_ARG_B_R2_ALPHA (15 << 5) +# define R200_TXC_ARG_B_R3_COLOR (16 << 5) +# define R200_TXC_ARG_B_R3_ALPHA (17 << 5) +# define R200_TXC_ARG_B_R4_COLOR (18 << 5) +# define R200_TXC_ARG_B_R4_ALPHA (19 << 5) +# define R200_TXC_ARG_B_R5_COLOR (20 << 5) +# define R200_TXC_ARG_B_R5_ALPHA (21 << 5) +# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) +# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) +# define R200_TXC_ARG_B_MASK (31 << 5) +# define R200_TXC_ARG_B_SHIFT 5 +# define R200_TXC_ARG_C_ZERO (0 << 10) +# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) +# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) +# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) +# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) +# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) +# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) +# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) +# define R200_TXC_ARG_C_R0_COLOR (10 << 10) +# define R200_TXC_ARG_C_R0_ALPHA (11 << 10) +# define R200_TXC_ARG_C_R1_COLOR (12 << 10) +# define R200_TXC_ARG_C_R1_ALPHA (13 << 10) +# define R200_TXC_ARG_C_R2_COLOR (14 << 10) +# define R200_TXC_ARG_C_R2_ALPHA (15 << 10) +# define R200_TXC_ARG_C_R3_COLOR (16 << 10) +# define R200_TXC_ARG_C_R3_ALPHA (17 << 10) +# define R200_TXC_ARG_C_R4_COLOR (18 << 10) +# define R200_TXC_ARG_C_R4_ALPHA (19 << 10) +# define R200_TXC_ARG_C_R5_COLOR (20 << 10) +# define R200_TXC_ARG_C_R5_ALPHA (21 << 10) +# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) +# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) +# define R200_TXC_ARG_C_MASK (31 << 10) +# define R200_TXC_ARG_C_SHIFT 10 +# define R200_TXC_COMP_ARG_A (1 << 16) +# define R200_TXC_COMP_ARG_A_SHIFT (16) +# define R200_TXC_BIAS_ARG_A (1 << 17) +# define R200_TXC_SCALE_ARG_A (1 << 18) +# define R200_TXC_NEG_ARG_A (1 << 19) +# define R200_TXC_COMP_ARG_B (1 << 20) +# define R200_TXC_COMP_ARG_B_SHIFT (20) +# define R200_TXC_BIAS_ARG_B (1 << 21) +# define R200_TXC_SCALE_ARG_B (1 << 22) +# define R200_TXC_NEG_ARG_B (1 << 23) +# define R200_TXC_COMP_ARG_C (1 << 24) +# define R200_TXC_COMP_ARG_C_SHIFT (24) +# define R200_TXC_BIAS_ARG_C (1 << 25) +# define R200_TXC_SCALE_ARG_C (1 << 26) +# define R200_TXC_NEG_ARG_C (1 << 27) +# define R200_TXC_OP_MADD (0 << 28) +# define R200_TXC_OP_CND0 (2 << 28) +# define R200_TXC_OP_LERP (3 << 28) +# define R200_TXC_OP_DOT3 (4 << 28) +# define R200_TXC_OP_DOT4 (5 << 28) +# define R200_TXC_OP_CONDITIONAL (6 << 28) +# define R200_TXC_OP_DOT2_ADD (7 << 28) +# define R200_TXC_OP_MASK (7 << 28) +#define R200_PP_TXCBLEND2_0 0x2f04 +# define R200_TXC_TFACTOR_SEL_SHIFT 0 +# define R200_TXC_TFACTOR_SEL_MASK 0x7 +# define R200_TXC_TFACTOR1_SEL_SHIFT 4 +# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXC_SCALE_SHIFT 8 +# define R200_TXC_SCALE_MASK (7 << 8) +# define R200_TXC_SCALE_1X (0 << 8) +# define R200_TXC_SCALE_2X (1 << 8) +# define R200_TXC_SCALE_4X (2 << 8) +# define R200_TXC_SCALE_8X (3 << 8) +# define R200_TXC_SCALE_INV2 (5 << 8) +# define R200_TXC_SCALE_INV4 (6 << 8) +# define R200_TXC_SCALE_INV8 (7 << 8) +# define R200_TXC_CLAMP_SHIFT 12 +# define R200_TXC_CLAMP_MASK (3 << 12) +# define R200_TXC_CLAMP_WRAP (0 << 12) +# define R200_TXC_CLAMP_0_1 (1 << 12) +# define R200_TXC_CLAMP_8_8 (2 << 12) +# define R200_TXC_OUTPUT_REG_MASK (7 << 16) +# define R200_TXC_OUTPUT_REG_NONE (0 << 16) +# define R200_TXC_OUTPUT_REG_R0 (1 << 16) +# define R200_TXC_OUTPUT_REG_R1 (2 << 16) +# define R200_TXC_OUTPUT_REG_R2 (3 << 16) +# define R200_TXC_OUTPUT_REG_R3 (4 << 16) +# define R200_TXC_OUTPUT_REG_R4 (5 << 16) +# define R200_TXC_OUTPUT_REG_R5 (6 << 16) +# define R200_TXC_OUTPUT_MASK_MASK (7 << 20) +# define R200_TXC_OUTPUT_MASK_RGB (0 << 20) +# define R200_TXC_OUTPUT_MASK_RG (1 << 20) +# define R200_TXC_OUTPUT_MASK_RB (2 << 20) +# define R200_TXC_OUTPUT_MASK_R (3 << 20) +# define R200_TXC_OUTPUT_MASK_GB (4 << 20) +# define R200_TXC_OUTPUT_MASK_G (5 << 20) +# define R200_TXC_OUTPUT_MASK_B (6 << 20) +# define R200_TXC_OUTPUT_MASK_NONE (7 << 20) +# define R200_TXC_REPL_NORMAL 0 +# define R200_TXC_REPL_RED 1 +# define R200_TXC_REPL_GREEN 2 +# define R200_TXC_REPL_BLUE 3 +# define R200_TXC_REPL_ARG_A_SHIFT 26 +# define R200_TXC_REPL_ARG_A_MASK (3 << 26) +# define R200_TXC_REPL_ARG_B_SHIFT 28 +# define R200_TXC_REPL_ARG_B_MASK (3 << 28) +# define R200_TXC_REPL_ARG_C_SHIFT 30 +# define R200_TXC_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXABLEND_0 0x2f08 +# define R200_TXA_ARG_A_ZERO (0) +# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ +# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ +# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) +# define R200_TXA_ARG_A_DIFFUSE_BLUE (5) +# define R200_TXA_ARG_A_SPECULAR_ALPHA (6) +# define R200_TXA_ARG_A_SPECULAR_BLUE (7) +# define R200_TXA_ARG_A_TFACTOR_ALPHA (8) +# define R200_TXA_ARG_A_TFACTOR_BLUE (9) +# define R200_TXA_ARG_A_R0_ALPHA (10) +# define R200_TXA_ARG_A_R0_BLUE (11) +# define R200_TXA_ARG_A_R1_ALPHA (12) +# define R200_TXA_ARG_A_R1_BLUE (13) +# define R200_TXA_ARG_A_R2_ALPHA (14) +# define R200_TXA_ARG_A_R2_BLUE (15) +# define R200_TXA_ARG_A_R3_ALPHA (16) +# define R200_TXA_ARG_A_R3_BLUE (17) +# define R200_TXA_ARG_A_R4_ALPHA (18) +# define R200_TXA_ARG_A_R4_BLUE (19) +# define R200_TXA_ARG_A_R5_ALPHA (20) +# define R200_TXA_ARG_A_R5_BLUE (21) +# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) +# define R200_TXA_ARG_A_TFACTOR1_BLUE (27) +# define R200_TXA_ARG_A_MASK (31 << 0) +# define R200_TXA_ARG_A_SHIFT 0 +# define R200_TXA_ARG_B_ZERO (0 << 5) +# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ +# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ +# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) +# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) +# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) +# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) +# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) +# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) +# define R200_TXA_ARG_B_R0_ALPHA (10 << 5) +# define R200_TXA_ARG_B_R0_BLUE (11 << 5) +# define R200_TXA_ARG_B_R1_ALPHA (12 << 5) +# define R200_TXA_ARG_B_R1_BLUE (13 << 5) +# define R200_TXA_ARG_B_R2_ALPHA (14 << 5) +# define R200_TXA_ARG_B_R2_BLUE (15 << 5) +# define R200_TXA_ARG_B_R3_ALPHA (16 << 5) +# define R200_TXA_ARG_B_R3_BLUE (17 << 5) +# define R200_TXA_ARG_B_R4_ALPHA (18 << 5) +# define R200_TXA_ARG_B_R4_BLUE (19 << 5) +# define R200_TXA_ARG_B_R5_ALPHA (20 << 5) +# define R200_TXA_ARG_B_R5_BLUE (21 << 5) +# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) +# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) +# define R200_TXA_ARG_B_MASK (31 << 5) +# define R200_TXA_ARG_B_SHIFT 5 +# define R200_TXA_ARG_C_ZERO (0 << 10) +# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ +# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ +# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) +# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) +# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) +# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) +# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) +# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) +# define R200_TXA_ARG_C_R0_ALPHA (10 << 10) +# define R200_TXA_ARG_C_R0_BLUE (11 << 10) +# define R200_TXA_ARG_C_R1_ALPHA (12 << 10) +# define R200_TXA_ARG_C_R1_BLUE (13 << 10) +# define R200_TXA_ARG_C_R2_ALPHA (14 << 10) +# define R200_TXA_ARG_C_R2_BLUE (15 << 10) +# define R200_TXA_ARG_C_R3_ALPHA (16 << 10) +# define R200_TXA_ARG_C_R3_BLUE (17 << 10) +# define R200_TXA_ARG_C_R4_ALPHA (18 << 10) +# define R200_TXA_ARG_C_R4_BLUE (19 << 10) +# define R200_TXA_ARG_C_R5_ALPHA (20 << 10) +# define R200_TXA_ARG_C_R5_BLUE (21 << 10) +# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) +# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) +# define R200_TXA_ARG_C_MASK (31 << 10) +# define R200_TXA_ARG_C_SHIFT 10 +# define R200_TXA_COMP_ARG_A (1 << 16) +# define R200_TXA_COMP_ARG_A_SHIFT (16) +# define R200_TXA_BIAS_ARG_A (1 << 17) +# define R200_TXA_SCALE_ARG_A (1 << 18) +# define R200_TXA_NEG_ARG_A (1 << 19) +# define R200_TXA_COMP_ARG_B (1 << 20) +# define R200_TXA_COMP_ARG_B_SHIFT (20) +# define R200_TXA_BIAS_ARG_B (1 << 21) +# define R200_TXA_SCALE_ARG_B (1 << 22) +# define R200_TXA_NEG_ARG_B (1 << 23) +# define R200_TXA_COMP_ARG_C (1 << 24) +# define R200_TXA_COMP_ARG_C_SHIFT (24) +# define R200_TXA_BIAS_ARG_C (1 << 25) +# define R200_TXA_SCALE_ARG_C (1 << 26) +# define R200_TXA_NEG_ARG_C (1 << 27) +# define R200_TXA_OP_MADD (0 << 28) +# define R200_TXA_OP_CND0 (2 << 28) +# define R200_TXA_OP_LERP (3 << 28) +# define R200_TXA_OP_CONDITIONAL (6 << 28) +# define R200_TXA_OP_MASK (7 << 28) +#define R200_PP_TXABLEND2_0 0x2f0c +# define R200_TXA_TFACTOR_SEL_SHIFT 0 +# define R200_TXA_TFACTOR_SEL_MASK 0x7 +# define R200_TXA_TFACTOR1_SEL_SHIFT 4 +# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXA_SCALE_SHIFT 8 +# define R200_TXA_SCALE_MASK (7 << 8) +# define R200_TXA_SCALE_1X (0 << 8) +# define R200_TXA_SCALE_2X (1 << 8) +# define R200_TXA_SCALE_4X (2 << 8) +# define R200_TXA_SCALE_8X (3 << 8) +# define R200_TXA_SCALE_INV2 (5 << 8) +# define R200_TXA_SCALE_INV4 (6 << 8) +# define R200_TXA_SCALE_INV8 (7 << 8) +# define R200_TXA_CLAMP_SHIFT 12 +# define R200_TXA_CLAMP_MASK (3 << 12) +# define R200_TXA_CLAMP_WRAP (0 << 12) +# define R200_TXA_CLAMP_0_1 (1 << 12) +# define R200_TXA_CLAMP_8_8 (2 << 12) +# define R200_TXA_OUTPUT_REG_MASK (7 << 16) +# define R200_TXA_OUTPUT_REG_NONE (0 << 16) +# define R200_TXA_OUTPUT_REG_R0 (1 << 16) +# define R200_TXA_OUTPUT_REG_R1 (2 << 16) +# define R200_TXA_OUTPUT_REG_R2 (3 << 16) +# define R200_TXA_OUTPUT_REG_R3 (4 << 16) +# define R200_TXA_OUTPUT_REG_R4 (5 << 16) +# define R200_TXA_OUTPUT_REG_R5 (6 << 16) +# define R200_TXA_DOT_ALPHA (1 << 20) +# define R200_TXA_REPL_NORMAL 0 +# define R200_TXA_REPL_RED 1 +# define R200_TXA_REPL_GREEN 2 +# define R200_TXA_REPL_ARG_A_SHIFT 26 +# define R200_TXA_REPL_ARG_A_MASK (3 << 26) +# define R200_TXA_REPL_ARG_B_SHIFT 28 +# define R200_TXA_REPL_ARG_B_MASK (3 << 28) +# define R200_TXA_REPL_ARG_C_SHIFT 30 +# define R200_TXA_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXCBLEND_1 0x2f10 +#define R200_PP_TXCBLEND2_1 0x2f14 +#define R200_PP_TXABLEND_1 0x2f18 +#define R200_PP_TXABLEND2_1 0x2f1c +#define R200_PP_TXCBLEND_2 0x2f20 +#define R200_PP_TXCBLEND2_2 0x2f24 +#define R200_PP_TXABLEND_2 0x2f28 +#define R200_PP_TXABLEND2_2 0x2f2c +#define R200_PP_TXCBLEND_3 0x2f30 +#define R200_PP_TXCBLEND2_3 0x2f34 +#define R200_PP_TXABLEND_3 0x2f38 +#define R200_PP_TXABLEND2_3 0x2f3c + +#define R200_SE_VTX_FMT_0 0x2088 +# define R200_VTX_XY 0 /* always have xy */ +# define R200_VTX_Z0 (1<<0) +# define R200_VTX_W0 (1<<1) +# define R200_VTX_WEIGHT_COUNT_SHIFT (2) +# define R200_VTX_PV_MATRIX_SEL (1<<5) +# define R200_VTX_N0 (1<<6) +# define R200_VTX_POINT_SIZE (1<<7) +# define R200_VTX_DISCRETE_FOG (1<<8) +# define R200_VTX_SHININESS_0 (1<<9) +# define R200_VTX_SHININESS_1 (1<<10) +# define R200_VTX_COLOR_NOT_PRESENT 0 +# define R200_VTX_PK_RGBA 1 +# define R200_VTX_FP_RGB 2 +# define R200_VTX_FP_RGBA 3 +# define R200_VTX_COLOR_MASK 3 +# define R200_VTX_COLOR_0_SHIFT 11 +# define R200_VTX_COLOR_1_SHIFT 13 +# define R200_VTX_COLOR_2_SHIFT 15 +# define R200_VTX_COLOR_3_SHIFT 17 +# define R200_VTX_COLOR_4_SHIFT 19 +# define R200_VTX_COLOR_5_SHIFT 21 +# define R200_VTX_COLOR_6_SHIFT 23 +# define R200_VTX_COLOR_7_SHIFT 25 +# define R200_VTX_XY1 (1<<28) +# define R200_VTX_Z1 (1<<29) +# define R200_VTX_W1 (1<<30) +# define R200_VTX_N1 (1<<31) +#define R200_SE_VTX_FMT_1 0x208c +# define R200_VTX_TEX0_COMP_CNT_SHIFT 0 +# define R200_VTX_TEX1_COMP_CNT_SHIFT 3 +# define R200_VTX_TEX2_COMP_CNT_SHIFT 6 +# define R200_VTX_TEX3_COMP_CNT_SHIFT 9 +# define R200_VTX_TEX4_COMP_CNT_SHIFT 12 +# define R200_VTX_TEX5_COMP_CNT_SHIFT 15 + +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +# define R200_OUTPUT_XYZW (1<<0) +# define R200_OUTPUT_COLOR_0 (1<<8) +# define R200_OUTPUT_COLOR_1 (1<<9) +# define R200_OUTPUT_TEX_0 (1<<16) +# define R200_OUTPUT_TEX_1 (1<<17) +# define R200_OUTPUT_TEX_2 (1<<18) +# define R200_OUTPUT_TEX_3 (1<<19) +# define R200_OUTPUT_TEX_4 (1<<20) +# define R200_OUTPUT_TEX_5 (1<<21) +# define R200_OUTPUT_TEX_MASK (0x3f<<16) +# define R200_OUTPUT_DISCRETE_FOG (1<<24) +# define R200_OUTPUT_PT_SIZE (1<<25) +# define R200_FORCE_INORDER_PROC (1<<31) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) + + /* Registers for CP and Microcode Engine */ +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_IB_BASE 0x0738 +#define RADEON_CP_IB_BUFSZ 0x073c + +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) +#define RADEON_CP_CSQ_STAT 0x07f8 +# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) +# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) +# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) +#define RADEON_CP_CSQ_ADDR 0x07f0 +#define RADEON_CP_CSQ_DATA 0x07f4 +#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 +#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +# define RADEON_PRE_WRITE_TIMER_SHIFT 0 +# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_AIC_CNTL 0x01d0 +# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +#define RADEON_AIC_LO_ADDR 0x01dc + + + + /* Constants */ +#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 +#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 + + + + /* CP packet types */ +#define RADEON_CP_PACKET0 0x00000000 +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_CP_PACKET_MASK 0xC0000000 +# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) +# define RADEON_CP_PACKET0_REG_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + + +#define RADEON_CP_VC_FRMT_XY 0x00000000 +#define RADEON_CP_VC_FRMT_W0 0x00000001 +#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 +#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 +#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 +#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 +#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 +#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 +#define RADEON_CP_VC_FRMT_ST0 0x00000080 +#define RADEON_CP_VC_FRMT_ST1 0x00000100 +#define RADEON_CP_VC_FRMT_Q1 0x00000200 +#define RADEON_CP_VC_FRMT_ST2 0x00000400 +#define RADEON_CP_VC_FRMT_Q2 0x00000800 +#define RADEON_CP_VC_FRMT_ST3 0x00001000 +#define RADEON_CP_VC_FRMT_Q3 0x00002000 +#define RADEON_CP_VC_FRMT_Q0 0x00004000 +#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 +#define RADEON_CP_VC_FRMT_N0 0x00040000 +#define RADEON_CP_VC_FRMT_XY1 0x08000000 +#define RADEON_CP_VC_FRMT_Z1 0x10000000 +#define RADEON_CP_VC_FRMT_W1 0x20000000 +#define RADEON_CP_VC_FRMT_N1 0x40000000 +#define RADEON_CP_VC_FRMT_Z 0x80000000 + +#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a +#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d +#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 +#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 +#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 +#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 +#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 +#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 +#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 + +#define RADEON_VS_MATRIX_0_ADDR 0 +#define RADEON_VS_MATRIX_1_ADDR 4 +#define RADEON_VS_MATRIX_2_ADDR 8 +#define RADEON_VS_MATRIX_3_ADDR 12 +#define RADEON_VS_MATRIX_4_ADDR 16 +#define RADEON_VS_MATRIX_5_ADDR 20 +#define RADEON_VS_MATRIX_6_ADDR 24 +#define RADEON_VS_MATRIX_7_ADDR 28 +#define RADEON_VS_MATRIX_8_ADDR 32 +#define RADEON_VS_MATRIX_9_ADDR 36 +#define RADEON_VS_MATRIX_10_ADDR 40 +#define RADEON_VS_MATRIX_11_ADDR 44 +#define RADEON_VS_MATRIX_12_ADDR 48 +#define RADEON_VS_MATRIX_13_ADDR 52 +#define RADEON_VS_MATRIX_14_ADDR 56 +#define RADEON_VS_MATRIX_15_ADDR 60 +#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 +#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 +#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 +#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 +#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 +#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 +#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 +#define RADEON_VS_UCP_ADDR 116 +#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 +#define RADEON_VS_FOG_PARAM_ADDR 123 +#define RADEON_VS_EYE_VECTOR_ADDR 124 + +#define RADEON_SS_LIGHT_DCD_ADDR 0 +#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 +#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 +#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 +#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 +#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 +#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 +#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 +#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 +#define RADEON_SS_SHININESS 60 + +#define RADEON_TV_MASTER_CNTL 0x0800 +# define RADEON_TV_ASYNC_RST (1 << 0) +# define RADEON_CRT_ASYNC_RST (1 << 1) +# define RADEON_RESTART_PHASE_FIX (1 << 3) +# define RADEON_TV_FIFO_ASYNC_RST (1 << 4) +# define RADEON_VIN_ASYNC_RST (1 << 5) +# define RADEON_AUD_ASYNC_RST (1 << 6) +# define RADEON_DVS_ASYNC_RST (1 << 7) +# define RADEON_CRT_FIFO_CE_EN (1 << 9) +# define RADEON_TV_FIFO_CE_EN (1 << 10) +# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) +# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) +# define RADEON_TV_ON (1 << 31) +#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 +# define RADEON_Y_RED_EN (1 << 0) +# define RADEON_C_GRN_EN (1 << 1) +# define RADEON_CMP_BLU_EN (1 << 2) +# define RADEON_DAC_DITHER_EN (1 << 3) +# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) +# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) +# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) +# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 +#define RADEON_TV_RGB_CNTL 0x0804 +# define RADEON_SWITCH_TO_BLUE (1 << 4) +# define RADEON_RGB_DITHER_EN (1 << 5) +# define RADEON_RGB_SRC_SEL_MASK (3 << 8) +# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) +# define RADEON_RGB_SRC_SEL_RMX (1 << 8) +# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) +# define RADEON_RGB_CONVERT_BY_PASS (1 << 10) +# define RADEON_UVRAM_READ_MARGIN_SHIFT 16 +# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 +# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) +# define RADEON_TVOUT_SCALE_EN (1 << 26) +# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) +#define RADEON_TV_SYNC_CNTL 0x0808 +# define RADEON_SYNC_OE (1 << 0) +# define RADEON_SYNC_OUT (1 << 1) +# define RADEON_SYNC_IN (1 << 2) +# define RADEON_SYNC_PUB (1 << 3) +# define RADEON_SYNC_PD (1 << 4) +# define RADEON_TV_SYNC_IO_DRIVE (1 << 5) +#define RADEON_TV_HTOTAL 0x080c +#define RADEON_TV_HDISP 0x0810 +#define RADEON_TV_HSTART 0x0818 +#define RADEON_TV_HCOUNT 0x081C +#define RADEON_TV_VTOTAL 0x0820 +#define RADEON_TV_VDISP 0x0824 +#define RADEON_TV_VCOUNT 0x0828 +#define RADEON_TV_FTOTAL 0x082c +#define RADEON_TV_FCOUNT 0x0830 +#define RADEON_TV_FRESTART 0x0834 +#define RADEON_TV_HRESTART 0x0838 +#define RADEON_TV_VRESTART 0x083c +#define RADEON_TV_HOST_READ_DATA 0x0840 +#define RADEON_TV_HOST_WRITE_DATA 0x0844 +#define RADEON_TV_HOST_RD_WT_CNTL 0x0848 +# define RADEON_HOST_FIFO_RD (1 << 12) +# define RADEON_HOST_FIFO_RD_ACK (1 << 13) +# define RADEON_HOST_FIFO_WT (1 << 14) +# define RADEON_HOST_FIFO_WT_ACK (1 << 15) +#define RADEON_TV_VSCALER_CNTL1 0x084c +# define RADEON_UV_INC_MASK 0xffff +# define RADEON_UV_INC_SHIFT 0 +# define RADEON_Y_W_EN (1 << 24) +# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ +# define RADEON_Y_DEL_W_SIG_SHIFT 26 +#define RADEON_TV_TIMING_CNTL 0x0850 +# define RADEON_H_INC_MASK 0xfff +# define RADEON_H_INC_SHIFT 0 +# define RADEON_REQ_Y_FIRST (1 << 19) +# define RADEON_FORCE_BURST_ALWAYS (1 << 21) +# define RADEON_UV_POST_SCALE_BYPASS (1 << 23) +# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 +#define RADEON_TV_VSCALER_CNTL2 0x0854 +# define RADEON_DITHER_MODE (1 << 0) +# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) +# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) +# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) +#define RADEON_TV_Y_FALL_CNTL 0x0858 +# define RADEON_Y_FALL_PING_PONG (1 << 16) +# define RADEON_Y_COEF_EN (1 << 17) +#define RADEON_TV_Y_RISE_CNTL 0x085c +# define RADEON_Y_RISE_PING_PONG (1 << 16) +#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 +#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 +# define RADEON_YUPSAMP_EN (1 << 0) +# define RADEON_UVUPSAMP_EN (1 << 2) +#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 +# define RADEON_Y_GAIN_LIMIT_SHIFT 0 +# define RADEON_UV_GAIN_LIMIT_SHIFT 16 +#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c +# define RADEON_Y_GAIN_SHIFT 0 +# define RADEON_UV_GAIN_SHIFT 16 +#define RADEON_TV_MODULATOR_CNTL1 0x0870 +# define RADEON_YFLT_EN (1 << 2) +# define RADEON_UVFLT_EN (1 << 3) +# define RADEON_ALT_PHASE_EN (1 << 6) +# define RADEON_SYNC_TIP_LEVEL (1 << 7) +# define RADEON_BLANK_LEVEL_SHIFT 8 +# define RADEON_SET_UP_LEVEL_SHIFT 16 +# define RADEON_SLEW_RATE_LIMIT (1 << 23) +# define RADEON_CY_FILT_BLEND_SHIFT 28 +#define RADEON_TV_MODULATOR_CNTL2 0x0874 +# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff +# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff +# define RADEON_TV_V_BURST_LEVEL_SHIFT 16 +#define RADEON_TV_CRC_CNTL 0x0890 +#define RADEON_TV_UV_ADR 0x08ac +# define RADEON_MAX_UV_ADR_MASK 0x000000ff +# define RADEON_MAX_UV_ADR_SHIFT 0 +# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 +# define RADEON_TABLE1_BOT_ADR_SHIFT 8 +# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 +# define RADEON_TABLE3_TOP_ADR_SHIFT 16 +# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 +# define RADEON_HCODE_TABLE_SEL_SHIFT 25 +# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 +# define RADEON_VCODE_TABLE_SEL_SHIFT 27 +# define RADEON_TV_MAX_FIFO_ADDR 0x1a7 +# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff +#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ +#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ +# define RADEON_TV_M0LO_MASK 0xff +# define RADEON_TV_M0HI_MASK 0x7 +# define RADEON_TV_M0HI_SHIFT 18 +# define RADEON_TV_N0LO_MASK 0x1ff +# define RADEON_TV_N0LO_SHIFT 8 +# define RADEON_TV_N0HI_MASK 0x3 +# define RADEON_TV_N0HI_SHIFT 21 +# define RADEON_TV_P_MASK 0xf +# define RADEON_TV_P_SHIFT 24 +# define RADEON_TV_SLIP_EN (1 << 23) +# define RADEON_TV_DTO_EN (1 << 28) +#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ +# define RADEON_TVPLL_RESET (1 << 1) +# define RADEON_TVPLL_SLEEP (1 << 3) +# define RADEON_TVPLL_REFCLK_SEL (1 << 4) +# define RADEON_TVPCP_SHIFT 8 +# define RADEON_TVPCP_MASK (7 << 8) +# define RADEON_TVPVG_SHIFT 11 +# define RADEON_TVPVG_MASK (7 << 11) +# define RADEON_TVPDC_SHIFT 14 +# define RADEON_TVPDC_MASK (3 << 14) +# define RADEON_TVPLL_TEST_DIS (1 << 31) +# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) + +#define RS400_DISP2_REQ_CNTL1 0xe30 +# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 +# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 +# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 +# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff +#define RS400_DISP2_REQ_CNTL2 0xe34 +# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 +# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff +# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 +# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff +#define RS400_DMIF_MEM_CNTL1 0xe38 +# define RS400_DISP2_START_ADR_SHIFT 0 +# define RS400_DISP2_START_ADR_MASK 0x3ff +# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 +# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff +# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 +# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff +#define RS400_DISP1_REQ_CNTL1 0xe3c +# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 +# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 +# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 +# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff + +#define RS690_MC_INDEX 0x78 +# define RS690_MC_INDEX_MASK 0x1ff +# define RS690_MC_INDEX_WR_EN (1 << 9) +# define RS690_MC_INDEX_WR_ACK 0x7f +#define RS690_MC_DATA 0x7c + +#define RS690_MC_FB_LOCATION 0x100 +#define RS690_MC_AGP_LOCATION 0x101 +#define RS690_MC_AGP_BASE 0x102 +#define RS690_MC_AGP_BASE_2 0x103 +#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 +#define RS690_MC_STATUS 0x90 +#define RS690_MC_STATUS_IDLE (1 << 0) + +#define RS600_MC_INDEX 0x70 +# define RS600_MC_ADDR_MASK 0xffff +# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) +# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) +# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) +# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) +# define RS600_MC_IND_AIC_RBS (1 << 20) +# define RS600_MC_IND_CITF_ARB0 (1 << 21) +# define RS600_MC_IND_CITF_ARB1 (1 << 22) +# define RS600_MC_IND_WR_EN (1 << 23) +#define RS600_MC_DATA 0x74 + +#define RS600_MC_STATUS 0x0 +# define RS600_MC_IDLE (1 << 1) +#define RS600_MC_FB_LOCATION 0x4 +#define RS600_MC_AGP_LOCATION 0x5 +#define RS600_AGP_BASE 0x6 +#define RS600_AGP_BASE2 0x7 + +#define AVIVO_MC_INDEX 0x0070 +#define R520_MC_STATUS 0x00 +# define R520_MC_STATUS_IDLE (1 << 1) +#define RV515_MC_STATUS 0x08 +# define RV515_MC_STATUS_IDLE (1 << 4) +#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 +#define AVIVO_MC_DATA 0x0074 + +#define RV515_MC_FB_LOCATION 0x1 +#define RV515_MC_AGP_LOCATION 0x2 +#define RV515_MC_AGP_BASE 0x3 +#define RV515_MC_AGP_BASE_2 0x4 +#define RV515_MC_CNTL 0x5 +# define RV515_MEM_NUM_CHANNELS_MASK 0x3 +#define R520_MC_FB_LOCATION 0x4 +#define R520_MC_AGP_LOCATION 0x5 +#define R520_MC_AGP_BASE 0x6 +#define R520_MC_AGP_BASE_2 0x7 +#define R520_MC_CNTL0 0x8 +# define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) +# define R520_MEM_NUM_CHANNELS_SHIFT 24 +# define R520_MC_CHANNEL_SIZE (1 << 23) + +#define RS780_MC_INDEX 0x28f8 +# define RS780_MC_INDEX_MASK 0x1ff +# define RS780_MC_INDEX_WR_EN (1 << 9) +#define RS780_MC_DATA 0x28fc + +#define R600_RAMCFG 0x2408 +# define R600_CHANSIZE (1 << 7) +# define R600_CHANSIZE_OVERRIDE (1 << 10) + +#define R600_SRBM_STATUS 0x0e50 + +#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ +# define AVIVO_CP_FORCEON (1 << 0) +#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ +# define AVIVO_E2_FORCEON (1 << 0) +#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ +# define AVIVO_IDCT_FORCEON (1 << 0) + +#define AVIVO_HDP_FB_LOCATION 0x134 + +#define AVIVO_VGA_RENDER_CONTROL 0x0300 +# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) +#define AVIVO_D1VGA_CONTROL 0x0330 +# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) +# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) +# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) +# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) +# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) +# define AVIVO_DVGA_CONTROL_ROTATE (1<<24) +#define AVIVO_D2VGA_CONTROL 0x0338 + +#define AVIVO_VGA25_PPLL_REF_DIV_SRC 0x0360 +#define AVIVO_VGA25_PPLL_REF_DIV 0x0364 +#define AVIVO_VGA28_PPLL_REF_DIV_SRC 0x0368 +#define AVIVO_VGA28_PPLL_REF_DIV 0x036c +#define AVIVO_VGA41_PPLL_REF_DIV_SRC 0x0370 +#define AVIVO_VGA41_PPLL_REF_DIV 0x0374 +#define AVIVO_VGA25_PPLL_FB_DIV 0x0378 +#define AVIVO_VGA28_PPLL_FB_DIV 0x037c +#define AVIVO_VGA41_PPLL_FB_DIV 0x0380 +#define AVIVO_VGA25_PPLL_POST_DIV_SRC 0x0384 +#define AVIVO_VGA25_PPLL_POST_DIV 0x0388 +#define AVIVO_VGA28_PPLL_POST_DIV_SRC 0x038c +#define AVIVO_VGA28_PPLL_POST_DIV 0x0390 +#define AVIVO_VGA41_PPLL_POST_DIV_SRC 0x0394 +#define AVIVO_VGA41_PPLL_POST_DIV 0x0398 +#define AVIVO_VGA25_PPLL_CNTL 0x039c +#define AVIVO_VGA28_PPLL_CNTL 0x03a0 +#define AVIVO_VGA41_PPLL_CNTL 0x03a4 + +#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 +#define AVIVO_EXT1_PPLL_REF_DIV 0x404 +#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 +#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c + +#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 +#define AVIVO_EXT2_PPLL_REF_DIV 0x414 +#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 +#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c + +#define AVIVO_EXT1_PPLL_FB_DIV 0x430 +#define AVIVO_EXT2_PPLL_FB_DIV 0x434 + +#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 +#define AVIVO_EXT1_PPLL_POST_DIV 0x43c + +#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 +#define AVIVO_EXT2_PPLL_POST_DIV 0x444 + +#define AVIVO_EXT1_PPLL_CNTL 0x448 +#define AVIVO_EXT2_PPLL_CNTL 0x44c + +#define AVIVO_P1PLL_CNTL 0x450 +#define AVIVO_P2PLL_CNTL 0x454 +#define AVIVO_P1PLL_INT_SS_CNTL 0x458 +#define AVIVO_P2PLL_INT_SS_CNTL 0x45c +#define AVIVO_P1PLL_TMDSA_CNTL 0x460 +#define AVIVO_P2PLL_LVTMA_CNTL 0x464 + +#define AVIVO_PCLK_CRTC1_CNTL 0x480 +#define AVIVO_PCLK_CRTC2_CNTL 0x484 + +#define AVIVO_D1CRTC_H_TOTAL 0x6000 +#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 +#define AVIVO_D1CRTC_H_SYNC_A 0x6008 +#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c +#define AVIVO_D1CRTC_H_SYNC_B 0x6010 +#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 + +#define AVIVO_D1CRTC_V_TOTAL 0x6020 +#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 +#define AVIVO_D1CRTC_V_SYNC_A 0x6028 +#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c +#define AVIVO_D1CRTC_V_SYNC_B 0x6030 +#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 + +#define AVIVO_D1CRTC_CONTROL 0x6080 +# define AVIVO_CRTC_EN (1<<0) +#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 +#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 +#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c +#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 + +/* master controls */ +#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 +#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc + +#define AVIVO_D1GRPH_ENABLE 0x6100 +#define AVIVO_D1GRPH_CONTROL 0x6104 +# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) + +# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) + +# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) + +# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) + + +# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) + +# define AVIVO_D1GRPH_SWAP_RB (1<<16) +# define AVIVO_D1GRPH_TILED (1<<20) +# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) + +#define AVIVO_D1GRPH_LUT_SEL 0x6108 + +#define R600_D1GRPH_SWAP_CONTROL 0x610C +# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) +# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) +# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) +# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) + +/* the *_HIGH surface regs are backwards; the D1 regs are in the D2 + * block and vice versa. This applies to GRPH, CUR, etc. + */ + +#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 +#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 +#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 +#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c +#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c +#define AVIVO_D1GRPH_PITCH 0x6120 +#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 +#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 +#define AVIVO_D1GRPH_X_START 0x612c +#define AVIVO_D1GRPH_Y_START 0x6130 +#define AVIVO_D1GRPH_X_END 0x6134 +#define AVIVO_D1GRPH_Y_END 0x6138 +#define AVIVO_D1GRPH_UPDATE 0x6144 +# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) +#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 + +#define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380 + +#define AVIVO_D1CUR_CONTROL 0x6400 +# define AVIVO_D1CURSOR_EN (1<<0) +# define AVIVO_D1CURSOR_MODE_SHIFT 8 +# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) +# define AVIVO_D1CURSOR_MODE_24BPP (0x2) +#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 +#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c +#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c +#define AVIVO_D1CUR_SIZE 0x6410 +#define AVIVO_D1CUR_POSITION 0x6414 +#define AVIVO_D1CUR_HOT_SPOT 0x6418 +#define AVIVO_D1CUR_UPDATE 0x6424 +# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) + +#define AVIVO_DC_LUT_RW_SELECT 0x6480 +#define AVIVO_DC_LUT_RW_MODE 0x6484 +#define AVIVO_DC_LUT_RW_INDEX 0x6488 +#define AVIVO_DC_LUT_SEQ_COLOR 0x648c +#define AVIVO_DC_LUT_PWL_DATA 0x6490 +#define AVIVO_DC_LUT_30_COLOR 0x6494 +#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 +#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c +#define AVIVO_DC_LUT_AUTOFILL 0x64a0 + +#define AVIVO_DC_LUTA_CONTROL 0x64c0 +#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 +#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 +#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc +#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 +#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 +#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 + +#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 +# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 +# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 +# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) +# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 +# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff +#define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548 +# define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff +# define AVIVO_DxMODE_PRIORITY_OFF (1 << 16) +# define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20) +# define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24) +#define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c +#define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48 +#define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c +#define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58 +# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf +# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 +# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf +# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 + +#define AVIVO_D1MODE_DATA_FORMAT 0x6528 +# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) +#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c +#define AVIVO_D1MODE_VLINE_START_END 0x6538 +# define AVIVO_D1MODE_VLINE_START_SHIFT 0 +# define AVIVO_D1MODE_VLINE_END_SHIFT 16 +# define AVIVO_D1MODE_VLINE_INV (1 << 31) +#define AVIVO_D1MODE_VLINE_STATUS 0x653c +# define AVIVO_D1MODE_VLINE_STAT (1 << 12) +#define AVIVO_D1MODE_VIEWPORT_START 0x6580 +#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 +#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 +#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c + +#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 +#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 +#define AVIVO_D1SCL_UPDATE 0x65cc +# define AVIVO_D1SCL_UPDATE_LOCK (1<<16) + +/* second crtc */ +#define AVIVO_D2CRTC_H_TOTAL 0x6800 +#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 +#define AVIVO_D2CRTC_H_SYNC_A 0x6808 +#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c +#define AVIVO_D2CRTC_H_SYNC_B 0x6810 +#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 + +#define AVIVO_D2CRTC_V_TOTAL 0x6820 +#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 +#define AVIVO_D2CRTC_V_SYNC_A 0x6828 +#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c +#define AVIVO_D2CRTC_V_SYNC_B 0x6830 +#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 + +#define AVIVO_D2CRTC_CONTROL 0x6880 +#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 +#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 +#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c +#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 + +#define AVIVO_D2GRPH_ENABLE 0x6900 +#define AVIVO_D2GRPH_CONTROL 0x6904 +#define AVIVO_D2GRPH_LUT_SEL 0x6908 +#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 +#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 +#define AVIVO_D2GRPH_PITCH 0x6920 +#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 +#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 +#define AVIVO_D2GRPH_X_START 0x692c +#define AVIVO_D2GRPH_Y_START 0x6930 +#define AVIVO_D2GRPH_X_END 0x6934 +#define AVIVO_D2GRPH_Y_END 0x6938 +#define AVIVO_D2GRPH_UPDATE 0x6944 +#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 + +#define AVIVO_D2CUR_CONTROL 0x6c00 +#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 +#define AVIVO_D2CUR_SIZE 0x6c10 +#define AVIVO_D2CUR_POSITION 0x6c14 + +#define RS690_DCP_CONTROL 0x6c9c + +#define AVIVO_D2MODE_DATA_FORMAT 0x6d28 +#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c +#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 +#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 +#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 +#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c + +#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 +#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 +#define AVIVO_D2SCL_UPDATE 0x6dcc + +#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 + +#define AVIVO_DACA_ENABLE 0x7800 +# define AVIVO_DAC_ENABLE (1 << 0) +#define AVIVO_DACA_SOURCE_SELECT 0x7804 +# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) +# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) +# define AVIVO_DAC_SOURCE_TV (2 << 0) + +#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACA_POWERDOWN 0x7850 +# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACA_POWERDOWN_RED (1 << 24) + +#define AVIVO_DACB_ENABLE 0x7a00 +#define AVIVO_DACB_SOURCE_SELECT 0x7a04 +#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACB_POWERDOWN 0x7a50 +# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACB_POWERDOWN_RED + +#define AVIVO_TMDSA_CNTL 0x7880 +# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) +# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) +#define AVIVO_TMDSA_SOURCE_SELECT 0x7884 +/* 78a8 appears to be some kind of (reasonably tolerant) clock? + * 78d0 definitely hits the transmitter, definitely clock. */ +/* MYSTERY1 This appears to control dithering? */ +#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) +#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 +# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) +#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 +#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define AVIVO_LVTMA_CNTL 0x7a80 +# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) +# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) +#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 +#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) + + + +#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 +# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) + +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define R500_LVTMA_CLOCK_ENABLE 0x7b00 +#define R600_LVTMA_CLOCK_ENABLE 0x7b04 + +#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 +#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 +#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 +#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 +# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) +# define AVIVO_LVTMA_SYNCEN (1 << 8) +# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) +# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) +# define AVIVO_LVTMA_DIGON (1 << 16) +# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) +# define AVIVO_LVTMA_DIGON_POL (1 << 18) +# define AVIVO_LVTMA_BLON (1 << 24) +# define AVIVO_LVTMA_BLON_OVRD (1 << 25) +# define AVIVO_LVTMA_BLON_POL (1 << 26) + +#define R500_LVTMA_PWRSEQ_STATE 0x7af4 +#define R600_LVTMA_PWRSEQ_STATE 0x7af8 +# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) +# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) +# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) + +#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 +# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) +# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 +# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 + +#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 + +#define AVIVO_GPIO_0 0x7e30 +#define AVIVO_GPIO_1 0x7e40 +#define AVIVO_GPIO_2 0x7e50 +#define AVIVO_GPIO_3 0x7e60 + +#define AVIVO_DC_GPIO_HPD_MASK 0x7e90 +#define AVIVO_DC_GPIO_HPD_A 0x7e94 +#define AVIVO_DC_GPIO_HPD_EN 0x7e98 +#define AVIVO_DC_GPIO_HPD_Y 0x7e9c + +#define AVIVO_I2C_STATUS 0x7d30 +# define AVIVO_I2C_STATUS_DONE (1 << 0) +# define AVIVO_I2C_STATUS_NACK (1 << 1) +# define AVIVO_I2C_STATUS_HALT (1 << 2) +# define AVIVO_I2C_STATUS_GO (1 << 3) +# define AVIVO_I2C_STATUS_MASK 0x7 +/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe + * DONE? */ +# define AVIVO_I2C_STATUS_CMD_RESET 0x7 +# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) +#define AVIVO_I2C_STOP 0x7d34 +#define AVIVO_I2C_START_CNTL 0x7d38 +# define AVIVO_I2C_START (1 << 8) +# define AVIVO_I2C_CONNECTOR0 (0 << 16) +# define AVIVO_I2C_CONNECTOR1 (1 << 16) +#define R520_I2C_START (1<<0) +#define R520_I2C_STOP (1<<1) +#define R520_I2C_RX (1<<2) +#define R520_I2C_EN (1<<8) +#define R520_I2C_DDC1 (0<<16) +#define R520_I2C_DDC2 (1<<16) +#define R520_I2C_DDC3 (2<<16) +#define R520_I2C_DDC_MASK (3<<16) +#define AVIVO_I2C_CONTROL2 0x7d3c +# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 +# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) +#define AVIVO_I2C_CONTROL3 0x7d40 +/* Reading is done 4 bytes at a time: read the bottom 8 bits from + * 7d44, four times in a row. + * Writing is a little more complex. First write DATA with + * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic + * magic number, zz is, I think, the slave address, and yy is the byte + * you want to write. */ +#define AVIVO_I2C_DATA 0x7d44 +#define R520_I2C_ADDR_COUNT_MASK (0x7) +#define R520_I2C_DATA_COUNT_SHIFT (8) +#define R520_I2C_DATA_COUNT_MASK (0xF00) +#define AVIVO_I2C_CNTL 0x7d50 +# define AVIVO_I2C_EN (1 << 0) +# define AVIVO_I2C_RESET (1 << 8) + +#define R600_GENERAL_PWRMGT 0x618 +# define R600_OPEN_DRAIN_PADS (1 << 11) + +#define R600_LOWER_GPIO_ENABLE 0x710 +#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 +#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c +#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 +#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 + +#define R600_MC_VM_FB_LOCATION 0x2180 +#define R600_MC_VM_AGP_TOP 0x2184 +#define R600_MC_VM_AGP_BOT 0x2188 +#define R600_MC_VM_AGP_BASE 0x218c +#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 +#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 +#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 + +#define R700_MC_VM_FB_LOCATION 0x2024 +#define R700_MC_VM_AGP_TOP 0x2028 +#define R700_MC_VM_AGP_BOT 0x202c +#define R700_MC_VM_AGP_BASE 0x2030 + +#define R600_HDP_NONSURFACE_BASE 0x2c04 + +#define R600_BUS_CNTL 0x5420 +#define R600_CONFIG_CNTL 0x5424 +#define R600_CONFIG_MEMSIZE 0x5428 +#define R600_CONFIG_F0_BASE 0x542C +#define R600_CONFIG_APER_SIZE 0x5430 + +#define R600_ROM_CNTL 0x1600 +# define R600_SCK_OVERWRITE (1 << 1) +# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 +# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) + +#define R600_CG_SPLL_FUNC_CNTL 0x600 +# define R600_SPLL_BYPASS_EN (1 << 3) +#define R600_CG_SPLL_STATUS 0x60c +# define R600_SPLL_CHG_STATUS (1 << 1) + +#define R600_BIOS_0_SCRATCH 0x1724 +#define R600_BIOS_1_SCRATCH 0x1728 +#define R600_BIOS_2_SCRATCH 0x172c +#define R600_BIOS_3_SCRATCH 0x1730 +#define R600_BIOS_4_SCRATCH 0x1734 +#define R600_BIOS_5_SCRATCH 0x1738 +#define R600_BIOS_6_SCRATCH 0x173c +#define R600_BIOS_7_SCRATCH 0x1740 + +/* evergreen */ +#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 +#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 +#define EVERGREEN_D3VGA_CONTROL 0x3e0 +#define EVERGREEN_D4VGA_CONTROL 0x3e4 +#define EVERGREEN_D5VGA_CONTROL 0x3e8 +#define EVERGREEN_D6VGA_CONTROL 0x3ec + +#define EVERGREEN_P1PLL_SS_CNTL 0x414 +#define EVERGREEN_P2PLL_SS_CNTL 0x454 +# define EVERGREEN_PxPLL_SS_EN (1 << 12) +/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ +#define EVERGREEN_GRPH_ENABLE 0x6800 +#define EVERGREEN_GRPH_CONTROL 0x6804 +# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) +# define EVERGREEN_GRPH_DEPTH_8BPP 0 +# define EVERGREEN_GRPH_DEPTH_16BPP 1 +# define EVERGREEN_GRPH_DEPTH_32BPP 2 +# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) +/* 8 BPP */ +# define EVERGREEN_GRPH_FORMAT_INDEXED 0 +/* 16 BPP */ +# define EVERGREEN_GRPH_FORMAT_ARGB1555 0 +# define EVERGREEN_GRPH_FORMAT_ARGB565 1 +# define EVERGREEN_GRPH_FORMAT_ARGB4444 2 +# define EVERGREEN_GRPH_FORMAT_AI88 3 +# define EVERGREEN_GRPH_FORMAT_MONO16 4 +# define EVERGREEN_GRPH_FORMAT_BGRA5551 5 +/* 32 BPP */ +# define EVERGREEN_GRPH_FORMAT_ARGB8888 0 +# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 +# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 +# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 +# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 +# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 +# define EVERGREEN_GRPH_FORMAT_RGB111110 6 +# define EVERGREEN_GRPH_FORMAT_BGR101111 7 +#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c +# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) +# define EVERGREEN_GRPH_ENDIAN_NONE 0 +# define EVERGREEN_GRPH_ENDIAN_8IN16 1 +# define EVERGREEN_GRPH_ENDIAN_8IN32 2 +# define EVERGREEN_GRPH_ENDIAN_8IN64 3 +# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) +# define EVERGREEN_GRPH_RED_SEL_R 0 +# define EVERGREEN_GRPH_RED_SEL_G 1 +# define EVERGREEN_GRPH_RED_SEL_B 2 +# define EVERGREEN_GRPH_RED_SEL_A 3 +# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) +# define EVERGREEN_GRPH_GREEN_SEL_G 0 +# define EVERGREEN_GRPH_GREEN_SEL_B 1 +# define EVERGREEN_GRPH_GREEN_SEL_A 2 +# define EVERGREEN_GRPH_GREEN_SEL_R 3 +# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) +# define EVERGREEN_GRPH_BLUE_SEL_B 0 +# define EVERGREEN_GRPH_BLUE_SEL_A 1 +# define EVERGREEN_GRPH_BLUE_SEL_R 2 +# define EVERGREEN_GRPH_BLUE_SEL_G 3 +# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) +# define EVERGREEN_GRPH_ALPHA_SEL_A 0 +# define EVERGREEN_GRPH_ALPHA_SEL_R 1 +# define EVERGREEN_GRPH_ALPHA_SEL_G 2 +# define EVERGREEN_GRPH_ALPHA_SEL_B 3 +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 +# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) +# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 +#define EVERGREEN_GRPH_PITCH 0x6818 +#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c +#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 +#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 +#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 +#define EVERGREEN_GRPH_X_START 0x682c +#define EVERGREEN_GRPH_Y_START 0x6830 +#define EVERGREEN_GRPH_X_END 0x6834 +#define EVERGREEN_GRPH_Y_END 0x6838 + +/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ +#define EVERGREEN_CUR_CONTROL 0x6998 +# define EVERGREEN_CURSOR_EN (1 << 0) +# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) +# define EVERGREEN_CURSOR_MONO 0 +# define EVERGREEN_CURSOR_24_1 1 +# define EVERGREEN_CURSOR_24_8_PRE_MULT 2 +# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 +# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) +# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) +# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) +# define EVERGREEN_CURSOR_URGENT_ALWAYS 0 +# define EVERGREEN_CURSOR_URGENT_1_8 1 +# define EVERGREEN_CURSOR_URGENT_1_4 2 +# define EVERGREEN_CURSOR_URGENT_3_8 3 +# define EVERGREEN_CURSOR_URGENT_1_2 4 +#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c +# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 +#define EVERGREEN_CUR_SIZE 0x69a0 +#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 +#define EVERGREEN_CUR_POSITION 0x69a8 +#define EVERGREEN_CUR_HOT_SPOT 0x69ac +#define EVERGREEN_CUR_COLOR1 0x69b0 +#define EVERGREEN_CUR_COLOR2 0x69b4 +#define EVERGREEN_CUR_UPDATE 0x69b8 +# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) +# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) +# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) +# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) + +/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ +#define EVERGREEN_DC_LUT_RW_MODE 0x69e0 +#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 +#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 +#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec +#define EVERGREEN_DC_LUT_30_COLOR 0x69f0 +#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 +#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 +#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc +#define EVERGREEN_DC_LUT_CONTROL 0x6a00 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 +#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c +#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 +#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 +#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 + +#define EVERGREEN_DATA_FORMAT 0x6b00 +# define EVERGREEN_INTERLEAVE_EN (1 << 0) +#define EVERGREEN_DESKTOP_HEIGHT 0x6b04 + +#define EVERGREEN_VIEWPORT_START 0x6d70 +#define EVERGREEN_VIEWPORT_SIZE 0x6d74 + +/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ +#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) +#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) +#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) +#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) +#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) +#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) + +/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ +#define EVERGREEN_CRTC_CONTROL 0x6e70 +# define EVERGREEN_CRTC_MASTER_EN (1 << 0) +#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 + +#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 +#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 +#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 +#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc + +#define R300_GB_TILE_CONFIG 0x4018 +# define R300_ENABLE_TILING (1 << 0) +# define R300_PIPE_COUNT_RV350 (0 << 1) +# define R300_PIPE_COUNT_R300 (3 << 1) +# define R300_PIPE_COUNT_R420_3P (6 << 1) +# define R300_PIPE_COUNT_R420 (7 << 1) +# define R300_TILE_SIZE_8 (0 << 4) +# define R300_TILE_SIZE_16 (1 << 4) +# define R300_TILE_SIZE_32 (2 << 4) +# define R300_SUBPIXEL_1_12 (0 << 16) +# define R300_SUBPIXEL_1_16 (1 << 16) +#define R300_GB_SELECT 0x401c +#define R300_GB_ENABLE 0x4008 +#define R300_GB_AA_CONFIG 0x4020 +#define R400_GB_PIPE_SELECT 0x402c +#define R300_GB_MSPOS0 0x4010 +# define R300_MS_X0_SHIFT 0 +# define R300_MS_Y0_SHIFT 4 +# define R300_MS_X1_SHIFT 8 +# define R300_MS_Y1_SHIFT 12 +# define R300_MS_X2_SHIFT 16 +# define R300_MS_Y2_SHIFT 20 +# define R300_MSBD0_Y_SHIFT 24 +# define R300_MSBD0_X_SHIFT 28 +#define R300_GB_MSPOS1 0x4014 +# define R300_MS_X3_SHIFT 0 +# define R300_MS_Y3_SHIFT 4 +# define R300_MS_X4_SHIFT 8 +# define R300_MS_Y4_SHIFT 12 +# define R300_MS_X5_SHIFT 16 +# define R300_MS_Y5_SHIFT 20 +# define R300_MSBD1_SHIFT 24 + +#define R300_GA_ENHANCE 0x4274 +# define R300_GA_DEADLOCK_CNTL (1 << 0) +# define R300_GA_FASTSYNC_CNTL (1 << 1) + +#define R300_GA_POLY_MODE 0x4288 +# define R300_FRONT_PTYPE_POINT (0 << 4) +# define R300_FRONT_PTYPE_LINE (1 << 4) +# define R300_FRONT_PTYPE_TRIANGE (2 << 4) +# define R300_BACK_PTYPE_POINT (0 << 7) +# define R300_BACK_PTYPE_LINE (1 << 7) +# define R300_BACK_PTYPE_TRIANGE (2 << 7) +#define R300_GA_ROUND_MODE 0x428c +# define R300_GEOMETRY_ROUND_TRUNC (0 << 0) +# define R300_GEOMETRY_ROUND_NEAREST (1 << 0) +# define R300_COLOR_ROUND_TRUNC (0 << 2) +# define R300_COLOR_ROUND_NEAREST (1 << 2) +#define R300_GA_COLOR_CONTROL 0x4278 +# define R300_RGB0_SHADING_SOLID (0 << 0) +# define R300_RGB0_SHADING_FLAT (1 << 0) +# define R300_RGB0_SHADING_GOURAUD (2 << 0) +# define R300_ALPHA0_SHADING_SOLID (0 << 2) +# define R300_ALPHA0_SHADING_FLAT (1 << 2) +# define R300_ALPHA0_SHADING_GOURAUD (2 << 2) +# define R300_RGB1_SHADING_SOLID (0 << 4) +# define R300_RGB1_SHADING_FLAT (1 << 4) +# define R300_RGB1_SHADING_GOURAUD (2 << 4) +# define R300_ALPHA1_SHADING_SOLID (0 << 6) +# define R300_ALPHA1_SHADING_FLAT (1 << 6) +# define R300_ALPHA1_SHADING_GOURAUD (2 << 6) +# define R300_RGB2_SHADING_SOLID (0 << 8) +# define R300_RGB2_SHADING_FLAT (1 << 8) +# define R300_RGB2_SHADING_GOURAUD (2 << 8) +# define R300_ALPHA2_SHADING_SOLID (0 << 10) +# define R300_ALPHA2_SHADING_FLAT (1 << 10) +# define R300_ALPHA2_SHADING_GOURAUD (2 << 10) +# define R300_RGB3_SHADING_SOLID (0 << 12) +# define R300_RGB3_SHADING_FLAT (1 << 12) +# define R300_RGB3_SHADING_GOURAUD (2 << 12) +# define R300_ALPHA3_SHADING_SOLID (0 << 14) +# define R300_ALPHA3_SHADING_FLAT (1 << 14) +# define R300_ALPHA3_SHADING_GOURAUD (2 << 14) +#define R300_GA_OFFSET 0x4290 + +#define R500_SU_REG_DEST 0x42c8 + +#define R300_VAP_CNTL_STATUS 0x2140 +# define R300_PVS_BYPASS (1 << 8) +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 +#define R300_VAP_CNTL 0x2080 +# define R300_PVS_NUM_SLOTS_SHIFT 0 +# define R300_PVS_NUM_CNTLRS_SHIFT 4 +# define R300_PVS_NUM_FPUS_SHIFT 8 +# define R300_VF_MAX_VTX_NUM_SHIFT 18 +# define R300_GL_CLIP_SPACE_DEF (0 << 22) +# define R300_DX_CLIP_SPACE_DEF (1 << 22) +# define R500_TCL_STATE_OPTIMIZATION (1 << 23) +#define R300_VAP_VTE_CNTL 0x20B0 +# define R300_VPORT_X_SCALE_ENA (1 << 0) +# define R300_VPORT_X_OFFSET_ENA (1 << 1) +# define R300_VPORT_Y_SCALE_ENA (1 << 2) +# define R300_VPORT_Y_OFFSET_ENA (1 << 3) +# define R300_VPORT_Z_SCALE_ENA (1 << 4) +# define R300_VPORT_Z_OFFSET_ENA (1 << 5) +# define R300_VTX_XY_FMT (1 << 8) +# define R300_VTX_Z_FMT (1 << 9) +# define R300_VTX_W0_FMT (1 << 10) +#define R300_VAP_VTX_STATE_CNTL 0x2180 +#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC +#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 +# define R300_DATA_TYPE_0_SHIFT 0 +# define R300_DATA_TYPE_FLOAT_1 0 +# define R300_DATA_TYPE_FLOAT_2 1 +# define R300_DATA_TYPE_FLOAT_3 2 +# define R300_DATA_TYPE_FLOAT_4 3 +# define R300_DATA_TYPE_BYTE 4 +# define R300_DATA_TYPE_D3DCOLOR 5 +# define R300_DATA_TYPE_SHORT_2 6 +# define R300_DATA_TYPE_SHORT_4 7 +# define R300_DATA_TYPE_VECTOR_3_TTT 8 +# define R300_DATA_TYPE_VECTOR_3_EET 9 +# define R300_SKIP_DWORDS_0_SHIFT 4 +# define R300_DST_VEC_LOC_0_SHIFT 8 +# define R300_LAST_VEC_0 (1 << 13) +# define R300_SIGNED_0 (1 << 14) +# define R300_NORMALIZE_0 (1 << 15) +# define R300_DATA_TYPE_1_SHIFT 16 +# define R300_SKIP_DWORDS_1_SHIFT 20 +# define R300_DST_VEC_LOC_1_SHIFT 24 +# define R300_LAST_VEC_1 (1 << 29) +# define R300_SIGNED_1 (1 << 30) +# define R300_NORMALIZE_1 (1 << 31) +#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 +# define R300_DATA_TYPE_2_SHIFT 0 +# define R300_SKIP_DWORDS_2_SHIFT 4 +# define R300_DST_VEC_LOC_2_SHIFT 8 +# define R300_LAST_VEC_2 (1 << 13) +# define R300_SIGNED_2 (1 << 14) +# define R300_NORMALIZE_2 (1 << 15) +# define R300_DATA_TYPE_3_SHIFT 16 +# define R300_SKIP_DWORDS_3_SHIFT 20 +# define R300_DST_VEC_LOC_3_SHIFT 24 +# define R300_LAST_VEC_3 (1 << 29) +# define R300_SIGNED_3 (1 << 30) +# define R300_NORMALIZE_3 (1 << 31) +#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 +# define R300_SWIZZLE_SELECT_X_0_SHIFT 0 +# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 +# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 +# define R300_SWIZZLE_SELECT_W_0_SHIFT 9 +# define R300_SWIZZLE_SELECT_X 0 +# define R300_SWIZZLE_SELECT_Y 1 +# define R300_SWIZZLE_SELECT_Z 2 +# define R300_SWIZZLE_SELECT_W 3 +# define R300_SWIZZLE_SELECT_FP_ZERO 4 +# define R300_SWIZZLE_SELECT_FP_ONE 5 +# define R300_WRITE_ENA_0_SHIFT 12 +# define R300_WRITE_ENA_X 1 +# define R300_WRITE_ENA_Y 2 +# define R300_WRITE_ENA_Z 4 +# define R300_WRITE_ENA_W 8 +# define R300_SWIZZLE_SELECT_X_1_SHIFT 16 +# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 +# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 +# define R300_SWIZZLE_SELECT_W_1_SHIFT 25 +# define R300_WRITE_ENA_1_SHIFT 28 +#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 +# define R300_SWIZZLE_SELECT_X_2_SHIFT 0 +# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 +# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 +# define R300_SWIZZLE_SELECT_W_2_SHIFT 9 +# define R300_WRITE_ENA_2_SHIFT 12 +# define R300_SWIZZLE_SELECT_X_3_SHIFT 16 +# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 +# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 +# define R300_SWIZZLE_SELECT_W_3_SHIFT 25 +# define R300_WRITE_ENA_3_SHIFT 28 +#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 +# define R300_PVS_FIRST_INST_SHIFT 0 +# define R300_PVS_XYZW_VALID_INST_SHIFT 10 +# define R300_PVS_LAST_INST_SHIFT 20 +#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 +# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 +#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 +# define R300_PVS_CODE_START 0 +# define R300_PVS_CONST_START 512 +# define R500_PVS_CONST_START 1024 +# define R300_PVS_VECTOR_INST_INDEX(x) ((x) + R300_PVS_CODE_START) +# define R300_PVS_VECTOR_CONST_INDEX(x) ((x) + R300_PVS_CONST_START) +# define R500_PVS_VECTOR_CONST_INDEX(x) ((x) + R500_PVS_CONST_START) +#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 +/* PVS instructions */ +/* Opcode and dst instruction */ +#define R300_PVS_DST_OPCODE(x) ((x) << 0) +/* Vector ops */ +# define R300_VECTOR_NO_OP 0 +# define R300_VE_DOT_PRODUCT 1 +# define R300_VE_MULTIPLY 2 +# define R300_VE_ADD 3 +# define R300_VE_MULTIPLY_ADD 4 +# define R300_VE_DISTANCE_VECTOR 5 +# define R300_VE_FRACTION 6 +# define R300_VE_MAXIMUM 7 +# define R300_VE_MINIMUM 8 +# define R300_VE_SET_GREATER_THAN_EQUAL 9 +# define R300_VE_SET_LESS_THAN 10 +# define R300_VE_MULTIPLYX2_ADD 11 +# define R300_VE_MULTIPLY_CLAMP 12 +# define R300_VE_FLT2FIX_DX 13 +# define R300_VE_FLT2FIX_DX_RND 14 +/* R500 additions */ +# define R500_VE_PRED_SET_EQ_PUSH 15 +# define R500_VE_PRED_SET_GT_PUSH 16 +# define R500_VE_PRED_SET_GTE_PUSH 17 +# define R500_VE_PRED_SET_NEQ_PUSH 18 +# define R500_VE_COND_WRITE_EQ 19 +# define R500_VE_COND_WRITE_GT 20 +# define R500_VE_COND_WRITE_GTE 21 +# define R500_VE_COND_WRITE_NEQ 22 +# define R500_VE_COND_MUX_EQ 23 +# define R500_VE_COND_MUX_GT 24 +# define R500_VE_COND_MUX_GTE 25 +# define R500_VE_SET_GREATER_THAN 26 +# define R500_VE_SET_EQUAL 27 +# define R500_VE_SET_NOT_EQUAL 28 +/* Math ops */ +# define R300_MATH_NO_OP 0 +# define R300_ME_EXP_BASE2_DX 1 +# define R300_ME_LOG_BASE2_DX 2 +# define R300_ME_EXP_BASEE_FF 3 +# define R300_ME_LIGHT_COEFF_DX 4 +# define R300_ME_POWER_FUNC_FF 5 +# define R300_ME_RECIP_DX 6 +# define R300_ME_RECIP_FF 7 +# define R300_ME_RECIP_SQRT_DX 8 +# define R300_ME_RECIP_SQRT_FF 9 +# define R300_ME_MULTIPLY 10 +# define R300_ME_EXP_BASE2_FULL_DX 11 +# define R300_ME_LOG_BASE2_FULL_DX 12 +# define R300_ME_POWER_FUNC_FF_CLAMP_B 13 +# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 +# define R300_ME_POWER_FUNC_FF_CLAMP_01 15 +# define R300_ME_SIN 16 +# define R300_ME_COS 17 +/* R500 additions */ +# define R500_ME_LOG_BASE2_IEEE 18 +# define R500_ME_RECIP_IEEE 19 +# define R500_ME_RECIP_SQRT_IEEE 20 +# define R500_ME_PRED_SET_EQ 21 +# define R500_ME_PRED_SET_GT 22 +# define R500_ME_PRED_SET_GTE 23 +# define R500_ME_PRED_SET_NEQ 24 +# define R500_ME_PRED_SET_CLR 25 +# define R500_ME_PRED_SET_INV 26 +# define R500_ME_PRED_SET_POP 27 +# define R500_ME_PRED_SET_RESTORE 28 +/* macro */ +# define R300_PVS_MACRO_OP_2CLK_MADD 0 +# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 +#define R300_PVS_DST_MATH_INST (1 << 6) +#define R300_PVS_DST_MACRO_INST (1 << 7) +#define R300_PVS_DST_REG_TYPE(x) ((x) << 8) +# define R300_PVS_DST_REG_TEMPORARY 0 +# define R300_PVS_DST_REG_A0 1 +# define R300_PVS_DST_REG_OUT 2 +# define R500_PVS_DST_REG_OUT_REPL_X 3 +# define R300_PVS_DST_REG_ALT_TEMPORARY 4 +# define R300_PVS_DST_REG_INPUT 5 +#define R300_PVS_DST_ADDR_MODE_1 (1 << 12) +#define R300_PVS_DST_OFFSET(x) ((x) << 13) +#define R300_PVS_DST_WE_X (1 << 20) +#define R300_PVS_DST_WE_Y (1 << 21) +#define R300_PVS_DST_WE_Z (1 << 22) +#define R300_PVS_DST_WE_W (1 << 23) +#define R300_PVS_DST_VE_SAT (1 << 24) +#define R300_PVS_DST_ME_SAT (1 << 25) +#define R300_PVS_DST_PRED_ENABLE (1 << 26) +#define R300_PVS_DST_PRED_SENSE (1 << 27) +#define R300_PVS_DST_DUAL_MATH_OP (1 << 28) +#define R300_PVS_DST_ADDR_SEL(x) ((x) << 29) +#define R300_PVS_DST_ADDR_MODE_0 (1 << 31) +/* src operand instruction */ +#define R300_PVS_SRC_REG_TYPE(x) ((x) << 0) +# define R300_PVS_SRC_REG_TEMPORARY 0 +# define R300_PVS_SRC_REG_INPUT 1 +# define R300_PVS_SRC_REG_CONSTANT 2 +# define R300_PVS_SRC_REG_ALT_TEMPORARY 3 +#define R300_SPARE_0 (1 << 2) +#define R300_PVS_SRC_ABS_XYZW (1 << 3) +#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) +#define R300_PVS_SRC_OFFSET(x) ((x) << 5) +#define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13) +#define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16) +#define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19) +#define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22) +# define R300_PVS_SRC_SELECT_X 0 +# define R300_PVS_SRC_SELECT_Y 1 +# define R300_PVS_SRC_SELECT_Z 2 +# define R300_PVS_SRC_SELECT_W 3 +# define R300_PVS_SRC_SELECT_FORCE_0 4 +# define R300_PVS_SRC_SELECT_FORCE_1 5 +#define R300_PVS_SRC_NEG_X (1 << 25) +#define R300_PVS_SRC_NEG_Y (1 << 26) +#define R300_PVS_SRC_NEG_Z (1 << 27) +#define R300_PVS_SRC_NEG_W (1 << 28) +#define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29) +#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) + +#define R300_VAP_PVS_CONST_CNTL 0x22d4 +# define R300_PVS_CONST_BASE_OFFSET(x) ((x) << 0) +# define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16) + +#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc +#define R300_VAP_OUT_VTX_FMT_0 0x2090 +# define R300_VTX_POS_PRESENT (1 << 0) +# define R300_VTX_COLOR_0_PRESENT (1 << 1) +# define R300_VTX_COLOR_1_PRESENT (1 << 2) +# define R300_VTX_COLOR_2_PRESENT (1 << 3) +# define R300_VTX_COLOR_3_PRESENT (1 << 4) +# define R300_VTX_PT_SIZE_PRESENT (1 << 16) +#define R300_VAP_OUT_VTX_FMT_1 0x2094 +# define R300_TEX_0_COMP_CNT_SHIFT 0 +# define R300_TEX_1_COMP_CNT_SHIFT 3 +# define R300_TEX_2_COMP_CNT_SHIFT 6 +# define R300_TEX_3_COMP_CNT_SHIFT 9 +# define R300_TEX_4_COMP_CNT_SHIFT 12 +# define R300_TEX_5_COMP_CNT_SHIFT 15 +# define R300_TEX_6_COMP_CNT_SHIFT 18 +# define R300_TEX_7_COMP_CNT_SHIFT 21 +#define R300_VAP_VTX_SIZE 0x20b4 +#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 +#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 +#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 +#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c +#define R300_VAP_CLIP_CNTL 0x221c +# define R300_UCP_ENA_0 (1 << 0) +# define R300_UCP_ENA_1 (1 << 1) +# define R300_UCP_ENA_2 (1 << 2) +# define R300_UCP_ENA_3 (1 << 3) +# define R300_UCP_ENA_4 (1 << 4) +# define R300_UCP_ENA_5 (1 << 5) +# define R300_PS_UCP_MODE_SHIFT 14 +# define R300_CLIP_DISABLE (1 << 16) +# define R300_UCP_CULL_ONLY_ENA (1 << 17) +# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 + +#define R500_VAP_INDEX_OFFSET 0x208c + +#define R300_SU_TEX_WRAP 0x42a0 +#define R300_SU_POLY_OFFSET_ENABLE 0x42b4 +#define R300_SU_CULL_MODE 0x42b8 +# define R300_CULL_FRONT (1 << 0) +# define R300_CULL_BACK (1 << 1) +# define R300_FACE_POS (0 << 2) +# define R300_FACE_NEG (1 << 2) +#define R300_SU_DEPTH_SCALE 0x42c0 +#define R300_SU_DEPTH_OFFSET 0x42c4 + +#define R300_RS_COUNT 0x4300 +# define R300_RS_COUNT_IT_COUNT_SHIFT 0 +# define R300_RS_COUNT_IC_COUNT_SHIFT 7 +# define R300_RS_COUNT_HIRES_EN (1 << 18) + +#define R300_RS_IP_0 0x4310 +#define R300_RS_IP_1 0x4314 +# define R300_RS_TEX_PTR(x) ((x) << 0) +# define R300_RS_COL_PTR(x) ((x) << 6) +# define R300_RS_COL_FMT(x) ((x) << 9) +# define R300_RS_COL_FMT_RGBA 0 +# define R300_RS_COL_FMT_RGB0 2 +# define R300_RS_COL_FMT_RGB1 3 +# define R300_RS_COL_FMT_000A 4 +# define R300_RS_COL_FMT_0000 5 +# define R300_RS_COL_FMT_0001 6 +# define R300_RS_COL_FMT_111A 8 +# define R300_RS_COL_FMT_1110 9 +# define R300_RS_COL_FMT_1111 10 +# define R300_RS_SEL_S(x) ((x) << 13) +# define R300_RS_SEL_T(x) ((x) << 16) +# define R300_RS_SEL_R(x) ((x) << 19) +# define R300_RS_SEL_Q(x) ((x) << 22) +# define R300_RS_SEL_C0 0 +# define R300_RS_SEL_C1 1 +# define R300_RS_SEL_C2 2 +# define R300_RS_SEL_C3 3 +# define R300_RS_SEL_K0 4 +# define R300_RS_SEL_K1 5 +#define R300_RS_INST_COUNT 0x4304 +# define R300_INST_COUNT_RS(x) ((x) << 0) +# define R300_RS_W_EN (1 << 4) +# define R300_TX_OFFSET_RS(x) ((x) << 5) +#define R300_RS_INST_0 0x4330 +#define R300_RS_INST_1 0x4334 +# define R300_INST_TEX_ID(x) ((x) << 0) +# define R300_RS_INST_TEX_CN_WRITE (1 << 3) +# define R300_INST_TEX_ADDR(x) ((x) << 6) + +#define R300_TX_INVALTAGS 0x4100 +#define R300_TX_FILTER0_0 0x4400 +#define R300_TX_FILTER0_1 0x4404 +#define R300_TX_FILTER0_2 0x4408 +# define R300_TX_CLAMP_S(x) ((x) << 0) +# define R300_TX_CLAMP_T(x) ((x) << 3) +# define R300_TX_CLAMP_R(x) ((x) << 6) +# define R300_TX_CLAMP_WRAP 0 +# define R300_TX_CLAMP_MIRROR 1 +# define R300_TX_CLAMP_CLAMP_LAST 2 +# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 +# define R300_TX_CLAMP_CLAMP_BORDER 4 +# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 +# define R300_TX_CLAMP_CLAMP_GL 6 +# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 +# define R300_TX_MAG_FILTER_NEAREST (1 << 9) +# define R300_TX_MIN_FILTER_NEAREST (1 << 11) +# define R300_TX_MAG_FILTER_LINEAR (2 << 9) +# define R300_TX_MIN_FILTER_LINEAR (2 << 11) +# define R300_TX_ID_SHIFT 28 +#define R300_TX_FILTER1_0 0x4440 +#define R300_TX_FILTER1_1 0x4444 +#define R300_TX_FILTER1_2 0x4448 +#define R300_TX_FORMAT0_0 0x4480 +#define R300_TX_FORMAT0_1 0x4484 +#define R300_TX_FORMAT0_2 0x4488 +# define R300_TXWIDTH_SHIFT 0 +# define R300_TXHEIGHT_SHIFT 11 +# define R300_NUM_LEVELS_SHIFT 26 +# define R300_NUM_LEVELS_MASK 0x +# define R300_TXPROJECTED (1 << 30) +# define R300_TXPITCH_EN (1 << 31) +#define R300_TX_FORMAT1_0 0x44c0 +#define R300_TX_FORMAT1_1 0x44c4 +#define R300_TX_FORMAT1_2 0x44c8 +# define R300_TX_FORMAT_X8 0x0 +# define R300_TX_FORMAT_X16 0x1 +# define R300_TX_FORMAT_Y4X4 0x2 +# define R300_TX_FORMAT_Y8X8 0x3 +# define R300_TX_FORMAT_Y16X16 0x4 +# define R300_TX_FORMAT_Z3Y3X2 0x5 +# define R300_TX_FORMAT_Z5Y6X5 0x6 +# define R300_TX_FORMAT_Z6Y5X5 0x7 +# define R300_TX_FORMAT_Z11Y11X10 0x8 +# define R300_TX_FORMAT_Z10Y11X11 0x9 +# define R300_TX_FORMAT_W4Z4Y4X4 0xA +# define R300_TX_FORMAT_W1Z5Y5X5 0xB +# define R300_TX_FORMAT_W8Z8Y8X8 0xC +# define R300_TX_FORMAT_W2Z10Y10X10 0xD +# define R300_TX_FORMAT_W16Z16Y16X16 0xE +# define R300_TX_FORMAT_DXT1 0xF +# define R300_TX_FORMAT_DXT3 0x10 +# define R300_TX_FORMAT_DXT5 0x11 +# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ +# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ +# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ +# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ +# define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ +# define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ +# define R300_TX_FORMAT_X24_Y8 0x1e +# define R300_TX_FORMAT_X32 0x1e + /* Floating point formats */ + /* Note - hardware supports both 16 and 32 bit floating point */ +# define R300_TX_FORMAT_FL_I16 0x18 +# define R300_TX_FORMAT_FL_I16A16 0x19 +# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A +# define R300_TX_FORMAT_FL_I32 0x1B +# define R300_TX_FORMAT_FL_I32A32 0x1C +# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D + /* alpha modes, convenience mostly */ + /* if you have alpha, pick constant appropriate to the + number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ +# define R300_TX_FORMAT_ALPHA_1CH 0x000 +# define R300_TX_FORMAT_ALPHA_2CH 0x200 +# define R300_TX_FORMAT_ALPHA_4CH 0x600 +# define R300_TX_FORMAT_ALPHA_NONE 0xA00 + /* Swizzling */ + /* constants */ +# define R300_TX_FORMAT_X 0 +# define R300_TX_FORMAT_Y 1 +# define R300_TX_FORMAT_Z 2 +# define R300_TX_FORMAT_W 3 +# define R300_TX_FORMAT_ZERO 4 +# define R300_TX_FORMAT_ONE 5 + /* 2.0*Z, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_Z 6 + /* 2.0*W, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_W 7 + +# define R300_TX_FORMAT_B_SHIFT 18 +# define R300_TX_FORMAT_G_SHIFT 15 +# define R300_TX_FORMAT_R_SHIFT 12 +# define R300_TX_FORMAT_A_SHIFT 9 + + /* Convenience macro to take care of layout and swizzling */ +# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ + ((R300_TX_FORMAT_##B)<Revision == 0) + return acpi_addr; + } + } + } + return NULL; +} + +/* Gets the ACPI 2.0 RSDP address */ +static struct acpi_2_rsdp* getAddressOfAcpi20Table() +{ + /* TODO: Before searching the BIOS space we are supposed to search the first 1K of the EBDA */ + + void *acpi_addr = (void*)ACPI_RANGE_START; + for(; acpi_addr <= (void*)ACPI_RANGE_END; acpi_addr += 16) + { + if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE) + { + uint8_t csum = checksum8(acpi_addr, 20); + + /* Only assume this is a 2.0 or better table if the revision is greater than 0 + * NOTE: ACPI 3.0 spec only seems to say that 1.0 tables have revision 1 + * and that the current revision is 2.. I am going to assume that rev > 0 is 2.0. + */ + + if(csum == 0 && (((struct acpi_2_rsdp*)acpi_addr)->Revision > 0)) + { + uint8_t csum2 = checksum8(acpi_addr, sizeof(struct acpi_2_rsdp)); + if(csum2 == 0) + return acpi_addr; + } + } + } + return NULL; +} +/** The folowing ACPI Table search algo. should be reused anywhere needed:*/ +int search_and_get_acpi_fd(const char * filename, const char ** outDirspec) +{ + int fd = 0; + char dirSpec[512] = ""; + + // Try finding 'filename' in the usual places + // Start searching any potential location for ACPI Table + sprintf(dirSpec, "%s", filename); + fd = open(dirSpec, 0); + if (fd < 0) + { + sprintf(dirSpec, "/Extra/%s", filename); + fd = open(dirSpec, 0); + if (fd < 0) + { + sprintf(dirSpec, "bt(0,0)/Extra/%s", filename); + fd = open(dirSpec, 0); + } + } + + if (fd < 0) + { + // NOT FOUND: + verbose("ACPI table not found: %s\n", filename); + *dirSpec = '\0'; + } + + if (outDirspec) *outDirspec = dirSpec; + return fd; +} + + +void *loadACPITable (const char * filename) +{ + void *tableAddr; + const char * dirspec=NULL; + + int fd = search_and_get_acpi_fd(filename, &dirspec); + + if (fd>=0) + { + tableAddr=(void*)AllocateKernelMemory(file_size (fd)); + if (tableAddr) + { + if (read (fd, tableAddr, file_size (fd))!=file_size (fd)) + { + printf("Couldn't read table %s\n",dirspec); + free (tableAddr); + close (fd); + return NULL; + } + + DBG("Table %s read and stored at: %x\n", dirspec, tableAddr); + close (fd); + return tableAddr; + } + close (fd); + printf("Couldn't allocate memory for table \n", dirspec); + } + //printf("Couldn't find table %s\n", filename); + return NULL; +} + +uint8_t acpi_cpu_count = 0; +char* acpi_cpu_name[32]; + +void get_acpi_cpu_names(unsigned char* dsdt, uint32_t length) +{ + uint32_t i; + + for (i=0; i> 6); + + bool add_name = true; + + uint8_t j; + + for (j=0; j<4; j++) + { + char c = dsdt[offset+j]; + + if (!aml_isvalidchar(c)) + { + add_name = false; + verbose("Invalid character found in ProcessorOP 0x%x!\n", c); + break; + } + } + + if (add_name) + { + acpi_cpu_name[acpi_cpu_count] = malloc(4); + memcpy(acpi_cpu_name[acpi_cpu_count], dsdt+offset, 4); + i = offset + 5; + + verbose("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]); + + if (++acpi_cpu_count == 32) return; + } + } + } +} + +struct acpi_2_ssdt *generate_cst_ssdt(struct acpi_2_fadt* fadt) +{ + char ssdt_header[] = + { + 0x53, 0x53, 0x44, 0x54, 0xE7, 0x00, 0x00, 0x00, /* SSDT.... */ + 0x01, 0x17, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x41, /* ..PmRefA */ + 0x43, 0x70, 0x75, 0x43, 0x73, 0x74, 0x00, 0x00, /* CpuCst.. */ + 0x00, 0x10, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* ....INTL */ + 0x31, 0x03, 0x10, 0x20 /* 1.._ */ + }; + + char cstate_resource_template[] = + { + 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, + 0x01, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x79, 0x00 + }; + + if (Platform.CPU.Vendor != 0x756E6547) { + verbose ("Not an Intel platform: C-States will not be generated !!!\n"); + return NULL; + } + + if (fadt == NULL) { + verbose ("FACP not exists: C-States will not be generated !!!\n"); + return NULL; + } + + struct acpi_2_dsdt* dsdt = (void*)fadt->DSDT; + + if (dsdt == NULL) { + verbose ("DSDT not found: C-States will not be generated !!!\n"); + return NULL; + } + + if (acpi_cpu_count == 0) + get_acpi_cpu_names((void*)dsdt, dsdt->Length); + + if (acpi_cpu_count > 0) + { + bool c2_enabled = false; + bool c3_enabled = false; + bool c4_enabled = false; + + getBoolForKey(kEnableC2States, &c2_enabled, &bootInfo->bootConfig); + getBoolForKey(kEnableC3States, &c3_enabled, &bootInfo->bootConfig); + getBoolForKey(kEnableC4States, &c4_enabled, &bootInfo->bootConfig); + + c2_enabled = c2_enabled | (fadt->C2_Latency < 100); + c3_enabled = c3_enabled | (fadt->C3_Latency < 1000); + + unsigned char cstates_count = 1 + (c2_enabled ? 1 : 0) + (c3_enabled ? 1 : 0); + + struct aml_chunk* root = aml_create_node(NULL); + aml_add_buffer(root, ssdt_header, sizeof(ssdt_header)); // SSDT header + struct aml_chunk* scop = aml_add_scope(root, "\\_PR_"); + struct aml_chunk* name = aml_add_name(scop, "CST_"); + struct aml_chunk* pack = aml_add_package(name); + aml_add_byte(pack, cstates_count); + + struct aml_chunk* tmpl = aml_add_package(pack); + cstate_resource_template[11] = 0x00; // C1 + aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template)); + aml_add_byte(tmpl, 0x01); // C1 + aml_add_byte(tmpl, 0x01); // Latency + aml_add_word(tmpl, 0x03e8); // Power + + // C2 + if (c2_enabled) + { + tmpl = aml_add_package(pack); + cstate_resource_template[11] = 0x10; // C2 + aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template)); + aml_add_byte(tmpl, 0x02); // C2 + aml_add_byte(tmpl, fadt->C2_Latency); + aml_add_word(tmpl, 0x01f4); // Power + } + // C4 + if (c4_enabled) + { + tmpl = aml_add_package(pack); + cstate_resource_template[11] = 0x30; // C4 + aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template)); + aml_add_byte(tmpl, 0x04); // C4 + aml_add_word(tmpl, fadt->C3_Latency / 2); // TODO: right latency for C4 + aml_add_byte(tmpl, 0xfa); // Power + } + else + // C3 + if (c3_enabled) + { + tmpl = aml_add_package(pack); + cstate_resource_template[11] = 0x20; // C3 + aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template)); + aml_add_byte(tmpl, 0x03); // C3 + aml_add_word(tmpl, fadt->C3_Latency); + aml_add_word(tmpl, 0x015e); // Power + } + + + // Aliaces + int i; + for (i = 0; i < acpi_cpu_count; i++) + { + char name[9]; + sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]); + + scop = aml_add_scope(root, name); + aml_add_alias(scop, "CST_", "_CST"); + } + + aml_calculate_size(root); + + struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size); + + aml_write_node(root, (void*)ssdt, 0); + + ssdt->Length = root->Size; + ssdt->Checksum = 0; + ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length); + + aml_destroy_node(root); + + //dumpPhysAddr("C-States SSDT content: ", ssdt, ssdt->Length); + + verbose ("SSDT with CPU C-States generated successfully\n"); + + return ssdt; + } + else + { + verbose ("ACPI CPUs not found: C-States not generated !!!\n"); + } + + return NULL; +} + +struct acpi_2_ssdt *generate_pss_ssdt(struct acpi_2_dsdt* dsdt) +{ + char ssdt_header[] = + { + 0x53, 0x53, 0x44, 0x54, 0x7E, 0x00, 0x00, 0x00, /* SSDT.... */ + 0x01, 0x6A, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x00, /* ..PmRef. */ + 0x43, 0x70, 0x75, 0x50, 0x6D, 0x00, 0x00, 0x00, /* CpuPm... */ + 0x00, 0x30, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* .0..INTL */ + 0x31, 0x03, 0x10, 0x20, /* 1.._ */ + }; + + if (Platform.CPU.Vendor != 0x756E6547) { + verbose ("Not an Intel platform: P-States will not be generated !!!\n"); + return NULL; + } + + if (!(Platform.CPU.Features & CPU_FEATURE_MSR)) { + verbose ("Unsupported CPU: P-States will not be generated !!!\n"); + return NULL; + } + + if (acpi_cpu_count == 0) + get_acpi_cpu_names((void*)dsdt, dsdt->Length); + + if (acpi_cpu_count > 0) + { + struct p_state initial, maximum, minimum, p_states[32]; + uint8_t p_states_count = 0; + + // Retrieving P-States, ported from code by superhai (c) + switch (Platform.CPU.Family) { + case 0x06: + { + switch (Platform.CPU.Model) + { + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah + case CPU_MODEL_MEROM: // Merom + case CPU_MODEL_PENRYN: // Penryn + case CPU_MODEL_ATOM: // Intel Atom (45nm) + { + bool cpu_dynamic_fsb = false; + + if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27)) + { + wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28))); + delay(1); + cpu_dynamic_fsb = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28); + } + + bool cpu_noninteger_bus_ratio = (rdmsr64(MSR_IA32_PERF_STATUS) & (1ULL << 46)); + + initial.Control = rdmsr64(MSR_IA32_PERF_STATUS); + + maximum.Control = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 32) & 0x1F3F) | (0x4000 * cpu_noninteger_bus_ratio); + maximum.CID = ((maximum.FID & 0x1F) << 1) | cpu_noninteger_bus_ratio; + + minimum.FID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 24) & 0x1F) | (0x80 * cpu_dynamic_fsb); + minimum.VID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 48) & 0x3F); + + if (minimum.FID == 0) + { + uint64_t msr; + uint8_t i; + // Probe for lowest fid + for (i = maximum.FID; i >= 0x6; i--) + { + msr = rdmsr64(MSR_IA32_PERF_CONTROL); + wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (i << 8) | minimum.VID); + intel_waitforsts(); + minimum.FID = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0x1F; + delay(1); + } + + msr = rdmsr64(MSR_IA32_PERF_CONTROL); + wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID); + intel_waitforsts(); + } + + if (minimum.VID == maximum.VID) + { + uint64_t msr; + uint8_t i; + // Probe for lowest vid + for (i = maximum.VID; i > 0xA; i--) + { + msr = rdmsr64(MSR_IA32_PERF_CONTROL); + wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (minimum.FID << 8) | i); + intel_waitforsts(); + minimum.VID = rdmsr64(MSR_IA32_PERF_STATUS) & 0x3F; + delay(1); + } + + msr = rdmsr64(MSR_IA32_PERF_CONTROL); + wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID); + intel_waitforsts(); + } + + minimum.CID = ((minimum.FID & 0x1F) << 1) >> cpu_dynamic_fsb; + + // Sanity check + if (maximum.CID < minimum.CID) + { + DBG("Insane FID values!"); + p_states_count = 0; + } + else + { + // Finalize P-States + // Find how many P-States machine supports + p_states_count = maximum.CID - minimum.CID + 1; + + if (p_states_count > 32) + p_states_count = 32; + + uint8_t vidstep; + uint8_t i = 0, u, invalid = 0; + + vidstep = ((maximum.VID << 2) - (minimum.VID << 2)) / (p_states_count - 1); + + for (u = 0; u < p_states_count; u++) + { + i = u - invalid; + + p_states[i].CID = maximum.CID - u; + p_states[i].FID = (p_states[i].CID >> 1); + + if (p_states[i].FID < 0x6) + { + if (cpu_dynamic_fsb) + p_states[i].FID = (p_states[i].FID << 1) | 0x80; + } + else if (cpu_noninteger_bus_ratio) + { + p_states[i].FID = p_states[i].FID | (0x40 * (p_states[i].CID & 0x1)); + } + + if (i && p_states[i].FID == p_states[i-1].FID) + invalid++; + + p_states[i].VID = ((maximum.VID << 2) - (vidstep * u)) >> 2; + + uint32_t multiplier = p_states[i].FID & 0x1f; // = 0x08 + bool half = p_states[i].FID & 0x40; // = 0x01 + bool dfsb = p_states[i].FID & 0x80; // = 0x00 + uint32_t fsb = Platform.CPU.FSBFrequency / 1000000; // = 400 + uint32_t halffsb = (fsb + 1) >> 1; // = 200 + uint32_t frequency = (multiplier * fsb); // = 3200 + + p_states[i].Frequency = (frequency + (half * halffsb)) >> dfsb; // = 3200 + 200 = 3400 + } + + p_states_count -= invalid; + } + + break; + } + case CPU_MODEL_FIELDS: + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: + case CPU_MODEL_NEHALEM: + case CPU_MODEL_NEHALEM_EX: + case CPU_MODEL_WESTMERE: + case CPU_MODEL_WESTMERE_EX: + case CPU_MODEL_SANDY: + case CPU_MODEL_SANDY_XEON: + { + maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)... + minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff; + + verbose("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control); + + // Sanity check + if (maximum.Control < minimum.Control) + { + DBG("Insane control values!"); + p_states_count = 0; + } + else + { + uint8_t i; + p_states_count = 0; + + for (i = maximum.Control; i >= minimum.Control; i--) + { + p_states[p_states_count].Control = i; + p_states[p_states_count].CID = p_states[p_states_count].Control << 1; + p_states[p_states_count].Frequency = (Platform.CPU.FSBFrequency / 1000000) * i; + p_states_count++; + } + } + + break; + } + default: + verbose ("Unsupported CPU: P-States not generated !!!\n"); + break; + } + } + } + + // Generating SSDT + if (p_states_count > 0) + { + int i; + + struct aml_chunk* root = aml_create_node(NULL); + aml_add_buffer(root, ssdt_header, sizeof(ssdt_header)); // SSDT header + struct aml_chunk* scop = aml_add_scope(root, "\\_PR_"); + struct aml_chunk* name = aml_add_name(scop, "PSS_"); + struct aml_chunk* pack = aml_add_package(name); + + for (i = 0; i < p_states_count; i++) + { + struct aml_chunk* pstt = aml_add_package(pack); + + aml_add_dword(pstt, p_states[i].Frequency); + aml_add_dword(pstt, 0x00000000); // Power + aml_add_dword(pstt, 0x0000000A); // Latency + aml_add_dword(pstt, 0x0000000A); // Latency + aml_add_dword(pstt, p_states[i].Control); + aml_add_dword(pstt, i+1); // Status + } + + // Add aliaces + for (i = 0; i < acpi_cpu_count; i++) + { + char name[9]; + sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]); + + scop = aml_add_scope(root, name); + aml_add_alias(scop, "PSS_", "_PSS"); + } + + aml_calculate_size(root); + + struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size); + + aml_write_node(root, (void*)ssdt, 0); + + ssdt->Length = root->Size; + ssdt->Checksum = 0; + ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length); + + aml_destroy_node(root); + + //dumpPhysAddr("P-States SSDT content: ", ssdt, ssdt->Length); + + verbose ("SSDT with CPU P-States generated successfully\n"); + + return ssdt; + } + } + else + { + verbose ("ACPI CPUs not found: P-States not generated !!!\n"); + } + + return NULL; +} + +struct acpi_2_fadt *patch_fadt(struct acpi_2_fadt *fadt, struct acpi_2_dsdt *new_dsdt) +{ + extern void setupSystemType(); + + struct acpi_2_fadt *fadt_mod; + bool fadt_rev2_needed = false; + bool fix_restart; + const char * value; + + // Restart Fix + if (Platform.CPU.Vendor == 0x756E6547) { /* Intel */ + fix_restart = true; + getBoolForKey(kRestartFix, &fix_restart, &bootInfo->bootConfig); + } else { + verbose ("Not an Intel platform: Restart Fix not applied !!!\n"); + fix_restart = false; + } + + if (fix_restart) fadt_rev2_needed = true; + + // Allocate new fadt table + if (fadt->Length < 0x84 && fadt_rev2_needed) + { + fadt_mod=(struct acpi_2_fadt *)AllocateKernelMemory(0x84); + memcpy(fadt_mod, fadt, fadt->Length); + fadt_mod->Length = 0x84; + fadt_mod->Revision = 0x02; // FADT rev 2 (ACPI 1.0B MS extensions) + } + else + { + fadt_mod=(struct acpi_2_fadt *)AllocateKernelMemory(fadt->Length); + memcpy(fadt_mod, fadt, fadt->Length); + } + // Determine system type / PM_Model + if ( (value=getStringForKey(kSystemType, &bootInfo->bootConfig))!=NULL) + { + if (Platform.Type > 6) + { + if(fadt_mod->PM_Profile<=6) + Platform.Type = fadt_mod->PM_Profile; // get the fadt if correct + else + Platform.Type = 1; /* Set a fixed value (Desktop) */ + verbose("Error: system-type must be 0..6. Defaulting to %d !\n", Platform.Type); + } + else + Platform.Type = (unsigned char) strtoul(value, NULL, 10); + } + // Set PM_Profile from System-type if only user wanted this value to be forced + if (fadt_mod->PM_Profile != Platform.Type) + { + if (value) + { // user has overriden the SystemType so take care of it in FACP + verbose("FADT: changing PM_Profile from 0x%02x to 0x%02x\n", fadt_mod->PM_Profile, Platform.Type); + fadt_mod->PM_Profile = Platform.Type; + } + else + { // PM_Profile has a different value and no override has been set, so reflect the user value to ioregs + Platform.Type = fadt_mod->PM_Profile <= 6 ? fadt_mod->PM_Profile : 1; + } + } + // We now have to write the systemm-type in ioregs: we cannot do it before in setupDeviceTree() + // because we need to take care of facp original content, if it is correct. + setupSystemType(); + + // Patch FADT to fix restart + if (fix_restart) + { + fadt_mod->Flags|= 0x400; + fadt_mod->Reset_SpaceID = 0x01; // System I/O + fadt_mod->Reset_BitWidth = 0x08; // 1 byte + fadt_mod->Reset_BitOffset = 0x00; // Offset 0 + fadt_mod->Reset_AccessWidth = 0x01; // Byte access + fadt_mod->Reset_Address = 0x0cf9; // Address of the register + fadt_mod->Reset_Value = 0x06; // Value to write to reset the system + verbose("FADT: Restart Fix applied!\n"); + } + + // Patch DSDT Address if we have loaded DSDT.aml + if(new_dsdt) + { + DBG("DSDT: Old @%x,%x, ",fadt_mod->DSDT,fadt_mod->X_DSDT); + + fadt_mod->DSDT=(uint32_t)new_dsdt; + if ((uint32_t)(&(fadt_mod->X_DSDT))-(uint32_t)fadt_mod+8<=fadt_mod->Length) + fadt_mod->X_DSDT=(uint32_t)new_dsdt; + + DBG("New @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT); + + verbose("FADT: Using custom DSDT!\n"); + } + + // Correct the checksum + fadt_mod->Checksum=0; + fadt_mod->Checksum=256-checksum8(fadt_mod,fadt_mod->Length); + + return fadt_mod; +} + +/* Setup ACPI without replacing DSDT. */ +int setupAcpiNoMod() +{ + // addConfigurationTable(&gEfiAcpiTableGuid, getAddressOfAcpiTable(), "ACPI"); + // addConfigurationTable(&gEfiAcpi20TableGuid, getAddressOfAcpi20Table(), "ACPI_20"); + /* XXX aserebln why uint32 cast if pointer is uint64 ? */ + acpi10_p = (uint32_t)getAddressOfAcpiTable(); + acpi20_p = (uint32_t)getAddressOfAcpi20Table(); + addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI"); + if(acpi20_p) addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20"); + return 1; +} + +/* Setup ACPI. Replace DSDT if DSDT.aml is found */ +int setupAcpi(void) +{ + int version; + void *new_dsdt; + + const char *filename; + char dirSpec[128]; + int len = 0; + + // Try using the file specified with the DSDT option + if (getValueForKey(kDSDT, &filename, &len, &bootInfo->bootConfig)) + { + sprintf(dirSpec, filename); + } + else + { + sprintf(dirSpec, "DSDT.aml"); + } + + // Load replacement DSDT + new_dsdt = loadACPITable(dirSpec); + // Mozodojo: going to patch FACP and load SSDT's even if DSDT.aml is not present + /*if (!new_dsdt) + { + return setupAcpiNoMod(); + }*/ + + // Mozodojo: Load additional SSDTs + struct acpi_2_ssdt *new_ssdt[32]; // 30 + 2 additional tables for pss & cst + int ssdt_count=0; + + // SSDT Options + bool drop_ssdt=false, generate_pstates=false, generate_cstates=false; + + getBoolForKey(kDropSSDT, &drop_ssdt, &bootInfo->bootConfig); + getBoolForKey(kGeneratePStates, &generate_pstates, &bootInfo->bootConfig); + getBoolForKey(kGenerateCStates, &generate_cstates, &bootInfo->bootConfig); + + { + int i; + + for (i=0; i<30; i++) + { + char filename[512]; + + sprintf(filename, i>0?"SSDT-%d.aml":"SSDT.aml", i); + + if(new_ssdt[ssdt_count] = loadACPITable(filename)) + { + ssdt_count++; + } + else + { + break; + } + } + } + + // Do the same procedure for both versions of ACPI + for (version=0; version<2; version++) { + struct acpi_2_rsdp *rsdp, *rsdp_mod; + struct acpi_2_rsdt *rsdt, *rsdt_mod; + int rsdplength; + + // Find original rsdp + rsdp=(struct acpi_2_rsdp *)(version?getAddressOfAcpi20Table():getAddressOfAcpiTable()); + if (!rsdp) + { + DBG("No ACPI version %d found. Ignoring\n", version+1); + if (version) + addConfigurationTable(&gEfiAcpi20TableGuid, NULL, "ACPI_20"); + else + addConfigurationTable(&gEfiAcpiTableGuid, NULL, "ACPI"); + continue; + } + rsdplength=version?rsdp->Length:20; + + DBG("RSDP version %d found @%x. Length=%d\n",version+1,rsdp,rsdplength); + + /* FIXME: no check that memory allocation succeeded + * Copy and patch RSDP,RSDT, XSDT and FADT + * For more info see ACPI Specification pages 110 and following + */ + + rsdp_mod=(struct acpi_2_rsdp *) AllocateKernelMemory(rsdplength); + memcpy(rsdp_mod, rsdp, rsdplength); + rsdt=(struct acpi_2_rsdt *)(rsdp->RsdtAddress); + + DBG("RSDT @%x, Length %d\n",rsdt, rsdt->Length); + + if (rsdt && (uint32_t)rsdt !=0xffffffff && rsdt->Length<0x10000) + { + uint32_t *rsdt_entries; + int rsdt_entries_num; + int dropoffset=0, i; + + // mozo: using malloc cos I didn't found how to free already allocated kernel memory + rsdt_mod=(struct acpi_2_rsdt *)malloc(rsdt->Length); + memcpy (rsdt_mod, rsdt, rsdt->Length); + rsdp_mod->RsdtAddress=(uint32_t)rsdt_mod; + rsdt_entries_num=(rsdt_mod->Length-sizeof(struct acpi_2_rsdt))/4; + rsdt_entries=(uint32_t *)(rsdt_mod+1); + for (i=0;iLength); + + if (!fadt || (uint32_t)fadt == 0xffffffff || fadt->Length>0x10000) + { + printf("FADT incorrect. Not modified\n"); + continue; + } + + fadt_mod = patch_fadt(fadt, new_dsdt); + rsdt_entries[i-dropoffset]=(uint32_t)fadt_mod; + + // Generate _CST SSDT + if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod))) + { + generate_cstates = false; // Generate SSDT only once! + ssdt_count++; + } + + // Generating _PSS SSDT + if (generate_pstates && (new_ssdt[ssdt_count] = generate_pss_ssdt((void*)fadt_mod->DSDT))) + { + generate_pstates = false; // Generate SSDT only once! + ssdt_count++; + } + + continue; + } + } + DBG("\n"); + + // Allocate rsdt in Kernel memory area + rsdt_mod->Length += 4*ssdt_count - 4*dropoffset; + struct acpi_2_rsdt *rsdt_copy = (struct acpi_2_rsdt *)AllocateKernelMemory(rsdt_mod->Length); + memcpy (rsdt_copy, rsdt_mod, rsdt_mod->Length); + free(rsdt_mod); rsdt_mod = rsdt_copy; + rsdp_mod->RsdtAddress=(uint32_t)rsdt_mod; + rsdt_entries_num=(rsdt_mod->Length-sizeof(struct acpi_2_rsdt))/4; + rsdt_entries=(uint32_t *)(rsdt_mod+1); + + // Mozodojo: Insert additional SSDTs into RSDT + if(ssdt_count>0) + { + int j; + + for (j=0; jChecksum); + + rsdt_mod->Checksum=0; + rsdt_mod->Checksum=256-checksum8(rsdt_mod,rsdt_mod->Length); + + DBG("New checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod); + } + else + { + rsdp_mod->RsdtAddress=0; + printf("RSDT not found or RSDT incorrect\n"); + } + + if (version) + { + struct acpi_2_xsdt *xsdt, *xsdt_mod; + + // FIXME: handle 64-bit address correctly + + xsdt=(struct acpi_2_xsdt*) ((uint32_t)rsdp->XsdtAddress); + DBG("XSDT @%x;%x, Length=%d\n", (uint32_t)(rsdp->XsdtAddress>>32),(uint32_t)rsdp->XsdtAddress, + xsdt->Length); + if (xsdt && (uint64_t)rsdp->XsdtAddress<0xffffffff && xsdt->Length<0x10000) + { + uint64_t *xsdt_entries; + int xsdt_entries_num, i; + int dropoffset=0; + + // mozo: using malloc cos I didn't found how to free already allocated kernel memory + xsdt_mod=(struct acpi_2_xsdt*)malloc(xsdt->Length); + memcpy(xsdt_mod, xsdt, xsdt->Length); + rsdp_mod->XsdtAddress=(uint32_t)xsdt_mod; + xsdt_entries_num=(xsdt_mod->Length-sizeof(struct acpi_2_xsdt))/8; + xsdt_entries=(uint64_t *)(xsdt_mod+1); + for (i=0;i>32),fadt, + fadt->Length); + + if (!fadt || (uint64_t)xsdt_entries[i] >= 0xffffffff || fadt->Length>0x10000) + { + verbose("FADT incorrect or after 4GB. Dropping XSDT\n"); + goto drop_xsdt; + } + + fadt_mod = patch_fadt(fadt, new_dsdt); + xsdt_entries[i-dropoffset]=(uint32_t)fadt_mod; + + DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]); + + // Generate _CST SSDT + if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod))) + { + generate_cstates = false; // Generate SSDT only once! + ssdt_count++; + } + + // Generating _PSS SSDT + if (generate_pstates && (new_ssdt[ssdt_count] = generate_pss_ssdt((void*)fadt_mod->DSDT))) + { + generate_pstates = false; // Generate SSDT only once! + ssdt_count++; + } + + continue; + } + + DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]); + + } + + // Allocate xsdt in Kernel memory area + xsdt_mod->Length += 8*ssdt_count - 8*dropoffset; + struct acpi_2_xsdt *xsdt_copy = (struct acpi_2_xsdt *)AllocateKernelMemory(xsdt_mod->Length); + memcpy(xsdt_copy, xsdt_mod, xsdt_mod->Length); + free(xsdt_mod); xsdt_mod = xsdt_copy; + rsdp_mod->XsdtAddress=(uint32_t)xsdt_mod; + xsdt_entries_num=(xsdt_mod->Length-sizeof(struct acpi_2_xsdt))/8; + xsdt_entries=(uint64_t *)(xsdt_mod+1); + + // Mozodojo: Insert additional SSDTs into XSDT + if(ssdt_count>0) + { + int j; + + for (j=0; jChecksum=0; + xsdt_mod->Checksum=256-checksum8(xsdt_mod,xsdt_mod->Length); + } + else + { + drop_xsdt: + + DBG("About to drop XSDT\n"); + + /*FIXME: Now we just hope that if MacOS doesn't find XSDT it reverts to RSDT. + * A Better strategy would be to generate + */ + + rsdp_mod->XsdtAddress=0xffffffffffffffffLL; + verbose("XSDT not found or XSDT incorrect\n"); + } + } + + // Correct the checksum of RSDP + + DBG("RSDP: Original checksum %d, ", rsdp_mod->Checksum); + + rsdp_mod->Checksum=0; + rsdp_mod->Checksum=256-checksum8(rsdp_mod,20); + + DBG("New checksum %d\n", rsdp_mod->Checksum); + + if (version) + { + DBG("RSDP: Original extended checksum %d", rsdp_mod->ExtendedChecksum); + + rsdp_mod->ExtendedChecksum=0; + rsdp_mod->ExtendedChecksum=256-checksum8(rsdp_mod,rsdp_mod->Length); + + DBG("New extended checksum %d\n", rsdp_mod->ExtendedChecksum); + + } + + //verbose("Patched ACPI version %d DSDT\n", version+1); + if (version) + { + /* XXX aserebln why uint32 cast if pointer is uint64 ? */ + acpi20_p = (uint32_t)rsdp_mod; + addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20"); + } + else + { + /* XXX aserebln why uint32 cast if pointer is uint64 ? */ + acpi10_p = (uint32_t)rsdp_mod; + addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI"); + } + } +#if DEBUG_ACPI + printf("Press a key to continue... (DEBUG_ACPI)\n"); + getc(); +#endif + return 1; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/platform.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/platform.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/platform.c.svn-base (revision 850) @@ -0,0 +1,66 @@ +/* + * platform.c + * + * AsereBLN: cleanup + */ + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "cpu.h" +#include "spd.h" +#include "dram_controllers.h" + +#ifndef DEBUG_PLATFORM +#define DEBUG_PLATFORM 0 +#endif + +#if DEBUG_PLATFORM +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +PlatformInfo_t Platform; +pci_dt_t * dram_controller_dev = NULL; + +/** Return if a CPU feature specified by feature is activated (true) or not (false) */ +bool platformCPUFeature(uint32_t feature) +{ + if (Platform.CPU.Features & feature) { + return true; + } else { + return false; + } +} + +/** scan mem for memory autodection purpose */ +void scan_mem() { + static bool done = false; + if (done) return; + + bool useAutodetection = true; + getBoolForKey(kUseMemDetect, &useAutodetection, &bootInfo->bootConfig); + + if (useAutodetection) { + if (dram_controller_dev!=NULL) { + scan_dram_controller(dram_controller_dev); // Rek: pci dev ram controller direct and fully informative scan ... + } + scan_spd(&Platform); + } + done = true; +} + +/** + Scan platform hardware information, called by the main entry point (common_boot() ) + _before_ bootConfig xml parsing settings are loaded +*/ +void scan_platform(void) +{ + memset(&Platform, 0, sizeof(Platform)); + build_pci_dt(); + scan_cpu(&Platform); + //scan_mem(); Rek: called after pci devs init in fake_efi now ... +} Index: branches/Chimera/i386/libsaio/.svn/text-base/hfs_compare.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/hfs_compare.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/hfs_compare.c.svn-base (revision 850) @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2000-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * HFSCompare.c - Functions for working with and comparing HFS nams. + * + * Copyright (c) 1999-2000 Apple Computer, Inc. + * + * DRI: Josh de Cesare + */ + +#include +#include "hfs_CaseTables.h" + +#if ! UNCOMPRESSED + +static unsigned short * +UncompressStructure(struct compressed_block *bp, int count, int size) +{ + unsigned short *out = malloc(size); + unsigned short *op = out; + unsigned short data; + int i, j; + + for (i=0; icount) + { + stop("HFS+ Unicode tables are malformed\n"); + } + data = bp->data; + for (j=0; jcount; j++) { + *op++ = data; + if (bp->type == kTypeAscending) data++; + else if (bp->type == kTypeAscending256) data += 256; + } + } + return out; +} + +static void +InitCompareTables(void) +{ + if (gCompareTable == 0) { + gCompareTable = UncompressStructure(gCompareTableCompressed, + kCompareTableNBlocks, kCompareTableDataSize); + gLowerCaseTable = UncompressStructure(gLowerCaseTableCompressed, + kLowerCaseTableNBlocks, kLowerCaseTableDataSize); + } +} + +#endif /* ! UNCOMPRESSED */ + +//_______________________________________________________________________ +// +// Routine: FastRelString +// +// Output: returns -1 if str1 < str2 +// returns 1 if str1 > str2 +// return 0 if equal +// +//_______________________________________________________________________ + +int32_t FastRelString(u_int8_t * str1, u_int8_t * str2) +{ + int32_t bestGuess; + u_int8_t length, length2; + +#if ! UNCOMPRESED + InitCompareTables(); +#endif + + length = *(str1++); + length2 = *(str2++); + + if (length == length2) + bestGuess = 0; + else if (length < length2) + bestGuess = -1; + else + { + bestGuess = 1; + length = length2; + } + + while (length--) + { + u_int32_t aChar, bChar; + + aChar = *(str1++); + bChar = *(str2++); + + if (aChar != bChar) /* If they don't match exacly, do case conversion */ + { + u_int16_t aSortWord, bSortWord; + + aSortWord = gCompareTable[aChar]; + bSortWord = gCompareTable[bChar]; + + if (aSortWord > bSortWord) + return 1; + + if (aSortWord < bSortWord) + return -1; + } + + /* + * If characters match exactly, then go on to next character + * immediately without doing any extra work. + */ + } + + /* if you got to here, then return bestGuess */ + return bestGuess; +} + + +// +// FastUnicodeCompare - Compare two Unicode strings; produce a relative ordering +// +// IF RESULT +// -------------------------- +// str1 < str2 => -1 +// str1 = str2 => 0 +// str1 > str2 => +1 +// +// The lower case table starts with 256 entries (one for each of the upper bytes +// of the original Unicode char). If that entry is zero, then all characters with +// that upper byte are already case folded. If the entry is non-zero, then it is +// the _index_ (not byte offset) of the start of the sub-table for the characters +// with that upper byte. All ignorable characters are folded to the value zero. +// +// In pseudocode: +// +// Let c = source Unicode character +// Let table[] = lower case table +// +// lower = table[highbyte(c)] +// if (lower == 0) +// lower = c +// else +// lower = table[lower+lowbyte(c)] +// +// if (lower == 0) +// ignore this character +// +// To handle ignorable characters, we now need a loop to find the next valid character. +// Also, we can't pre-compute the number of characters to compare; the string length might +// be larger than the number of non-ignorable characters. Further, we must be able to handle +// ignorable characters at any point in the string, including as the first or last characters. +// We use a zero value as a sentinel to detect both end-of-string and ignorable characters. +// Since the File Manager doesn't prevent the NUL character (value zero) as part of a filename, +// the case mapping table is assumed to map u+0000 to some non-zero value (like 0xFFFF, which is +// an invalid Unicode character). +// +// Pseudocode: +// +// while (1) { +// c1 = GetNextValidChar(str1) // returns zero if at end of string +// c2 = GetNextValidChar(str2) +// +// if (c1 != c2) break // found a difference +// +// if (c1 == 0) // reached end of string on both strings at once? +// return 0; // yes, so strings are equal +// } +// +// // When we get here, c1 != c2. So, we just need to determine which one is less. +// if (c1 < c2) +// return -1; +// else +// return 1; +// + +int32_t FastUnicodeCompare( u_int16_t * str1, register u_int32_t length1, + u_int16_t * str2, register u_int32_t length2, int byte_order ) +{ + register u_int16_t c1,c2; + register u_int16_t temp; + +#if ! UNCOMPRESSED + InitCompareTables(); +#endif + + while (1) { + /* Set default values for c1, c2 in case there are no more valid chars */ + c1 = 0; + c2 = 0; + + /* Find next non-ignorable char from str1, or zero if no more */ + while (length1 && c1 == 0) { + if (byte_order == OSBigEndian) + c1 = SWAP_BE16(*(str1++)); + else + c1 = SWAP_LE16(*(str1++)); + --length1; + if ((temp = gLowerCaseTable[c1>>8]) != 0) // is there a subtable for this upper byte? + c1 = gLowerCaseTable[temp + (c1 & 0x00FF)]; // yes, so fold the char + } + + /* Find next non-ignorable char from str2, or zero if no more */ + while (length2 && c2 == 0) { + if (byte_order == OSBigEndian) + c2 = SWAP_BE16(*(str2++)); + else + c2 = SWAP_LE16(*(str2++)); + --length2; + if ((temp = gLowerCaseTable[c2>>8]) != 0) // is there a subtable for this upper byte? + c2 = gLowerCaseTable[temp + (c2 & 0x00FF)]; // yes, so fold the char + } + + if (c1 != c2) /* found a difference, so stop looping */ + break; + + if (c1 == 0) /* did we reach the end of both strings at the same time? */ + return 0; /* yes, so strings are equal */ + } + + if (c1 < c2) + return -1; + else + return 1; +} + + +// +// BinaryUnicodeCompare - Compare two Unicode strings; produce a relative ordering +// Compared using a 16-bit binary comparison (no case folding) +// +int32_t BinaryUnicodeCompare (u_int16_t * str1, u_int32_t length1, + u_int16_t * str2, u_int32_t length2) +{ + register u_int16_t c1, c2; + int32_t bestGuess; + u_int32_t length; + + bestGuess = 0; + + if (length1 < length2) { + length = length1; + --bestGuess; + } else if (length1 > length2) { + length = length2; + ++bestGuess; + } else { + length = length1; + } + + while (length--) { + c1 = *(str1++); + c2 = *(str2++); + + if (c1 > c2) + return (1); + if (c1 < c2) + return (-1); + } + + return (bestGuess); +} + + +/* + * UTF-8 (UCS Transformation Format) + * + * The following subset of UTF-8 is used to encode UCS-2 filenames. It + * requires a maximum of three 3 bytes per UCS-2 character. Only the + * shortest encoding required to represent the significant UCS-2 bits + * is legal. + * + * UTF-8 Multibyte Codes + * + * Bytes Bits UCS-2 Min UCS-2 Max UTF-8 Byte Sequence (binary) + * ------------------------------------------------------------------- + * 1 7 0x0000 0x007F 0xxxxxxx + * 2 11 0x0080 0x07FF 110xxxxx 10xxxxxx + * 3 16 0x0800 0xFFFF 1110xxxx 10xxxxxx 10xxxxxx + * ------------------------------------------------------------------- + */ + + +/* + * utf_encodestr - Encodes the UCS-2 (Unicode) string at ucsp into a + * null terminated UTF-8 string at utf8p. + * + * ucslen is the number of UCS-2 input characters (not bytes) + * bufsize is the size of the output buffer in bytes + */ +void +utf_encodestr( const u_int16_t * ucsp, int ucslen, + u_int8_t * utf8p, u_int32_t bufsize, int byte_order ) +{ + u_int8_t *bufend; + u_int16_t ucs_ch; + + bufend = utf8p + bufsize; + + while (ucslen-- > 0) { + if (byte_order == OSBigEndian) + ucs_ch = SWAP_BE16(*ucsp++); + else + ucs_ch = SWAP_LE16(*ucsp++); + + if (ucs_ch < 0x0080) { + if (utf8p >= bufend) + break; + if (ucs_ch == '\0') + continue; /* skip over embedded NULLs */ + *utf8p++ = ucs_ch; + + } else if (ucs_ch < 0x800) { + if ((utf8p + 1) >= bufend) + break; + *utf8p++ = (ucs_ch >> 6) | 0xc0; + *utf8p++ = (ucs_ch & 0x3f) | 0x80; + + } else { + if ((utf8p + 2) >= bufend) + break; + *utf8p++ = (ucs_ch >> 12) | 0xe0; + *utf8p++ = ((ucs_ch >> 6) & 0x3f) | 0x80; + *utf8p++ = ((ucs_ch) & 0x3f) | 0x80; + } + } + + *utf8p = '\0'; +} + + +/* + * utf_decodestr - Decodes the null terminated UTF-8 string at + * utf8p into a UCS-2 (Unicode) string at ucsp. + * + * ucslen is the number of UCS-2 output characters (not bytes) + * bufsize is the size of the output buffer in bytes + */ +void utf_decodestr(const u_int8_t * utf8p, u_int16_t * ucsp, u_int16_t * ucslen, u_int32_t bufsize, int byte_order) +{ + u_int16_t *bufstart; + u_int16_t *bufend; + u_int16_t ucs_ch; + u_int8_t byte; + + bufstart = ucsp; + bufend = (u_int16_t *)((u_int8_t *)ucsp + bufsize); + + while ((byte = *utf8p++) != '\0') { + if (ucsp >= bufend) + break; + + /* check for ascii */ + if (byte < 0x80) { + ucs_ch = byte; + + if (byte_order == OSBigEndian) + *ucsp++ = SWAP_BE16(ucs_ch); + else + *ucsp++ = SWAP_LE16(ucs_ch); + + continue; + } + + switch (byte & 0xf0) { + /* 2 byte sequence*/ + case 0xc0: + case 0xd0: + /* extract bits 6 - 10 from first byte */ + ucs_ch = (byte & 0x1F) << 6; + break; + /* 3 byte sequence*/ + case 0xe0: + /* extract bits 12 - 15 from first byte */ + ucs_ch = (byte & 0x0F) << 6; + + /* extract bits 6 - 11 from second byte */ + if (((byte = *utf8p++) & 0xc0) != 0x80) + goto stop; + + ucs_ch += (byte & 0x3F); + ucs_ch <<= 6; + break; + default: + goto stop; + } + + /* extract bits 0 - 5 from final byte */ + if (((byte = *utf8p++) & 0xc0) != 0x80) + goto stop; + ucs_ch += (byte & 0x3F); + + if (byte_order == OSBigEndian) + *ucsp++ = SWAP_BE16(ucs_ch); + else + *ucsp++ = SWAP_LE16(ucs_ch); + } +stop: + if (byte_order == OSBigEndian) + *ucslen = SWAP_BE16(ucsp - bufstart); + else + *ucslen = SWAP_LE16(ucsp - bufstart); +} Index: branches/Chimera/i386/libsaio/.svn/text-base/spd.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/spd.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/spd.c.svn-base (revision 850) @@ -0,0 +1,412 @@ +/* + * spd.c - serial presence detect memory information + * + * Originally restored from pcefi10.5 + * Dynamic mem detection original impl. by Rekursor + * System profiler fix and other fixes by Mozodojo. + */ + +#include "libsaio.h" +#include "pci.h" +#include "platform.h" +#include "spd.h" +#include "cpu.h" +#include "saio_internal.h" +#include "bootstruct.h" +#include "memvendors.h" + +#ifndef DEBUG_SPD +#define DEBUG_SPD 0 +#endif + +#if DEBUG_SPD +#define DBG(x...) printf(x) +#else +#define DBG(x...) msglog(x) +#endif + +static const char *spd_memory_types[] = +{ + "RAM", /* 00h Undefined */ + "FPM", /* 01h FPM */ + "EDO", /* 02h EDO */ + "", /* 03h PIPELINE NIBBLE */ + "SDRAM", /* 04h SDRAM */ + "", /* 05h MULTIPLEXED ROM */ + "DDR SGRAM", /* 06h SGRAM DDR */ + "DDR SDRAM", /* 07h SDRAM DDR */ + "DDR2 SDRAM", /* 08h SDRAM DDR 2 */ + "", /* 09h Undefined */ + "", /* 0Ah Undefined */ + "DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */ +}; + +#define UNKNOWN_MEM_TYPE 2 +static uint8_t spd_mem_to_smbios[] = +{ + UNKNOWN_MEM_TYPE, /* 00h Undefined */ + UNKNOWN_MEM_TYPE, /* 01h FPM */ + UNKNOWN_MEM_TYPE, /* 02h EDO */ + UNKNOWN_MEM_TYPE, /* 03h PIPELINE NIBBLE */ + SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */ + SMB_MEM_TYPE_ROM, /* 05h MULTIPLEXED ROM */ + SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */ + SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */ + SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */ + UNKNOWN_MEM_TYPE, /* 09h Undefined */ + UNKNOWN_MEM_TYPE, /* 0Ah Undefined */ + SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */ +}; +#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t)) + +#define rdtsc(low,high) \ +__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) + +#define SMBHSTSTS 0 +#define SMBHSTCNT 2 +#define SMBHSTCMD 3 +#define SMBHSTADD 4 +#define SMBHSTDAT 5 +#define SBMBLKDAT 7 + +/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */ +unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd) +{ + int l1, h1, l2, h2; + unsigned long long t; + + outb(base + SMBHSTSTS, 0x1f); // reset SMBus Controller + outb(base + SMBHSTDAT, 0xff); + + rdtsc(l1, h1); + while ( inb(base + SMBHSTSTS) & 0x01) // wait until read + { + rdtsc(l2, h2); + t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100); + if (t > 5) + return 0xFF; // break + } + + outb(base + SMBHSTCMD, cmd); + outb(base + SMBHSTADD, (adr << 1) | 0x01 ); + outb(base + SMBHSTCNT, 0x48 ); + + rdtsc(l1, h1); + + while (!( inb(base + SMBHSTSTS) & 0x02)) // wait til command finished + { + rdtsc(l2, h2); + t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100); + if (t > 5) + break; // break after 5ms + } + return inb(base + SMBHSTDAT); +} + +/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */ +#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x) + +int spd_indexes[] = { + SPD_MEMORY_TYPE, + SPD_DDR3_MEMORY_BANK, + SPD_DDR3_MEMORY_CODE, + SPD_NUM_ROWS, + SPD_NUM_COLUMNS, + SPD_NUM_DIMM_BANKS, + SPD_NUM_BANKS_PER_SDRAM, + 4,7,8,9,12,64, /* TODO: give names to these values */ + 95,96,97,98, 122,123,124,125 /* UIS */ +}; +#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int)) + +/** Read from spd *used* values only*/ +static void init_spd(char * spd, uint32_t base, int slot) +{ + int i; + for (i=0; i< SPD_INDEXES_SIZE; i++) { + READ_SPD(spd, base, slot, spd_indexes[i]); + } +} + +/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, + have different formats, always return a valid ptr.*/ +const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num) +{ + uint8_t bank = 0; + uint8_t code = 0; + int i = 0; + uint8_t * spd = (uint8_t *) slot->spd; + + if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3 + bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1 + code = spd[SPD_DDR3_MEMORY_CODE]; + for (i=0; i < VEN_MAP_SIZE; i++) + if (bank==vendorMap[i].bank && code==vendorMap[i].code) + return vendorMap[i].name; + } + else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) { + if(spd[64]==0x7f) { + for (i=64; i<72 && spd[i]==0x7f;i++) { + bank++; + READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop + } + READ_SPD(spd, base, slot_num,i); + code = spd[i]; + } else { + code = spd[64]; + bank = 0; + } + for (i=0; i < VEN_MAP_SIZE; i++) + if (bank==vendorMap[i].bank && code==vendorMap[i].code) + return vendorMap[i].name; + } + /* OK there is no vendor id here lets try to match the partnum if it exists */ + if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint + return "Unifosa"; + return "NoName"; +} + +/** Get Default Memory Module Speed (no overclocking handled) */ +int getDDRspeedMhz(const char * spd) +{ + if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { + switch(spd[12]) { + case 0x0f: + return 1066; + case 0x0c: + return 1333; + case 0x0a: + return 1600; + case 0x14: + default: + return 800; + } + } + else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) { + switch(spd[9]) { + case 0x50: + return 400; + case 0x3d: + return 533; + case 0x30: + return 667; + case 0x25: + default: + return 800; + } + } + return 800; // default freq for unknown types +} + +#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4)) +#define SLST(a) ((uint8_t)(spd[a] & 0x0f)) + +/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */ +const char *getDDRSerial(const char* spd) +{ + static char asciiSerial[16]; + + if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3 + { + sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125)); + } + else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR + { + sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98)); + } + + return strdup(asciiSerial); +} + +/** Get DDR3 or DDR2 Part Number, always return a valid ptr */ +const char * getDDRPartNum(char* spd, uint32_t base, int slot) +{ + static char asciiPartNo[32]; + int i, start=0, index = 0; + + if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { + start = 128; + } + else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) { + start = 73; + } + + // Check that the spd part name is zero terminated and that it is ascii: + bzero(asciiPartNo, sizeof(asciiPartNo)); + char c; + for (i=start; i < start + sizeof(asciiPartNo); i++) { + READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2) + c = spd[i]; + if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits... + asciiPartNo[index++] = c; + else if (!isascii(c)) + break; + } + + return strdup(asciiPartNo); +} + +int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11}; + + +/** Read from smbus the SPD content and interpret it for detecting memory attributes */ +static void read_smb_intel(pci_dt_t *smbus_dev) +{ + int i, speed; + uint8_t spd_size, spd_type; + uint32_t base, mmio, hostc; + bool dump = false; + RamSlotInfo_t* slot; + + uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04); + DBG("SMBus CmdReg: 0x%x\n", cmd); + pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1); + + mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f; + base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE; + hostc = pci_config_read8(smbus_dev->dev.addr, 0x40); + verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", + smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc); + + getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig); + // needed at least for laptops + bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots; + + char spdbuf[MAX_SPD_SIZE]; + // Search MAX_RAM_SLOTS slots + for (i = 0; i < MAX_RAM_SLOTS; i++){ + slot = &Platform.RAM.DIMM[i]; + spd_size = smb_read_byte_intel(base, 0x50 + i, 0); + DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i); + // Check spd is present + if (spd_size && (spd_size != 0xff)) + { + + slot->spd = spdbuf; + slot->InUse = true; + + bzero(slot->spd, spd_size); + + // Copy spd data into buffer + + //for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x); + init_spd(slot->spd, base, i); + + switch (slot->spd[SPD_MEMORY_TYPE]) { + case SPD_MEMORY_TYPE_SDRAM_DDR2: + + slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * + ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]); + break; + + case SPD_MEMORY_TYPE_SDRAM_DDR3: + + slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 ); + slot->ModuleSize -= (slot->spd[7] & 0x7) + 25; + slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1)); + + break; + } + + spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0); + slot->Type = spd_mem_to_smbios[spd_type]; + slot->PartNo = getDDRPartNum(slot->spd, base, i); + slot->Vendor = getVendorName(slot, base, i); + slot->SerialNo = getDDRSerial(slot->spd); + + // determine spd speed + speed = getDDRspeedMhz(slot->spd); + if (slot->FrequencyFrequency = speed; + + // pci memory controller if available, is more reliable + if (Platform.RAM.Frequency > 0) { + uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000; + // now round off special cases + uint32_t fmod100 = freq %100; + switch(fmod100) { + case 1: freq--; break; + case 32: freq++; break; + case 65: freq++; break; + case 98: freq+=2;break; + case 99: freq++; break; + } + slot->Frequency = freq; + } + + verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", + i, + (int)slot->Type, + slot->ModuleSize, + spd_memory_types[spd_type], + slot->Frequency, + slot->Vendor, + slot->PartNo, + slot->SerialNo); + +#if DEBUG_SPD + dumpPhysAddr("spd content: ", slot->spd, spd_size); + getc(); +#endif + } + + // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so: + Platform.DMI.DIMM[i]= + i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ? + mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this + + slot->spd = NULL; + + } // for +} + +static struct smbus_controllers_t smbus_controllers[] = { + + {0x8086, 0x269B, "ESB2", read_smb_intel }, + {0x8086, 0x25A4, "6300ESB", read_smb_intel }, + {0x8086, 0x24C3, "ICH4", read_smb_intel }, + {0x8086, 0x24D3, "ICH5", read_smb_intel }, + {0x8086, 0x266A, "ICH6", read_smb_intel }, + {0x8086, 0x27DA, "ICH7", read_smb_intel }, + {0x8086, 0x283E, "ICH8", read_smb_intel }, + {0x8086, 0x2930, "ICH9", read_smb_intel }, + {0x8086, 0x3A30, "ICH10R", read_smb_intel }, + {0x8086, 0x3A60, "ICH10B", read_smb_intel }, + {0x8086, 0x3B30, "P55", read_smb_intel }, + {0x8086, 0x5032, "EP80579", read_smb_intel } + +}; + +// initial call : pci_dt = root_pci_dev; +// find_and_read_smbus_controller(root_pci_dev); +bool find_and_read_smbus_controller(pci_dt_t* pci_dt) +{ + pci_dt_t *current = pci_dt; + int i; + + while (current) { +#if 0 + printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", + current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, + current->class_id, current->vendor_id, current->device_id, + get_pci_dev_path(current)); +#endif + for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ ) + { + if (current->vendor_id == smbus_controllers[i].vendor && + current->device_id == smbus_controllers[i].device) + { + smbus_controllers[i].read_smb(current); // read smb + return true; + } + } + find_and_read_smbus_controller(current->children); + current = current->next; + } + return false; // not found +} + +void scan_spd(PlatformInfo_t *p) +{ + find_and_read_smbus_controller(root_pci_dev); +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/usb.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/usb.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/usb.c.svn-base (revision 850) @@ -0,0 +1,345 @@ +/* + * usb.c + * + * + * Created by mackerintel on 12/20/08. + * Copyright 2008 mackerintel. All rights reserved. + * + */ + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "pci.h" + +#ifndef DEBUG_USB +#define DEBUG_USB 0 +#endif + +#if DEBUG_USB +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + + +struct pciList +{ + pci_dt_t* pciDev; + struct pciList* next; +}; + +struct pciList* usbList = NULL; + +int legacy_off (pci_dt_t *pci_dev); +int ehci_acquire (pci_dt_t *pci_dev); +int uhci_reset (pci_dt_t *pci_dev); + +// Add usb device to the list +void notify_usb_dev(pci_dt_t *pci_dev) +{ + + struct pciList* current = usbList; + if(!usbList) + { + usbList = (struct pciList*)malloc(sizeof(struct pciList)); + usbList->next = NULL; + usbList->pciDev = pci_dev; + + } + else + { + while(current != NULL && current->next != NULL) + { + current = current->next; + } + current->next = (struct pciList*)malloc(sizeof(struct pciList)); + current = current->next; + + current->pciDev = pci_dev; + current->next = NULL; + } +} + +// Loop through the list and call the apropriate patch function +int usb_loop() +{ + int retVal = 1; + bool fix_ehci, fix_uhci, fix_usb, fix_legacy; + fix_ehci = fix_uhci = fix_usb = fix_legacy = false; + + if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig)) + { + fix_ehci = fix_uhci = fix_legacy = fix_usb; // Disable all if none set + } + else + { + getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig); + getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig); + getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig); + } + + struct pciList* current = usbList; + + while(current) + { + switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG)) + { + // EHCI + case 0x20: + if(fix_ehci) retVal &= ehci_acquire(current->pciDev); + if(fix_legacy) retVal &= legacy_off(current->pciDev); + + break; + + // UHCI + case 0x00: + if (fix_uhci) retVal &= uhci_reset(current->pciDev); + + break; + } + + current = current->next; + } + return retVal; +} + +int legacy_off (pci_dt_t *pci_dev) +{ + // Set usb legacy off modification by Signal64 + // NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb. + // NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used) + // AKA: Make this run immediatly before the kernel is called + uint32_t capaddr, opaddr; + uint8_t eecp; + uint32_t usbcmd, usbsts, usbintr; + uint32_t usblegsup, usblegctlsts; + + int isOSowned; + int isBIOSowned; + + verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", + pci_dev->vendor_id, pci_dev->device_id, + pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func); + + + // capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE) + capaddr = pci_config_read32(pci_dev->dev.addr, 0x10); + + // opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0) + opaddr = capaddr + *((unsigned char*)(capaddr)); + + // eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8 + eecp=*((unsigned char*)(capaddr + 9)); + + DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp); + + usbcmd = *((unsigned int*)(opaddr)); // Command Register + usbsts = *((unsigned int*)(opaddr + 4)); // Status Register + usbintr = *((unsigned int*)(opaddr + 8)); // Interrupt Enable Register + + DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr); + + // read PCI Config 32bit USBLEGSUP (eecp+0) + usblegsup = pci_config_read32(pci_dev->dev.addr, eecp); + + // informational only + isBIOSowned = !!((usblegsup) & (1 << (16))); + isOSowned = !!((usblegsup) & (1 << (24))); + + // read PCI Config 32bit USBLEGCTLSTS (eecp+4) + usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4); + + DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts); + + // Reset registers to Legacy OFF + DBG("Clearing USBLEGCTLSTS\n"); + pci_config_write32(pci_dev->dev.addr, eecp + 4, 0); //usblegctlsts + + // if delay value is in milliseconds it doesn't appear to work. + // setting value to anything up to 65535 does not add the expected delay here. + delay(100); + + usbcmd = *((unsigned int*)(opaddr)); + usbsts = *((unsigned int*)(opaddr + 4)); + usbintr = *((unsigned int*)(opaddr + 8)); + + DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr); + + DBG("Clearing Registers\n"); + + // clear registers to default + usbcmd = (usbcmd & 0xffffff00); + *((unsigned int*)(opaddr)) = usbcmd; + *((unsigned int*)(opaddr + 8)) = 0; //usbintr - clear interrupt registers + *((unsigned int*)(opaddr + 4)) = 0x1000; //usbsts - clear status registers + pci_config_write32(pci_dev->dev.addr, eecp, 1); //usblegsup + + // get the results + usbcmd = *((unsigned int*)(opaddr)); + usbsts = *((unsigned int*)(opaddr + 4)); + usbintr = *((unsigned int*)(opaddr + 8)); + + DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr); + + // read 32bit USBLEGSUP (eecp+0) + usblegsup = pci_config_read32(pci_dev->dev.addr, eecp); + + // informational only + isBIOSowned = !!((usblegsup) & (1 << (16))); + isOSowned = !!((usblegsup) & (1 << (24))); + + // read 32bit USBLEGCTLSTS (eecp+4) + usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4); + + DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts); + + verbose("Legacy USB Off Done\n"); + return 1; +} + +int ehci_acquire (pci_dt_t *pci_dev) +{ + int j, k; + uint32_t base; + uint8_t eecp; + uint8_t legacy[8]; + bool isOwnershipConflict; + bool alwaysHardBIOSReset; + + alwaysHardBIOSReset = false; + if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) { + alwaysHardBIOSReset = true; + } + + pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002); + base = pci_config_read32(pci_dev->dev.addr, 0x10); + + verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", + pci_dev->vendor_id, pci_dev->device_id, + pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, + base); + + if (*((unsigned char*)base) < 0xc) + { + DBG("Config space too small: no legacy implementation\n"); + return 1; + } + eecp = *((unsigned char*)(base + 9)); + if (!eecp) { + DBG("No extended capabilities: no legacy implementation\n"); + return 1; + } + + DBG("eecp=%x\n",eecp); + + // bad way to do it + // pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001); + for (j = 0; j < 8; j++) { + legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); + DBG("%02x ", legacy[j]); + } + DBG("\n"); + + //Real Job: based on orByte's AppleUSBEHCI.cpp + //We try soft reset first - some systems hang on reboot with hard reset + // Definitely needed during reboot on 10.4.6 + + isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0)); + if (!alwaysHardBIOSReset && isOwnershipConflict) { + DBG("EHCI - Ownership conflict - attempting soft reset ...\n"); + DBG("EHCI - toggle OS Ownership to 0\n"); + pci_config_write8(pci_dev->dev.addr, eecp + 3, 0); + for (k = 0; k < 25; k++) { + for (j = 0; j < 8; j++) { + legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); + } + if (legacy[3] == 0) { + break; + } + delay(10); + } + } + + DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]); + pci_config_write8(pci_dev->dev.addr, eecp + 3, 1); + + // wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear + for (k = 0; k < 25; k++) { + for (j = 0;j < 8; j++) { + legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); + } + DBG ("%x:%x,",legacy[3],legacy[2]); + if (legacy[2] == 0) { + break; + } + delay(10); + } + + for (j = 0;j < 8; j++) { + legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); + } + isOwnershipConflict = ((legacy[2]) != 0); + if (isOwnershipConflict) { + // Soft reset has failed. Assume SMI being ignored + // Hard reset + // Force Clear BIOS BIT + DBG("EHCI - Ownership conflict - attempting hard reset ...\n"); + DBG ("%x:%x\n",legacy[3],legacy[2]); + DBG("EHCI - Force BIOS Ownership to 0\n"); + + pci_config_write8(pci_dev->dev.addr, eecp + 2, 0); + for (k = 0; k < 25; k++) { + for (j = 0; j < 8; j++) { + legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); + } + DBG ("%x:%x,",legacy[3],legacy[2]); + + if ((legacy[2]) == 0) { + break; + } + delay(10); + } + // Disable further SMI events + for (j = 4; j < 8; j++) { + pci_config_write8(pci_dev->dev.addr, eecp + j, 0); + } + } + + for (j = 0; j < 8; j++) { + legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j); + } + + DBG ("%x:%x\n",legacy[3],legacy[2]); + + // Final Ownership Resolution Check... + if (legacy[2] & 1) { + DBG("EHCI controller unable to take control from BIOS\n"); + return 0; + } + + DBG("EHCI Acquire OS Ownership done\n"); + return 1; +} + +int uhci_reset (pci_dt_t *pci_dev) +{ + uint32_t base, port_base; + + base = pci_config_read32(pci_dev->dev.addr, 0x20); + port_base = (base >> 5) & 0x07ff; + + verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", + pci_dev->vendor_id, pci_dev->device_id, + pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, + port_base, base); + + pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00); + + outw (port_base, 0x0002); + delay(10); + outw (port_base+4,0); + delay(10); + outw (port_base,0); + return 1; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/misc.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/misc.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/misc.c.svn-base (revision 850) @@ -0,0 +1,120 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Mach Operating System + * Copyright (c) 1990 Carnegie-Mellon University + * Copyright (c) 1989 Carnegie-Mellon University + * All rights reserved. The CMU software License Agreement specifies + * the terms and conditions for use and redistribution. + */ + +/* + * INTEL CORPORATION PROPRIETARY INFORMATION + * + * This software is supplied under the terms of a license agreement or + * nondisclosure agreement with Intel Corporation and may not be copied + * nor disclosed except in accordance with the terms of that agreement. + * + * Copyright 1988, 1989 Intel Corporation + */ + +/* + * Copyright 1993 NeXT, Inc. + * All rights reserved. + */ + +#include "libsaio.h" + +/* + * keyboard controller (8042) I/O port addresses + */ +#define PORT_A 0x60 /* port A */ +#define PORT_B 0x64 /* port B */ + +/* + * keyboard controller command + */ +#define CMD_WOUT 0xd1 /* write controller's output port */ + +/* + * keyboard controller status flags + */ +#define KB_INFULL 0x2 /* input buffer full */ +#define KB_OUTFULL 0x1 /* output buffer full */ + +#define KB_A20 0x9f /* enable A20, + enable output buffer full interrupt + enable data line + disable clock line */ + +//========================================================================== +// Enable A20 gate to be able to access memory above 1MB + +static inline void flushKeyboardInputBuffer() +{ + unsigned char ret; + /* Apparently all flags on means that they're invalid and that the code + should stop trying to check them because they'll never change */ + do + { + ret = inb(PORT_B); + } while( (ret != 0xff) && (ret & KB_INFULL)); +} + +void enableA20() +{ + /* make sure that the input buffer is empty */ + flushKeyboardInputBuffer(); + + /* make sure that the output buffer is empty */ + if (inb(PORT_B) & KB_OUTFULL) + (void)inb(PORT_A); + + /* make sure that the input buffer is empty */ + flushKeyboardInputBuffer(); + + /* write output port */ + outb(PORT_B, CMD_WOUT); + delay(100); + + /* wait until command is accepted */ + flushKeyboardInputBuffer(); + + outb(PORT_A, KB_A20); + delay(100); + + /* wait until done */ + flushKeyboardInputBuffer(); +} + +//========================================================================== +// Return the platform name for this hardware. +// +#ifndef BOOT1 +void +getPlatformName(char *nameBuf) +{ + strcpy(nameBuf, "ACPI"); +} +#endif Index: branches/Chimera/i386/libsaio/.svn/text-base/cpu.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/cpu.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/cpu.h.svn-base (revision 850) @@ -0,0 +1,146 @@ +/* + * Copyright 2008 Islam Ahmed Zaid. All rights reserved. + * AsereBLN: 2009: cleanup and bugfix + */ + +#ifndef __LIBSAIO_CPU_H +#define __LIBSAIO_CPU_H + +#include "libsaio.h" + +extern void scan_cpu(PlatformInfo_t *); + +#define bit(n) (1UL << (n)) +#define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1)) +#define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l) + +#define CPU_STRING_UNKNOWN "Unknown CPU Typ" + +#define MSR_IA32_PERF_STATUS 0x198 +#define MSR_IA32_PERF_CONTROL 0x199 +#define MSR_IA32_EXT_CONFIG 0x00EE +#define MSR_FLEX_RATIO 0x194 +#define MSR_TURBO_RATIO_LIMIT 0x1AD +#define MSR_PLATFORM_INFO 0xCE +#define MSR_CORE_THREAD_COUNT 0x35 // Undocumented + +#define K8_FIDVID_STATUS 0xC0010042 +#define K10_COFVID_STATUS 0xC0010071 + +#define DEFAULT_FSB 100000 /* for now, hardcoding 100MHz for old CPUs */ + +// DFE: This constant comes from older xnu: +#define CLKNUM 1193182 /* formerly 1193167 */ + +// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM +#define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ +#define CALIBRATE_LATCH ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) + +static inline uint64_t rdtsc64(void) +{ + uint64_t ret; + __asm__ volatile("rdtsc" : "=A" (ret)); + return ret; +} + +static inline uint64_t rdmsr64(uint32_t msr) +{ + uint64_t ret; + __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr)); + return ret; +} + +static inline void wrmsr64(uint32_t msr, uint64_t val) +{ + __asm__ volatile("wrmsr" : : "c" (msr), "A" (val)); +} + +static inline void intel_waitforsts(void) { + uint32_t inline_timeout = 100000; + while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; } +} + +static inline void do_cpuid(uint32_t selector, uint32_t *data) +{ + asm volatile ("cpuid" + : "=a" (data[0]), + "=b" (data[1]), + "=c" (data[2]), + "=d" (data[3]) + : "a" (selector)); +} + +static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data) +{ + asm volatile ("cpuid" + : "=a" (data[0]), + "=b" (data[1]), + "=c" (data[2]), + "=d" (data[3]) + : "a" (selector), "c" (selector2)); +} + +// DFE: enable_PIT2 and disable_PIT2 come from older xnu + +/* + * Enable or disable timer 2. + * Port 0x61 controls timer 2: + * bit 0 gates the clock, + * bit 1 gates output to speaker. + */ +static inline void enable_PIT2(void) +{ + /* Enable gate, disable speaker */ + __asm__ volatile( + " inb $0x61,%%al \n\t" + " and $0xFC,%%al \n\t" /* & ~0x03 */ + " or $1,%%al \n\t" + " outb %%al,$0x61 \n\t" + : : : "%al" ); +} + +static inline void disable_PIT2(void) +{ + /* Disable gate and output to speaker */ + __asm__ volatile( + " inb $0x61,%%al \n\t" + " and $0xFC,%%al \n\t" /* & ~0x03 */ + " outb %%al,$0x61 \n\t" + : : : "%al" ); +} + +// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are +// roughly based on Linux code + +/* Set the 8254 channel 2 to mode 0 with the specified value. + In mode 0, the counter will initially set its gate low when the + timer expires. For this to be useful, you ought to set it high + before calling this function. The enable_PIT2 function does this. + */ +static inline void set_PIT2_mode0(uint16_t value) +{ + __asm__ volatile( + " movb $0xB0,%%al \n\t" + " outb %%al,$0x43 \n\t" + " movb %%dl,%%al \n\t" + " outb %%al,$0x42 \n\t" + " movb %%dh,%%al \n\t" + " outb %%al,$0x42" + : : "d"(value) /*: no clobber */ ); +} + +/* Returns the number of times the loop ran before the PIT2 signaled */ +static inline unsigned long poll_PIT2_gate(void) +{ + unsigned long count = 0; + unsigned char nmi_sc_val; + do { + ++count; + __asm__ volatile( + "inb $0x61,%0" + : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */); + } while( (nmi_sc_val & 0x20) == 0); + return count; +} + +#endif /* !__LIBSAIO_CPU_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/smbios.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/smbios.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/smbios.c.svn-base (revision 850) @@ -0,0 +1,789 @@ +/* + * SMBIOS Table Patcher, part of the Chameleon Boot Loader Project + * + * Copyright 2010 by Islam M. Ahmed Zaid. All rights reserved. + * + */ + + +#include "boot.h" +#include "bootstruct.h" +#include "smbios_getters.h" + +#ifndef DEBUG_SMBIOS +#define DEBUG_SMBIOS 0 +#endif + +#if DEBUG_SMBIOS +#define DBG(x...) printf(x) +#else +#define DBG(x...) msglog(x) +#endif + +#define SMBPlist &bootInfo->smbiosConfig +/* ASSUMPTION: 16KB should be enough for the whole thing */ +#define SMB_ALLOC_SIZE 16384 + + +//------------------------------------------------------------------------------------------------------------------------- +// SMBIOS Plist Keys +//------------------------------------------------------------------------------------------------------------------------- +/* BIOS Information */ +#define kSMBBIOSInformationVendorKey "SMbiosvendor" +#define kSMBBIOSInformationVersionKey "SMbiosversion" +#define kSMBBIOSInformationReleaseDateKey "SMbiosdate" + +/* System Information */ +#define kSMBSystemInformationManufacturerKey "SMmanufacturer" +#define kSMBSystemInformationProductNameKey "SMproductname" +#define kSMBSystemInformationVersionKey "SMsystemversion" +#define kSMBSystemInformationSerialNumberKey "SMserial" +#define kSMBSystemInformationFamilyKey "SMfamily" + +/* Base Board */ +#define kSMBBaseBoardManufacturerKey "SMboardmanufacturer" +#define kSMBBaseBoardProductKey "SMboardproduct" + +/* Processor Information */ +#define kSMBProcessorInformationExternalClockKey "SMexternalclock" +#define kSMBProcessorInformationMaximumClockKey "SMmaximalclock" + +/* Memory Device */ +#define kSMBMemoryDeviceDeviceLocatorKey "SMmemdevloc" +#define kSMBMemoryDeviceBankLocatorKey "SMmembankloc" +#define kSMBMemoryDeviceMemoryTypeKey "SMmemtype" +#define kSMBMemoryDeviceMemorySpeedKey "SMmemspeed" +#define kSMBMemoryDeviceManufacturerKey "SMmemmanufacturer" +#define kSMBMemoryDeviceSerialNumberKey "SMmemserial" +#define kSMBMemoryDevicePartNumberKey "SMmempart" + +/* Apple Specific */ +#define kSMBOemProcessorTypeKey "SMcputype" +#define kSMBOemProcessorBusSpeedKey "SMbusspeed" + +//------------------------------------------------------------------------------------------------------------------------- +// Default SMBIOS Data +//------------------------------------------------------------------------------------------------------------------------- +/* Rewrite: use a struct */ + +#define kDefaultVendorManufacturer "Apple Inc." +#define kDefaultBIOSReleaseDate "11/06/2009" +#define kDefaultSerialNumber "SOMESRLNMBR" +#define kDefaultBoardProduct "Mac-F4208DC8" +#define kDefaultSystemVersion "1.0" + +// defaults for a Mac mini +#define kDefaultMacminiFamily "Macmini" +#define kDefaultMacmini "Macmini2,1" +#define kDefaultMacminiBIOSVersion " MM21.88Z.009A.B00.0903051113" + +// defaults for a MacBook +#define kDefaultMacBookFamily "MacBook" +#define kDefaultMacBook "MacBook4,1" +#define kDefaultMacBookBIOSVersion " MB41.88Z.0073.B00.0903051113" + +// defaults for a MacBook Pro +#define kDefaultMacBookProFamily "MacBookPro" +#define kDefaultMacBookPro "MacBookPro4,1" +#define kDefaultMacBookProBIOSVersion " MBP41.88Z.0073.B00.0903051113" + +// defaults for an iMac +#define kDefaultiMacFamily "iMac" +#define kDefaultiMac "iMac8,1" +#define kDefaultiMacBIOSVersion " IM81.88Z.00C1.B00.0903051113" +// defaults for an iMac11,1 core i3/i5/i7 +#define kDefaultiMacNehalem "iMac11,1" +#define kDefaultiMacNehalemBIOSVersion " IM111.88Z.0034.B00.0903051113" +// defaults for an iMac12,1 +#define kDefaultiMacSandy "iMac12,1" +#define kDefaultiMacSandyBIOSVersion " IM121.88Z.0047.B00.1102091756" + +// defaults for a Mac Pro +#define kDefaultMacProFamily "MacPro" +#define kDefaultMacPro "MacPro3,1" +#define kDefaultMacProBIOSVersion " MP31.88Z.006C.B05.0903051113" +// defaults for a Mac Pro 4,1 core i7/Xeon +#define kDefaultMacProNehalem "MacPro4,1" +#define kDefaultMacProNehalemBIOSVersion " MP41.88Z.0081.B04.0903051113" +// defaults for a Mac Pro 5,1 core i7/Xeon +#define kDefaultMacProWestmere "MacPro5,1" +#define kDefaultMacProWestmereBIOSVersion " MP51.88Z.007F.B00.1008031144" +#define kDefaulMacProWestmereBIOSReleaseDate "08/03/10" +//------------------------------------------------------------------------------------------------------------------------- + + +#define getFieldOffset(struct, field) ((uint8_t)(uint32_t)&(((struct *)0)->field)) + +typedef struct { + SMBStructHeader *orig; + SMBStructHeader *new; +} SMBStructPtrs; + +struct { + char *vendor; + char *version; + char *releaseDate; +} defaultBIOSInfo; + +struct { + char *manufacturer; + char *productName; + char *version; + char *serialNumber; + char *family; +} defaultSystemInfo; + +struct { + char *manufacturer; + char *product; +} defaultBaseBoard; + + +typedef struct { + uint8_t type; + SMBValueType valueType; + uint8_t fieldOffset; + char *keyString; + bool (*getSMBValue)(returnType *); + char **defaultValue; +} SMBValueSetter; + +SMBValueSetter SMBSetters[] = +{ + //------------------------------------------------------------------------------------------------------------------------- + // BIOSInformation + //------------------------------------------------------------------------------------------------------------------------- + {kSMBTypeBIOSInformation, kSMBString, getFieldOffset(SMBBIOSInformation, vendor), kSMBBIOSInformationVendorKey, + NULL, &defaultBIOSInfo.vendor }, + + {kSMBTypeBIOSInformation, kSMBString, getFieldOffset(SMBBIOSInformation, version), kSMBBIOSInformationVersionKey, + NULL, &defaultBIOSInfo.version }, + + {kSMBTypeBIOSInformation, kSMBString, getFieldOffset(SMBBIOSInformation, releaseDate), kSMBBIOSInformationReleaseDateKey, + NULL, &defaultBIOSInfo.releaseDate }, + + //------------------------------------------------------------------------------------------------------------------------- + // SystemInformation + //------------------------------------------------------------------------------------------------------------------------- + {kSMBTypeSystemInformation, kSMBString, getFieldOffset(SMBSystemInformation, manufacturer), kSMBSystemInformationManufacturerKey, + NULL, &defaultSystemInfo.manufacturer }, + + {kSMBTypeSystemInformation, kSMBString, getFieldOffset(SMBSystemInformation, productName), kSMBSystemInformationProductNameKey, + NULL, &defaultSystemInfo.productName }, + + {kSMBTypeSystemInformation, kSMBString, getFieldOffset(SMBSystemInformation, version), kSMBSystemInformationVersionKey, + NULL, &defaultSystemInfo.version }, + + {kSMBTypeSystemInformation, kSMBString, getFieldOffset(SMBSystemInformation, serialNumber), kSMBSystemInformationSerialNumberKey, + NULL, &defaultSystemInfo.serialNumber }, + + {kSMBTypeSystemInformation, kSMBString, getFieldOffset(SMBSystemInformation, skuNumber), NULL, + NULL, NULL }, + + {kSMBTypeSystemInformation, kSMBString, getFieldOffset(SMBSystemInformation, family), kSMBSystemInformationFamilyKey, + NULL, &defaultSystemInfo.family }, + + + //------------------------------------------------------------------------------------------------------------------------- + // BaseBoard + //------------------------------------------------------------------------------------------------------------------------- + {kSMBTypeBaseBoard, kSMBString, getFieldOffset(SMBBaseBoard, manufacturer), kSMBBaseBoardManufacturerKey, + NULL, &defaultBaseBoard.manufacturer }, + + {kSMBTypeBaseBoard, kSMBString, getFieldOffset(SMBBaseBoard, product), kSMBBaseBoardProductKey, + NULL, &defaultBaseBoard.product }, + + {kSMBTypeBaseBoard, kSMBString, getFieldOffset(SMBBaseBoard, version), NULL, NULL, NULL}, + + {kSMBTypeBaseBoard, kSMBString, getFieldOffset(SMBBaseBoard, serialNumber), NULL, NULL, NULL}, + + {kSMBTypeBaseBoard, kSMBString, getFieldOffset(SMBBaseBoard, assetTagNumber), NULL, NULL, NULL}, + + {kSMBTypeBaseBoard, kSMBString, getFieldOffset(SMBBaseBoard, locationInChassis), NULL, NULL, NULL}, + + + //------------------------------------------------------------------------------------------------------------------------- + // ProcessorInformation + //------------------------------------------------------------------------------------------------------------------------- + {kSMBTypeProcessorInformation, kSMBString, getFieldOffset(SMBProcessorInformation, socketDesignation), NULL, NULL, NULL}, + + {kSMBTypeProcessorInformation, kSMBString, getFieldOffset(SMBProcessorInformation, manufacturer), NULL, NULL, NULL}, + + {kSMBTypeProcessorInformation, kSMBString, getFieldOffset(SMBProcessorInformation, processorVersion), NULL, NULL, NULL}, + + {kSMBTypeProcessorInformation, kSMBWord, getFieldOffset(SMBProcessorInformation, externalClock), kSMBProcessorInformationExternalClockKey, + getProcessorInformationExternalClock, NULL}, + + {kSMBTypeProcessorInformation, kSMBWord, getFieldOffset(SMBProcessorInformation, maximumClock), kSMBProcessorInformationMaximumClockKey, + getProcessorInformationMaximumClock, NULL}, + + {kSMBTypeProcessorInformation, kSMBString, getFieldOffset(SMBProcessorInformation, serialNumber), NULL, NULL, NULL}, + + {kSMBTypeProcessorInformation, kSMBString, getFieldOffset(SMBProcessorInformation, assetTag), NULL, NULL, NULL}, + + {kSMBTypeProcessorInformation, kSMBString, getFieldOffset(SMBProcessorInformation, partNumber), NULL, NULL, NULL}, + + //------------------------------------------------------------------------------------------------------------------------- + // Memory Device + //------------------------------------------------------------------------------------------------------------------------- + {kSMBTypeMemoryDevice, kSMBString, getFieldOffset(SMBMemoryDevice, deviceLocator), kSMBMemoryDeviceDeviceLocatorKey, + NULL, NULL}, + + {kSMBTypeMemoryDevice, kSMBString, getFieldOffset(SMBMemoryDevice, bankLocator), kSMBMemoryDeviceBankLocatorKey, + NULL, NULL}, + + {kSMBTypeMemoryDevice, kSMBByte, getFieldOffset(SMBMemoryDevice, memoryType), kSMBMemoryDeviceMemoryTypeKey, + getSMBMemoryDeviceMemoryType, NULL}, + + {kSMBTypeMemoryDevice, kSMBWord, getFieldOffset(SMBMemoryDevice, memorySpeed), kSMBMemoryDeviceMemorySpeedKey, + getSMBMemoryDeviceMemorySpeed, NULL}, + + {kSMBTypeMemoryDevice, kSMBString, getFieldOffset(SMBMemoryDevice, manufacturer), kSMBMemoryDeviceManufacturerKey, + getSMBMemoryDeviceManufacturer, NULL}, + + {kSMBTypeMemoryDevice, kSMBString, getFieldOffset(SMBMemoryDevice, serialNumber), kSMBMemoryDeviceSerialNumberKey, + getSMBMemoryDeviceSerialNumber, NULL}, + + {kSMBTypeMemoryDevice, kSMBString, getFieldOffset(SMBMemoryDevice, assetTag), NULL, NULL, NULL}, + + {kSMBTypeMemoryDevice, kSMBString, getFieldOffset(SMBMemoryDevice, partNumber), kSMBMemoryDevicePartNumberKey, + getSMBMemoryDevicePartNumber, NULL}, + + + //------------------------------------------------------------------------------------------------------------------------- + // Apple Specific + //------------------------------------------------------------------------------------------------------------------------- + {kSMBTypeOemProcessorType, kSMBWord, getFieldOffset(SMBOemProcessorType, ProcessorType), kSMBOemProcessorTypeKey, + getSMBOemProcessorType, NULL}, + + {kSMBTypeOemProcessorBusSpeed, kSMBWord, getFieldOffset(SMBOemProcessorBusSpeed, ProcessorBusSpeed), kSMBOemProcessorBusSpeedKey, + getSMBOemProcessorBusSpeed, NULL} +}; + +int numOfSetters = sizeof(SMBSetters) / sizeof(SMBValueSetter); + + +SMBEntryPoint *origeps = 0; +SMBEntryPoint *neweps = 0; + +static uint8_t stringIndex; // increament when a string is added and set the field value accordingly +static uint8_t stringsSize; // add string size + +static SMBWord tableLength = 0; +static SMBWord handle = 0; +static SMBWord maxStructSize = 0; +static SMBWord structureCount = 0; + +/* Rewrite this function */ +void setDefaultSMBData(void) +{ + defaultBIOSInfo.vendor = kDefaultVendorManufacturer; + defaultBIOSInfo.releaseDate = kDefaultBIOSReleaseDate; + + defaultSystemInfo.manufacturer = kDefaultVendorManufacturer; + defaultSystemInfo.version = kDefaultSystemVersion; + defaultSystemInfo.serialNumber = kDefaultSerialNumber; + + defaultBaseBoard.manufacturer = kDefaultVendorManufacturer; + defaultBaseBoard.product = kDefaultBoardProduct; + + if (platformCPUFeature(CPU_FEATURE_MOBILE)) + { + if (Platform.CPU.NoCores > 1) + { + defaultBIOSInfo.version = kDefaultMacBookProBIOSVersion; + defaultSystemInfo.productName = kDefaultMacBookPro; + defaultSystemInfo.family = kDefaultMacBookProFamily; + } + else + { + defaultBIOSInfo.version = kDefaultMacBookBIOSVersion; + defaultSystemInfo.productName = kDefaultMacBook; + defaultSystemInfo.family = kDefaultMacBookFamily; + } + } + else + { + switch (Platform.CPU.NoCores) + { + case 1: + defaultBIOSInfo.version = kDefaultMacminiBIOSVersion; + defaultSystemInfo.productName = kDefaultMacmini; + defaultSystemInfo.family = kDefaultMacminiFamily; + break; + + case 2: + defaultBIOSInfo.version = kDefaultiMacBIOSVersion; + defaultSystemInfo.productName = kDefaultiMac; + defaultSystemInfo.family = kDefaultiMacFamily; + break; + default: + { + switch (Platform.CPU.Family) + { + case 0x06: + { + switch (Platform.CPU.Model) + { + case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + case 0x19: // Intel Core i5 650 @3.20 Ghz + defaultBIOSInfo.version = kDefaultiMacNehalemBIOSVersion; + defaultSystemInfo.productName = kDefaultiMacNehalem; + defaultSystemInfo.family = kDefaultiMacFamily; + break; + + case CPU_MODEL_SANDY: + case CPU_MODEL_SANDY_XEON: + defaultBIOSInfo.version = kDefaultiMacSandyBIOSVersion; + defaultSystemInfo.productName = kDefaultiMacSandy; + defaultSystemInfo.family = kDefaultiMacFamily; + break; + case CPU_MODEL_NEHALEM: + case CPU_MODEL_NEHALEM_EX: + defaultBIOSInfo.version = kDefaultMacProNehalemBIOSVersion; + defaultSystemInfo.productName = kDefaultMacProNehalem; + defaultSystemInfo.family = kDefaultMacProFamily; + break; + + case CPU_MODEL_WESTMERE: + case CPU_MODEL_WESTMERE_EX: + defaultBIOSInfo.version = kDefaultMacProWestmereBIOSVersion; + defaultBIOSInfo.releaseDate = kDefaulMacProWestmereBIOSReleaseDate; + defaultSystemInfo.productName = kDefaultMacProWestmere; + defaultSystemInfo.family = kDefaultMacProFamily; + break; + + default: + defaultBIOSInfo.version = kDefaultMacProBIOSVersion; + defaultSystemInfo.productName = kDefaultMacPro; + defaultSystemInfo.family = kDefaultMacProFamily; + break; + } + break; + } + default: + defaultBIOSInfo.version = kDefaultMacProBIOSVersion; + defaultSystemInfo.productName = kDefaultMacPro; + defaultSystemInfo.family = kDefaultMacProFamily; + break; + } + break; + } + } + } +} + +/* Used for SM*n smbios.plist keys */ +bool getSMBValueForKey(SMBStructHeader *structHeader, const char *keyString, const char **string, returnType *value) +{ + static int idx = -1; + static int current = -1; + int len; + char key[24]; + + if (current != structHeader->handle) + { + idx++; + current = structHeader->handle; + } + + sprintf(key, "%s%d", keyString, idx); + + if (value) + if (getIntForKey(key, (int *)&(value->dword), SMBPlist)) + return true; + else + if (getValueForKey(key, string, &len, SMBPlist)) + return true; + return false; +} + +char *getSMBStringForField(SMBStructHeader *structHeader, uint8_t field) +{ + uint8_t *stringPtr = (uint8_t *)structHeader + structHeader->length; + + if (!field) + return (char *)0; + + for (field--; field != 0 && strlen((char *)stringPtr) > 0; + field--, stringPtr = (uint8_t *)((uint32_t)stringPtr + strlen((char *)stringPtr) + 1)); + + return (char *)stringPtr; +} + +void setSMBStringForField(SMBStructHeader *structHeader, const char *string, uint8_t *field) +{ + int strSize; + + if (!field) + return; + if (!string) + { + *field = 0; + return; + } + + strSize = strlen(string); + + // remove any spaces found at the end + while ((string[strSize - 1] == ' ') && strSize != 0) + strSize--; + + if (strSize == 0) + { + *field = 0; + return; + } + + memcpy((uint8_t *)structHeader + structHeader->length + stringsSize, string, strSize); + *field = stringIndex; + + stringIndex++; + stringsSize += strSize + 1; +} + +bool setSMBValue(SMBStructPtrs *structPtr, int idx, returnType *value) +{ + const char *string = 0; + int len; + + if (numOfSetters <= idx) + return false; + + switch (SMBSetters[idx].valueType) + { + case kSMBString: + if (SMBSetters[idx].keyString) + { + if (getValueForKey(SMBSetters[idx].keyString, &string, &len, SMBPlist)) + break; + else + if (structPtr->orig->type == kSMBTypeMemoryDevice) // MemoryDevice only + if (getSMBValueForKey(structPtr->orig, SMBSetters[idx].keyString, &string, NULL)) + break; + } + if (SMBSetters[idx].getSMBValue) + if (SMBSetters[idx].getSMBValue((returnType *)&string)) + break; + if ((SMBSetters[idx].defaultValue) && *(SMBSetters[idx].defaultValue)) + { + string = *(SMBSetters[idx].defaultValue); + break; + } + string = getSMBStringForField(structPtr->orig, *(uint8_t *)value); + break; + + case kSMBByte: + case kSMBWord: + case kSMBDWord: + //case kSMBQWord: + if (SMBSetters[idx].keyString) + { + if (getIntForKey(SMBSetters[idx].keyString, (int *)&(value->dword), SMBPlist)) + return true; + else + if (structPtr->orig->type == kSMBTypeMemoryDevice) // MemoryDevice only + if (getSMBValueForKey(structPtr->orig, SMBSetters[idx].keyString, NULL, value)) + return true; + } + if (SMBSetters[idx].getSMBValue) + if (SMBSetters[idx].getSMBValue(value)) + return true; +#if 0 + if (*(SMBSetters[idx].defaultValue)) + { + value->dword = *(uint32_t *)(SMBSetters[idx].defaultValue); + return true; + } +#endif + break; + } + + if (SMBSetters[idx].valueType == kSMBString && string) + setSMBStringForField(structPtr->new, string, &value->byte); + + return true; +} + +//------------------------------------------------------------------------------------------------------------------------- +// Apple Specific +//------------------------------------------------------------------------------------------------------------------------- +void addSMBFirmwareVolume(SMBStructPtrs *structPtr) +{ + return; +} + +void addSMBMemorySPD(SMBStructPtrs *structPtr) +{ + /* SPD data from Platform.RAM.spd */ + return; +} + +void addSMBOemProcessorType(SMBStructPtrs *structPtr) +{ + SMBOemProcessorType *p = (SMBOemProcessorType *)structPtr->new; + + p->header.type = kSMBTypeOemProcessorType; + p->header.length = sizeof(SMBOemProcessorType); + p->header.handle = handle++; + + setSMBValue(structPtr, numOfSetters - 2 , (returnType *)&(p->ProcessorType)); + + structPtr->new = (SMBStructHeader *)((uint8_t *)structPtr->new + sizeof(SMBOemProcessorType) + 2); + tableLength += sizeof(SMBOemProcessorType) + 2; + structureCount++; +} + +void addSMBOemProcessorBusSpeed(SMBStructPtrs *structPtr) +{ + SMBOemProcessorBusSpeed *p = (SMBOemProcessorBusSpeed *)structPtr->new; + + p->header.type = kSMBTypeOemProcessorBusSpeed; + p->header.length = sizeof(SMBOemProcessorBusSpeed); + p->header.handle = handle++; + + setSMBValue(structPtr, numOfSetters -1, (returnType *)&(p->ProcessorBusSpeed)); + + structPtr->new = (SMBStructHeader *)((uint8_t *)structPtr->new + sizeof(SMBOemProcessorBusSpeed) + 2); + tableLength += sizeof(SMBOemProcessorBusSpeed) + 2; + structureCount++; +} + +//------------------------------------------------------------------------------------------------------------------------- +// EndOfTable +//------------------------------------------------------------------------------------------------------------------------- +void addSMBEndOfTable(SMBStructPtrs *structPtr) +{ + structPtr->new->type = kSMBTypeEndOfTable; + structPtr->new->length = sizeof(SMBStructHeader); + structPtr->new->handle = handle++; + + structPtr->new = (SMBStructHeader *)((uint8_t *)structPtr->new + sizeof(SMBStructHeader) + 2); + tableLength += sizeof(SMBStructHeader) + 2; + structureCount++; +} + +void setSMBStruct(SMBStructPtrs *structPtr) +{ + bool setterFound = false; + + uint8_t *ptr; + SMBWord structSize; + int i; + + stringIndex = 1; + stringsSize = 0; + + if (handle < structPtr->orig->handle) + handle = structPtr->orig->handle; + + memcpy((void *)structPtr->new, structPtr->orig, structPtr->orig->length); + + for (i = 0; i < numOfSetters; i++) + if (structPtr->orig->type == SMBSetters[i].type) + { + setterFound = true; + setSMBValue(structPtr, i, (returnType *)((uint8_t *)structPtr->new + SMBSetters[i].fieldOffset)); + } + + if (setterFound) + { + ptr = (uint8_t *)structPtr->new + structPtr->orig->length; + for (; ((uint16_t *)ptr)[0] != 0; ptr++); + + if (((uint16_t *)ptr)[0] == 0) + ptr += 2; + + structSize = ptr - (uint8_t *)structPtr->new; + } + else + { + ptr = (uint8_t *)structPtr->orig + structPtr->orig->length; + for (; ((uint16_t *)ptr)[0] != 0; ptr++); + + if (((uint16_t *)ptr)[0] == 0) + ptr += 2; + + structSize = ptr - (uint8_t *)structPtr->orig; + memcpy((void *)structPtr->new, structPtr->orig, structSize); + } + + structPtr->new = (SMBStructHeader *)((uint8_t *)structPtr->new + structSize); + + tableLength += structSize; + + if (structSize > maxStructSize) + maxStructSize = structSize; + + structureCount++; +} + +void setupNewSMBIOSTable(SMBEntryPoint *eps, SMBStructPtrs *structPtr) +{ + uint8_t *ptr = (uint8_t *)eps->dmi.tableAddress; + structPtr->orig = (SMBStructHeader *)ptr; + + for (;((eps->dmi.tableAddress + eps->dmi.tableLength) > ((uint32_t)(uint8_t *)structPtr->orig + sizeof(SMBStructHeader)));) + { + switch (structPtr->orig->type) + { + /* Skip all Apple Specific Structures */ + case kSMBTypeFirmwareVolume: + case kSMBTypeMemorySPD: + case kSMBTypeOemProcessorType: + case kSMBTypeOemProcessorBusSpeed: + /* And this one too, to be added at the end */ + case kSMBTypeEndOfTable: + break; + + default: + /* Add */ + setSMBStruct(structPtr); + break; + } + + ptr = (uint8_t *)((uint32_t)structPtr->orig + structPtr->orig->length); + for (; ((uint16_t *)ptr)[0] != 0; ptr++); + + if (((uint16_t *)ptr)[0] == 0) + ptr += 2; + + structPtr->orig = (SMBStructHeader *)ptr; + } + + addSMBFirmwareVolume(structPtr); + addSMBMemorySPD(structPtr); + addSMBOemProcessorType(structPtr); + addSMBOemProcessorBusSpeed(structPtr); + + addSMBEndOfTable(structPtr); +} + +void setupSMBIOSTable(void) +{ + SMBStructPtrs *structPtr; + uint8_t *buffer; + bool setSMB = true; + + if (!origeps) + return; + + neweps = origeps; + + structPtr = (SMBStructPtrs *)malloc(sizeof(SMBStructPtrs)); + if (!structPtr) + return; + + buffer = malloc(SMB_ALLOC_SIZE); + if (!buffer) + return; + + bzero(buffer, SMB_ALLOC_SIZE); + structPtr->new = (SMBStructHeader *)buffer; + + getBoolForKey(kSMBIOSdefaults, &setSMB, &bootInfo->bootConfig); + if (setSMB) + setDefaultSMBData(); + + setupNewSMBIOSTable(origeps, structPtr); + + neweps = (SMBEntryPoint *)AllocateKernelMemory(sizeof(SMBEntryPoint)); + if (!neweps) + return; + bzero(neweps, sizeof(SMBEntryPoint)); + + neweps->anchor[0] = '_'; + neweps->anchor[1] = 'S'; + neweps->anchor[2] = 'M'; + neweps->anchor[3] = '_'; + neweps->entryPointLength = sizeof(SMBEntryPoint); + neweps->majorVersion = 2; + neweps->minorVersion = 4; + neweps->maxStructureSize = maxStructSize; + neweps->entryPointRevision = 0; + + neweps->dmi.anchor[0] = '_'; + neweps->dmi.anchor[1] = 'D'; + neweps->dmi.anchor[2] = 'M'; + neweps->dmi.anchor[3] = 'I'; + neweps->dmi.anchor[4] = '_'; + neweps->dmi.tableLength = tableLength; + neweps->dmi.tableAddress = AllocateKernelMemory(tableLength); + neweps->dmi.structureCount = structureCount; + neweps->dmi.bcdRevision = 0x24; + + if (!neweps->dmi.tableAddress) + return; + + memcpy((void *)neweps->dmi.tableAddress, buffer, tableLength); + + neweps->dmi.checksum = 0; + neweps->dmi.checksum = 0x100 - checksum8(&neweps->dmi, sizeof(DMIEntryPoint)); + + neweps->checksum = 0; + neweps->checksum = 0x100 - checksum8(neweps, sizeof(SMBEntryPoint)); + + free(buffer); + decodeSMBIOSTable(neweps); +} + +void *getSmbios(int which) +{ + switch (which) + { + case SMBIOS_ORIGINAL: + if (!origeps) + origeps = getAddressOfSmbiosTable(); + return origeps; + case SMBIOS_PATCHED: + return neweps; + } + + return 0; +} + +/* Collect any information needed later */ +void readSMBIOSInfo(SMBEntryPoint *eps) +{ + uint8_t *structPtr = (uint8_t *)eps->dmi.tableAddress; + SMBStructHeader *structHeader = (SMBStructHeader *)structPtr; + + int dimmnbr = 0; + Platform.DMI.MaxMemorySlots = 0; + Platform.DMI.CntMemorySlots = 0; + Platform.DMI.MemoryModules = 0; + + for (;((eps->dmi.tableAddress + eps->dmi.tableLength) > ((uint32_t)(uint8_t *)structHeader + sizeof(SMBStructHeader)));) + { + switch (structHeader->type) + { + case kSMBTypeSystemInformation: + Platform.UUID = ((SMBSystemInformation *)structHeader)->uuid; + break; + + case kSMBTypePhysicalMemoryArray: + Platform.DMI.MaxMemorySlots += ((SMBPhysicalMemoryArray *)structHeader)->numMemoryDevices; + break; + + case kSMBTypeMemoryDevice: + Platform.DMI.CntMemorySlots++; + if (((SMBMemoryDevice *)structHeader)->memorySize != 0) + Platform.DMI.MemoryModules++; + if (((SMBMemoryDevice *)structHeader)->memorySpeed > 0) + Platform.RAM.DIMM[dimmnbr].Frequency = ((SMBMemoryDevice *)structHeader)->memorySpeed; + dimmnbr++; + break; + } + + structPtr = (uint8_t *)((uint32_t)structHeader + structHeader->length); + for (; ((uint16_t *)structPtr)[0] != 0; structPtr++); + + if (((uint16_t *)structPtr)[0] == 0) + structPtr += 2; + + structHeader = (SMBStructHeader *)structPtr; + } +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/hpet.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/hpet.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/hpet.c.svn-base (revision 850) @@ -0,0 +1,103 @@ +/* + * + */ + +#include "libsaio.h" +#include "pci.h" +#include "hpet.h" + +#ifndef DEBUG_HPET +#define DEBUG_HPET 0 +#endif + +#if DEBUG_HPET +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +static struct lpc_controller_t lpc_controllers[] = { + + // Default unknown chipset + { 0, 0, "" }, + + // Intel + { 0x8086, 0x24dc, "ICH5" }, + { 0x8086, 0x2640, "ICH6" }, + { 0x8086, 0x2641, "ICH6M" }, + + { 0x8086, 0x27b0, "ICH7 DH" }, + { 0x8086, 0x27b8, "ICH7" }, + { 0x8086, 0x27b9, "ICH7M" }, + { 0x8086, 0x27bd, "ICH7M DH" }, + + { 0x8086, 0x2810, "ICH8R" }, + { 0x8086, 0x2811, "ICH8M-E" }, + { 0x8086, 0x2812, "ICH8DH" }, + { 0x8086, 0x2814, "ICH8DO" }, + { 0x8086, 0x2815, "ICH8M" }, + + { 0x8086, 0x2912, "ICH9DH" }, + { 0x8086, 0x2914, "ICH9DO" }, + { 0x8086, 0x2916, "ICH9R" }, + { 0x8086, 0x2917, "ICH9M-E" }, + { 0x8086, 0x2918, "ICH9" }, + { 0x8086, 0x2919, "ICH9M" }, + + { 0x8086, 0x3a14, "ICH10DO" }, + { 0x8086, 0x3a16, "ICH10R" }, + { 0x8086, 0x3a18, "ICH10" }, + { 0x8086, 0x3a1a, "ICH10D" }, + +}; + +void force_enable_hpet(pci_dt_t *lpc_dev) +{ + int i; + uint32_t val, hpet_address = 0xFED00000; + void *rcba; + + /* LPC on Intel ICH is always (?) at 00:1f.0 */ + for(i = 1; i < sizeof(lpc_controllers) / sizeof(lpc_controllers[0]); i++) + if ((lpc_controllers[i].vendor == lpc_dev->vendor_id) + && (lpc_controllers[i].device == lpc_dev->device_id)) + { + rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000); + + DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", + lpc_controllers[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba); + + if (rcba == 0) + printf(" RCBA disabled; cannot force enable HPET\n"); + else + { + val = REG32(rcba, 0x3404); + if (val & 0x80) + { + // HPET is enabled in HPTC. Just not reported by BIOS + DBG(" HPET is enabled in HPTC, just not reported by BIOS\n"); + hpet_address |= (val & 3) << 12 ; + DBG(" HPET MMIO @ 0x%lx\n", hpet_address); + } + else + { + // HPET disabled in HPTC. Trying to enable + DBG(" HPET is disabled in HPTC, trying to enable\n"); + REG32(rcba, 0x3404) = val | 0x80; + hpet_address |= (val & 3) << 12 ; + DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address); + } + + // verify if the job is done + val = REG32(rcba, 0x3404); + if (!(val & 0x80)) + printf(" Failed to force enable HPET\n"); + } + break; + } + +#if DEBUG_HPET + printf("Press [Enter] to continue...\n"); + getc(); +#endif +} Index: branches/Chimera/i386/libsaio/.svn/text-base/ufs.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ufs.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ufs.h.svn-base (revision 850) @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +extern long UFSInitPartition(CICell ih); +extern long UFSLoadFile(CICell ih, char * filePath); +extern long UFSReadFile( CICell ih, char * filePath, void * base, uint64_t offset, uint64_t length ); +extern long UFSGetDirEntry(CICell ih, char * dirPath, long long * dirIndex, + char ** name, long * flags, long * time, + FinderInfo * finderInfo, long * infoValid); +extern void UFSGetDescription(CICell ih, char *str, long strMaxLen); +extern long UFSGetFileBlock(CICell ih, char *str, unsigned long long *firstBlock); +extern long UFSGetUUID(CICell ih, char *uuidStr); +extern void UFSFree(CICell ih); + Index: branches/Chimera/i386/libsaio/.svn/text-base/fdisk.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/fdisk.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/fdisk.h.svn-base (revision 850) @@ -0,0 +1,89 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright (c) 1992 NeXT Computer, Inc. + * + * IBM PC disk partitioning data structures. + * + * HISTORY + * + * 8 July 1992 David E. Bohman at NeXT + * Created. + */ + +#ifndef __LIBSAIO_FDISK_H +#define __LIBSAIO_FDISK_H + +#define DISK_BLK0 0 /* blkno of boot block */ +#define DISK_BLK0SZ 512 /* size of boot block */ +#define DISK_BOOTSZ 446 /* size of boot code in boot block */ +#define DISK_SIGNATURE 0xAA55 /* signature of the boot record */ +#define FDISK_NPART 4 /* number of entries in fdisk table */ +#define FDISK_ACTIVE 0x80 /* indicator of active partition */ +#define FDISK_NEXTNAME 0xA7 /* indicator of NeXT partition */ +#define FDISK_DOS12 0x01 /* 12-bit fat < 10MB dos partition */ +#define FDISK_DOS16S 0x04 /* 16-bit fat < 32MB dos partition */ +#define FDISK_DOSEXT 0x05 /* extended dos partition */ +#define FDISK_DOS16B 0x06 /* 16-bit fat >= 32MB dos partition */ +#define FDISK_NTFS 0x07 /* NTFS partition */ +#define FDISK_SMALLFAT32 0x0b /* FAT32 partition */ +#define FDISK_FAT32 0x0c /* FAT32 partition */ +#define FDISK_DOS16SLBA 0x0e +#define FDISK_LINUX 0x83 +#define FDISK_UFS 0xa8 /* Apple UFS partition */ +#define FDISK_HFS 0xaf /* Apple HFS partition */ +#define FDISK_BOOTER 0xab /* Apple booter partition */ + +/* + * Format of fdisk partion entry (if present). + */ +struct fdisk_part { + unsigned char bootid; /* bootable or not */ + unsigned char beghead; /* begining head, sector, cylinder */ + unsigned char begsect; /* begcyl is a 10-bit number */ + unsigned char begcyl; /* High 2 bits are in begsect */ + unsigned char systid; /* OS type */ + unsigned char endhead; /* ending head, sector, cylinder */ + unsigned char endsect; /* endcyl is a 10-bit number */ + unsigned char endcyl; /* High 2 bits are in endsect */ + unsigned long relsect; /* partion physical offset on disk */ + unsigned long numsect; /* number of sectors in partition */ +} __attribute__((packed)); + +/* + * Format of boot block. + */ +struct disk_blk0 { + unsigned char bootcode[DISK_BOOTSZ]; + unsigned char parts[FDISK_NPART][sizeof (struct fdisk_part)]; + unsigned short signature; +}; + +struct REAL_disk_blk0 { + unsigned char bootcode[DISK_BOOTSZ]; + struct fdisk_part parts[FDISK_NPART]; + unsigned short signature; +} __attribute__((packed)); + +#endif /* !__LIBSAIO_FDISK_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/dram_controllers.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/dram_controllers.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/dram_controllers.c.svn-base (revision 850) @@ -0,0 +1,564 @@ +/* + * dram controller access and scan from the pci host controller + * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work + * original source comes from: + * + * memtest86 + * + * Released under version 2 of the Gnu Public License. + * By Chris Brady, cbrady@sgi.com + * ---------------------------------------------------- + * MemTest86+ V4.00 Specific code (GPL V2.0) + * By Samuel DEMEULEMEESTER, sdemeule@memtest.org + * http://www.canardpc.com - http://www.memtest.org + */ + +#include "libsaio.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "dram_controllers.h" + +#ifndef DEBUG_DRAM +#define DEBUG_DRAM 0 +#endif + +#if DEBUG_DRAM +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +/* + * Initialise memory controller functions + */ + +// Setup P35 Memory Controller +static void setup_p35(pci_dt_t *dram_dev) +{ + uint32_t dev0; + + // Activate MMR I/O + dev0 = pci_config_read32(dram_dev->dev.addr, 0x48); + if (!(dev0 & 0x1)) + pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1)); +} + +int nhm_bus = 0x3F; + +// Setup Nehalem Integrated Memory Controller +static void setup_nhm(pci_dt_t *dram_dev) +{ + static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F}; + unsigned long did, vid; + int i; + + // Nehalem supports Scrubbing + // First, locate the PCI bus where the MCH is located + for(i = 0; i < sizeof(possible_nhm_bus); i++) + { + vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00); + did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02); + vid &= 0xFFFF; + did &= 0xFF00; + + if(vid == 0x8086 && did >= 0x2C00) + nhm_bus = possible_nhm_bus[i]; + } +} + +/* + * Retrieve memory controller fsb functions + */ + + +// Get i965 Memory Speed +static void get_fsb_i965(pci_dt_t *dram_dev) +{ + uint32_t dev0, mch_ratio, mch_cfg, mch_fsb; + + long *ptr; + + // Find Ratio + dev0 = pci_config_read32(dram_dev->dev.addr, 0x48); + dev0 &= 0xFFFFC000; + ptr = (long*)(dev0 + 0xC00); + mch_cfg = *ptr & 0xFFFF; + + mch_ratio = 100000; + + switch (mch_cfg & 7) + { + case 0: mch_fsb = 1066; break; + case 1: mch_fsb = 533; break; + default: + case 2: mch_fsb = 800; break; + case 3: mch_fsb = 667; break; + case 4: mch_fsb = 1333; break; + case 6: mch_fsb = 1600; break; + } + + DBG("mch_fsb %d\n", mch_fsb); + + switch (mch_fsb) + { + case 533: + switch ((mch_cfg >> 4) & 7) + { + case 1: mch_ratio = 200000; break; + case 2: mch_ratio = 250000; break; + case 3: mch_ratio = 300000; break; + } + break; + + default: + case 800: + switch ((mch_cfg >> 4) & 7) + { + case 0: mch_ratio = 100000; break; + case 1: mch_ratio = 125000; break; + case 2: mch_ratio = 166667; break; // 1.666666667 + case 3: mch_ratio = 200000; break; + case 4: mch_ratio = 266667; break; // 2.666666667 + case 5: mch_ratio = 333333; break; // 3.333333333 + } + break; + + case 1066: + switch ((mch_cfg >> 4) & 7) + { + case 1: mch_ratio = 100000; break; + case 2: mch_ratio = 125000; break; + case 3: mch_ratio = 150000; break; + case 4: mch_ratio = 200000; break; + case 5: mch_ratio = 250000; break; + } + break; + + case 1333: + switch ((mch_cfg >> 4) & 7) + { + case 2: mch_ratio = 100000; break; + case 3: mch_ratio = 120000; break; + case 4: mch_ratio = 160000; break; + case 5: mch_ratio = 200000; break; + } + break; + + case 1600: + switch ((mch_cfg >> 4) & 7) + { + case 3: mch_ratio = 100000; break; + case 4: mch_ratio = 133333; break; // 1.333333333 + case 5: mch_ratio = 150000; break; + case 6: mch_ratio = 200000; break; + } + break; + } + + DBG("mch_ratio %d\n", mch_ratio); + + // Compute RAM Frequency + Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000; + + DBG("ram_fsb %d\n", Platform.RAM.Frequency); + +} + +// Get i965m Memory Speed +static void get_fsb_im965(pci_dt_t *dram_dev) +{ + uint32_t dev0, mch_ratio, mch_cfg, mch_fsb; + + long *ptr; + + // Find Ratio + dev0 = pci_config_read32(dram_dev->dev.addr, 0x48); + dev0 &= 0xFFFFC000; + ptr = (long*)(dev0 + 0xC00); + mch_cfg = *ptr & 0xFFFF; + + mch_ratio = 100000; + + switch (mch_cfg & 7) + { + case 1: mch_fsb = 533; break; + default: + case 2: mch_fsb = 800; break; + case 3: mch_fsb = 667; break; + case 6: mch_fsb = 1066; break; + } + + switch (mch_fsb) + { + case 533: + switch ((mch_cfg >> 4) & 7) + { + case 1: mch_ratio = 125000; break; + case 2: mch_ratio = 150000; break; + case 3: mch_ratio = 200000; break; + } + break; + + case 667: + switch ((mch_cfg >> 4)& 7) + { + case 1: mch_ratio = 100000; break; + case 2: mch_ratio = 120000; break; + case 3: mch_ratio = 160000; break; + case 4: mch_ratio = 200000; break; + case 5: mch_ratio = 240000; break; + } + break; + + default: + case 800: + switch ((mch_cfg >> 4) & 7) + { + case 1: mch_ratio = 83333; break; // 0.833333333 + case 2: mch_ratio = 100000; break; + case 3: mch_ratio = 133333; break; // 1.333333333 + case 4: mch_ratio = 166667; break; // 1.666666667 + case 5: mch_ratio = 200000; break; + } + break; + case 1066: + switch ((mch_cfg >> 4)&7) { + case 5: mch_ratio = 150000; break; + case 6: mch_ratio = 200000; break; + } + + } + + // Compute RAM Frequency + Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000; +} + + +// Get iCore7 Memory Speed +static void get_fsb_nhm(pci_dt_t *dram_dev) +{ + uint32_t mch_ratio, mc_dimm_clk_ratio; + + // Get the clock ratio + mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 ); + mch_ratio = (mc_dimm_clk_ratio & 0x1F); + + // Compute RAM Frequency + Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2; +} + +/* + * Retrieve memory controller info functions + */ + +// Get i965 Memory Timings +static void get_timings_i965(pci_dt_t *dram_dev) +{ + // Thanks for CDH optis + uint32_t dev0, c0ckectrl, c1ckectrl, offset; + uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register; + + long *ptr; + + // Read MMR Base Address + dev0 = pci_config_read32(dram_dev->dev.addr, 0x48); + dev0 &= 0xFFFFC000; + + ptr = (long*)(dev0 + 0x260); + c0ckectrl = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + 0x660); + c1ckectrl = *ptr & 0xFFFFFFFF; + + // If DIMM 0 not populated, check DIMM 1 + ((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400); + + ptr = (long*)(dev0 + offset + 0x29C); + ODT_Control_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x250); + Precharge_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x252); + ACT_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x258); + Read_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x244); + Misc_Register = *ptr & 0xFFFFFFFF; + + // 965 Series only support DDR2 + Platform.RAM.Type = SMB_MEM_TYPE_DDR2; + + // CAS Latency (tCAS) + Platform.RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3; + + // RAS-To-CAS (tRCD) + Platform.RAM.TRC = (Read_Register >> 16) & 0xF; + + // RAS Precharge (tRP) + Platform.RAM.TRP = (ACT_Register >> 13) & 0xF; + + // RAS Active to precharge (tRAS) + Platform.RAM.RAS = (Precharge_Register >> 11) & 0x1F; + + if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) + Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL; + else + Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE; +} + +// Get im965 Memory Timings +static void get_timings_im965(pci_dt_t *dram_dev) +{ + // Thanks for CDH optis + uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register; + long *ptr; + + // Read MMR Base Address + dev0 = pci_config_read32(dram_dev->dev.addr, 0x48); + dev0 &= 0xFFFFC000; + + ptr = (long*)(dev0 + 0x1200); + c0ckectrl = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + 0x1300); + c1ckectrl = *ptr & 0xFFFFFFFF; + + // If DIMM 0 not populated, check DIMM 1 + ((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100); + + ptr = (long*)(dev0 + offset + 0x121C); + ODT_Control_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x1214); + Precharge_Register = *ptr & 0xFFFFFFFF; + + // Series only support DDR2 + Platform.RAM.Type = SMB_MEM_TYPE_DDR2; + + // CAS Latency (tCAS) + Platform.RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3; + + // RAS-To-CAS (tRCD) + Platform.RAM.TRC = ((Precharge_Register >> 5) & 7) + 2; + + // RAS Precharge (tRP) + Platform.RAM.TRP= (Precharge_Register & 7) + 2; + + // RAS Active to precharge (tRAS) + Platform.RAM.RAS = (Precharge_Register >> 21) & 0x1F; + + if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) + Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL; + else + Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE; +} + +// Get P35 Memory Timings +static void get_timings_p35(pci_dt_t *dram_dev) +{ + // Thanks for CDH optis + unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset; + unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register; + long *ptr; + + //Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02); + //Device_ID &= 0xFFFF; + + // Now, read MMR Base Address + dev0 = pci_config_read32(dram_dev->dev.addr, 0x48); + dev0 &= 0xFFFFC000; + + ptr = (long*)(dev0 + 0x260); + c0ckectrl = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + 0x660); + c1ckectrl = *ptr & 0xFFFFFFFF; + + // If DIMM 0 not populated, check DIMM 1 + ((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400); + + ptr = (long*)(dev0 + offset + 0x265); + ODT_Control_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x25D); + Precharge_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x252); + ACT_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x258); + Read_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x244); + Misc_Register = *ptr & 0xFFFFFFFF; + + ptr = (long*)(dev0 + offset + 0x1E8); + Memory_Check = *ptr & 0xFFFFFFFF; + + // On P45, check 1A8 + if(dram_dev->device_id > 0x2E00) { + ptr = (long*)(dev0 + offset + 0x1A8); + Memory_Check = *ptr & 0xFFFFFFFF; + Memory_Check >>= 2; + Memory_Check &= 1; + Memory_Check = !Memory_Check; + } else { + ptr = (long*)(dev0 + offset + 0x1E8); + Memory_Check = *ptr & 0xFFFFFFFF; + } + + // Determine DDR-II or DDR-III + if (Memory_Check & 1) + Platform.RAM.Type = SMB_MEM_TYPE_DDR2; + else + Platform.RAM.Type = SMB_MEM_TYPE_DDR3; + + // CAS Latency (tCAS) + if(dram_dev->device_id > 0x2E00) + Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6; + else + Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9; + + // RAS-To-CAS (tRCD) + Platform.RAM.TRC = (Read_Register >> 17) & 0xF; + + // RAS Precharge (tRP) + Platform.RAM.TRP = (ACT_Register >> 13) & 0xF; + + // RAS Active to precharge (tRAS) + Platform.RAM.RAS = Precharge_Register & 0x3F; + + // Channel configuration + if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) + Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL; + else + Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE; +} + +// Get Nehalem Memory Timings +static void get_timings_nhm(pci_dt_t *dram_dev) +{ + unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value; + int fvc_bn = 4; + + // Find which channels are populated + mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48); + mc_control = (mc_control >> 8) & 0x7; + + // DDR-III + Platform.RAM.Type = SMB_MEM_TYPE_DDR3; + + // Get the first valid channel + if(mc_control & 1) + fvc_bn = 4; + else if(mc_control & 2) + fvc_bn = 5; + else if(mc_control & 7) + fvc_bn = 6; + + // Now, detect timings + mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88); + mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70); + + // CAS Latency (tCAS) + Platform.RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4; + + // RAS-To-CAS (tRCD) + Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; + + // RAS Active to precharge (tRAS) + Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F; + + // RAS Precharge (tRP) + Platform.RAM.TRP = mc_channel_bank_timing & 0xF; + + // Single , Dual or Triple Channels + if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) + Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE; + else if (mc_control == 7) + Platform.RAM.Channels = SMB_MEM_CHANNEL_TRIPLE; + else + Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL; +} + +static struct mem_controller_t dram_controllers[] = { + + // Default unknown chipset + { 0, 0, "", NULL, NULL, NULL }, + + // Intel + { 0x8086, 0x7190, "VMWare", NULL, NULL, NULL }, + + { 0x8086, 0x1A30, "i845", NULL, NULL, NULL }, + + { 0x8086, 0x2970, "i946PL/GZ", setup_p35, get_fsb_i965, get_timings_i965 }, + { 0x8086, 0x2990, "Q963/Q965", setup_p35, get_fsb_i965, get_timings_i965 }, + { 0x8086, 0x29A0, "P965/G965", setup_p35, get_fsb_i965, get_timings_i965 }, + + { 0x8086, 0x2A00, "GM965/GL960", setup_p35, get_fsb_im965, get_timings_im965 }, + { 0x8086, 0x2A10, "GME965/GLE960", setup_p35, get_fsb_im965, get_timings_im965 }, + { 0x8086, 0x2A40, "PM/GM45/47", setup_p35, get_fsb_im965, get_timings_im965 }, + + { 0x8086, 0x29B0, "Q35", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x29C0, "P35/G33", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x29D0, "Q33", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x29E0, "X38/X48", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x2E00, "Eaglelake", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x2E10, "Q45/Q43", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x2E20, "P45/G45", setup_p35, get_fsb_i965, get_timings_p35 }, + { 0x8086, 0x2E30, "G41", setup_p35, get_fsb_i965, get_timings_p35 }, + + { 0x8086, 0xD131, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0xD132, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3400, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3401, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3402, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3403, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3404, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3405, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3406, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + { 0x8086, 0x3407, "NHM IMC", setup_nhm, get_fsb_nhm, get_timings_nhm }, + +}; + +static const char *memory_channel_types[] = +{ + "Unknown", "Single", "Dual", "Triple" +}; + +void scan_dram_controller(pci_dt_t *dram_dev) +{ + int i; + for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++) + if ((dram_controllers[i].vendor == dram_dev->vendor_id) + && (dram_controllers[i].device == dram_dev->device_id)) + { + verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", + (dram_dev->vendor_id == 0x8086) ? "Intel " : "" , + dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id, + dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func); + + if (dram_controllers[i].initialise != NULL) + dram_controllers[i].initialise(dram_dev); + + if (dram_controllers[i].poll_timings != NULL) + dram_controllers[i].poll_timings(dram_dev); + + if (dram_controllers[i].poll_speed != NULL) + dram_controllers[i].poll_speed(dram_dev); + + verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", + (uint32_t)Platform.RAM.Frequency / 1000000, + (uint32_t)Platform.RAM.Frequency / 500000, + memory_channel_types[Platform.RAM.Channels] + ,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS + ,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS + ); + /* getc(); + */ + } +} Index: branches/Chimera/i386/libsaio/.svn/text-base/ext2fs.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ext2fs.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ext2fs.c.svn-base (revision 850) @@ -0,0 +1,42 @@ +/* + * ext2fs.c + * + * + * Created by mackerintel on 1/26/09. + * Copyright 2009 __MyCompanyName__. All rights reserved. + * + */ + +#include "libsaio.h" +#include "sl.h" +#include "ext2fs.h" + +#define EX2ProbeSize 2048 + +bool EX2Probe (const void *buf) +{ + return (OSReadLittleInt16(buf+0x438,0)==0xEF53); +} + +void EX2GetDescription(CICell ih, char *str, long strMaxLen) +{ + char * buf=malloc (EX2ProbeSize); + str[0]=0; + if (!buf) + return; + Seek(ih, 0); + Read(ih, (long)buf, EX2ProbeSize); + if (!EX2Probe (buf)) + { + free (buf); + return; + } + if (OSReadLittleInt32 (buf+0x44c,0)<1) + { + free (buf); + return; + } + str[strMaxLen]=0; + strncpy (str, buf+0x478, min (strMaxLen, 16)); + free (buf); +} Index: branches/Chimera/i386/libsaio/.svn/text-base/hfs_CaseTables.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/hfs_CaseTables.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/hfs_CaseTables.h.svn-base (revision 850) @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2000-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + File: CaseTables.h +*/ + + +/* The lower case table consists of a 256-entry high-byte table followed by some number of + 256-entry subtables. The high-byte table contains either an offset to the subtable for + characters with that high byte or zero, which means that there are no case mappings or + ignored characters in that block. Ignored characters are mapped to zero. + */ + +#if UNCOMPRESSED +u_int16_t gLowerCaseTable[] = { + + // High-byte indices ( == 0 iff no case mapping and no ignorables ) + + /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 5 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 6 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 7 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 8 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 9 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* A */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* B */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* C */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* D */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* E */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* F */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0900, 0x0A00, + + // Table 1 (for high byte 0x00) + + /* 0 */ 0xFFFF, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008, 0x0009, 0x000A, 0x000B, 0x000C, 0x000D, 0x000E, 0x000F, + /* 1 */ 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017, 0x0018, 0x0019, 0x001A, 0x001B, 0x001C, 0x001D, 0x001E, 0x001F, + /* 2 */ 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027, 0x0028, 0x0029, 0x002A, 0x002B, 0x002C, 0x002D, 0x002E, 0x002F, + /* 3 */ 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037, 0x0038, 0x0039, 0x003A, 0x003B, 0x003C, 0x003D, 0x003E, 0x003F, + /* 4 */ 0x0040, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067, 0x0068, 0x0069, 0x006A, 0x006B, 0x006C, 0x006D, 0x006E, 0x006F, + /* 5 */ 0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077, 0x0078, 0x0079, 0x007A, 0x005B, 0x005C, 0x005D, 0x005E, 0x005F, + /* 6 */ 0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067, 0x0068, 0x0069, 0x006A, 0x006B, 0x006C, 0x006D, 0x006E, 0x006F, + /* 7 */ 0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077, 0x0078, 0x0079, 0x007A, 0x007B, 0x007C, 0x007D, 0x007E, 0x007F, + /* 8 */ 0x0080, 0x0081, 0x0082, 0x0083, 0x0084, 0x0085, 0x0086, 0x0087, 0x0088, 0x0089, 0x008A, 0x008B, 0x008C, 0x008D, 0x008E, 0x008F, + /* 9 */ 0x0090, 0x0091, 0x0092, 0x0093, 0x0094, 0x0095, 0x0096, 0x0097, 0x0098, 0x0099, 0x009A, 0x009B, 0x009C, 0x009D, 0x009E, 0x009F, + /* A */ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + /* B */ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + /* C */ 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00E6, 0x00C7, 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + /* D */ 0x00F0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, 0x00F8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00FE, 0x00DF, + /* E */ 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + /* F */ 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF, + + // Table 2 (for high byte 0x01) + + /* 0 */ 0x0100, 0x0101, 0x0102, 0x0103, 0x0104, 0x0105, 0x0106, 0x0107, 0x0108, 0x0109, 0x010A, 0x010B, 0x010C, 0x010D, 0x010E, 0x010F, + /* 1 */ 0x0111, 0x0111, 0x0112, 0x0113, 0x0114, 0x0115, 0x0116, 0x0117, 0x0118, 0x0119, 0x011A, 0x011B, 0x011C, 0x011D, 0x011E, 0x011F, + /* 2 */ 0x0120, 0x0121, 0x0122, 0x0123, 0x0124, 0x0125, 0x0127, 0x0127, 0x0128, 0x0129, 0x012A, 0x012B, 0x012C, 0x012D, 0x012E, 0x012F, + /* 3 */ 0x0130, 0x0131, 0x0133, 0x0133, 0x0134, 0x0135, 0x0136, 0x0137, 0x0138, 0x0139, 0x013A, 0x013B, 0x013C, 0x013D, 0x013E, 0x0140, + /* 4 */ 0x0140, 0x0142, 0x0142, 0x0143, 0x0144, 0x0145, 0x0146, 0x0147, 0x0148, 0x0149, 0x014B, 0x014B, 0x014C, 0x014D, 0x014E, 0x014F, + /* 5 */ 0x0150, 0x0151, 0x0153, 0x0153, 0x0154, 0x0155, 0x0156, 0x0157, 0x0158, 0x0159, 0x015A, 0x015B, 0x015C, 0x015D, 0x015E, 0x015F, + /* 6 */ 0x0160, 0x0161, 0x0162, 0x0163, 0x0164, 0x0165, 0x0167, 0x0167, 0x0168, 0x0169, 0x016A, 0x016B, 0x016C, 0x016D, 0x016E, 0x016F, + /* 7 */ 0x0170, 0x0171, 0x0172, 0x0173, 0x0174, 0x0175, 0x0176, 0x0177, 0x0178, 0x0179, 0x017A, 0x017B, 0x017C, 0x017D, 0x017E, 0x017F, + /* 8 */ 0x0180, 0x0253, 0x0183, 0x0183, 0x0185, 0x0185, 0x0254, 0x0188, 0x0188, 0x0256, 0x0257, 0x018C, 0x018C, 0x018D, 0x01DD, 0x0259, + /* 9 */ 0x025B, 0x0192, 0x0192, 0x0260, 0x0263, 0x0195, 0x0269, 0x0268, 0x0199, 0x0199, 0x019A, 0x019B, 0x026F, 0x0272, 0x019E, 0x0275, + /* A */ 0x01A0, 0x01A1, 0x01A3, 0x01A3, 0x01A5, 0x01A5, 0x01A6, 0x01A8, 0x01A8, 0x0283, 0x01AA, 0x01AB, 0x01AD, 0x01AD, 0x0288, 0x01AF, + /* B */ 0x01B0, 0x028A, 0x028B, 0x01B4, 0x01B4, 0x01B6, 0x01B6, 0x0292, 0x01B9, 0x01B9, 0x01BA, 0x01BB, 0x01BD, 0x01BD, 0x01BE, 0x01BF, + /* C */ 0x01C0, 0x01C1, 0x01C2, 0x01C3, 0x01C6, 0x01C6, 0x01C6, 0x01C9, 0x01C9, 0x01C9, 0x01CC, 0x01CC, 0x01CC, 0x01CD, 0x01CE, 0x01CF, + /* D */ 0x01D0, 0x01D1, 0x01D2, 0x01D3, 0x01D4, 0x01D5, 0x01D6, 0x01D7, 0x01D8, 0x01D9, 0x01DA, 0x01DB, 0x01DC, 0x01DD, 0x01DE, 0x01DF, + /* E */ 0x01E0, 0x01E1, 0x01E2, 0x01E3, 0x01E5, 0x01E5, 0x01E6, 0x01E7, 0x01E8, 0x01E9, 0x01EA, 0x01EB, 0x01EC, 0x01ED, 0x01EE, 0x01EF, + /* F */ 0x01F0, 0x01F3, 0x01F3, 0x01F3, 0x01F4, 0x01F5, 0x01F6, 0x01F7, 0x01F8, 0x01F9, 0x01FA, 0x01FB, 0x01FC, 0x01FD, 0x01FE, 0x01FF, + + // Table 3 (for high byte 0x03) + + /* 0 */ 0x0300, 0x0301, 0x0302, 0x0303, 0x0304, 0x0305, 0x0306, 0x0307, 0x0308, 0x0309, 0x030A, 0x030B, 0x030C, 0x030D, 0x030E, 0x030F, + /* 1 */ 0x0310, 0x0311, 0x0312, 0x0313, 0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031C, 0x031D, 0x031E, 0x031F, + /* 2 */ 0x0320, 0x0321, 0x0322, 0x0323, 0x0324, 0x0325, 0x0326, 0x0327, 0x0328, 0x0329, 0x032A, 0x032B, 0x032C, 0x032D, 0x032E, 0x032F, + /* 3 */ 0x0330, 0x0331, 0x0332, 0x0333, 0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033C, 0x033D, 0x033E, 0x033F, + /* 4 */ 0x0340, 0x0341, 0x0342, 0x0343, 0x0344, 0x0345, 0x0346, 0x0347, 0x0348, 0x0349, 0x034A, 0x034B, 0x034C, 0x034D, 0x034E, 0x034F, + /* 5 */ 0x0350, 0x0351, 0x0352, 0x0353, 0x0354, 0x0355, 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035C, 0x035D, 0x035E, 0x035F, + /* 6 */ 0x0360, 0x0361, 0x0362, 0x0363, 0x0364, 0x0365, 0x0366, 0x0367, 0x0368, 0x0369, 0x036A, 0x036B, 0x036C, 0x036D, 0x036E, 0x036F, + /* 7 */ 0x0370, 0x0371, 0x0372, 0x0373, 0x0374, 0x0375, 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037C, 0x037D, 0x037E, 0x037F, + /* 8 */ 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0386, 0x0387, 0x0388, 0x0389, 0x038A, 0x038B, 0x038C, 0x038D, 0x038E, 0x038F, + /* 9 */ 0x0390, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + /* A */ 0x03C0, 0x03C1, 0x03A2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, 0x03C9, 0x03AA, 0x03AB, 0x03AC, 0x03AD, 0x03AE, 0x03AF, + /* B */ 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + /* C */ 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x03CF, + /* D */ 0x03D0, 0x03D1, 0x03D2, 0x03D3, 0x03D4, 0x03D5, 0x03D6, 0x03D7, 0x03D8, 0x03D9, 0x03DA, 0x03DB, 0x03DC, 0x03DD, 0x03DE, 0x03DF, + /* E */ 0x03E0, 0x03E1, 0x03E3, 0x03E3, 0x03E5, 0x03E5, 0x03E7, 0x03E7, 0x03E9, 0x03E9, 0x03EB, 0x03EB, 0x03ED, 0x03ED, 0x03EF, 0x03EF, + /* F */ 0x03F0, 0x03F1, 0x03F2, 0x03F3, 0x03F4, 0x03F5, 0x03F6, 0x03F7, 0x03F8, 0x03F9, 0x03FA, 0x03FB, 0x03FC, 0x03FD, 0x03FE, 0x03FF, + + // Table 4 (for high byte 0x04) + + /* 0 */ 0x0400, 0x0401, 0x0452, 0x0403, 0x0454, 0x0455, 0x0456, 0x0407, 0x0458, 0x0459, 0x045A, 0x045B, 0x040C, 0x040D, 0x040E, 0x045F, + /* 1 */ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0419, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + /* 2 */ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + /* 3 */ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + /* 4 */ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + /* 5 */ 0x0450, 0x0451, 0x0452, 0x0453, 0x0454, 0x0455, 0x0456, 0x0457, 0x0458, 0x0459, 0x045A, 0x045B, 0x045C, 0x045D, 0x045E, 0x045F, + /* 6 */ 0x0461, 0x0461, 0x0463, 0x0463, 0x0465, 0x0465, 0x0467, 0x0467, 0x0469, 0x0469, 0x046B, 0x046B, 0x046D, 0x046D, 0x046F, 0x046F, + /* 7 */ 0x0471, 0x0471, 0x0473, 0x0473, 0x0475, 0x0475, 0x0476, 0x0477, 0x0479, 0x0479, 0x047B, 0x047B, 0x047D, 0x047D, 0x047F, 0x047F, + /* 8 */ 0x0481, 0x0481, 0x0482, 0x0483, 0x0484, 0x0485, 0x0486, 0x0487, 0x0488, 0x0489, 0x048A, 0x048B, 0x048C, 0x048D, 0x048E, 0x048F, + /* 9 */ 0x0491, 0x0491, 0x0493, 0x0493, 0x0495, 0x0495, 0x0497, 0x0497, 0x0499, 0x0499, 0x049B, 0x049B, 0x049D, 0x049D, 0x049F, 0x049F, + /* A */ 0x04A1, 0x04A1, 0x04A3, 0x04A3, 0x04A5, 0x04A5, 0x04A7, 0x04A7, 0x04A9, 0x04A9, 0x04AB, 0x04AB, 0x04AD, 0x04AD, 0x04AF, 0x04AF, + /* B */ 0x04B1, 0x04B1, 0x04B3, 0x04B3, 0x04B5, 0x04B5, 0x04B7, 0x04B7, 0x04B9, 0x04B9, 0x04BB, 0x04BB, 0x04BD, 0x04BD, 0x04BF, 0x04BF, + /* C */ 0x04C0, 0x04C1, 0x04C2, 0x04C4, 0x04C4, 0x04C5, 0x04C6, 0x04C8, 0x04C8, 0x04C9, 0x04CA, 0x04CC, 0x04CC, 0x04CD, 0x04CE, 0x04CF, + /* D */ 0x04D0, 0x04D1, 0x04D2, 0x04D3, 0x04D4, 0x04D5, 0x04D6, 0x04D7, 0x04D8, 0x04D9, 0x04DA, 0x04DB, 0x04DC, 0x04DD, 0x04DE, 0x04DF, + /* E */ 0x04E0, 0x04E1, 0x04E2, 0x04E3, 0x04E4, 0x04E5, 0x04E6, 0x04E7, 0x04E8, 0x04E9, 0x04EA, 0x04EB, 0x04EC, 0x04ED, 0x04EE, 0x04EF, + /* F */ 0x04F0, 0x04F1, 0x04F2, 0x04F3, 0x04F4, 0x04F5, 0x04F6, 0x04F7, 0x04F8, 0x04F9, 0x04FA, 0x04FB, 0x04FC, 0x04FD, 0x04FE, 0x04FF, + + // Table 5 (for high byte 0x05) + + /* 0 */ 0x0500, 0x0501, 0x0502, 0x0503, 0x0504, 0x0505, 0x0506, 0x0507, 0x0508, 0x0509, 0x050A, 0x050B, 0x050C, 0x050D, 0x050E, 0x050F, + /* 1 */ 0x0510, 0x0511, 0x0512, 0x0513, 0x0514, 0x0515, 0x0516, 0x0517, 0x0518, 0x0519, 0x051A, 0x051B, 0x051C, 0x051D, 0x051E, 0x051F, + /* 2 */ 0x0520, 0x0521, 0x0522, 0x0523, 0x0524, 0x0525, 0x0526, 0x0527, 0x0528, 0x0529, 0x052A, 0x052B, 0x052C, 0x052D, 0x052E, 0x052F, + /* 3 */ 0x0530, 0x0561, 0x0562, 0x0563, 0x0564, 0x0565, 0x0566, 0x0567, 0x0568, 0x0569, 0x056A, 0x056B, 0x056C, 0x056D, 0x056E, 0x056F, + /* 4 */ 0x0570, 0x0571, 0x0572, 0x0573, 0x0574, 0x0575, 0x0576, 0x0577, 0x0578, 0x0579, 0x057A, 0x057B, 0x057C, 0x057D, 0x057E, 0x057F, + /* 5 */ 0x0580, 0x0581, 0x0582, 0x0583, 0x0584, 0x0585, 0x0586, 0x0557, 0x0558, 0x0559, 0x055A, 0x055B, 0x055C, 0x055D, 0x055E, 0x055F, + /* 6 */ 0x0560, 0x0561, 0x0562, 0x0563, 0x0564, 0x0565, 0x0566, 0x0567, 0x0568, 0x0569, 0x056A, 0x056B, 0x056C, 0x056D, 0x056E, 0x056F, + /* 7 */ 0x0570, 0x0571, 0x0572, 0x0573, 0x0574, 0x0575, 0x0576, 0x0577, 0x0578, 0x0579, 0x057A, 0x057B, 0x057C, 0x057D, 0x057E, 0x057F, + /* 8 */ 0x0580, 0x0581, 0x0582, 0x0583, 0x0584, 0x0585, 0x0586, 0x0587, 0x0588, 0x0589, 0x058A, 0x058B, 0x058C, 0x058D, 0x058E, 0x058F, + /* 9 */ 0x0590, 0x0591, 0x0592, 0x0593, 0x0594, 0x0595, 0x0596, 0x0597, 0x0598, 0x0599, 0x059A, 0x059B, 0x059C, 0x059D, 0x059E, 0x059F, + /* A */ 0x05A0, 0x05A1, 0x05A2, 0x05A3, 0x05A4, 0x05A5, 0x05A6, 0x05A7, 0x05A8, 0x05A9, 0x05AA, 0x05AB, 0x05AC, 0x05AD, 0x05AE, 0x05AF, + /* B */ 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, 0x05B8, 0x05B9, 0x05BA, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, + /* C */ 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05C4, 0x05C5, 0x05C6, 0x05C7, 0x05C8, 0x05C9, 0x05CA, 0x05CB, 0x05CC, 0x05CD, 0x05CE, 0x05CF, + /* D */ 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + /* E */ 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x05EB, 0x05EC, 0x05ED, 0x05EE, 0x05EF, + /* F */ 0x05F0, 0x05F1, 0x05F2, 0x05F3, 0x05F4, 0x05F5, 0x05F6, 0x05F7, 0x05F8, 0x05F9, 0x05FA, 0x05FB, 0x05FC, 0x05FD, 0x05FE, 0x05FF, + + // Table 6 (for high byte 0x10) + + /* 0 */ 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, 0x1006, 0x1007, 0x1008, 0x1009, 0x100A, 0x100B, 0x100C, 0x100D, 0x100E, 0x100F, + /* 1 */ 0x1010, 0x1011, 0x1012, 0x1013, 0x1014, 0x1015, 0x1016, 0x1017, 0x1018, 0x1019, 0x101A, 0x101B, 0x101C, 0x101D, 0x101E, 0x101F, + /* 2 */ 0x1020, 0x1021, 0x1022, 0x1023, 0x1024, 0x1025, 0x1026, 0x1027, 0x1028, 0x1029, 0x102A, 0x102B, 0x102C, 0x102D, 0x102E, 0x102F, + /* 3 */ 0x1030, 0x1031, 0x1032, 0x1033, 0x1034, 0x1035, 0x1036, 0x1037, 0x1038, 0x1039, 0x103A, 0x103B, 0x103C, 0x103D, 0x103E, 0x103F, + /* 4 */ 0x1040, 0x1041, 0x1042, 0x1043, 0x1044, 0x1045, 0x1046, 0x1047, 0x1048, 0x1049, 0x104A, 0x104B, 0x104C, 0x104D, 0x104E, 0x104F, + /* 5 */ 0x1050, 0x1051, 0x1052, 0x1053, 0x1054, 0x1055, 0x1056, 0x1057, 0x1058, 0x1059, 0x105A, 0x105B, 0x105C, 0x105D, 0x105E, 0x105F, + /* 6 */ 0x1060, 0x1061, 0x1062, 0x1063, 0x1064, 0x1065, 0x1066, 0x1067, 0x1068, 0x1069, 0x106A, 0x106B, 0x106C, 0x106D, 0x106E, 0x106F, + /* 7 */ 0x1070, 0x1071, 0x1072, 0x1073, 0x1074, 0x1075, 0x1076, 0x1077, 0x1078, 0x1079, 0x107A, 0x107B, 0x107C, 0x107D, 0x107E, 0x107F, + /* 8 */ 0x1080, 0x1081, 0x1082, 0x1083, 0x1084, 0x1085, 0x1086, 0x1087, 0x1088, 0x1089, 0x108A, 0x108B, 0x108C, 0x108D, 0x108E, 0x108F, + /* 9 */ 0x1090, 0x1091, 0x1092, 0x1093, 0x1094, 0x1095, 0x1096, 0x1097, 0x1098, 0x1099, 0x109A, 0x109B, 0x109C, 0x109D, 0x109E, 0x109F, + /* A */ 0x10D0, 0x10D1, 0x10D2, 0x10D3, 0x10D4, 0x10D5, 0x10D6, 0x10D7, 0x10D8, 0x10D9, 0x10DA, 0x10DB, 0x10DC, 0x10DD, 0x10DE, 0x10DF, + /* B */ 0x10E0, 0x10E1, 0x10E2, 0x10E3, 0x10E4, 0x10E5, 0x10E6, 0x10E7, 0x10E8, 0x10E9, 0x10EA, 0x10EB, 0x10EC, 0x10ED, 0x10EE, 0x10EF, + /* C */ 0x10F0, 0x10F1, 0x10F2, 0x10F3, 0x10F4, 0x10F5, 0x10C6, 0x10C7, 0x10C8, 0x10C9, 0x10CA, 0x10CB, 0x10CC, 0x10CD, 0x10CE, 0x10CF, + /* D */ 0x10D0, 0x10D1, 0x10D2, 0x10D3, 0x10D4, 0x10D5, 0x10D6, 0x10D7, 0x10D8, 0x10D9, 0x10DA, 0x10DB, 0x10DC, 0x10DD, 0x10DE, 0x10DF, + /* E */ 0x10E0, 0x10E1, 0x10E2, 0x10E3, 0x10E4, 0x10E5, 0x10E6, 0x10E7, 0x10E8, 0x10E9, 0x10EA, 0x10EB, 0x10EC, 0x10ED, 0x10EE, 0x10EF, + /* F */ 0x10F0, 0x10F1, 0x10F2, 0x10F3, 0x10F4, 0x10F5, 0x10F6, 0x10F7, 0x10F8, 0x10F9, 0x10FA, 0x10FB, 0x10FC, 0x10FD, 0x10FE, 0x10FF, + + // Table 7 (for high byte 0x20) + + /* 0 */ 0x2000, 0x2001, 0x2002, 0x2003, 0x2004, 0x2005, 0x2006, 0x2007, 0x2008, 0x2009, 0x200A, 0x200B, 0x0000, 0x0000, 0x0000, 0x0000, + /* 1 */ 0x2010, 0x2011, 0x2012, 0x2013, 0x2014, 0x2015, 0x2016, 0x2017, 0x2018, 0x2019, 0x201A, 0x201B, 0x201C, 0x201D, 0x201E, 0x201F, + /* 2 */ 0x2020, 0x2021, 0x2022, 0x2023, 0x2024, 0x2025, 0x2026, 0x2027, 0x2028, 0x2029, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x202F, + /* 3 */ 0x2030, 0x2031, 0x2032, 0x2033, 0x2034, 0x2035, 0x2036, 0x2037, 0x2038, 0x2039, 0x203A, 0x203B, 0x203C, 0x203D, 0x203E, 0x203F, + /* 4 */ 0x2040, 0x2041, 0x2042, 0x2043, 0x2044, 0x2045, 0x2046, 0x2047, 0x2048, 0x2049, 0x204A, 0x204B, 0x204C, 0x204D, 0x204E, 0x204F, + /* 5 */ 0x2050, 0x2051, 0x2052, 0x2053, 0x2054, 0x2055, 0x2056, 0x2057, 0x2058, 0x2059, 0x205A, 0x205B, 0x205C, 0x205D, 0x205E, 0x205F, + /* 6 */ 0x2060, 0x2061, 0x2062, 0x2063, 0x2064, 0x2065, 0x2066, 0x2067, 0x2068, 0x2069, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 7 */ 0x2070, 0x2071, 0x2072, 0x2073, 0x2074, 0x2075, 0x2076, 0x2077, 0x2078, 0x2079, 0x207A, 0x207B, 0x207C, 0x207D, 0x207E, 0x207F, + /* 8 */ 0x2080, 0x2081, 0x2082, 0x2083, 0x2084, 0x2085, 0x2086, 0x2087, 0x2088, 0x2089, 0x208A, 0x208B, 0x208C, 0x208D, 0x208E, 0x208F, + /* 9 */ 0x2090, 0x2091, 0x2092, 0x2093, 0x2094, 0x2095, 0x2096, 0x2097, 0x2098, 0x2099, 0x209A, 0x209B, 0x209C, 0x209D, 0x209E, 0x209F, + /* A */ 0x20A0, 0x20A1, 0x20A2, 0x20A3, 0x20A4, 0x20A5, 0x20A6, 0x20A7, 0x20A8, 0x20A9, 0x20AA, 0x20AB, 0x20AC, 0x20AD, 0x20AE, 0x20AF, + /* B */ 0x20B0, 0x20B1, 0x20B2, 0x20B3, 0x20B4, 0x20B5, 0x20B6, 0x20B7, 0x20B8, 0x20B9, 0x20BA, 0x20BB, 0x20BC, 0x20BD, 0x20BE, 0x20BF, + /* C */ 0x20C0, 0x20C1, 0x20C2, 0x20C3, 0x20C4, 0x20C5, 0x20C6, 0x20C7, 0x20C8, 0x20C9, 0x20CA, 0x20CB, 0x20CC, 0x20CD, 0x20CE, 0x20CF, + /* D */ 0x20D0, 0x20D1, 0x20D2, 0x20D3, 0x20D4, 0x20D5, 0x20D6, 0x20D7, 0x20D8, 0x20D9, 0x20DA, 0x20DB, 0x20DC, 0x20DD, 0x20DE, 0x20DF, + /* E */ 0x20E0, 0x20E1, 0x20E2, 0x20E3, 0x20E4, 0x20E5, 0x20E6, 0x20E7, 0x20E8, 0x20E9, 0x20EA, 0x20EB, 0x20EC, 0x20ED, 0x20EE, 0x20EF, + /* F */ 0x20F0, 0x20F1, 0x20F2, 0x20F3, 0x20F4, 0x20F5, 0x20F6, 0x20F7, 0x20F8, 0x20F9, 0x20FA, 0x20FB, 0x20FC, 0x20FD, 0x20FE, 0x20FF, + + // Table 8 (for high byte 0x21) + + /* 0 */ 0x2100, 0x2101, 0x2102, 0x2103, 0x2104, 0x2105, 0x2106, 0x2107, 0x2108, 0x2109, 0x210A, 0x210B, 0x210C, 0x210D, 0x210E, 0x210F, + /* 1 */ 0x2110, 0x2111, 0x2112, 0x2113, 0x2114, 0x2115, 0x2116, 0x2117, 0x2118, 0x2119, 0x211A, 0x211B, 0x211C, 0x211D, 0x211E, 0x211F, + /* 2 */ 0x2120, 0x2121, 0x2122, 0x2123, 0x2124, 0x2125, 0x2126, 0x2127, 0x2128, 0x2129, 0x212A, 0x212B, 0x212C, 0x212D, 0x212E, 0x212F, + /* 3 */ 0x2130, 0x2131, 0x2132, 0x2133, 0x2134, 0x2135, 0x2136, 0x2137, 0x2138, 0x2139, 0x213A, 0x213B, 0x213C, 0x213D, 0x213E, 0x213F, + /* 4 */ 0x2140, 0x2141, 0x2142, 0x2143, 0x2144, 0x2145, 0x2146, 0x2147, 0x2148, 0x2149, 0x214A, 0x214B, 0x214C, 0x214D, 0x214E, 0x214F, + /* 5 */ 0x2150, 0x2151, 0x2152, 0x2153, 0x2154, 0x2155, 0x2156, 0x2157, 0x2158, 0x2159, 0x215A, 0x215B, 0x215C, 0x215D, 0x215E, 0x215F, + /* 6 */ 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, + /* 7 */ 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, + /* 8 */ 0x2180, 0x2181, 0x2182, 0x2183, 0x2184, 0x2185, 0x2186, 0x2187, 0x2188, 0x2189, 0x218A, 0x218B, 0x218C, 0x218D, 0x218E, 0x218F, + /* 9 */ 0x2190, 0x2191, 0x2192, 0x2193, 0x2194, 0x2195, 0x2196, 0x2197, 0x2198, 0x2199, 0x219A, 0x219B, 0x219C, 0x219D, 0x219E, 0x219F, + /* A */ 0x21A0, 0x21A1, 0x21A2, 0x21A3, 0x21A4, 0x21A5, 0x21A6, 0x21A7, 0x21A8, 0x21A9, 0x21AA, 0x21AB, 0x21AC, 0x21AD, 0x21AE, 0x21AF, + /* B */ 0x21B0, 0x21B1, 0x21B2, 0x21B3, 0x21B4, 0x21B5, 0x21B6, 0x21B7, 0x21B8, 0x21B9, 0x21BA, 0x21BB, 0x21BC, 0x21BD, 0x21BE, 0x21BF, + /* C */ 0x21C0, 0x21C1, 0x21C2, 0x21C3, 0x21C4, 0x21C5, 0x21C6, 0x21C7, 0x21C8, 0x21C9, 0x21CA, 0x21CB, 0x21CC, 0x21CD, 0x21CE, 0x21CF, + /* D */ 0x21D0, 0x21D1, 0x21D2, 0x21D3, 0x21D4, 0x21D5, 0x21D6, 0x21D7, 0x21D8, 0x21D9, 0x21DA, 0x21DB, 0x21DC, 0x21DD, 0x21DE, 0x21DF, + /* E */ 0x21E0, 0x21E1, 0x21E2, 0x21E3, 0x21E4, 0x21E5, 0x21E6, 0x21E7, 0x21E8, 0x21E9, 0x21EA, 0x21EB, 0x21EC, 0x21ED, 0x21EE, 0x21EF, + /* F */ 0x21F0, 0x21F1, 0x21F2, 0x21F3, 0x21F4, 0x21F5, 0x21F6, 0x21F7, 0x21F8, 0x21F9, 0x21FA, 0x21FB, 0x21FC, 0x21FD, 0x21FE, 0x21FF, + + // Table 9 (for high byte 0xFE) + + /* 0 */ 0xFE00, 0xFE01, 0xFE02, 0xFE03, 0xFE04, 0xFE05, 0xFE06, 0xFE07, 0xFE08, 0xFE09, 0xFE0A, 0xFE0B, 0xFE0C, 0xFE0D, 0xFE0E, 0xFE0F, + /* 1 */ 0xFE10, 0xFE11, 0xFE12, 0xFE13, 0xFE14, 0xFE15, 0xFE16, 0xFE17, 0xFE18, 0xFE19, 0xFE1A, 0xFE1B, 0xFE1C, 0xFE1D, 0xFE1E, 0xFE1F, + /* 2 */ 0xFE20, 0xFE21, 0xFE22, 0xFE23, 0xFE24, 0xFE25, 0xFE26, 0xFE27, 0xFE28, 0xFE29, 0xFE2A, 0xFE2B, 0xFE2C, 0xFE2D, 0xFE2E, 0xFE2F, + /* 3 */ 0xFE30, 0xFE31, 0xFE32, 0xFE33, 0xFE34, 0xFE35, 0xFE36, 0xFE37, 0xFE38, 0xFE39, 0xFE3A, 0xFE3B, 0xFE3C, 0xFE3D, 0xFE3E, 0xFE3F, + /* 4 */ 0xFE40, 0xFE41, 0xFE42, 0xFE43, 0xFE44, 0xFE45, 0xFE46, 0xFE47, 0xFE48, 0xFE49, 0xFE4A, 0xFE4B, 0xFE4C, 0xFE4D, 0xFE4E, 0xFE4F, + /* 5 */ 0xFE50, 0xFE51, 0xFE52, 0xFE53, 0xFE54, 0xFE55, 0xFE56, 0xFE57, 0xFE58, 0xFE59, 0xFE5A, 0xFE5B, 0xFE5C, 0xFE5D, 0xFE5E, 0xFE5F, + /* 6 */ 0xFE60, 0xFE61, 0xFE62, 0xFE63, 0xFE64, 0xFE65, 0xFE66, 0xFE67, 0xFE68, 0xFE69, 0xFE6A, 0xFE6B, 0xFE6C, 0xFE6D, 0xFE6E, 0xFE6F, + /* 7 */ 0xFE70, 0xFE71, 0xFE72, 0xFE73, 0xFE74, 0xFE75, 0xFE76, 0xFE77, 0xFE78, 0xFE79, 0xFE7A, 0xFE7B, 0xFE7C, 0xFE7D, 0xFE7E, 0xFE7F, + /* 8 */ 0xFE80, 0xFE81, 0xFE82, 0xFE83, 0xFE84, 0xFE85, 0xFE86, 0xFE87, 0xFE88, 0xFE89, 0xFE8A, 0xFE8B, 0xFE8C, 0xFE8D, 0xFE8E, 0xFE8F, + /* 9 */ 0xFE90, 0xFE91, 0xFE92, 0xFE93, 0xFE94, 0xFE95, 0xFE96, 0xFE97, 0xFE98, 0xFE99, 0xFE9A, 0xFE9B, 0xFE9C, 0xFE9D, 0xFE9E, 0xFE9F, + /* A */ 0xFEA0, 0xFEA1, 0xFEA2, 0xFEA3, 0xFEA4, 0xFEA5, 0xFEA6, 0xFEA7, 0xFEA8, 0xFEA9, 0xFEAA, 0xFEAB, 0xFEAC, 0xFEAD, 0xFEAE, 0xFEAF, + /* B */ 0xFEB0, 0xFEB1, 0xFEB2, 0xFEB3, 0xFEB4, 0xFEB5, 0xFEB6, 0xFEB7, 0xFEB8, 0xFEB9, 0xFEBA, 0xFEBB, 0xFEBC, 0xFEBD, 0xFEBE, 0xFEBF, + /* C */ 0xFEC0, 0xFEC1, 0xFEC2, 0xFEC3, 0xFEC4, 0xFEC5, 0xFEC6, 0xFEC7, 0xFEC8, 0xFEC9, 0xFECA, 0xFECB, 0xFECC, 0xFECD, 0xFECE, 0xFECF, + /* D */ 0xFED0, 0xFED1, 0xFED2, 0xFED3, 0xFED4, 0xFED5, 0xFED6, 0xFED7, 0xFED8, 0xFED9, 0xFEDA, 0xFEDB, 0xFEDC, 0xFEDD, 0xFEDE, 0xFEDF, + /* E */ 0xFEE0, 0xFEE1, 0xFEE2, 0xFEE3, 0xFEE4, 0xFEE5, 0xFEE6, 0xFEE7, 0xFEE8, 0xFEE9, 0xFEEA, 0xFEEB, 0xFEEC, 0xFEED, 0xFEEE, 0xFEEF, + /* F */ 0xFEF0, 0xFEF1, 0xFEF2, 0xFEF3, 0xFEF4, 0xFEF5, 0xFEF6, 0xFEF7, 0xFEF8, 0xFEF9, 0xFEFA, 0xFEFB, 0xFEFC, 0xFEFD, 0xFEFE, 0x0000, + + // Table 10 (for high byte 0xFF) + + /* 0 */ 0xFF00, 0xFF01, 0xFF02, 0xFF03, 0xFF04, 0xFF05, 0xFF06, 0xFF07, 0xFF08, 0xFF09, 0xFF0A, 0xFF0B, 0xFF0C, 0xFF0D, 0xFF0E, 0xFF0F, + /* 1 */ 0xFF10, 0xFF11, 0xFF12, 0xFF13, 0xFF14, 0xFF15, 0xFF16, 0xFF17, 0xFF18, 0xFF19, 0xFF1A, 0xFF1B, 0xFF1C, 0xFF1D, 0xFF1E, 0xFF1F, + /* 2 */ 0xFF20, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, + /* 3 */ 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0xFF3B, 0xFF3C, 0xFF3D, 0xFF3E, 0xFF3F, + /* 4 */ 0xFF40, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, + /* 5 */ 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0xFF5B, 0xFF5C, 0xFF5D, 0xFF5E, 0xFF5F, + /* 6 */ 0xFF60, 0xFF61, 0xFF62, 0xFF63, 0xFF64, 0xFF65, 0xFF66, 0xFF67, 0xFF68, 0xFF69, 0xFF6A, 0xFF6B, 0xFF6C, 0xFF6D, 0xFF6E, 0xFF6F, + /* 7 */ 0xFF70, 0xFF71, 0xFF72, 0xFF73, 0xFF74, 0xFF75, 0xFF76, 0xFF77, 0xFF78, 0xFF79, 0xFF7A, 0xFF7B, 0xFF7C, 0xFF7D, 0xFF7E, 0xFF7F, + /* 8 */ 0xFF80, 0xFF81, 0xFF82, 0xFF83, 0xFF84, 0xFF85, 0xFF86, 0xFF87, 0xFF88, 0xFF89, 0xFF8A, 0xFF8B, 0xFF8C, 0xFF8D, 0xFF8E, 0xFF8F, + /* 9 */ 0xFF90, 0xFF91, 0xFF92, 0xFF93, 0xFF94, 0xFF95, 0xFF96, 0xFF97, 0xFF98, 0xFF99, 0xFF9A, 0xFF9B, 0xFF9C, 0xFF9D, 0xFF9E, 0xFF9F, + /* A */ 0xFFA0, 0xFFA1, 0xFFA2, 0xFFA3, 0xFFA4, 0xFFA5, 0xFFA6, 0xFFA7, 0xFFA8, 0xFFA9, 0xFFAA, 0xFFAB, 0xFFAC, 0xFFAD, 0xFFAE, 0xFFAF, + /* B */ 0xFFB0, 0xFFB1, 0xFFB2, 0xFFB3, 0xFFB4, 0xFFB5, 0xFFB6, 0xFFB7, 0xFFB8, 0xFFB9, 0xFFBA, 0xFFBB, 0xFFBC, 0xFFBD, 0xFFBE, 0xFFBF, + /* C */ 0xFFC0, 0xFFC1, 0xFFC2, 0xFFC3, 0xFFC4, 0xFFC5, 0xFFC6, 0xFFC7, 0xFFC8, 0xFFC9, 0xFFCA, 0xFFCB, 0xFFCC, 0xFFCD, 0xFFCE, 0xFFCF, + /* D */ 0xFFD0, 0xFFD1, 0xFFD2, 0xFFD3, 0xFFD4, 0xFFD5, 0xFFD6, 0xFFD7, 0xFFD8, 0xFFD9, 0xFFDA, 0xFFDB, 0xFFDC, 0xFFDD, 0xFFDE, 0xFFDF, + /* E */ 0xFFE0, 0xFFE1, 0xFFE2, 0xFFE3, 0xFFE4, 0xFFE5, 0xFFE6, 0xFFE7, 0xFFE8, 0xFFE9, 0xFFEA, 0xFFEB, 0xFFEC, 0xFFED, 0xFFEE, 0xFFEF, + /* F */ 0xFFF0, 0xFFF1, 0xFFF2, 0xFFF3, 0xFFF4, 0xFFF5, 0xFFF6, 0xFFF7, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0xFFFF, +}; + +/* RelString case folding table */ + +unsigned short gCompareTable[] = { + + /* 0 */ 0x0000, 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700, 0x0800, 0x0900, 0x0A00, 0x0B00, 0x0C00, 0x0D00, 0x0E00, 0x0F00, + /* 1 */ 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500, 0x1600, 0x1700, 0x1800, 0x1900, 0x1A00, 0x1B00, 0x1C00, 0x1D00, 0x1E00, 0x1F00, + /* 2 */ 0x2000, 0x2100, 0x2200, 0x2300, 0x2400, 0x2500, 0x2600, 0x2700, 0x2800, 0x2900, 0x2A00, 0x2B00, 0x2C00, 0x2D00, 0x2E00, 0x2F00, + /* 3 */ 0x3000, 0x3100, 0x3200, 0x3300, 0x3400, 0x3500, 0x3600, 0x3700, 0x3800, 0x3900, 0x3A00, 0x3B00, 0x3C00, 0x3D00, 0x3E00, 0x3F00, + /* 4 */ 0x4000, 0x4100, 0x4200, 0x4300, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800, 0x4900, 0x4A00, 0x4B00, 0x4C00, 0x4D00, 0x4E00, 0x4F00, + /* 5 */ 0x5000, 0x5100, 0x5200, 0x5300, 0x5400, 0x5500, 0x5600, 0x5700, 0x5800, 0x5900, 0x5A00, 0x5B00, 0x5C00, 0x5D00, 0x5E00, 0x5F00, + + // 0x60 maps to 'a' + // range 0x61 to 0x7a ('a' to 'z') map to upper case + + /* 6 */ 0x4180, 0x4100, 0x4200, 0x4300, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800, 0x4900, 0x4A00, 0x4B00, 0x4C00, 0x4D00, 0x4E00, 0x4F00, + /* 7 */ 0x5000, 0x5100, 0x5200, 0x5300, 0x5400, 0x5500, 0x5600, 0x5700, 0x5800, 0x5900, 0x5A00, 0x7B00, 0x7C00, 0x7D00, 0x7E00, 0x7F00, + + // range 0x80 to 0xd8 gets mapped... + + /* 8 */ 0x4108, 0x410C, 0x4310, 0x4502, 0x4E0A, 0x4F08, 0x5508, 0x4182, 0x4104, 0x4186, 0x4108, 0x410A, 0x410C, 0x4310, 0x4502, 0x4584, + /* 9 */ 0x4586, 0x4588, 0x4982, 0x4984, 0x4986, 0x4988, 0x4E0A, 0x4F82, 0x4F84, 0x4F86, 0x4F08, 0x4F0A, 0x5582, 0x5584, 0x5586, 0x5508, + /* A */ 0xA000, 0xA100, 0xA200, 0xA300, 0xA400, 0xA500, 0xA600, 0x5382, 0xA800, 0xA900, 0xAA00, 0xAB00, 0xAC00, 0xAD00, 0x4114, 0x4F0E, + /* B */ 0xB000, 0xB100, 0xB200, 0xB300, 0xB400, 0xB500, 0xB600, 0xB700, 0xB800, 0xB900, 0xBA00, 0x4192, 0x4F92, 0xBD00, 0x4114, 0x4F0E, + /* C */ 0xC000, 0xC100, 0xC200, 0xC300, 0xC400, 0xC500, 0xC600, 0x2206, 0x2208, 0xC900, 0x2000, 0x4104, 0x410A, 0x4F0A, 0x4F14, 0x4F14, + /* D */ 0xD000, 0xD100, 0x2202, 0x2204, 0x2702, 0x2704, 0xD600, 0xD700, 0x5988, 0xD900, 0xDA00, 0xDB00, 0xDC00, 0xDD00, 0xDE00, 0xDF00, + + /* E */ 0xE000, 0xE100, 0xE200, 0xE300, 0xE400, 0xE500, 0xE600, 0xE700, 0xE800, 0xE900, 0xEA00, 0xEB00, 0xEC00, 0xED00, 0xEE00, 0xEF00, + /* F */ 0xF000, 0xF100, 0xF200, 0xF300, 0xF400, 0xF500, 0xF600, 0xF700, 0xF800, 0xF900, 0xFA00, 0xFB00, 0xFC00, 0xFD00, 0xFE00, 0xFF00, + +}; +#else /* ! UNCOMPRESSED */ + +enum { + kTypeLiteral = 0, + kTypeAscending = 1, + kTypeAscending256 = 2 +}; + +struct compressed_block { + unsigned char type; + unsigned char count; + unsigned short data; +}; + +unsigned short *gLowerCaseTable; + +struct compressed_block gLowerCaseTableCompressed[] = { + {0x0, 0x1, 0x100}, + {0x0, 0x1, 0x200}, + {0x0, 0x1, 0x0}, + {0x0, 0x1, 0x300}, + {0x0, 0x1, 0x400}, + {0x0, 0x1, 0x500}, + {0x0, 0xa, 0x0}, + {0x0, 0x1, 0x600}, + {0x0, 0xf, 0x0}, + {0x0, 0x1, 0x700}, + {0x0, 0x1, 0x800}, + {0x0, 0xdc, 0x0}, + {0x0, 0x1, 0x900}, + {0x0, 0x1, 0xa00}, + {0x0, 0x1, 0xffff}, + {0x1, 0x40, 0x1}, + {0x1, 0x1a, 0x61}, + {0x1, 0x6b, 0x5b}, + {0x0, 0x1, 0xe6}, + {0x1, 0x9, 0xc7}, + {0x0, 0x1, 0xf0}, + {0x1, 0x7, 0xd1}, + {0x0, 0x1, 0xf8}, + {0x1, 0x5, 0xd9}, + {0x0, 0x1, 0xfe}, + {0x1, 0x31, 0xdf}, + {0x0, 0x2, 0x111}, + {0x1, 0x14, 0x112}, + {0x0, 0x2, 0x127}, + {0x1, 0xa, 0x128}, + {0x0, 0x2, 0x133}, + {0x1, 0xb, 0x134}, + {0x0, 0x2, 0x140}, + {0x0, 0x2, 0x142}, + {0x1, 0x7, 0x143}, + {0x0, 0x2, 0x14b}, + {0x1, 0x6, 0x14c}, + {0x0, 0x2, 0x153}, + {0x1, 0x12, 0x154}, + {0x0, 0x2, 0x167}, + {0x1, 0x19, 0x168}, + {0x0, 0x1, 0x253}, + {0x0, 0x2, 0x183}, + {0x0, 0x2, 0x185}, + {0x0, 0x1, 0x254}, + {0x0, 0x2, 0x188}, + {0x1, 0x2, 0x256}, + {0x0, 0x2, 0x18c}, + {0x0, 0x1, 0x18d}, + {0x0, 0x1, 0x1dd}, + {0x0, 0x1, 0x259}, + {0x0, 0x1, 0x25b}, + {0x0, 0x2, 0x192}, + {0x0, 0x1, 0x260}, + {0x0, 0x1, 0x263}, + {0x0, 0x1, 0x195}, + {0x0, 0x1, 0x269}, + {0x0, 0x1, 0x268}, + {0x0, 0x2, 0x199}, + {0x1, 0x2, 0x19a}, + {0x0, 0x1, 0x26f}, + {0x0, 0x1, 0x272}, + {0x0, 0x1, 0x19e}, + {0x0, 0x1, 0x275}, + {0x1, 0x2, 0x1a0}, + {0x0, 0x2, 0x1a3}, + {0x0, 0x2, 0x1a5}, + {0x0, 0x1, 0x1a6}, + {0x0, 0x2, 0x1a8}, + {0x0, 0x1, 0x283}, + {0x1, 0x2, 0x1aa}, + {0x0, 0x2, 0x1ad}, + {0x0, 0x1, 0x288}, + {0x1, 0x2, 0x1af}, + {0x1, 0x2, 0x28a}, + {0x0, 0x2, 0x1b4}, + {0x0, 0x2, 0x1b6}, + {0x0, 0x1, 0x292}, + {0x0, 0x2, 0x1b9}, + {0x1, 0x2, 0x1ba}, + {0x0, 0x2, 0x1bd}, + {0x1, 0x6, 0x1be}, + {0x0, 0x3, 0x1c6}, + {0x0, 0x3, 0x1c9}, + {0x0, 0x3, 0x1cc}, + {0x1, 0x17, 0x1cd}, + {0x0, 0x2, 0x1e5}, + {0x1, 0xb, 0x1e6}, + {0x0, 0x3, 0x1f3}, + {0x1, 0xc, 0x1f4}, + {0x1, 0x91, 0x300}, + {0x1, 0x11, 0x3b1}, + {0x0, 0x1, 0x3a2}, + {0x1, 0x7, 0x3c3}, + {0x1, 0x38, 0x3aa}, + {0x0, 0x2, 0x3e3}, + {0x0, 0x2, 0x3e5}, + {0x0, 0x2, 0x3e7}, + {0x0, 0x2, 0x3e9}, + {0x0, 0x2, 0x3eb}, + {0x0, 0x2, 0x3ed}, + {0x0, 0x2, 0x3ef}, + {0x1, 0x12, 0x3f0}, + {0x0, 0x1, 0x452}, + {0x0, 0x1, 0x403}, + {0x1, 0x3, 0x454}, + {0x0, 0x1, 0x407}, + {0x1, 0x4, 0x458}, + {0x1, 0x3, 0x40c}, + {0x0, 0x1, 0x45f}, + {0x1, 0x9, 0x430}, + {0x0, 0x1, 0x419}, + {0x1, 0x16, 0x43a}, + {0x1, 0x30, 0x430}, + {0x0, 0x2, 0x461}, + {0x0, 0x2, 0x463}, + {0x0, 0x2, 0x465}, + {0x0, 0x2, 0x467}, + {0x0, 0x2, 0x469}, + {0x0, 0x2, 0x46b}, + {0x0, 0x2, 0x46d}, + {0x0, 0x2, 0x46f}, + {0x0, 0x2, 0x471}, + {0x0, 0x2, 0x473}, + {0x0, 0x2, 0x475}, + {0x1, 0x2, 0x476}, + {0x0, 0x2, 0x479}, + {0x0, 0x2, 0x47b}, + {0x0, 0x2, 0x47d}, + {0x0, 0x2, 0x47f}, + {0x0, 0x2, 0x481}, + {0x1, 0xe, 0x482}, + {0x0, 0x2, 0x491}, + {0x0, 0x2, 0x493}, + {0x0, 0x2, 0x495}, + {0x0, 0x2, 0x497}, + {0x0, 0x2, 0x499}, + {0x0, 0x2, 0x49b}, + {0x0, 0x2, 0x49d}, + {0x0, 0x2, 0x49f}, + {0x0, 0x2, 0x4a1}, + {0x0, 0x2, 0x4a3}, + {0x0, 0x2, 0x4a5}, + {0x0, 0x2, 0x4a7}, + {0x0, 0x2, 0x4a9}, + {0x0, 0x2, 0x4ab}, + {0x0, 0x2, 0x4ad}, + {0x0, 0x2, 0x4af}, + {0x0, 0x2, 0x4b1}, + {0x0, 0x2, 0x4b3}, + {0x0, 0x2, 0x4b5}, + {0x0, 0x2, 0x4b7}, + {0x0, 0x2, 0x4b9}, + {0x0, 0x2, 0x4bb}, + {0x0, 0x2, 0x4bd}, + {0x0, 0x2, 0x4bf}, + {0x1, 0x3, 0x4c0}, + {0x0, 0x2, 0x4c4}, + {0x1, 0x2, 0x4c5}, + {0x0, 0x2, 0x4c8}, + {0x1, 0x2, 0x4c9}, + {0x0, 0x2, 0x4cc}, + {0x1, 0x64, 0x4cd}, + {0x1, 0x26, 0x561}, + {0x1, 0xa9, 0x557}, + {0x1, 0xa0, 0x1000}, + {0x1, 0x26, 0x10d0}, + {0x1, 0x3a, 0x10c6}, + {0x1, 0xc, 0x2000}, + {0x0, 0x4, 0x0}, + {0x1, 0x1a, 0x2010}, + {0x0, 0x5, 0x0}, + {0x1, 0x3b, 0x202f}, + {0x0, 0x6, 0x0}, + {0x1, 0xf0, 0x2070}, + {0x1, 0x10, 0x2170}, + {0x1, 0x90, 0x2170}, + {0x1, 0xff, 0xfe00}, + {0x0, 0x1, 0x0}, + {0x1, 0x21, 0xff00}, + {0x1, 0x1a, 0xff41}, + {0x1, 0xc5, 0xff3b}, +}; +// Please update count if you add/remove entries but also please just let +// the compiler calculate it so you don't get it wrong. +//#define kLowerCaseTableNBlocks 182 +#define kLowerCaseTableNBlocks (sizeof(gLowerCaseTableCompressed)/sizeof(*gLowerCaseTableCompressed)) +// WARNING: The expanded size MUST be updated if you change the table and +// cannot be calculated at compile time. +#define kLowerCaseTableDataSize 5632 /* size of uncompressed structure in bytes */ + +unsigned short *gCompareTable; + +struct compressed_block gCompareTableCompressed[] = { + {0x2, 0x60, 0x0}, + {0x0, 0x1, 0x4180}, + {0x2, 0x1a, 0x4100}, + {0x2, 0x5, 0x7b00}, + {0x0, 0x1, 0x4108}, + {0x0, 0x1, 0x410c}, + {0x0, 0x1, 0x4310}, + {0x0, 0x1, 0x4502}, + {0x0, 0x1, 0x4e0a}, + {0x0, 0x1, 0x4f08}, + {0x0, 0x1, 0x5508}, + {0x0, 0x1, 0x4182}, + {0x0, 0x1, 0x4104}, + {0x0, 0x1, 0x4186}, + {0x0, 0x1, 0x4108}, + {0x0, 0x1, 0x410a}, + {0x0, 0x1, 0x410c}, + {0x0, 0x1, 0x4310}, + {0x0, 0x1, 0x4502}, + {0x0, 0x1, 0x4584}, + {0x0, 0x1, 0x4586}, + {0x0, 0x1, 0x4588}, + {0x0, 0x1, 0x4982}, + {0x0, 0x1, 0x4984}, + {0x0, 0x1, 0x4986}, + {0x0, 0x1, 0x4988}, + {0x0, 0x1, 0x4e0a}, + {0x0, 0x1, 0x4f82}, + {0x0, 0x1, 0x4f84}, + {0x0, 0x1, 0x4f86}, + {0x0, 0x1, 0x4f08}, + {0x0, 0x1, 0x4f0a}, + {0x0, 0x1, 0x5582}, + {0x0, 0x1, 0x5584}, + {0x0, 0x1, 0x5586}, + {0x0, 0x1, 0x5508}, + {0x2, 0x7, 0xa000}, + {0x0, 0x1, 0x5382}, + {0x2, 0x6, 0xa800}, + {0x0, 0x1, 0x4114}, + {0x0, 0x1, 0x4f0e}, + {0x2, 0xb, 0xb000}, + {0x0, 0x1, 0x4192}, + {0x0, 0x1, 0x4f92}, + {0x0, 0x1, 0xbd00}, + {0x0, 0x1, 0x4114}, + {0x0, 0x1, 0x4f0e}, + {0x2, 0x7, 0xc000}, + {0x0, 0x1, 0x2206}, + {0x0, 0x1, 0x2208}, + {0x0, 0x1, 0xc900}, + {0x0, 0x1, 0x2000}, + {0x0, 0x1, 0x4104}, + {0x0, 0x1, 0x410a}, + {0x0, 0x1, 0x4f0a}, + {0x0, 0x2, 0x4f14}, + {0x2, 0x2, 0xd000}, + {0x0, 0x1, 0x2202}, + {0x0, 0x1, 0x2204}, + {0x0, 0x1, 0x2702}, + {0x0, 0x1, 0x2704}, + {0x2, 0x2, 0xd600}, + {0x0, 0x1, 0x5988}, + {0x2, 0x27, 0xd900}, +}; +// Please update count if you add/remove entries but also please just let +// the compiler calculate it so you don't get it wrong. +//#define kCompareTableNBlocks 64 +#define kCompareTableNBlocks (sizeof(gCompareTableCompressed)/sizeof(*gCompareTableCompressed)) +// WARNING: The expanded size MUST be updated if you change the table and +// cannot be calculated at compile time. +#define kCompareTableDataSize 512 /* size of uncompressed structure in bytes */ + +#endif /* UNCOMPRESSED */ Index: branches/Chimera/i386/libsaio/.svn/text-base/ati.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ati.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ati.c.svn-base (revision 850) @@ -0,0 +1,1240 @@ +/* + * ATI Graphics Card Enabler, part of the Chameleon Boot Loader Project + * + * Copyright 2010 by Islam M. Ahmed Zaid. All rights reserved. + * + */ + + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "device_inject.h" + +#include "ati_reg.h" + +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x6e + +#define Reg32(reg) (*(volatile uint32_t *)(card->mmio + reg)) +#define RegRead32(reg) (Reg32(reg)) +#define RegWrite32(reg, value) (Reg32(reg) = value) + +typedef enum { + kNul, + kStr, + kPtr, + kCst +} type_t; + +typedef enum { + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_RS600, + CHIP_FAMILY_RS690, + CHIP_FAMILY_RS740, + /* R600 */ + CHIP_FAMILY_R600, + CHIP_FAMILY_RV610, + CHIP_FAMILY_RV630, + CHIP_FAMILY_RV670, + CHIP_FAMILY_RV620, + CHIP_FAMILY_RV635, + CHIP_FAMILY_RS780, + CHIP_FAMILY_RS880, + /* R700 */ + CHIP_FAMILY_RV770, + CHIP_FAMILY_RV730, + CHIP_FAMILY_RV710, + CHIP_FAMILY_RV740, + /* Evergreen */ + CHIP_FAMILY_CEDAR, + CHIP_FAMILY_REDWOOD, + CHIP_FAMILY_JUNIPER, + CHIP_FAMILY_CYPRESS, + CHIP_FAMILY_HEMLOCK, + /* Northern Islands */ + CHIP_FAMILY_BARTS, + CHIP_FAMILY_CAICOS, + CHIP_FAMILY_CAYMAN, + CHIP_FAMILY_TURKS, + CHIP_FAMILY_LAST +} chip_family_t; + +static const char *chip_family_name[] = { + "UNKNOW", + "RS600", + "RS690", + "RS740", + /* R600 */ + "R600", + "RV610", + "RV630", + "RV670", + "RV620", + "RV635", + "RS780", + "RS880", + /* R700 */ + "RV770", + "RV730", + "RV710", + "RV740", + /* Evergreen */ + "Cedar", // RV810 + "Redwood", // RV830 + "Juniper", // RV840 + "Cypress", // RV870 + "Hemlock", + /* Northern Islands */ + "Barts", + "Caicos", + "Cayman", + "Turks", + "" +}; + +typedef struct { + const char *name; + uint8_t ports; +} card_config_t; + +static card_config_t card_configs[] = { + {NULL, 0}, + {"Alopias", 2}, + {"Alouatta", 4}, + {"Baboon", 3}, + {"Cardinal", 2}, + {"Caretta", 1}, + {"Colobus", 2}, + {"Douc", 2}, + {"Eulemur", 3}, + {"Flicker", 3}, + {"Galago", 2}, + {"Gliff", 3}, + {"Hoolock", 3}, + {"Hypoprion", 2}, + {"Iago", 2}, + {"Kakapo", 3}, + {"Kipunji", 4}, + {"Lamna", 2}, + {"Langur", 3}, + {"Megalodon", 3}, + {"Motmot", 2}, + {"Nomascus", 5}, + {"Orangutan", 2}, + {"Peregrine", 2}, + {"Quail", 3}, + {"Raven", 3}, + {"Shrike", 3}, + {"Sphyrna", 1}, + {"Triakis", 2}, + {"Uakari", 4}, + {"Vervet", 4}, + {"Zonalis", 6}, + {"Pithecia", 3}, + {"Bulrushes", 6}, + {"Cattail", 4}, + {"Hydrilla", 5}, + {"Duckweed", 4}, + {"Fanwort", 4}, + {"Elodea", 5}, + {"Kudzu", 2}, + {"Gibba", 5}, + {"Lotus", 3}, + {"Ipomoea", 3}, + {"Mangabey", 2}, + {"Muskgrass", 4}, + {"Juncus", 4} +}; + +typedef enum { + kNull, + kAlopias, + kAlouatta, + kBaboon, + kCardinal, + kCaretta, + kColobus, + kDouc, + kEulemur, + kFlicker, + kGalago, + kGliff, + kHoolock, + kHypoprion, + kIago, + kKakapo, + kKipunji, + kLamna, + kLangur, + kMegalodon, + kMotmot, + kNomascus, + kOrangutan, + kPeregrine, + kQuail, + kRaven, + kShrike, + kSphyrna, + kTriakis, + kUakari, + kVervet, + kZonalis, + kPithecia, + kBulrushes, + kCattail, + kHydrilla, + kDuckweed, + kFanwort, + kElodea, + kKudzu, + kGibba, + kLotus, + kIpomoea, + kMangabey, + kMuskgrass, + kJuncus, + kCfgEnd +} config_name_t; + +typedef struct { + uint16_t device_id; + uint32_t subsys_id; + chip_family_t chip_family; + const char *model_name; + config_name_t cfg_name; +} radeon_card_info_t; + +static radeon_card_info_t radeon_cards[] = { + /* Earlier cards are not supported */ + { 0x9400, 0x30001002, CHIP_FAMILY_R600, "ATI Radeon HD 2900 PRO", kNull }, + { 0x9400, 0x25521002, CHIP_FAMILY_R600, "ATI Radeon HD 2900 XT", kNull }, + + { 0x9440, 0x24401682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, + { 0x9440, 0x24411682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, + { 0x9440, 0x24441682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, + { 0x9440, 0x24451682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870", kMotmot }, + + { 0x9441, 0x24401682, CHIP_FAMILY_RV770, "ATI Radeon HD 4870 X2", kMotmot }, + + { 0x9442, 0x24701682, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, + { 0x9442, 0x24711682, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, + { 0x9442, 0x080110B0, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, + { 0x9442, 0xE104174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4850", kMotmot }, + + { 0x944A, 0x30001682, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944A, 0x30001043, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944A, 0x30001458, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944A, 0x30001462, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944A, 0x30001545, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944A, 0x30001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944A, 0x3000174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944A, 0x300017AF, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + + { 0x944C, 0x24801682, CHIP_FAMILY_RV770, "ATI Radeon HD 4830", kMotmot }, + { 0x944C, 0x24811682, CHIP_FAMILY_RV770, "ATI Radeon HD 4830", kMotmot }, + + { 0x944E, 0x3260174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 Series", kMotmot }, + { 0x944E, 0x3261174B, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 series", kMotmot }, + { 0x944E, 0x30001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4730 Series", kMotmot }, + { 0x944E, 0x30101787, CHIP_FAMILY_RV770, "ATI Radeon HD 4810 Series", kMotmot }, + { 0x944E, 0x31001787, CHIP_FAMILY_RV770, "ATI Radeon HD 4820", kMotmot }, + + { 0x9490, 0x30501787, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull }, + { 0x9490, 0x4710174B, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull }, + { 0x9490, 0x300017AF, CHIP_FAMILY_RV730, "ATI Radeon HD 4710", kNull }, + + { 0x9498, 0x30501787, CHIP_FAMILY_RV730, "ATI Radeon HD 4700", kNull }, + { 0x9498, 0x31001787, CHIP_FAMILY_RV730, "ATI Radeon HD 4720", kNull }, + { 0x9498, 0x24511682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull }, + { 0x9498, 0x24521682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull }, + { 0x9498, 0x24541682, CHIP_FAMILY_RV730, "ATI Radeon HD 4650", kNull }, + { 0x9498, 0x29331682, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kNull }, + { 0x9498, 0x29341682, CHIP_FAMILY_RV730, "ATI Radeon HD 4670", kNull }, + { 0x9498, 0x21CF1458, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kNull }, + + { 0x94B3, 0x29001682, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, + { 0x94B3, 0x1170174B, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, + { 0x94B3, 0x10020D00, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, + + { 0x94C1, 0x10021002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Pro", kNull }, + { 0x94C1, 0x0D021002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, + { 0x94C1, 0x0D021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Pro", kNull }, + { 0x94C1, 0x0D021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, + { 0x94C1, 0x21741458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, + { 0x94C1, 0x10401462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, + { 0x94C1, 0x10331462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, + { 0x94C1, 0x10331462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, + { 0x94C1, 0x11101462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 XT", kNull }, + + { 0x94C3, 0x37161642, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x30001642, CHIP_FAMILY_RV610, "ATI Radeon HD 3410", kNull }, + { 0x94C3, 0x03421002, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x30001025, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, + { 0x94C3, 0x04021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, + { 0x94C3, 0x03021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x04021028, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x216A1458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x21721458, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x30001458, CHIP_FAMILY_RV610, "ATI Radeon HD 3410", kNull }, + { 0x94C3, 0x11041462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, + { 0x94C3, 0x10411462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, + { 0x94C3, 0x11051462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, + { 0x94C3, 0x10321462, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x30001462, CHIP_FAMILY_RV610, "ATI Radeon HD 3410", kNull }, + { 0x94C3, 0x3000148C, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, + { 0x94C3, 0x2247148C, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 LE", kNull }, + { 0x94C3, 0x3000174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, + { 0x94C3, 0xE400174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0xE370174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0xE400174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0xE370174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0xE400174B, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 PRO", kNull }, + { 0x94C3, 0x203817AF, CHIP_FAMILY_RV610, "ATI Radeon HD 2400", kNull }, + { 0x94C3, 0x30001787, CHIP_FAMILY_RV610, "ATI Radeon HD 2350 Series", kNull }, + { 0x94C3, 0x22471787, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 LE", kNull }, + { 0x94C3, 0x01011A93, CHIP_FAMILY_RV610, "Qimonda Radeon HD 2400 PRO", kNull }, + + + { 0x9501, 0x30001002, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, + { 0x9501, 0x25421002, CHIP_FAMILY_RV670, "ATI Radeon HD 3870", kNull }, + { 0x9501, 0x4750174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, + { 0x9501, 0x3000174B, CHIP_FAMILY_RV670, "Sapphire Radeon HD 3690", kNull }, + { 0x9501, 0x30001787, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, + + { 0x9505, 0x30001002, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, + { 0x9505, 0x25421002, CHIP_FAMILY_RV670, "ATI Radeon HD 3850", kNull }, + { 0x9505, 0x30011043, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, + { 0x9505, 0x3000148C, CHIP_FAMILY_RV670, "ATI Radeon HD 3850", kNull }, + { 0x9505, 0x3002148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, + { 0x9505, 0x3001148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, + { 0x9505, 0x3003148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, + { 0x9505, 0x3004148C, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, + { 0x9505, 0x4730174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4730", kNull }, + { 0x9505, 0x3010174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, + { 0x9505, 0x3001174B, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, + { 0x9505, 0x3000174B, CHIP_FAMILY_RV670, "Sapphire Radeon HD 3690", kNull }, + { 0x9505, 0x30001787, CHIP_FAMILY_RV670, "ATI Radeon HD 3690", kNull }, + { 0x9505, 0x301017AF, CHIP_FAMILY_RV670, "ATI Radeon HD 4750", kNull }, + + { 0x9540, 0x4590174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4590", kNull }, + { 0x9540, 0x30501787, CHIP_FAMILY_RV710, "ATI Radeon HD 4590", kNull }, + + { 0x954F, 0x29201682, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull }, + { 0x954F, 0x29211682, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull }, + { 0x954F, 0x30901682, CHIP_FAMILY_RV710, "XFX Radeon HD 4570", kNull }, + { 0x954F, 0x4450174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull }, + { 0x954F, 0x3000174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4520", kNull }, + { 0x954F, 0x30501787, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull }, + { 0x954F, 0x31001787, CHIP_FAMILY_RV710, "ATI Radeon HD 4520", kNull }, + { 0x954F, 0x4570174B, CHIP_FAMILY_RV710, "Sapphire Radeon HD4570", kNull }, + { 0x954F, 0x301017AF, CHIP_FAMILY_RV710, "ATI Radeon HD 4450", kNull }, + + { 0x9552, 0x3000148C, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, + { 0x9552, 0x3000174B, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, + { 0x9552, 0x30001787, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, + { 0x9552, 0x300017AF, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, + + { 0x9581, 0x95811002, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, + { 0x9581, 0x3000148C, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, + + { 0x9583, 0x3000148C, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, + { 0x9588, 0x01021A93, CHIP_FAMILY_RV630, "Qimonda Radeon HD 2600 XT", kNull }, + + { 0x9589, 0x30001462, CHIP_FAMILY_RV630, "ATI Radeon HD 3610", kNull }, + { 0x9589, 0x30001642, CHIP_FAMILY_RV630, "ATI Radeon HD 3610", kNull }, + { 0x9589, 0x0E41174B, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, + { 0x9589, 0x30001787, CHIP_FAMILY_RV630, "ATI Radeon HD 3600 Series", kNull }, + { 0x9589, 0x01001A93, CHIP_FAMILY_RV630, "Qimonda Radeon HD 2600 PRO", kNull }, + + { 0x9591, 0x2303148C, CHIP_FAMILY_RV635, "ATI Radeon HD 3600 Series", kNull }, + + { 0x9598, 0xB3831002, CHIP_FAMILY_RV635, "ATI All-in-Wonder HD", kNull }, + { 0x9598, 0x30011043, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, + { 0x9598, 0x30001043, CHIP_FAMILY_RV635, "HD3730", kNull }, + { 0x9598, 0x3000148C, CHIP_FAMILY_RV635, "ATI Radeon HD 3730", kNull }, + { 0x9598, 0x3031148C, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, + { 0x9598, 0x3001148C, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull }, + { 0x9598, 0x30011545, CHIP_FAMILY_RV635, "VisionTek Radeon HD 2600 Pro", kNull }, + { 0x9598, 0x30001545, CHIP_FAMILY_RV635, "VisionTek Radeon HD 2600 XT", kNull }, + { 0x9598, 0x4570174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, + { 0x9598, 0x4580174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull }, + { 0x9598, 0x4610174B, CHIP_FAMILY_RV635, "ATI Radeon HD 4610", kNull }, + { 0x9598, 0x3000174B, CHIP_FAMILY_RV635, "Sapphire Radeon HD 3730", kNull }, + { 0x9598, 0x3001174B, CHIP_FAMILY_RV635, "Sapphire Radeon HD 3750", kNull }, + { 0x9598, 0x301017AF, CHIP_FAMILY_RV635, "ATI Radeon HD 4570", kNull }, + { 0x9598, 0x301117AF, CHIP_FAMILY_RV635, "ATI Radeon HD 4580", kNull }, + { 0x9598, 0x300117AF, CHIP_FAMILY_RV635, "ATI Radeon HD3750", kNull }, + { 0x9598, 0x30501787, CHIP_FAMILY_RV635, "ATI Radeon HD 4610", kNull }, + + { 0x95C0, 0x3000148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull }, + { 0x95C0, 0xE3901745, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull }, + { 0x95C0, 0x3002174B, CHIP_FAMILY_RV620, "ATI Radeon HD 3570", kNull }, + { 0x95C0, 0x3020174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, + { 0x95C0, 0x3000174B, CHIP_FAMILY_RV620, "Sapphire Radeon HD 3550", kNull }, + + { 0x95C5, 0x3000148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3450", kNull }, + { 0x95C5, 0x3001148C, CHIP_FAMILY_RV620, "ATI Radeon HD 3550", kNull }, + { 0x95C5, 0x3002148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull }, + { 0x95C5, 0x3033148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull }, + { 0x95C5, 0x3003148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, + { 0x95C5, 0x3032148C, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, + { 0x95C5, 0x3010174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, + { 0x95C5, 0x4250174B, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, + { 0x95C5, 0x30501787, CHIP_FAMILY_RV620, "ATI Radeon HD 4250", kNull }, + { 0x95C5, 0x301017AF, CHIP_FAMILY_RV620, "ATI Radeon HD 4230", kNull }, + { 0x95C5, 0x01051A93, CHIP_FAMILY_RV620, "Qimonda Radeon HD 3450", kNull }, + { 0x95C5, 0x01041A93, CHIP_FAMILY_RV620, "Qimonda Radeon HD 3450", kNull }, + + /* Evergreen */ + { 0x6898, 0x032E1043, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari }, + { 0x6898, 0xE140174B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari }, + { 0x6898, 0x29611682, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kUakari }, + { 0x6898, 0x0B001002, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kZonalis }, + { 0x6898, 0x00D0106B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5870", kLangur }, + + { 0x6899, 0x21E41458, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, + { 0x6899, 0x200A1787, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, + { 0x6899, 0x22901787, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, + { 0x6899, 0xE140174B, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5850", kUakari }, + + { 0x689C, 0x03521043, CHIP_FAMILY_HEMLOCK, "ASUS ARES", kUakari }, + { 0x689C, 0x039E1043, CHIP_FAMILY_HEMLOCK, "ASUS EAH5870 Series", kUakari }, + { 0x689C, 0x30201682, CHIP_FAMILY_HEMLOCK, "ATI Radeon HD 5970", kUakari }, + + { 0x68B8, 0xE147174B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, + { 0x68B8, 0x21D71458, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, + { 0x68B8, 0x1482174B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, + { 0x68B8, 0x29901682, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, + { 0x68B8, 0x29911682, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, + { 0x68B8, 0x200B1787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, + { 0x68B8, 0x22881787, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kVervet }, + { 0x68B8, 0x00CF106B, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5770", kHoolock }, + + { 0x68D8, 0x301117AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5690", kNull }, + { 0x68D8, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull }, + { 0x68D8, 0x30001787, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull }, + { 0x68D8, 0x5690174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5690", kNull }, + { 0x68D8, 0x5730174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5730", kNull }, + { 0x68D8, 0x21D91458, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon }, + { 0x68D8, 0x03561043, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon }, + { 0x68D8, 0xE151174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5670", kBaboon }, + { 0x68D9, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, + { 0x68DA, 0x301017AF, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, + { 0x68DA, 0x30001787, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, + { 0x68DA, 0x5630174B, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5630", kNull }, + + { 0x68E0, 0x04561028, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470M", kEulemur }, + { 0x68E1, 0x1426103C, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5430M", kEulemur }, + { 0x68F9, 0x301317AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, + { 0x68F9, 0x301117AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, + { 0x68F9, 0x301217AF, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull }, + { 0x68F9, 0x30001787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, + { 0x68F9, 0x30021787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull }, + { 0x68F9, 0x30011787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5530", kNull }, + { 0x68F9, 0x5470174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5470", kNull }, + { 0x68F9, 0x5490174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5490", kNull }, + { 0x68F9, 0x5530174B, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5530", kNull }, + + /* Northen Islands */ + { 0x6718, 0x0B001002, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull }, + { 0x6718, 0x31301682, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull }, + { 0x6718, 0x67181002, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6970", kNull }, + + { 0x6738, 0x67381002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6870", kDuckweed }, + { 0x6739, 0x67391002, CHIP_FAMILY_BARTS, "AMD Radeon HD 6850", kDuckweed }, + + { 0x6759, 0xE193174B, CHIP_FAMILY_TURKS, "AMD Radeon HD 6570", kNull }, + + /* standard/default models */ + { 0x9400, 0x00000000, CHIP_FAMILY_R600, "ATI Radeon HD 2900 XT", kNull }, + { 0x9405, 0x00000000, CHIP_FAMILY_R600, "ATI Radeon HD 2900 GT", kNull }, + { 0x9440, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x9441, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4870 X2", kMotmot }, + { 0x9442, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x9443, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4850 X2", kMotmot }, + { 0x944C, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x944E, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4700 Series", kMotmot }, + { 0x944E, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4700 Series", kMotmot }, + { 0x9450, 0x00000000, CHIP_FAMILY_RV770, "AMD FireStream 9270", kMotmot }, + { 0x9452, 0x00000000, CHIP_FAMILY_RV770, "AMD FireStream 9250", kMotmot }, + { 0x9460, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x9462, 0x00000000, CHIP_FAMILY_RV770, "ATI Radeon HD 4800 Series", kMotmot }, + { 0x9490, 0x00000000, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kFlicker }, + { 0x9498, 0x00000000, CHIP_FAMILY_RV730, "ATI Radeon HD 4600 Series", kFlicker }, + { 0x94B3, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, + { 0x94B4, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4700 Series", kFlicker }, + { 0x94B5, 0x00000000, CHIP_FAMILY_RV740, "ATI Radeon HD 4770", kFlicker }, + { 0x94C1, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago }, + { 0x94C3, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago }, + { 0x94C7, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2350", kIago }, + { 0x94CC, 0x00000000, CHIP_FAMILY_RV610, "ATI Radeon HD 2400 Series", kIago }, + + { 0x9501, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3800 Series", kMegalodon }, + { 0x9505, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3800 Series", kMegalodon }, + { 0x9507, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3830", kMegalodon }, + { 0x950F, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3870 X2", kMegalodon }, + { 0x9513, 0x00000000, CHIP_FAMILY_RV670, "ATI Radeon HD 3850 X2", kMegalodon }, + { 0x9519, 0x00000000, CHIP_FAMILY_RV670, "AMD FireStream 9170", kMegalodon }, + { 0x9540, 0x00000000, CHIP_FAMILY_RV710, "ATI Radeon HD 4550", kNull }, + { 0x954F, 0x00000000, CHIP_FAMILY_RV710, "ATI Radeon HD 4300/4500 Series", kNull }, + { 0x9588, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 XT", kLamna }, + { 0x9589, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 PRO", kLamna }, + { 0x958A, 0x00000000, CHIP_FAMILY_RV630, "ATI Radeon HD 2600 X2 Series", kLamna }, + { 0x9598, 0x00000000, CHIP_FAMILY_RV635, "ATI Radeon HD 3600 Series", kMegalodon }, + { 0x95C0, 0x00000000, CHIP_FAMILY_RV620, "ATI Radeon HD 3400 Series", kIago }, + { 0x95C5, 0x00000000, CHIP_FAMILY_RV620, "ATI Radeon HD 3400 Series", kIago }, + + { 0x9610, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon HD 3200 Graphics", kNull }, + { 0x9611, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon 3100 Graphics", kNull }, + { 0x9614, 0x00000000, CHIP_FAMILY_RS780, "ATI Radeon HD 3300 Graphics", kNull }, + { 0x9616, 0x00000000, CHIP_FAMILY_RS780, "AMD 760G", kNull }, + + { 0x9710, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4200", kNull }, + { 0x9715, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4250", kNull }, + { 0x9714, 0x00000000, CHIP_FAMILY_RS880, "ATI Radeon HD 4290", kNull }, + + + /* Evergreen */ + { 0x688D, 0x00000000, CHIP_FAMILY_CYPRESS, "AMD FireStream 9350", kUakari }, + + { 0x6898, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari }, + { 0x6899, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari }, + { 0x689E, 0x00000000, CHIP_FAMILY_CYPRESS, "ATI Radeon HD 5800 Series", kUakari }, + { 0x689C, 0x00000000, CHIP_FAMILY_HEMLOCK, "ATI Radeon HD 5900 Series", kUakari }, + + { 0x68B9, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5600 Series", kVervet }, + { 0x68B8, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5700 Series", kVervet }, + { 0x68BE, 0x00000000, CHIP_FAMILY_JUNIPER, "ATI Radeon HD 5700 Series", kVervet }, + + { 0x68D8, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5600 Series", kBaboon }, + { 0x68D9, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5500 Series", kBaboon }, + { 0x68DA, 0x00000000, CHIP_FAMILY_REDWOOD, "ATI Radeon HD 5500 Series", kBaboon }, + + { 0x68F9, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5400 Series", kNull }, + + { 0x6718, 0x00000000, CHIP_FAMILY_CAYMAN, "AMD Radeon HD 6900 Series", kNull }, + + /* Northen Islands */ + { 0x6758, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6670", kNull }, + { 0x6759, 0x00000000, CHIP_FAMILY_TURKS, "AMD Radeon HD 6500 Series", kNull }, + + { 0x6770, 0x00000000, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6400 Series", kNull }, + { 0x6779, 0x00000000, CHIP_FAMILY_CAICOS, "AMD Radeon HD 6450 Series", kNull }, + + { 0x68F9, 0x00000000, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5400 Series", kNull }, + + { 0x0000, 0x00000000, CHIP_FAMILY_UNKNOW, NULL, kNull } +}; + + +typedef struct { + struct DevPropDevice *device; + radeon_card_info_t *info; + pci_dt_t *pci_dev; + uint8_t *fb; + uint8_t *mmio; + uint8_t *io; + uint8_t *rom; + uint32_t rom_size; + uint32_t vram_size; + uint8_t ports; + uint32_t flags; + bool posted; +} card_t; +card_t *card; + +/* Flags */ +#define MKFLAG(n) (1 << n) +#define FLAGTRUE MKFLAG(0) +#define EVERGREEN MKFLAG(1) + +static uint8_t atN = 0; + +typedef struct { + type_t type; + uint32_t size; + uint8_t *data; +} value_t; + +static value_t aty_name; +static value_t aty_nameparent; +//static value_t aty_model; + +#define DATVAL(x) {kPtr, sizeof(x), (uint8_t *)x} +#define STRVAL(x) {kStr, sizeof(x), (uint8_t *)x} +#define BYTVAL(x) {kCst, 1, (uint8_t *)x} +#define WRDVAL(x) {kCst, 2, (uint8_t *)x} +#define DWRVAL(x) {kCst, 4, (uint8_t *)x} +#define QWRVAL(x) {kCst, 8, (uint8_t *)x} +#define NULVAL {kNul, 0, (uint8_t *)NULL} + +bool get_bootdisplay_val(value_t *val); +bool get_vrammemory_val(value_t *val); +bool get_name_val(value_t *val); +bool get_nameparent_val(value_t *val); +bool get_model_val(value_t *val); +bool get_conntype_val(value_t *val); +bool get_vrammemsize_val(value_t *val); +bool get_binimage_val(value_t *val); +bool get_romrevision_val(value_t *val); +bool get_deviceid_val(value_t *val); +bool get_mclk_val(value_t *val); +bool get_sclk_val(value_t *val); +bool get_refclk_val(value_t *val); +bool get_platforminfo_val(value_t *val); +bool get_vramtotalsize_val(value_t *val); + +typedef struct { + uint32_t flags; + bool all_ports; + char *name; + bool (*get_value)(value_t *val); + value_t default_val; +} dev_prop_t; + +dev_prop_t ati_devprop_list[] = { + {FLAGTRUE, false, "@0,AAPL,boot-display", get_bootdisplay_val, NULVAL }, +// {FLAGTRUE, false, "@0,ATY,EFIDisplay", NULL, STRVAL("TMDSA") }, + +// {FLAGTRUE, true, "@0,AAPL,vram-memory", get_vrammemory_val, NULVAL }, +// {FLAGTRUE, true, "@0,compatible", get_name_val, NULVAL }, +// {FLAGTRUE, true, "@0,connector-type", get_conntype_val, NULVAL }, +// {FLAGTRUE, true, "@0,device_type", NULL, STRVAL("display") }, +// {FLAGTRUE, false, "@0,display-connect-flags", NULL, DWRVAL((uint32_t)0) }, +// {FLAGTRUE, true, "@0,display-type", NULL, STRVAL("NONE") }, + {FLAGTRUE, true, "@0,name", get_name_val, NULVAL }, +// {FLAGTRUE, true, "@0,VRAM,memsize", get_vrammemsize_val, NULVAL }, + +// {FLAGTRUE, false, "AAPL,aux-power-connected", NULL, DWRVAL((uint32_t)1) }, +// {FLAGTRUE, false, "AAPL,backlight-control", NULL, DWRVAL((uint32_t)0) }, + {FLAGTRUE, false, "ATY,bin_image", get_binimage_val, NULVAL }, + {FLAGTRUE, false, "ATY,Copyright", NULL, STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010") }, + {FLAGTRUE, false, "ATY,Card#", get_romrevision_val, NULVAL }, + {FLAGTRUE, false, "ATY,VendorID", NULL, WRDVAL((uint16_t)0x1002) }, + {FLAGTRUE, false, "ATY,DeviceID", get_deviceid_val, NULVAL }, + +// {FLAGTRUE, false, "ATY,MCLK", get_mclk_val, NULVAL }, +// {FLAGTRUE, false, "ATY,SCLK", get_sclk_val, NULVAL }, +// {FLAGTRUE, false, "ATY,RefCLK", get_refclk_val, DWRVAL((uint32_t)0x0a8c) }, + +// {FLAGTRUE, false, "ATY,PlatformInfo", get_platforminfo_val, NULVAL }, + + {FLAGTRUE, false, "name", get_nameparent_val, NULVAL }, + {FLAGTRUE, false, "device_type", get_nameparent_val, NULVAL }, + {FLAGTRUE, false, "model", get_model_val, STRVAL("ATI Radeon") }, +// {FLAGTRUE, false, "VRAM,totalsize", get_vramtotalsize_val, NULVAL }, + + {FLAGTRUE, false, NULL, NULL, NULVAL } +}; + +bool get_bootdisplay_val(value_t *val) +{ + static uint32_t v = 0; + + if (v) + return false; + + if (!card->posted) + return false; + + v = 1; + val->type = kCst; + val->size = 4; + val->data = (uint8_t *)&v; + + return true; +} + +bool get_vrammemory_val(value_t *val) +{ + return false; +} + +bool get_name_val(value_t *val) +{ + val->type = aty_name.type; + val->size = aty_name.size; + val->data = aty_name.data; + + return true; +} + +bool get_nameparent_val(value_t *val) +{ + val->type = aty_nameparent.type; + val->size = aty_nameparent.size; + val->data = aty_nameparent.data; + + return true; +} + +bool get_model_val(value_t *val) +{ + if (!card->info->model_name) + return false; + + val->type = kStr; + val->size = strlen(card->info->model_name) + 1; + val->data = (uint8_t *)card->info->model_name; + + return true; +} + +bool get_conntype_val(value_t *val) +{ +/* +Connector types: +0x4 : DisplayPort +0x400: DL DVI-I +0x800: HDMI +*/ + return false; +} + +bool get_vrammemsize_val(value_t *val) +{ + static int idx = -1; + static uint64_t memsize; + + idx++; + memsize = ((uint64_t)card->vram_size << 32); + if (idx == 0) + memsize = memsize | (uint64_t)card->vram_size; + + val->type = kCst; + val->size = 8; + val->data = (uint8_t *)&memsize; + + return true; +} + +bool get_binimage_val(value_t *val) +{ + if (!card->rom) + return false; + + val->type = kPtr; + val->size = card->rom_size; + val->data = card->rom; + + return true; +} + +bool get_romrevision_val(value_t *val) +{ + uint8_t *rev; + if (!card->rom) + return false; + + rev = card->rom + *(uint8_t *)(card->rom + OFFSET_TO_GET_ATOMBIOS_STRINGS_START); + + val->type = kPtr; + val->size = strlen((char *)rev); + val->data = malloc(val->size); + + if (!val->data) + return false; + + memcpy(val->data, rev, val->size); + + return true; +} + +bool get_deviceid_val(value_t *val) +{ + val->type = kCst; + val->size = 2; + val->data = (uint8_t *)&card->pci_dev->device_id; + + return true; +} + +bool get_mclk_val(value_t *val) +{ + return false; +} + +bool get_sclk_val(value_t *val) +{ + return false; +} + +bool get_refclk_val(value_t *val) +{ + return false; +} + +bool get_platforminfo_val(value_t *val) +{ + val->data = malloc(0x80); + if (!val->data) + return false; + + bzero(val->data, 0x80); + + val->type = kPtr; + val->size = 0x80; + val->data[0] = 1; + + return true; +} + +bool get_vramtotalsize_val(value_t *val) +{ + val->type = kCst; + val->size = 4; + val->data = (uint8_t *)&card->vram_size; + + return true; +} + +void free_val(value_t *val) +{ + if (val->type == kPtr) + free(val->data); + bzero(val, sizeof(value_t)); +} + +void devprop_add_list(dev_prop_t devprop_list[]) +{ + value_t *val = malloc(sizeof(value_t)); + int i, pnum; + for (i = 0; devprop_list[i].name != NULL; i++) + if ((devprop_list[i].flags == FLAGTRUE) || (devprop_list[i].flags | card->flags)) + if (devprop_list[i].get_value && devprop_list[i].get_value(val)) + { + devprop_add_value(card->device, devprop_list[i].name, val->data, val->size); + free_val(val); + if (devprop_list[i].all_ports) + { + for (pnum = 1; pnum < card->ports; pnum++) + { + if (devprop_list[i].get_value(val)) + { + devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii + devprop_add_value(card->device, devprop_list[i].name, val->data, val->size); + free_val(val); + } + } + devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card + } + } + else + { + if (devprop_list[i].default_val.type != kNul) + devprop_add_value(card->device, devprop_list[i].name, + devprop_list[i].default_val.type == kCst ? + (uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, + devprop_list[i].default_val.size); + + if (devprop_list[i].all_ports) + { + for (pnum = 1; pnum < card->ports; pnum++) + { + if (devprop_list[i].default_val.type != kNul) + { + devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii + devprop_add_value(card->device, devprop_list[i].name, + devprop_list[i].default_val.type == kCst ? + (uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, + devprop_list[i].default_val.size); + } + } + devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card + } + } + + free(val); +} + + +bool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev) +{ + option_rom_pci_header_t *rom_pci_header; + + if (rom_header->signature != 0xaa55) + return false; + + rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset); + + if (rom_pci_header->signature != 0x52494350) + return false; + + if (rom_pci_header->vendor_id != pci_dev->vendor_id || rom_pci_header->device_id != pci_dev->device_id) + return false; + + return true; +} + +bool load_vbios_file(const char *key, uint16_t vendor_id, uint16_t device_id, uint32_t subsys_id) +{ + int fd; + char file_name[24]; + bool do_load = false; + + getBoolForKey(key, &do_load, &bootInfo->bootConfig); + if (!do_load) + return false; + + sprintf(file_name, "/Extra/%04x_%04x_%08x.rom", vendor_id, device_id, subsys_id); + if ((fd = open_bvdev("bt(0,0)", file_name, 0)) < 0) + return false; + + card->rom_size = file_size(fd); + card->rom = malloc(card->rom_size); + if (!card->rom) + return false; + + read(fd, (char *)card->rom, card->rom_size); + + if (!validate_rom((option_rom_header_t *)card->rom, card->pci_dev)) + { + card->rom_size = 0; + card->rom = 0; + return false; + } + + card->rom_size = ((option_rom_header_t *)card->rom)->rom_size * 512; + + close(fd); + + return true; +} + +void get_vram_size(void) +{ + chip_family_t chip_family = card->info->chip_family; + + card->vram_size = 0; + + if (chip_family >= CHIP_FAMILY_CEDAR) + /* size in MB on evergreen */ + /* XXX watch for overflow!!! */ + card->vram_size = RegRead32(R600_CONFIG_MEMSIZE) * 1024 * 1024; + else + if (chip_family >= CHIP_FAMILY_R600) + card->vram_size = RegRead32(R600_CONFIG_MEMSIZE); +} + +bool read_vbios(bool from_pci) +{ + option_rom_header_t *rom_addr; + + if (from_pci) + { + rom_addr = (option_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff); + verbose(" @0x%x", rom_addr); + } + else + rom_addr = (option_rom_header_t *)0xc0000; + + if (!validate_rom(rom_addr, card->pci_dev)) + return false; + + card->rom_size = rom_addr->rom_size * 512; + if (!card->rom_size) + return false; + + card->rom = malloc(card->rom_size); + if (!card->rom) + return false; + + memcpy(card->rom, (void *)rom_addr, card->rom_size); + + return true; +} + +bool read_disabled_vbios(void) +{ + bool ret = false; + chip_family_t chip_family = card->info->chip_family; + + if (chip_family >= CHIP_FAMILY_RV770) + { + uint32_t viph_control = RegRead32(RADEON_VIPH_CONTROL); + uint32_t bus_cntl = RegRead32(RADEON_BUS_CNTL); + uint32_t d1vga_control = RegRead32(AVIVO_D1VGA_CONTROL); + uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL); + uint32_t vga_render_control = RegRead32(AVIVO_VGA_RENDER_CONTROL); + uint32_t rom_cntl = RegRead32(R600_ROM_CNTL); + uint32_t cg_spll_func_cntl = 0; + uint32_t cg_spll_status; + + /* disable VIP */ + RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); + + /* enable the rom */ + RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); + + /* Disable VGA mode */ + RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + + if (chip_family == CHIP_FAMILY_RV730) + { + cg_spll_func_cntl = RegRead32(R600_CG_SPLL_FUNC_CNTL); + + /* enable bypass mode */ + RegWrite32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN)); + + /* wait for SPLL_CHG_STATUS to change to 1 */ + cg_spll_status = 0; + while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) + cg_spll_status = RegRead32(R600_CG_SPLL_STATUS); + + RegWrite32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); + } + else + RegWrite32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); + + ret = read_vbios(true); + + /* restore regs */ + if (chip_family == CHIP_FAMILY_RV730) + { + RegWrite32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); + + /* wait for SPLL_CHG_STATUS to change to 1 */ + cg_spll_status = 0; + while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) + cg_spll_status = RegRead32(R600_CG_SPLL_STATUS); + } + RegWrite32(RADEON_VIPH_CONTROL, viph_control); + RegWrite32(RADEON_BUS_CNTL, bus_cntl); + RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control); + RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + RegWrite32(R600_ROM_CNTL, rom_cntl); + } + else + if (chip_family >= CHIP_FAMILY_R600) + { + uint32_t viph_control = RegRead32(RADEON_VIPH_CONTROL); + uint32_t bus_cntl = RegRead32(RADEON_BUS_CNTL); + uint32_t d1vga_control = RegRead32(AVIVO_D1VGA_CONTROL); + uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL); + uint32_t vga_render_control = RegRead32(AVIVO_VGA_RENDER_CONTROL); + uint32_t rom_cntl = RegRead32(R600_ROM_CNTL); + uint32_t general_pwrmgt = RegRead32(R600_GENERAL_PWRMGT); + uint32_t low_vid_lower_gpio_cntl = RegRead32(R600_LOW_VID_LOWER_GPIO_CNTL); + uint32_t medium_vid_lower_gpio_cntl = RegRead32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); + uint32_t high_vid_lower_gpio_cntl = RegRead32(R600_HIGH_VID_LOWER_GPIO_CNTL); + uint32_t ctxsw_vid_lower_gpio_cntl = RegRead32(R600_CTXSW_VID_LOWER_GPIO_CNTL); + uint32_t lower_gpio_enable = RegRead32(R600_LOWER_GPIO_ENABLE); + + /* disable VIP */ + RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); + + /* enable the rom */ + RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); + + /* Disable VGA mode */ + RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT))); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); + RegWrite32(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | R600_SCK_OVERWRITE)); + RegWrite32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); + RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); + RegWrite32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); + + ret = read_vbios(true); + + /* restore regs */ + RegWrite32(RADEON_VIPH_CONTROL, viph_control); + RegWrite32(RADEON_BUS_CNTL, bus_cntl); + RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control); + RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control); + RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); + RegWrite32(R600_ROM_CNTL, rom_cntl); + RegWrite32(R600_GENERAL_PWRMGT, general_pwrmgt); + RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); + RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); + RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); + RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); + RegWrite32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); + + } + + return ret; +} + +bool radeon_card_posted(void) +{ + uint32_t reg; + + /* first check CRTCs */ + reg = RegRead32(RADEON_CRTC_GEN_CNTL) | RegRead32(RADEON_CRTC2_GEN_CNTL); + if (reg & RADEON_CRTC_EN) + return true; + + /* then check MEM_SIZE, in case something turned the crtcs off */ + reg = RegRead32(R600_CONFIG_MEMSIZE); + if (reg) + return true; + + return false; +} +#if 0 +bool devprop_add_pci_config_space(void) +{ + int offset; + + uint8_t *config_space = malloc(0x100); + if (!config_space) + return false; + + for (offset = 0; offset < 0x100; offset += 4) + config_space[offset / 4] = pci_config_read32(card->pci_dev->dev.addr, offset); + + devprop_add_value(card->device, "ATY,PCIConfigSpace", config_space, 0x100); + free(config_space); + return true; +} +#endif + +static bool init_card(pci_dt_t *pci_dev) +{ + const char *fb_name; + char name[24]; + char name_parent[24]; + int i; + bool add_vbios = true; + + card = malloc(sizeof(card_t)); + if (!card) + return false; + bzero(card, sizeof(card_t)); + + card->pci_dev = pci_dev; + + for (i = 0; radeon_cards[i].device_id ; i++) + if (radeon_cards[i].device_id == pci_dev->device_id) + { + card->info = &radeon_cards[i]; + if ((radeon_cards[i].subsys_id == 0x00000000) || + (radeon_cards[i].subsys_id == pci_dev->subsys_id.subsys_id)) + break; + } + + if (!card->info->device_id || !card->info->cfg_name) + { + printf("Unsupported card!\n"); + return false; + } + + + card->fb = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_0) & ~0x0f); + card->mmio = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f); + card->io = (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03); + + verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n", + card->fb, card->mmio, card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS)); + + card->posted = radeon_card_posted(); + verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed"); + + get_vram_size(); + + getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->bootConfig); + + if (add_vbios) + if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id)) + { + verbose("reading VBIOS from %s", card->posted ? "legacy space" : "PCI ROM"); + if (card->posted) + read_vbios(false); + else + read_disabled_vbios(); + verbose("\n"); + } + + card->ports = 2; // default + + if (card->info->chip_family >= CHIP_FAMILY_CEDAR) + { + card->flags |= EVERGREEN; + card->ports = 3; + } + + atN = 0; + + fb_name = getStringForKey(kAtiConfig, &bootInfo->bootConfig); + if (!fb_name) + { + fb_name = card_configs[card->info->cfg_name].name; + card->ports = card_configs[card->info->cfg_name].ports; + } + else + { + for (i = 0; i < kCfgEnd; i++) + if (strcmp(fb_name, card_configs[i].name) == 0) + card->ports = card_configs[i].ports; + } + + sprintf(name, "ATY,%s", fb_name); + aty_name.type = kStr; + aty_name.size = strlen(name) + 1; + aty_name.data = (uint8_t *)name; + + sprintf(name_parent, "ATY,%sParent", fb_name); + aty_nameparent.type = kStr; + aty_nameparent.size = strlen(name_parent) + 1; + aty_nameparent.data = (uint8_t *)name_parent; + + return true; +} + +bool setup_ati_devprop(pci_dt_t *ati_dev) +{ + char *devicepath; + + if (!init_card(ati_dev)) + return false; + + /* ------------------------------------------------- */ + /* Find a better way to do this (in device_inject.c) */ + if (!string) + string = devprop_create_string(); + + devicepath = get_pci_dev_path(ati_dev); + card->device = devprop_add_device(string, devicepath); + if (!card->device) + return false; + /* ------------------------------------------------- */ + +#if 0 + uint64_t fb = (uint32_t)card->fb; + uint64_t mmio = (uint32_t)card->mmio; + uint64_t io = (uint32_t)card->io; + devprop_add_value(card->device, "ATY,FrameBufferOffset", &fb, 8); + devprop_add_value(card->device, "ATY,RegisterSpaceOffset", &mmio, 8); + devprop_add_value(card->device, "ATY,IOSpaceOffset", &io, 8); +#endif + + devprop_add_list(ati_devprop_list); + + /* ------------------------------------------------- */ + /* Find a better way to do this (in device_inject.c) */ + stringdata = malloc(string->length); + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + /* ------------------------------------------------- */ + + verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n", + chip_family_name[card->info->chip_family], card->info->model_name, + (uint32_t)(card->vram_size / (1024 * 1024)), card_configs[card->info->cfg_name].name, + ati_dev->vendor_id, ati_dev->device_id, + ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id, + devicepath); + + free(card); + + return true; +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/pci_root.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/pci_root.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/pci_root.c.svn-base (revision 850) @@ -0,0 +1,113 @@ +/* + * Copyright 2009 netkas + */ + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" + +#ifndef DEBUG_PCIROOT +#define DEBUG_PCIROOT 1 +#endif + +#if DEBUG_PCIROOT +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +static int rootuid = 10; //value means function wasnt ran yet + +static unsigned int findrootuid(unsigned char * dsdt, int len) +{ + int i; + for (i=0; i<64 && ibootConfig)) { + if (isdigit(val[0])) rootuid = val[0] - '0'; + goto out; + } + /* Chameleon compatibility */ + else if (getValueForKey("PciRoot", &val, &len, &bootInfo->bootConfig)) { + if (isdigit(val[0])) rootuid = val[0] - '0'; + goto out; + } + /* PCEFI compatibility */ + else if (getValueForKey("-pci0", &val, &len, &bootInfo->bootConfig)) { + rootuid = 0; + goto out; + } + else if (getValueForKey("-pci1", &val, &len, &bootInfo->bootConfig)) { + rootuid = 1; + goto out; + } + + int fd = search_and_get_acpi_fd("DSDT.aml", &dsdt_filename); + + // Check booting partition + if (fd<0) + { + verbose("No DSDT found, using 0 as uid value.\n"); + rootuid = 0; + goto out; + } + + fsize = file_size(fd); + + if ((new_dsdt = malloc(fsize)) == NULL) { + verbose("[ERROR] alloc DSDT memory failed\n"); + close (fd); + goto out; + } + if (read (fd, new_dsdt, fsize) != fsize) { + verbose("[ERROR] read %s failed\n", dsdt_filename); + close (fd); + goto out; + } + close (fd); + + rootuid = findpciroot(new_dsdt, fsize); + free(new_dsdt); + + // make sure it really works: + if (rootuid == 11) rootuid=0; //usually when _UID isnt present, it means uid is zero + else if (rootuid < 0 || rootuid > 9) + { + printf("PciRoot uid value wasnt found, using 0, if you want it to be 1, use -PciRootUID flag"); + rootuid = 0; + } +out: + verbose("Using PCI-Root-UID value: %d\n", rootuid); + return rootuid; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/convert.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/convert.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/convert.c.svn-base (revision 850) @@ -0,0 +1,153 @@ +/* + * Convert.c + * Implement conversion utility functions + * Create UUID parsing functions and gather other conversion routines + * --Rek + */ + +#include "convert.h" + +/** Transform a 16 bytes hexadecimal value UUID to a string */ +const char * getStringFromUUID(const EFI_CHAR8* eUUID) +{ + static char msg[UUID_LEN*2 + 8] = ""; + if (!eUUID) return ""; + const unsigned char * uuid = (unsigned char*) eUUID; + sprintf(msg, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x", + uuid[0], uuid[1], uuid[2], uuid[3], + uuid[4], uuid[5], uuid[6], uuid[7], + uuid[8], uuid[9], uuid[10],uuid[11], + uuid[12],uuid[13],uuid[14],uuid[15]); + return msg ; +} + +/** Parse an UUID string into an (EFI_CHAR8*) buffer */ +EFI_CHAR8* getUUIDFromString(const char *source) +{ + if (!source) return 0; + + char *p = (char *)source; + int i; + char buf[3]; + static EFI_CHAR8 uuid[UUID_LEN+1]=""; + + buf[2] = '\0'; + for (i=0; i= 48 && buff[i] <= 57) // '0' through '9' + digit = buff[i] - 48; + else if (buff[i] >= 65 && buff[i] <= 70) // 'A' through 'F' + digit = buff[i] - 55; + else if (buff[i] >= 97 && buff[i] <= 102) // 'a' through 'f' + digit = buff[i] - 87; + else + return value; + + value = digit + 16 * value; + } + return value; +} + +void *convertHexStr2Binary(const char *hexStr, int *outLength) +{ + int len; + char hexNibble; + char hexByte[2]; + uint8_t binChar; + uint8_t *binStr; + int hexStrIdx, binStrIdx, hexNibbleIdx; + + len = strlen(hexStr); + if (len > 1) + { + // the resulting binary will be the half size of the input hex string + binStr = malloc(len / 2); + binStrIdx = 0; + hexNibbleIdx = 0; + for (hexStrIdx = 0; hexStrIdx < len; hexStrIdx++) + { + hexNibble = hexStr[hexStrIdx]; + + // ignore all chars except valid hex numbers + if (hexNibble >= '0' && hexNibble <= '9' + || hexNibble >= 'A' && hexNibble <= 'F' + || hexNibble >= 'a' && hexNibble <= 'f') + { + hexByte[hexNibbleIdx++] = hexNibble; + + // found both two nibbles, convert to binary + if (hexNibbleIdx == 2) + { + binChar = 0; + + for (hexNibbleIdx = 0; hexNibbleIdx < sizeof(hexByte); hexNibbleIdx++) + { + if (hexNibbleIdx > 0) binChar = binChar << 4; + + if (hexByte[hexNibbleIdx] <= '9') binChar += hexByte[hexNibbleIdx] - '0'; + else if (hexByte[hexNibbleIdx] <= 'F') binChar += hexByte[hexNibbleIdx] - ('A' - 10); + else if (hexByte[hexNibbleIdx] <= 'f') binChar += hexByte[hexNibbleIdx] - ('a' - 10); + } + + binStr[binStrIdx++] = binChar; + hexNibbleIdx = 0; + } + } + } + *outLength = binStrIdx; + return binStr; + } + else + { + *outLength = 0; + return NULL; + } +} + +// FIXME: can't use my original code here, +// Ironically, trying to reuse convertHexStr2Binary() would RESET the system! +/* +static EFI_CHAR8* getUUIDFromString2(const char * szInUUID) +{ + char szUUID[UUID_LEN+1], *p=szUUID; + int size=0; + void* ret; + + if (!szInUUID || strlen(szInUUID) to valid UUID.\n", szUUID); + return (EFI_CHAR8*) 0; + } + return (EFI_CHAR8*) ret; // new allocated buffer containing the converted string to bin +} +*/ Index: branches/Chimera/i386/libsaio/.svn/text-base/biosfn.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/biosfn.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/biosfn.c.svn-base (revision 850) @@ -0,0 +1,956 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright 1993 NeXT Computer, Inc. + * All rights reserved. + */ + +/* Copyright 2007 David Elliott + 2007-12-30 dfe + - Enhanced code to normalize segment/offset to huge pointers so that any + linear address within the first MB of memory can be passed to BIOS + functions. This allows some of the __DATA sections to span into the + next segment and also allows stack variables to be used whereas the + old code could only operate on static data in the first 64k. + NOTE: Requires bios.s change to respect DS. + */ +/* Copyright 2007 VMware Inc. + 2007-12-29 dfe + - Added ebiosEjectMedia + */ +#include "bootstruct.h" +#include "libsaio.h" + +#define MAX_DRIVES 8 + +static biosBuf_t bb; + +int bgetc(void) +{ + /* Poll for the next character. Most real BIOS do not need this as the + INT 16h,AH=0h function will block until one is received. + Unfortunately, Apple's EFI CSM will never wake up. This idea is lifted + from the grub-a20.patch to GRUB's stage2/asm.S file. + */ + while(!readKeyboardStatus()) + ; + bb.intno = 0x16; + bb.eax.r.h = 0x00; + bios(&bb); + return bb.eax.rr; +} + +int readKeyboardStatus(void) +{ + bb.intno = 0x16; + bb.eax.r.h = 0x01; + bios(&bb); + if (bb.flags.zf) { + return 0; + } else { + return bb.eax.rr; + } +} + +int readKeyboardShiftFlags(void) +{ + bb.intno = 0x16; + bb.eax.r.h = 0x02; + bios(&bb); + return bb.eax.r.l; +} + +unsigned int time18(void) +{ + union { + struct { + unsigned int low:16; + unsigned int high:16; + } s; + unsigned int i; + } time; + + bb.intno = 0x1a; + bb.eax.r.h = 0x00; + bios(&bb); + time.s.low = bb.edx.rr; + time.s.high = bb.ecx.rr; + return time.i; +} + +#if 0 +static unsigned long rerangeMemoryMap(unsigned long count) +{ + int i, still_changing, newcount = count; + + MemoryRange * range = (MemoryRange *)BIOS_ADDR; + struct MemoryRange change_tmp; + + /* sort map list by memory addresses (low -> high) */ + still_changing = 1; + while (still_changing) { + still_changing = 0; + for (i=1; i > , swap */ + if (range[i].base < range[i-1].base) { + change_tmp.base = range[i].base; + change_tmp.length = range[i].length; + change_tmp.type = range[i].type; + + range[i].base = range[i-1].base; + range[i].length = range[i-1].length; + range[i].type = range[i-1].type; + + range[i-1].base = change_tmp.base; + range[i-1].length = change_tmp.length; + range[i-1].type = change_tmp.type; + + still_changing=1; + } + } + } + + /* clear overlaps */ + /* linux's arch/i386/kern/setup.c may have better algorithm */ + for (i=1; i range[i].base ) { + range[newcount].base = range[i].base + range[i].length; + range[newcount].length = range[i-1].base + range[i-1].length - range[newcount].base; + range[newcount].type = range[i-1].type; + newcount++; + + range[i-1].length = range[i].base - range[i-1].base; + } + } + + /* + * 0xb0000000 : 0x10000000 NG + * 0xc0000400 NG + * 0xf2000000 NG + */ + range[newcount].base = 0xb0000000; + range[newcount].length = 0x0f000000; + range[newcount].type = kMemoryRangeUsable; + newcount++; + + return newcount; +} +#endif + +unsigned long getMemoryMap( MemoryRange * rangeArray, + unsigned long maxRangeCount, + unsigned long * conMemSizePtr, + unsigned long * extMemSizePtr ) +{ + #define kMemoryMapSignature 'SMAP' + #define kDescriptorSizeMin 20 + + MemoryRange * range = (MemoryRange *)BIOS_ADDR; + unsigned long count = 0; + // unsigned long rerangedCount; + unsigned long long conMemSize = 0; + unsigned long long extMemSize = 0; + + // Prepare for the INT15 E820h call. Each call returns a single + // memory range. A continuation value is returned that must be + // provided on a subsequent call to fetch the next range. + // + // Certain BIOSes (Award 6.00PG) expect the upper word in EAX + // to be cleared on entry, otherwise only a single range will + // be reported. + // + // Some BIOSes will simply ignore the value of ECX on entry. + // Probably best to keep its value at 20 to avoid surprises. + + //printf("Get memory map 0x%x, %d\n", rangeArray);getc(); + if (maxRangeCount > (BIOS_LEN / sizeof(MemoryRange))) { + maxRangeCount = (BIOS_LEN / sizeof(MemoryRange)); + } + bb.ebx.rx = 0; // Initial continuation value must be zero. + + while ( count < maxRangeCount ) + { + bb.intno = 0x15; + bb.eax.rx = 0xe820; + bb.ecx.rx = kDescriptorSizeMin; + bb.edx.rx = kMemoryMapSignature; + bb.edi.rr = NORMALIZED_OFFSET( (unsigned long) range ); + bb.es = NORMALIZED_SEGMENT( (unsigned long) range ); + bios(&bb); + + // Check for errors. + + if ( bb.flags.cf + || bb.eax.rx != kMemoryMapSignature + || bb.ecx.rx != kDescriptorSizeMin ) { + //printf("Got an error %x %x %x\n", bb.flags.cf, + // bb.eax.rx, bb.ecx.rx); + break; + } + + // Tally up the conventional/extended memory sizes. + + if ( range->type == kMemoryRangeUsable || + range->type == kMemoryRangeACPI || + range->type == kMemoryRangeNVS ) + { + // Tally the conventional memory ranges. + if ( range->base + range->length <= 0xa0000 ) { + conMemSize += range->length; + } + + // Record the top of extended memory. + if ( range->base >= EXTENDED_ADDR ) { + extMemSize += range->length; + } + } + + range++; + count++; + + // Is this the last address range? + + if ( bb.ebx.rx == 0 ) { + //printf("last range\n"); + break; + } + } + *conMemSizePtr = conMemSize / 1024; // size in KB + *extMemSizePtr = extMemSize / 1024; // size in KB + +#if 0 + rerangedCount = rerangeMemoryMap(count); + range += rerangedCount - count; +#endif + + // Copy out data + bcopy((char *)BIOS_ADDR, rangeArray, ((char *)range - (char *)BIOS_ADDR)); + +#if DEBUG + { + int i; + printf("%d total ranges\n", count);getc(); + for (i=0, range = rangeArray; itype, (unsigned int)range->base, (unsigned int)range->length); getc(); + } + } +#endif + + return count; +} + +unsigned long getExtendedMemorySize() +{ + // Get extended memory size for large configurations. Not used unless + // the INT15, E820H call (Get System Address Map) failed. + // + // Input: + // + // AX Function Code E801h + // + // Outputs: + // + // CF Carry Flag Carry cleared indicates no error. + // AX Extended 1 Number of contiguous KB between 1 and 16 MB, + // maximum 0x3C00 = 15 MB. + // BX Extended 2 Number of contiguous 64 KB blocks between + // 16 MB and 4 GB. + // CX Configured 1 Number of contiguous KB between 1 and 16 MB, + // maximum 0x3C00 = 15 MB. + // DX Configured 2 Number of contiguous 64 KB blocks between + // 16 MB and 4 GB. + + bb.intno = 0x15; + bb.eax.rx = 0xe801; + bios(&bb); + + // Return the size of memory above 1MB (extended memory) in kilobytes. + + if ( bb.flags.cf == 0 ) return (bb.ebx.rr * 64 + bb.eax.rr); + + // Get Extended memory size. Called on last resort since the return + // value is limited to 16-bits (a little less than 64MB max). May + // not be supported by modern BIOSes. + // + // Input: + // + // AX Function Code E801h + // + // Outputs: + // + // CF Carry Flag Carry cleared indicates no error. + // AX Memory Count Number of contiguous KB above 1MB. + + bb.intno = 0x15; + bb.eax.rx = 0x88; + bios(&bb); + + // Return the size of memory above 1MB (extended memory) in kilobytes. + + return bb.flags.cf ? 0 : bb.eax.rr; +} + +unsigned long getConventionalMemorySize() +{ + bb.intno = 0x12; + bios(&bb); + return bb.eax.rr; // kilobytes +} + +void video_mode(int mode) +{ + bb.intno = 0x10; + bb.eax.r.h = 0x00; + bb.eax.r.l = mode; + bios(&bb); +} + +int biosread(int dev, int cyl, int head, int sec, int num) +{ + int i; + + bb.intno = 0x13; + sec += 1; /* sector numbers start at 1 */ + + for (i=0;;) { + bb.ecx.r.h = cyl; + bb.ecx.r.l = ((cyl & 0x300) >> 2) | (sec & 0x3F); + bb.edx.r.h = head; + bb.edx.r.l = dev; + bb.eax.r.l = num; + bb.ebx.rr = OFFSET(ptov(BIOS_ADDR)); + bb.es = SEGMENT(ptov(BIOS_ADDR)); + + bb.eax.r.h = 0x02; + bios(&bb); + + /* In case of a successful call, make sure we set AH (return code) to zero. */ + if (bb.flags.cf == 0) + bb.eax.r.h = 0; + + /* Now we can really check for the return code (AH) value. */ + if ((bb.eax.r.h == 0x00) || (i++ >= 5)) + break; + + /* reset disk subsystem and try again */ + bb.eax.r.h = 0x00; + bios(&bb); + } + return bb.eax.r.h; +} + +int ebiosread(int dev, unsigned long long sec, int count) +{ + int i; + static struct { + unsigned char size; + unsigned char reserved; + unsigned char numblocks; + unsigned char reserved2; + unsigned short bufferOffset; + unsigned short bufferSegment; + unsigned long long startblock; + } addrpacket __attribute__((aligned(16))) = {0}; + addrpacket.size = sizeof(addrpacket); + + for (i=0;;) { + bb.intno = 0x13; + bb.eax.r.h = 0x42; + bb.edx.r.l = dev; + bb.esi.rr = NORMALIZED_OFFSET((unsigned)&addrpacket); + bb.ds = NORMALIZED_SEGMENT((unsigned)&addrpacket); + addrpacket.reserved = addrpacket.reserved2 = 0; + addrpacket.numblocks = count; + addrpacket.bufferOffset = OFFSET(ptov(BIOS_ADDR)); + addrpacket.bufferSegment = SEGMENT(ptov(BIOS_ADDR)); + addrpacket.startblock = sec; + bios(&bb); + + /* In case of a successful call, make sure we set AH (return code) to zero. */ + if (bb.flags.cf == 0) + bb.eax.r.h = 0; + + /* Now we can really check for the return code (AH) value. */ + if ((bb.eax.r.h == 0x00) || (i++ >= 5)) + break; + + /* reset disk subsystem and try again */ + bb.eax.r.h = 0x00; + bios(&bb); + } + return bb.eax.r.h; +} + +int ebioswrite(int dev, long sec, int count) +{ + int i; + static struct { + unsigned char size; + unsigned char reserved; + unsigned char numblocks; + unsigned char reserved2; + unsigned short bufferOffset; + unsigned short bufferSegment; + unsigned long long startblock; + } addrpacket __attribute__((aligned(16))) = {0}; + addrpacket.size = sizeof(addrpacket); + + for (i=0;;) { + bb.intno = 0x13; + bb.eax.r.l = 0; /* Don't verify */ + bb.eax.r.h = 0x43; + bb.edx.r.l = dev; + bb.esi.rr = NORMALIZED_OFFSET((unsigned)&addrpacket); + bb.ds = NORMALIZED_SEGMENT((unsigned)&addrpacket); + addrpacket.reserved = addrpacket.reserved2 = 0; + addrpacket.numblocks = count; + addrpacket.bufferOffset = OFFSET(ptov(BIOS_ADDR)); + addrpacket.bufferSegment = SEGMENT(ptov(BIOS_ADDR)); + addrpacket.startblock = sec; + bios(&bb); + + /* In case of a successful call, make sure we set AH (return code) to zero. */ + if (bb.flags.cf == 0) + bb.eax.r.h = 0; + + /* Now we can really check for the return code (AH) value. */ + if ((bb.eax.r.h == 0x00) || (i++ >= 5)) + break; + + /* reset disk subsystem and try again */ + bb.eax.r.h = 0x00; + bios(&bb); + } + return bb.eax.r.h; +} + +void putc(int ch) +{ + bb.intno = 0x10; + bb.ebx.r.h = 0x00; /* background black */ + bb.ebx.r.l = 0x0F; /* foreground white */ + bb.eax.r.h = 0x0e; + bb.eax.r.l = ch; + bios(&bb); +} + +void putca(int ch, int attr, int repeat) +{ + bb.intno = 0x10; + bb.ebx.r.h = 0x00; /* page number */ + bb.ebx.r.l = attr; /* attribute */ + bb.eax.r.h = 0x9; + bb.eax.r.l = ch; + bb.ecx.rx = repeat; /* repeat count */ + bios(&bb); +} + +/* Check to see if the passed-in drive is in El Torito no-emulation mode. */ +int is_no_emulation(int drive) +{ + struct packet { + unsigned char packet_size; + unsigned char media_type; + unsigned char drive_num; + unsigned char ctrlr_index; + unsigned long lba; + unsigned short device_spec; + unsigned short buffer_segment; + unsigned short load_segment; + unsigned short sector_count; + unsigned char cyl_count; + unsigned char sec_count; + unsigned char head_count; + unsigned char reseved; + } __attribute__((packed)); + static struct packet pkt; + + bzero(&pkt, sizeof(pkt)); + pkt.packet_size = 0x13; + + bb.intno = 0x13; + bb.eax.r.h = 0x4b; + bb.eax.r.l = 0x01; // subfunc: get info + bb.edx.r.l = drive; + bb.esi.rr = NORMALIZED_OFFSET((unsigned)&pkt); + bb.ds = NORMALIZED_SEGMENT((unsigned)&pkt); + + bios(&bb); +#if DEBUG + printf("el_torito info drive %x\n", drive); + + printf("--> cf %x, eax %x\n", bb.flags.cf, bb.eax.rr); + + printf("pkt_size: %x\n", pkt.packet_size); + printf("media_type: %x\n", pkt.media_type); + printf("drive_num: %x\n", pkt.drive_num); + printf("device_spec: %x\n", pkt.device_spec); + printf("press a key->\n");getc(); +#endif + + /* Some BIOSes erroneously return cf = 1 */ + /* Just check to see if the drive number is the same. */ + if (pkt.drive_num == drive) { + if ((pkt.media_type & 0x0F) == 0) { + /* We are in no-emulation mode. */ + return 1; + } + } + + return 0; +} + +#if DEBUG +/* + * BIOS drive information. + */ +void print_drive_info(boot_drive_info_t *dp) +{ + // printf("buf_size = %x\n", dp->params.buf_size); + printf("info_flags = %x\n", dp->params.info_flags); + printf(" phys_cyls = %lx\n", dp->params. phys_cyls); + printf(" phys_heads = %lx\n", dp->params. phys_heads); + printf(" phys_spt = %lx\n", dp->params. phys_spt); + printf("phys_sectors = %lx%lx\n", ((unsigned long *)(&dp->params.phys_sectors))[1], + ((unsigned long *)(&dp->params.phys_sectors))[0]); + printf("phys_nbps = %x\n", dp->params.phys_nbps); + // printf("dpte_offset = %x\n", dp->params.dpte_offset); + // printf("dpte_segment = %x\n", dp->params.dpte_segment); + // printf("key = %x\n", dp->params.key); + // printf("path_len = %x\n", dp->params. path_len); + // printf("reserved1 = %x\n", dp->params. reserved1); + // printf("reserved2 = %x\n", dp->params.reserved2); + //printf("bus_type[4] = %x\n", dp->params. bus_type[4]); + //printf("interface_type[8] = %x\n", dp->params. interface_type[8]); + //printf("interface_path[8] = %x\n", dp->params. interface_path[8]); + //printf("dev_path[8] = %x\n", dp->params. dev_path[8]); + // printf("reserved3 = %x\n", dp->params. reserved3); + // printf("checksum = %x\n", dp->params. checksum); + + printf(" io_port_base = %x\n", dp->dpte.io_port_base); + printf(" control_port_base = %x\n", dp->dpte.control_port_base); + printf(" head_flags = %x\n", dp->dpte. head_flags); + printf(" vendor_info = %x\n", dp->dpte. vendor_info); + printf(" irq = %x\n", dp->dpte. irq); + // printf(" irq_unused = %x\n", dp->dpte. irq_unused); + printf(" block_count = %x\n", dp->dpte. block_count); + printf(" dma_channe = %x\n", dp->dpte. dma_channel); + printf(" dma_type = %x\n", dp->dpte. dma_type); + printf(" pio_type = %x\n", dp->dpte. pio_type); + printf(" pio_unused = %x\n", dp->dpte. pio_unused); + printf(" option_flags = %x\n", dp->dpte.option_flags); + // printf(" reserved = %x\n", dp->dpte.reserved); + printf(" revision = %x\n", dp->dpte. revision); + // printf(" checksum = %x\n", dp->dpte. checksum); +} + +#endif + +int get_drive_info(int drive, struct driveInfo *dp) +{ + boot_drive_info_t *di = &dp->di; + int ret = 0; + +#if UNUSED + if (maxhd == 0) { + bb.intno = 0x13; + bb.eax.r.h = 0x08; + bb.edx.r.l = 0x80; + bios(&bb); + if (bb.flags.cf == 0) + maxhd = 0x7f + bb.edx.r.l; + }; + + if (drive > maxhd) + return 0; +#endif + + bzero(dp, sizeof(struct driveInfo)); + dp->biosdev = drive; + + /* Check for El Torito no-emulation mode. */ + dp->no_emulation = is_no_emulation(drive); + + /* Check drive for EBIOS support. */ + bb.intno = 0x13; + bb.eax.r.h = 0x41; + bb.edx.r.l = drive; + bb.ebx.rr = 0x55aa; + bios(&bb); + if((bb.ebx.rr == 0xaa55) && (bb.flags.cf == 0)) { + /* Get flags for supported operations. */ + dp->uses_ebios = bb.ecx.r.l; + } + + if (dp->uses_ebios & (EBIOS_ENHANCED_DRIVE_INFO | EBIOS_LOCKING_ACCESS | EBIOS_FIXED_DISK_ACCESS)) { + /* Get EBIOS drive info. */ + static struct drive_params params; + + params.buf_size = sizeof(params); + bb.intno = 0x13; + bb.eax.r.h = 0x48; + bb.edx.r.l = drive; + bb.esi.rr = NORMALIZED_OFFSET((unsigned)¶ms); + bb.ds = NORMALIZED_SEGMENT((unsigned)¶ms); + bios(&bb); + if(bb.flags.cf != 0 /* || params.phys_sectors < 2097152 */) { + dp->uses_ebios = 0; + di->params.buf_size = 1; + } else { + bcopy(¶ms, &di->params, sizeof(params)); + + if (drive >= BASE_HD_DRIVE && + (dp->uses_ebios & EBIOS_ENHANCED_DRIVE_INFO) && + di->params.buf_size >= 30 && + !(di->params.dpte_offset == 0xFFFF && di->params.dpte_segment == 0xFFFF)) { + void *ptr = (void *)(di->params.dpte_offset + ((unsigned int)di->params.dpte_segment << 4)); + bcopy(ptr, &di->dpte, sizeof(di->dpte)); + } + } + } + +/* + * zef: This code will fail on recent JMicron and Intel option ROMs + */ +// if (di->params.phys_heads == 0 || di->params.phys_spt == 0) { +// /* Either it's not EBIOS, or EBIOS didn't tell us. */ +// bb.intno = 0x13; +// bb.eax.r.h = 0x08; +// bb.edx.r.l = drive; +// bios(&bb); +// if (bb.flags.cf == 0 && bb.eax.r.h == 0) { +// unsigned long cyl; +// unsigned long sec; +// unsigned long hds; +// +// hds = bb.edx.r.h; +// sec = bb.ecx.r.l & 0x3F; +// if((dp->uses_ebios & EBIOS_ENHANCED_DRIVE_INFO) && (sec != 0)) { +// cyl = (di->params.phys_sectors / ((hds + 1) * sec)) - 1; +// } +// else { +// cyl = bb.ecx.r.h | ((bb.ecx.r.l & 0xC0) << 2); +// } +// di->params.phys_heads = hds; +// di->params.phys_spt = sec; +// di->params.phys_cyls = cyl; +// } else { +// ret = -1; +// } +// } + + if (dp->no_emulation) { + /* Some BIOSes give us erroneous EBIOS support information. + * Assume that if you're on a CD, then you can use + * EBIOS disk calls. + */ + dp->uses_ebios |= EBIOS_FIXED_DISK_ACCESS; + } +#if DEBUG + print_drive_info(di); + printf("uses_ebios = 0x%x\n", dp->uses_ebios); + printf("result %d\n", ret); + printf("press a key->\n");getc(); +#endif + + if (ret == 0) { + dp->valid = 1; + } + return ret; +} + +int ebiosEjectMedia(int biosdev) +{ + bb.intno = 0x13; + bb.eax.r.h = 0x46; + bb.eax.r.l = 0; + bb.edx.rx = biosdev; + bios(&bb); + return bb.eax.r.h; +} + +void setCursorPosition(int x, int y, int page) +{ + bb.intno = 0x10; + bb.eax.r.h = 0x02; + bb.ebx.r.h = page; /* page 0 for graphics */ + bb.edx.r.l = x; + bb.edx.r.h = y; + bios(&bb); +} + +void setCursorType(int type) +{ + bb.intno = 0x10; + bb.eax.r.h = 0x01; + bb.ecx.rr = type; + bios(&bb); +} + +void getCursorPositionAndType(int * x, int * y, int * type) +{ + bb.intno = 0x10; + bb.eax.r.h = 0x03; + bios(&bb); + *x = bb.edx.r.l; + *y = bb.edx.r.h; + *type = bb.ecx.rr; +} + +void scollPage(int x1, int y1, int x2, int y2, int attr, int rows, int dir) +{ + bb.intno = 0x10; + bb.eax.r.h = (dir > 0) ? 0x06 : 0x07; + bb.eax.r.l = rows; + bb.ebx.r.h = attr; + bb.ecx.r.h = y1; + bb.ecx.r.l = x1; + bb.edx.r.h = y2; + bb.edx.r.l = x2; + bios(&bb); +} + +void clearScreenRows( int y1, int y2 ) +{ + scollPage( 0, y1, 80 - 1, y2, 0x07, y2 - y1 + 1, 1 ); +} + +void setActiveDisplayPage( int page ) +{ + bb.intno = 0x10; + bb.eax.r.h = 5; + bb.eax.r.l = page; + bios(&bb); +} + +#if DEBUG + +int terminateDiskEmulation() +{ + static char cd_spec[0x13]; + + bb.intno = 0x13; + bb.eax.r.h = 0x4b; + bb.eax.r.l = 0; // subfunc: terminate emulation + bb.esi.rr = NORMALIZED_OFFSET((unsigned)&cd_spec); + bb.ds = NORMALIZED_SEGMENT((unsigned)&cd_spec); + bios(&bb); + return bb.eax.r.h; +} + +int readDriveParameters(int drive, struct driveParameters *dp) +{ + bb.intno = 0x13; + bb.edx.r.l = drive; + bb.eax.r.h = 0x08; + bios(&bb); + if (bb.eax.r.h == 0) { + dp->heads = bb.edx.r.h; + dp->sectors = bb.ecx.r.l & 0x3F; + dp->cylinders = bb.ecx.r.h | ((bb.ecx.r.l & 0xC0) << 2); + dp->totalDrives = bb.edx.r.l; + } else { + bzero(dp, sizeof(*dp)); + } + return bb.eax.r.h; + +} +#endif + +#ifdef APM_SUPPORT + +#define APM_INTNO 0x15 +#define APM_INTCODE 0x53 + +int +APMPresent(void) +{ + bb.intno = APM_INTNO; + bb.eax.r.h = APM_INTCODE; + bb.eax.r.l = 0x00; + bb.ebx.rr = 0x0000; + bios(&bb); + if ((bb.flags.cf == 0) && + (bb.ebx.r.h == 'P') && + (bb.ebx.r.l == 'M')) { + /* Success */ + bootArgs->apmConfig.major_vers = bb.eax.r.h; + bootArgs->apmConfig.minor_vers = bb.eax.r.l; + bootArgs->apmConfig.flags.data = bb.ecx.rr; + return 1; + } + return 0; +} + +int +APMConnect32(void) +{ + bb.intno = APM_INTNO; + bb.eax.r.h = APM_INTCODE; + bb.eax.r.l = 0x03; + bb.ebx.rr = 0x0000; + bios(&bb); + if (bb.flags.cf == 0) { + /* Success */ + bootArgs->apmConfig.cs32_base = (bb.eax.rr) << 4; + bootArgs->apmConfig.entry_offset = bb.ebx.rx; + bootArgs->apmConfig.cs16_base = (bb.ecx.rr) << 4; + bootArgs->apmConfig.ds_base = (bb.edx.rr) << 4; + if (bootArgs->apmConfig.major_vers >= 1 && + bootArgs->apmConfig.minor_vers >= 1) { + bootArgs->apmConfig.cs_length = bb.esi.rr; + bootArgs->apmConfig.ds_length = bb.edi.rr; + } else { + bootArgs->apmConfig.cs_length = + bootArgs->apmConfig.ds_length = 64 * 1024; + } + bootArgs->apmConfig.connected = 1; + return 1; + } + return 0; +} + +#endif /* APM_SUPPORT */ + +#ifdef EISA_SUPPORT +bool eisa_present(void) +{ + static bool checked = false; + static bool isEISA; + + if (!checked) { + if (strncmp((char *)0xfffd9, "EISA", 4) == 0) + isEISA = true; + + checked = true; + } + + return (isEISA); +} + +int +ReadEISASlotInfo(EISA_slot_info_t *ep, int slot) +{ + union { + struct { + unsigned char char2h :2; + unsigned char char1 :5; + unsigned char char3 :5; + unsigned char char2l :3; + unsigned char d2 :4; + unsigned char d1 :4; + unsigned char d4 :4; + unsigned char d3 :4; + } s; + unsigned char data[4]; + } u; + static char hex[0x10] = "0123456789ABCDEF"; + + + bb.intno = 0x15; + bb.eax.r.h = 0xd8; + bb.eax.r.l = 0x00; + bb.ecx.r.l = slot; + bios(&bb); + if (bb.flags.cf) + return bb.eax.r.h; + ep->u_ID.d = bb.eax.r.l; + ep->configMajor = bb.ebx.r.h; + ep->configMinor = bb.ebx.r.l; + ep->checksum = bb.ecx.rr; + ep->numFunctions = bb.edx.r.h; + ep->u_resources.d = bb.edx.r.l; + u.data[0] = bb.edi.r.l; + u.data[1] = bb.edi.r.h; + u.data[2] = bb.esi.r.l; + u.data[3] = bb.esi.r.h; + ep->id[0] = u.s.char1 + ('A' - 1); + ep->id[1] = (u.s.char2l | (u.s.char2h << 3)) + ('A' - 1); + ep->id[2] = u.s.char3 + ('A' - 1); + ep->id[3] = hex[u.s.d1]; + ep->id[4] = hex[u.s.d2]; + ep->id[5] = hex[u.s.d3]; + ep->id[6] = hex[u.s.d4]; + ep->id[7] = 0; + return 0; +} + +/* + * Note: ep must point to an address below 64k. + */ + +int +ReadEISAFuncInfo(EISA_func_info_t *ep, int slot, int function) +{ + bb.intno = 0x15; + bb.eax.r.h = 0xd8; + bb.eax.r.l = 0x01; + bb.ecx.r.l = slot; + bb.ecx.r.h = function; + bb.esi.rr = (unsigned int)ep->data; + bios(&bb); + if (bb.eax.r.h == 0) { + ep->slot = slot; + ep->function = function; + } + return bb.eax.r.h; +} +#endif /* EISA_SUPPORT */ + +#define PCI_SIGNATURE 0x20494350 /* "PCI " */ + +int +ReadPCIBusInfo(PCI_bus_info_t *pp) +{ + bb.intno = 0x1a; + bb.eax.r.h = 0xb1; + bb.eax.r.l = 0x01; + bios(&bb); + if ((bb.eax.r.h == 0) && (bb.edx.rx == PCI_SIGNATURE)) { + pp->BIOSPresent = 1; + pp->u_bus.d = bb.eax.r.l; + pp->majorVersion = bb.ebx.r.h; + pp->minorVersion = bb.ebx.r.l; + pp->maxBusNum = bb.ecx.r.l; + return 0; + } + return -1; +} + +void sleep(int n) +{ + unsigned int endtime = (time18() + 18*n); + while (time18() < endtime); +} + +void delay(int ms) +{ + bb.intno = 0x15; + bb.eax.r.h = 0x86; + bb.ecx.rr = ms >> 16; + bb.edx.rr = ms & 0xFFFF; + bios(&bb); +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/pci.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/pci.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/pci.h.svn-base (revision 850) @@ -0,0 +1,904 @@ +/* + * + * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved. + * + */ + +#ifndef __LIBSAIO_PCI_H +#define __LIBSAIO_PCI_H + +typedef struct { + uint32_t :2; + uint32_t reg :6; + uint32_t func:3; + uint32_t dev :5; + uint32_t bus :8; + uint32_t :7; + uint32_t eb :1; +} pci_addr_t; + +typedef union { + pci_addr_t bits; + uint32_t addr; +} pci_dev_t; + +typedef struct pci_dt_t { + pci_dev_t dev; + + uint16_t vendor_id; + uint16_t device_id; + + union { + struct { + uint16_t vendor_id; + uint16_t device_id; + } subsys; + uint32_t subsys_id; + } subsys_id; + + uint16_t class_id; + + struct pci_dt_t *parent; + struct pci_dt_t *children; + struct pci_dt_t *next; +} pci_dt_t; + +#define PCIADDR(bus, dev, func) (1 << 31) | (bus << 16) | (dev << 11) | (func << 8) +#define PCI_ADDR_REG 0xcf8 +#define PCI_DATA_REG 0xcfc + +extern pci_dt_t *root_pci_dev; +extern uint8_t pci_config_read8(uint32_t, uint8_t); +extern uint16_t pci_config_read16(uint32_t, uint8_t); +extern uint32_t pci_config_read32(uint32_t, uint8_t); +extern void pci_config_write8(uint32_t, uint8_t, uint8_t); +extern void pci_config_write16(uint32_t, uint8_t, uint16_t); +extern void pci_config_write32(uint32_t, uint8_t, uint32_t); +extern char *get_pci_dev_path(pci_dt_t *); +extern void build_pci_dt(void); +extern void dump_pci_dt(pci_dt_t *); + +/* Option ROM header */ +typedef struct { + uint16_t signature; // 0xAA55 + uint8_t rom_size; + uint32_t entry_point; + uint8_t reserved[15]; + uint16_t pci_header_offset; + uint16_t expansion_header_offset; +} option_rom_header_t; + +/* Option ROM PCI Data Structure */ +typedef struct { + uint32_t signature; // 0x52494350 'PCIR' + uint16_t vendor_id; + uint16_t device_id; + uint16_t vital_product_data_offset; + uint16_t structure_length; + uint8_t structure_revision; + uint8_t class_code[3]; + uint16_t image_length; + uint16_t image_revision; + uint8_t code_type; + uint8_t indicator; + uint16_t reserved; +} option_rom_pci_header_t; + +//----------------------------------------------------------------------------- +// added by iNDi + +typedef struct { + uint32_t signature; // 0x24506E50 '$PnP' + uint8_t revision; // 1 + uint8_t length; // + uint16_t offset; + uint8_t checksum; + uint32_t identifier; + uint16_t manufacturer; + uint16_t product; + uint8_t class[3]; + uint8_t indicators; + uint16_t boot_vector; + uint16_t disconnect_vector; + uint16_t bootstrap_vector; + uint16_t reserved; + uint16_t resource_vector; +} option_rom_pnp_header_t; + +/* + * Under PCI, each device has 256 bytes of configuration address space, + * of which the first 64 bytes are standardized as follows: + */ + +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_DEVICE_ID 0x02 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ +#define PCI_COMMAND_DISABLE_INTx 0x400 /* PCIE: Disable INTx interrupts */ + +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_INTx 0x08 /* PCIE: INTx interrupt pending */ +#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ +#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ +#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ +#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ +#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ +#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ +#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ +#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ + +#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */ + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 + +#define PCI_BIST 0x0f /* 8 bits */ +#define PCI_BIST_CODE_MASK 0x0f /* Return result */ +#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ +#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ + +/* + * Base addresses specify locations in memory or I/O space. + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only + * 1 bits are decoded. + */ +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f) +#define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03) +/* bit 1 is reserved if address_space = 1 */ + +/* Header type 0 (normal devices) */ +#define PCI_CARDBUS_CIS 0x28 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c +#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 +#define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff) + +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ + +/* 0x35-0x3b are reserved */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_MIN_GNT 0x3e /* 8 bits */ +#define PCI_MAX_LAT 0x3f /* 8 bits */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1d +#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ +#define PCI_IO_RANGE_TYPE_16 0x00 +#define PCI_IO_RANGE_TYPE_32 0x01 +#define PCI_IO_RANGE_MASK ~0x0f +#define PCI_SEC_STATUS 0x1e /* Secondary status register */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f +#define PCI_MEMORY_RANGE_MASK ~0x0f +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_RANGE_TYPE_MASK 0x0f +#define PCI_PREF_RANGE_TYPE_32 0x00 +#define PCI_PREF_RANGE_TYPE_64 0x01 +#define PCI_PREF_RANGE_MASK ~0x0f +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2c +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +/* 0x34 same as for htype 0 */ +/* 0x35-0x3b is reserved */ +#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_BRIDGE_CONTROL 0x3e +#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ +#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ +#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ +#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ +#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ +#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100 /* PCI-X? */ +#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200 /* PCI-X? */ +#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400 /* PCI-X? */ +#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800 /* PCI-X? */ + +/* Header type 2 (CardBus bridges) */ +/* 0x14-0x15 reserved */ +#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ +#define PCI_CB_MEMORY_BASE_0 0x1c +#define PCI_CB_MEMORY_LIMIT_0 0x20 +#define PCI_CB_MEMORY_BASE_1 0x24 +#define PCI_CB_MEMORY_LIMIT_1 0x28 +#define PCI_CB_IO_BASE_0 0x2c +#define PCI_CB_IO_BASE_0_HI 0x2e +#define PCI_CB_IO_LIMIT_0 0x30 +#define PCI_CB_IO_LIMIT_0_HI 0x32 +#define PCI_CB_IO_BASE_1 0x34 +#define PCI_CB_IO_BASE_1_HI 0x36 +#define PCI_CB_IO_LIMIT_1 0x38 +#define PCI_CB_IO_LIMIT_1_HI 0x3a +#define PCI_CB_IO_RANGE_MASK ~0x03 +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_CB_BRIDGE_CONTROL 0x3e +#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ +#define PCI_CB_BRIDGE_CTL_SERR 0x02 +#define PCI_CB_BRIDGE_CTL_ISA 0x04 +#define PCI_CB_BRIDGE_CTL_VGA 0x08 +#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 +#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 +#define PCI_CB_SUBSYSTEM_ID 0x42 +#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ +/* 0x48-0x7f reserved */ + +/* Capability lists */ +#define PCI_CAP_LIST_ID 0 /* Capability ID */ +#define PCI_CAP_ID_PM 0x01 /* Power Management */ +#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ +#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ +#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */ +#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ +#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ +#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ +#define PCI_CAP_ID_DBG 0x0A /* Debug port */ +#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ +#define PCI_CAP_ID_HOTPLUG 0x0C /* PCI hot-plug */ +#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ +#define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */ +#define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */ +#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ +#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ +#define PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */ +#define PCI_CAP_ID_AF 0x13 /* Advanced features of PCI devices integrated in PCIe root cplx */ +#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ +#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ +#define PCI_CAP_SIZEOF 4 + +/* Capabilities residing in the PCI Express extended configuration space */ + +#define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */ +#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */ +#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ +#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ +#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ +#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */ +#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ +#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ +#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */ +#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */ +#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */ +#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */ +#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */ +#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ + +/* Power Management Registers */ + +#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ +#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ +#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */ +#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */ +#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ +#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ +#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */ +#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */ +#define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */ +#define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */ +#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */ +#define PCI_PM_CTRL 4 /* PM control and status register */ +#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ +#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */ +#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */ +#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ +#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */ +#define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */ +#define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */ +#define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */ +#define PCI_PM_SIZEOF 8 + +/* AGP registers */ + +#define PCI_AGP_VERSION 2 /* BCD version number */ +#define PCI_AGP_RFU 3 /* Rest of capability flags */ +#define PCI_AGP_STATUS 4 /* Status register */ +#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ +#define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */ +#define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ +#define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */ +#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ +#define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */ +#define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */ +#define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */ +#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */ +#define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */ +#define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */ +#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */ +#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */ +#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ +#define PCI_AGP_COMMAND 8 /* Control register */ +#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ +#define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ +#define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ +#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ +#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ +#define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ +#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ +#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ +#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ +#define PCI_AGP_SIZEOF 12 + +/* Vital Product Data */ + +#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ +#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ +#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ +#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ + +/* Slot Identification */ + +#define PCI_SID_ESR 2 /* Expansion Slot Register */ +#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ +#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ +#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ + +/* Message Signaled Interrupts registers */ + +#define PCI_MSI_FLAGS 2 /* Various flags */ +#define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */ +#define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */ +#define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */ +#define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */ +#define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */ +#define PCI_MSI_RFU 3 /* Rest of capability flags */ +#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ +#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ +#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ +#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ +#define PCI_MSI_MASK_BIT_32 12 /* per-vector masking for 32-bit devices */ +#define PCI_MSI_MASK_BIT_64 16 /* per-vector masking for 64-bit devices */ +#define PCI_MSI_PENDING_32 16 /* per-vector interrupt pending for 32-bit devices */ +#define PCI_MSI_PENDING_64 20 /* per-vector interrupt pending for 64-bit devices */ + +/* PCI-X */ +#define PCI_PCIX_COMMAND 2 /* Command register offset */ +#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ +#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ +#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 +#define PCI_PCIX_COMMAND_RESERVED 0xf80 +#define PCI_PCIX_STATUS 4 /* Status register offset */ +#define PCI_PCIX_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_STATUS_64BIT 0x00010000 +#define PCI_PCIX_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 +#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 +#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ +#define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ +#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ +#define PCI_PCIX_SIZEOF 4 + +/* PCI-X Bridges */ +#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 +#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 +#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 +#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 +#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ +#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 +#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ +#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 +#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 +#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff +#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 +#define PCI_PCIX_BRIDGE_SIZEOF 12 + +/* PCI Express */ +#define PCI_EXP_FLAGS 0x2 /* Capabilities register */ +#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ +#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ +#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ +#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */ +#define PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */ +#define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */ +#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ +#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ +#define PCI_EXP_DEVCAP 0x4 /* Device capabilities */ +#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ +#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ +#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ +#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ +#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ +#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ +#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ +#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ +#define PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */ +#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ +#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ +#define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */ +#define PCI_EXP_DEVCTL 0x8 /* Device Control */ +#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ +#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ +#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ +#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ +#define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */ +#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ +#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ +#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ +#define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */ +#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ +#define PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */ +#define PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */ +#define PCI_EXP_DEVSTA 0xa /* Device Status */ +#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ +#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ +#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ +#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ +#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ +#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ +#define PCI_EXP_LNKCAP 0xc /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */ +#define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */ +#define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */ +#define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ +#define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ +#define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */ +#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */ +#define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */ +#define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */ +#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ +#define PCI_EXP_LNKCTL 0x10 /* Link Control */ +#define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ +#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ +#define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */ +#define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */ +#define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */ +#define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */ +#define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */ +#define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */ +#define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */ +#define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */ +#define PCI_EXP_LNKSTA 0x12 /* Link Status */ +#define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */ +#define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */ +#define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */ +#define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */ +#define PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */ +#define PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */ +#define PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */ +#define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */ +#define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */ +#define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */ +#define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */ +#define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */ +#define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ +#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ +#define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ +#define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ +#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */ +#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_SLTCTL 0x18 /* Slot Control */ +#define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */ +#define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */ +#define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */ +#define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */ +#define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */ +#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ +#define PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */ +#define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */ +#define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */ +#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */ +#define PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */ +#define PCI_EXP_SLTSTA 0x1a /* Slot Status */ +#define PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */ +#define PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */ +#define PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */ +#define PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */ +#define PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */ +#define PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */ +#define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */ +#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */ +#define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */ +#define PCI_EXP_RTCTL 0x1c /* Root Control */ +#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ +#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ +#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ +#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ +#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */ +#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ +#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */ +#define PCI_EXP_RTSTA 0x20 /* Root Status */ +#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */ +#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ +#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ +#define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */ +#define PCI_EXP_DEVCTL2 0x28 /* Device Control */ +#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */ +#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */ +#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */ +#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */ +#define PCI_EXP_DEVSTA2 0x2a /* Device Status */ +#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ +#define PCI_EXP_LNKCTL2 0x30 /* Link Control */ +#define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ +#define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */ +#define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */ +#define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ +#define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */ +#define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */ +#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */ +#define PCI_EXP_LNKSTA2 0x32 /* Link Status */ +#define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */ +#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ +#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ +#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ + +/* MSI-X */ +#define PCI_MSIX_ENABLE 0x8000 +#define PCI_MSIX_MASK 0x4000 +#define PCI_MSIX_TABSIZE 0x03ff +#define PCI_MSIX_TABLE 4 +#define PCI_MSIX_PBA 8 +#define PCI_MSIX_BIR 0x7 + +/* Subsystem vendor/device ID for PCI bridges */ +#define PCI_SSVID_VENDOR 4 +#define PCI_SSVID_DEVICE 6 + +/* Advanced Error Reporting */ +#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ +#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */ +#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ +#define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */ +#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ +#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ +#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ +#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ +#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ +#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ +#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ +#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ +#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ +#define PCI_ERR_UNC_ACS_VIOL 0x00200000 /* ACS Violation */ +#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ +/* Same bits as above */ +#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ +/* Same bits as above */ +#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ +#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ +#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ +#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ +#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ +#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ +#define PCI_ERR_COR_REP_ANFE 0x00002000 /* Advisory Non-Fatal Error */ +#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ +/* Same bits as above */ +#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ +#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ +#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ +#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ +#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ +#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ +#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ +#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ +#define PCI_ERR_ROOT_STATUS 48 +#define PCI_ERR_ROOT_COR_SRC 52 +#define PCI_ERR_ROOT_SRC 54 + +/* Virtual Channel */ +#define PCI_VC_PORT_REG1 4 +#define PCI_VC_PORT_REG2 8 +#define PCI_VC_PORT_CTRL 12 +#define PCI_VC_PORT_STATUS 14 +#define PCI_VC_RES_CAP 16 +#define PCI_VC_RES_CTRL 20 +#define PCI_VC_RES_STATUS 26 + +/* Power Budgeting */ +#define PCI_PWR_DSR 4 /* Data Select Register */ +#define PCI_PWR_DATA 8 /* Data Register */ +#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ +#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ +#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ +#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ +#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ +#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ +#define PCI_PWR_CAP 12 /* Capability */ +#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ + +/* Access Control Services */ +#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ +#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ +#define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */ +#define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */ +#define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */ +#define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */ +#define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */ +#define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */ +#define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */ +#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ +#define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */ +#define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable */ +#define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable */ +#define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enable */ +#define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */ +#define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */ +#define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable */ +#define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */ + +/* Alternative Routing-ID Interpretation */ +#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ +#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ +#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ +#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ +#define PCI_ARI_CTRL 0x06 /* ARI Control Register */ +#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ +#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ +#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ + +/* Address Translation Service */ +#define PCI_ATS_CAP 0x04 /* ATS Capability Register */ +#define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */ +#define PCI_ATS_CTRL 0x06 /* ATS Control Register */ +#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ +#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ + +/* Single Root I/O Virtualization */ +#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */ +#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */ +#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */ +#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */ +#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */ +#define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */ +#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */ +#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */ +#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ +#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */ +#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */ +#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */ +#define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs that could be associated */ +#define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available */ +#define PCI_IOV_FDL 0x12 /* Function Dependency Link */ +#define PCI_IOV_OFFSET 0x14 /* First VF Offset */ +#define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */ +#define PCI_IOV_DID 0x1a /* VF Device ID */ +#define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */ +#define PCI_IOV_SYSPS 0x20 /* System Page Size */ +#define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */ +#define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */ +#define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset */ +#define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */ +#define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */ + +/* + * The PCI interface treats multi-function devices as independent + * devices. The slot/function address of each device is encoded + * in a single byte as follows: + * + * 7:3 = slot + * 2:0 = function + */ +#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) +#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) +#define PCI_FUNC(devfn) ((devfn) & 0x07) + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_ATA 0x0105 +#define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_SAS 0x0107 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_ISDN 0x0204 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV 0x0403 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_PCI_SEMI 0x0609 +#define PCI_CLASS_BRIDGE_IB_TO_PCI 0x060a +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MSERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 +#define PCI_CLASS_SERIAL_INFINIBAND 0x0c06 + +#define PCI_BASE_CLASS_WIRELESS 0x0d +#define PCI_CLASS_WIRELESS_IRDA 0x0d00 +#define PCI_CLASS_WIRELESS_CONSUMER_IR 0x0d01 +#define PCI_CLASS_WIRELESS_RF 0x0d10 +#define PCI_CLASS_WIRELESS_OTHER 0x0d80 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1010 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL 0x11 +#define PCI_CLASS_SIGNAL_DPIO 0x1100 +#define PCI_CLASS_SIGNAL_PERF_CTR 0x1101 +#define PCI_CLASS_SIGNAL_SYNCHRONIZER 0x1110 +#define PCI_CLASS_SIGNAL_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff + +/* Several ID's we need in the library */ + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_VENDOR_ID_AMD 0x1002 +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_VENDOR_ID_TEXAS_INSTRUMENTS 0x104c +#define PCI_VENDOR_ID_VIA 0x1106 + +#endif /* !__LIBSAIO_PCI_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/ufs_byteorder.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ufs_byteorder.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ufs_byteorder.h.svn-base (revision 850) @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright (c) 1992 NeXT Computer, Inc. + * + * UFS byte swapping routines to make a big endian file system useful on a + * little endian machine. + * + * HISTORY + * + * 8 Jul 1992 Brian Pinkerton at NeXT + * Created. + */ + +#ifndef __LIBSAIO_UFS_BYTEORDER_H +#define __LIBSAIO_UFS_BYTEORDER_H + +#include +#include +#include +#include +#include +#include +#include + +void byte_swap_ints(unsigned int *array, int count); +void byte_swap_shorts(unsigned short *array, int count); +void byte_swap_longlongs(unsigned long long *array, int count); + +void byte_swap_superblock(struct fs *sb); +void byte_swap_dinode_in(struct dinode *di); +void byte_swap_dir_block_in(char *addr, int count); +void byte_swap_inode_in(struct dinode *dc, struct dinode *ic); + +#endif /* !__LIBSAIO_UFS_BYTEORDER_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/acpi.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/acpi.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/acpi.h.svn-base (revision 850) @@ -0,0 +1,153 @@ +#ifndef __LIBSAIO_ACPI_H +#define __LIBSAIO_ACPI_H + +#define ACPI_RANGE_START (0x0E0000) +#define ACPI_RANGE_END (0x0FFFFF) + +#define UINT64_LE_FROM_CHARS(a,b,c,d,e,f,g,h) \ +( ((uint64_t)h << 56) \ +| ((uint64_t)g << 48) \ +| ((uint64_t)f << 40) \ +| ((uint64_t)e << 32) \ +| ((uint64_t)d << 24) \ +| ((uint64_t)c << 16) \ +| ((uint64_t)b << 8) \ +| ((uint64_t)a << 0) \ +) + +#define ACPI_SIGNATURE_UINT64_LE UINT64_LE_FROM_CHARS('R','S','D',' ','P','T','R',' ') + +/* Per ACPI 3.0a spec */ + +// TODO Migrate +struct acpi_2_rsdp { + char Signature[8]; + uint8_t Checksum; + char OEMID[6]; + uint8_t Revision; + uint32_t RsdtAddress; + uint32_t Length; + uint64_t XsdtAddress; + uint8_t ExtendedChecksum; + char Reserved[3]; +} __attribute__((packed)); + +// TODO Migrate +struct acpi_2_rsdt { + char Signature[4]; + uint32_t Length; + uint8_t Revision; + uint8_t Checksum; + char OEMID[6]; + char OEMTableId[8]; + uint32_t OEMRevision; + uint32_t CreatorId; + uint32_t CreatorRevision; +} __attribute__((packed)); + +// TODO Migrate +struct acpi_2_xsdt { + char Signature[4]; + uint32_t Length; + uint8_t Revision; + uint8_t Checksum; + char OEMID[6]; + char OEMTableId[8]; + uint32_t OEMRevision; + uint32_t CreatorId; + uint32_t CreatorRevision; +} __attribute__((packed)); + +// TODO Migrate +struct acpi_2_ssdt { + char Signature[4]; + uint32_t Length; + uint8_t Revision; + uint8_t Checksum; + char OEMID[6]; + char OEMTableId[8]; + uint32_t OEMRevision; + uint32_t CreatorId; + uint32_t CreatorRevision; +} __attribute__((packed)); + +// TODO Migrate +struct acpi_2_dsdt { + char Signature[4]; + uint32_t Length; + uint8_t Revision; + uint8_t Checksum; + char OEMID[6]; + char OEMTableId[8]; + uint32_t OEMRevision; + uint32_t CreatorId; + uint32_t CreatorRevision; +} __attribute__((packed)); + +// TODO Migrate +struct acpi_2_fadt { + char Signature[4]; + uint32_t Length; + uint8_t Revision; + uint8_t Checksum; + char OEMID[6]; + char OEMTableId[8]; + uint32_t OEMRevision; + uint32_t CreatorId; + uint32_t CreatorRevision; + uint32_t FIRMWARE_CTRL; + uint32_t DSDT; + uint8_t Model; // JrCs + uint8_t PM_Profile; // JrCs + uint16_t SCI_Interrupt; + uint32_t SMI_Command_Port; + uint8_t ACPI_Enable; + uint8_t ACPI_Disable; + uint8_t S4BIOS_Command; + uint8_t PState_Control; + uint32_t PM1A_Event_Block_Address; + uint32_t PM1B_Event_Block_Address; + uint32_t PM1A_Control_Block_Address; + uint32_t PM1B_Control_Block_Address; + uint32_t PM2_Control_Block_Address; + uint32_t PM_Timer_Block_Address; + uint32_t GPE0_Block_Address; + uint32_t GPE1_Block_Address; + uint8_t PM1_Event_Block_Length; + uint8_t PM1_Control_Block_Length; + uint8_t PM2_Control_Block_Length; + uint8_t PM_Timer_Block_Length; + uint8_t GPE0_Block_Length; + uint8_t GPE1_Block_Length; + uint8_t GPE1_Base_Offset; + uint8_t CST_Support; + uint16_t C2_Latency; + uint16_t C3_Latency; + uint16_t CPU_Cache_Size; + uint16_t Cache_Flush_Stride; + uint8_t Duty_Cycle_Offset; + uint8_t Duty_Cycle_Width; + uint8_t RTC_Day_Alarm_Index; + uint8_t RTC_Month_Alarm_Index; + uint8_t RTC_Century_Index; + uint16_t Boot_Flags; + uint8_t Reserved0; +/* Begin Asere */ + //Reset Fix + uint32_t Flags; + uint8_t Reset_SpaceID; + uint8_t Reset_BitWidth; + uint8_t Reset_BitOffset; + uint8_t Reset_AccessWidth; + uint64_t Reset_Address; + uint8_t Reset_Value; + uint8_t Reserved[3]; + + uint64_t X_FIRMWARE_CTRL; + uint64_t X_DSDT; +/* End Asere */ + /*We absolutely don't care about theese fields*/ + uint8_t notimp2[96]; +} __attribute__((packed)); + +#endif /* !__LIBSAIO_ACPI_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/device_tree.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/device_tree.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/device_tree.h.svn-base (revision 850) @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2005 Apple Computer, Inc. All Rights Reserved. + */ + +#ifndef __DEVICE_TREE_H +#define __DEVICE_TREE_H + +#include +#include + +typedef struct _Property { + const char * name; + uint32_t length; + void * value; + + struct _Property * next; +} Property; + +typedef struct _Node { + struct _Property * properties; + struct _Property * last_prop; + + struct _Node * children; + + struct _Node * next; +} Node; + + +extern Property * +DT__AddProperty(Node *node, const char *name, uint32_t length, void *value); + +extern Node * +DT__AddChild(Node *parent, const char *name); + +Node * +DT__FindNode(const char *path, bool createIfMissing); + +extern void +DT__FreeProperty(Property *prop); + +extern void +DT__FreeNode(Node *node); + +extern char * +DT__GetName(Node *node); + +void +DT__Initialize(void); + +/* + * Free up memory used by in-memory representation + * of device tree. + */ +extern void +DT__Finalize(void); + +void +DT__FlattenDeviceTree(void **result, uint32_t *length); + + +#endif /* __DEVICE_TREE_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/saio_types.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/saio_types.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/saio_types.h.svn-base (revision 850) @@ -0,0 +1,259 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* Useful types. */ + +#ifndef __LIBSAIO_SAIO_TYPES_H +#define __LIBSAIO_SAIO_TYPES_H + +#include +#include +#include "bios.h" +#include "nbp_cmd.h" +#include "bootargs.h" + +#if DEBUG +#define DEBUG_DISK(x) printf x +#else +#define DEBUG_DISK(x) +#endif + +typedef unsigned long entry_t; + +typedef struct { + unsigned int sectors:8; + unsigned int heads:8; + unsigned int cylinders:16; +} compact_diskinfo_t; + +struct driveParameters { + int cylinders; + int sectors; + int heads; + int totalDrives; +}; + +struct Tag { + long type; + char *string; + long offset; + struct Tag *tag; + struct Tag *tagNext; +}; +typedef struct Tag Tag, *TagPtr; + +typedef struct { + char plist[4096]; // buffer for plist + TagPtr dictionary; // buffer for xml dictionary + bool canOverride; // flag to mark a dictionary can be overriden +} config_file_t; + +/* + * BIOS drive information. + */ +struct boot_drive_info { + struct drive_params { + unsigned short buf_size; + unsigned short info_flags; + unsigned long phys_cyls; + unsigned long phys_heads; + unsigned long phys_spt; + unsigned long long phys_sectors; + unsigned short phys_nbps; + unsigned short dpte_offset; + unsigned short dpte_segment; + unsigned short key; + unsigned char path_len; + unsigned char reserved1; + unsigned short reserved2; + unsigned char bus_type[4]; + unsigned char interface_type[8]; + unsigned char interface_path[8]; + unsigned char dev_path[8]; + unsigned char reserved3; + unsigned char checksum; + } params; + struct drive_dpte { + unsigned short io_port_base; + unsigned short control_port_base; + unsigned char head_flags; + unsigned char vendor_info; + unsigned char irq : 4; + unsigned char irq_unused : 4; + unsigned char block_count; + unsigned char dma_channel : 4; + unsigned char dma_type : 4; + unsigned char pio_type : 4; + unsigned char pio_unused : 4; + unsigned short option_flags; + unsigned short reserved; + unsigned char revision; + unsigned char checksum; + } dpte; +} __attribute__((packed)); +typedef struct boot_drive_info boot_drive_info_t; + +struct driveInfo { + boot_drive_info_t di; + int uses_ebios; + int no_emulation; + int biosdev; + int valid; +}; + +typedef struct FinderInfo { + unsigned char data[16]; +} FinderInfo; + +struct BootVolume; +typedef struct BootVolume * BVRef; +typedef struct BootVolume * CICell; + +typedef long (*FSInit)(CICell ih); +typedef long (*FSLoadFile)(CICell ih, char * filePath); +typedef long (*FSReadFile)(CICell ih, char *filePath, void *base, uint64_t offset, uint64_t length); +typedef long (*FSGetFileBlock)(CICell ih, char *filePath, unsigned long long *firstBlock); +typedef long (*FSGetDirEntry)(CICell ih, char * dirPath, long long * dirIndex, + char ** name, long * flags, long * time, + FinderInfo * finderInfo, long * infoValid); +typedef long (*FSGetUUID)(CICell ih, char *uuidStr); +typedef void (*BVGetDescription)(CICell ih, char * str, long strMaxLen); +// Can be just pointed to free or a special free function +typedef void (*BVFree)(CICell ih); + +struct iob { + unsigned int i_flgs; /* see F_* below */ + unsigned int i_offset; /* seek byte offset in file */ + int i_filesize; /* size of file */ + char * i_buf; /* file load address */ +}; + +#define BPS 512 /* sector size of the device */ +#define F_READ 0x1 /* file opened for reading */ +#define F_WRITE 0x2 /* file opened for writing */ +#define F_ALLOC 0x4 /* buffer allocated */ +#define F_FILE 0x8 /* file instead of device */ +#define F_NBSF 0x10 /* no bad sector forwarding */ +#define F_SSI 0x40 /* set skip sector inhibit */ +#define F_MEM 0x80 /* memory instead of file or device */ + +struct dirstuff { + char * dir_path; /* directory path */ + long long dir_index; /* directory entry index */ + BVRef dir_bvr; /* volume reference */ +}; + +#define BVSTRLEN 32 + +struct BootVolume { + BVRef next; /* list linkage pointer */ + int biosdev; /* BIOS device number */ + int type; /* device type (floppy, hd, network) */ + unsigned int flags; /* attribute flags */ + BVGetDescription description; /* BVGetDescription function */ + int part_no; /* partition number (1 based) */ + unsigned int part_boff; /* partition block offset */ + unsigned int part_type; /* partition type */ + unsigned int fs_boff; /* 1st block # of next read */ + unsigned int fs_byteoff; /* Byte offset for read within block */ + FSLoadFile fs_loadfile; /* FSLoadFile function */ + FSReadFile fs_readfile; /* FSReadFile function */ + FSGetDirEntry fs_getdirentry; /* FSGetDirEntry function */ + FSGetFileBlock fs_getfileblock; /* FSGetFileBlock function */ + FSGetUUID fs_getuuid; /* FSGetUUID function */ + unsigned int bps; /* bytes per sector for this device */ + char name[BVSTRLEN]; /* (name of partition) */ + char type_name[BVSTRLEN]; /* (type of partition, eg. Apple_HFS) */ + BVFree bv_free; /* BVFree function */ + uint32_t modTime; + char label[BVSTRLEN]; /* partition volume label */ + char altlabel[BVSTRLEN]; /* partition volume label */ + bool filtered; /* newFilteredBVChain() will set to TRUE */ + bool visible; /* will shown in the device list */ +}; + +enum { + kBVFlagPrimary = 0x01, + kBVFlagNativeBoot = 0x02, + kBVFlagForeignBoot = 0x04, + kBVFlagBootable = 0x08, + kBVFlagEFISystem = 0x10, + kBVFlagBooter = 0x20, + kBVFlagSystemVolume = 0x40 +}; + +enum { + kBIOSDevTypeFloppy = 0x00, + kBIOSDevTypeHardDrive = 0x80, + kBIOSDevTypeNetwork = 0xE0, + kBIOSDevUnitMask = 0x0F, + kBIOSDevTypeMask = 0xF0, + kBIOSDevMask = 0xFF +}; + +enum { + + kPartitionTypeHFS = 0xAF, + kPartitionTypeHPFS = 0x07, + kPartitionTypeFAT16 = 0x06, + kPartitionTypeFAT32 = 0x0c, + kPartitionTypeEXT3 = 0x83, +}; + +//#define BIOS_DEV_TYPE(d) ((d) & kBIOSDevTypeMask) +#define BIOS_DEV_UNIT(bvr) ((bvr)->biosdev - (bvr)->type) + +/* + * KernBootStruct device types. + */ +enum { + DEV_SD = 0, + DEV_HD = 1, + DEV_FD = 2, + DEV_EN = 3 +}; + +#ifndef max +#define max(a,b) ((a) > (b) ? (a) : (b)) +#endif + +#ifndef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#define round2(x, m) (((x) + (m / 2)) & ~(m - 1)) +#define roundup2(x, m) (((x) + m - 1) & ~(m - 1)) + +#define MAKEKERNDEV(t, u, p) MAKEBOOTDEV(t, 0, 0, u, p) + +enum { + kNetworkDeviceType = kBIOSDevTypeNetwork, + kBlockDeviceType = kBIOSDevTypeHardDrive +}; //gBootFileType_t; + +enum { + kCursorTypeHidden = 0x0100, + kCursorTypeUnderline = 0x0607 +}; + +#endif /* !__LIBSAIO_SAIO_TYPES_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/acpi_patcher.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/acpi_patcher.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/acpi_patcher.h.svn-base (revision 850) @@ -0,0 +1,37 @@ +/* + * Copyright 2008 mackerintel + */ + +#ifndef __LIBSAIO_ACPI_PATCHER_H +#define __LIBSAIO_ACPI_PATCHER_H + +#include "libsaio.h" + +uint64_t acpi10_p; +uint64_t acpi20_p; +uint64_t smbios_p; + +extern int setupAcpi(); + +extern EFI_STATUS addConfigurationTable(); + +extern EFI_GUID gEfiAcpiTableGuid; +extern EFI_GUID gEfiAcpi20TableGuid; + +struct p_state +{ + union + { + uint16_t Control; + struct + { + uint8_t VID; // Voltage ID + uint8_t FID; // Frequency ID + }; + }; + + uint8_t CID; // Compare ID + uint32_t Frequency; +}; + +#endif /* !__LIBSAIO_ACPI_PATCHER_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/libsaio.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/libsaio.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/libsaio.h.svn-base (revision 850) @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* libsaio.h */ + +#ifndef __LIBSAIO_LIBSAIO_H +#define __LIBSAIO_LIBSAIO_H + +#include "libsa.h" +#include "memory.h" +#include "io_inline.h" +#include "saio_types.h" +#include "saio_internal.h" + +#endif /* !__LIBSAIO_LIBSAIO_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/md5c.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/md5c.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/md5c.c.svn-base (revision 850) @@ -0,0 +1,298 @@ +/* + * MD5C.C - RSA Data Security, Inc., MD5 message-digest algorithm + * + * Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All + * rights reserved. + * + * License to copy and use this software is granted provided that it + * is identified as the "RSA Data Security, Inc. MD5 Message-Digest + * Algorithm" in all material mentioning or referencing this software + * or this function. + * + * License is also granted to make and use derivative works provided + * that such works are identified as "derived from the RSA Data + * Security, Inc. MD5 Message-Digest Algorithm" in all material + * mentioning or referencing the derived work. + * + * RSA Data Security, Inc. makes no representations concerning either + * the merchantability of this software or the suitability of this + * software for any particular purpose. It is provided "as is" + * without express or implied warranty of any kind. + * + * These notices must be retained in any copies of any part of this + * documentation and/or software. + * + * $Id: md5c.c,v 1.1 2005/06/24 22:47:12 curtisg Exp $ + * + * This code is the same as the code published by RSA Inc. It has been + * edited for clarity and style only. + */ + +#include "libsaio.h" + +#if MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_X_VERSION_10_5 +# include +#else +# include +#endif + + +#define Encode memcpy +#define Decode memcpy + +static unsigned char PADDING[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* F, G, H and I are basic MD5 functions. */ +#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) +#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) +#define H(x, y, z) ((x) ^ (y) ^ (z)) +#define I(x, y, z) ((y) ^ ((x) | (~z))) + +/* ROTATE_LEFT rotates x left n bits. */ +#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) + +/* + * FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4. + * Rotation is separate from addition to prevent recomputation. + */ +#define FF(a, b, c, d, x, s, ac) { \ + (a) += F ((b), (c), (d)) + (x) + (u_int32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define GG(a, b, c, d, x, s, ac) { \ + (a) += G ((b), (c), (d)) + (x) + (u_int32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define HH(a, b, c, d, x, s, ac) { \ + (a) += H ((b), (c), (d)) + (x) + (u_int32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define II(a, b, c, d, x, s, ac) { \ + (a) += I ((b), (c), (d)) + (x) + (u_int32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } + +static void MD5Transform (u_int32_t state[4], const unsigned char block[64]); + +/* MD5 initialization. Begins an MD5 operation, writing a new context. */ + +void +MD5Init (context) + MD5_CTX *context; +{ + + context->count[0] = context->count[1] = 0; + + /* Load magic initialization constants. */ + context->state[0] = 0x67452301; + context->state[1] = 0xefcdab89; + context->state[2] = 0x98badcfe; + context->state[3] = 0x10325476; +} + +/* + * MD5 block update operation. Continues an MD5 message-digest + * operation, processing another message block, and updating the + * context. + */ + +void +MD5Update (context, input, inputLen) + MD5_CTX *context; +#if MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_X_VERSION_10_5 + const void *input; +#else + const unsigned char *input; +#endif + unsigned int inputLen; +{ + unsigned int i, index, partLen; + + /* Compute number of bytes mod 64 */ + index = (unsigned int)((context->count[0] >> 3) & 0x3F); + + /* Update number of bits */ + if ((context->count[0] += ((u_int32_t)inputLen << 3)) + < ((u_int32_t)inputLen << 3)) + context->count[1]++; + context->count[1] += ((u_int32_t)inputLen >> 29); + + partLen = 64 - index; + + /* Transform as many times as possible. */ + if (inputLen >= partLen) { + memcpy((void *)&context->buffer[index], (const void *)input, + partLen); + MD5Transform (context->state, context->buffer); + + for (i = partLen; i + 63 < inputLen; i += 64) + MD5Transform (context->state, &((const unsigned char *)input)[i]); + + index = 0; + } + else + i = 0; + + /* Buffer remaining input */ + memcpy ((void *)&context->buffer[index], (const void *)&((const unsigned char*)input)[i], + inputLen-i); +} + +/* + * MD5 padding. Adds padding followed by original length. + */ + +void +MD5Pad (context) + MD5_CTX *context; +{ + unsigned char bits[8]; + unsigned int index, padLen; + + /* Save number of bits */ + Encode (bits, context->count, 8); + + /* Pad out to 56 mod 64. */ + index = (unsigned int)((context->count[0] >> 3) & 0x3f); + padLen = (index < 56) ? (56 - index) : (120 - index); + MD5Update (context, PADDING, padLen); + + /* Append length (before padding) */ + MD5Update (context, bits, 8); +} + +/* + * MD5 finalization. Ends an MD5 message-digest operation, writing the + * the message digest and zeroizing the context. + */ + +void +MD5Final (digest, context) + unsigned char digest[16]; + MD5_CTX *context; +{ + /* Do padding. */ + MD5Pad (context); + + /* Store state in digest */ + Encode (digest, context->state, 16); + + /* Zeroize sensitive information. */ + memset ((void *)context, 0, sizeof (*context)); +} + +/* MD5 basic transformation. Transforms state based on block. */ + +static void +MD5Transform (state, block) + u_int32_t state[4]; + const unsigned char block[64]; +{ + u_int32_t a = state[0], b = state[1], c = state[2], d = state[3], x[16]; + + Decode (x, block, 64); + + /* Round 1 */ +#define S11 7 +#define S12 12 +#define S13 17 +#define S14 22 + FF (a, b, c, d, x[ 0], S11, 0xd76aa478); /* 1 */ + FF (d, a, b, c, x[ 1], S12, 0xe8c7b756); /* 2 */ + FF (c, d, a, b, x[ 2], S13, 0x242070db); /* 3 */ + FF (b, c, d, a, x[ 3], S14, 0xc1bdceee); /* 4 */ + FF (a, b, c, d, x[ 4], S11, 0xf57c0faf); /* 5 */ + FF (d, a, b, c, x[ 5], S12, 0x4787c62a); /* 6 */ + FF (c, d, a, b, x[ 6], S13, 0xa8304613); /* 7 */ + FF (b, c, d, a, x[ 7], S14, 0xfd469501); /* 8 */ + FF (a, b, c, d, x[ 8], S11, 0x698098d8); /* 9 */ + FF (d, a, b, c, x[ 9], S12, 0x8b44f7af); /* 10 */ + FF (c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */ + FF (b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */ + FF (a, b, c, d, x[12], S11, 0x6b901122); /* 13 */ + FF (d, a, b, c, x[13], S12, 0xfd987193); /* 14 */ + FF (c, d, a, b, x[14], S13, 0xa679438e); /* 15 */ + FF (b, c, d, a, x[15], S14, 0x49b40821); /* 16 */ + + /* Round 2 */ +#define S21 5 +#define S22 9 +#define S23 14 +#define S24 20 + GG (a, b, c, d, x[ 1], S21, 0xf61e2562); /* 17 */ + GG (d, a, b, c, x[ 6], S22, 0xc040b340); /* 18 */ + GG (c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */ + GG (b, c, d, a, x[ 0], S24, 0xe9b6c7aa); /* 20 */ + GG (a, b, c, d, x[ 5], S21, 0xd62f105d); /* 21 */ + GG (d, a, b, c, x[10], S22, 0x2441453); /* 22 */ + GG (c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */ + GG (b, c, d, a, x[ 4], S24, 0xe7d3fbc8); /* 24 */ + GG (a, b, c, d, x[ 9], S21, 0x21e1cde6); /* 25 */ + GG (d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */ + GG (c, d, a, b, x[ 3], S23, 0xf4d50d87); /* 27 */ + GG (b, c, d, a, x[ 8], S24, 0x455a14ed); /* 28 */ + GG (a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */ + GG (d, a, b, c, x[ 2], S22, 0xfcefa3f8); /* 30 */ + GG (c, d, a, b, x[ 7], S23, 0x676f02d9); /* 31 */ + GG (b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */ + + /* Round 3 */ +#define S31 4 +#define S32 11 +#define S33 16 +#define S34 23 + HH (a, b, c, d, x[ 5], S31, 0xfffa3942); /* 33 */ + HH (d, a, b, c, x[ 8], S32, 0x8771f681); /* 34 */ + HH (c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */ + HH (b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */ + HH (a, b, c, d, x[ 1], S31, 0xa4beea44); /* 37 */ + HH (d, a, b, c, x[ 4], S32, 0x4bdecfa9); /* 38 */ + HH (c, d, a, b, x[ 7], S33, 0xf6bb4b60); /* 39 */ + HH (b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */ + HH (a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */ + HH (d, a, b, c, x[ 0], S32, 0xeaa127fa); /* 42 */ + HH (c, d, a, b, x[ 3], S33, 0xd4ef3085); /* 43 */ + HH (b, c, d, a, x[ 6], S34, 0x4881d05); /* 44 */ + HH (a, b, c, d, x[ 9], S31, 0xd9d4d039); /* 45 */ + HH (d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */ + HH (c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */ + HH (b, c, d, a, x[ 2], S34, 0xc4ac5665); /* 48 */ + + /* Round 4 */ +#define S41 6 +#define S42 10 +#define S43 15 +#define S44 21 + II (a, b, c, d, x[ 0], S41, 0xf4292244); /* 49 */ + II (d, a, b, c, x[ 7], S42, 0x432aff97); /* 50 */ + II (c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */ + II (b, c, d, a, x[ 5], S44, 0xfc93a039); /* 52 */ + II (a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */ + II (d, a, b, c, x[ 3], S42, 0x8f0ccc92); /* 54 */ + II (c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */ + II (b, c, d, a, x[ 1], S44, 0x85845dd1); /* 56 */ + II (a, b, c, d, x[ 8], S41, 0x6fa87e4f); /* 57 */ + II (d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */ + II (c, d, a, b, x[ 6], S43, 0xa3014314); /* 59 */ + II (b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */ + II (a, b, c, d, x[ 4], S41, 0xf7537e82); /* 61 */ + II (d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */ + II (c, d, a, b, x[ 2], S43, 0x2ad7d2bb); /* 63 */ + II (b, c, d, a, x[ 9], S44, 0xeb86d391); /* 64 */ + + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + + /* Zeroize sensitive information. */ + memset ((void *)x, 0, sizeof (x)); +} Index: branches/Chimera/i386/libsaio/.svn/text-base/platform.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/platform.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/platform.h.svn-base (revision 850) @@ -0,0 +1,156 @@ +/* + * platform.h + * AsereBLN: reworked and extended + * + */ + +#ifndef __LIBSAIO_PLATFORM_H +#define __LIBSAIO_PLATFORM_H + +#include "libsaio.h" + +extern bool platformCPUFeature(uint32_t); +extern void scan_platform(void); +extern void dumpPhysAddr(const char * title, void * a, int len); + +/* CPUID index into cpuid_raw */ +#define CPUID_0 0 +#define CPUID_1 1 +#define CPUID_2 2 +#define CPUID_3 3 +#define CPUID_4 4 +#define CPUID_80 5 +#define CPUID_81 6 +#define CPUID_MAX 7 + +#define CPU_MODEL_YONAH 0x0E +#define CPU_MODEL_MEROM 0x0F +#define CPU_MODEL_PENRYN 0x17 +#define CPU_MODEL_NEHALEM 0x1A +#define CPU_MODEL_ATOM 0x1C +#define CPU_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield, Jasper */ +#define CPU_MODEL_DALES 0x1F /* Havendale, Auburndale */ +#define CPU_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */ +#define CPU_MODEL_SANDY 0x2a /* Sandy bridge */ +#define CPU_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP, Westmere-WS */ +#define CPU_MODEL_SANDY_XEON 0x2D +#define CPU_MODEL_NEHALEM_EX 0x2E +#define CPU_MODEL_WESTMERE_EX 0x2F + +/* CPU Features */ +#define CPU_FEATURE_MMX 0x00000001 // MMX Instruction Set +#define CPU_FEATURE_SSE 0x00000002 // SSE Instruction Set +#define CPU_FEATURE_SSE2 0x00000004 // SSE2 Instruction Set +#define CPU_FEATURE_SSE3 0x00000008 // SSE3 Instruction Set +#define CPU_FEATURE_SSE41 0x00000010 // SSE41 Instruction Set +#define CPU_FEATURE_SSE42 0x00000020 // SSE42 Instruction Set +#define CPU_FEATURE_EM64T 0x00000040 // 64Bit Support +#define CPU_FEATURE_HTT 0x00000080 // HyperThreading +#define CPU_FEATURE_MOBILE 0x00000100 // Mobile CPU +#define CPU_FEATURE_MSR 0x00000200 // MSR Support + +/* SMBIOS Memory Types */ +#define SMB_MEM_TYPE_UNDEFINED 0 +#define SMB_MEM_TYPE_OTHER 1 +#define SMB_MEM_TYPE_UNKNOWN 2 +#define SMB_MEM_TYPE_DRAM 3 +#define SMB_MEM_TYPE_EDRAM 4 +#define SMB_MEM_TYPE_VRAM 5 +#define SMB_MEM_TYPE_SRAM 6 +#define SMB_MEM_TYPE_RAM 7 +#define SMB_MEM_TYPE_ROM 8 +#define SMB_MEM_TYPE_FLASH 9 +#define SMB_MEM_TYPE_EEPROM 10 +#define SMB_MEM_TYPE_FEPROM 11 +#define SMB_MEM_TYPE_EPROM 12 +#define SMB_MEM_TYPE_CDRAM 13 +#define SMB_MEM_TYPE_3DRAM 14 +#define SMB_MEM_TYPE_SDRAM 15 +#define SMB_MEM_TYPE_SGRAM 16 +#define SMB_MEM_TYPE_RDRAM 17 +#define SMB_MEM_TYPE_DDR 18 +#define SMB_MEM_TYPE_DDR2 19 +#define SMB_MEM_TYPE_FBDIMM 20 +#define SMB_MEM_TYPE_DDR3 24 // Supported in 10.5.6+ AppleSMBIOS + +/* Memory Configuration Types */ +#define SMB_MEM_CHANNEL_UNKNOWN 0 +#define SMB_MEM_CHANNEL_SINGLE 1 +#define SMB_MEM_CHANNEL_DUAL 2 +#define SMB_MEM_CHANNEL_TRIPLE 3 + +/* Maximum number of ram slots */ +#define MAX_RAM_SLOTS 8 +#define RAM_SLOT_ENUMERATOR {0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11} + +/* Maximum number of SPD bytes */ +#define MAX_SPD_SIZE 256 + +/* Size of SMBIOS UUID in bytes */ +#define UUID_LEN 16 + +typedef struct _RamSlotInfo_t { + uint32_t ModuleSize; // Size of Module in MB + uint32_t Frequency; // in Mhz + const char* Vendor; + const char* PartNo; + const char* SerialNo; + char* spd; // SPD Dump + bool InUse; + uint8_t Type; + uint8_t BankConnections; // table type 6, see (3.3.7) + uint8_t BankConnCnt; + +} RamSlotInfo_t; + +typedef struct _PlatformInfo_t { + struct CPU { + uint32_t Features; // CPU Features like MMX, SSE2, VT, MobileCPU + uint32_t Vendor; // Vendor + uint32_t Signature; // Signature + uint32_t Stepping; // Stepping + uint32_t Model; // Model + uint32_t ExtModel; // Extended Model + uint32_t Family; // Family + uint32_t ExtFamily; // Extended Family + uint32_t NoCores; // No Cores per Package + uint32_t NoThreads; // Threads per Package + uint8_t MaxCoef; // Max Multiplier + uint8_t MaxDiv; + uint8_t CurrCoef; // Current Multiplier + uint8_t CurrDiv; + uint64_t TSCFrequency; // TSC Frequency Hz + uint64_t FSBFrequency; // FSB Frequency Hz + uint64_t CPUFrequency; // CPU Frequency Hz + uint32_t MaxRatio; // Max Bus Ratio + uint32_t MinRatio; // Min Bus Ratio + char BrandString[48]; // 48 Byte Branding String + uint32_t CPUID[CPUID_MAX][4]; // CPUID 0..4, 80..81 Raw Values + } CPU; + + struct RAM { + uint64_t Frequency; // Ram Frequency + uint32_t Divider; // Memory divider + uint8_t CAS; // CAS 1/2/2.5/3/4/5/6/7 + uint8_t TRC; + uint8_t TRP; + uint8_t RAS; + uint8_t Channels; // Channel Configuration Single,Dual or Triple + uint8_t NoSlots; // Maximum no of slots available + uint8_t Type; // Standard SMBIOS v2.5 Memory Type + RamSlotInfo_t DIMM[MAX_RAM_SLOTS]; // Information about each slot + } RAM; + + struct DMI { + int MaxMemorySlots; // number of memory slots polulated by SMBIOS + int CntMemorySlots; // number of memory slots counted + int MemoryModules; // number of memory modules installed + int DIMM[MAX_RAM_SLOTS]; // Information and SPD mapping for each slot + } DMI; + uint8_t Type; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile) + uint8_t *UUID; +} PlatformInfo_t; + +extern PlatformInfo_t Platform; + +#endif /* !__LIBSAIO_PLATFORM_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/spd.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/spd.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/spd.h.svn-base (revision 850) @@ -0,0 +1,160 @@ +/* + * Copyright 2010 AsereBLN. All rights reserved. + * + * spd.h + */ + +#ifndef __LIBSAIO_SPD_H +#define __LIBSAIO_SPD_H + +#include "platform.h" +#include "libsaio.h" + +void scan_spd(PlatformInfo_t *p); + +struct smbus_controllers_t { + uint32_t vendor; + uint32_t device; + char *name; + void (*read_smb)(pci_dt_t *smbus_dev); +}; + + +/* + * Serial Presence Detect (SPD) data stored on SDRAM modules. + * + * Datasheet: + * - Name: PC SDRAM Serial Presence Detect (SPD) Specification + * Revision 1.2A, December, 1997 + * - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf + * + * Datasheet (alternative): + * - Name: SERIAL PRESENCE DETECT STANDARD, General Standard + * JEDEC Standard No. 21-C + * - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF + */ + + +/* Byte numbers. */ +#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ +#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ +#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */ +#define SPD_NUM_ROWS 3 /* Number of row address bits */ +#define SPD_NUM_COLUMNS 4 /* Number of column address bits */ +#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */ +#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */ +#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */ +#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */ +#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ +#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ +#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */ +#define SPD_REFRESH 12 /* Refresh rate/type */ +#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */ +#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */ +#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */ +#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */ +#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */ +#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */ +#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */ +#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */ +#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */ +#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */ +#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */ +#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */ +#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */ +#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */ +#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */ +#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */ +#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */ +#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */ +#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */ +#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */ +#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ +#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */ +#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */ +#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */ +#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */ +#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */ +#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */ +#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */ +#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */ +#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */ +#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */ +#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */ +#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ +#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ +#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ +#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */ +#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */ +#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */ +#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */ +#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */ +#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */ +#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ +#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */ +#define SPD_DDR3_MEMORY_BANK 0x75 +#define SPD_DDR3_MEMORY_CODE 0x76 + +/* DRAM specifications use the following naming conventions for SPD locations */ +#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME +#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE +#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY +#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY +#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE +#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME +#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ +#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ + + +/* SPD_MEMORY_TYPE values. */ +#define SPD_MEMORY_TYPE_FPM_DRAM 1 +#define SPD_MEMORY_TYPE_EDO 2 +#define SPD_MEMORY_TYPE_PIPELINED_NIBBLE 3 +#define SPD_MEMORY_TYPE_SDRAM 4 +#define SPD_MEMORY_TYPE_MULTIPLEXED_ROM 5 +#define SPD_MEMORY_TYPE_SGRAM_DDR 6 +#define SPD_MEMORY_TYPE_SDRAM_DDR 7 +#define SPD_MEMORY_TYPE_SDRAM_DDR2 8 +#define SPD_MEMORY_TYPE_SDRAM_DDR3 0xb + +/* SPD_MODULE_VOLTAGE values. */ +#define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */ +#define SPD_VOLTAGE_LVTTL 1 /* LVTTL */ +#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */ +#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */ +#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */ + +/* SPD_DIMM_CONFIG_TYPE values. */ +#define ERROR_SCHEME_NONE 0 +#define ERROR_SCHEME_PARITY 1 +#define ERROR_SCHEME_ECC 2 + +/* SPD_ACCEPTABLE_CAS_LATENCIES values. */ +// TODO: Check values. +#define SPD_CAS_LATENCY_1_0 0x01 +#define SPD_CAS_LATENCY_1_5 0x02 +#define SPD_CAS_LATENCY_2_0 0x04 +#define SPD_CAS_LATENCY_2_5 0x08 +#define SPD_CAS_LATENCY_3_0 0x10 +#define SPD_CAS_LATENCY_3_5 0x20 +#define SPD_CAS_LATENCY_4_0 0x40 + +#define SPD_CAS_LATENCY_DDR2_3 (1 << 3) +#define SPD_CAS_LATENCY_DDR2_4 (1 << 4) +#define SPD_CAS_LATENCY_DDR2_5 (1 << 5) +#define SPD_CAS_LATENCY_DDR2_6 (1 << 6) + +/* SPD_SUPPORTED_BURST_LENGTHS values. */ +#define SPD_BURST_LENGTH_1 1 +#define SPD_BURST_LENGTH_2 2 +#define SPD_BURST_LENGTH_4 4 +#define SPD_BURST_LENGTH_8 8 +#define SPD_BURST_LENGTH_PAGE (1 << 7) + +/* SPD_MODULE_ATTRIBUTES values. */ +#define MODULE_BUFFERED 1 +#define MODULE_REGISTERED 2 + +#endif /* !__LIBSAIO_SPD_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/saio_internal.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/saio_internal.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/saio_internal.h.svn-base (revision 850) @@ -0,0 +1,221 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#ifndef __LIBSAIO_SAIO_INTERNAL_H +#define __LIBSAIO_SAIO_INTERNAL_H + +#include "saio_types.h" + +/* asm.s */ +extern void real_to_prot(void); +extern void prot_to_real(void); +extern void halt(void); +extern void startprog(unsigned int address, void *arg); +extern void loader(UInt32 code, UInt32 cmdptr); + +/* bios.s */ +extern void bios(biosBuf_t *bb); + +/* biosfn.c */ +#ifdef EISA_SUPPORT +extern bool eisa_present(void); +#endif +extern int bgetc(void); +extern int biosread(int dev, int cyl, int head, int sec, int num); +extern int ebiosread(int dev, unsigned long long sec, int count); +extern int ebioswrite(int dev, long sec, int count); +extern int get_drive_info(int drive, struct driveInfo *dp); +extern int ebiosEjectMedia(int biosdev); +extern void putc(int ch); +extern void putca(int ch, int attr, int repeat); +extern int getc(void); +extern void pause(); +extern int readKeyboardStatus(void); +extern int readKeyboardShiftFlags(void); +extern unsigned int time18(void); +extern void delay(int ms); +extern unsigned int get_diskinfo(int dev); +#if APM_SUPPORT +extern int APMPresent(void); +extern int APMConnect32(void); +#endif +extern int memsize(int i); +extern void video_mode(int mode); +extern void setCursorPosition(int x, int y, int page); +extern void setCursorType(int type); +extern void getCursorPositionAndType(int *x, int *y, int *type); +extern void scollPage(int x1, int y1, int x2, int y2, int attr, int rows, int dir); +extern void clearScreenRows(int y1, int y2); +extern void setActiveDisplayPage( int page ); +extern unsigned long getMemoryMap(struct MemoryRange * rangeArray, unsigned long maxRangeCount, + unsigned long * conMemSizePtr, unsigned long * extMemSizePtr); +extern unsigned long getExtendedMemorySize(); +extern unsigned long getConventionalMemorySize(); +extern void sleep(int n); + +/* bootstruct.c */ +extern void initKernBootStruct(void); +extern void reserveKernBootStruct(void); +extern void copyKernBootStruct(void); +extern void finalizeBootStruct(void); + +/* cache.c */ +extern void CacheReset(); +extern void CacheInit(CICell ih, long blockSize); +extern long CacheRead(CICell ih, char *buffer, long long offset, + long length, long cache); + +/* console.c */ +extern bool gVerboseMode; +extern bool gErrors; +extern void initBooterLog(void); +extern void setupBooterLog(void); +extern void putchar(int ch); +extern int getchar(void); +extern void msglog(const char * format, ...); +extern int printf(const char *format, ...); +extern int error(const char *format, ...); +extern int verbose(const char *format, ...); +extern void stop(const char *format, ...); + +/* disk.c */ +extern void rescanBIOSDevice(int biosdev); +extern struct DiskBVMap* diskResetBootVolumes(int biosdev); +extern void diskFreeMap(struct DiskBVMap *map); +extern int testBiosread( int biosdev, unsigned long long secno ); +extern BVRef diskScanBootVolumes(int biosdev, int *count); +extern void diskSeek(BVRef bvr, long long position); +extern int diskRead(BVRef bvr, long addr, long length); +extern int diskIsCDROM(BVRef bvr); +extern int biosDevIsCDROM(int biosdev); +extern BVRef getBVChainForBIOSDev(int biosdev); +extern BVRef newFilteredBVChain(int minBIOSDev, int maxBIOSDev, unsigned int allowFlags, unsigned int denyFlags, int *count); +extern int freeFilteredBVChain(const BVRef chain); +extern int rawDiskRead(BVRef bvr, unsigned int secno, void *buffer, unsigned int len); +extern int rawDiskWrite(BVRef bvr, unsigned int secno, void *buffer, unsigned int len); +extern int readBootSector(int biosdev, unsigned int secno, void *buffer); +extern void turnOffFloppy(void); +extern int testFAT32EFIBootSector( int biosdev, unsigned int secno, void * buffer ); + +/* hfs_compare.c */ +extern int32_t FastUnicodeCompare(u_int16_t *uniStr1, u_int32_t len1, + u_int16_t *uniStr2, u_int32_t len2, int byte_order); +extern void utf_encodestr( const u_int16_t * ucsp, int ucslen, + u_int8_t * utf8p, u_int32_t bufsize, int byte_order ); +extern void utf_decodestr(const u_int8_t *utf8p, u_int16_t *ucsp, + u_int16_t *ucslen, u_int32_t bufsize, int byte_order ); + +/* load.c */ +extern bool gHaveKernelCache; +extern long ThinFatFile(void **binary, unsigned long *length); +extern long DecodeMachO(void *binary, entry_t *rentry, char **raddr, int *rsize); + +/* memory.c */ +long AllocateKernelMemory( long inSize ); +long AllocateMemoryRange(char * rangeName, long start, long length, long type); + +/* misc.c */ +extern void enableA20(void); +extern int checkForSupportedHardware(); +extern int isLaptop(); +extern void getPlatformName(char *nameBuf); + +/* nbp.c */ +extern UInt32 nbpUnloadBaseCode(); +extern BVRef nbpScanBootVolumes(int biosdev, int *count); + +/* stringTable.c */ +extern char * newStringFromList(char **list, int *size); +extern int stringLength(const char *table, int compress); +extern bool getValueForConfigTableKey(config_file_t *config, const char *key, const char **val, int *size); +extern bool removeKeyFromTable(const char *key, char *table); +extern char * newStringForStringTableKey(config_file_t *config, char *key); +extern char * newStringForKey(char *key, config_file_t *configBuff); +extern bool getValueForBootKey(const char *line, const char *match, const char **matchval, int *len); +extern bool getValueForKey(const char *key, const char **val, int *size, config_file_t *configBuff); +extern const char * getStringForKey(const char * key, config_file_t *config); +extern bool getBoolForKey(const char *key, bool *val, config_file_t *configBuff); +extern bool getIntForKey(const char *key, int *val, config_file_t *configBuff); +extern bool getColorForKey(const char *key, unsigned int *val, config_file_t *configBuff); +extern bool getDimensionForKey( const char *key, unsigned int *value, config_file_t *config, unsigned int dimension_max, unsigned int object_size ); +extern int loadConfigFile(const char *configFile, config_file_t *configBuff); +extern int loadSystemConfig(config_file_t *configBuff); +extern int loadHelperConfig(config_file_t *configBuff); +extern int loadOverrideConfig(config_file_t *configBuff); +extern char * newString(const char *oldString); +extern char * getNextArg(char ** ptr, char * val); +extern int ParseXMLFile( char * buffer, TagPtr * dict ); + +/* sys.c */ +extern BVRef getBootVolumeRef( const char * path, const char ** outPath ); +extern long LoadVolumeFile(BVRef bvr, const char *fileSpec); +extern long LoadFile(const char *fileSpec); +extern long ReadFileAtOffset(const char * fileSpec, void *buffer, uint64_t offset, uint64_t length); +extern long LoadThinFatFile(const char *fileSpec, void **binary); +extern long GetDirEntry(const char *dirSpec, long long *dirIndex, const char **name, + long *flags, long *time); +extern long GetFileInfo(const char *dirSpec, const char *name, + long *flags, long *time); +extern long GetFileBlock(const char *fileSpec, unsigned long long *firstBlock); +extern long GetFSUUID(char *spec, char *uuidStr); +extern long CreateUUIDString(uint8_t uubytes[], int nbytes, char *uuidStr); +extern int openmem(char *buf, int len); +extern int open(const char *str, int how); +extern int open_bvdev(const char *bvd, const char *path, int flags); +extern int close(int fdesc); +extern int file_size(int fdesc); +extern int read(int fdesc, char *buf, int count); +extern int write(int fdesc, const char *buf, int count); +extern int writebyte(int fdesc, char value); +extern int writeint(int fdesc, int value); +extern int b_lseek(int fdesc, int addr, int ptr); +extern int tell(int fdesc); +extern const char * systemConfigDir(void); +extern struct dirstuff * opendir(const char *path); +extern struct dirstuff * vol_opendir(BVRef bvr, const char *path); +extern int closedir(struct dirstuff *dirp); +extern int readdir(struct dirstuff *dirp, const char **name, long *flags, long *time); +extern int readdir_ext(struct dirstuff * dirp, const char ** name, long * flags, + long * time, FinderInfo *finderInfo, long *infoValid); +extern void flushdev(void); +extern void scanBootVolumes(int biosdev, int *count); +extern void scanDisks(int biosdev, int *count); +extern BVRef selectBootVolume(BVRef chain); +extern void getBootVolumeDescription(BVRef bvr, char *str, long strMaxLen, bool verbose); +extern void setRootVolume(BVRef volume); +extern void setBootGlobals(BVRef chain); +extern int getDeviceDescription(BVRef volume, char *str); + +extern int gBIOSDev; +extern int gBootFileType; +extern BVRef gBootVolume; +extern BVRef gBIOSBootVolume; + +// Function pointer to be filled in if ramdisks are available +extern int (*p_get_ramdisk_info)(int biosdev, struct driveInfo *dip); +extern int (*p_ramdiskReadBytes)( int biosdev, unsigned int blkno, + unsigned int byteoff, + unsigned int byteCount, void * buffer ); + +#endif /* !__LIBSAIO_SAIO_INTERNAL_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/xml.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/xml.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/xml.c.svn-base (revision 850) @@ -0,0 +1,1150 @@ +/* + * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 2003 Apple Computer, Inc. All Rights + * Reserved. + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#include "bootstruct.h" +#include "libsaio.h" +#include "sl.h" +#include "xml.h" + +string_ref *ref_strings = NULL; + +/// TODO: remove below +static char* buffer_start = NULL; +// TODO: redo the next two functions +void SaveRefString(char* string, int id) +{ + //printf("Adding Ref String %d (%s)\n", id, string); + string_ref* tmp = ref_strings; + while(tmp) + { + if(tmp->id == id) + { + tmp->string = malloc(strlen(string)+1); + sprintf(tmp->string, "%s", string); + return; + } + tmp = tmp->next; + } + + string_ref* new_ref = malloc(sizeof(string_ref)); + new_ref->string = malloc(strlen(string)+1); + sprintf(new_ref->string, "%s", string); + new_ref->id = id; + new_ref->next = ref_strings; + ref_strings = new_ref; +} + +char* GetRefString(int id) +{ + string_ref* tmp = ref_strings; + while(tmp) + { + if(tmp->id == id) return tmp->string; + tmp = tmp->next; + } + //verbose("Unable to locate Ref String %d\n", id); + return ""; +} + + +struct Module { + struct Module *nextModule; + long willLoad; + TagPtr dict; + char *plistAddr; + long plistLength; + char *driverPath; +}; +typedef struct Module Module, *ModulePtr; + +struct DriverInfo { + char *plistAddr; + long plistLength; + void *moduleAddr; + long moduleLength; +}; +typedef struct DriverInfo DriverInfo, *DriverInfoPtr; + +#define kDriverPackageSignature1 'MKXT' +#define kDriverPackageSignature2 'MOSX' + +struct DriversPackage { + unsigned long signature1; + unsigned long signature2; + unsigned long length; + unsigned long adler32; + unsigned long version; + unsigned long numDrivers; + unsigned long reserved1; + unsigned long reserved2; +}; +typedef struct DriversPackage DriversPackage; + +enum { + kCFBundleType2, + kCFBundleType3 +}; + + +#define USEMALLOC 1 +#define DOFREE 1 + +static long ParseTagList(char *buffer, TagPtr *tag, long type, long empty); +static long ParseTagKey(char *buffer, TagPtr *tag); +static long ParseTagString(char *buffer, TagPtr *tag); +static long ParseTagInteger(char *buffer, TagPtr *tag); +static long ParseTagData(char *buffer, TagPtr *tag); +static long ParseTagDate(char *buffer, TagPtr *tag); +static long ParseTagBoolean(char *buffer, TagPtr *tag, long type); +static long GetNextTag(char *buffer, char **tag, long *start); +static long FixDataMatchingTag(char *buffer, char *tag); +static TagPtr NewTag(void); +static char *NewSymbol(char *string); +#if DOFREE +static void FreeSymbol(char *string); +#endif + + +//========================================================================== +// XMLGetProperty + +TagPtr +XMLGetProperty( TagPtr dict, const char * key ) +{ + TagPtr tagList, tag; + + if (dict->type != kTagTypeDict) return 0; + + tag = 0; + tagList = dict->tag; + while (tagList) + { + tag = tagList; + tagList = tag->tagNext; + + if ((tag->type != kTagTypeKey) || (tag->string == 0)) continue; + + if (!strcmp(tag->string, key)) return tag->tag; + } + + return 0; +} + + +// XMLGetTag(int index) + +// XMLTagCount( TagPtr dict ) +int XMLTagCount( TagPtr dict ) +{ + int count = 0; + TagPtr tagList, tag; + + if (dict->type != kTagTypeDict && dict->type != kTagTypeArray) return 0; + tag = 0; + tagList = dict->tag; + while (tagList) + { + tag = tagList; + tagList = tag->tagNext; + + if (((tag->type != kTagTypeKey) && ((tag->string == 0) || (tag->string[0] == 0))) + && (dict->type != kTagTypeArray) // If we are an array, any element is valid + ) continue; + + if(tag->type == kTagTypeKey) printf("Located key %s\n", tag->string); + + count++; + } + + return count; +} + +TagPtr XMLGetElement( TagPtr dict, int id ) +{ + if(dict->type != kTagTypeArray) return 0; + + int element = 0; + TagPtr tmp = dict->tag; + + while(element < id) + { + element++; + tmp = tmp->tagNext; + } + + return tmp; +} +/* Function for basic XML character entities parsing */ + +char* +XMLDecode(const char* src) +{ + typedef const struct XMLEntity { + const char* name; + size_t nameLen; + char value; + } XMLEntity; + + /* This is ugly, but better than specifying the lengths by hand */ + #define _e(str,c) {str,sizeof(str)-1,c} + const XMLEntity ents[] = { + _e("quot;",'"'), _e("apos;",'\''), + _e("lt;", '<'), _e("gt;", '>'), + _e("amp;", '&') + }; + + size_t len; + const char *s; + char *out, *o; + + if ( !src || !(len = strlen(src)) || !(out = malloc(len+1)) ) + return 0; + + o = out; + s = src; + while (s <= src+len) /* Make sure the terminator is also copied */ + { + if ( *s == '&' ) + { + bool entFound = false; + int i; + + s++; + for ( i = 0; i < sizeof(ents); i++) + { + if ( strncmp(s, ents[i].name, ents[i].nameLen) == 0 ) + { + entFound = true; + break; + } + } + if ( entFound ) + { + *o++ = ents[i].value; + s += ents[i].nameLen; + continue; + } + } + + *o++ = *s++; + } + + return out; +} + +//#if UNUSED +//========================================================================== +// XMLParseFile +// Expects to see one dictionary in the XML file, the final pos will be returned +// If the pos is not equal to the strlen, then there are multiple dicts +// Puts the first dictionary it finds in the +// tag pointer and returns the end of the dic, or returns -1 if not found. +// +long +XMLParseFile( char * buffer, TagPtr * dict ) +{ + long length, pos; + TagPtr tag; + pos = 0; + char *configBuffer; + + + + configBuffer = malloc(strlen(buffer)+1); + strcpy(configBuffer, buffer); + + buffer_start = configBuffer; + + while (1) + { + length = XMLParseNextTag(configBuffer + pos, &tag); + if (length == -1) break; + + pos += length; + + if (tag == 0) continue; + if (tag->type == kTagTypeDict) break; + + XMLFreeTag(tag); + } + free(configBuffer); + if (length < 0) { + return -1; + } + *dict = tag; + return pos; +} +//#endif /* UNUSED */ + +//========================================================================== +// ParseNextTag +// TODO: cleanup +long +XMLParseNextTag( char * buffer, TagPtr * tag ) +{ + long length, pos; + char * tagName; + + length = GetNextTag(buffer, &tagName, 0); + if (length == -1) return -1; + + pos = length; + if (!strncmp(tagName, kXMLTagPList, 6)) + { + length = 0; + } + /***** dict ****/ + else if (!strcmp(tagName, kXMLTagDict)) + { + length = ParseTagList(buffer + pos, tag, kTagTypeDict, 0); + } + else if (!strncmp(tagName, kXMLTagDict, strlen(kXMLTagDict)) && tagName[strlen(tagName)-1] == '/') + { + length = ParseTagList(buffer + pos, tag, kTagTypeDict, 1); + } + else if (!strncmp(tagName, kXMLTagDict " ", strlen(kXMLTagDict " "))) + { + length = ParseTagList(buffer + pos, tag, kTagTypeDict, 0); + } + /***** key ****/ + else if (!strcmp(tagName, kXMLTagKey)) + { + length = ParseTagKey(buffer + pos, tag); + } + + /***** string ****/ + else if (!strcmp(tagName, kXMLTagString)) + { + length = ParseTagString(buffer + pos, tag); + } + else if (!strncmp(tagName, kXMLTagString " ", strlen(kXMLTagString " "))) + { + // TODO: save tag if if found + if(!strncmp(tagName + strlen(kXMLTagString " "), kXMLStringID, strlen(kXMLStringID))) + { + // ID= + int id = 0; + int cnt = strlen(kXMLTagString " " kXMLStringID "\"") + 1; + while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++; + tagName[cnt] = 0; + char* val = tagName + strlen(kXMLTagString " " kXMLStringID "\""); + while(*val) + { + if ((*val >= '0' && *val <= '9')) // 0 - 9 + { + id = (id * 10) + (*val++ - '0'); + } + else + { + printf("ParseStringID error (0x%x)\n", *val); + getc(); + return -1; + + } + + } + length = ParseTagString(buffer + pos, tag); + + SaveRefString(buffer + pos, id); + } + else if(!strncmp(tagName + strlen(kXMLTagString " "), kXMLStringIDRef, strlen(kXMLStringIDRef))) + { + // IDREF= + int id = 0; + int cnt = strlen(kXMLTagString " " kXMLStringIDRef "\"") + 1; + while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++; + tagName[cnt] = 0; + char* val = tagName + strlen(kXMLTagString " " kXMLStringIDRef "\""); + while(*val) + { + if ((*val >= '0' && *val <= '9')) // 0 - 9 + { + id = (id * 10) + (*val++ - '0'); + } + else + { + printf("ParseStringIDREF error (0x%x)\n", *val); + getc(); + return -1; + + } + + } + char* str = GetRefString(id); + + TagPtr tmpTag = NewTag(); + tmpTag->type = kTagTypeString; + tmpTag->string = str; + tmpTag->tag = 0; + tmpTag->tagNext = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start + pos : 0; + *tag = tmpTag; + + length = 0; + //printf("Located IDREF, id = %d, string = %s\n", id, str); + } + + } + + /***** integer ****/ + else if (!strcmp(tagName, kXMLTagInteger)) + { + length = ParseTagInteger(buffer + pos, tag); + } + else if (!strncmp(tagName, kXMLTagInteger " ", strlen(kXMLTagInteger " "))) + { + if(!strncmp(tagName + strlen(kXMLTagInteger " "), kXMLStringID, strlen(kXMLStringID))) + { + // ID= + int id = 0; + int cnt = strlen(kXMLTagInteger " " kXMLStringID "\"") + 1; + while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++; + tagName[cnt] = 0; + char* val = tagName + strlen(kXMLTagInteger " " kXMLStringID "\""); + while(*val) + { + if ((*val >= '0' && *val <= '9')) // 0 - 9 + { + id = (id * 10) + (*val++ - '0'); + } + else + { + printf("ParseIntegerID error (0x%x)\n", *val); + getc(); + return -1; + + } + + } + length = ParseTagInteger(buffer + pos, tag); + + SaveRefString((*tag)->string, id); + } + else if(!strncmp(tagName + strlen(kXMLTagInteger " "), kXMLStringIDRef, strlen(kXMLStringIDRef))) + { + // IDREF= + int id = 0; + int cnt = strlen(kXMLTagInteger " " kXMLStringIDRef "\"") + 1; + while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++; + tagName[cnt] = 0; + char* val = tagName + strlen(kXMLTagInteger " " kXMLStringIDRef "\""); + while(*val) + { + if ((*val >= '0' && *val <= '9')) // 0 - 9 + { + id = (id * 10) + (*val++ - '0'); + } + else + { + printf("ParseStringIDREF error (0x%x)\n", *val); + getc(); + return -1; + + } + + } + int integer = (int)GetRefString(id); + + TagPtr tmpTag = NewTag(); + tmpTag->type = kTagTypeInteger; + tmpTag->string = (char*) integer; + tmpTag->tag = 0; + tmpTag->tagNext = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start + pos : 0; + + *tag = tmpTag; + + length = 0; + //printf("Located IDREF, id = %d, string = %s\n", id, str); + } + else + { + length = ParseTagInteger(buffer + pos, tag); + } + } + + /***** data ****/ + else if (!strcmp(tagName, kXMLTagData)) + { + length = ParseTagData(buffer + pos, tag); + } + else if (!strncmp(tagName, kXMLTagData " ", strlen(kXMLTagData " "))) + { + length = ParseTagData(buffer + pos, tag); + } + else if (!strcmp(tagName, kXMLTagDate)) + { + length = ParseTagDate(buffer + pos, tag); + } + + /***** date ****/ + else if (!strncmp(tagName, kXMLTagDate " ", strlen(kXMLTagDate " "))) + { + length = ParseTagDate(buffer + pos, tag); + } + + /***** false ****/ + else if (!strcmp(tagName, kXMLTagFalse)) + { + length = ParseTagBoolean(buffer + pos, tag, kTagTypeFalse); + } + /***** true ****/ + else if (!strcmp(tagName, kXMLTagTrue)) + { + length = ParseTagBoolean(buffer + pos, tag, kTagTypeTrue); + } + + /***** array ****/ + else if (!strcmp(tagName, kXMLTagArray)) + { + length = ParseTagList(buffer + pos, tag, kTagTypeArray, 0); + } + else if (!strncmp(tagName, kXMLTagArray " ", strlen(kXMLTagArray " "))) + { + length = ParseTagList(buffer + pos, tag, kTagTypeArray, 0); + } + else if (!strcmp(tagName, kXMLTagArray "/")) + { + length = ParseTagList(buffer + pos, tag, kTagTypeArray, 1); + } + + /***** unknown ****/ + else + { + *tag = 0; + length = 0; + } + + + if (length == -1) return -1; + + return pos + length; +} + +//========================================================================== +// ParseTagList + +static long +ParseTagList( char * buffer, TagPtr * tag, long type, long empty ) +{ + long length, pos; + TagPtr tagList, tmpTag; + + tagList = 0; + pos = 0; + + if (!empty) + { + while (1) + { + length = XMLParseNextTag(buffer + pos, &tmpTag); + if (length == -1) break; + + pos += length; + + if (tmpTag == 0) break; + tmpTag->tagNext = tagList; + tagList = tmpTag; + } + + if (length == -1) + { + XMLFreeTag(tagList); + return -1; + } + } + + tmpTag = NewTag(); + if (tmpTag == 0) + { + XMLFreeTag(tagList); + return -1; + } + + tmpTag->type = type; + tmpTag->string = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start : 0; + tmpTag->tag = tagList; + tmpTag->tagNext = 0; + + *tag = tmpTag; + + return pos; +} + +//========================================================================== +// ParseTagKey + +static long +ParseTagKey( char * buffer, TagPtr * tag ) +{ + long length, length2; + char *string; + TagPtr tmpTag, subTag; + + length = FixDataMatchingTag(buffer, kXMLTagKey); + if (length == -1) return -1; + + length2 = XMLParseNextTag(buffer + length, &subTag); + if (length2 == -1) return -1; + + tmpTag = NewTag(); + if (tmpTag == 0) + { + XMLFreeTag(subTag); + return -1; + } + + string = NewSymbol(buffer); + if (string == 0) + { + XMLFreeTag(subTag); + XMLFreeTag(tmpTag); + return -1; + } + + tmpTag->type = kTagTypeKey; + tmpTag->string = string; + tmpTag->tag = subTag; + tmpTag->offset = buffer_start ? buffer - buffer_start: 0; + tmpTag->tagNext = 0; + + *tag = tmpTag; + + return length + length2; +} + +//========================================================================== +// ParseTagString + +static long +ParseTagString( char * buffer, TagPtr * tag ) +{ + long length; + char * string; + + length = FixDataMatchingTag(buffer, kXMLTagString); + if (length == -1) return -1; + + TagPtr tmpTag = NewTag(); + if (tmpTag == 0) return -1; + + string = NewSymbol(buffer); + if (string == 0) + { + XMLFreeTag(tmpTag); + return -1; + } + + tmpTag->type = kTagTypeString; + tmpTag->string = string; + tmpTag->tag = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start: 0; + tmpTag->tagNext = 0; + + *tag = tmpTag; + return length; +} + +//========================================================================== +// ParseTagInteger + +static long +ParseTagInteger( char * buffer, TagPtr * tag ) +{ + long length, integer; + bool negative = false; + TagPtr tmpTag; + char* val = buffer; + int size; + + + if(buffer[0] == '<') + { + printf("Warning integer is non existant\n"); + getc(); + tmpTag = NewTag(); + tmpTag->type = kTagTypeInteger; + tmpTag->string = 0; + tmpTag->tag = 0; + tmpTag->offset = 0; + tmpTag->tagNext = 0; + + *tag = tmpTag; + + return 0; + } + + size = length = FixDataMatchingTag(buffer, kXMLTagInteger); + if (length == -1) return -1; + + tmpTag = NewTag(); + if (tmpTag == 0) return -1; + + integer = 0; + + if(size > 1 && (val[1] == 'x' || val[1] == 'X')) // Hex value + { + val += 2; + while(*val) + { + if ((*val >= '0' && *val <= '9')) // 0 - 9 + { + integer = (integer * 16) + (*val++ - '0'); + } + else if ((*val >= 'a' && *val <= 'f')) // a - f + { + integer = (integer * 16) + (*val++ - 'a' + 10); + } + else if ((*val >= 'A' && *val <= 'F')) // A - F + { + integer = (integer * 16) + (*val++ - 'a' + 10); + } + else + { + printf("ParseTagInteger hex error (0x%x) in buffer %s\n", *val, buffer); + getc(); + return -1; + + } + + } + } + else if ( size ) // Decimal value + { + if (*val == '-') + { + negative = true; + val++; + size--; + } + + for (integer = 0; size > 0; size--) + { + if(*val) // UGLY HACK, fix me. + { + if (*val < '0' || *val > '9') + { + printf("ParseTagInteger decimal error (0x%x) in buffer %s\n", *val, buffer); + getc(); + return -1; + } + + integer = (integer * 10) + (*val++ - '0'); + } + } + + if (negative) + integer = -integer; + } + + tmpTag->type = kTagTypeInteger; + tmpTag->string = (char *)integer; + tmpTag->tag = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start: 0; + tmpTag->tagNext = 0; + + *tag = tmpTag; + + return length; +} + +//========================================================================== +// ParseTagData + +static long +ParseTagData( char * buffer, TagPtr * tag ) +{ + long length; + TagPtr tmpTag; + + length = FixDataMatchingTag(buffer, kXMLTagData); + if (length == -1) return -1; + + tmpTag = NewTag(); + if (tmpTag == 0) return -1; + + //printf("ParseTagData unimplimented\n"); + //printf("Data: %s\n", buffer); + // getc(); + + // TODO: base64 decode + + char* string = NewSymbol(buffer); + tmpTag->type = kTagTypeData; + tmpTag->string = string; + tmpTag->tag = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start: 0; + tmpTag->tagNext = 0; + + *tag = tmpTag; + + return length; +} + +//========================================================================== +// ParseTagDate + +static long +ParseTagDate( char * buffer, TagPtr * tag ) +{ + long length; + TagPtr tmpTag; + + length = FixDataMatchingTag(buffer, kXMLTagDate); + if (length == -1) return -1; + + tmpTag = NewTag(); + if (tmpTag == 0) return -1; + + printf("ParseTagDate unimplimented\n"); + getc(); + + tmpTag->type = kTagTypeDate; + tmpTag->string = 0; + tmpTag->tag = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start: 0; + tmpTag->tagNext = 0; + + *tag = tmpTag; + + return length; +} + +//========================================================================== +// ParseTagBoolean + +static long +ParseTagBoolean( char * buffer, TagPtr * tag, long type ) +{ + TagPtr tmpTag; + + tmpTag = NewTag(); + if (tmpTag == 0) return -1; + + tmpTag->type = type; + tmpTag->string = 0; + tmpTag->tag = 0; + tmpTag->offset = buffer_start ? buffer - buffer_start: 0; + tmpTag->tagNext = 0; + + *tag = tmpTag; + + return 0; +} + +//========================================================================== +// GetNextTag + +static long +GetNextTag( char * buffer, char ** tag, long * start ) +{ + long cnt, cnt2; + + if (tag == 0) return -1; + + // Find the start of the tag. + cnt = 0; + while ((buffer[cnt] != '\0') && (buffer[cnt] != '<')) cnt++; + if (buffer[cnt] == '\0') return -1; + + // Find the end of the tag. + cnt2 = cnt + 1; + while ((buffer[cnt2] != '\0') && (buffer[cnt2] != '>')) cnt2++; + if (buffer[cnt2] == '\0') return -1; + + // Fix the tag data. + *tag = buffer + cnt + 1; + buffer[cnt2] = '\0'; + if (start) *start = cnt; + + return cnt2 + 1; +} + +//========================================================================== +// FixDataMatchingTag +// Modifies 'buffer' to add a '\0' at the end of the tag matching 'tag'. +// Returns the length of the data found, counting the end tag, +// or -1 if the end tag was not found. + +static long +FixDataMatchingTag( char * buffer, char * tag ) +{ + long length, start, stop; + char * endTag; + + start = 0; + while (1) + { + length = GetNextTag(buffer + start, &endTag, &stop); + if (length == -1) return -1; + + if ((*endTag == '/') && !strcmp(endTag + 1, tag)) break; + start += length; + } + + buffer[start + stop] = '\0'; + + return start + length; +} + +//========================================================================== +// NewTag + +#define kTagsPerBlock (0x1000) + +static TagPtr gTagsFree; + +static TagPtr +NewTag( void ) +{ + long cnt; + TagPtr tag; + + if (gTagsFree == 0) + { +#if USEMALLOC + tag = (TagPtr)malloc(kTagsPerBlock * sizeof(Tag)); +#else + tag = (TagPtr)AllocateBootXMemory(kTagsPerBlock * sizeof(Tag)); +#endif + if (tag == 0) return 0; + + // Initalize the new tags. + for (cnt = 0; cnt < kTagsPerBlock; cnt++) + { + tag[cnt].type = kTagTypeNone; + tag[cnt].string = 0; + tag[cnt].tag = 0; + tag[cnt].tagNext = tag + cnt + 1; + } + tag[kTagsPerBlock - 1].tagNext = 0; + + gTagsFree = tag; + } + + tag = gTagsFree; + gTagsFree = tag->tagNext; + + return tag; +} + +//========================================================================== +// XMLFreeTag + +void +XMLFreeTag( TagPtr tag ) +{ +#if DOFREE + if (tag == 0) return; + + if (tag->string) FreeSymbol(tag->string); + + XMLFreeTag(tag->tag); + XMLFreeTag(tag->tagNext); + + // Clear and free the tag. + tag->type = kTagTypeNone; + tag->string = 0; + tag->tag = 0; + tag->offset = 0; + tag->tagNext = gTagsFree; + gTagsFree = tag; +#else + return; +#endif +} + +//========================================================================== +// Symbol object. + +struct Symbol +{ + long refCount; + struct Symbol *next; + char string[]; +}; +typedef struct Symbol Symbol, *SymbolPtr; + +static SymbolPtr FindSymbol(char * string, SymbolPtr * prevSymbol); + +static SymbolPtr gSymbolsHead; + +//========================================================================== +// NewSymbol + +static char * +NewSymbol( char * string ) +{ +static SymbolPtr lastGuy = 0; + SymbolPtr symbol; + + // Look for string in the list of symbols. + symbol = FindSymbol(string, 0); + + // Add the new symbol. + if (symbol == 0) + { +#if USEMALLOC + symbol = (SymbolPtr)malloc(sizeof(Symbol) + 1 + strlen(string)); +#else + symbol = (SymbolPtr)AllocateBootXMemory(sizeof(Symbol) + 1 + strlen(string)); +#endif + if (symbol == 0) //return 0; + stop("NULL symbol!"); + + // Set the symbol's data. + symbol->refCount = 0; + strcpy(symbol->string, string); + + // Add the symbol to the list. + symbol->next = gSymbolsHead; + gSymbolsHead = symbol; + } + + // Update the refCount and return the string. + symbol->refCount++; + + if (lastGuy && lastGuy->next != 0) stop("last guy not last!"); + return symbol->string; +} + +//========================================================================== +// FreeSymbol + +#if DOFREE +static void +FreeSymbol( char * string ) +{ + SymbolPtr symbol, prev; + prev = 0; + + // Look for string in the list of symbols. + symbol = FindSymbol(string, &prev); + if (symbol == 0) return; + + // Update the refCount. + symbol->refCount--; + + if (symbol->refCount != 0) return; + + // Remove the symbol from the list. + if (prev != 0) prev->next = symbol->next; + else gSymbolsHead = symbol->next; + + // Free the symbol's memory. + free(symbol); +} +#endif + +//========================================================================== +// FindSymbol + +static SymbolPtr +FindSymbol( char * string, SymbolPtr * prevSymbol ) +{ + SymbolPtr symbol, prev; + + symbol = gSymbolsHead; + prev = 0; + + while (symbol != 0) { + if (!strcmp(symbol->string, string)) break; + + prev = symbol; + symbol = symbol->next; + } + + if ((symbol != 0) && (prevSymbol != 0)) *prevSymbol = prev; + + return symbol; +} + + + +bool XMLIsType(TagPtr dict, enum xmltype type) +{ + if(!dict) return (type == kTagTypeNone); + return (dict->type == type); +} + + +/*** Cast functions ***/ +TagPtr XMLCastArray(TagPtr dict) +{ + if(!dict) return NULL; + if(dict->type == kTagTypeArray) return dict; + else return NULL; +} + + +TagPtr XMLCastDict(TagPtr dict) +{ + if(!dict) return NULL; + if(dict->type == kTagTypeDict) return dict; + else return NULL; +} + +char* XMLCastString(TagPtr dict) +{ + if(!dict) return NULL; + + if((dict->type == kTagTypeString) || + (dict->type == kTagTypeKey)) return dict->string; + + return NULL; +} + +long XMLCastStringOffset(TagPtr dict) +{ + if(dict && + ((dict->type == kTagTypeString) || + (dict->type == kTagTypeKey))) + { + return dict->offset; + } + else + { + return -1; + } +} + + +bool XMLCastBoolean(TagPtr dict) +{ + if(!dict) return false; + if(dict->type == kTagTypeTrue) return true; + return false; +} + +int XMLCastInteger(TagPtr dict) +{ + if(!dict) + { + printf("XMLCastInteger: null dict\n"); + return 0; + } + if(dict->type == kTagTypeInteger) return (int)(dict->string); + return 0; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/asm.s.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/asm.s.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/asm.s.svn-base (revision 850) @@ -0,0 +1,497 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Mach Operating System + * Copyright (c) 1990 Carnegie-Mellon University + * Copyright (c) 1989 Carnegie-Mellon University + * All rights reserved. The CMU software License Agreement specifies + * the terms and conditions for use and redistribution. + */ +/* + * HISTORY + * $Log: asm.s,v $ + * Revision 1.8 2005/06/24 22:47:12 curtisg + * Merging changes for 4159531 to pass data to the kernel in EFI format. + * + * Revision 1.7 2004/05/13 17:58:38 curtisg + * Integrating: + * : (Silent boot) + * : (5 sec boot timeout is too short) + * : (Boot option to display graphics modes) + * : (Default graphics mode should be 32-bit) + * : (Booter should always find a video mode) + * : (Booter displays "0MB" VRAM) + * + * Revision 1.6 2003/11/05 20:51:02 curtisg + * Integrated 3069695,3331770,3370488,3371823 + * + * Revision 1.5.26.1 2003/10/27 23:57:59 curtisg + * Added printing of volume names, better handling of extended + * partitions, and updated Apple license strings. + * New chain booter should work better with foreign operating + * systems. + * + * Revision 1.5 2002/11/05 20:34:26 jliu + * Integrating: + * 3051234 boot shouldnt require Graphics = Yes + * 3091627 Need support for refresh rate adjustment + * + * Revision 1.4 2002/10/02 00:06:18 curtisg + * Integrating PR-3032510. + * + * Revision 1.3.6.1 2002/08/30 21:16:29 curtisg + * KERNBOOTSTRUCT is going away in favor of KernelBootArgs_t in . + * + * Revision 1.3 2002/07/09 14:06:21 jliu + * Merging changes from PR-2954224 branch in boot/i386. + * + * Revision 1.2.30.1 2002/07/05 16:24:51 jliu + * Merged UFS/HFS/HFS+ filesystem support from BootX. + * Moved boot2 load address due to increased size. boot0/boot1 also changed. + * Updated boot graphics and CLUT. + * Added support to chain load foreign booters. + * Fixed param passing bug in network loader. + * Misc cleanup in libsaio. + * + * Revision 1.2 2000/05/23 23:01:11 lindak + * Merged PR-2309530 into Kodiak (liu i386 booter: does not support label-less + * ufs partitions) + * + * Revision 1.1.1.2.4.1 2000/05/13 17:07:39 jliu + * New boot0 (boot1 has been deprecated). Booter must now reside in its own partition, no disk label required. + * + * Revision 1.1.1.2 1999/08/04 21:16:57 wsanchez + * Impoort of boot-66 + * + * Revision 1.3 1999/08/04 21:12:12 wsanchez + * Update APSL + * + * Revision 1.2 1999/03/25 05:48:30 wsanchez + * Add APL. + * Remove unused gzip code. + * Remove unused Adobe fonts. + * + * Revision 1.1.1.1.66.2 1999/03/16 16:08:54 wsanchez + * Substitute License + * + * Revision 1.1.1.1.66.1 1999/03/16 07:33:21 wsanchez + * Add APL + * + * Revision 1.1.1.1 1997/12/05 21:57:57 wsanchez + * Import of boot-25 (~mwatson) + * + * Revision 2.1.1.2 90//03//22 17:59:50 rvb + * Added _sp() => where is the stack at. [kupfer] + * + * Revision 2.1.1.1 90//02//09 17:25:04 rvb + * Add Intel copyright + * [90//02//09 rvb] + * + */ + + +// INTEL CORPORATION PROPRIETARY INFORMATION +// +// This software is supplied under the terms of a license agreement or +// nondisclosure agreement with Intel Corporation and may not be copied +// nor disclosed except in accordance with the terms of that agreement. +// +// Copyright 1988 Intel Corporation +// Copyright 1988, 1989 by Intel Corporation +// + +#include +#include "memory.h" + +#define data32 .byte 0x66 +#define addr32 .byte 0x67 + + .file "asm.s" + +CR0_PE_ON = 0x1 +#ifdef BOOT1 +CR0_PE_OFF = 0x7ffffffe +#else +CR0_PE_OFF = 0x7ffffff0 +#endif + +STACK32_BASE = ADDR32(STACK_SEG, 0) +STACK16_SEG = STACK_SEG +CODE32_BASE = ADDR32(BASE_SEG, 0) +CODE16_SEG = BASE_SEG + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// Pointer to 6-bytes in memory that contains the base address and the limit +// (size of GDT table in bytes) of the GDT. The LGDT is the only instruction +// that directly loads a linear address (not a segment relative address) and +// a limit in protected mode. + +.globl _Gdtr + //.data + .section __INIT,__data // turbo - Data that must be in the first segment + .align 2, 0x90 +_Gdtr: + .word GDTLIMIT + .long vtop(_Gdt) + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// IDTR representing real-mode IVT. The values are constant. + //.const + .section __INIT,__data // turbo - Data that must be in the first segment +// Real mode IDT + .align 2 +.globl _Idtr_real +_Idtr_real: + .word 0x03ff + .long 0x00000000 + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// IDTR representing protected-mode IDT. It is initially NULL which tells the +// procesor that no IDT is available. After we get into protected mode we can +// allocate memory for a proper IDT and update this IDTR to point to it. + //.data + .section __INIT,__data // turbo - Data that must be in the first segment + .align 2 +.globl _Idtr_prot +_Idtr_prot: + .word 0 + .long 0 + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// Data area for __switch_stack. +// +save_sp: .long STACK_OFS +save_ss: .long STACK_SEG + + //.text + .section __INIT,__text // turbo - This code must reside within the first segment +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// real_to_prot() +// +// Transfer from real mode to protected mode. +// Preserves all registers except EAX. +// +LABEL(__real_to_prot) + + // Interrupts are disabled in protected mode. + + cli + + // Load the Global Descriptor Table Register (GDTR). + + addr32 + data32 + lgdt OFFSET16(_Gdtr) + + // Enter protected mode by setting the PE bit in CR0. + + mov %cr0, %eax + data32 + or $CR0_PE_ON, %eax + mov %eax, %cr0 + + // Make intrasegment jump to flush the processor pipeline and + // reload CS register. + + data32 + ljmp $0x08, $xprot + +xprot: + // we are in USE32 mode now + // set up the protected mode segment registers : DS, SS, ES, FS, GS + + mov $0x10, %eax + movw %ax, %ds + movw %ax, %ss + movw %ax, %es + movw %ax, %fs + movw %ax, %gs + + // set up the PM IDT + lidt _Idtr_prot + + // Convert STACK_SEG:SP to 32-bit linear stack pointer. + + movzwl %sp, %eax + addl $STACK32_BASE, %eax + movl %eax, %esp + + // Convert STACK_SEG:BP to 32-bit linear base pointer. + + movzwl %bp, %eax + addl $STACK32_BASE, %eax + movl %eax, %ebp + + // Modify the caller's return address on the stack from + // segment offset to linear address. + + popl %eax + addl $CODE32_BASE, %eax + pushl %eax + + ret + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// prot_to_real() +// +// Transfer from protected mode to real mode. +// Preserves all registers except EAX. +// +LABEL(__prot_to_real) + + // Load real-mode IDT while we're still in USE32 mode so we don't need + // 32-bit addressing prefixes. + lidt _Idtr_real + + // Set up segment registers appropriate for real mode. + + movw $0x30, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %fs + movw %ax, %gs + movw %ax, %ss + + ljmp $0x18, $x16 // change to USE16 mode + +x16: + mov %cr0, %eax // clear the PE bit of CR0 + data32 + and $CR0_PE_OFF, %eax + mov %eax, %cr0 + + // make intersegment jmp to flush the processor pipeline + // and reload CS register + + data32 + ljmp $CODE16_SEG, $xreal - CODE32_BASE + +xreal: + // we are in real mode now + // set up the real mode segment registers : DS, DS, ES, FS, GS + + movw %cs, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %fs + movw %ax, %gs + + // load stack segment register SS. + + data32 + movl $STACK16_SEG, %eax + movw %ax, %ss + + // clear top 16-bits of ESP and EBP. + + data32 + movzwl %sp, %esp + data32 + movzwl %bp, %ebp + + // Modify caller's return address on the stack + // from linear address to segment offset. + + data32 + popl %eax + data32 + movzwl %ax, %eax + data32 + pushl %eax + + // Reenable maskable interrupts. + + sti + + data32 + ret + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// halt() +// +LABEL(_halt) +#ifdef BOOT1 + hlt +#else + call _bgetc +#endif + jmp _halt + +#ifndef BOOT1 +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// startprog(phyaddr, arg) +// Start the program on protected mode where phyaddr is the entry point. +// Passes arg to the program in %eax. +// +LABEL(_startprog) + push %ebp + mov %esp, %ebp + + mov 0xc(%ebp), %eax // argument to program + mov 0x8(%ebp), %ecx // entry offset + mov $0x28, %ebx // segment + push %ebx + push %ecx + + // set up %ds and %es + + mov $0x20, %ebx + movw %bx, %ds + movw %bx, %es + + lret +#endif + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// Returns the current stack pointer. +// +LABEL(__sp) + mov %esp, %eax + ret + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// Returns the current frame pointer. +// +LABEL(__bp) + mov %ebp, %eax + ret + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// switch_stack() +// +// Switches stack pointer between SS:SP and memory save_ss:save_sp. +// Call this function from real mode only!!! +// +// AX, DI, and SI are clobbered. +// +LABEL(__switch_stack) + popl %eax # save return address + popl %edi # discard upper 16-bit + + data32 + addr32 + movl OFFSET16(save_ss), %esi # new SS to SI + + data32 + addr32 + movl OFFSET16(save_sp), %edi # new SP to DI + + addr32 + mov %ss, OFFSET16(save_ss) # save current SS to memory + + data32 + addr32 + movl %esp, OFFSET16(save_sp) # save current SP to memory + + cli + mov %si, %ss # switch stack + mov %di, %sp + sti + + pushl %eax # push IP of caller onto the new stack + + xorl %eax, %eax + xorl %esi, %esi + xorl %edi, %edi + + ret + +#ifndef BOOT1 +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// loader() +// +// Issue a request to the network loader. +// +LABEL(_loader) + enter $0, $0 + pushal + + # + # Pass a far pointer to the command structure + # to the INT call through DX:CX. + # + # The command code is in BX. + # + + movw 8(%ebp), %bx # 8[EBP] = command code + movw 12(%ebp), %cx # 12[EBP] = command structure offset + movw 14(%ebp), %dx # 14[EBP] = command structure segment + + call __prot_to_real # Revert to real mode + + ###### Real Mode Begin ###### + + data32 + call __switch_stack # Switch to NBP stack + + int $0x2b # Call NBP + + data32 + call __switch_stack # Restore stack + + data32 + call __real_to_prot # Back to protected mode + + ###### Real Mode End ###### + + popal + leave + ret +#endif + +#if UNUSED +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// pcpy(src, dst, cnt) +// where src is a virtual address and dst is a physical address +// +LABEL(_pcpy) + push %ebp + mov %esp, %ebp + push %es + push %esi + push %edi + push %ecx + + cld + + // set %es to point at the flat segment + + mov $0x20, %eax + movw %ax , %es + + mov 0x8(%ebp), %esi // source + mov 0xc(%ebp), %edi // destination + mov 0x10(%ebp), %ecx // count + + rep + movsb + + pop %ecx + pop %edi + pop %esi + pop %es + pop %ebp + + ret +#endif Index: branches/Chimera/i386/libsaio/.svn/text-base/smbios.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/smbios.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/smbios.h.svn-base (revision 850) @@ -0,0 +1,456 @@ +/* + * Copyright (c) 1998-2009 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 1.1 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#ifndef __LIBSAIO_SMBIOS_H +#define __LIBSAIO_SMBIOS_H + +// +// Based on System Management BIOS Reference Specification v2.5 +// + +typedef uint8_t SMBString; +typedef uint8_t SMBByte; +typedef uint16_t SMBWord; +typedef uint32_t SMBDWord; +typedef uint64_t SMBQWord; + + +typedef struct DMIEntryPoint { + SMBByte anchor[5]; + SMBByte checksum; + SMBWord tableLength; + SMBDWord tableAddress; + SMBWord structureCount; + SMBByte bcdRevision; +} __attribute__((packed)) DMIEntryPoint; + +typedef struct SMBEntryPoint { + SMBByte anchor[4]; + SMBByte checksum; + SMBByte entryPointLength; + SMBByte majorVersion; + SMBByte minorVersion; + SMBWord maxStructureSize; + SMBByte entryPointRevision; + SMBByte formattedArea[5]; + DMIEntryPoint dmi; +} __attribute__((packed)) SMBEntryPoint; + +// +// Header common to all SMBIOS structures +// + +typedef struct SMBStructHeader { + SMBByte type; + SMBByte length; + SMBWord handle; +} __attribute__((packed)) SMBStructHeader; + +#define SMB_STRUCT_HEADER SMBStructHeader header; + +typedef struct SMBAnchor +{ + const SMBStructHeader * header; + const uint8_t * next; + const uint8_t * end; +} SMBAnchor; + +#define SMB_ANCHOR_IS_VALID(x) \ + ((x) && ((x)->header) && ((x)->next) && ((x)->end)) + +#define SMB_ANCHOR_RESET(x) \ + bzero(x, sizeof(typedef struct SMBAnchor)); + +// +// SMBIOS structure types. +// + +enum { + kSMBTypeBIOSInformation = 0, + kSMBTypeSystemInformation = 1, + kSMBTypeBaseBoard = 2, + kSMBTypeSystemEnclosure = 3, + kSMBTypeProcessorInformation = 4, + kSMBTypeMemoryModule = 6, + kSMBTypeCacheInformation = 7, + kSMBTypeSystemSlot = 9, + kSMBTypePhysicalMemoryArray = 16, + kSMBTypeMemoryDevice = 17, + kSMBType32BitMemoryErrorInfo = 18, + kSMBType64BitMemoryErrorInfo = 33, + + kSMBTypeEndOfTable = 127, + + /* Apple Specific Structures */ + kSMBTypeFirmwareVolume = 128, + kSMBTypeMemorySPD = 130, + kSMBTypeOemProcessorType = 131, + kSMBTypeOemProcessorBusSpeed = 132 +}; + +// +// BIOS Information (Type 0) +// +typedef struct SMBBIOSInformation { + SMB_STRUCT_HEADER // Type 0 + SMBString vendor; // BIOS vendor name + SMBString version; // BIOS version + SMBWord startSegment; // BIOS segment start + SMBString releaseDate; // BIOS release date + SMBByte romSize; // (n); 64K * (n+1) bytes + SMBQWord characteristics; // supported BIOS functions +} __attribute__((packed)) SMBBIOSInformation; + +// +// System Information (Type 1) +// + +typedef struct SMBSystemInformation { + // 2.0+ spec (8 bytes) + SMB_STRUCT_HEADER // Type 1 + SMBString manufacturer; + SMBString productName; + SMBString version; + SMBString serialNumber; + // 2.1+ spec (25 bytes) + SMBByte uuid[16]; // can be all 0 or all 1's + SMBByte wakeupReason; // reason for system wakeup + // 2.4+ spec (27 bytes) + SMBString skuNumber; + SMBString family; +} __attribute__((packed)) SMBSystemInformation; + +// +// Base Board (Type 2) +// + +typedef struct SMBBaseBoard { + SMB_STRUCT_HEADER // Type 2 + SMBString manufacturer; + SMBString product; + SMBString version; + SMBString serialNumber; + SMBString assetTagNumber; + SMBByte featureFlags; + SMBString locationInChassis; + SMBWord chassisHandle; + SMBByte boardType; + SMBByte numberOfContainedHandles; + // 0 - 255 contained handles go here but we do not include + // them in our structure. Be careful to use numberOfContainedHandles + // times sizeof(SMBWord) when computing the actual record size, + // if you need it. +} __attribute__((packed)) SMBBaseBoard; + +// Values for boardType in Type 2 records +enum { + kSMBBaseBoardUnknown = 0x01, + kSMBBaseBoardOther = 0x02, + kSMBBaseBoardServerBlade = 0x03, + kSMBBaseBoardConnectivitySwitch = 0x04, + kSMBBaseBoardSystemMgmtModule = 0x05, + kSMBBaseBoardProcessorModule = 0x06, + kSMBBaseBoardIOModule = 0x07, + kSMBBaseBoardMemoryModule = 0x08, + kSMBBaseBoardDaughter = 0x09, + kSMBBaseBoardMotherboard = 0x0A, + kSMBBaseBoardProcessorMemoryModule = 0x0B, + kSMBBaseBoardProcessorIOModule = 0x0C, + kSMBBaseBoardInterconnect = 0x0D, +}; + + +// +// System Enclosure (Type 3) +// + +typedef struct SMBSystemEnclosure { + SMB_STRUCT_HEADER // Type 3 + SMBString manufacturer; + SMBByte type; + SMBString version; + SMBString serialNumber; + SMBString assetTagNumber; + SMBByte bootupState; + SMBByte powerSupplyState; + SMBByte thermalState; + SMBByte securityStatus; + SMBDWord oemDefined; +} __attribute__((packed)) SMBSystemEnclosure; + +// +// Processor Information (Type 4) +// + +typedef struct SMBProcessorInformation { + // 2.0+ spec (26 bytes) + SMB_STRUCT_HEADER // Type 4 + SMBString socketDesignation; + SMBByte processorType; // CPU = 3 + SMBByte processorFamily; // processor family enum + SMBString manufacturer; + SMBQWord processorID; // based on CPUID + SMBString processorVersion; + SMBByte voltage; // bit7 cleared indicate legacy mode + SMBWord externalClock; // external clock in MHz + SMBWord maximumClock; // max internal clock in MHz + SMBWord currentClock; // current internal clock in MHz + SMBByte status; + SMBByte processorUpgrade; // processor upgrade enum + // 2.1+ spec (32 bytes) + SMBWord L1CacheHandle; + SMBWord L2CacheHandle; + SMBWord L3CacheHandle; + // 2.3+ spec (35 bytes) + SMBString serialNumber; + SMBString assetTag; + SMBString partNumber; +} __attribute__((packed)) SMBProcessorInformation; + +#define kSMBProcessorInformationMinSize 26 + +// +// Memory Module Information (Type 6) +// Obsoleted since SMBIOS version 2.1 +// + +typedef struct SMBMemoryModule { + SMB_STRUCT_HEADER // Type 6 + SMBString socketDesignation; + SMBByte bankConnections; + SMBByte currentSpeed; + SMBWord currentMemoryType; + SMBByte installedSize; + SMBByte enabledSize; + SMBByte errorStatus; +} __attribute__((packed)) SMBMemoryModule; + +#define kSMBMemoryModuleSizeNotDeterminable 0x7D +#define kSMBMemoryModuleSizeNotEnabled 0x7E +#define kSMBMemoryModuleSizeNotInstalled 0x7F + +// +// Cache Information (Type 7) +// + +typedef struct SMBCacheInformation { + SMB_STRUCT_HEADER // Type 7 + SMBString socketDesignation; + SMBWord cacheConfiguration; + SMBWord maximumCacheSize; + SMBWord installedSize; + SMBWord supportedSRAMType; + SMBWord currentSRAMType; + SMBByte cacheSpeed; + SMBByte errorCorrectionType; + SMBByte systemCacheType; + SMBByte associativity; +} __attribute__((packed)) SMBCacheInformation; + +typedef struct SMBSystemSlot { + // 2.0+ spec (12 bytes) + SMB_STRUCT_HEADER // Type 9 + SMBString slotDesignation; + SMBByte slotType; + SMBByte slotDataBusWidth; + SMBByte currentUsage; + SMBByte slotLength; + SMBWord slotID; + SMBByte slotCharacteristics1; + // 2.1+ spec (13 bytes) + SMBByte slotCharacteristics2; +} __attribute__((packed)) SMBSystemSlot; + +// +// Physical Memory Array (Type 16) +// + +typedef struct SMBPhysicalMemoryArray { + // 2.1+ spec (15 bytes) + SMB_STRUCT_HEADER // Type 16 + SMBByte physicalLocation; // physical location + SMBByte arrayUse; // the use for the memory array + SMBByte errorCorrection; // error correction/detection method + SMBDWord maximumCapacity; // maximum memory capacity in kilobytes + SMBWord errorHandle; // handle of a previously detected error + SMBWord numMemoryDevices; // number of memory slots or sockets +} __attribute__((packed)) SMBPhysicalMemoryArray; + +// Memory Array - Use +enum { + kSMBMemoryArrayUseOther = 0x01, + kSMBMemoryArrayUseUnknown = 0x02, + kSMBMemoryArrayUseSystemMemory = 0x03, + kSMBMemoryArrayUseVideoMemory = 0x04, + kSMBMemoryArrayUseFlashMemory = 0x05, + kSMBMemoryArrayUseNonVolatileMemory = 0x06, + kSMBMemoryArrayUseCacheMemory = 0x07 +}; + +// Memory Array - Error Correction Types +enum { + kSMBMemoryArrayErrorCorrectionTypeOther = 0x01, + kSMBMemoryArrayErrorCorrectionTypeUnknown = 0x02, + kSMBMemoryArrayErrorCorrectionTypeNone = 0x03, + kSMBMemoryArrayErrorCorrectionTypeParity = 0x04, + kSMBMemoryArrayErrorCorrectionTypeSingleBitECC = 0x05, + kSMBMemoryArrayErrorCorrectionTypeMultiBitECC = 0x06, + kSMBMemoryArrayErrorCorrectionTypeCRC = 0x07 +}; + +// +// Memory Device (Type 17) +// + +typedef struct SMBMemoryDevice { + // 2.1+ spec (21 bytes) + SMB_STRUCT_HEADER // Type 17 + SMBWord arrayHandle; // handle of the parent memory array + SMBWord errorHandle; // handle of a previously detected error + SMBWord totalWidth; // total width in bits; including ECC bits + SMBWord dataWidth; // data width in bits + SMBWord memorySize; // bit15 is scale, 0 = MB, 1 = KB + SMBByte formFactor; // memory device form factor + SMBByte deviceSet; // parent set of identical memory devices + SMBString deviceLocator; // labeled socket; e.g. "SIMM 3" + SMBString bankLocator; // labeled bank; e.g. "Bank 0" or "A" + SMBByte memoryType; // type of memory + SMBWord memoryTypeDetail; // additional detail on memory type + // 2.3+ spec (27 bytes) + SMBWord memorySpeed; // speed of device in MHz (0 for unknown) + SMBString manufacturer; + SMBString serialNumber; + SMBString assetTag; + SMBString partNumber; +} __attribute__((packed)) SMBMemoryDevice; + +// +// Firmware Volume Description (Apple Specific - Type 128) +// + +enum { + FW_REGION_RESERVED = 0, + FW_REGION_RECOVERY = 1, + FW_REGION_MAIN = 2, + FW_REGION_NVRAM = 3, + FW_REGION_CONFIG = 4, + FW_REGION_DIAGVAULT = 5, + + NUM_FLASHMAP_ENTRIES = 8 +}; + +typedef struct FW_REGION_INFO +{ + SMBDWord StartAddress; + SMBDWord EndAddress; +} __attribute__((packed)) FW_REGION_INFO; + +typedef struct SMBFirmwareVolume { + SMB_STRUCT_HEADER // Type 128 + SMBByte RegionCount; + SMBByte Reserved[3]; + SMBDWord FirmwareFeatures; + SMBDWord FirmwareFeaturesMask; + SMBByte RegionType[ NUM_FLASHMAP_ENTRIES ]; + FW_REGION_INFO FlashMap[ NUM_FLASHMAP_ENTRIES ]; +} __attribute__((packed)) SMBFirmwareVolume; + +// +// Memory SPD Data (Apple Specific - Type 130) +// + +typedef struct SMBMemorySPD { + SMB_STRUCT_HEADER // Type 130 + SMBWord Type17Handle; + SMBWord Offset; + SMBWord Size; + SMBWord Data[]; +} __attribute__((packed)) SMBMemorySPD; + +static const char * +SMBMemoryDeviceTypes[] = +{ + "RAM", /* 00h Undefined */ + "RAM", /* 01h Other */ + "RAM", /* 02h Unknown */ + "DRAM", /* 03h DRAM */ + "EDRAM", /* 04h EDRAM */ + "VRAM", /* 05h VRAM */ + "SRAM", /* 06h SRAM */ + "RAM", /* 07h RAM */ + "ROM", /* 08h ROM */ + "FLASH", /* 09h FLASH */ + "EEPROM", /* 0Ah EEPROM */ + "FEPROM", /* 0Bh FEPROM */ + "EPROM", /* 0Ch EPROM */ + "CDRAM", /* 0Dh CDRAM */ + "3DRAM", /* 0Eh 3DRAM */ + "SDRAM", /* 0Fh SDRAM */ + "SGRAM", /* 10h SGRAM */ + "RDRAM", /* 11h RDRAM */ + "DDR SDRAM", /* 12h DDR */ + "DDR2 SDRAM", /* 13h DDR2 */ + "DDR2 FB-DIMM", /* 14h DDR2 FB-DIMM */ + "RAM", /* 15h unused */ + "RAM", /* 16h unused */ + "RAM", /* 17h unused */ + "DDR3", /* 18h DDR3, chosen in [5776134] */ +}; + +static const int +kSMBMemoryDeviceTypeCount = sizeof(SMBMemoryDeviceTypes) / + sizeof(SMBMemoryDeviceTypes[0]); + +// +// OEM Processor Type (Apple Specific - Type 131) +// + +typedef struct SMBOemProcessorType { + SMB_STRUCT_HEADER + SMBWord ProcessorType; +} __attribute__((packed)) SMBOemProcessorType; + +// +// OEM Processor Bus Speed (Apple Specific - Type 132) +// +typedef struct SMBOemProcessorBusSpeed { + SMB_STRUCT_HEADER + SMBWord ProcessorBusSpeed; // MT/s unit +} __attribute__((packed)) SMBOemProcessorBusSpeed; + +//---------------------------------------------------------------------------------------------------------- + +/* From Foundation/Efi/Guid/Smbios/SmBios.h */ +/* Modified to wrap Data4 array init with {} */ +#define EFI_SMBIOS_TABLE_GUID {0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} + +#define SMBIOS_ORIGINAL 0 +#define SMBIOS_PATCHED 1 + +extern void *getSmbios(int which); +extern void readSMBIOSInfo(SMBEntryPoint *eps); +extern void setupSMBIOSTable(void); + +extern void decodeSMBIOSTable(SMBEntryPoint *eps); + + +#endif /* !__LIBSAIO_SMBIOS_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/hpet.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/hpet.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/hpet.h.svn-base (revision 850) @@ -0,0 +1,20 @@ +/* + * + */ + +#ifndef __LIBSAIO_HPET_H +#define __LIBSAIO_HPET_H + +#include "libsaio.h" + +#define REG32(base, reg) ((volatile uint32_t *)base)[(reg) >> 2] + +void force_enable_hpet(pci_dt_t *lpc_dev); + +struct lpc_controller_t { + unsigned vendor; + unsigned device; + char *name; +}; + +#endif /* !__LIBSAIO_HPET_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/nbp_cmd.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/nbp_cmd.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/nbp_cmd.h.svn-base (revision 850) @@ -0,0 +1,85 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#ifndef __LIBSAIO_NBP_CMD_H +#define __LIBSAIO_NBP_CMD_H + +#include + +/*========================================================================== + * NBP return status codes. + */ +typedef enum { + nbpStatusSuccess = 0, + nbpStatusFailed, + nbpStatusInvalid, +} nbpStatus_t; + +/*========================================================================== + * NBP commands codes. + */ +typedef enum { + nbpCommandTFTPReadFile = 1, + nbpCommandTFTPGetFileSize, + nbpCommandUnloadBaseCode, +} nbpCommandCode_t; + +/*========================================================================== + * NBP commands. + */ +typedef struct { + UInt32 status; /* return code from NBP */ +} nbpCommandHeader_s; + +typedef struct { + UInt32 status; /* return code from NBP */ + UInt8 filename[128]; /* name of file to be downloaded */ + UInt32 bufferSize; /* size of the download buffer */ + UInt32 buffer; /* physical address of the download buffer */ +} nbpCommandTFTPReadFile_s; + +typedef struct { + UInt32 status; /* return code from NBP */ + UInt8 filename[128]; /* name of file to be downloaded */ + UInt32 filesize; /* size of the file specified */ +} nbpCommandTFTPGetFileSize_s; + +typedef struct { + UInt32 status; /* return code from NBP */ + UInt8 sname[64]; /* server name */ + UInt32 CIP; /* client IP address */ + UInt32 SIP; /* server IP address */ + UInt32 GIP; /* gateway IP address */ +} nbpCommandGetNetworkInfo_s; + +/*========================================================================== + * An union of all NBP command structures. + */ +typedef union { + nbpCommandHeader_s header; + nbpCommandTFTPReadFile_s tftpReadFile; + nbpCommandTFTPGetFileSize_s tftpFileSize; +} nbpCommand_u; + +#endif /* !__LIBSAIO_NBP_CMD_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/efi.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/efi.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/efi.h.svn-base (revision 850) @@ -0,0 +1,558 @@ +/* + * Copyright (c) 2005 Apple Computer, Inc. All rights reserved. + * + * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ + * + * This file contains Original Code and/or Modifications of Original Code + * as defined in and that are subject to the Apple Public Source License + * Version 2.0 (the 'License'). You may not use this file except in + * compliance with the License. The rights granted to you under the License + * may not be used to create, or enable the creation or redistribution of, + * unlawful or unlicensed copies of an Apple operating system, or to + * circumvent, violate, or enable the circumvention or violation of, any + * terms of an Apple operating system software license agreement. + * + * Please obtain a copy of the License at + * http://www.opensource.apple.com/apsl/ and read it before using this file. + * + * The Original Code and all software distributed under the License are + * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. + * Please see the License for the specific language governing rights and + * limitations under the License. + * + * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ + */ + +#ifndef _PEXPERT_I386_EFI_H +#define _PEXPERT_I386_EFI_H + +#include + +typedef uint8_t EFI_UINT8; +typedef uint16_t EFI_UINT16; +typedef uint32_t EFI_UINT32; +typedef uint64_t EFI_UINT64; + +typedef uint32_t EFI_UINTN; /* natural size for firmware, not kernel */ + +typedef int8_t EFI_INT8; +typedef int16_t EFI_INT16; +typedef int32_t EFI_INT32; +typedef int64_t EFI_INT64; + +typedef int8_t EFI_CHAR8; +typedef int16_t EFI_CHAR16; +typedef int32_t EFI_CHAR32; +typedef int64_t EFI_CHAR64; + +typedef uint32_t EFI_STATUS; +typedef uint8_t EFI_BOOLEAN; +typedef void VOID; + +typedef uint32_t EFI_PTR32; +typedef uint32_t EFI_HANDLE32; + +typedef uint64_t EFI_PTR64; +typedef uint64_t EFI_HANDLE64; +/* + +Portions Copyright 2004, Intel Corporation +All rights reserved. This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +*/ + + +// +// Modifiers for EFI Runtime and Boot Services +// +#define EFI_RUNTIMESERVICE +#define EFIAPI +#define IN +#define OUT +#define OPTIONAL + +#define EFI_MAX_BIT 0x80000000 + +// +// Set the upper bit to indicate EFI Error. +// +#define EFIERR(a) (EFI_MAX_BIT | (a)) + +#define EFIWARN(a) (a) +#define EFI_ERROR(a) (((INTN) (a)) < 0) + +#define EFI_SUCCESS 0 +#define EFI_LOAD_ERROR EFIERR (1) +#define EFI_INVALID_PARAMETER EFIERR (2) +#define EFI_UNSUPPORTED EFIERR (3) +#define EFI_BAD_BUFFER_SIZE EFIERR (4) +#define EFI_BUFFER_TOO_SMALL EFIERR (5) +#define EFI_NOT_READY EFIERR (6) +#define EFI_DEVICE_ERROR EFIERR (7) +#define EFI_WRITE_PROTECTED EFIERR (8) +#define EFI_OUT_OF_RESOURCES EFIERR (9) +#define EFI_VOLUME_CORRUPTED EFIERR (10) +#define EFI_VOLUME_FULL EFIERR (11) +#define EFI_NO_MEDIA EFIERR (12) +#define EFI_MEDIA_CHANGED EFIERR (13) +#define EFI_NOT_FOUND EFIERR (14) +#define EFI_ACCESS_DENIED EFIERR (15) +#define EFI_NO_RESPONSE EFIERR (16) +#define EFI_NO_MAPPING EFIERR (17) +#define EFI_TIMEOUT EFIERR (18) +#define EFI_NOT_STARTED EFIERR (19) +#define EFI_ALREADY_STARTED EFIERR (20) +#define EFI_ABORTED EFIERR (21) +#define EFI_ICMP_ERROR EFIERR (22) +#define EFI_TFTP_ERROR EFIERR (23) +#define EFI_PROTOCOL_ERROR EFIERR (24) +#define EFI_INCOMPATIBLE_VERSION EFIERR (25) +#define EFI_SECURITY_VIOLATION EFIERR (26) +#define EFI_CRC_ERROR EFIERR (27) + +#define EFI_WARN_UNKNOWN_GLYPH EFIWARN (1) +#define EFI_WARN_DELETE_FAILURE EFIWARN (2) +#define EFI_WARN_WRITE_FAILURE EFIWARN (3) +#define EFI_WARN_BUFFER_TOO_SMALL EFIWARN (4) + +// +// EFI Specification Revision information +// +#define EFI_SPECIFICATION_MAJOR_REVISION 1 +#define EFI_SPECIFICATION_MINOR_REVISION 10 + +typedef struct { + EFI_UINT32 Data1; + EFI_UINT16 Data2; + EFI_UINT16 Data3; + EFI_UINT8 Data4[8]; +} EFI_GUID; + +#define APPLE_VENDOR_GUID \ + {0xAC39C713, 0x7E50, 0x423D, {0x88, 0x9D, 0x27,0x8F, 0xCC, 0x34, 0x22, 0xB6} } + +#define EFI_GLOBAL_VARIABLE_GUID \ + {0x8BE4DF61, 0x93CA, 0x11d2, {0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C} } + +typedef union { + EFI_GUID Guid; + EFI_UINT8 Raw[16]; +} EFI_GUID_UNION; + +// +// EFI Time Abstraction: +// Year: 2000 - 20XX +// Month: 1 - 12 +// Day: 1 - 31 +// Hour: 0 - 23 +// Minute: 0 - 59 +// Second: 0 - 59 +// Nanosecond: 0 - 999,999,999 +// TimeZone: -1440 to 1440 or 2047 +// +typedef struct { + EFI_UINT16 Year; + EFI_UINT8 Month; + EFI_UINT8 Day; + EFI_UINT8 Hour; + EFI_UINT8 Minute; + EFI_UINT8 Second; + EFI_UINT8 Pad1; + EFI_UINT32 Nanosecond; + EFI_INT16 TimeZone; + EFI_UINT8 Daylight; + EFI_UINT8 Pad2; +} EFI_TIME; + +// +// Bit definitions for EFI_TIME.Daylight +// +#define EFI_TIME_ADJUST_DAYLIGHT 0x01 +#define EFI_TIME_IN_DAYLIGHT 0x02 + +// +// Value definition for EFI_TIME.TimeZone +// +#define EFI_UNSPECIFIED_TIMEZONE 0x07FF + +typedef enum { + EfiReservedMemoryType, + EfiLoaderCode, + EfiLoaderData, + EfiBootServicesCode, + EfiBootServicesData, + EfiRuntimeServicesCode, + EfiRuntimeServicesData, + EfiConventionalMemory, + EfiUnusableMemory, + EfiACPIReclaimMemory, + EfiACPIMemoryNVS, + EfiMemoryMappedIO, + EfiMemoryMappedIOPortSpace, + EfiPalCode, + EfiMaxMemoryType +} EFI_MEMORY_TYPE; + +typedef struct { + EFI_UINT64 Signature; + EFI_UINT32 Revision; + EFI_UINT32 HeaderSize; + EFI_UINT32 CRC32; + EFI_UINT32 Reserved; +} __attribute__((aligned(8))) EFI_TABLE_HEADER; + +// +// possible caching types for the memory range +// +#define EFI_MEMORY_UC 0x0000000000000001ULL +#define EFI_MEMORY_WC 0x0000000000000002ULL +#define EFI_MEMORY_WT 0x0000000000000004ULL +#define EFI_MEMORY_WB 0x0000000000000008ULL +#define EFI_MEMORY_UCE 0x0000000000000010ULL + +// +// physical memory protection on range +// +#define EFI_MEMORY_WP 0x0000000000001000ULL +#define EFI_MEMORY_RP 0x0000000000002000ULL +#define EFI_MEMORY_XP 0x0000000000004000ULL + +// +// range requires a runtime mapping +// +#define EFI_MEMORY_RUNTIME 0x8000000000000000ULL + +typedef EFI_UINT64 EFI_PHYSICAL_ADDRESS; +typedef EFI_UINT64 EFI_VIRTUAL_ADDRESS; + +#define EFI_MEMORY_DESCRIPTOR_VERSION 1 +typedef struct { + EFI_UINT32 Type; + EFI_UINT32 Pad; + EFI_PHYSICAL_ADDRESS PhysicalStart; + EFI_VIRTUAL_ADDRESS VirtualStart; + EFI_UINT64 NumberOfPages; + EFI_UINT64 Attribute; +} __attribute__((aligned(8))) EFI_MEMORY_DESCRIPTOR; + + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_SET_VIRTUAL_ADDRESS_MAP) ( + IN EFI_UINTN MemoryMapSize, + IN EFI_UINTN DescriptorSize, + IN EFI_UINT32 DescriptorVersion, + IN EFI_MEMORY_DESCRIPTOR * VirtualMap + ) __attribute__((regparm(0))); + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_CONVERT_POINTER) ( + IN EFI_UINTN DebugDisposition, + IN OUT VOID **Address + ) __attribute__((regparm(0))); + +// +// Variable attributes +// +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +#define EFI_VARIABLE_READ_ONLY 0x00000008 + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_GET_VARIABLE) ( + IN EFI_CHAR16 * VariableName, + IN EFI_GUID * VendorGuid, + OUT EFI_UINT32 * Attributes OPTIONAL, + IN OUT EFI_UINTN * DataSize, + OUT VOID * Data + ) __attribute__((regparm(0))); + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_GET_NEXT_VARIABLE_NAME) ( + IN OUT EFI_UINTN * VariableNameSize, + IN OUT EFI_CHAR16 * VariableName, + IN OUT EFI_GUID * VendorGuid + ) __attribute__((regparm(0))); + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_SET_VARIABLE) ( + IN EFI_CHAR16 * VariableName, + IN EFI_GUID * VendorGuid, + IN EFI_UINT32 Attributes, + IN EFI_UINTN DataSize, + IN VOID * Data + ) __attribute__((regparm(0))); + +// +// EFI Time +// +typedef struct { + EFI_UINT32 Resolution; + EFI_UINT32 Accuracy; + EFI_BOOLEAN SetsToZero; +} __attribute__((aligned(4))) EFI_TIME_CAPABILITIES; + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_GET_TIME) ( + OUT EFI_TIME * Time, + OUT EFI_TIME_CAPABILITIES * Capabilities OPTIONAL + ) __attribute__((regparm(0))); + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_SET_TIME) ( + IN EFI_TIME * Time + ) __attribute__((regparm(0))); + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_GET_WAKEUP_TIME) ( + OUT EFI_BOOLEAN * Enabled, + OUT EFI_BOOLEAN * Pending, + OUT EFI_TIME * Time + ) __attribute__((regparm(0))); + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_SET_WAKEUP_TIME) ( + IN EFI_BOOLEAN Enable, + IN EFI_TIME * Time OPTIONAL + ) __attribute((regparm(0))); + +typedef enum { + EfiResetCold, + EfiResetWarm, + EfiResetShutdown, + +#ifdef TIANO_EXTENSION_FLAG + EfiResetUpdate +#endif + +} EFI_RESET_TYPE; + +typedef +EFI_RUNTIMESERVICE +VOID +(EFIAPI *EFI_RESET_SYSTEM) ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN EFI_UINTN DataSize, + IN EFI_CHAR16 * ResetData OPTIONAL + ) __attribute__((regparm(0))); + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_GET_NEXT_HIGH_MONO_COUNT) ( + OUT EFI_UINT32 * HighCount + ) __attribute__((regparm(0))); + +// +// Definition of Status Code extended data header +// +// HeaderSize The size of the architecture. This is specified to enable +// the future expansion +// +// Size The size of the data in bytes. This does not include the size +// of the header structure. +// +// Type A GUID defining the type of the data +// +// +#ifdef TIANO_EXTENSION_FLAG + +typedef +EFI_RUNTIMESERVICE +EFI_STATUS +(EFIAPI *EFI_REPORT_STATUS_CODE) ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN EFI_UINT32 Instance, + IN EFI_GUID * CallerId OPTIONAL, + IN EFI_STATUS_CODE_DATA * Data OPTIONAL + ) __attribute__((regparm(0))); + +#endif +// +// EFI Runtime Services Table +// +#define EFI_RUNTIME_SERVICES_SIGNATURE 0x56524553544e5552ULL +#define EFI_RUNTIME_SERVICES_REVISION ((EFI_SPECIFICATION_MAJOR_REVISION << 16) | (EFI_SPECIFICATION_MINOR_REVISION)) + +typedef struct { + EFI_TABLE_HEADER Hdr; + + // + // Time services + // + EFI_PTR32 GetTime; + EFI_PTR32 SetTime; + EFI_PTR32 GetWakeupTime; + EFI_PTR32 SetWakeupTime; + + // + // Virtual memory services + // + EFI_PTR32 SetVirtualAddressMap; + EFI_PTR32 ConvertPointer; + + // + // Variable services + // + EFI_PTR32 GetVariable; + EFI_PTR32 GetNextVariableName; + EFI_PTR32 SetVariable; + + // + // Misc + // + EFI_PTR32 GetNextHighMonotonicCount; + EFI_PTR32 ResetSystem; + +#ifdef TIANO_EXTENSION_FLAG + // + // //////////////////////////////////////////////////// + // Extended EFI Services + ////////////////////////////////////////////////////// + // + EFI_PTR32 ReportStatusCode; +#endif + +} __attribute__((aligned(8))) EFI_RUNTIME_SERVICES_32; + +typedef struct { + EFI_TABLE_HEADER Hdr; + + // + // Time services + // + EFI_PTR64 GetTime; + EFI_PTR64 SetTime; + EFI_PTR64 GetWakeupTime; + EFI_PTR64 SetWakeupTime; + + // + // Virtual memory services + // + EFI_PTR64 SetVirtualAddressMap; + EFI_PTR64 ConvertPointer; + + // + // Variable services + // + EFI_PTR64 GetVariable; + EFI_PTR64 GetNextVariableName; + EFI_PTR64 SetVariable; + + // + // Misc + // + EFI_PTR64 GetNextHighMonotonicCount; + EFI_PTR64 ResetSystem; + +#ifdef TIANO_EXTENSION_FLAG + // + // //////////////////////////////////////////////////// + // Extended EFI Services + ////////////////////////////////////////////////////// + // + EFI_PTR64 ReportStatusCode; +#endif + +} __attribute__((aligned(8))) EFI_RUNTIME_SERVICES_64; + +// +// EFI Configuration Table +// +typedef struct { + EFI_GUID VendorGuid; + EFI_PTR32 VendorTable; +} EFI_CONFIGURATION_TABLE_32; + +typedef struct { + EFI_GUID VendorGuid; + EFI_PTR64 VendorTable; +} __attribute__((aligned(8))) EFI_CONFIGURATION_TABLE_64; + +// +// EFI System Table +// +#define EFI_SYSTEM_TABLE_SIGNATURE 0x5453595320494249ULL +#define EFI_SYSTEM_TABLE_REVISION ((EFI_SPECIFICATION_MAJOR_REVISION << 16) | (EFI_SPECIFICATION_MINOR_REVISION)) +#define EFI_2_00_SYSTEM_TABLE_REVISION ((2 << 16) | 00) +#define EFI_1_02_SYSTEM_TABLE_REVISION ((1 << 16) | 02) +#define EFI_1_10_SYSTEM_TABLE_REVISION ((1 << 16) | 10) + +typedef struct EFI_SYSTEM_TABLE_32 { + EFI_TABLE_HEADER Hdr; + + EFI_PTR32 FirmwareVendor; + EFI_UINT32 FirmwareRevision; + + EFI_HANDLE32 ConsoleInHandle; + EFI_PTR32 ConIn; + + EFI_HANDLE32 ConsoleOutHandle; + EFI_PTR32 ConOut; + + EFI_HANDLE32 StandardErrorHandle; + EFI_PTR32 StdErr; + + EFI_PTR32 RuntimeServices; + EFI_PTR32 BootServices; + + EFI_UINT32 NumberOfTableEntries; + EFI_PTR32 ConfigurationTable; + +} __attribute__((aligned(8))) EFI_SYSTEM_TABLE_32; + +typedef struct EFI_SYSTEM_TABLE_64 { + EFI_TABLE_HEADER Hdr; + + EFI_PTR64 FirmwareVendor; + EFI_UINT32 FirmwareRevision; + + EFI_UINT32 __pad; + + EFI_HANDLE64 ConsoleInHandle; + EFI_PTR64 ConIn; + + EFI_HANDLE64 ConsoleOutHandle; + EFI_PTR64 ConOut; + + EFI_HANDLE64 StandardErrorHandle; + EFI_PTR64 StdErr; + + EFI_PTR64 RuntimeServices; + EFI_PTR64 BootServices; + + EFI_UINT64 NumberOfTableEntries; + EFI_PTR64 ConfigurationTable; + +} __attribute__((aligned(8))) EFI_SYSTEM_TABLE_64; + +#endif /* _PEXPERT_I386_EFI_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/bootstruct.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/bootstruct.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/bootstruct.c.svn-base (revision 850) @@ -0,0 +1,215 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright 1993 NeXT, Inc. + * All rights reserved. + */ + +#include "libsaio.h" +#include "bootstruct.h" + +/*========================================================================== + * Initialize the structure of parameters passed to + * the kernel by the booter. + */ + +boot_args *bootArgs; +boot_args_pre_lion *bootArgsPreLion; +PrivateBootInfo_t *bootInfo; +Node *gMemoryMapNode; + +static char platformName[64]; + +void initKernBootStruct( void ) +{ + Node *node; + int nameLen; + static int init_done = 0; + + if ( !init_done ) + { + bootArgs = (boot_args *)malloc(sizeof(boot_args)); + bootArgsPreLion = (boot_args_pre_lion *)malloc(sizeof(boot_args_pre_lion)); + bootInfo = (PrivateBootInfo_t *)malloc(sizeof(PrivateBootInfo_t)); + if (bootArgs == 0 || bootInfo == 0) + stop("Couldn't allocate boot info\n"); + + bzero(bootArgs, sizeof(boot_args)); + bzero(bootArgsPreLion, sizeof(boot_args_pre_lion)); + bzero(bootInfo, sizeof(PrivateBootInfo_t)); + + // Get system memory map. Also update the size of the + // conventional/extended memory for backwards compatibility. + + bootInfo->memoryMapCount = + getMemoryMap( bootInfo->memoryMap, kMemoryMapCountMax, + (unsigned long *) &bootInfo->convmem, + (unsigned long *) &bootInfo->extmem ); + + if ( bootInfo->memoryMapCount == 0 ) + { + // BIOS did not provide a memory map, systems with + // discontiguous memory or unusual memory hole locations + // may have problems. + + bootInfo->convmem = getConventionalMemorySize(); + bootInfo->extmem = getExtendedMemorySize(); + } + + bootInfo->configEnd = bootInfo->config; + bootArgs->Video.v_display = VGA_TEXT_MODE; + + DT__Initialize(); + + node = DT__FindNode("/", true); + if (node == 0) { + stop("Couldn't create root node"); + } + getPlatformName(platformName); + nameLen = strlen(platformName) + 1; + DT__AddProperty(node, "compatible", nameLen, platformName); + DT__AddProperty(node, "model", nameLen, platformName); + + gMemoryMapNode = DT__FindNode("/chosen/memory-map", true); + + bootArgs->Version = kBootArgsVersion; + bootArgs->Revision = kBootArgsRevision; + + bootArgsPreLion->Version = kBootArgsPreLionVersion; + bootArgsPreLion->Revision = kBootArgsPreLionRevision; + + init_done = 1; + } + +} + + +/* Copy boot args after kernel and record address. */ + +void +reserveKernBootStruct(void) +{ + if ((gMacOSVersion[0] == '1') && (gMacOSVersion[1] == '0') && (gMacOSVersion[2] == '.') && (gMacOSVersion[3] == '7')) + { + void *oldAddr = bootArgs; + bootArgs = (boot_args *)AllocateKernelMemory(sizeof(boot_args)); + bcopy(oldAddr, bootArgs, sizeof(boot_args)); + } + else { + void *oldAddr = bootArgsPreLion; + bootArgsPreLion = (boot_args_pre_lion *)AllocateKernelMemory(sizeof(boot_args_pre_lion)); + bcopy(oldAddr, bootArgsPreLion, sizeof(boot_args_pre_lion)); + } + +} + +void +finalizeBootStruct(void) +{ + uint32_t size; + void *addr; + int i; + EfiMemoryRange *memoryMap; + MemoryRange *range; + int memoryMapCount = bootInfo->memoryMapCount; + + if (memoryMapCount == 0) { + // XXX could make a two-part map here + stop("Unable to convert memory map into proper format\n"); + } + + // convert memory map to boot_args memory map + memoryMap = (EfiMemoryRange *)AllocateKernelMemory(sizeof(EfiMemoryRange) * memoryMapCount); + bootArgs->MemoryMap = (uint32_t)memoryMap; + bootArgs->MemoryMapSize = sizeof(EfiMemoryRange) * memoryMapCount; + bootArgs->MemoryMapDescriptorSize = sizeof(EfiMemoryRange); + bootArgs->MemoryMapDescriptorVersion = 0; + + for (i=0; imemoryMap[i]; + switch(range->type) { + case kMemoryRangeACPI: + memoryMap->Type = kEfiACPIReclaimMemory; + break; + case kMemoryRangeNVS: + memoryMap->Type = kEfiACPIMemoryNVS; + break; + case kMemoryRangeUsable: + memoryMap->Type = kEfiConventionalMemory; + break; + case kMemoryRangeReserved: + default: + memoryMap->Type = kEfiReservedMemoryType; + break; + } + memoryMap->PhysicalStart = range->base; + memoryMap->VirtualStart = range->base; + memoryMap->NumberOfPages = range->length >> I386_PGSHIFT; + memoryMap->Attribute = 0; + } + + // copy bootFile into device tree + // XXX + + // add PCI info somehow into device tree + // XXX + + // Flatten device tree + DT__FlattenDeviceTree(0, &size); + addr = (void *)AllocateKernelMemory(size); + if (addr == 0) { + stop("Couldn't allocate device tree\n"); + } + + DT__FlattenDeviceTree((void **)&addr, &size); + bootArgs->deviceTreeP = (uint32_t)addr; + bootArgs->deviceTreeLength = size; + + // Copy BootArgs values to older structure + + memcpy(&bootArgsPreLion->CommandLine, &bootArgs->CommandLine, BOOT_LINE_LENGTH); + memcpy(&bootArgsPreLion->Video, &bootArgs->Video, sizeof(Boot_Video)); + + bootArgsPreLion->MemoryMap = bootArgs->MemoryMap; + bootArgsPreLion->MemoryMapSize = bootArgs->MemoryMapSize; + bootArgsPreLion->MemoryMapDescriptorSize = bootArgs->MemoryMapDescriptorSize; + bootArgsPreLion->MemoryMapDescriptorVersion = bootArgs->MemoryMapDescriptorVersion; + + bootArgsPreLion->deviceTreeP = bootArgs->deviceTreeP; + bootArgsPreLion->deviceTreeLength = bootArgs->deviceTreeLength; + + bootArgsPreLion->kaddr = bootArgs->kaddr; + bootArgsPreLion->ksize = bootArgs->ksize; + + bootArgsPreLion->efiRuntimeServicesPageStart = bootArgs->efiRuntimeServicesPageStart; + bootArgsPreLion->efiRuntimeServicesPageCount = bootArgs->efiRuntimeServicesPageCount; + bootArgsPreLion->efiSystemTable = bootArgs->efiSystemTable; + + bootArgsPreLion->efiMode = bootArgs->efiMode; + + bootArgsPreLion->performanceDataStart = bootArgs->performanceDataStart; + bootArgsPreLion->performanceDataSize = bootArgs->performanceDataSize; + bootArgsPreLion->efiRuntimeServicesVirtualPageStart = bootArgs->efiRuntimeServicesVirtualPageStart; + +} Index: branches/Chimera/i386/libsaio/.svn/text-base/ntfs.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ntfs.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ntfs.c.svn-base (revision 850) @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2004 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Copyright (c) 1999-2004 Apple Computer, Inc. All Rights Reserved. + * + * This file contains Original Code and/or Modifications of Original Code + * as defined in and that are subject to the Apple Public Source License + * Version 2.0 (the 'License'). You may not use this file except in + * compliance with the License. Please obtain a copy of the License at + * http://www.opensource.apple.com/apsl/ and read it before using this + * file. + * + * The Original Code and all software distributed under the License are + * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. + * Please see the License for the specific language governing rights and + * limitations under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#include "libsaio.h" +#include "sl.h" + +#define BYTE_ORDER_MARK 0xFEFF + +#include "ntfs_private.h" + +#define FS_TYPE "ntfs" +#define FS_NAME_FILE "NTFS" + +#define MAX_BLOCK_SIZE 2048 +#define MAX_CLUSTER_SIZE 32768 + +#define LABEL_LENGTH 1024 +#define UNKNOWN_LABEL "Untitled NTFS" + +#define FSUR_IO_FAIL -1 +#define FSUR_UNRECOGNIZED -1 +#define FSUR_RECOGNIZED 0 + +#define ERROR -1 + +/* + * Process per-sector "fixups" that NTFS uses to detect corruption of + * multi-sector data structures, like MFT records. + */ +static int +ntfs_fixup( + char *buf, + size_t len, + u_int32_t magic, + u_int32_t bytesPerSector) +{ + struct fixuphdr *fhp = (struct fixuphdr *) buf; + int i; + u_int16_t fixup; + u_int16_t *fxp; + u_int16_t *cfxp; + u_int32_t fixup_magic; + u_int16_t fixup_count; + u_int16_t fixup_offset; + + fixup_magic = OSReadLittleInt32(&fhp->fh_magic,0); + if (fixup_magic != magic) { + error("ntfs_fixup: magic doesn't match: %08x != %08x\n", + fixup_magic, magic); + return (ERROR); + } + fixup_count = OSReadLittleInt16(&fhp->fh_fnum,0); + if ((fixup_count - 1) * bytesPerSector != len) { + error("ntfs_fixup: " \ + "bad fixups number: %d for %ld bytes block\n", + fixup_count, (long)len); /* XXX printf kludge */ + return (ERROR); + } + fixup_offset = OSReadLittleInt16(&fhp->fh_foff,0); + if (fixup_offset >= len) { + error("ntfs_fixup: invalid offset: %x", fixup_offset); + return (ERROR); + } + fxp = (u_int16_t *) (buf + fixup_offset); + cfxp = (u_int16_t *) (buf + bytesPerSector - 2); + fixup = *fxp++; + for (i = 1; i < fixup_count; i++, fxp++) { + if (*cfxp != fixup) { + error("ntfs_fixup: fixup %d doesn't match\n", i); + return (ERROR); + } + *cfxp = *fxp; + cfxp = (u_int16_t *)(((caddr_t)cfxp) + bytesPerSector); + } + return (0); +} + +/* + * Find a resident attribute of a given type. Returns a pointer to the + * attribute data, and its size in bytes. + */ +static int +ntfs_find_attr( + char *buf, + u_int32_t attrType, + void **attrData, + size_t *attrSize) +{ + struct filerec *filerec; + struct attr *attr; + u_int16_t offset; + + filerec = (struct filerec *) buf; + offset = OSReadLittleInt16(&filerec->fr_attroff,0); + attr = (struct attr *) (buf + offset); + + /* Should we also check offset < buffer size? */ + while (attr->a_hdr.a_type != 0xFFFFFFFF) /* same for big/little endian */ + { + if (OSReadLittleInt32(&attr->a_hdr.a_type,0) == attrType) + { + if (attr->a_hdr.a_flag != 0) + { + //verbose("NTFS: attriubte 0x%X is non-resident\n", attrType); + return 1; + } + + *attrSize = OSReadLittleInt16(&attr->a_r.a_datalen,0); + *attrData = buf + offset + OSReadLittleInt16(&attr->a_r.a_dataoff,0); + return 0; /* found it! */ + } + + /* Skip to the next attribute */ + offset += OSReadLittleInt32(&attr->a_hdr.reclen,0); + attr = (struct attr *) (buf + offset); + } + + return 1; /* No matching attrType found */ +} + +/* + * Examine a volume to see if we recognize it as a mountable. + */ +void +NTFSGetDescription(CICell ih, char *str, long strMaxLen) +{ + struct bootfile *boot; + unsigned bytesPerSector; + unsigned sectorsPerCluster; + int mftRecordSize; + u_int64_t totalClusters; + u_int64_t cluster, mftCluster; + size_t mftOffset; + void *nameAttr; + size_t nameSize; + char *buf; + + buf = (char *)malloc(MAX_CLUSTER_SIZE); + if (buf == 0) { + goto error; + } + + /* + * Read the boot sector, check signatures, and do some minimal + * sanity checking. NOTE: the size of the read below is intended + * to be a multiple of all supported block sizes, so we don't + * have to determine or change the device's block size. + */ + Seek(ih, 0); + Read(ih, (long)buf, MAX_BLOCK_SIZE); + + boot = (struct bootfile *) buf; + + /* + * The first three bytes are an Intel x86 jump instruction. I assume it + * can be the same forms as DOS FAT: + * 0xE9 0x?? 0x?? + * 0xEC 0x?? 0x90 + * where 0x?? means any byte value is OK. + */ + if (boot->reserved1[0] != 0xE9 + && (boot->reserved1[0] != 0xEB || boot->reserved1[2] != 0x90)) + { + goto error; + } + + /* + * Check the "NTFS " signature. + */ + if (memcmp((const char *)boot->bf_sysid, "NTFS ", 8) != 0) + { + goto error; + } + + /* + * Make sure the bytes per sector and sectors per cluster are + * powers of two, and within reasonable ranges. + */ + bytesPerSector = OSReadLittleInt16(&boot->bf_bps,0); + if ((bytesPerSector & (bytesPerSector-1)) || bytesPerSector < 512 || bytesPerSector > 32768) + { + //verbose("NTFS: invalid bytes per sector (%d)\n", bytesPerSector); + goto error; + } + + sectorsPerCluster = boot->bf_spc; /* Just one byte; no swapping needed */ + if ((sectorsPerCluster & (sectorsPerCluster-1)) || sectorsPerCluster > 128) + { + //verbose("NTFS: invalid sectors per cluster (%d)\n", bytesPerSector); + goto error; + } + + /* + * Calculate the number of clusters from the number of sectors. + * Then bounds check the $MFT and $MFTMirr clusters. + */ + totalClusters = OSReadLittleInt64(&boot->bf_spv,0) / sectorsPerCluster; + mftCluster = OSReadLittleInt64(&boot->bf_mftcn,0); + if (mftCluster > totalClusters) + { + ////verbose("NTFS: invalid $MFT cluster (%lld)\n", mftCluster); + goto error; + } + cluster = OSReadLittleInt64(&boot->bf_mftmirrcn,0); + if (cluster > totalClusters) + { + //verbose("NTFS: invalid $MFTMirr cluster (%lld)\n", cluster); + goto error; + } + + /* + * Determine the size of an MFT record. + */ + mftRecordSize = (int8_t) boot->bf_mftrecsz; + if (mftRecordSize < 0) + mftRecordSize = 1 << -mftRecordSize; + else + mftRecordSize *= bytesPerSector * sectorsPerCluster; + //verbose("NTFS: MFT record size = %d\n", mftRecordSize); + + /* + * Read the MFT record for $Volume. This assumes the first four + * file records in the MFT are contiguous; if they aren't, we + * would have to map the $MFT itself. + * + * This will fail if the device sector size is larger than the + * MFT record size, since the $Volume record won't be aligned + * on a sector boundary. + */ + mftOffset = mftCluster * sectorsPerCluster * bytesPerSector; + mftOffset += mftRecordSize * NTFS_VOLUMEINO; + + Seek(ih, mftOffset); + Read(ih, (long)buf, mftRecordSize); +#if UNUSED + if (lseek(fd, mftOffset, SEEK_SET) == -1) + { + //verbose("NTFS: lseek to $Volume failed: %s\n", strerror(errno)); + goto error; + } + if (read(fd, buf, mftRecordSize) != mftRecordSize) + { + //verbose("NTFS: error reading MFT $Volume record: %s\n", + strerror(errno)); + goto error; + } +#endif + + if (ntfs_fixup(buf, mftRecordSize, NTFS_FILEMAGIC, bytesPerSector) != 0) + { + //verbose("NTFS: block fixup failed\n"); + goto error; + } + + /* + * Loop over the attributes, looking for $VOLUME_NAME (0x60). + */ + if(ntfs_find_attr(buf, NTFS_A_VOLUMENAME, &nameAttr, &nameSize) != 0) + { + //verbose("NTFS: $VOLUME_NAME attribute not found\n"); + goto error; + } + + str[0] = '\0'; + + utf_encodestr( nameAttr, nameSize / 2, (u_int8_t *)str, strMaxLen, OSLittleEndian ); + + free(buf); + return; + + error: + if (buf) free(buf); + return; +} + +long NTFSGetUUID(CICell ih, char *uuidStr) +{ + bool NTFSProbe(const void*); + + struct bootfile *boot; + void *buf = malloc(MAX_BLOCK_SIZE); + if ( !buf ) + return -1; + + /* + * Read the boot sector, check signatures, and do some minimal + * sanity checking. NOTE: the size of the read below is intended + * to be a multiple of all supported block sizes, so we don't + * have to determine or change the device's block size. + */ + Seek(ih, 0); + Read(ih, (long)buf, MAX_BLOCK_SIZE); + + boot = (struct bootfile *) buf; + + // Check for NTFS signature + if ( memcmp((void*)boot->bf_sysid, NTFS_BBID, NTFS_BBIDLEN) != 0 ) + return -1; + + // Check for non-null volume serial number + if( !boot->bf_volsn ) + return -1; + + // Use UUID like the one you get on Windows + sprintf(uuidStr, "%04X-%04X", (unsigned short)(boot->bf_volsn >> 16) & 0xFFFF, + (unsigned short)boot->bf_volsn & 0xFFFF); + + return 0; +} + +bool NTFSProbe(const void * buffer) +{ + bool result = false; + + const struct bootfile * part_bootfile = buffer; // NTFS boot sector structure + + // Looking for NTFS signature. + if (strncmp((const char *)part_bootfile->bf_sysid, NTFS_BBID, NTFS_BBIDLEN) == 0) + result = true; + + return result; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/nvidia.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/nvidia.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/nvidia.c.svn-base (revision 850) @@ -0,0 +1,942 @@ +/* + * NVidia injector + * + * Copyright (C) 2009 Jasmin Fazlic, iNDi + * + * NVidia injector is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * NVidia driver and injector is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with NVidia injector. If not, see . + */ +/* + * Alternatively you can choose to comply with APSL + */ + + +/* + * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license: + * + * + * Copyright 2005-2006 Erik Waling + * Copyright 2006 Stephane Marchesin + * Copyright 2007-2009 Stuart Bennett + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "pci.h" +#include "platform.h" +#include "device_inject.h" +#include "nvidia.h" + +#ifndef DEBUG_NVIDIA +#define DEBUG_NVIDIA 0 +#endif + +#if DEBUG_NVIDIA +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +#define NVIDIA_ROM_SIZE 0x10000 +#define PATCH_ROM_SUCCESS 1 +#define PATCH_ROM_SUCCESS_HAS_LVDS 2 +#define PATCH_ROM_FAILED 0 +#define MAX_NUM_DCB_ENTRIES 16 + +#define TYPE_GROUPED 0xff + +extern uint32_t devices_number; + +const char *nvidia_compatible_0[] = { "@0,compatible", "NVDA,NVMac" }; +const char *nvidia_compatible_1[] = { "@1,compatible", "NVDA,NVMac" }; +const char *nvidia_device_type_0[] = { "@0,device_type", "display" }; +const char *nvidia_device_type_1[] = { "@1,device_type", "display" }; +const char *nvidia_device_type[] = { "device_type", "NVDA,Parent" }; +const char *nvidia_name_0[] = { "@0,name", "NVDA,Display-A" }; +const char *nvidia_name_1[] = { "@1,name", "NVDA,Display-B" }; +const char *nvidia_slot_name[] = { "AAPL,slot-name", "Slot-1" }; + +static uint8_t default_NVCAP[]= { + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x00 +}; + +#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) ) + +static struct nv_chipsets_t NVKnownChipsets[] = { + { 0x00000000, "Unknown" }, + { 0x10DE0040, "GeForce 6800 Ultra" }, + { 0x10DE0041, "GeForce 6800" }, + { 0x10DE0042, "GeForce 6800 LE" }, + { 0x10DE0043, "GeForce 6800 XE" }, + { 0x10DE0044, "GeForce 6800 XT" }, + { 0x10DE0045, "GeForce 6800 GT" }, + { 0x10DE0046, "GeForce 6800 GT" }, + { 0x10DE0047, "GeForce 6800 GS" }, + { 0x10DE0048, "GeForce 6800 XT" }, + { 0x10DE004E, "Quadro FX 4000" }, + { 0x10DE0090, "GeForce 7800 GTX" }, + { 0x10DE0091, "GeForce 7800 GTX" }, + { 0x10DE0092, "GeForce 7800 GT" }, + { 0x10DE0093, "GeForce 7800 GS" }, + { 0x10DE0095, "GeForce 7800 SLI" }, + { 0x10DE0098, "GeForce Go 7800" }, + { 0x10DE0099, "GeForce Go 7800 GTX" }, + { 0x10DE009D, "Quadro FX 4500" }, + { 0x10DE00C0, "GeForce 6800 GS" }, + { 0x10DE00C1, "GeForce 6800" }, + { 0x10DE00C2, "GeForce 6800 LE" }, + { 0x10DE00C3, "GeForce 6800 XT" }, + { 0x10DE00C8, "GeForce Go 6800" }, + { 0x10DE00C9, "GeForce Go 6800 Ultra" }, + { 0x10DE00CC, "Quadro FX Go1400" }, + { 0x10DE00CD, "Quadro FX 3450/4000 SDI" }, + { 0x10DE00CE, "Quadro FX 1400" }, + { 0x10DE0140, "GeForce 6600 GT" }, + { 0x10DE0141, "GeForce 6600" }, + { 0x10DE0142, "GeForce 6600 LE" }, + { 0x10DE0143, "GeForce 6600 VE" }, + { 0x10DE0144, "GeForce Go 6600" }, + { 0x10DE0145, "GeForce 6610 XL" }, + { 0x10DE0146, "GeForce Go 6600 TE/6200 TE" }, + { 0x10DE0147, "GeForce 6700 XL" }, + { 0x10DE0148, "GeForce Go 6600" }, + { 0x10DE0149, "GeForce Go 6600 GT" }, + { 0x10DE014C, "Quadro FX 550" }, + { 0x10DE014D, "Quadro FX 550" }, + { 0x10DE014E, "Quadro FX 540" }, + { 0x10DE014F, "GeForce 6200" }, + { 0x10DE0160, "GeForce 6500" }, + { 0x10DE0161, "GeForce 6200 TurboCache(TM)" }, + { 0x10DE0162, "GeForce 6200SE TurboCache(TM)" }, + { 0x10DE0163, "GeForce 6200 LE" }, + { 0x10DE0164, "GeForce Go 6200" }, + { 0x10DE0165, "Quadro NVS 285" }, + { 0x10DE0166, "GeForce Go 6400" }, + { 0x10DE0167, "GeForce Go 6200" }, + { 0x10DE0168, "GeForce Go 6400" }, + { 0x10DE0169, "GeForce 6250" }, + { 0x10DE016A, "GeForce 7100 GS" }, + { 0x10DE0191, "GeForce 8800 GTX" }, + { 0x10DE0193, "GeForce 8800 GTS" }, + { 0x10DE0194, "GeForce 8800 Ultra" }, + { 0x10DE019D, "Quadro FX 5600" }, + { 0x10DE019E, "Quadro FX 4600" }, + { 0x10DE01D1, "GeForce 7300 LE" }, + { 0x10DE01D3, "GeForce 7300 SE" }, + { 0x10DE01D6, "GeForce Go 7200" }, + { 0x10DE01D7, "GeForce Go 7300" }, + { 0x10DE01D8, "GeForce Go 7400" }, + { 0x10DE01D9, "GeForce Go 7400 GS" }, + { 0x10DE01DA, "Quadro NVS 110M" }, + { 0x10DE01DB, "Quadro NVS 120M" }, + { 0x10DE01DC, "Quadro FX 350M" }, + { 0x10DE01DD, "GeForce 7500 LE" }, + { 0x10DE01DE, "Quadro FX 350" }, + { 0x10DE01DF, "GeForce 7300 GS" }, + { 0x10DE0211, "GeForce 6800" }, + { 0x10DE0212, "GeForce 6800 LE" }, + { 0x10DE0215, "GeForce 6800 GT" }, + { 0x10DE0218, "GeForce 6800 XT" }, + { 0x10DE0221, "GeForce 6200" }, + { 0x10DE0222, "GeForce 6200 A-LE" }, + { 0x10DE0240, "GeForce 6150" }, + { 0x10DE0241, "GeForce 6150 LE" }, + { 0x10DE0242, "GeForce 6100" }, + { 0x10DE0244, "GeForce Go 6150" }, + { 0x10DE0247, "GeForce Go 6100" }, + { 0x10DE0290, "GeForce 7900 GTX" }, + { 0x10DE0291, "GeForce 7900 GT" }, + { 0x10DE0292, "GeForce 7900 GS" }, + { 0x10DE0298, "GeForce Go 7900 GS" }, + { 0x10DE0299, "GeForce Go 7900 GTX" }, + { 0x10DE029A, "Quadro FX 2500M" }, + { 0x10DE029B, "Quadro FX 1500M" }, + { 0x10DE029C, "Quadro FX 5500" }, + { 0x10DE029D, "Quadro FX 3500" }, + { 0x10DE029E, "Quadro FX 1500" }, + { 0x10DE029F, "Quadro FX 4500 X2" }, + { 0x10DE0301, "GeForce FX 5800 Ultra" }, + { 0x10DE0302, "GeForce FX 5800" }, + { 0x10DE0308, "Quadro FX 2000" }, + { 0x10DE0309, "Quadro FX 1000" }, + { 0x10DE0311, "GeForce FX 5600 Ultra" }, + { 0x10DE0312, "GeForce FX 5600" }, + { 0x10DE0314, "GeForce FX 5600XT" }, + { 0x10DE031A, "GeForce FX Go5600" }, + { 0x10DE031B, "GeForce FX Go5650" }, + { 0x10DE031C, "Quadro FX Go700" }, + { 0x10DE0324, "GeForce FX Go5200" }, + { 0x10DE0325, "GeForce FX Go5250" }, + { 0x10DE0326, "GeForce FX 5500" }, + { 0x10DE0328, "GeForce FX Go5200 32M/64M" }, + { 0x10DE032A, "Quadro NVS 55/280 PCI" }, + { 0x10DE032B, "Quadro FX 500/600 PCI" }, + { 0x10DE032C, "GeForce FX Go53xx Series" }, + { 0x10DE032D, "GeForce FX Go5100" }, + { 0x10DE0330, "GeForce FX 5900 Ultra" }, + { 0x10DE0331, "GeForce FX 5900" }, + { 0x10DE0332, "GeForce FX 5900XT" }, + { 0x10DE0333, "GeForce FX 5950 Ultra" }, + { 0x10DE0334, "GeForce FX 5900ZT" }, + { 0x10DE0338, "Quadro FX 3000" }, + { 0x10DE033F, "Quadro FX 700" }, + { 0x10DE0341, "GeForce FX 5700 Ultra" }, + { 0x10DE0342, "GeForce FX 5700" }, + { 0x10DE0343, "GeForce FX 5700LE" }, + { 0x10DE0344, "GeForce FX 5700VE" }, + { 0x10DE0347, "GeForce FX Go5700" }, + { 0x10DE0348, "GeForce FX Go5700" }, + { 0x10DE034C, "Quadro FX Go1000" }, + { 0x10DE034E, "Quadro FX 1100" }, + { 0x10DE0391, "GeForce 7600 GT" }, + { 0x10DE0392, "GeForce 7600 GS" }, + { 0x10DE0393, "GeForce 7300 GT" }, + { 0x10DE0394, "GeForce 7600 LE" }, + { 0x10DE0395, "GeForce 7300 GT" }, + { 0x10DE0397, "GeForce Go 7700" }, + { 0x10DE0398, "GeForce Go 7600" }, + { 0x10DE0399, "GeForce Go 7600 GT"}, + { 0x10DE039A, "Quadro NVS 300M" }, + { 0x10DE039B, "GeForce Go 7900 SE" }, + { 0x10DE039C, "Quadro FX 550M" }, + { 0x10DE039E, "Quadro FX 560" }, + { 0x10DE0400, "GeForce 8600 GTS" }, + { 0x10DE0401, "GeForce 8600 GT" }, + { 0x10DE0402, "GeForce 8600 GT" }, + { 0x10DE0403, "GeForce 8600 GS" }, + { 0x10DE0404, "GeForce 8400 GS" }, + { 0x10DE0405, "GeForce 9500M GS" }, + { 0x10DE0407, "GeForce 8600M GT" }, + { 0x10DE0408, "GeForce 9650M GS" }, + { 0x10DE0409, "GeForce 8700M GT" }, + { 0x10DE040A, "Quadro FX 370" }, + { 0x10DE040B, "Quadro NVS 320M" }, + { 0x10DE040C, "Quadro FX 570M" }, + { 0x10DE040D, "Quadro FX 1600M" }, + { 0x10DE040E, "Quadro FX 570" }, + { 0x10DE040F, "Quadro FX 1700" }, + { 0x10DE0420, "GeForce 8400 SE" }, + { 0x10DE0421, "GeForce 8500 GT" }, + { 0x10DE0422, "GeForce 8400 GS" }, + { 0x10DE0423, "GeForce 8300 GS" }, + { 0x10DE0424, "GeForce 8400 GS" }, + { 0x10DE0425, "GeForce 8600M GS" }, + { 0x10DE0426, "GeForce 8400M GT" }, + { 0x10DE0427, "GeForce 8400M GS" }, + { 0x10DE0428, "GeForce 8400M G" }, + { 0x10DE0429, "Quadro NVS 140M" }, + { 0x10DE042A, "Quadro NVS 130M" }, + { 0x10DE042B, "Quadro NVS 135M" }, + { 0x10DE042C, "GeForce 9400 GT" }, + { 0x10DE042D, "Quadro FX 360M" }, + { 0x10DE042E, "GeForce 9300M G" }, + { 0x10DE042F, "Quadro NVS 290" }, + { 0x10DE05E0, "GeForce GTX 295" }, + { 0x10DE05E1, "GeForce GTX 280" }, + { 0x10DE05E2, "GeForce GTX 260" }, + { 0x10DE05E3, "GeForce GTX 285" }, + { 0x10DE05E6, "GeForce GTX 275" }, + { 0x10DE05EA, "GeForce GTX 260" }, + { 0x10DE05EB, "GeForce GTX 295" }, + { 0x10DE05F9, "Quadro CX" }, + { 0x10DE05FD, "Quadro FX 5800" }, + { 0x10DE05FE, "Quadro FX 4800" }, + { 0x10DE0600, "GeForce 8800 GTS 512" }, + { 0x10DE0602, "GeForce 8800 GT" }, + { 0x10DE0604, "GeForce 9800 GX2" }, + { 0x10DE0605, "GeForce 9800 GT" }, + { 0x10DE0606, "GeForce 8800 GS" }, + { 0x10DE0607, "GeForce GTS 240" }, + { 0x10DE0608, "GeForce 9800M GTX" }, + { 0x10DE0609, "GeForce 8800M GTS" }, + { 0x10DE060A, "GeForce GTX 280M" }, + { 0x10DE060B, "GeForce 9800M GT" }, + { 0x10DE060C, "GeForce 8800M GTX" }, + { 0x10DE060D, "GeForce 8800 GS" }, + { 0x10DE0610, "GeForce 9600 GSO" }, + { 0x10DE0611, "GeForce 8800 GT" }, + { 0x10DE0612, "GeForce 9800 GTX" }, + { 0x10DE0613, "GeForce 9800 GTX+" }, + { 0x10DE0614, "GeForce 9800 GT" }, + { 0x10DE0615, "GeForce GTS 250" }, + { 0x10DE0617, "GeForce 9800M GTX" }, + { 0x10DE0618, "GeForce GTX 260M" }, + { 0x10DE061A, "Quadro FX 3700" }, + { 0x10DE061C, "Quadro FX 3600M" }, + { 0x10DE061D, "Quadro FX 2800M" }, + { 0x10DE061F, "Quadro FX 3800M" }, + { 0x10DE0622, "GeForce 9600 GT" }, + { 0x10DE0623, "GeForce 9600 GS" }, + { 0x10DE0625, "GeForce 9600 GSO 512"}, + { 0x10DE0626, "GeForce GT 130" }, + { 0x10DE0627, "GeForce GT 140" }, + { 0x10DE0628, "GeForce 9800M GTS" }, + { 0x10DE062A, "GeForce 9700M GTS" }, + { 0x10DE062C, "GeForce 9800M GTS" }, + { 0x10DE0640, "GeForce 9500 GT" }, + { 0x10DE0641, "GeForce 9400 GT" }, + { 0x10DE0642, "GeForce 8400 GS" }, + { 0x10DE0643, "GeForce 9500 GT" }, + { 0x10DE0644, "GeForce 9500 GS" }, + { 0x10DE0645, "GeForce 9500 GS" }, + { 0x10DE0646, "GeForce GT 120" }, + { 0x10DE0647, "GeForce 9600M GT" }, + { 0x10DE0648, "GeForce 9600M GS" }, + { 0x10DE0649, "GeForce 9600M GT" }, + { 0x10DE064A, "GeForce 9700M GT" }, + { 0x10DE064B, "GeForce 9500M G" }, + { 0x10DE064C, "GeForce 9650M GT" }, + { 0x10DE0652, "GeForce GT 130M" }, + { 0x10DE0658, "Quadro FX 380" }, + { 0x10DE0659, "Quadro FX 580" }, + { 0x10DE065A, "Quadro FX 1700M" }, + { 0x10DE065B, "GeForce 9400 GT" }, + { 0x10DE065C, "Quadro FX 770M" }, + { 0x10DE06E0, "GeForce 9300 GE" }, + { 0x10DE06E1, "GeForce 9300 GS" }, + { 0x10DE06E4, "GeForce 8400 GS" }, + { 0x10DE06E5, "GeForce 9300M GS" }, + { 0x10DE06E8, "GeForce 9200M GS" }, + { 0x10DE06E9, "GeForce 9300M GS" }, + { 0x10DE06EA, "Quadro NVS 150M" }, + { 0x10DE06EB, "Quadro NVS 160M" }, + { 0x10DE06EC, "GeForce G 105M" }, + { 0x10DE06EF, "GeForce G 103M" }, + { 0x10DE06F8, "Quadro NVS 420" }, + { 0x10DE06F9, "Quadro FX 370 LP" }, + { 0x10DE06FA, "Quadro NVS 450" }, + { 0x10DE06FD, "Quadro NVS 295" }, + { 0x10DE086A, "GeForce 9400" }, + { 0x10DE0874, "ION 9300M" }, + { 0x10DE086C, "GeForce 9300/nForce 730i" }, + { 0x10DE087D, "ION 9400M" }, + { 0x10DE087E, "ION LE" }, + { 0x10DE0A20, "GeForce GT220" }, + { 0x10DE0A23, "GeForce 210" }, + { 0x10DE0A28, "GeForce GT 230M" }, + { 0x10DE0A29, "GeForce GT 330M" }, + { 0x10DE0A2A, "GeForce GT 230M" }, + { 0x10DE0A34, "GeForce GT 240M" }, + { 0x10DE0A60, "GeForce G210" }, + { 0x10DE0A62, "GeForce 205" }, + { 0x10DE0A63, "GeForce 310" }, + { 0x10DE0A65, "GeForce 210" }, + { 0x10DE0A66, "GeForce 310" }, + { 0x10DE0A74, "GeForce G210M" }, + { 0x10DE0A75, "GeForce G310M" }, + { 0x10DE0A78, "Quadro FX 380 LP" }, + { 0x10DE0CA3, "GeForce GT 240" }, + { 0x10DE0CA8, "GeForce GTS 260M" }, + { 0x10DE0CA9, "GeForce GTS 250M" }, + { 0x10DE0CB1, "GeForce GTS 360M" }, + { 0x10DE0CA3, "GeForce GT240" }, + + // 06C0 - 06DFF + { 0x10DE06C0, "GeForce GTX 480" }, + { 0x10DE06C3, "GeForce GTX D12U" }, + { 0x10DE06C4, "GeForce GTX 465" }, + { 0x10DE06CA, "GeForce GTX 480M" }, + { 0x10DE06CD, "GeForce GTX 470" }, + { 0x10DE06D1, "Tesla C2050" }, // TODO: sub-device id: 0x0771 + { 0x10DE06D1, "Tesla C2070" }, // TODO: sub-device id: 0x0772 + { 0x10DE06D2, "Tesla M2070" }, + { 0x10DE06D8, "Quadro 6000" }, + { 0x10DE06D9, "Quadro 5000" }, + { 0x10DE06DA, "Quadro 5000M" }, + { 0x10DE06DC, "Quadro 6000" }, + { 0x10DE06DE, "Tesla M2050" }, // TODO: sub-device id: 0x0846 + { 0x10DE06DE, "Tesla M2070" }, // TODO: sub-device id: ? + // 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070 + { 0x10DE06DD, "Quadro 4000" }, + + // 0DC0 - 0DFF + { 0x10DE0DC0, "GeForce GT 440" }, + { 0x10DE0DC1, "D12-P1-35" }, + { 0x10DE0DC2, "D12-P1-35" }, + { 0x10DE0DC4, "GeForce GTS 450" }, + { 0x10DE0DC5, "GeForce GTS 450" }, + { 0x10DE0DC6, "GeForce GTS 450" }, + { 0x10DE0DCA, "GF10x" }, + { 0x10DE0DD1, "GeForce GTX 460M" }, + { 0x10DE0DD2, "GeForce GT 445M" }, + { 0x10DE0DD3, "GeForce GT 435M" }, + { 0x10DE0DD8, "Quadro 2000" }, + { 0x10DE0DDE, "GF106-ES" }, + { 0x10DE0DDF, "GF106-INT" }, + { 0x10DE0DE1, "GeForce GT 430" }, + { 0x10DE0DE2, "GeForce GT 420" }, + { 0x10DE0DEB, "GeForce GT 555M" }, + { 0x10DE0DEE, "GeForce GT 415M" }, + { 0x10DE0DF0, "GeForce GT 425M" }, + { 0x10DE0DF1, "GeForce GT 420M" }, + { 0x10DE0DF2, "GeForce GT 435M" }, + { 0x10DE0DF3, "GeForce GT 420M" }, + { 0x10DE0DF8, "Quadro 600" }, + { 0x10DE0DFE, "GF108 ES" }, + { 0x10DE0DFF, "GF108 INT" }, + + // 0E20 - 0E3F + { 0x10DE0E21, "D12U-25" }, + { 0x10DE0E22, "GeForce GTX 460" }, + { 0x10DE0E23, "GeForce GTX 460 SE" }, + { 0x10DE0E24, "GeForce GTX 460" }, + { 0x10DE0E25, "D12U-50" }, + { 0x10DE0E30, "GeForce GTX 470M" }, + { 0x10DE0E38, "GF104GL" }, + { 0x10DE0E3E, "GF104-ES" }, + { 0x10DE0E3F, "GF104-INT" }, + + // 0EE0 - 0EFF: none yet + // 0F00 - 0F3F: none yet + // 1040 - 107F: none yet + + // 1080 - 109F + { 0x10DE1080, "GeForce GTX 580" }, + { 0x10DE1081, "D13U" }, + { 0x10DE1082, "D13U" }, + { 0x10DE1083, "D13U" }, + { 0x10DE1098, "D13U" }, + { 0x10DE109A, "N12E-Q5" }, +}; + +static uint16_t swap16(uint16_t x) +{ + return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8)); +} + +static uint16_t read16(uint8_t *ptr, uint16_t offset) +{ + uint8_t ret[2]; + ret[0] = ptr[offset+1]; + ret[1] = ptr[offset]; + return *((uint16_t*)&ret); +} + +#if 0 +static uint32_t swap32(uint32_t x) +{ + return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24); +} + +static uint8_t read8(uint8_t *ptr, uint16_t offset) +{ + return ptr[offset]; +} + +static uint32_t read32(uint8_t *ptr, uint16_t offset) +{ + uint8_t ret[4]; + ret[0] = ptr[offset+3]; + ret[1] = ptr[offset+2]; + ret[2] = ptr[offset+1]; + ret[3] = ptr[offset]; + return *((uint32_t*)&ret); +} +#endif + +static int patch_nvidia_rom(uint8_t *rom) +{ + if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) { + printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]); + return PATCH_ROM_FAILED; + } + + uint16_t dcbptr = swap16(read16(rom, 0x36)); + if(!dcbptr) { + printf("no dcb table found\n"); + return PATCH_ROM_FAILED; + }/* else + printf("dcb table at offset 0x%04x\n", dcbptr); + */ + uint8_t *dcbtable = &rom[dcbptr]; + uint8_t dcbtable_version = dcbtable[0]; + uint8_t headerlength = 0; + uint8_t recordlength = 0; + uint8_t numentries = 0; + + if(dcbtable_version >= 0x20) { + uint32_t sig; + + if(dcbtable_version >= 0x30) { + headerlength = dcbtable[1]; + numentries = dcbtable[2]; + recordlength = dcbtable[3]; + sig = *(uint32_t *)&dcbtable[6]; + } else { + sig = *(uint32_t *)&dcbtable[4]; + headerlength = 8; + } + if (sig != 0x4edcbdcb) { + printf("bad display config block signature (0x%8x)\n", sig); + return PATCH_ROM_FAILED; + } + } else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */ + char sig[8] = { 0 }; + + strncpy(sig, (char *)&dcbtable[-7], 7); + recordlength = 10; + if (strcmp(sig, "DEV_REC")) { + printf("Bad Display Configuration Block signature (%s)\n", sig); + return PATCH_ROM_FAILED; + } + } else { + printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version); + return PATCH_ROM_FAILED; + } + + if(numentries >= MAX_NUM_DCB_ENTRIES) + numentries = MAX_NUM_DCB_ENTRIES; + + uint8_t num_outputs = 0, i=0; + struct dcbentry { + uint8_t type; + uint8_t index; + uint8_t *heads; + } entries[numentries]; + + for (i = 0; i < numentries; i++) { + uint32_t connection; + connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i]; + /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */ + if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ + continue; + if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ + continue; + if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */ + continue; + + entries[num_outputs].type = connection & 0xf; + entries[num_outputs].index = num_outputs; + entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]); + + } + + int has_lvds = false; + uint8_t channel1 = 0, channel2 = 0; + + for(i=0; i channel2) { + uint8_t buff = channel1; + channel1 = channel2; + channel2 = buff; + } + + default_NVCAP[6] = channel1; + default_NVCAP[8] = channel2; + + // patching HEADS + for(i=0; i bufsize) { + printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize); + size = bufsize; + } + size = read(fd, (char *)buf, size); + close(fd); + return size > 0 ? size : 0; +} + +static int devprop_add_nvidia_template(struct DevPropDevice *device) +{ + char tmp[16]; + + if(!device) + return 0; + + if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0)) + return 0; + if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0)) + return 0; + if(!DP_ADD_TEMP_VAL(device, nvidia_name_0)) + return 0; + if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1)) + return 0; + if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1)) + return 0; + if(!DP_ADD_TEMP_VAL(device, nvidia_name_1)) + return 0; + if(!DP_ADD_TEMP_VAL(device, nvidia_device_type)) + return 0; + // Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0! + // len = sprintf(tmp, "Slot-%x", devices_number); + sprintf(tmp, "Slot-%x",devices_number); + devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp)); + devices_number++; + + return 1; +} + +int hex2bin(const char *hex, uint8_t *bin, int len) +{ + char *p; + int i; + char buf[3]; + + if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) { + printf("[ERROR] bin2hex input error\n"); + return -1; + } + + buf[2] = '\0'; + p = (char *) hex; + for (i=0; i= NV_ARCH_C0 + vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20; + vram_size *= REG32(NVC0_MEM_CTRLR_COUNT); + } + + return vram_size; +} + +bool setup_nvidia_devprop(pci_dt_t *nvda_dev) +{ + struct DevPropDevice *device; + char *devicepath; + option_rom_pci_header_t *rom_pci_header; + volatile uint8_t *regs; + uint8_t *rom; + uint8_t *nvRom; + uint8_t nvCardType; + unsigned long long videoRam; + uint32_t nvBiosOveride; + uint32_t bar[7]; + uint32_t boot_display; + int nvPatch; + int len; + char biosVersion[32]; + char nvFilename[32]; + char kNVCAP[12]; + char *model; + const char *value; + bool doit; + + devicepath = get_pci_dev_path(nvda_dev); + bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 ); + regs = (uint8_t *) (bar[0] & ~0x0f); + + // get card type + nvCardType = (REG32(0) >> 20) & 0x1ff; + + // Amount of VRAM in kilobytes + videoRam = mem_detect(regs, nvCardType, nvda_dev); + model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id); + + verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", + model, (uint32_t)(videoRam / 1024 / 1024), + (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id, + devicepath); + + rom = malloc(NVIDIA_ROM_SIZE); + sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id); + if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) { + verbose("Looking for nvidia video bios file %s\n", nvFilename); + nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE); + if (nvBiosOveride > 0) { + verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride); + DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride); + } else { + printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename); + return false; + } + } else { + // Otherwise read bios from card + nvBiosOveride = 0; + + // TODO: we should really check for the signature before copying the rom, i think. + + // PRAMIN first + nvRom = (uint8_t*)®s[NV_PRAMIN_OFFSET]; + bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE); + + // Valid Signature ? + if (rom[0] != 0x55 && rom[1] != 0xaa) { + // PROM next + // Enable PROM access + (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED; + + nvRom = (uint8_t*)®s[NV_PROM_OFFSET]; + bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE); + + // disable PROM access + (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; + + // Valid Signature ? + if (rom[0] != 0x55 && rom[1] != 0xaa) { + // 0xC0000 last + bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE); + + // Valid Signature ? + if (rom[0] != 0x55 && rom[1] != 0xaa) { + printf("ERROR: Unable to locate nVidia Video BIOS\n"); + return false; + } else { + DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + } + } else { + DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + } + } else { + DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]); + } + } + + if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) { + printf("ERROR: nVidia ROM Patching Failed!\n"); + //return false; + } + + rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]); + + // check for 'PCIR' sig + if (rom_pci_header->signature == 0x50434952) { + if (rom_pci_header->device_id != nvda_dev->device_id) { + // Get Model from the OpROM + model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id); + } else { + printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature); + } + } + + if (!string) { + string = devprop_create_string(); + } + device = devprop_add_device(string, devicepath); + + /* FIXME: for primary graphics card only */ + boot_display = 1; + devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4); + + if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) { + uint8_t built_in = 0x01; + devprop_add_value(device, "@0,built-in", &built_in, 1); + } + + // get bios version + const int MAX_BIOS_VERSION_LENGTH = 32; + char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH); + memset(version_str, 0, MAX_BIOS_VERSION_LENGTH); + int i, version_start; + int crlf_count = 0; + // only search the first 384 bytes + for(i = 0; i < 0x180; i++) { + if(rom[i] == 0x0D && rom[i+1] == 0x0A) { + crlf_count++; + // second 0x0D0A was found, extract bios version + if(crlf_count == 2) { + if(rom[i-1] == 0x20) i--; // strip last " " + for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) { + // find start + if(rom[version_start] == 0x00) { + version_start++; + + // strip "Version " + if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) { + version_start += 8; + } + + strncpy(version_str, (const char*)rom+version_start, i-version_start); + break; + } + } + break; + } + } + } + + sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str); + + sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id); + if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) { + uint8_t new_NVCAP[NVCAP_LEN]; + + if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) { + verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath); + memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN); + } + } + + #if DEBUG_NVCAP + printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n", + default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3], + default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7], + default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11], + default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15], + default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]); +#endif + + + devprop_add_nvidia_template(device); + devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN); + devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4); + devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1); + devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1); + if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) { + devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512)); + } + + stringdata = malloc(sizeof(uint8_t) * string->length); + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + + return true; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/vbe.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/vbe.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/vbe.c.svn-base (revision 850) @@ -0,0 +1,310 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright 1993 NeXT, Inc. + * All rights reserved. + */ + +#include "libsaio.h" +#include "vbe.h" + +/* + * Various inline routines for video I/O + */ +static inline void +outi (int port, int index, int val) +{ + outw (port, (val << 8) | index); +} + +static inline void +outib (int port, int index, int val) +{ + outb (port, index); + outb (port + 1, val); +} + +static inline int +ini (int port, int index) +{ + outb (port, index); + return inb (port + 1); +} + +static inline void +rmwi (int port, int index, int clear, int set) +{ + outb (port, index); + outb (port + 1, (inb (port + 1) & ~clear) | set); +} + +/* + * Globals + */ +static biosBuf_t bb; + +int getVBEInfo( void * infoBlock ) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetControllerInfo; + bb.es = SEG( infoBlock ); + bb.edi.rr = OFF( infoBlock ); + bios( &bb ); + return(bb.eax.r.h); +} + +int getVBEModeInfo( int mode, void * minfo_p ) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetModeInfo; + bb.ecx.rr = mode; + bb.es = SEG(minfo_p); + bb.edi.rr = OFF(minfo_p); + bios(&bb); + return(bb.eax.r.h); +} + +int getVBEDACFormat(unsigned char *format) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetSetPaletteFormat; + bb.ebx.r.l = subfuncGet; + bios(&bb); + *format = bb.ebx.r.h; + return(bb.eax.r.h); +} + +int setVBEDACFormat(unsigned char format) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetSetPaletteFormat; + bb.ebx.r.l = subfuncSet; + bb.ebx.r.h = format; + bios(&bb); + return(bb.eax.r.h); +} + +/* + * Default GTF parameter values. + */ +#define kCellGranularity 8.0 // character cell granularity +#define kMinVSyncPlusBP 550.0 // min VSync + BP interval (us) +#define kMinFrontPorch 1.0 // minimum front porch in lines(V)/cells(H) +#define kVSyncLines 3.0 // width of VSync in lines +#define kHSyncWidth 8.0 // HSync as a percent of total line width +#define kC 30.0 // C = (C'-J) * (K/256) + J +#define kM 300.0 // M = K/256 * M' + +int Round(double f) +{ + return (int)(f + 0.5); +} + +/* + * from http://www.azillionmonkeys.com/qed/sqroot.html + */ + +double Sqrt( double y ) +{ + double x, z, tempf; + unsigned long *tfptr = ((unsigned long *)&tempf) + 1; + + tempf = y; + *tfptr = (0xbfcdd90a - *tfptr)>>1; /* estimate of 1/sqrt(y) */ + x = tempf; + z = y*0.5; /* hoist out the “/2” */ + x = (1.5*x) - (x*x)*(x*z); /* iteration formula */ + x = (1.5*x) - (x*x)*(x*z); + x = (1.5*x) - (x*x)*(x*z); + x = (1.5*x) - (x*x)*(x*z); + x = (1.5*x) - (x*x)*(x*z); + return x*y; +} + +int generateCRTCTiming( unsigned short width, + unsigned short height, + unsigned long paramValue, + int paramType, + VBECRTCInfoBlock * timing ) +{ + double h_period_est, h_freq, h_period, h_total_pixels, h_sync_pixels; + double h_active_pixels, h_ideal_duty_cycle, h_blank_pixels, pixel_freq = 0; + double v_sync_plus_bp = 0, v_total_lines = 0, v_field_rate_est, v_frame_rate = 0; + const double h_pixels = (double) width; + const double v_lines = (double) height; + + enum { + left_margin_pixels = 0, + right_margin_pixels = 0, + top_margin_lines = 0, + bot_margin_lines = 0, + interlace = 0 + }; + + // Total number of active pixels in image and both margins + h_active_pixels = h_pixels + left_margin_pixels + right_margin_pixels; + + if (paramType == kCRTCParamPixelClock) + { + // Pixel clock provided in MHz + pixel_freq = (double) paramValue / 1000000; + + // Ideal horizontal period from the blanking duty cycle equation + h_period = ((kC - 100) + (Sqrt(((100 - kC) * (100 - kC)) + (0.4 * kM * + (h_active_pixels + right_margin_pixels + left_margin_pixels) / + pixel_freq)))) / 2.0 / kM * 1000; + } + else /* kCRTCParamRefreshRate */ + { + double v_field_rate_in = (double) paramValue; + + // Estimate the horizontal period + h_period_est = ((1 / v_field_rate_in) - kMinVSyncPlusBP / 1000000) / + (v_lines + (2 * top_margin_lines) + kMinFrontPorch + interlace) * + 1000000; + + // Number of lines in Vsync + back porch + v_sync_plus_bp = Round(kMinVSyncPlusBP / h_period_est); + + // Total number of lines in Vetical field period + v_total_lines = v_lines + top_margin_lines + bot_margin_lines + + v_sync_plus_bp + interlace + kMinFrontPorch; + + // Estimate the vertical field frequency + v_field_rate_est = 1 / h_period_est / v_total_lines * 1000000; + + // Find the actual horizontal period + h_period = h_period_est / (v_field_rate_in / v_field_rate_est); + + // Find the vertical frame rate (no interlace) + v_frame_rate = 1 / h_period / v_total_lines * 1000000; + } + + // Ideal blanking duty cycle from the blanking duty cycle equation + h_ideal_duty_cycle = kC - (kM * h_period / 1000); + + // Number of pixels in the blanking time to the nearest double character cell + h_blank_pixels = Round(h_active_pixels * h_ideal_duty_cycle / + (100 - h_ideal_duty_cycle) / (2 * kCellGranularity)) * + (2 * kCellGranularity); + + // Total number of horizontal pixels + h_total_pixels = h_active_pixels + h_blank_pixels; + + if (paramType == kCRTCParamPixelClock) + { + // Horizontal frequency + h_freq = pixel_freq / h_total_pixels * 1000; + + // Number of lines in V sync + back porch + v_sync_plus_bp = Round(kMinVSyncPlusBP * h_freq / 1000); + + // Total number of lines in vertical field period + v_total_lines = v_lines + top_margin_lines + bot_margin_lines + + interlace + v_sync_plus_bp + kMinFrontPorch; + + // Vertical frame frequency + v_frame_rate = Round(h_freq / v_total_lines * 1000); + } + else + { + // Find pixel clock frequency + pixel_freq = Round(h_total_pixels / h_period); + } + + h_sync_pixels = Round(h_total_pixels * kHSyncWidth / 100 / kCellGranularity) * + kCellGranularity; + + timing->HTotal = h_total_pixels; + timing->HSyncStart = h_active_pixels + (h_blank_pixels / 2) - h_sync_pixels; + timing->HSyncEnd = timing->HSyncStart + h_sync_pixels; + timing->VTotal = v_total_lines; + timing->VSyncStart = v_total_lines - v_sync_plus_bp; + timing->VSyncEnd = timing->VSyncStart + kVSyncLines; + timing->Flags = kCRTCNegativeHorizontalSync; + timing->PixelClock = pixel_freq * 1000000; + timing->RefreshRate = v_frame_rate * 100; + + return 0; +} + +int setVBEMode(unsigned short mode, const VBECRTCInfoBlock * timing) +{ + bb.intno = 0x10; + bb.eax.rr = funcSetMode; + bb.ebx.rr = mode; + if (timing) { + bb.es = SEG(timing); + bb.edi.rr = OFF(timing); + } + bios(&bb); + return(bb.eax.r.h); +} + +int setVBEPalette(void *palette) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetSetPaletteData; + bb.ebx.r.l = subfuncSet; + bb.ecx.rr = 256; + bb.edx.rr = 0; + bb.es = SEG(palette); + bb.edi.rr = OFF(palette); + bios(&bb); + return(bb.eax.r.h); +} + +int getVBEPalette(void *palette) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetSetPaletteData; + bb.ebx.r.l = subfuncGet; + bb.ecx.rr = 256; + bb.edx.rr = 0; + bb.es = SEG(palette); + bb.edi.rr = OFF(palette); + bios(&bb); + return(bb.eax.r.h); +} + +int getVBECurrentMode(unsigned short *mode) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetCurrentMode; + bios(&bb); + *mode = bb.ebx.rr; + return(bb.eax.r.h); +} + +int getVBEPixelClock(unsigned short mode, unsigned long * pixelClock) +{ + bb.intno = 0x10; + bb.eax.rr = funcGetSetPixelClock; + bb.ebx.r.l = 0; + bb.ecx.rx = *pixelClock; + bb.edx.rr = mode; + bios(&bb); + *pixelClock = bb.ecx.rx; + return(bb.eax.r.h); +} Index: branches/Chimera/i386/libsaio/.svn/text-base/dram_controllers.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/dram_controllers.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/dram_controllers.h.svn-base (revision 850) @@ -0,0 +1,32 @@ +/* + * dram controller access and scan from the pci host controller + * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work + * original source comes from: + * + * memtest86 + * + * Released under version 2 of the Gnu Public License. + * By Chris Brady, cbrady@sgi.com + * ---------------------------------------------------- + * MemTest86+ V4.00 Specific code (GPL V2.0) + * By Samuel DEMEULEMEESTER, sdemeule@memtest.org + * http://www.canardpc.com - http://www.memtest.org + */ + +#ifndef __LIBSAIO_DRAM_CONTROLLERS_H +#define __LIBSAIO_DRAM_CONTROLLERS_H + +#include "libsaio.h" + +void scan_dram_controller(); + +struct mem_controller_t { + uint16_t vendor; + uint16_t device; + char *name; + void (*initialise)(pci_dt_t *dram_dev); + void (*poll_speed)(pci_dt_t *dram_dev); + void (*poll_timings)(pci_dt_t *dram_dev); +}; + +#endif /* !__LIBSAIO_DRAM_CONTROLLERS_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/sys.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/sys.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/sys.c.svn-base (revision 850) @@ -0,0 +1,1088 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Mach Operating System + * Copyright (c) 1990 Carnegie-Mellon University + * Copyright (c) 1989 Carnegie-Mellon University + * Copyright (c) 1988 Carnegie-Mellon University + * Copyright (c) 1987 Carnegie-Mellon University + * All rights reserved. The CMU software License Agreement specifies + * the terms and conditions for use and redistribution. + * + */ +/* + * HISTORY + * Revision 2.3 88/08/08 13:47:07 rvb + * Allocate buffers dynamically vs statically. + * Now b[i] and i_fs and i_buf, are allocated dynamically. + * boot_calloc(size) allocates and zeros a buffer rounded to a NPG + * boundary. + * Generalize boot spec to allow, xx()/mach, xx(n,[a..h])/mach, + * xx([a..h])/mach, ... + * Also default "xx" if unspecified and alloc just "/mach", + * where everything is defaulted + * Add routine, ptol(), to parse partition letters. + * + */ + +/* + * Copyright (c) 1982, 1986 Regents of the University of California. + * All rights reserved. The Berkeley software License Agreement + * specifies the terms and conditions for redistribution. + * + * @(#)sys.c 7.1 (Berkeley) 6/5/86 + */ + +/* Copyright 2007 VMware Inc. + "Preboot" ramdisk support added by David Elliott + */ + +#include + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "disk.h" +#include "ramdisk.h" +#include "xml.h" +#if MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_X_VERSION_10_5 +# include +#else +# include +#endif +#include +#if 0 /* No OS X release has ever included this. */ +#include +#else +/* copied from uuid/namespace.h, just like BootX's fs.c does. */ +UUID_DEFINE( kFSUUIDNamespaceSHA1, 0xB3, 0xE2, 0x0F, 0x39, 0xF2, 0x92, 0x11, 0xD6, 0x97, 0xA4, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC ); +#endif + +extern int multiboot_partition; +extern int multiboot_partition_set; + +struct devsw { + const char * name; + // size increased from char to short to handle non-BIOS internal devices + unsigned short biosdev; + int type; +}; + +// Device entries must be ordered by bios device numbers. +static struct devsw devsw[] = +{ + { "hd", 0x80, kBIOSDevTypeHardDrive }, /* DEV_HD */ + { "en", 0xE0, kBIOSDevTypeNetwork }, /* DEV_EN */ + { "rd", 0x100, kBIOSDevTypeHardDrive }, + { "bt", 0x101, kBIOSDevTypeHardDrive }, // turbo - type for booter partition + { 0, 0 } +}; + +// Pseudo BIOS devices +enum { + kPseudoBIOSDevRAMDisk = 0x100, + kPseudoBIOSDevBooter = 0x101 +}; + +/* + * Max number of file descriptors. + */ +#define NFILES 6 + +static struct iob iob[NFILES]; + +void * gFSLoadAddress = 0; + +// Turbo - save what we think is our original BIOS boot volume if we have one 0xab +BVRef gBIOSBootVolume = NULL; +BVRef gBootVolume; + +//static BVRef getBootVolumeRef( const char * path, const char ** outPath ); +static BVRef newBootVolumeRef( int biosdev, int partno ); + +//========================================================================== +// LoadVolumeFile - LOW-LEVEL FILESYSTEM FUNCTION. +// Load the specified file from the specified volume +// to the load buffer at LOAD_ADDR. +// If the file is fat, load only the i386 portion. + +long LoadVolumeFile(BVRef bvr, const char *filePath) +{ + long fileSize; + + // Read file into load buffer. The data in the load buffer will be + // overwritten by the next LoadFile() call. + + gFSLoadAddress = (void *) LOAD_ADDR; + + fileSize = bvr->fs_loadfile(bvr, (char *)filePath); + + // Return the size of the file, or -1 if load failed. + + return fileSize; +} + +//========================================================================== +// LoadFile - LOW-LEVEL FILESYSTEM FUNCTION. +// Load the specified file to the load buffer at LOAD_ADDR. +// If the file is fat, load only the i386 portion. + +long LoadFile(const char * fileSpec) +{ + const char * filePath; + BVRef bvr; + + // Resolve the boot volume from the file spec. + + if ((bvr = getBootVolumeRef(fileSpec, &filePath)) == NULL) + return -1; + + return LoadVolumeFile(bvr, filePath); +} + +long ReadFileAtOffset(const char * fileSpec, void *buffer, uint64_t offset, uint64_t length) +{ + const char *filePath; + BVRef bvr; + + if ((bvr = getBootVolumeRef(fileSpec, &filePath)) == NULL) + return -1; + + if (bvr->fs_readfile == NULL) + return -1; + + return bvr->fs_readfile(bvr, (char *)filePath, buffer, offset, length); +} + +long LoadThinFatFile(const char *fileSpec, void **binary) +{ + const char *filePath; + FSReadFile readFile; + BVRef bvr; + unsigned long length, length2; + + // Resolve the boot volume from the file spec. + + if ((bvr = getBootVolumeRef(fileSpec, &filePath)) == NULL) + return -1; + + *binary = (void *)kLoadAddr; + + // Read file into load buffer. The data in the load buffer will be + // overwritten by the next LoadFile() call. + + gFSLoadAddress = (void *) LOAD_ADDR; + + readFile = bvr->fs_readfile; + + if (readFile != NULL) { + // Read the first 4096 bytes (fat header) + length = readFile(bvr, (char *)filePath, *binary, 0, 0x1000); + if (length > 0) { + if (ThinFatFile(binary, &length) == 0) { + if (length == 0) + return 0; + // We found a fat binary; read only the thin part + length = readFile(bvr, (char *)filePath, + (void *)kLoadAddr, (unsigned long)(*binary) - kLoadAddr, length); + *binary = (void *)kLoadAddr; + } else { + // Not a fat binary; read the rest of the file + length2 = readFile(bvr, (char *)filePath, (void *)(kLoadAddr + length), length, 0); + if (length2 == -1) return -1; + length += length2; + } + } + } else { + length = bvr->fs_loadfile(bvr, (char *)filePath); + if (length > 0) { + ThinFatFile(binary, &length); + } + } + + return length; +} + +#if UNUSED +long GetFSUUID(char *spec, char *uuidStr) +{ + BVRef bvr; + long rval = -1; + const char *devSpec; + + if ((bvr = getBootVolumeRef(spec, &devSpec)) == NULL) + return -1; + + if(bvr->fs_getuuid) + rval = bvr->fs_getuuid(bvr, uuidStr); + + return rval; +} +#endif + +// filesystem-specific getUUID functions call this shared string generator +long CreateUUIDString(uint8_t uubytes[], int nbytes, char *uuidStr) +{ + unsigned fmtbase, fmtidx, i; + uint8_t uuidfmt[] = { 4, 2, 2, 2, 6 }; + char *p = uuidStr; + MD5_CTX md5c; + uint8_t mdresult[16]; + + bzero(mdresult, sizeof(mdresult)); + + // just like AppleFileSystemDriver + MD5Init(&md5c); + MD5Update(&md5c, kFSUUIDNamespaceSHA1, sizeof(kFSUUIDNamespaceSHA1)); + MD5Update(&md5c, uubytes, nbytes); + MD5Final(mdresult, &md5c); + + // this UUID has been made version 3 style (i.e. via namespace) + // see "-uuid-urn-" IETF draft (which otherwise copies byte for byte) + mdresult[6] = 0x30 | ( mdresult[6] & 0x0F ); + mdresult[8] = 0x80 | ( mdresult[8] & 0x3F ); + + + // generate the text: e.g. 5EB1869F-C4FA-3502-BDEB-3B8ED5D87292 + i = 0; fmtbase = 0; + for(fmtidx = 0; fmtidx < sizeof(uuidfmt); fmtidx++) { + for(i=0; i < uuidfmt[fmtidx]; i++) { + uint8_t byte = mdresult[fmtbase+i]; + char nib; + + nib = byte >> 4; + *p = nib + '0'; // 0x4 -> '4' + if(*p > '9') *p = (nib - 9 + ('A'-1)); // 0xB -> 'B' + p++; + + nib = byte & 0xf; + *p = nib + '0'; // 0x4 -> '4' + if(*p > '9') *p = (nib - 9 + ('A'-1)); // 0xB -> 'B' + p++; + + } + fmtbase += i; + if(fmtidx < sizeof(uuidfmt)-1) + *(p++) = '-'; + else + *p = '\0'; + } + + return 0; +} + + +//========================================================================== +// GetDirEntry - LOW-LEVEL FILESYSTEM FUNCTION. +// Fetch the next directory entry for the given directory. + +long GetDirEntry(const char * dirSpec, long long * dirIndex, const char ** name, + long * flags, long * time) +{ + const char * dirPath; + BVRef bvr; + + // Resolve the boot volume from the dir spec. + + if ((bvr = getBootVolumeRef(dirSpec, &dirPath)) == NULL) + return -1; + + // Return 0 on success, or -1 if there are no additional entries. + + return bvr->fs_getdirentry( bvr, + /* dirPath */ (char *)dirPath, + /* dirIndex */ dirIndex, + /* dirEntry */ (char **)name, flags, time, 0, 0 ); +} + +//========================================================================== +// GetFileInfo - LOW-LEVEL FILESYSTEM FUNCTION. +// Get attributes for the specified file. + +static char* gMakeDirSpec; + +long GetFileInfo(const char * dirSpec, const char * name, + long * flags, long * time) +{ + long long index = 0; + const char * entryName; + + if (gMakeDirSpec == 0) + gMakeDirSpec = (char *)malloc(1024); + + if (!dirSpec) { + long idx, len; + + len = strlen(name); + + for (idx = len; idx && (name[idx] != '/' && name[idx] != '\\'); idx--) {} + if (idx == 0) { + gMakeDirSpec[0] = '/'; + gMakeDirSpec[1] = '\0'; + } else { + idx++; + strncpy(gMakeDirSpec, name, idx); + name += idx; + } + dirSpec = gMakeDirSpec; + } + + while (GetDirEntry(dirSpec, &index, &entryName, flags, time) == 0) + { + if (strcmp(entryName, name) == 0) + return 0; // success + } + return -1; // file not found +} + +long GetFileBlock(const char *fileSpec, unsigned long long *firstBlock) +{ + const char * filePath; + BVRef bvr; + + // Resolve the boot volume from the file spec. + + if ((bvr = getBootVolumeRef(fileSpec, &filePath)) == NULL) { + printf("Boot volume for '%s' is bogus\n", fileSpec); + return -1; + } + + return bvr->fs_getfileblock(bvr, (char *)filePath, firstBlock); +} + +//========================================================================== +// GetFreeFD() + +static int GetFreeFd(void) +{ + int fd; + + // Locate a free descriptor slot. + for (fd = 0; fd < NFILES; fd++) { + if (iob[fd].i_flgs == 0) { + return fd; + } + } + stop("Out of file descriptors"); + // not reached + return -1; +} + +//========================================================================== +// iob_from_fdesc() +// +// Return a pointer to an allocated 'iob' based on the file descriptor +// provided. Returns NULL if the file descriptor given is invalid. + +static struct iob * iob_from_fdesc(int fdesc) +{ + register struct iob * io; + + if (fdesc < 0 || fdesc >= NFILES || + ((io = &iob[fdesc])->i_flgs & F_ALLOC) == 0) + return NULL; + else + return io; +} + +//========================================================================== +// openmem() + +int openmem(char * buf, int len) +{ + int fdesc; + struct iob * io; + + fdesc = GetFreeFd(); + io = &iob[fdesc]; + bzero(io, sizeof(*io)); + + // Mark the descriptor as taken. Set the F_MEM flag to indicate + // that the file buffer is provided by the caller. + + io->i_flgs = F_ALLOC | F_MEM; + io->i_buf = buf; + io->i_filesize = len; + + return fdesc; +} + +//========================================================================== +// open() - Open the file specified by 'path' for reading. + +static int open_bvr(BVRef bvr, const char *filePath, int flags) +{ + struct iob *io; + int fdesc; + int i; + + if (bvr == NULL) { + return -1; + } + + fdesc = GetFreeFd(); + io = &iob[fdesc]; + bzero(io, sizeof(*io)); + + // Mark the descriptor as taken. + io->i_flgs = F_ALLOC; + + // Find the next available memory block in the download buffer. + io->i_buf = (char *) LOAD_ADDR; + for (i = 0; i < NFILES; i++) { + if ((iob[i].i_flgs != F_ALLOC) || (i == fdesc)) { + continue; + } + io->i_buf = max(iob[i].i_filesize + iob[i].i_buf, io->i_buf); + } + + // Load entire file into memory. Unnecessary open() calls must be avoided. + gFSLoadAddress = io->i_buf; + io->i_filesize = bvr->fs_loadfile(bvr, (char *)filePath); + if (io->i_filesize < 0) { + close(fdesc); + return -1; + } + return fdesc; +} + +int open(const char *path, int flags) +{ + const char *filepath; + BVRef bvr; + + // Resolve the boot volume from the file spec. + if ((bvr = getBootVolumeRef(path, &filepath)) != NULL) { + return open_bvr(bvr, filepath, flags); + } + return -1; +} + +int open_bvdev(const char *bvd, const char *path, int flags) +{ + const struct devsw *dp; + const char *cp; + BVRef bvr; + int i; + int len; + int unit; + int partition; + + if ((i = open(path, flags)) >= 0) { + return i; + } + + if (bvd == NULL || (len = strlen(bvd)) < 2) { + return -1; + } + + for (dp=devsw; dp->name; dp++) { + if (bvd[0] == dp->name[0] && bvd[1] == dp->name[1]) { + unit = 0; + partition = 0; + /* get optional unit and partition */ + if (len >= 5 && bvd[2] == '(') { /* min must be present xx(0) */ + cp = &bvd[3]; + i = 0; + while ((cp - path) < len && isdigit(*cp)) { + i = i * 10 + *cp++ - '0'; + unit = i; + } + if (*cp++ == ',') { + i = 0; + while ((cp - path) < len && isdigit(*cp)) { + i = i * 10 + *cp++ - '0'; + partition = i; + } + } + } + bvr = newBootVolumeRef(dp->biosdev + unit, partition); + return open_bvr(bvr, path, flags); + } + } + return -1; +} + +//========================================================================== +// close() - Close a file descriptor. + +int close(int fdesc) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == NULL) + return (-1); + + io->i_flgs = 0; + + return 0; +} + +//========================================================================== +// lseek() - Reposition the byte offset of the file descriptor from the +// beginning of the file. Returns the relocated offset. + +int b_lseek(int fdesc, int offset, int ptr) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == NULL) + return (-1); + + io->i_offset = offset; + + return offset; +} + +//========================================================================== +// tell() - Returns the byte offset of the file descriptor. + +int tell(int fdesc) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == NULL) + return 0; + + return io->i_offset; +} + +//========================================================================== +// read() - Read up to 'count' bytes of data from the file descriptor +// into the buffer pointed to by buf. + +int read(int fdesc, char * buf, int count) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == NULL) + return (-1); + + if ((io->i_offset + count) > (unsigned int)io->i_filesize) + count = io->i_filesize - io->i_offset; + + if (count <= 0) + return 0; // end of file + + bcopy(io->i_buf + io->i_offset, buf, count); + + io->i_offset += count; + + return count; +} + +//========================================================================== +// write() - Write up to 'count' bytes of data to the file descriptor +// from the buffer pointed to by buf. + +int write(int fdesc, const char * buf, int count) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == NULL) + return (-1); + + if ((io->i_offset + count) > (unsigned int)io->i_filesize) + count = io->i_filesize - io->i_offset; + + if (count <= 0) + return 0; // end of file + + bcopy(buf, io->i_buf + io->i_offset, count); + + io->i_offset += count; + + return count; +} + +int writebyte(int fdesc, char value) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == NULL) + return (-1); + + if ((io->i_offset + 1) > (unsigned int)io->i_filesize) + return 0; // end of file + + io->i_buf[io->i_offset++] = value; + + return 1; +} + +int writeint(int fdesc, int value) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == NULL) + return (-1); + + if ((io->i_offset + 4) > (unsigned int)io->i_filesize) + return 0; // end of file + + bcopy(&value, io->i_buf + io->i_offset, 4); + + io->i_offset += 4; + + return 4; +} + +//========================================================================== +// file_size() - Returns the size of the file described by the file +// descriptor. + +int file_size(int fdesc) +{ + struct iob * io; + + if ((io = iob_from_fdesc(fdesc)) == 0) + return 0; + + return io->i_filesize; +} + +//========================================================================== + +struct dirstuff * vol_opendir(BVRef bvr, const char * path) +{ + struct dirstuff * dirp = 0; + + dirp = (struct dirstuff *) malloc(sizeof(struct dirstuff)); + if (dirp == NULL) + goto error; + + dirp->dir_path = newString(path); + if (dirp->dir_path == NULL) + goto error; + + dirp->dir_bvr = bvr; + + return dirp; + +error: + closedir(dirp); + return NULL; +} + +//========================================================================== + +struct dirstuff * opendir(const char * path) +{ + struct dirstuff * dirp = 0; + const char * dirPath; + BVRef bvr; + + if ((bvr = getBootVolumeRef(path, &dirPath)) == NULL) + goto error; + + dirp = (struct dirstuff *) malloc(sizeof(struct dirstuff)); + if (dirp == NULL) + goto error; + + dirp->dir_path = newString(dirPath); + if (dirp->dir_path == NULL) + goto error; + + dirp->dir_bvr = bvr; + + return dirp; + +error: + closedir(dirp); + return NULL; +} + +//========================================================================== + +int closedir(struct dirstuff * dirp) +{ + if (dirp) { + if (dirp->dir_path) free(dirp->dir_path); + free(dirp); + } + return 0; +} + +//========================================================================== + +int readdir(struct dirstuff * dirp, const char ** name, long * flags, + long * time) +{ + return dirp->dir_bvr->fs_getdirentry( dirp->dir_bvr, + /* dirPath */ dirp->dir_path, + /* dirIndex */ &dirp->dir_index, + /* dirEntry */ (char **)name, flags, time, + 0, 0); +} + +//========================================================================== + +int readdir_ext(struct dirstuff * dirp, const char ** name, long * flags, + long * time, FinderInfo *finderInfo, long *infoValid) +{ + return dirp->dir_bvr->fs_getdirentry( dirp->dir_bvr, + /* dirPath */ dirp->dir_path, + /* dirIndex */ &dirp->dir_index, + /* dirEntry */ (char **)name, + flags, time, + finderInfo, infoValid); +} + +//========================================================================== + +const char * systemConfigDir() +{ + if (gBootFileType == kNetworkDeviceType) + return ""; + return "/Library/Preferences/SystemConfiguration"; +} + +//========================================================================== + +int gBootFileType; + +void scanBootVolumes( int biosdev, int * count ) +{ + BVRef bvr = 0; + + bvr = diskScanBootVolumes(biosdev, count); + if (bvr == NULL) + { + bvr = nbpScanBootVolumes(biosdev, count); + if (bvr != NULL) + { + gBootFileType = kNetworkDeviceType; + } + } + else + { + gBootFileType = kBlockDeviceType; + } +} + +//========================================================================== + +void scanDisks(int biosdev, int *count) +{ + #define MAX_HDD_COUNT 32 + int bvCount; + int hd = 0; + + // Testing up to MAX_HDD_COUNT hard drives. + while(!testBiosread(0x80 + hd, 0) && hd < MAX_HDD_COUNT) + { + bvCount = 0; + scanBootVolumes(0x80 + hd, &bvCount); + hd++; + } + + // Also scanning CD/DVD drive. + if (biosDevIsCDROM(gBIOSDev)) + { + bvCount = 0; + scanBootVolumes(gBIOSDev, &bvCount); + } +} + +//========================================================================== + +BVRef selectBootVolume( BVRef chain ) +{ + bool filteredChain = false; + bool foundPrimary = false; + BVRef bvr, bvr1 = 0, bvr2 = 0; + + if (chain->filtered) filteredChain = true; + + if (multiboot_partition_set) + for ( bvr = chain; bvr; bvr = bvr->next ) + if ( bvr->part_no == multiboot_partition && bvr->biosdev == gBIOSDev ) + return bvr; + + /* + * Checking "Default Partition" key in system configuration - use format: hd(x,y), the volume UUID or label - + * to override the default selection. + * We accept only kBVFlagSystemVolume or kBVFlagForeignBoot volumes. + */ + char *val = XMLDecode(getStringForKey(kDefaultPartition, &bootInfo->bootConfig)); + if (val) { + for ( bvr = chain; bvr; bvr = bvr->next ) { + if (matchVolumeToString(bvr, val, false)) { + free(val); + return bvr; + } + } + free(val); + } + + /* + * Scannig the volume chain backwards and trying to find + * a HFS+ volume with valid boot record signature. + * If not found any active partition then we will + * select this volume as the boot volume. + */ + for ( bvr = chain; bvr; bvr = bvr->next ) + { + if ( bvr->flags & kBVFlagPrimary && bvr->biosdev == gBIOSDev ) foundPrimary = true; + // zhell -- Undo a regression that was introduced from r491 to 492. + // if gBIOSBootVolume is set already, no change is required + if ( bvr->flags & (kBVFlagBootable|kBVFlagSystemVolume) + && gBIOSBootVolume + && (!filteredChain || (filteredChain && bvr->visible)) + && bvr->biosdev == gBIOSDev ) + bvr2 = bvr; + // zhell -- if gBIOSBootVolume is NOT set, we use the "if" statement + // from r491, + if ( bvr->flags & kBVFlagBootable + && ! gBIOSBootVolume + && bvr->biosdev == gBIOSDev ) + bvr2 = bvr; + } + + + /* + * Use the standrad method for selecting the boot volume. + */ + if (foundPrimary) + { + for ( bvr = chain; bvr; bvr = bvr->next ) + { + if ( bvr->flags & kBVFlagNativeBoot && bvr->biosdev == gBIOSDev ) bvr1 = bvr; + if ( bvr->flags & kBVFlagPrimary && bvr->biosdev == gBIOSDev ) bvr2 = bvr; + } + } + + bvr = bvr2 ? bvr2 : + bvr1 ? bvr1 : chain; + + return bvr; +} + +//========================================================================== + +#define LP '(' +#define RP ')' +int gBIOSDev; + +/*! + This is like boot2's gBootVolume except it is for the internal use of + libsaio to track which volume an unqualified path should be relative to. + This replaces bootInfo->kernDev as the carrier of this information. + */ +static BVRef gRootVolume; + +void setRootVolume(BVRef volume) +{ + gRootVolume = volume; + // Veto non-native FS. Basically that means don't allow the root volume to + // be set to a volume we can't read files from. + if(gRootVolume != NULL && ((gRootVolume->flags & kBVFlagNativeBoot) == 0)) + gRootVolume = NULL; +} + +void setBootGlobals(BVRef chain) +{ + // Record default boot device. + gBootVolume = selectBootVolume(chain); + + // turbo - Save the ORIGINAL boot volume too for loading our mkext + if (!gBIOSBootVolume) gBIOSBootVolume = gBootVolume; + + setRootVolume(gBootVolume); +} + +/*! + Extracts the volume selector from the pathname, returns the selected + BVRef, and sets *outPath to the remainder of the path. + If the path did not include a volume selector then the current volume + is used. When called with a volume selector the current volume + is changed to the selected volume unless the volume selector is + that of a ramdisk. + */ +BVRef getBootVolumeRef( const char * path, const char ** outPath ) +{ + const char * cp; + BVRef bvr = gRootVolume; + int biosdev = gBIOSDev; + + // Search for left parenthesis in the path specification. + + for (cp = path; *cp; cp++) { + if (*cp == LP || *cp == '/') break; + } + + if (*cp != LP) // no left paren found + { + // Path is using the implicit current device so if there is + // no current device, then we must fail. + cp = path; + if ( gRootVolume == NULL ) + return NULL; + } + else if ((cp - path) == 2) // found "xx(" + { + const struct devsw * dp; + const char * xp = path; + int i; + int unit = -1; + int part = -1; + + cp++; + + // Check the 2 character device name pointed by 'xp'. + + for (dp = devsw; dp->name; dp++) + { + if ((xp[0] == dp->name[0]) && (xp[1] == dp->name[1])) + break; // found matching entry + } + if (dp->name == NULL) + { + error("Unknown device '%c%c'\n", xp[0], xp[1]); + return NULL; + } + + // Extract the optional unit number from the specification. + // hd(unit) or hd(unit, part). + + i = 0; + while (*cp >= '0' && *cp <= '9') + { + i = i * 10 + *cp++ - '0'; + unit = i; + } + + // Unit is no longer optional and never really was. + // If the user failed to specify it then the unit number from the previous kernDev + // would have been used which makes little sense anyway. + // For example, if the user did fd()/foobar and the current root device was the + // second hard disk (i.e. unit 1) then fd() would select the second floppy drive! + if(unit == -1) + return NULL; + + // Extract the optional partition number from the specification. + + if (*cp == ',') + part = atoi(++cp); + + // If part is not specified part will be -1 whereas before it would have been + // whatever the last partition was which makes about zero sense if the device + // has been switched. + + // Skip past the right paren. + + for ( ; *cp && *cp != RP; cp++) /* LOOP */; + if (*cp == RP) cp++; + + biosdev = dp->biosdev + unit; + bvr = newBootVolumeRef(biosdev, part); + + if(bvr == NULL) + return NULL; + } + else + { + // Bad device specifier, skip past the right paren. + + for ( cp++; *cp && *cp != RP; cp++) /* LOOP */; + if (*cp == RP) cp++; + // If gRootVolume was NULL, then bvr will be NULL as well which + // should be caught by the caller. + } + + // Returns the file path following the device spec. + // e.g. 'hd(1,b)mach_kernel' is reduced to 'mach_kernel'. + + *outPath = cp; + + return bvr; +} + +//========================================================================== +// Function name is a misnomer as scanBootVolumes usually calls diskScanBootVolumes +// which caches the information. So it's only allocated on the first run. +static BVRef newBootVolumeRef( int biosdev, int partno ) +{ + BVRef bvr, bvr1, bvrChain; + + bvr = bvr1 = NULL; + + // Try resolving "rd" and "bt" devices first. + if (biosdev == kPseudoBIOSDevRAMDisk) + { + if (gRAMDiskVolume) + bvr1 = gRAMDiskVolume; + } + else if (biosdev == kPseudoBIOSDevBooter) + { + if (gRAMDiskVolume != NULL && gRAMDiskBTAliased) + bvr1 = gRAMDiskVolume; + else + bvr1 = gBIOSBootVolume; + } + else + { + // Fetch the volume list from the device. + + scanBootVolumes( biosdev, NULL ); + bvrChain = getBVChainForBIOSDev(biosdev); + + // Look for a perfect match based on device and partition number. + + for ( bvr1 = NULL, bvr = bvrChain; bvr; bvr = bvr->next ) + { + if ( ( bvr->flags & kBVFlagNativeBoot ) == 0 ) continue; + + bvr1 = bvr; + if ( bvr->part_no == partno ) break; + } + } + + return bvr ? bvr : bvr1; +} + +//========================================================================== +// getDeviceDescription() - Extracts unit number and partition number +// from bvr structure into "dw(u,p)" format. +// Returns length of the out string +int getDeviceDescription(BVRef bvr, char *str) +{ + if(!str) + return 0; + + *str = '\0'; + + if (bvr) + { + const struct devsw *dp = devsw; + while(dp->name && bvr->biosdev >= dp->biosdev) + dp++; + + dp--; + if (dp->name) + return sprintf(str, "%s(%d,%d)", dp->name, bvr->biosdev - dp->biosdev, bvr->part_no); + } + + return 0; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/aml_generator.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/aml_generator.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/aml_generator.c.svn-base (revision 850) @@ -0,0 +1,498 @@ +/* + * aml_generator.c + * Chameleon + * + * Created by Mozodojo on 20/07/10. + * Copyright 2010 mozo. All rights reserved. + * + */ + +#include "aml_generator.h" + +bool aml_add_to_parent(struct aml_chunk* parent, struct aml_chunk* node) +{ + if (parent && node) + { + switch (parent->Type) + { + case AML_CHUNK_NONE: + case AML_CHUNK_BYTE: + case AML_CHUNK_WORD: + case AML_CHUNK_DWORD: + case AML_CHUNK_QWORD: + case AML_CHUNK_ALIAS: + verbose("aml_add_to_parent: node doesn't support child nodes!"); + return false; + case AML_CHUNK_NAME: + if (parent->First) + { + verbose("aml_add_to_parent: name node supports only one child node!"); + return false; + } + break; + + default: + break; + } + + if (!parent->First) + parent->First = node; + + if (parent->Last) + parent->Last->Next = node; + + parent->Last = node; + + return true; + } + + return false; +} + +struct aml_chunk* aml_create_node(struct aml_chunk* parent) +{ + struct aml_chunk* node = (struct aml_chunk*)malloc(sizeof(struct aml_chunk)); + + aml_add_to_parent(parent, node); + + return node; +} + +void aml_destroy_node(struct aml_chunk* node) +{ + // Delete child nodes + struct aml_chunk* child = node->First; + + while (child) + { + struct aml_chunk* next = child->Next; + + if (child->Buffer) + free(child->Buffer); + + free(child); + + child = next; + } + + // Free node + if (node->Buffer) + free(node->Buffer); + + free(node); +} + +struct aml_chunk* aml_add_buffer(struct aml_chunk* parent, const char* buffer, unsigned int size) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_NONE; + node->Length = size; + node->Buffer = malloc(node->Length); + memcpy(node->Buffer, buffer, node->Length); + } + + return node; +} + +struct aml_chunk* aml_add_byte(struct aml_chunk* parent, unsigned char value) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_BYTE; + + node->Length = 1; + node->Buffer = malloc(node->Length); + node->Buffer[0] = value; + } + + return node; +} + +struct aml_chunk* aml_add_word(struct aml_chunk* parent, unsigned int value) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_WORD; + node->Length = 2; + node->Buffer = malloc(node->Length); + node->Buffer[0] = value & 0xff; + node->Buffer[1] = value >> 8; + } + + return node; +} + +struct aml_chunk* aml_add_dword(struct aml_chunk* parent, unsigned long value) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_DWORD; + node->Length = 4; + node->Buffer = malloc(node->Length); + node->Buffer[0] = value & 0xff; + node->Buffer[1] = (value >> 8) & 0xff; + node->Buffer[2] = (value >> 16) & 0xff; + node->Buffer[3] = (value >> 24) & 0xff; + } + + return node; +} + +struct aml_chunk* aml_add_qword(struct aml_chunk* parent, unsigned long long value) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_QWORD; + node->Length = 8; + node->Buffer = malloc(node->Length); + node->Buffer[0] = value & 0xff; + node->Buffer[1] = (value >> 8) & 0xff; + node->Buffer[2] = (value >> 16) & 0xff; + node->Buffer[3] = (value >> 24) & 0xff; + node->Buffer[4] = (value >> 32) & 0xff; + node->Buffer[5] = (value >> 40) & 0xff; + node->Buffer[6] = (value >> 48) & 0xff; + node->Buffer[7] = (value >> 56) & 0xff; + } + + return node; +} + +unsigned int aml_fill_simple_name(char* buffer, const char* name) +{ + if (strlen(name) < 4) + { + verbose("aml_fill_simple_name: simple name %s has incorrect lengh! Must be 4.", name); + return 0; + } + + memcpy(buffer, name, 4); + return 4; +} + +unsigned int aml_fill_name(struct aml_chunk* node, const char* name) +{ + if (!node) + return 0; + + int len = strlen(name), offset = 0, count = len / 4; + + if ((len % 4) > 1 || count == 0) + { + verbose("aml_fill_name: pathname %s has incorrect length! Must be 4, 8, 12, 16, etc...", name); + return 0; + } + + unsigned int root = 0; + + if ((len % 4) == 1 && name[0] == '\\') + root++; + + if (count == 1) + { + node->Length = 4 + root; + node->Buffer = malloc(node->Length); + memcpy(node->Buffer, name, 4 + root); + return node->Length; + } + + if (count == 2) + { + node->Length = 2 + 8; + node->Buffer = malloc(node->Length); + node->Buffer[offset++] = 0x5c; // Root Char + node->Buffer[offset++] = 0x2e; // Double name + memcpy(node->Buffer+offset, name + root, 8); + return node->Length; + } + + node->Length = 3 + count*4; + node->Buffer = malloc(node->Length); + node->Buffer[offset++] = 0x5c; // Root Char + node->Buffer[offset++] = 0x2f; // Multi name + node->Buffer[offset++] = count; // Names count + memcpy(node->Buffer+offset, name + root, count*4); + + return node->Length; +} + +struct aml_chunk* aml_add_scope(struct aml_chunk* parent, const char* name) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_SCOPE; + + aml_fill_name(node, name); + } + + return node; +} + +struct aml_chunk* aml_add_name(struct aml_chunk* parent, const char* name) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_NAME; + + aml_fill_name(node, name); + } + + return node; +} + +struct aml_chunk* aml_add_package(struct aml_chunk* parent) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_PACKAGE; + + node->Length = 1; + node->Buffer = malloc(node->Length); + } + + return node; +} + +struct aml_chunk* aml_add_alias(struct aml_chunk* parent, const char* name1, const char* name2) +{ + struct aml_chunk* node = aml_create_node(parent); + + if (node) + { + node->Type = AML_CHUNK_ALIAS; + + node->Length = 8; + node->Buffer = malloc(node->Length); + aml_fill_simple_name(node->Buffer, name1); + aml_fill_simple_name(node->Buffer+4, name2); + } + + return node; +} + +unsigned char aml_get_size_length(unsigned int size) +{ + if (size + 1 <= 0x3f) + return 1; + else if (size + 2 <= 0x3fff) + return 2; + else if (size + 3 <= 0x3fffff) + return 3; + + return 4; +} + +unsigned int aml_calculate_size(struct aml_chunk* node) +{ + if (node) + { + node->Size = 0; + + // Calculate child nodes size + struct aml_chunk* child = node->First; + unsigned char child_count = 0; + + while (child) + { + child_count++; + + node->Size += aml_calculate_size(child); + + child = child->Next; + } + + switch (node->Type) + { + case AML_CHUNK_NONE: + node->Size += node->Length; + break; + case AML_CHUNK_SCOPE: + node->Size += 1 + node->Length; + node->Size += aml_get_size_length(node->Size); + break; + case AML_CHUNK_PACKAGE: + node->Buffer[0] = child_count; + node->Size += 1 + node->Length; + node->Size += aml_get_size_length(node->Size); + break; + + case AML_CHUNK_BYTE: + if (node->Buffer[0] == 0x0 || node->Buffer[0] == 0x1) + { + node->Size += node->Length; + } + else + { + node->Size += 1 + node->Length; + } + + break; + + case AML_CHUNK_WORD: + case AML_CHUNK_DWORD: + case AML_CHUNK_QWORD: + case AML_CHUNK_ALIAS: + case AML_CHUNK_NAME: + node->Size += 1 + node->Length; + break; + } + + return node->Size; + } + + return 0; +} + +unsigned int aml_write_byte(unsigned char value, char* buffer, unsigned int offset) +{ + buffer[offset++] = value; + + return offset; +} + +unsigned int aml_write_word(unsigned int value, char* buffer, unsigned int offset) +{ + buffer[offset++] = value & 0xff; + buffer[offset++] = value >> 8; + + return offset; +} + +unsigned int aml_write_dword(unsigned long value, char* buffer, unsigned int offset) +{ + buffer[offset++] = value & 0xff; + buffer[offset++] = (value >> 8) & 0xff; + buffer[offset++] = (value >> 16) & 0xff; + buffer[offset++] = (value >> 24) & 0xff; + + return offset; +} + +unsigned int aml_write_qword(unsigned long long value, char* buffer, unsigned int offset) +{ + buffer[offset++] = value & 0xff; + buffer[offset++] = (value >> 8) & 0xff; + buffer[offset++] = (value >> 16) & 0xff; + buffer[offset++] = (value >> 24) & 0xff; + buffer[offset++] = (value >> 32) & 0xff; + buffer[offset++] = (value >> 40) & 0xff; + buffer[offset++] = (value >> 48) & 0xff; + buffer[offset++] = (value >> 56) & 0xff; + + return offset; +} + +unsigned int aml_write_buffer(const char* value, unsigned int size, char* buffer, unsigned int offset) +{ + if (size > 0) + { + memcpy(buffer + offset, value, size); + } + + return offset + size; +} + +unsigned int aml_write_size(unsigned int size, char* buffer, unsigned int offset) +{ + if (size <= 0x3f) + { + buffer[offset++] = size; + } + else if (size <= 0x3fff) + { + buffer[offset++] = 0x40 | (size & 0xf); + buffer[offset++] = (size >> 4) & 0xff; + } + else if (size <= 0x3fffff) + { + buffer[offset++] = 0x80 | (size & 0xf); + buffer[offset++] = (size >> 4) & 0xff; + buffer[offset++] = (size >> 12) & 0xff; + } + else + { + buffer[offset++] = 0xc0 | (size & 0xf); + buffer[offset++] = (size >> 4) & 0xff; + buffer[offset++] = (size >> 12) & 0xff; + buffer[offset++] = (size >> 20) & 0xff; + } + + return offset; +} + +unsigned int aml_write_node(struct aml_chunk* node, char* buffer, unsigned int offset) +{ + if (node && buffer) + { + unsigned int old = offset; + + switch (node->Type) + { + case AML_CHUNK_NONE: + offset = aml_write_buffer(node->Buffer, node->Length, buffer, offset); + break; + + case AML_CHUNK_SCOPE: + case AML_CHUNK_PACKAGE: + offset = aml_write_byte(node->Type, buffer, offset); + offset = aml_write_size(node->Size-1, buffer, offset); + offset = aml_write_buffer(node->Buffer, node->Length, buffer, offset); + break; + + case AML_CHUNK_BYTE: + if (node->Buffer[0] == 0x0 || node->Buffer[0] == 0x1) + { + offset = aml_write_buffer(node->Buffer, node->Length, buffer, offset); + } + else + { + offset = aml_write_byte(node->Type, buffer, offset); + offset = aml_write_buffer(node->Buffer, node->Length, buffer, offset); + } + break; + + case AML_CHUNK_WORD: + case AML_CHUNK_DWORD: + case AML_CHUNK_QWORD: + case AML_CHUNK_ALIAS: + case AML_CHUNK_NAME: + offset = aml_write_byte(node->Type, buffer, offset); + offset = aml_write_buffer(node->Buffer, node->Length, buffer, offset); + break; + + default: + break; + } + + struct aml_chunk* child = node->First; + + while (child) + { + offset = aml_write_node(child, buffer, offset); + + child = child->Next; + } + + if (offset - old != node->Size) + verbose("Node size incorrect: 0x%x\n", node->Type); + } + + return offset; +} \ No newline at end of file Index: branches/Chimera/i386/libsaio/.svn/text-base/hfs.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/hfs.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/hfs.c.svn-base (revision 850) @@ -0,0 +1,1064 @@ +/* + * Copyright (c) 2000-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * hfs.c - File System Module for HFS and HFS+. + * + * Copyright (c) 1999-2002 Apple Computer, Inc. + * + * DRI: Josh de Cesare + */ + +#include +#include + +#include "hfs.h" + +#define kBlockSize (0x200) + +#define kMDBBaseOffset (2 * kBlockSize) + +#define kBTreeCatalog (0) +#define kBTreeExtents (1) + +#ifdef __i386__ + +static CICell gCurrentIH; +static long long gAllocationOffset; +static long gIsHFSPlus; +static long gCaseSensitive; +static long gBlockSize; +static long gCacheBlockSize; +static char *gBTreeHeaderBuffer; +static BTHeaderRec *gBTHeaders[2]; +static char *gHFSMdbVib; +static HFSMasterDirectoryBlock *gHFSMDB; +static char *gHFSPlusHeader; +static HFSPlusVolumeHeader *gHFSPlus; +static char *gLinkTemp; +static long long gVolID; +static char *gTempStr; + +#else /* !__i386__ */ + +static CICell gCurrentIH; +static long long gAllocationOffset; +static long gIsHFSPlus; +static long gBlockSize; +static long gCaseSensitive; +static long gCacheBlockSize; +static char gBTreeHeaderBuffer[512]; +static BTHeaderRec *gBTHeaders[2]; +static char gHFSMdbVib[kBlockSize]; +static HFSMasterDirectoryBlock *gHFSMDB =(HFSMasterDirectoryBlock*)gHFSMdbVib; +static char gHFSPlusHeader[kBlockSize]; +static HFSPlusVolumeHeader *gHFSPlus =(HFSPlusVolumeHeader*)gHFSPlusHeader; +static char gLinkTemp[64]; +static long long gVolID; + +#endif /* !__i386__ */ + +static long ReadFile(void *file, uint64_t *length, void *base, uint64_t offset); +static long GetCatalogEntryInfo(void *entry, long *flags, long *time, + FinderInfo *finderInfo, long *infoValid); +static long ResolvePathToCatalogEntry(char *filePath, long *flags, + void *entry, long dirID, long long *dirIndex); + +static long GetCatalogEntry(long long *dirIndex, char **name, + long *flags, long *time, + FinderInfo *finderInfo, long *infoValid); +static long ReadCatalogEntry(char *fileName, long dirID, void *entry, + long long *dirIndex); +static long ReadExtentsEntry(long fileID, long startBlock, void *entry); + +static long ReadBTreeEntry(long btree, void *key, char *entry, long long *dirIndex); +static void GetBTreeRecord(long index, char *nodeBuffer, long nodeSize, + char **key, char **data); + +static long ReadExtent(char *extent, uint64_t extentSize, long extentFile, + uint64_t offset, uint64_t size, void *buffer, long cache); + +static long GetExtentStart(void *extents, long index); +static long GetExtentSize(void *extents, long index); + +static long CompareHFSCatalogKeys(void *key, void *testKey); +static long CompareHFSPlusCatalogKeys(void *key, void *testKey); +static long CompareHFSExtentsKeys(void *key, void *testKey); +static long CompareHFSPlusExtentsKeys(void *key, void *testKey); + +extern long FastRelString(u_int8_t *str1, u_int8_t *str2); +extern long BinaryUnicodeCompare(u_int16_t *uniStr1, u_int32_t len1, + u_int16_t *uniStr2, u_int32_t len2); + + +static void SwapFinderInfo(FndrFileInfo *dst, FndrFileInfo *src) +{ + dst->fdType = SWAP_BE32(src->fdType); + dst->fdCreator = SWAP_BE32(src->fdCreator); + dst->fdFlags = SWAP_BE16(src->fdFlags); + // Don't bother with location +} + +void HFSFree(CICell ih) +{ + if(gCurrentIH == ih) + gCurrentIH = 0; + free(ih); +} + +bool HFSProbe (const void *buf) +{ + const HFSMasterDirectoryBlock *mdb; + const HFSPlusVolumeHeader *header; + mdb=(const HFSMasterDirectoryBlock *)(((const char*)buf)+kMDBBaseOffset); + header=(const HFSPlusVolumeHeader *)(((const char*)buf)+kMDBBaseOffset); + + if ( SWAP_BE16(mdb->drSigWord) == kHFSSigWord ) + return true; + if (SWAP_BE16(header->signature) != kHFSPlusSigWord && + SWAP_BE16(header->signature) != kHFSXSigWord) + return false; + return true; +} + +long HFSInitPartition(CICell ih) +{ + long extentSize, extentFile, nodeSize; + void *extent; + + if (ih == gCurrentIH) { +#ifdef __i386__ + CacheInit(ih, gCacheBlockSize); +#endif + return 0; + } + +#ifdef __i386__ + if (!gTempStr) gTempStr = (char *)malloc(4096); + if (!gLinkTemp) gLinkTemp = (char *)malloc(64); + if (!gBTreeHeaderBuffer) gBTreeHeaderBuffer = (char *)malloc(512); + if (!gHFSMdbVib) { + gHFSMdbVib = (char *)malloc(kBlockSize); + gHFSMDB = (HFSMasterDirectoryBlock *)gHFSMdbVib; + } + if (!gHFSPlusHeader) { + gHFSPlusHeader = (char *)malloc(kBlockSize); + gHFSPlus = (HFSPlusVolumeHeader *)gHFSPlusHeader; + } + if (!gTempStr || !gLinkTemp || !gBTreeHeaderBuffer || + !gHFSMdbVib || !gHFSPlusHeader) return -1; +#endif /* __i386__ */ + + gAllocationOffset = 0; + gIsHFSPlus = 0; + gCaseSensitive = 0; + gBTHeaders[0] = 0; + gBTHeaders[1] = 0; + + // Look for the HFS MDB + Seek(ih, kMDBBaseOffset); + Read(ih, (long)gHFSMdbVib, kBlockSize); + + if ( SWAP_BE16(gHFSMDB->drSigWord) == kHFSSigWord ) { + gAllocationOffset = SWAP_BE16(gHFSMDB->drAlBlSt) * kBlockSize; + + // See if it is HFSPlus + if (SWAP_BE16(gHFSMDB->drEmbedSigWord) != kHFSPlusSigWord) { + // Normal HFS; + gCacheBlockSize = gBlockSize = SWAP_BE32(gHFSMDB->drAlBlkSiz); + CacheInit(ih, gCacheBlockSize); + gCurrentIH = ih; + + // grab the 64 bit volume ID + bcopy(&gHFSMDB->drFndrInfo[6], &gVolID, 8); + + // Get the Catalog BTree node size. + extent = (HFSExtentDescriptor *)&gHFSMDB->drCTExtRec; + extentSize = SWAP_BE32(gHFSMDB->drCTFlSize); + extentFile = kHFSCatalogFileID; + ReadExtent(extent, extentSize, extentFile, 0, 256, + gBTreeHeaderBuffer + kBTreeCatalog * 256, 0); + + nodeSize = SWAP_BE16(((BTHeaderRec *)(gBTreeHeaderBuffer + kBTreeCatalog * 256 + + sizeof(BTNodeDescriptor)))->nodeSize); + + // If the BTree node size is larger than the block size, reset the cache. + if (nodeSize > gBlockSize) { + gCacheBlockSize = nodeSize; + CacheInit(ih, gCacheBlockSize); + } + + return 0; + } + + // Calculate the offset to the embeded HFSPlus volume. + gAllocationOffset += (long long)SWAP_BE16(gHFSMDB->drEmbedExtent.startBlock) * + SWAP_BE32(gHFSMDB->drAlBlkSiz); + } + + // Look for the HFSPlus Header + Seek(ih, gAllocationOffset + kMDBBaseOffset); + Read(ih, (long)gHFSPlusHeader, kBlockSize); + + // Not a HFS+ or HFSX volume. + if (SWAP_BE16(gHFSPlus->signature) != kHFSPlusSigWord && + SWAP_BE16(gHFSPlus->signature) != kHFSXSigWord) { + verbose("HFS signature was not present.\n"); + gCurrentIH = 0; + return -1; + } + + gIsHFSPlus = 1; + gCacheBlockSize = gBlockSize = SWAP_BE32(gHFSPlus->blockSize); + CacheInit(ih, gCacheBlockSize); + gCurrentIH = ih; + + ih->modTime = SWAP_BE32(gHFSPlus->modifyDate) - 2082844800; + + // grab the 64 bit volume ID + bcopy(&gHFSPlus->finderInfo[24], &gVolID, 8); + + // Get the Catalog BTree node size. + extent = &gHFSPlus->catalogFile.extents; + extentSize = SWAP_BE64(gHFSPlus->catalogFile.logicalSize); + extentFile = kHFSCatalogFileID; + + ReadExtent(extent, extentSize, extentFile, 0, 256, + gBTreeHeaderBuffer + kBTreeCatalog * 256, 0); + + nodeSize = SWAP_BE16(((BTHeaderRec *)(gBTreeHeaderBuffer + kBTreeCatalog * 256 + + sizeof(BTNodeDescriptor)))->nodeSize); + + // If the BTree node size is larger than the block size, reset the cache. + if (nodeSize > gBlockSize) { + gCacheBlockSize = nodeSize; + CacheInit(ih, gCacheBlockSize); + } + + return 0; +} + +long HFSLoadFile(CICell ih, char * filePath) +{ + return HFSReadFile(ih, filePath, (void *)gFSLoadAddress, 0, 0); +} + +long HFSReadFile(CICell ih, char * filePath, void *base, uint64_t offset, uint64_t length) +{ + char entry[512]; + char devStr[12]; + long dirID, result, flags; + + if (HFSInitPartition(ih) == -1) return -1; + + dirID = kHFSRootFolderID; + // Skip a lead '\'. Start in the system folder if there are two. + if (filePath[0] == '/') { + if (filePath[1] == '/') { + if (gIsHFSPlus) dirID = SWAP_BE32(((long *)gHFSPlus->finderInfo)[5]); + else dirID = SWAP_BE32(gHFSMDB->drFndrInfo[5]); + if (dirID == 0) { + return -1; + } + filePath++; + } + filePath++; + } + + result = ResolvePathToCatalogEntry(filePath, &flags, entry, dirID, 0); + if ((result == -1) || ((flags & kFileTypeMask) != kFileTypeFlat)) { + return -1; + } + +#if UNUSED + // Not yet for Intel. System.config/Default.table will fail this check. + // Check file owner and permissions. + if (flags & (kOwnerNotRoot | kPermGroupWrite | kPermOtherWrite)) return -1; +#endif + + result = ReadFile(entry, &length, base, offset); + if (result == -1) { + return -1; + } + + getDeviceDescription(ih, devStr); + verbose("Read HFS%s file: [%s/%s] %d bytes.\n", + (gIsHFSPlus ? "+" : ""), devStr, filePath, (uint32_t)length); + + return length; +} + +long HFSGetDirEntry(CICell ih, char * dirPath, long long * dirIndex, char ** name, + long * flags, long * time, + FinderInfo * finderInfo, long * infoValid) +{ + char entry[512]; + long dirID, dirFlags; + + if (HFSInitPartition(ih) == -1) return -1; + + if (*dirIndex == -1) return -1; + + dirID = kHFSRootFolderID; + // Skip a lead '\'. Start in the system folder if there are two. + if (dirPath[0] == '/') { + if (dirPath[1] == '/') { + if (gIsHFSPlus) dirID = SWAP_BE32(((long *)gHFSPlus->finderInfo)[5]); + else dirID = SWAP_BE32(gHFSMDB->drFndrInfo[5]); + if (dirID == 0) return -1; + dirPath++; + } + dirPath++; + } + + if (*dirIndex == 0) { + ResolvePathToCatalogEntry(dirPath, &dirFlags, entry, dirID, dirIndex); + if (*dirIndex == 0) *dirIndex = -1; + if ((dirFlags & kFileTypeMask) != kFileTypeUnknown) return -1; + } + + GetCatalogEntry(dirIndex, name, flags, time, finderInfo, infoValid); + if (*dirIndex == 0) *dirIndex = -1; + if ((*flags & kFileTypeMask) == kFileTypeUnknown) return -1; + + return 0; +} + +void +HFSGetDescription(CICell ih, char *str, long strMaxLen) +{ + + UInt16 nodeSize; + UInt32 firstLeafNode; + long long dirIndex; + char *name; + long flags, time; + + if (HFSInitPartition(ih) == -1) { return; } + + /* Fill some crucial data structures by side effect. */ + dirIndex = 0; + HFSGetDirEntry(ih, "/", &dirIndex, &name, &flags, &time, 0, 0); + + /* Now we can loook up the volume name node. */ + nodeSize = SWAP_BE16(gBTHeaders[kBTreeCatalog]->nodeSize); + firstLeafNode = SWAP_BE32(gBTHeaders[kBTreeCatalog]->firstLeafNode); + + dirIndex = (long long) firstLeafNode * nodeSize; + + GetCatalogEntry(&dirIndex, &name, &flags, &time, 0, 0); + + strncpy(str, name, strMaxLen); + str[strMaxLen] = '\0'; +} + + +long +HFSGetFileBlock(CICell ih, char *filePath, unsigned long long *firstBlock) +{ + char entry[512]; + long dirID, result, flags; + void *extents; + HFSCatalogFile *hfsFile = (void *)entry; + HFSPlusCatalogFile *hfsPlusFile = (void *)entry; + + if (HFSInitPartition(ih) == -1) return -1; + + dirID = kHFSRootFolderID; + // Skip a lead '\'. Start in the system folder if there are two. + if (filePath[0] == '/') { + if (filePath[1] == '/') { + if (gIsHFSPlus) dirID = SWAP_BE32(((long *)gHFSPlus->finderInfo)[5]); + else dirID = SWAP_BE32(gHFSMDB->drFndrInfo[5]); + if (dirID == 0) { + return -1; + } + filePath++; + } + filePath++; + } + + result = ResolvePathToCatalogEntry(filePath, &flags, entry, dirID, 0); + if ((result == -1) || ((flags & kFileTypeMask) != kFileTypeFlat)) { + printf("HFS: Resolve path %s failed\n", filePath); + return -1; + } + + if (gIsHFSPlus) { + extents = &hfsPlusFile->dataFork.extents; + } else { + extents = &hfsFile->dataExtents; + } + +#if DEBUG + printf("extent start 0x%x\n", (unsigned long)GetExtentStart(extents, 0)); + printf("block size 0x%x\n", (unsigned long)gBlockSize); + printf("Allocation offset 0x%x\n", (unsigned long)gAllocationOffset); +#endif + *firstBlock = ((unsigned long long)GetExtentStart(extents, 0) * (unsigned long long) gBlockSize + gAllocationOffset) / 512ULL; + return 0; +} + +long HFSGetUUID(CICell ih, char *uuidStr) +{ + if (HFSInitPartition(ih) == -1) return -1; + if (gVolID == 0LL) return -1; + + return CreateUUIDString((uint8_t*)(&gVolID), sizeof(gVolID), uuidStr); +} + +// Private Functions + +static long ReadFile(void * file, uint64_t * length, void * base, uint64_t offset) +{ + void *extents; + long fileID; + uint64_t fileLength; + HFSCatalogFile *hfsFile = file; + HFSPlusCatalogFile *hfsPlusFile = file; + + if (gIsHFSPlus) { + fileID = SWAP_BE32(hfsPlusFile->fileID); + fileLength = (uint64_t)SWAP_BE64(hfsPlusFile->dataFork.logicalSize); + extents = &hfsPlusFile->dataFork.extents; + } else { + fileID = SWAP_BE32(hfsFile->fileID); + fileLength = SWAP_BE32(hfsFile->dataLogicalSize); + extents = &hfsFile->dataExtents; + } + + if (offset > fileLength) { + printf("Offset is too large.\n"); + return -1; + } + + if ((*length == 0) || ((offset + *length) > fileLength)) { + *length = fileLength - offset; + } + +/* if (*length > kLoadSize) { + printf("File is too large.\n"); + return -1; + }*/ + + *length = ReadExtent((char *)extents, fileLength, fileID, + offset, *length, (char *)base, 0); + + return 0; +} + +static long GetCatalogEntryInfo(void * entry, long * flags, long * time, + FinderInfo * finderInfo, long * infoValid) +{ + long tmpTime = 0; + long valid = 0; + + // Get information about the file. + + switch ( SWAP_BE16(*(short *)entry) ) + { + case kHFSFolderRecord : + *flags = kFileTypeDirectory; + tmpTime = SWAP_BE32(((HFSCatalogFolder *)entry)->modifyDate); + break; + + case kHFSPlusFolderRecord : + *flags = kFileTypeDirectory | + (SWAP_BE16(((HFSPlusCatalogFolder *)entry)->bsdInfo.fileMode) & kPermMask); + if (SWAP_BE32(((HFSPlusCatalogFolder *)entry)->bsdInfo.ownerID) != 0) + *flags |= kOwnerNotRoot; + tmpTime = SWAP_BE32(((HFSPlusCatalogFolder *)entry)->contentModDate); + break; + + case kHFSFileRecord : + *flags = kFileTypeFlat; + tmpTime = SWAP_BE32(((HFSCatalogFile *)entry)->modifyDate); + if (finderInfo) { + SwapFinderInfo((FndrFileInfo *)finderInfo, &((HFSCatalogFile *)entry)->userInfo); + valid = 1; + } + break; + + case kHFSPlusFileRecord : + *flags = kFileTypeFlat | + (SWAP_BE16(((HFSPlusCatalogFile *)entry)->bsdInfo.fileMode) & kPermMask); + if (SWAP_BE32(((HFSPlusCatalogFile *)entry)->bsdInfo.ownerID) != 0) + *flags |= kOwnerNotRoot; + tmpTime = SWAP_BE32(((HFSPlusCatalogFile *)entry)->contentModDate); + if (finderInfo) { + SwapFinderInfo((FndrFileInfo *)finderInfo, &((HFSPlusCatalogFile *)entry)->userInfo); + valid = 1; + } + break; + + case kHFSFileThreadRecord : + case kHFSPlusFileThreadRecord : + case kHFSFolderThreadRecord : + case kHFSPlusFolderThreadRecord : + *flags = kFileTypeUnknown; + tmpTime = 0; + break; + } + + if (time != 0) { + // Convert base time from 1904 to 1970. + *time = tmpTime - 2082844800; + } + if (infoValid) *infoValid = valid; + + return 0; +} + +static long ResolvePathToCatalogEntry(char * filePath, long * flags, + void * entry, long dirID, long long * dirIndex) +{ + char *restPath; + long result, cnt, subFolderID = 0; + long long tmpDirIndex; + HFSPlusCatalogFile *hfsPlusFile; + + // Copy the file name to gTempStr + cnt = 0; + while ((filePath[cnt] != '/') && (filePath[cnt] != '\0')) cnt++; + strlcpy(gTempStr, filePath, cnt+1); + + // Move restPath to the right place. + if (filePath[cnt] != '\0') cnt++; + restPath = filePath + cnt; + + // gTempStr is a name in the current Dir. + // restPath is the rest of the path if any. + + result = ReadCatalogEntry(gTempStr, dirID, entry, dirIndex); + if (result == -1) { + return -1; + } + + GetCatalogEntryInfo(entry, flags, 0, 0, 0); + + if ((*flags & kFileTypeMask) == kFileTypeDirectory) { + if (gIsHFSPlus) + subFolderID = SWAP_BE32(((HFSPlusCatalogFolder *)entry)->folderID); + else + subFolderID = SWAP_BE32(((HFSCatalogFolder *)entry)->folderID); + } + + if ((*flags & kFileTypeMask) == kFileTypeDirectory) + result = ResolvePathToCatalogEntry(restPath, flags, entry, + subFolderID, dirIndex); + + if (gIsHFSPlus && ((*flags & kFileTypeMask) == kFileTypeFlat)) { + hfsPlusFile = (HFSPlusCatalogFile *)entry; + if ((SWAP_BE32(hfsPlusFile->userInfo.fdType) == kHardLinkFileType) && + (SWAP_BE32(hfsPlusFile->userInfo.fdCreator) == kHFSPlusCreator)) { + sprintf(gLinkTemp, "%s/%s%ld", HFSPLUSMETADATAFOLDER, + HFS_INODE_PREFIX, SWAP_BE32(hfsPlusFile->bsdInfo.special.iNodeNum)); + result = ResolvePathToCatalogEntry(gLinkTemp, flags, entry, + kHFSRootFolderID, &tmpDirIndex); + } + } + + return result; +} + +static long GetCatalogEntry(long long * dirIndex, char ** name, + long * flags, long * time, + FinderInfo * finderInfo, long * infoValid) +{ + long extentSize, nodeSize, curNode, index; + void *extent; + char *nodeBuf, *testKey, *entry; + BTNodeDescriptor *node; + + if (gIsHFSPlus) { + extent = &gHFSPlus->catalogFile.extents; + extentSize = SWAP_BE64(gHFSPlus->catalogFile.logicalSize); + } else { + extent = (HFSExtentDescriptor *)&gHFSMDB->drCTExtRec; + extentSize = SWAP_BE32(gHFSMDB->drCTFlSize); + } + + nodeSize = SWAP_BE16(gBTHeaders[kBTreeCatalog]->nodeSize); + nodeBuf = (char *)malloc(nodeSize); + node = (BTNodeDescriptor *)nodeBuf; + + index = (long) (*dirIndex % nodeSize); + curNode = (long) (*dirIndex / nodeSize); + + // Read the BTree node and get the record for index. + ReadExtent(extent, extentSize, kHFSCatalogFileID, + (long long) curNode * nodeSize, nodeSize, nodeBuf, 1); + GetBTreeRecord(index, nodeBuf, nodeSize, &testKey, &entry); + + GetCatalogEntryInfo(entry, flags, time, finderInfo, infoValid); + + // Get the file name. + if (gIsHFSPlus) { + utf_encodestr(((HFSPlusCatalogKey *)testKey)->nodeName.unicode, + SWAP_BE16(((HFSPlusCatalogKey *)testKey)->nodeName.length), + (u_int8_t *)gTempStr, 256, OSBigEndian); + } else { + strncpy(gTempStr, + (const char *)&((HFSCatalogKey *)testKey)->nodeName[1], + ((HFSCatalogKey *)testKey)->nodeName[0]); + gTempStr[((HFSCatalogKey *)testKey)->nodeName[0]] = '\0'; + } + *name = gTempStr; + + // Update dirIndex. + index++; + if (index == SWAP_BE16(node->numRecords)) { + index = 0; + curNode = SWAP_BE32(node->fLink); + } + *dirIndex = (long long) curNode * nodeSize + index; + + free(nodeBuf); + + return 0; +} + +static long ReadCatalogEntry(char * fileName, long dirID, + void * entry, long long * dirIndex) +{ + long length; + char key[sizeof(HFSPlusCatalogKey)]; + HFSCatalogKey *hfsKey = (HFSCatalogKey *)key; + HFSPlusCatalogKey *hfsPlusKey = (HFSPlusCatalogKey *)key; + + // Make the catalog key. + if ( gIsHFSPlus ) + { + hfsPlusKey->parentID = SWAP_BE32(dirID); + length = strlen(fileName); + if (length > 255) length = 255; + utf_decodestr((u_int8_t *)fileName, hfsPlusKey->nodeName.unicode, + &(hfsPlusKey->nodeName.length), 512, OSBigEndian); + } else { + hfsKey->parentID = SWAP_BE32(dirID); + length = strlen(fileName); + if (length > 31) length = 31; + hfsKey->nodeName[0] = length; + strncpy((char *)(hfsKey->nodeName + 1), fileName, length); + } + + return ReadBTreeEntry(kBTreeCatalog, &key, entry, dirIndex); +} + +static long ReadExtentsEntry(long fileID, long startBlock, void * entry) +{ + char key[sizeof(HFSPlusExtentKey)]; + HFSExtentKey *hfsKey = (HFSExtentKey *)key; + HFSPlusExtentKey *hfsPlusKey = (HFSPlusExtentKey *)key; + + // Make the extents key. + if (gIsHFSPlus) { + hfsPlusKey->forkType = 0; + hfsPlusKey->fileID = SWAP_BE32(fileID); + hfsPlusKey->startBlock = SWAP_BE32(startBlock); + } else { + hfsKey->forkType = 0; + hfsKey->fileID = SWAP_BE32(fileID); + hfsKey->startBlock = SWAP_BE16(startBlock); + } + + return ReadBTreeEntry(kBTreeExtents, &key, entry, 0); +} + +static long ReadBTreeEntry(long btree, void * key, char * entry, long long * dirIndex) +{ + long extentSize; + void *extent; + short extentFile; + char *nodeBuf; + BTNodeDescriptor *node; + long nodeSize, result = 0, entrySize = 0; + long curNode, index = 0, lowerBound, upperBound; + char *testKey, *recordData; + + // Figure out which tree is being looked at. + if (btree == kBTreeCatalog) { + if (gIsHFSPlus) { + extent = &gHFSPlus->catalogFile.extents; + extentSize = SWAP_BE64(gHFSPlus->catalogFile.logicalSize); + } else { + extent = (HFSExtentDescriptor *)&gHFSMDB->drCTExtRec; + extentSize = SWAP_BE32(gHFSMDB->drCTFlSize); + } + extentFile = kHFSCatalogFileID; + } else { + if (gIsHFSPlus) { + extent = &gHFSPlus->extentsFile.extents; + extentSize = SWAP_BE64(gHFSPlus->extentsFile.logicalSize); + } else { + extent = (HFSExtentDescriptor *)&gHFSMDB->drXTExtRec; + extentSize = SWAP_BE32(gHFSMDB->drXTFlSize); + } + extentFile = kHFSExtentsFileID; + } + + // Read the BTree Header if needed. + if (gBTHeaders[btree] == 0) { + ReadExtent(extent, extentSize, extentFile, 0, 256, + gBTreeHeaderBuffer + btree * 256, 0); + gBTHeaders[btree] = (BTHeaderRec *)(gBTreeHeaderBuffer + btree * 256 + + sizeof(BTNodeDescriptor)); + if ((gIsHFSPlus && btree == kBTreeCatalog) && + (gBTHeaders[btree]->keyCompareType == kHFSBinaryCompare)) { + gCaseSensitive = 1; + } + } + + curNode = SWAP_BE32(gBTHeaders[btree]->rootNode); + nodeSize = SWAP_BE16(gBTHeaders[btree]->nodeSize); + nodeBuf = (char *)malloc(nodeSize); + node = (BTNodeDescriptor *)nodeBuf; + + while (1) { + // Read the current node. + ReadExtent(extent, extentSize, extentFile, + (long long) curNode * nodeSize, nodeSize, nodeBuf, 1); + + // Find the matching key. + lowerBound = 0; + upperBound = SWAP_BE16(node->numRecords) - 1; + while (lowerBound <= upperBound) { + index = (lowerBound + upperBound) / 2; + + GetBTreeRecord(index, nodeBuf, nodeSize, &testKey, &recordData); + + if (gIsHFSPlus) { + if (btree == kBTreeCatalog) { + result = CompareHFSPlusCatalogKeys(key, testKey); + } else { + result = CompareHFSPlusExtentsKeys(key, testKey); + } + } else { + if (btree == kBTreeCatalog) { + result = CompareHFSCatalogKeys(key, testKey); + } else { + result = CompareHFSExtentsKeys(key, testKey); + } + } + + if (result < 0) upperBound = index - 1; // search < trial + else if (result > 0) lowerBound = index + 1; // search > trial + else break; // search = trial + } + + if (result < 0) { + index = upperBound; + GetBTreeRecord(index, nodeBuf, nodeSize, &testKey, &recordData); + } + + // Found the closest key... Recurse on it if this is an index node. + if (node->kind == kBTIndexNode) { + curNode = SWAP_BE32( *((long *)recordData) ); + } else break; + } + + // Return error if the file was not found. + if (result != 0) { free(nodeBuf); return -1; } + + if (btree == kBTreeCatalog) { + switch (SWAP_BE16(*(short *)recordData)) { + case kHFSFolderRecord : entrySize = 70; break; + case kHFSFileRecord : entrySize = 102; break; + case kHFSFolderThreadRecord : entrySize = 46; break; + case kHFSFileThreadRecord : entrySize = 46; break; + case kHFSPlusFolderRecord : entrySize = 88; break; + case kHFSPlusFileRecord : entrySize = 248; break; + case kHFSPlusFolderThreadRecord : entrySize = 264; break; + case kHFSPlusFileThreadRecord : entrySize = 264; break; + } + } else { + if (gIsHFSPlus) entrySize = sizeof(HFSPlusExtentRecord); + else entrySize = sizeof(HFSExtentRecord); + } + + bcopy(recordData, entry, entrySize); + + // Update dirIndex. + if (dirIndex != 0) { + index++; + if (index == SWAP_BE16(node->numRecords)) { + index = 0; + curNode = SWAP_BE32(node->fLink); + } + *dirIndex = (long long) curNode * nodeSize + index; + } + + free(nodeBuf); + + return 0; +} + +static void GetBTreeRecord(long index, char * nodeBuffer, long nodeSize, + char ** key, char ** data) +{ + long keySize; + long recordOffset; + + recordOffset = SWAP_BE16(*((short *)(nodeBuffer + (nodeSize - 2 * index - 2)))); + *key = nodeBuffer + recordOffset; + if (gIsHFSPlus) { + keySize = SWAP_BE16(*(short *)*key); + *data = *key + 2 + keySize; + } else { + keySize = **key; + *data = *key + 2 + keySize - (keySize & 1); + } +} + +static long ReadExtent(char * extent, uint64_t extentSize, + long extentFile, uint64_t offset, uint64_t size, + void * buffer, long cache) +{ + uint64_t lastOffset; + long long blockNumber, countedBlocks = 0; + long long nextExtent = 0, sizeRead = 0, readSize; + long long nextExtentBlock, currentExtentBlock = 0; + long long readOffset; + long long extentDensity, sizeofExtent, currentExtentSize; + char *currentExtent, *extentBuffer = 0, *bufferPos = buffer; + + if (offset >= extentSize) return 0; + + if (gIsHFSPlus) { + extentDensity = kHFSPlusExtentDensity; + sizeofExtent = sizeof(HFSPlusExtentDescriptor); + } else { + extentDensity = kHFSExtentDensity; + sizeofExtent = sizeof(HFSExtentDescriptor); + } + + lastOffset = offset + size; + while (offset < lastOffset) { + blockNumber = offset / gBlockSize; + + // Find the extent for the offset. + for (; ; nextExtent++) { + if (nextExtent < extentDensity) { + if ((countedBlocks+GetExtentSize(extent, nextExtent)-1)= blockNumber) { + currentExtent = extentBuffer + sizeofExtent * (nextExtent % extentDensity); + break; + } + + countedBlocks += currentExtentSize; + } + + readOffset = ((blockNumber - countedBlocks) * gBlockSize) + + (offset % gBlockSize); + + // MacWen: fix overflow in multiplication by forcing 64bit multiplication + readSize = (long long)GetExtentSize(currentExtent, 0) * gBlockSize - readOffset; + if (readSize > (size - sizeRead)) readSize = size - sizeRead; + + readOffset += (long long)GetExtentStart(currentExtent, 0) * gBlockSize; + + CacheRead(gCurrentIH, bufferPos, gAllocationOffset + readOffset, + readSize, cache); + + sizeRead += readSize; + offset += readSize; + bufferPos += readSize; + } + + if (extentBuffer) free(extentBuffer); + + return sizeRead; +} + +static long GetExtentStart(void * extents, long index) +{ + long start; + HFSExtentDescriptor *hfsExtents = extents; + HFSPlusExtentDescriptor *hfsPlusExtents = extents; + + if (gIsHFSPlus) start = SWAP_BE32(hfsPlusExtents[index].startBlock); + else start = SWAP_BE16(hfsExtents[index].startBlock); + + return start; +} + +static long GetExtentSize(void * extents, long index) +{ + long size; + HFSExtentDescriptor *hfsExtents = extents; + HFSPlusExtentDescriptor *hfsPlusExtents = extents; + + if (gIsHFSPlus) size = SWAP_BE32(hfsPlusExtents[index].blockCount); + else size = SWAP_BE16(hfsExtents[index].blockCount); + + return size; +} + +static long CompareHFSCatalogKeys(void * key, void * testKey) +{ + HFSCatalogKey *searchKey, *trialKey; + long result, searchParentID, trialParentID; + + searchKey = key; + trialKey = testKey; + + searchParentID = SWAP_BE32(searchKey->parentID); + trialParentID = SWAP_BE32(trialKey->parentID); + + // parent dirID is unsigned + if (searchParentID > trialParentID) result = 1; + else if (searchParentID < trialParentID) result = -1; + else { + // parent dirID's are equal, compare names + result = FastRelString(searchKey->nodeName, trialKey->nodeName); + } + + return result; +} + +static long CompareHFSPlusCatalogKeys(void * key, void * testKey) +{ + HFSPlusCatalogKey *searchKey, *trialKey; + long result, searchParentID, trialParentID; + + searchKey = key; + trialKey = testKey; + + searchParentID = SWAP_BE32(searchKey->parentID); + trialParentID = SWAP_BE32(trialKey->parentID); + + // parent dirID is unsigned + if (searchParentID > trialParentID) result = 1; + else if (searchParentID < trialParentID) result = -1; + else { + // parent dirID's are equal, compare names + if ((searchKey->nodeName.length == 0) || (trialKey->nodeName.length == 0)) + result = searchKey->nodeName.length - trialKey->nodeName.length; + else + if (gCaseSensitive) { + result = BinaryUnicodeCompare(&searchKey->nodeName.unicode[0], + SWAP_BE16(searchKey->nodeName.length), + &trialKey->nodeName.unicode[0], + SWAP_BE16(trialKey->nodeName.length)); + } else { + result = FastUnicodeCompare(&searchKey->nodeName.unicode[0], + SWAP_BE16(searchKey->nodeName.length), + &trialKey->nodeName.unicode[0], + SWAP_BE16(trialKey->nodeName.length), OSBigEndian); + } + } + + return result; +} + +static long CompareHFSExtentsKeys(void * key, void * testKey) +{ + HFSExtentKey *searchKey, *trialKey; + long result; + + searchKey = key; + trialKey = testKey; + + // assume searchKey < trialKey + result = -1; + + if (searchKey->fileID == trialKey->fileID) { + // FileNum's are equal; compare fork types + if (searchKey->forkType == trialKey->forkType) { + // Fork types are equal; compare allocation block number + if (searchKey->startBlock == trialKey->startBlock) { + // Everything is equal + result = 0; + } else { + // Allocation block numbers differ; determine sign + if (SWAP_BE16(searchKey->startBlock) > SWAP_BE16(trialKey->startBlock)) + result = 1; + } + } else { + // Fork types differ; determine sign + if (searchKey->forkType > trialKey->forkType) result = 1; + } + } else { + // FileNums differ; determine sign + if (SWAP_BE32(searchKey->fileID) > SWAP_BE32(trialKey->fileID)) + result = 1; + } + + return result; +} + +static long CompareHFSPlusExtentsKeys(void * key, void * testKey) +{ + HFSPlusExtentKey *searchKey, *trialKey; + long result; + + searchKey = key; + trialKey = testKey; + + // assume searchKey < trialKey + result = -1; + + if (searchKey->fileID == trialKey->fileID) { + // FileNum's are equal; compare fork types + if (searchKey->forkType == trialKey->forkType) { + // Fork types are equal; compare allocation block number + if (searchKey->startBlock == trialKey->startBlock) { + // Everything is equal + result = 0; + } else { + // Allocation block numbers differ; determine sign + if (SWAP_BE32(searchKey->startBlock) > SWAP_BE32(trialKey->startBlock)) + result = 1; + } + } else { + // Fork types differ; determine sign + if (searchKey->forkType > trialKey->forkType) result = 1; + } + } else { + // FileNums differ; determine sign + if (SWAP_BE32(searchKey->fileID) > SWAP_BE32(trialKey->fileID)) + result = 1; + } + + return result; +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/ext2fs.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ext2fs.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ext2fs.h.svn-base (revision 850) @@ -0,0 +1,11 @@ +/* + * ext2fs.h + * + * + * Created by mackerintel on 1/26/09. + * Copyright 2009 __MyCompanyName__. All rights reserved. + * + */ + +extern bool EX2Probe (const void *buf); +extern void EX2GetDescription(CICell ih, char *str, long strMaxLen); Index: branches/Chimera/i386/libsaio/.svn/text-base/pci_root.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/pci_root.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/pci_root.h.svn-base (revision 850) @@ -0,0 +1,13 @@ +/* + * Copyright 2008 mackerintel + */ + +#ifndef __LIBSAIO_PCI_ROOT_H +#define __LIBSAIO_PCI_ROOT_H + +#include "libsaio.h" + + +extern int getPciRootUID(void); + +#endif /* !__LIBSAIO_DSDT_PATCHER_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/allocate.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/allocate.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/allocate.c.svn-base (revision 850) @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#include "sl.h" +#include "saio_internal.h" +#include "bootstruct.h" +#include "device_tree.h" + +static long gImageLastKernelAddr; + +#define kPageSize 4096 +#define RoundPage(x) ((((unsigned)(x)) + kPageSize - 1) & ~(kPageSize - 1)) + + +long +AllocateMemoryRange(char * rangeName, long start, long length, long type) +{ + char *nameBuf; + uint32_t *buffer; + + nameBuf = malloc(strlen(rangeName) + 1); + if (nameBuf == 0) return -1; + strcpy(nameBuf, rangeName); + + buffer = malloc(2 * sizeof(uint32_t)); + if (buffer == 0) return -1; + + buffer[0] = start; + buffer[1] = length; + + DT__AddProperty(gMemoryMapNode, nameBuf, 2 * sizeof(uint32_t), (char *)buffer); + + return 0; +} + +long +AllocateKernelMemory( long inSize ) +{ + long addr; + + if (gImageLastKernelAddr == 0) { + gImageLastKernelAddr = RoundPage( bootArgs->kaddr + + bootArgs->ksize ); + } + addr = gImageLastKernelAddr; + gImageLastKernelAddr += RoundPage(inSize); + + if ( gImageLastKernelAddr >= (KERNEL_ADDR + KERNEL_LEN) ) { + stop ("AllocateKernelMemory error"); + } + + bootArgs->ksize = gImageLastKernelAddr - bootArgs->kaddr; + + return addr; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/msdos.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/msdos.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/msdos.c.svn-base (revision 850) @@ -0,0 +1,956 @@ +/* + * Copyright (c) 2004 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * The contents of this file constitute Original Code as defined in and + * are subject to the Apple Public Source License Version 2.0 (the + * "License"). You may not use this file except in compliance with the + * License. Please obtain a copy of the License at + * http://www.apple.com/publicsource and read it before using this file. + * + * This Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright (c) 1998 Robert Nordier + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define tolower(c) (((c)>='A' && c<='Z')?((c) | 0x20):(c)) +#include "libsaio.h" +#include "sl.h" + +#include "msdos_private.h" +#include "msdos.h" + +#define LABEL_LENGTH 11 +#define MSDOS_CACHE_BLOCKSIZE BPS + +#define CLUST_FIRST 2/* reserved cluster range */ +#define CLUST_RSRVD32 0x0ffffff8 /* reserved cluster range */ +#define CLUST_RSRVD16 0xfff8 /* reserved cluster range */ +#define CLUST_RSRVD12 0xff8 /* reserved cluster range */ + + +#define false 0 +#define true 1 + +static int msdosressector=0; +static int msdosnfats = 0; +static int msdosfatsecs = 0; +static int msdosbps = 0; +static int msdosclustersize = 0; +static int msdosrootDirSectors = 0; +static CICell msdoscurrent = 0; +static int msdosrootcluster = 0; +static int msdosfatbits = 0; + +#if UNUSED +/* + * Check a volume label. + */ +static int +oklabel(const char *src) +{ + int c, i; + + for (i = 0, c = 0; i <= 11; i++) { + c = (u_char)*src++; + if (c < ' ' + !i || strchr("\"*+,./:;<=>?[\\]|", c)) + break; + } + return i && !c; +} +#endif /* UNUSED */ + +void MSDOSFree(CICell ih) +{ + if(msdoscurrent == ih) + msdoscurrent = 0; + free(ih); +} + +int MSDOSProbe(const void * buffer) +{ + union bootsector *bsp; + struct bpb33 *b33; + struct bpb50 *b50; + struct bpb710 *b710; + u_int16_t bps; + u_int8_t spc; + + bsp = (union bootsector *)buffer; + b33 = (struct bpb33 *)bsp->bs33.bsBPB; + b50 = (struct bpb50 *)bsp->bs50.bsBPB; + b710 = (struct bpb710 *)bsp->bs710.bsBPB; + + /* We only work with 512, 1024, and 2048 byte sectors */ + bps = OSSwapLittleToHostInt16(b33->bpbBytesPerSec); + if ((bps < 0x200) || (bps & (bps - 1)) || (bps > 0x800)) + return 0; + + /* Check to make sure valid sectors per cluster */ + spc = b33->bpbSecPerClust; + if ((spc == 0 ) || (spc & (spc - 1))) + return 0; + + if (OSSwapLittleToHostInt16(b50->bpbRootDirEnts) == 0) { /* It's FAT32 */ + if (!memcmp(((struct extboot *)bsp->bs710.bsExt)->exFileSysType, "FAT32 ", 8)) + return 32; + } + else if (((struct extboot *)bsp->bs50.bsExt)->exBootSignature == EXBOOTSIG) { + if (!memcmp((char *)((struct extboot *)bsp->bs50.bsExt)->exFileSysType, "FAT16 ", 8)) + return 16; + if (!memcmp((char *)((struct extboot *)bsp->bs50.bsExt)->exFileSysType, "FAT12 ", 8)) + return 12; + } + + return 0; +} + + +long +MSDOSInitPartition (CICell ih) +{ + union bootsector *bsp; + struct bpb33 *b33; + struct bpb50 *b50; + struct bpb710 *b710; + u_int8_t spc; + char *buf; + + if (msdoscurrent == ih) + { + CacheInit(ih, MSDOS_CACHE_BLOCKSIZE); + return 0; + } + + buf=malloc (512); + /* + * Read the boot sector of the filesystem, and then check the + * boot signature. If not a dos boot sector then error out. + * + * NOTE: 2048 is a maximum sector size in current... + */ + Seek(ih, 0); + Read(ih, (long)buf, 512); + + bsp = (union bootsector *)buf; + b33 = (struct bpb33 *)bsp->bs33.bsBPB; + b50 = (struct bpb50 *)bsp->bs50.bsBPB; + b710 = (struct bpb710 *)bsp->bs710.bsBPB; + + + /* We only work with 512, 1024, and 2048 byte sectors */ + msdosbps = OSSwapLittleToHostInt16(b33->bpbBytesPerSec); + if ((msdosbps < 0x200) || (msdosbps & (msdosbps - 1)) || (msdosbps > 0x800)) + { + free (buf); + return -1; + } + + /* Check to make sure valid sectors per cluster */ + spc = b33->bpbSecPerClust; + if ((spc == 0 ) || (spc & (spc - 1))) + return -1; + + if (OSSwapLittleToHostInt16(b50->bpbRootDirEnts) == 0) { /* It's FAT32 */ + if (memcmp(((struct extboot *)bsp->bs710.bsExt)->exFileSysType, "FAT32 ", 8)) + { + free (buf); + return -1; + } + msdosressector = OSSwapLittleToHostInt16(b710->bpbResSectors); + msdosnfats = b710->bpbFATs; + msdosfatsecs = OSSwapLittleToHostInt16(b710->bpbBigFATsecs); + msdosrootcluster = OSSwapLittleToHostInt32(b710->bpbRootClust); + msdosrootDirSectors = 0; + msdosfatbits = 32; + } + else if (((struct extboot *)bsp->bs50.bsExt)->exBootSignature == EXBOOTSIG) { + if (!memcmp((char *)((struct extboot *)bsp->bs50.bsExt)->exFileSysType, "FAT16 ", 8)) + msdosfatbits = 16; + else if (!memcmp((char *)((struct extboot *)bsp->bs50.bsExt)->exFileSysType, "FAT12 ", 8)) + msdosfatbits = 12; + else + { + free (buf); + return -1; + } + + msdosressector = OSSwapLittleToHostInt16(b33->bpbResSectors); + msdosnfats = b33->bpbFATs; + msdosfatsecs = OSSwapLittleToHostInt16(b33->bpbFATsecs); + msdosrootcluster = 0; + msdosrootDirSectors = ((OSSwapLittleToHostInt16(b50->bpbRootDirEnts) * sizeof(struct direntry)) + + (msdosbps-1)) / msdosbps; + } else { + free (buf); + return -1; + } + + msdosclustersize = msdosbps * spc; + msdoscurrent = ih; + + CacheInit(ih, MSDOS_CACHE_BLOCKSIZE); + free (buf); + return 0; +} + +static int +readSector(CICell ih, off_t readOffset, char *buf, int size) +{ + // Caching only FAT entries (4 bytes) by utlizing the cache with sector aligned read requests. + if (size < BPS) + { + long long sectorOffset = (uint64_t)readOffset / BPS * BPS; + long relOffset = readOffset % BPS; + char *cacheBuffer; + + cacheBuffer = malloc(MSDOS_CACHE_BLOCKSIZE); + CacheRead(ih, cacheBuffer, sectorOffset, MSDOS_CACHE_BLOCKSIZE, true); + bcopy(cacheBuffer + relOffset, buf, size); + free(cacheBuffer); + } + else + { + Seek(ih, readOffset); + Read(ih, (long)buf, size); + } + + return 0; +} + +static int +msdosreadcluster (CICell ih, uint8_t *buf, int size, off_t *cluster) +{ + off_t readOffset; + char tmpbuf[8]; + off_t clusn; + + switch (msdosfatbits) { + case 32: + if (*cluster < CLUST_FIRST ||*cluster >= CLUST_RSRVD32) + return 0; + clusn = *cluster - CLUST_FIRST; + break; + case 16: + if (*cluster < CLUST_FIRST ||*cluster >= CLUST_RSRVD16) + return 0; + clusn = *cluster - CLUST_FIRST; + break; + case 12: + if (*cluster < CLUST_FIRST ||*cluster >= CLUST_RSRVD12) + return 0; + clusn = *cluster - CLUST_FIRST; + break; + default: + return 0; + } + + /* Find sector where clusters start */ + readOffset = (msdosressector + + (msdosnfats * msdosfatsecs)+msdosrootDirSectors)*msdosbps; + /* Find sector where "cluster" starts */ + readOffset += clusn * msdosclustersize; + + /* Read in "cluster" */ + if (buf) + { + Seek(ih, readOffset); + Read(ih, (long)buf, size); + } + + /* Find first sector of FAT */ + readOffset = msdosressector * msdosbps; + + /* Find sector containing "cluster" entry in FAT */ + readOffset += ((uint64_t)*cluster * (uint64_t)msdosfatbits) / 8; + + /* Read one sector of the FAT */ + readSector(ih, readOffset, tmpbuf, 4); + + switch (msdosfatbits) { + case 32: + *cluster = OSReadLittleInt32(tmpbuf, 0); + *cluster &= 0x0FFFFFFF; // ignore reserved upper bits + return 1; + case 16: + *cluster = OSReadLittleInt16(tmpbuf, 0); + return 1; + case 12: + *cluster = OSReadLittleInt16(tmpbuf, 0)>>(((uint64_t)*cluster * (uint64_t)msdosfatbits)%8); + *cluster &= 0xfff; + return 1; + default: + return 0; + } +} + +struct msdosdirstate +{ + struct direntry *buf; + uint8_t vfatchecksum; + int root16; + off_t cluster; + int nument; + int vfatnumber; +}; + +static struct direntry * +getnextdirent (CICell ih, uint16_t *longname, struct msdosdirstate *st) +{ + struct direntry *dirp; + while (1) + { + if (st->root16) + { + if (st->cluster >= msdosrootDirSectors && st->nument == 0) + return 0; + if (st->nument == 0) + { + Seek(ih, (msdosressector + + (msdosnfats * msdosfatsecs)+st->cluster)*msdosbps); + Read(ih, (long)st->buf, msdosbps); + st->cluster++; + } + } else if (st->nument == 0 && !msdosreadcluster (ih, (uint8_t *)st->buf, msdosclustersize, &(st->cluster))) + return 0; + + dirp=st->buf+st->nument; + + if (dirp->deName[0] == SLOT_EMPTY) + return 0; + else if (dirp->deName[0] == SLOT_DELETED) + st->vfatnumber = 0; + else if (dirp->deAttributes == ATTR_WIN95) + { + struct winentry *wdirp = (struct winentry *)dirp; + int num; + if (wdirp->weCnt & 0x80) + continue; + num=(wdirp->weCnt&0x3f); + if (WIN_CHARS * num > WIN_MAXLEN) + continue; + if (st->vfatchecksum!=wdirp->weChksum) + { + st->vfatnumber = 0; + st->vfatchecksum = wdirp->weChksum; + } + if (st->vfatnumber < num) + st->vfatnumber = num; + bcopy (&(wdirp->wePart1),longname+WIN_CHARS*(num-1),sizeof (wdirp->wePart1)); + bcopy (&(wdirp->wePart2),longname+WIN_CHARS*(num-1)+5,sizeof (wdirp->wePart2)); + bcopy (&(wdirp->wePart3),longname+WIN_CHARS*(num-1)+11,sizeof (wdirp->wePart3)); + } else { + uint8_t labelchecksum; + int i; + longname[st->vfatnumber*WIN_CHARS]=0; + + labelchecksum=0; + for(i=0;i>1)+(labelchecksum<<7)+dirp->deName[i]; + if (!(labelchecksum==st->vfatchecksum && st->vfatnumber)) + longname[0]=0; + st->vfatnumber = 0; + st->vfatchecksum = 0; + st->vfatnumber = 0; + st->nument++; + if ((!st->root16 &&st->nument * sizeof (struct direntry)>=msdosclustersize) + || (st->root16 &&st->nument * sizeof (struct direntry)>=msdosbps)) + st->nument = 0; + return dirp; + } + st->nument++; + if ((!st->root16 &&st->nument * sizeof (struct direntry)>=msdosclustersize) + || (st->root16 &&st->nument * sizeof (struct direntry)>=msdosbps)) + st->nument = 0; + } +} + +static void +initRoot (struct msdosdirstate *st) +{ + if (msdosrootDirSectors) { /* FAT12 or FAT16 */ + st->root16 = 1; + st->vfatchecksum = 0; + st->nument = 0; + st->cluster = 0; + st->vfatnumber = 0; + } else { /* FAT32 */ + st->root16 = 0; + st->vfatchecksum = 0; + st->nument = 0; + st->cluster = msdosrootcluster; + st->vfatnumber = 0; + } +} + +/* First comes lowercase, then uppercase*/ +static uint16_t cp850[128][2]= +{ +{0x00E7,0x00C7}, +{0x00FC,0x00DC}, +{0x00E9,0x00C9}, +{0x00E2,0x00C2}, +{0x00E4,0x00C4}, +{0x00E0,0x00C0}, +{0x00E5,0x00C5}, +{0x00E7,0x00C7}, +{0x00EA,0x00CA}, +{0x00EB,0x00CB}, +{0x00E8,0x00C8}, +{0x00EF,0x00CF}, +{0x00EE,0x00CE}, +{0x00EC,0x00CC}, +{0x00E4,0x00C4}, +{0x00E5,0x00C5}, +{0x00E9,0x00C9}, +{0x00E6,0x00C6}, +{0x00E6,0x00C6}, +{0x00F4,0x00D4}, +{0x00F6,0x00D6}, +{0x00F2,0x00D2}, +{0x00FB,0x00DB}, +{0x00F9,0x00D9}, +{0x00FF,0x0178}, +{0x00F6,0x00D6}, +{0x00FC,0x00DC}, +{0x00F8,0x00D8}, +{0x00A3,0x00A3}, +{0x00F8,0x00D8}, +{0x00D7,0x00D7}, +{0x0192,0x0191}, +{0x00E1,0x00C1}, +{0x00ED,0x00CD}, +{0x00F3,0x00D3}, +{0x00FA,0x00DA}, +{0x00F1,0x00D1}, +{0x00F1,0x00D1}, +{0x00AA,0x00AA}, +{0x00BA,0x00BA}, +{0x00BF,0x00BF}, +{0x00AE,0x00AE}, +{0x00AC,0x00AC}, +{0x00BD,0x00BD}, +{0x00BC,0x00BC}, +{0x00A1,0x00A1}, +{0x00AB,0x00AB}, +{0x00BB,0x00BB}, +{0x2591,0x2591}, +{0x2592,0x2592}, +{0x2593,0x2593}, +{0x2502,0x2502}, +{0x2524,0x2524}, +{0x00E1,0x00C1}, +{0x00E2,0x00C2}, +{0x00E0,0x00C0}, +{0x00A9,0x00A9}, +{0x2563,0x2563}, +{0x2551,0x2551}, +{0x2557,0x2557}, +{0x255D,0x255D}, +{0x00A2,0x00A2}, +{0x00A5,0x00A5}, +{0x2510,0x2510}, +{0x2514,0x2514}, +{0x2534,0x2534}, +{0x252C,0x252C}, +{0x251C,0x251C}, +{0x2500,0x2500}, +{0x253C,0x253C}, +{0x00E3,0x00C3}, +{0x00E3,0x00C3}, +{0x255A,0x255A}, +{0x2554,0x2554}, +{0x2569,0x2569}, +{0x2566,0x2566}, +{0x2560,0x2560}, +{0x2550,0x2550}, +{0x256C,0x256C}, +{0x00A4,0x00A4}, +{0x00F0,0x00D0}, +{0x00F0,0x00D0}, +{0x00EA,0x00CA}, +{0x00EB,0x00CB}, +{0x00E8,0x00C8}, +{0x0131,0x0049}, +{0x00ED,0x00CD}, +{0x00EE,0x00CE}, +{0x00EF,0x00CF}, +{0x2518,0x2518}, +{0x250C,0x250C}, +{0x2588,0x2588}, +{0x2584,0x2584}, +{0x00A6,0x00A6}, +{0x00EC,0x00CC}, +{0x2580,0x2580}, +{0x00F3,0x00D3}, +{0x00DF,0x00DF}, +{0x00F4,0x00D4}, +{0x00F2,0x00D2}, +{0x00F5,0x00D5}, +{0x00F5,0x00D5}, +{0x00B5,0x00B5}, +{0x00FE,0x00DE}, +{0x00FE,0x00DE}, +{0x00FA,0x00DA}, +{0x00FB,0x00DB}, +{0x00F9,0x00D9}, +{0x00FD,0x00DD}, +{0x00FD,0x00DD}, +{0x00AF,0x00AF}, +{0x00B4,0x00B4}, +{0x00AD,0x00AD}, +{0x00B1,0x00B1}, +{0x2017,0x2017}, +{0x00BE,0x00BE}, +{0x00B6,0x00B6}, +{0x00A7,0x00A7}, +{0x00F7,0x00F7}, +{0x00B8,0x00B8}, +{0x00B0,0x00B0}, +{0x00A8,0x00A8}, +{0x00B7,0x00B7}, +{0x00B9,0x00B9}, +{0x00B3,0x00B3}, +{0x00B2,0x00B2}, +{0x25A0,0x25A0}, +{0x00A0,0x00A0} +}; + +static int +checkname (uint16_t *ucsname, int ucslen, struct direntry *dirp, uint16_t *vfatname) +{ + uint16_t tmp[15]; + if (vfatname[0]) + { + int i; + for (i=0;vfatname[i];i++); + return !FastUnicodeCompare (ucsname, ucslen, vfatname, i, OSLittleEndian); + } + else + { + int i, j, k; + for (i=7;i>=0;i--) + if (dirp->deName[i]!=' ') + break; + j=i+1; + tmp[i+1]=0; + for(;i>=0;i--) + tmp[i]=SWAP_LE16((dirp->deName[i]>=128)?cp850[dirp->deName[i]-128][0]:tolower(dirp->deName[i])); + for (i=2;i>=0;i--) + if (dirp->deName[8+i]!=' ') + break; + if (i>=0) + { + tmp[j++]='.'; + tmp[j+i+1]=0; + k=j+i+1; + for(;i>=0;i--) + tmp[j+i]=SWAP_LE16((dirp->deName[i+8]>=128)?cp850[dirp->deName[i+8]-128][0]:tolower(dirp->deName[i+8])); + j=k; + } + return !FastUnicodeCompare (ucsname, ucslen, tmp, j, OSLittleEndian); + } + +} + +static struct direntry * +getdirpfrompath (CICell ih, char *dirspec, uint8_t *buf) +{ + struct msdosdirstate st; + struct direntry *dirp; + uint8_t * ptr; + uint8_t *slash; + char c; + uint16_t vfatname[WIN_MAXLEN+2*WIN_CHARS]; + uint16_t ucsname[WIN_MAXLEN+1]; + uint16_t ucslen; + int ucslenhost; + initRoot (&st); + st.buf = (struct direntry *)buf; + ptr=(uint8_t*)dirspec; + for (slash=ptr;*slash && *slash!='/';slash++); + c=*slash; + *slash=0; + utf_decodestr (ptr, ucsname, &ucslen, WIN_MAXLEN, OSLittleEndian); + ucslenhost = OSReadLittleInt16 (&ucslen,0); + ucsname[ucslenhost]=0; + *slash=c; + while ((dirp = getnextdirent (ih, vfatname, &st))) + { + if (checkname (ucsname, ucslenhost, dirp, vfatname)) + { + for (;*ptr && *ptr!='/';ptr++); + if (!*ptr) + return dirp; + ptr++; + if (!*ptr) + return dirp; + for (slash=ptr;*slash && *slash!='/';slash++); + c=*slash; + *slash=0; + utf_decodestr (ptr, ucsname, &ucslen, WIN_MAXLEN, OSLittleEndian); + ucslenhost = OSReadLittleInt16 (&ucslen,0); + ucsname[ucslenhost]=0; + *slash=c; + if (!(dirp->deAttributes & ATTR_DIRECTORY)) + return 0; + st.root16 = 0; + st.vfatchecksum = 0; + st.nument = 0; + st.cluster = OSReadLittleInt16 ((dirp->deStartCluster),0); + if (msdosfatbits == 32) + st.cluster |= ((uint32_t)OSReadLittleInt16 ((dirp->deHighClust),0)) <<16; + st.vfatnumber = 0; + } + } + return 0; +} + +long MSDOSGetDirEntry(CICell ih, char * dirPath, long long * dirIndex, + char ** name, long * flags, long * time, + FinderInfo * finderInfo, long * infoValid) +{ + struct msdosdirstate *st; + struct direntry *dirp; + uint16_t vfatname[WIN_MAXLEN+2*WIN_CHARS]; + if (MSDOSInitPartition (ih)<0) + return -1; + if (dirPath[0] == '/') + dirPath++; + st = (struct msdosdirstate *)(long) *dirIndex; + if (!st) + { + st=malloc (sizeof (*st)); + if (dirPath[0]) + { + uint8_t *buf=malloc(msdosclustersize); + dirp = getdirpfrompath (ih, dirPath, buf); + if (!dirp || !(dirp->deAttributes & ATTR_DIRECTORY)) + { + free (buf); + free (st); + return -1; + } + st->buf = (struct direntry *)buf; + st->root16 = 0; + st->vfatchecksum = 0; + st->nument = 0; + st->cluster = OSReadLittleInt16 ((dirp->deStartCluster),0); + st->vfatnumber = 0; + if (msdosfatbits == 32) + st->cluster |= ((uint32_t)OSReadLittleInt16 ((dirp->deHighClust),0)) <<16; + } + else + initRoot (st); + *dirIndex = (long long) (long) st; + } + while((dirp = getnextdirent (ih, vfatname, st))&& (dirp->deAttributes & ATTR_VOLUME)); + if (!dirp) + { + free (st->buf); + free (st); + return -1; + } + if (vfatname[0]) + { + int i; + for (i=0;vfatname[i];i++); + *name = malloc (256); + utf_encodestr(vfatname, i, (u_int8_t *)*name, 255, OSLittleEndian ); + } + else + { + int i, j, k; + uint16_t tmp[13]; + *name = malloc (26); + for (i=7;i>=0;i--) + if (dirp->deName[i]!=' ') + break; + j=i+1; + tmp[i+1]=0; + for(;i>=0;i--) + tmp[i]=(dirp->deName[i]>=128)?cp850[dirp->deName[i]-128][0]:tolower(dirp->deName[i]); + for (i=2;i>=0;i--) + if (dirp->deName[8+i]!=' ') + break; + + if (i>=0) + { + tmp[j++]='.'; + tmp[j+i+1]=0; + k=j+i+1; + for(;i>=0;i--) + tmp[j+i]=(dirp->deName[i]>=128)?cp850[dirp->deName[i+8]-128][0]:tolower(dirp->deName[i+8]); + j=k; + } + + utf_encodestr(tmp, j, (uint8_t*)*name, 25, OSHostByteOrder() ); + } + if (dirp->deAttributes & ATTR_DIRECTORY) + *flags = kFileTypeDirectory; + else + *flags = kFileTypeFlat; + + // Calculate a fake timestamp using modification date and time values. + *time = (dirp->deMDate & 0x7FFF) << 16 + dirp->deMTime; + + if (infoValid) + *infoValid = 1; + + return 0; +} + +long +MSDOSReadFile(CICell ih, char * filePath, void *base, uint64_t offset, uint64_t length) +{ + uint8_t *buf; + off_t cluster; + uint64_t size; + uint64_t nskip; + int toread, wastoread; + char *ptr = (char *)base; + struct direntry *dirp; + int i; + char devStr[12]; + + if (MSDOSInitPartition (ih)<0) + return -1; + if (filePath[0] == '/') + filePath++; + buf = malloc(msdosclustersize); + dirp = getdirpfrompath (ih, filePath, buf); + + if (!dirp || (dirp->deAttributes & ATTR_DIRECTORY)) + { + free (buf); + return -1; + } + cluster = OSReadLittleInt16 ((dirp->deStartCluster),0); + if (msdosfatbits == 32) + cluster |= ((uint32_t)OSReadLittleInt16 ((dirp->deHighClust),0)) <<16; + size = (uint32_t)OSReadLittleInt32 ((dirp->deFileSize),0); + if (size<=offset) + return -1; + nskip=offset/msdosclustersize; + for (i=0;isize-offset) + toread=size-offset; + wastoread=toread; + bcopy (buf+(offset%msdosclustersize),ptr,min(msdosclustersize-(offset%msdosclustersize), toread)); + ptr+=msdosclustersize-(offset%msdosclustersize); + toread-=msdosclustersize-(offset%msdosclustersize); + while (toread>0 && msdosreadcluster (ih, (uint8_t *)ptr, min(msdosclustersize,toread), &cluster)) + { + ptr+=msdosclustersize; + toread-=msdosclustersize; + } + + getDeviceDescription(ih, devStr); + verbose("Read FAT%d file: [%s/%s] %d bytes.\n", + msdosfatbits, devStr, filePath, (uint32_t)( toread<0 ) ? wastoread : wastoread-toread); + free (buf); + if (toread<0) + return wastoread; + else + return wastoread-toread; +} + +long +MSDOSGetFileBlock(CICell ih, char *filePath, unsigned long long *firstBlock) +{ + uint8_t *buf; + off_t cluster; + struct direntry *dirp; + if (MSDOSInitPartition (ih)<0) + return -1; + if (filePath[0] == '/') + filePath++; + buf = malloc(msdosclustersize); + dirp = getdirpfrompath (ih, filePath, buf); + if (!dirp || (dirp->deAttributes & ATTR_DIRECTORY)) + { + free (buf); + return -1; + } + cluster = OSReadLittleInt16 ((dirp->deStartCluster),0); + if (msdosfatbits == 32) + cluster |= ((uint32_t)OSReadLittleInt16 ((dirp->deHighClust),0)) <<16; + + off_t clusn; + + switch (msdosfatbits) { + case 32: + if (cluster < CLUST_FIRST ||cluster >= CLUST_RSRVD32) + return -1; + clusn = cluster - CLUST_FIRST; + break; + case 16: + if (cluster < CLUST_FIRST ||cluster >= CLUST_RSRVD16) + return 0; + clusn = cluster - CLUST_FIRST; + break; + case 12: + + if (cluster < CLUST_FIRST ||cluster >= CLUST_RSRVD12) + return 0; + clusn = cluster - CLUST_FIRST; + break; + default: + return 0; + } + + *firstBlock = ((msdosressector + + (msdosnfats * msdosfatsecs))*msdosbps + clusn * msdosclustersize)/512; + free (buf); + return 0; +} + + +long MSDOSLoadFile(CICell ih, char * filePath) +{ + return MSDOSReadFile(ih, filePath, (void *)gFSLoadAddress, 0, 0); +} + +/* Fix up volume label. */ +static void +fixLabel(uint8_t *label, char *str, long strMaxLen) +{ + int i, len; + uint16_t labelucs[13]; + //unsigned char labelUTF8[LABEL_LENGTH*3]; + + /* Convert leading 0x05 to 0xE5 for multibyte languages like Japanese */ + if (label[0] == 0x05) + label[0] = 0xE5; + + /* Remove any trailing spaces */ + for (i=LABEL_LENGTH-1; i>=0; --i) { + if (label[i] == ' ') + label[i] = 0; + else + break; + } + labelucs[i++]=0; + len=i; + for (;i>=0;--i) + labelucs[i]=label[i]>=128?cp850[label[i]-128][1]:(label[i]); + + utf_encodestr(labelucs, len, (uint8_t *)str, strMaxLen, OSHostByteOrder() ); +} + + +void +MSDOSGetDescription(CICell ih, char *str, long strMaxLen) +{ + struct direntry *dirp; + uint8_t label[LABEL_LENGTH+1]; + uint16_t vfatlabel[WIN_MAXLEN+2*WIN_CHARS]; + struct msdosdirstate st; + int labelfound = 0; + + if (MSDOSInitPartition (ih)<0) + { + str[0]=0; + return; + } + + label[0] = '\0'; + + initRoot (&st); + st.buf = malloc(msdosclustersize); + while ((dirp = getnextdirent (ih, vfatlabel, &st))) + if (dirp->deAttributes & ATTR_VOLUME) { + strncpy((char *)label, (char *)dirp->deName, LABEL_LENGTH); + labelfound = 1; + break; + } + + free(st.buf); + + if (vfatlabel[0] && labelfound) + { + int i; + for (i=0;vfatlabel[i];i++); + utf_encodestr(vfatlabel, i, (u_int8_t *)str, strMaxLen, OSLittleEndian ); + } + else if (labelfound) + fixLabel(label, str, strMaxLen); + + /* else look in the boot blocks */ + if (!labelfound || str[0] == '\0') { + char *buf = malloc (512); + union bootsector *bsp = (union bootsector *)buf; + Seek(ih, 0); + Read(ih, (long)buf, 512); + if (msdosfatbits == 32) { /* It's FAT32 */ + strncpy((char *)label, (char *)((struct extboot *)bsp->bs710.bsExt)->exVolumeLabel, LABEL_LENGTH); + } + else if (msdosfatbits == 16) { + strncpy((char *)label, (char *)((struct extboot *)bsp->bs50.bsExt)->exVolumeLabel, LABEL_LENGTH); + } + free (buf); + fixLabel(label, str, strMaxLen); + } + + return; +} + +long +MSDOSGetUUID(CICell ih, char *uuidStr) +{ + char *buf = malloc (512); + union bootsector *bsp = (union bootsector *)buf; + + if (MSDOSInitPartition (ih)<0) + { + return -1; + } + bzero (uuidStr, 16); + Seek(ih, 0); + Read(ih, (long)buf, 512); + if (msdosfatbits == 32) { /* It's FAT32 */ + memcpy(uuidStr+12, (char *)((struct extboot *)bsp->bs710.bsExt)->exVolumeID, 4); + } + else if (msdosfatbits == 16) { + memcpy(uuidStr+12, (char *)((struct extboot *)bsp->bs50.bsExt)->exVolumeID, 4); + } + free (buf); + return 0; + +} Index: branches/Chimera/i386/libsaio/.svn/text-base/convert.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/convert.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/convert.h.svn-base (revision 850) @@ -0,0 +1,33 @@ +/* + * Convert.h + * Declare conversion utility functions + * --Rek + */ + +#ifndef __CONVERT_H +#define __CONVERT_H +#include "libsaio.h" +#include "efi.h" + +#define UUID_LEN 16 + +const char * getStringFromUUID(const EFI_CHAR8* uuid); +EFI_CHAR8* getUUIDFromString(const char *source); +void *convertHexStr2Binary(const char *hexStr, int *outLength); +uint32_t ascii_hex_to_int(char *buff); + +static inline uint16_t dp_swap16(uint16_t toswap) +{ + return (((toswap & 0x00FF) << 8) | ((toswap & 0xFF00) >> 8)); +} + +static inline uint32_t dp_swap32(uint32_t toswap) +{ + return ((toswap & 0x000000FF) << 24) | + ((toswap & 0x0000FF00) << 8 ) | + ((toswap & 0x00FF0000) >> 8 ) | + ((toswap & 0xFF000000) >> 24); +} + + +#endif Index: branches/Chimera/i386/libsaio/.svn/text-base/table.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/table.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/table.c.svn-base (revision 850) @@ -0,0 +1,101 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Mach Operating System + * Copyright (c) 1990 Carnegie-Mellon University + * Copyright (c) 1989 Carnegie-Mellon University + * All rights reserved. The CMU software License Agreement specifies + * the terms and conditions for use and redistribution. + */ + +/* + * INTEL CORPORATION PROPRIETARY INFORMATION + * + * This software is supplied under the terms of a license agreement or + * nondisclosure agreement with Intel Corporation and may not be copied + * nor disclosed except in accordance with the terms of that agreement. + * + * Copyright 1988, 1989 Intel Corporation + */ + +/* + * Copyright 1993 NeXT, Inc. + * All rights reserved. + */ + +#include "memory.h" + +/* Segment Descriptor + * + * 31 24 19 16 7 0 + * ------------------------------------------------------------ + * | | |B| |A| | | |1|0|E|W|A| | + * | BASE 31..24 |G|/|0|V| LIMIT |P|DPL| TYPE | BASE 23:16 | + * | | |D| |L| 19..16| | |1|1|C|R|A| | + * ------------------------------------------------------------ + * | | | + * | BASE 15..0 | LIMIT 15..0 | + * | | | + * ------------------------------------------------------------ + */ + +struct seg_desc { + unsigned short limit_15_0; + unsigned short base_15_0; + unsigned char base_23_16; + unsigned char bit_15_8; + unsigned char bit_23_16; + unsigned char base_31_24; +}; + +// turbo - GDT must be in first 64k segment +struct seg_desc __attribute__ ((section("__INIT,__data"))) Gdt[ NGDTENT ] = { + /* 0x0 : null */ + {0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00}, + + /* 0x8 : boot protected mode 32-bit code segment + byte granularity, 1MB limit, MEMBASE offset */ + //{0xFFFF, MEMBASE, 0x00, 0x9E, 0x4F, 0x00}, + {0xFFFF, 0x0000, 0x00, 0x9E, 0xCF, 0x00}, + + /* 0x10 : boot protected mode data segment + page granularity, 4GB limit, MEMBASE offset */ + {0xFFFF, MEMBASE, 0x00, 0x92, 0xCF, 0x00}, + + /* 0x18 : boot protected mode 16-bit code segment + byte granularity, 1MB limit, MEMBASE offset */ + {0xFFFF, MEMBASE, 0x00, 0x9E, 0x0F, 0x00}, + + /* 0x20 : kernel init 32-bit data segment + page granularity, 4GB limit, zero offset */ + {0xFFFF, 0x0000, 0x00, 0x92, 0xCF, 0x00}, + + /* 0x28 : kernel init 32-bit code segment + page granularity, 4GB limit, zero offset */ + {0xFFFF, 0x0000, 0x00, 0x9E, 0xCF, 0x00}, + + /* 0x30 : boot real mode data/stack segment + byte granularity, 64K limit, MEMBASE offset, expand-up */ + {0xFFFF, MEMBASE, 0x00, 0x92, 0x00, 0x00}, +}; Index: branches/Chimera/i386/libsaio/.svn/text-base/fake_efi.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/fake_efi.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/fake_efi.c.svn-base (revision 850) @@ -0,0 +1,763 @@ + +/* + * Copyright 2007 David F. Elliott. All rights reserved. + */ + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "efi.h" +#include "acpi.h" +#include "fake_efi.h" +#include "efi_tables.h" +#include "platform.h" +#include "acpi_patcher.h" +#include "smbios.h" +#include "device_inject.h" +#include "convert.h" +#include "pci.h" +#include "sl.h" + +extern void setup_pci_devs(pci_dt_t *pci_dt); + +/* + * Modern Darwin kernels require some amount of EFI because Apple machines all + * have EFI. Modifying the kernel source to not require EFI is of course + * possible but would have to be maintained as a separate patch because it is + * unlikely that Apple wishes to add legacy support to their kernel. + * + * As you can see from the Apple-supplied code in bootstruct.c, it seems that + * the intention was clearly to modify this booter to provide EFI-like structures + * to the kernel rather than modifying the kernel to handle non-EFI stuff. This + * makes a lot of sense from an engineering point of view as it means the kernel + * for the as yet unreleased EFI-only Macs could still be booted by the non-EFI + * DTK systems so long as the kernel checked to ensure the boot tables were + * filled in appropriately. Modern xnu requires a system table and a runtime + * services table and performs no checks whatsoever to ensure the pointers to + * these tables are non-NULL. Therefore, any modern xnu kernel will page fault + * early on in the boot process if the system table pointer is zero. + * + * Even before that happens, the tsc_init function in modern xnu requires the FSB + * Frequency to be a property in the /efi/platform node of the device tree or else + * it panics the bootstrap process very early on. + * + * As of this writing, the current implementation found here is good enough + * to make the currently available xnu kernel boot without modification on a + * system with an appropriate processor. With a minor source modification to + * the tsc_init function to remove the explicit check for Core or Core 2 + * processors the kernel can be made to boot on other processors so long as + * the code can be executed by the processor and the machine contains the + * necessary hardware. + */ + +/*========================================================================== + * Utility function to make a device tree string from an EFI_GUID + */ + +static inline char * mallocStringForGuid(EFI_GUID const *pGuid) +{ + char *string = malloc(37); + efi_guid_unparse_upper(pGuid, string); + return string; +} + +/*========================================================================== + * Function to map 32 bit physical address to 64 bit virtual address + */ + +static uint64_t ptov64(uint32_t addr) +{ + return ((uint64_t)addr | 0xFFFFFF8000000000ULL); +} + +/*========================================================================== + * Fake EFI implementation + */ + +/* Identify ourselves as the EFI firmware vendor */ +static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'C','h','a','m','e','l','e','o','n','_','2','.','0', 0}; +static EFI_UINT32 const FIRMWARE_REVISION = 132; /* FIXME: Find a constant for this. */ + +/* Default platform system_id (fix by IntVar) */ +static EFI_CHAR8 const SYSTEM_ID[] = "0123456789ABCDEF"; //random value gen by uuidgen + +/* Just a ret instruction */ +static uint8_t const VOIDRET_INSTRUCTIONS[] = {0xc3}; + +/* movl $0x80000003,%eax; ret */ +static uint8_t const UNSUPPORTEDRET_INSTRUCTIONS[] = {0xb8, 0x03, 0x00, 0x00, 0x80, 0xc3}; + +EFI_SYSTEM_TABLE_32 *gST32 = NULL; +EFI_SYSTEM_TABLE_64 *gST64 = NULL; +Node *gEfiConfigurationTableNode = NULL; + +extern EFI_STATUS addConfigurationTable(EFI_GUID const *pGuid, void *table, char const *alias) +{ + EFI_UINTN i = 0; + + //Azi: as is, cpu's with em64t will use EFI64 on pre 10.6 systems, + // wich seems to cause no problem. In case it does, force i386 arch. + if (archCpuType == CPU_TYPE_I386) + { + i = gST32->NumberOfTableEntries; + } + else + { + i = gST64->NumberOfTableEntries; + } + + // We only do adds, not modifications and deletes like InstallConfigurationTable + if (i >= MAX_CONFIGURATION_TABLE_ENTRIES) + stop("Ran out of space for configuration tables. Increase the reserved size in the code.\n"); + + if (pGuid == NULL) + return EFI_INVALID_PARAMETER; + + if (table != NULL) + { + // FIXME + //((EFI_CONFIGURATION_TABLE_64 *)gST->ConfigurationTable)[i].VendorGuid = *pGuid; + //((EFI_CONFIGURATION_TABLE_64 *)gST->ConfigurationTable)[i].VendorTable = (EFI_PTR64)table; + + //++gST->NumberOfTableEntries; + + Node *tableNode = DT__AddChild(gEfiConfigurationTableNode, mallocStringForGuid(pGuid)); + + // Use the pointer to the GUID we just stuffed into the system table + DT__AddProperty(tableNode, "guid", sizeof(EFI_GUID), (void*)pGuid); + + // The "table" property is the 32-bit (in our implementation) physical address of the table + DT__AddProperty(tableNode, "table", sizeof(void*) * 2, table); + + // Assume the alias pointer is a global or static piece of data + if (alias != NULL) + DT__AddProperty(tableNode, "alias", strlen(alias)+1, (char*)alias); + + return EFI_SUCCESS; + } + return EFI_UNSUPPORTED; +} + +//Azi: crc32 done in place, on the cases were it wasn't. +/*static inline void fixupEfiSystemTableCRC32(EFI_SYSTEM_TABLE_64 *efiSystemTable) + { + efiSystemTable->Hdr.CRC32 = 0; + efiSystemTable->Hdr.CRC32 = crc32(0L, efiSystemTable, efiSystemTable->Hdr.HeaderSize); + }*/ + +/* + * What we do here is simply allocate a fake EFI system table and a fake EFI + * runtime services table. + * + * Because we build against modern headers with kBootArgsRevision 4 we + * also take care to set efiMode = 32. + */ + +void setupEfiTables32(void) +{ + // We use the fake_efi_pages struct so that we only need to do one kernel + // memory allocation for all needed EFI data. Otherwise, small allocations + // like the FIRMWARE_VENDOR string would take up an entire page. + // NOTE WELL: Do NOT assume this struct has any particular layout within itself. + // It is absolutely not intended to be publicly exposed anywhere + // We say pages (plural) although right now we are well within the 1 page size + // and probably will stay that way. + struct fake_efi_pages + { + EFI_SYSTEM_TABLE_32 efiSystemTable; + EFI_RUNTIME_SERVICES_32 efiRuntimeServices; + EFI_CONFIGURATION_TABLE_32 efiConfigurationTable[MAX_CONFIGURATION_TABLE_ENTRIES]; + EFI_CHAR16 firmwareVendor[sizeof(FIRMWARE_VENDOR)/sizeof(EFI_CHAR16)]; + uint8_t voidret_instructions[sizeof(VOIDRET_INSTRUCTIONS)/sizeof(uint8_t)]; + uint8_t unsupportedret_instructions[sizeof(UNSUPPORTEDRET_INSTRUCTIONS)/sizeof(uint8_t)]; + }; + + struct fake_efi_pages *fakeEfiPages = (struct fake_efi_pages*)AllocateKernelMemory(sizeof(struct fake_efi_pages)); + + // Zero out all the tables in case fields are added later + bzero(fakeEfiPages, sizeof(struct fake_efi_pages)); + + // -------------------------------------------------------------------- + // Initialize some machine code that will return EFI_UNSUPPORTED for + // functions returning int and simply return for void functions. + memcpy(fakeEfiPages->voidret_instructions, VOIDRET_INSTRUCTIONS, sizeof(VOIDRET_INSTRUCTIONS)); + memcpy(fakeEfiPages->unsupportedret_instructions, UNSUPPORTEDRET_INSTRUCTIONS, sizeof(UNSUPPORTEDRET_INSTRUCTIONS)); + + // -------------------------------------------------------------------- + // System table + EFI_SYSTEM_TABLE_32 *efiSystemTable = gST32 = &fakeEfiPages->efiSystemTable; + efiSystemTable->Hdr.Signature = EFI_SYSTEM_TABLE_SIGNATURE; + efiSystemTable->Hdr.Revision = EFI_SYSTEM_TABLE_REVISION; + efiSystemTable->Hdr.HeaderSize = sizeof(EFI_SYSTEM_TABLE_32); + efiSystemTable->Hdr.CRC32 = 0; // Initialize to zero and then do CRC32 + efiSystemTable->Hdr.Reserved = 0; + + efiSystemTable->FirmwareVendor = (EFI_PTR32)&fakeEfiPages->firmwareVendor; + memcpy(fakeEfiPages->firmwareVendor, FIRMWARE_VENDOR, sizeof(FIRMWARE_VENDOR)); + efiSystemTable->FirmwareRevision = FIRMWARE_REVISION; + + // XXX: We may need to have basic implementations of ConIn/ConOut/StdErr + // The EFI spec states that all handles are invalid after boot services have been + // exited so we can probably get by with leaving the handles as zero. + efiSystemTable->ConsoleInHandle = 0; + efiSystemTable->ConIn = 0; + + efiSystemTable->ConsoleOutHandle = 0; + efiSystemTable->ConOut = 0; + + efiSystemTable->StandardErrorHandle = 0; + efiSystemTable->StdErr = 0; + + efiSystemTable->RuntimeServices = (EFI_PTR32)&fakeEfiPages->efiRuntimeServices; + + // According to the EFI spec, BootServices aren't valid after the + // boot process is exited so we can probably do without it. + // Apple didn't provide a definition for it in pexpert/i386/efi.h + // so I'm guessing they don't use it. + efiSystemTable->BootServices = 0; + + efiSystemTable->NumberOfTableEntries = 0; + efiSystemTable->ConfigurationTable = (EFI_PTR32)fakeEfiPages->efiConfigurationTable; + + // We're done. Now CRC32 the thing so the kernel will accept it. + // Must be initialized to zero before CRC32, done above. + gST32->Hdr.CRC32 = crc32(0L, gST32, gST32->Hdr.HeaderSize); + + // -------------------------------------------------------------------- + // Runtime services + EFI_RUNTIME_SERVICES_32 *efiRuntimeServices = &fakeEfiPages->efiRuntimeServices; + efiRuntimeServices->Hdr.Signature = EFI_RUNTIME_SERVICES_SIGNATURE; + efiRuntimeServices->Hdr.Revision = EFI_RUNTIME_SERVICES_REVISION; + efiRuntimeServices->Hdr.HeaderSize = sizeof(EFI_RUNTIME_SERVICES_32); + efiRuntimeServices->Hdr.CRC32 = 0; + efiRuntimeServices->Hdr.Reserved = 0; + + // There are a number of function pointers in the efiRuntimeServices table. + // These are the Foundation (e.g. core) services and are expected to be present on + // all EFI-compliant machines. Some kernel extensions (notably AppleEFIRuntime) + // will call these without checking to see if they are null. + // + // We don't really feel like doing an EFI implementation in the bootloader + // but it is nice if we can at least prevent a complete crash by + // at least providing some sort of implementation until one can be provided + // nicely in a kext. + void (*voidret_fp)() = (void*)fakeEfiPages->voidret_instructions; + void (*unsupportedret_fp)() = (void*)fakeEfiPages->unsupportedret_instructions; + efiRuntimeServices->GetTime = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->SetTime = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->GetWakeupTime = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->SetWakeupTime = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->SetVirtualAddressMap = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->ConvertPointer = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->GetVariable = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->GetNextVariableName = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->SetVariable = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->GetNextHighMonotonicCount = (EFI_PTR32)unsupportedret_fp; + efiRuntimeServices->ResetSystem = (EFI_PTR32)voidret_fp; + + // We're done. Now CRC32 the thing so the kernel will accept it + efiRuntimeServices->Hdr.CRC32 = crc32(0L, efiRuntimeServices, efiRuntimeServices->Hdr.HeaderSize); + + // -------------------------------------------------------------------- + // Finish filling in the rest of the boot args that we need. + bootArgs->efiSystemTable = (uint32_t)efiSystemTable; + bootArgs->efiMode = kBootArgsEfiMode32; + + // The bootArgs structure as a whole is bzero'd so we don't need to fill in + // things like efiRuntimeServices* and what not. + // + // In fact, the only code that seems to use that is the hibernate code so it + // knows not to save the pages. It even checks to make sure its nonzero. +} + +void setupEfiTables64(void) +{ + struct fake_efi_pages + { + EFI_SYSTEM_TABLE_64 efiSystemTable; + EFI_RUNTIME_SERVICES_64 efiRuntimeServices; + EFI_CONFIGURATION_TABLE_64 efiConfigurationTable[MAX_CONFIGURATION_TABLE_ENTRIES]; + EFI_CHAR16 firmwareVendor[sizeof(FIRMWARE_VENDOR)/sizeof(EFI_CHAR16)]; + uint8_t voidret_instructions[sizeof(VOIDRET_INSTRUCTIONS)/sizeof(uint8_t)]; + uint8_t unsupportedret_instructions[sizeof(UNSUPPORTEDRET_INSTRUCTIONS)/sizeof(uint8_t)]; + }; + + struct fake_efi_pages *fakeEfiPages = (struct fake_efi_pages*)AllocateKernelMemory(sizeof(struct fake_efi_pages)); + + // Zero out all the tables in case fields are added later + bzero(fakeEfiPages, sizeof(struct fake_efi_pages)); + + // -------------------------------------------------------------------- + // Initialize some machine code that will return EFI_UNSUPPORTED for + // functions returning int and simply return for void functions. + memcpy(fakeEfiPages->voidret_instructions, VOIDRET_INSTRUCTIONS, sizeof(VOIDRET_INSTRUCTIONS)); + memcpy(fakeEfiPages->unsupportedret_instructions, UNSUPPORTEDRET_INSTRUCTIONS, sizeof(UNSUPPORTEDRET_INSTRUCTIONS)); + + // -------------------------------------------------------------------- + // System table + EFI_SYSTEM_TABLE_64 *efiSystemTable = gST64 = &fakeEfiPages->efiSystemTable; + efiSystemTable->Hdr.Signature = EFI_SYSTEM_TABLE_SIGNATURE; + efiSystemTable->Hdr.Revision = EFI_SYSTEM_TABLE_REVISION; + efiSystemTable->Hdr.HeaderSize = sizeof(EFI_SYSTEM_TABLE_64); + efiSystemTable->Hdr.CRC32 = 0; // Initialize to zero and then do CRC32 + efiSystemTable->Hdr.Reserved = 0; + + efiSystemTable->FirmwareVendor = ptov64((EFI_PTR32)&fakeEfiPages->firmwareVendor); + memcpy(fakeEfiPages->firmwareVendor, FIRMWARE_VENDOR, sizeof(FIRMWARE_VENDOR)); + efiSystemTable->FirmwareRevision = FIRMWARE_REVISION; + + // XXX: We may need to have basic implementations of ConIn/ConOut/StdErr + // The EFI spec states that all handles are invalid after boot services have been + // exited so we can probably get by with leaving the handles as zero. + efiSystemTable->ConsoleInHandle = 0; + efiSystemTable->ConIn = 0; + + efiSystemTable->ConsoleOutHandle = 0; + efiSystemTable->ConOut = 0; + + efiSystemTable->StandardErrorHandle = 0; + efiSystemTable->StdErr = 0; + + efiSystemTable->RuntimeServices = ptov64((EFI_PTR32)&fakeEfiPages->efiRuntimeServices); + // According to the EFI spec, BootServices aren't valid after the + // boot process is exited so we can probably do without it. + // Apple didn't provide a definition for it in pexpert/i386/efi.h + // so I'm guessing they don't use it. + efiSystemTable->BootServices = 0; + + efiSystemTable->NumberOfTableEntries = 0; + efiSystemTable->ConfigurationTable = ptov64((EFI_PTR32)fakeEfiPages->efiConfigurationTable); + + // We're done. Now CRC32 the thing so the kernel will accept it + gST64->Hdr.CRC32 = crc32(0L, gST64, gST64->Hdr.HeaderSize); + + // -------------------------------------------------------------------- + // Runtime services + EFI_RUNTIME_SERVICES_64 *efiRuntimeServices = &fakeEfiPages->efiRuntimeServices; + efiRuntimeServices->Hdr.Signature = EFI_RUNTIME_SERVICES_SIGNATURE; + efiRuntimeServices->Hdr.Revision = EFI_RUNTIME_SERVICES_REVISION; + efiRuntimeServices->Hdr.HeaderSize = sizeof(EFI_RUNTIME_SERVICES_64); + efiRuntimeServices->Hdr.CRC32 = 0; + efiRuntimeServices->Hdr.Reserved = 0; + + // There are a number of function pointers in the efiRuntimeServices table. + // These are the Foundation (e.g. core) services and are expected to be present on + // all EFI-compliant machines. Some kernel extensions (notably AppleEFIRuntime) + // will call these without checking to see if they are null. + // + // We don't really feel like doing an EFI implementation in the bootloader + // but it is nice if we can at least prevent a complete crash by + // at least providing some sort of implementation until one can be provided + // nicely in a kext. + + void (*voidret_fp)() = (void*)fakeEfiPages->voidret_instructions; + void (*unsupportedret_fp)() = (void*)fakeEfiPages->unsupportedret_instructions; + efiRuntimeServices->GetTime = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->SetTime = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->GetWakeupTime = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->SetWakeupTime = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->SetVirtualAddressMap = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->ConvertPointer = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->GetVariable = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->GetNextVariableName = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->SetVariable = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->GetNextHighMonotonicCount = ptov64((EFI_PTR32)unsupportedret_fp); + efiRuntimeServices->ResetSystem = ptov64((EFI_PTR32)voidret_fp); + + // We're done. Now CRC32 the thing so the kernel will accept it + efiRuntimeServices->Hdr.CRC32 = crc32(0L, efiRuntimeServices, efiRuntimeServices->Hdr.HeaderSize); + + // -------------------------------------------------------------------- + // Finish filling in the rest of the boot args that we need. + bootArgs->efiSystemTable = (uint32_t)efiSystemTable; + bootArgs->efiMode = kBootArgsEfiMode64; + + // The bootArgs structure as a whole is bzero'd so we don't need to fill in + // things like efiRuntimeServices* and what not. + // + // In fact, the only code that seems to use that is the hibernate code so it + // knows not to save the pages. It even checks to make sure its nonzero. +} + +/* + * In addition to the EFI tables there is also the EFI device tree node. + * In particular, we need /efi/platform to have an FSBFrequency key. Without it, + * the tsc_init function will panic very early on in kernel startup, before + * the console is available. + */ + +/*========================================================================== + * FSB Frequency detection + */ + +/* These should be const but DT__AddProperty takes char* */ +static const char const TSC_Frequency_prop[] = "TSCFrequency"; +static const char const FSB_Frequency_prop[] = "FSBFrequency"; +static const char const CPU_Frequency_prop[] = "CPUFrequency"; + +/*========================================================================== + * SMBIOS + */ + +/* From Foundation/Efi/Guid/Smbios/SmBios.c */ +EFI_GUID const gEfiSmbiosTableGuid = EFI_SMBIOS_TABLE_GUID; + +#define SMBIOS_RANGE_START 0x000F0000 +#define SMBIOS_RANGE_END 0x000FFFFF + +/* '_SM_' in little endian: */ +#define SMBIOS_ANCHOR_UINT32_LE 0x5f4d535f + +#define EFI_ACPI_TABLE_GUID \ +{ \ +0xeb9d2d30, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ +} + +#define EFI_ACPI_20_TABLE_GUID \ +{ \ +0x8868e871, 0xe4f1, 0x11d3, { 0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ +} + +EFI_GUID gEfiAcpiTableGuid = EFI_ACPI_TABLE_GUID; +EFI_GUID gEfiAcpi20TableGuid = EFI_ACPI_20_TABLE_GUID; + + +/*========================================================================== + * Fake EFI implementation + */ + +/* These should be const but DT__AddProperty takes char* */ +static const char const FIRMWARE_REVISION_PROP[] = "firmware-revision"; +static const char const FIRMWARE_ABI_PROP[] = "firmware-abi"; +static const char const FIRMWARE_VENDOR_PROP[] = "firmware-vendor"; +static const char const FIRMWARE_ABI_32_PROP_VALUE[] = "EFI32"; +static const char const FIRMWARE_ABI_64_PROP_VALUE[] = "EFI64"; +static const char const SYSTEM_ID_PROP[] = "system-id"; +static const char const SYSTEM_SERIAL_PROP[] = "SystemSerialNumber"; +static const char const SYSTEM_TYPE_PROP[] = "system-type"; +static const char const MODEL_PROP[] = "Model"; +static const char const BOARDID_PROP[] = "board-id"; + + +/* + * Get an smbios option string option to convert to EFI_CHAR16 string + */ + +static EFI_CHAR16* getSmbiosChar16(const char * key, size_t* len) +{ + const char *src = getStringForKey(key, &bootInfo->smbiosConfig); + EFI_CHAR16* dst = 0; + size_t i = 0; + + if (!key || !(*key) || !len || !src) return 0; + + *len = strlen(src); + dst = (EFI_CHAR16*) malloc( ((*len)+1) * 2 ); + for (; i < (*len); i++) dst[i] = src[i]; + dst[(*len)] = '\0'; + *len = ((*len)+1)*2; // return the CHAR16 bufsize in cluding zero terminated CHAR16 + return dst; +} + +/* + * Get the SystemID from the bios dmi info + */ + +static EFI_CHAR8* getSmbiosUUID() +{ + static EFI_CHAR8 uuid[UUID_LEN]; + int i, isZero, isOnes; + SMBByte *p; + + p = (SMBByte*)Platform.UUID; + + for (i=0, isZero=1, isOnes=1; ibootConfig); + EFI_CHAR8* ret = getUUIDFromString(sysId); + + if (!sysId || !ret) // try bios dmi info UUID extraction + { + ret = getSmbiosUUID(); + sysId = 0; + } + + if (!ret) // no bios dmi UUID available, set a fixed value for system-id + ret=getUUIDFromString((sysId = (const char*) SYSTEM_ID)); + + verbose("Customizing SystemID with : %s\n", getStringFromUUID(ret)); // apply a nice formatting to the displayed output + return ret; +} + +/* + * Must be called AFTER setup Acpi because we need to take care of correct + * facp content to reflect in ioregs + */ + +void setupSystemType() +{ + Node *node = DT__FindNode("/", false); + if (node == 0) stop("Couldn't get root node"); + // we need to write this property after facp parsing + // Export system-type only if it has been overrriden by the SystemType option + DT__AddProperty(node, SYSTEM_TYPE_PROP, sizeof(Platform.Type), &Platform.Type); +} + +void setupEfiDeviceTree(void) +{ + EFI_CHAR8* ret = 0; + EFI_CHAR16* ret16 = 0; + size_t len = 0; + Node *node; + + node = DT__FindNode("/", false); + + if (node == 0) stop("Couldn't get root node"); + + // We could also just do DT__FindNode("/efi/platform", true) + // But I think eventually we want to fill stuff in the efi node + // too so we might as well create it so we have a pointer for it too. + node = DT__AddChild(node, "efi"); + + if (archCpuType == CPU_TYPE_I386) + { + DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_32_PROP_VALUE), (char*)FIRMWARE_ABI_32_PROP_VALUE); + } + else + { + DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_64_PROP_VALUE), (char*)FIRMWARE_ABI_64_PROP_VALUE); + } + + DT__AddProperty(node, FIRMWARE_REVISION_PROP, sizeof(FIRMWARE_REVISION), (EFI_UINT32*)&FIRMWARE_REVISION); + DT__AddProperty(node, FIRMWARE_VENDOR_PROP, sizeof(FIRMWARE_VENDOR), (EFI_CHAR16*)FIRMWARE_VENDOR); + + // TODO: Fill in other efi properties if necessary + + // Set up the /efi/runtime-services table node similar to the way a child node of configuration-table + // is set up. That is, name and table properties + Node *runtimeServicesNode = DT__AddChild(node, "runtime-services"); + + if (archCpuType == CPU_TYPE_I386) + { + // The value of the table property is the 32-bit physical address for the RuntimeServices table. + // Since the EFI system table already has a pointer to it, we simply use the address of that pointer + // for the pointer to the property data. Warning.. DT finalization calls free on that but we're not + // the only thing to use a non-malloc'd pointer for something in the DT + + DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST32->RuntimeServices); + } + else + { + DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST64->RuntimeServices); + } + + // Set up the /efi/configuration-table node which will eventually have several child nodes for + // all of the configuration tables needed by various kernel extensions. + gEfiConfigurationTableNode = DT__AddChild(node, "configuration-table"); + + // Now fill in the /efi/platform Node + Node *efiPlatformNode = DT__AddChild(node, "platform"); + + // NOTE WELL: If you do add FSB Frequency detection, make sure to store + // the value in the fsbFrequency global and not an malloc'd pointer + // because the DT_AddProperty function does not copy its args. + + if (Platform.CPU.FSBFrequency != 0) + DT__AddProperty(efiPlatformNode, FSB_Frequency_prop, sizeof(uint64_t), &Platform.CPU.FSBFrequency); + + // Export TSC and CPU frequencies for use by the kernel or KEXTs + if (Platform.CPU.TSCFrequency != 0) + DT__AddProperty(efiPlatformNode, TSC_Frequency_prop, sizeof(uint64_t), &Platform.CPU.TSCFrequency); + + if (Platform.CPU.CPUFrequency != 0) + DT__AddProperty(efiPlatformNode, CPU_Frequency_prop, sizeof(uint64_t), &Platform.CPU.CPUFrequency); + + // Export system-id. Can be disabled with SystemId=No in com.apple.Boot.plist + if ((ret=getSystemID())) + DT__AddProperty(efiPlatformNode, SYSTEM_ID_PROP, UUID_LEN, (EFI_UINT32*) ret); + + // Export SystemSerialNumber if present + if ((ret16=getSmbiosChar16("SMserial", &len))) + DT__AddProperty(efiPlatformNode, SYSTEM_SERIAL_PROP, len, ret16); + + // Export Model if present + if ((ret16=getSmbiosChar16("SMproductname", &len))) + DT__AddProperty(efiPlatformNode, MODEL_PROP, len, ret16); + + // Fill /efi/device-properties node. + setupDeviceProperties(node); +} + +/* + * Must be called AFTER getSmbios + */ + +void setupBoardId() +{ + Node *node; + node = DT__FindNode("/", false); + if (node == 0) { + stop("Couldn't get root node"); + } + const char *boardid = getStringForKey("SMboardproduct", &bootInfo->smbiosConfig); + if (boardid) + DT__AddProperty(node, BOARDID_PROP, strlen(boardid)+1, (EFI_CHAR16*)boardid); +} + +/* + * Load the smbios.plist override config file if any + */ + +static void setupSmbiosConfigFile(const char *filename) +{ + char dirSpecSMBIOS[128] = ""; + const char *override_pathname = NULL; + int len = 0, err = 0; + extern void scan_mem(); + + // Take in account user overriding + if (getValueForKey(kSMBIOSKey, &override_pathname, &len, &bootInfo->bootConfig) && len > 0) + { + // Specify a path to a file, e.g. SMBIOS=/Extra/macProXY.plist + sprintf(dirSpecSMBIOS, override_pathname); + err = loadConfigFile(dirSpecSMBIOS, &bootInfo->smbiosConfig); + } + else + { + // Check selected volume's Extra. + sprintf(dirSpecSMBIOS, "/Extra/%s", filename); + if (err = loadConfigFile(dirSpecSMBIOS, &bootInfo->smbiosConfig)) + { + // Check booter volume/rdbt Extra. + sprintf(dirSpecSMBIOS, "bt(0,0)/Extra/%s", filename); + err = loadConfigFile(dirSpecSMBIOS, &bootInfo->smbiosConfig); + } + } + + if (err) + { + verbose("No SMBIOS replacement found.\n"); + } + + // get a chance to scan mem dynamically if user asks for it while having the config options loaded as well, + // as opposed to when it was in scan_platform(); also load the orig. smbios so that we can access dmi info without + // patching the smbios yet + + scan_mem(); +} + +/* + * Installs all the needed configuration table entries + */ + +static void setupEfiConfigurationTable() +{ + smbios_p = (EFI_PTR32)getSmbios(SMBIOS_PATCHED); + addConfigurationTable(&gEfiSmbiosTableGuid, &smbios_p, NULL); + + setupBoardId(); //need to be called after getSmbios + + // Setup ACPI with DSDT overrides (mackerintel's patch) + setupAcpi(); + + // We've obviously changed the count.. so fix up the CRC32 + if (archCpuType == CPU_TYPE_I386) + { + gST32->Hdr.CRC32 = 0; + gST32->Hdr.CRC32 = crc32(0L, gST32, gST32->Hdr.HeaderSize); + } + else + { + gST64->Hdr.CRC32 = 0; + gST64->Hdr.CRC32 = crc32(0L, gST64, gST64->Hdr.HeaderSize); + } +} + +void saveOriginalSMBIOS(void) +{ + Node *node; + SMBEntryPoint *origeps; + void *tableAddress; + + node = DT__FindNode("/efi/platform", false); + if (!node) + { + verbose("/efi/platform node not found\n"); + return; + } + + origeps = getSmbios(SMBIOS_ORIGINAL); + if (!origeps) + { + return; + } + + tableAddress = (void *)AllocateKernelMemory(origeps->dmi.tableLength); + if (!tableAddress) + { + return; + } + + memcpy(tableAddress, (void *)origeps->dmi.tableAddress, origeps->dmi.tableLength); + DT__AddProperty(node, "SMBIOS", origeps->dmi.tableLength, tableAddress); +} + +/* + * Entrypoint from boot.c + */ + +void setupFakeEfi(void) +{ + // Generate efi device strings + setup_pci_devs(root_pci_dev); + + readSMBIOSInfo(getSmbios(SMBIOS_ORIGINAL)); + + // load smbios.plist file if any + setupSmbiosConfigFile("smbios.plist"); + + setupSMBIOSTable(); + + // Initialize the base table + if (archCpuType == CPU_TYPE_I386) + { + setupEfiTables32(); + } + else + { + setupEfiTables64(); + } + + // Initialize the device tree + setupEfiDeviceTree(); + + saveOriginalSMBIOS(); + + // Add configuration table entries to both the services table and the device tree + setupEfiConfigurationTable(); +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/smbios_getters.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/smbios_getters.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/smbios_getters.c.svn-base (revision 850) @@ -0,0 +1,327 @@ +/* + * Add (c) here + * + * Copyright .... All rights reserved. + * + */ + +#include "smbios_getters.h" + +#ifndef DEBUG_SMBIOS +#define DEBUG_SMBIOS 0 +#endif + +#if DEBUG_SMBIOS +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + + +bool getProcessorInformationExternalClock(returnType *value) +{ + value->word = Platform.CPU.FSBFrequency/1000000; + return true; +} + +bool getProcessorInformationMaximumClock(returnType *value) +{ + value->word = Platform.CPU.CPUFrequency/1000000; + return true; +} + +bool getSMBOemProcessorBusSpeed(returnType *value) +{ + if (Platform.CPU.Vendor == 0x756E6547) // Intel + { + switch (Platform.CPU.Family) + { + case 0x06: + { + switch (Platform.CPU.Model) + { + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah 0x0E + case CPU_MODEL_MEROM: // Merom 0x0F + case CPU_MODEL_PENRYN: // Penryn 0x17 + case CPU_MODEL_ATOM: // Atom 45nm 0x1C + return false; + + case 0x19: // Intel Core i5 650 @3.20 Ghz + case CPU_MODEL_SANDY: // Intel Core i5, i7 LGA1155 sandy bridge + case CPU_MODEL_SANDY_XEON: + case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) + case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core + case CPU_MODEL_NEHALEM_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + { + // thanks to dgobe for i3/i5/i7 bus speed detection + int nhm_bus = 0x3F; + static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F}; + unsigned long did, vid; + int i; + + // Nehalem supports Scrubbing + // First, locate the PCI bus where the MCH is located + for(i = 0; i < sizeof(possible_nhm_bus); i++) + { + vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00); + did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02); + vid &= 0xFFFF; + did &= 0xFF00; + + if(vid == 0x8086 && did >= 0x2C00) + nhm_bus = possible_nhm_bus[i]; + } + + unsigned long qpimult, qpibusspeed; + qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50); + qpimult &= 0x7F; + DBG("qpimult %d\n", qpimult); + qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000)); + // Rek: rounding decimals to match original mac profile info + if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100; + DBG("qpibusspeed %d\n", qpibusspeed); + value->word = qpibusspeed; + return true; + } + } + } + } + } + return false; +} + +uint16_t simpleGetSMBOemProcessorType(void) +{ + if (Platform.CPU.NoCores >= 4) + { + return 0x0501; // Quad-Core Xeon + } + else if (Platform.CPU.NoCores == 1) + { + return 0x0201; // Core Solo + }; + + return 0x0301; // Core 2 Duo +} + +bool getSMBOemProcessorType(returnType *value) +{ + static bool done = false; + + value->word = simpleGetSMBOemProcessorType(); + + if (Platform.CPU.Vendor == 0x756E6547) // Intel + { + if (!done) + { + verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model); + done = true; + } + + switch (Platform.CPU.Family) + { + case 0x06: + { + switch (Platform.CPU.Model) + { + case 0x0D: // ? + case CPU_MODEL_YONAH: // Yonah + case CPU_MODEL_MEROM: // Merom + case CPU_MODEL_PENRYN: // Penryn + case CPU_MODEL_ATOM: // Intel Atom (45nm) + return true; + + case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + if (strstr(Platform.CPU.BrandString, "Xeon(R)")) + value->word = 0x0501; // Xeon + else + value->word = 0x0701; // Core i7 + + return true; + + case CPU_MODEL_FIELDS: // Lynnfield, Clarksfield, Jasper + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + value->word = 0x601; // Core i5 + else + value->word = 0x0701; // Core i7 + return true; + + case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale) + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + value->word = 0x601; // Core i5 + else + value->word = 0x0701; // Core i7 + return true; + + case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 sandy bridge + case CPU_MODEL_SANDY_XEON: + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) + value->word = 0x901; // Core i3 + else + if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) + value->word = 0x601; // Core i5 + else + value->word = 0x0701; // Core i7 + return true; + + case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS) + case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + value->word = 0x0501; // Core i7 + return true; + + case 0x19: // Intel Core i5 650 @3.20 Ghz + value->word = 0x601; // Core i5 + return true; + } + } + } + } + + return false; +} + +bool getSMBMemoryDeviceMemoryType(returnType *value) +{ + static int idx = -1; + int map; + + idx++; + if (idx < MAX_RAM_SLOTS) + { + map = Platform.DMI.DIMM[idx]; + if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) + { + DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type); + value->byte = Platform.RAM.DIMM[map].Type; + return true; + } + } + + return false; +// value->byte = SMB_MEM_TYPE_DDR2; +// return true; +} + +bool getSMBMemoryDeviceMemorySpeed(returnType *value) +{ + static int idx = -1; + int map; + + idx++; + if (idx < MAX_RAM_SLOTS) + { + map = Platform.DMI.DIMM[idx]; + if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) + { + DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency); + value->dword = Platform.RAM.DIMM[map].Frequency; + return true; + } + } + + return false; +// value->dword = 800; +// return true; +} + +bool getSMBMemoryDeviceManufacturer(returnType *value) +{ + static int idx = -1; + int map; + + idx++; + if (idx < MAX_RAM_SLOTS) + { + map = Platform.DMI.DIMM[idx]; + if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) + { + DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor); + value->string = Platform.RAM.DIMM[map].Vendor; + return true; + } + } + +// return false; + value->string = NOT_AVAILABLE; + return true; +} + +bool getSMBMemoryDeviceSerialNumber(returnType *value) +{ + static int idx = -1; + int map; + + idx++; + if (idx < MAX_RAM_SLOTS) + { + map = Platform.DMI.DIMM[idx]; + if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) + { + DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo); + value->string = Platform.RAM.DIMM[map].SerialNo; + return true; + } + } + +// return false; + value->string = NOT_AVAILABLE; + return true; +} + +bool getSMBMemoryDevicePartNumber(returnType *value) +{ + static int idx = -1; + int map; + + idx++; + if (idx < MAX_RAM_SLOTS) + { + map = Platform.DMI.DIMM[idx]; + if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) + { + DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo); + value->string = Platform.RAM.DIMM[map].PartNo; + return true; + } + } + +// return false; + value->string = NOT_AVAILABLE; + return true; +} + + +// getting smbios addr with fast compare ops, late checksum testing ... +#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) ) +static const char * const SMTAG = "_SM_"; +static const char* const DMITAG = "_DMI_"; + +SMBEntryPoint *getAddressOfSmbiosTable(void) +{ + SMBEntryPoint *smbios; + /* + * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking + * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_"). + */ + smbios = (SMBEntryPoint*)SMBIOS_RANGE_START; + while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) { + if (COMPARE_DWORD(smbios->anchor, SMTAG) && + COMPARE_DWORD(smbios->dmi.anchor, DMITAG) && + smbios->dmi.anchor[4] == DMITAG[4] && + checksum8(smbios, sizeof(SMBEntryPoint)) == 0) + { + return smbios; + } + smbios = (SMBEntryPoint*)(((char*)smbios) + 16); + } + printf("ERROR: Unable to find SMBIOS!\n"); + pause(); + return NULL; +} + Index: branches/Chimera/i386/libsaio/.svn/text-base/disk.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/disk.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/disk.c.svn-base (revision 850) @@ -0,0 +1,2010 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Mach Operating System + * Copyright (c) 1990 Carnegie-Mellon University + * Copyright (c) 1989 Carnegie-Mellon University + * All rights reserved. The CMU software License Agreement specifies + * the terms and conditions for use and redistribution. + */ + +/* + * INTEL CORPORATION PROPRIETARY INFORMATION + * + * This software is supplied under the terms of a license agreement or + * nondisclosure agreement with Intel Corporation and may not be copied + * nor disclosed except in accordance with the terms of that agreement. + * + * Copyright 1988, 1989 Intel Corporation + */ + +/* + * Copyright 1993 NeXT Computer, Inc. + * All rights reserved. + */ + +/* Copyright 2007 VMware Inc. + "Preboot" ramdisk support added by David Elliott + GPT support added by David Elliott. Based on IOGUIDPartitionScheme.cpp. + */ + +// Allow UFS_SUPPORT to be overridden with preprocessor option. +#ifndef UFS_SUPPORT +// zef: Disabled UFS support +#define UFS_SUPPORT 0 +#endif + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "fdisk.h" +#if UFS_SUPPORT +#include "ufs.h" +#endif +#include "hfs.h" +#include "ntfs.h" +#include "msdos.h" +#include "ext2fs.h" + +#include "xml.h" +#include "disk.h" + +#include +#include +#include +typedef struct gpt_hdr gpt_hdr; +typedef struct gpt_ent gpt_ent; + +// For EFI_GUID +#include "efi.h" +#include "efi_tables.h" + +#define PROBEFS_SIZE BPS * 4 /* buffer size for filesystem probe */ +#define CD_BPS 2048 /* CD-ROM block size */ +#define N_CACHE_SECS (BIOS_LEN / BPS) /* Must be a multiple of 4 for CD-ROMs */ +#define UFS_FRONT_PORCH 0 +#define kAPMSector 2 /* Sector number of Apple partition map */ +#define kAPMCDSector 8 /* Translated sector of Apple partition map on a CD */ + +/* + * IORound and IOTrunc convenience functions, in the spirit + * of vm's round_page() and trunc_page(). + */ +#define IORound(value,multiple) \ + ((((value) + (multiple) - 1) / (multiple)) * (multiple)) + +#define IOTrunc(value,multiple) \ + (((value) / (multiple)) * (multiple)); + +/* + * trackbuf points to the start of the track cache. Biosread() + * will store the sectors read from disk to this memory area. + * + * biosbuf points to a sector within the track cache, and is + * updated by Biosread(). + */ +static char * const trackbuf = (char *) ptov(BIOS_ADDR); +static char * biosbuf; + +/* + * Map a disk drive to bootable volumes contained within. + */ +struct DiskBVMap { + int biosdev; // BIOS device number (unique) + BVRef bvr; // chain of boot volumes on the disk + int bvrcnt; // number of boot volumes + struct DiskBVMap * next; // linkage to next mapping +}; + +static struct DiskBVMap * gDiskBVMap = NULL; +static struct disk_blk0 * gBootSector = NULL; + +// Function pointers to be filled in if ramdisks are available: +int (*p_ramdiskReadBytes)( int biosdev, unsigned int blkno, + unsigned int byteoff, + unsigned int byteCount, void * buffer ) = NULL; +int (*p_get_ramdisk_info)(int biosdev, struct driveInfo *dip) = NULL; + + +extern void spinActivityIndicator(int sectors); + +//========================================================================== + +static int getDriveInfo( int biosdev, struct driveInfo *dip ) +{ + static struct driveInfo cached_di; + int cc; + + // Real BIOS devices are 8-bit, so anything above that is for internal use. + // Don't cache ramdisk drive info since it doesn't require several BIOS + // calls and is thus not worth it. + if(biosdev >= 0x100) + { + if(p_get_ramdisk_info != NULL) + cc = (*p_get_ramdisk_info)(biosdev, dip); + else + cc = -1; + if(cc < 0) + { + dip->valid = 0; + return -1; + } + else + return 0; + } + + if ( !cached_di.valid || biosdev != cached_di.biosdev ) + { + cc = get_drive_info(biosdev, &cached_di); + if (cc < 0) { + cached_di.valid = 0; + DEBUG_DISK(("get_drive_info returned error\n")); + return (-1); // BIOS call error + } + } + + bcopy(&cached_di, dip, sizeof(cached_di)); + + return 0; +} + +//========================================================================== +// Maps (E)BIOS return codes to message strings. + +struct NamedValue { + unsigned char value; + const char * name; +}; + +static const char * getNameForValue( const struct NamedValue * nameTable, + unsigned char value ) +{ + const struct NamedValue * np; + + for ( np = nameTable; np->value; np++) + if (np->value == value) + return np->name; + + return NULL; +} + +#define ECC_CORRECTED_ERR 0x11 + +static const struct NamedValue bios_errors[] = { + { 0x10, "Media error" }, + { 0x11, "Corrected ECC error" }, + { 0x20, "Controller or device error" }, + { 0x40, "Seek failed" }, + { 0x80, "Device timeout" }, + { 0xAA, "Drive not ready" }, + { 0x00, 0 } +}; + +static const char * bios_error(int errnum) +{ + static char errorstr[] = "Error 0x00"; + const char * errname; + + errname = getNameForValue( bios_errors, errnum ); + if ( errname ) return errname; + + sprintf(errorstr, "Error 0x%02x", errnum); + return errorstr; // No string, print error code only +} + +//========================================================================== +// Use BIOS INT13 calls to read the sector specified. This function will +// also perform read-ahead to cache a few subsequent sector to the sector +// cache. +// +// Return: +// 0 on success, or an error code from INT13/F2 or INT13/F42 BIOS call. + +static bool cache_valid = false; + +static int Biosread( int biosdev, unsigned long long secno ) +{ + static int xbiosdev, xcyl, xhead; + static unsigned int xsec, xnsecs; + struct driveInfo di; + + int rc = -1; + int cyl, head, sec; + int tries = 0; + int bps, divisor; + + if (getDriveInfo(biosdev, &di) < 0) { + return -1; + } + if (di.no_emulation) { + /* Always assume 2k block size; BIOS may lie about geometry */ + bps = 2048; + } else { + bps = di.di.params.phys_nbps; + if (bps == 0) { + return -1; + } + } + divisor = bps / BPS; + + DEBUG_DISK(("Biosread dev %x sec %d bps %d\n", biosdev, secno, bps)); + + // To read the disk sectors, use EBIOS if we can. Otherwise, + // revert to the standard BIOS calls. + + if ((biosdev >= kBIOSDevTypeHardDrive) && + (di.uses_ebios & EBIOS_FIXED_DISK_ACCESS)) + { + if (cache_valid && + (biosdev == xbiosdev) && + (secno >= xsec) && + ((unsigned int)secno < (xsec + xnsecs))) + { + biosbuf = trackbuf + (BPS * (secno - xsec)); + return 0; + } + + xnsecs = N_CACHE_SECS; + xsec = (secno / divisor) * divisor; + cache_valid = false; + + while ((rc = ebiosread(biosdev, secno / divisor, xnsecs / divisor)) && (++tries < 5)) + { + if (rc == ECC_CORRECTED_ERR) { + /* Ignore corrected ECC errors */ + rc = 0; + break; + } + error(" EBIOS read error: %s\n", bios_error(rc), rc); + error(" Block 0x%x Sectors %d\n", secno, xnsecs); + sleep(1); + } + } + else + { + /* spc = spt * heads */ + int spc = (di.di.params.phys_spt * di.di.params.phys_heads); + cyl = secno / spc; + head = (secno % spc) / di.di.params.phys_spt; + sec = secno % di.di.params.phys_spt; + + if (cache_valid && + (biosdev == xbiosdev) && + (cyl == xcyl) && + (head == xhead) && + ((unsigned int)sec >= xsec) && + ((unsigned int)sec < (xsec + xnsecs))) + { + // this sector is in trackbuf cache + biosbuf = trackbuf + (BPS * (sec - xsec)); + return 0; + } + + // Cache up to a track worth of sectors, but do not cross a + // track boundary. + + xcyl = cyl; + xhead = head; + xsec = sec; + xnsecs = ((unsigned int)(sec + N_CACHE_SECS) > di.di.params.phys_spt) ? (di.di.params.phys_spt - sec) : N_CACHE_SECS; + cache_valid = false; + + while ((rc = biosread(biosdev, cyl, head, sec, xnsecs)) && + (++tries < 5)) + { + if (rc == ECC_CORRECTED_ERR) { + /* Ignore corrected ECC errors */ + rc = 0; + break; + } + error(" BIOS read error: %s\n", bios_error(rc), rc); + error(" Block %d, Cyl %d Head %d Sector %d\n", + secno, cyl, head, sec); + sleep(1); + } + } + + // If the BIOS reported success, mark the sector cache as valid. + + if (rc == 0) { + cache_valid = true; + } + biosbuf = trackbuf + (secno % divisor) * BPS; + xbiosdev = biosdev; + + spinActivityIndicator(xnsecs); + + return rc; +} + +//========================================================================== + +int testBiosread( int biosdev, unsigned long long secno ) +{ + return Biosread(biosdev, secno); +} + +//========================================================================== + +static int readBytes( int biosdev, unsigned long long blkno, + unsigned int byteoff, + unsigned int byteCount, void * buffer ) +{ + // ramdisks require completely different code for reading. + if(p_ramdiskReadBytes != NULL && biosdev >= 0x100) + return (*p_ramdiskReadBytes)(biosdev, blkno, byteoff, byteCount, buffer); + + char * cbuf = (char *) buffer; + int error; + int copy_len; + + DEBUG_DISK(("%s: dev %x block %x [%d] -> 0x%x...", __FUNCTION__, + biosdev, blkno, byteCount, (unsigned)cbuf)); + + for ( ; byteCount; cbuf += copy_len, blkno++ ) + { + error = Biosread( biosdev, blkno ); + if ( error ) + { + DEBUG_DISK(("error\n")); + return (-1); + } + + copy_len = ((byteCount + byteoff) > BPS) ? (BPS - byteoff) : byteCount; + bcopy( biosbuf + byteoff, cbuf, copy_len ); + byteCount -= copy_len; + byteoff = 0; + } + + DEBUG_DISK(("done\n")); + + return 0; +} + +//========================================================================== + +static int isExtendedFDiskPartition( const struct fdisk_part * part ) +{ + static unsigned char extParts[] = + { + 0x05, /* Extended */ + 0x0f, /* Win95 extended */ + 0x85, /* Linux extended */ + }; + + unsigned int i; + + for (i = 0; i < sizeof(extParts)/sizeof(extParts[0]); i++) + { + if (extParts[i] == part->systid) return 1; + } + return 0; +} + +//========================================================================== + +static int getNextFDiskPartition( int biosdev, int * partno, + const struct fdisk_part ** outPart ) +{ + static int sBiosdev = -1; + static int sNextPartNo; + static unsigned int sFirstBase; + static unsigned int sExtBase; + static unsigned int sExtDepth; + static struct fdisk_part * sExtPart; + struct fdisk_part * part; + + if ( sBiosdev != biosdev || *partno < 0 ) + { + // Fetch MBR. + if ( readBootSector( biosdev, DISK_BLK0, 0 ) ) return 0; + + sBiosdev = biosdev; + sNextPartNo = 0; + sFirstBase = 0; + sExtBase = 0; + sExtDepth = 0; + sExtPart = NULL; + } + + while (1) + { + part = NULL; + + if ( sNextPartNo < FDISK_NPART ) + { + part = (struct fdisk_part *) gBootSector->parts[sNextPartNo]; + } + else if ( sExtPart ) + { + unsigned int blkno = sExtPart->relsect + sFirstBase; + + // Save the block offset of the first extended partition. + + if (sExtDepth == 0) { + sFirstBase = blkno; + } + sExtBase = blkno; + + // Load extended partition table. + + if ( readBootSector( biosdev, blkno, 0 ) == 0 ) + { + sNextPartNo = 0; + sExtDepth++; + sExtPart = NULL; + continue; + } + // Fall through to part == NULL + } + + if ( part == NULL ) break; // Reached end of partition chain. + + // Advance to next partition number. + + sNextPartNo++; + + if ( isExtendedFDiskPartition(part) ) + { + sExtPart = part; + continue; + } + + // Skip empty slots. + + if ( part->systid == 0x00 ) + { + continue; + } + + // Change relative offset to an absolute offset. + part->relsect += sExtBase; + + *outPart = part; + *partno = sExtDepth ? (int)(sExtDepth + FDISK_NPART) : sNextPartNo; + + break; + } + + return (part != NULL); +} + +//========================================================================== + +static BVRef newFDiskBVRef( int biosdev, int partno, unsigned int blkoff, + const struct fdisk_part * part, + FSInit initFunc, FSLoadFile loadFunc, + FSReadFile readFunc, + FSGetDirEntry getdirFunc, + FSGetFileBlock getBlockFunc, + FSGetUUID getUUIDFunc, + BVGetDescription getDescriptionFunc, + BVFree bvFreeFunc, + int probe, int type, unsigned int bvrFlags ) +{ + BVRef bvr = (BVRef) malloc( sizeof(*bvr) ); + if ( bvr ) + { + bzero(bvr, sizeof(*bvr)); + + bvr->biosdev = biosdev; + bvr->part_no = partno; + bvr->part_boff = blkoff; + bvr->part_type = part->systid; + bvr->fs_loadfile = loadFunc; + bvr->fs_readfile = readFunc; + bvr->fs_getdirentry = getdirFunc; + bvr->fs_getfileblock= getBlockFunc; + bvr->fs_getuuid = getUUIDFunc; + bvr->description = getDescriptionFunc; + bvr->type = type; + bvr->bv_free = bvFreeFunc; + + if ((part->bootid & FDISK_ACTIVE) && (part->systid == FDISK_HFS)) + bvr->flags |= kBVFlagPrimary; + + // Probe the filesystem. + + if ( initFunc ) + { + bvr->flags |= kBVFlagNativeBoot; + + if ( probe && initFunc( bvr ) != 0 ) + { + // filesystem probe failed. + + DEBUG_DISK(("%s: failed probe on dev %x part %d\n", + __FUNCTION__, biosdev, partno)); + + (*bvr->bv_free)(bvr); + bvr = NULL; + } + if ( readBootSector( biosdev, blkoff, (void *)0x7e00 ) == 0 ) + { + bvr->flags |= kBVFlagBootable; + } + } + else if ( readBootSector( biosdev, blkoff, (void *)0x7e00 ) == 0 ) + { + bvr->flags |= kBVFlagForeignBoot; + } + else + { + (*bvr->bv_free)(bvr); + bvr = NULL; + } + } + if (bvr) bvr->flags |= bvrFlags; + return bvr; +} + +//========================================================================== + +BVRef newAPMBVRef( int biosdev, int partno, unsigned int blkoff, + const DPME * part, + FSInit initFunc, FSLoadFile loadFunc, + FSReadFile readFunc, + FSGetDirEntry getdirFunc, + FSGetFileBlock getBlockFunc, + FSGetUUID getUUIDFunc, + BVGetDescription getDescriptionFunc, + BVFree bvFreeFunc, + int probe, int type, unsigned int bvrFlags ) +{ + BVRef bvr = (BVRef) malloc( sizeof(*bvr) ); + if ( bvr ) + { + bzero(bvr, sizeof(*bvr)); + + bvr->biosdev = biosdev; + bvr->part_no = partno; + bvr->part_boff = blkoff; + bvr->fs_loadfile = loadFunc; + bvr->fs_readfile = readFunc; + bvr->fs_getdirentry = getdirFunc; + bvr->fs_getfileblock= getBlockFunc; + bvr->fs_getuuid = getUUIDFunc; + bvr->description = getDescriptionFunc; + bvr->type = type; + bvr->bv_free = bvFreeFunc; + strlcpy(bvr->name, part->dpme_name, DPISTRLEN); + strlcpy(bvr->type_name, part->dpme_type, DPISTRLEN); + + /* + if ( part->bootid & FDISK_ACTIVE ) + bvr->flags |= kBVFlagPrimary; + */ + + // Probe the filesystem. + + if ( initFunc ) + { + bvr->flags |= kBVFlagNativeBoot | kBVFlagBootable | kBVFlagSystemVolume; + + if ( probe && initFunc( bvr ) != 0 ) + { + // filesystem probe failed. + + DEBUG_DISK(("%s: failed probe on dev %x part %d\n", + __FUNCTION__, biosdev, partno)); + + (*bvr->bv_free)(bvr); + bvr = NULL; + } + } + /* + else if ( readBootSector( biosdev, blkoff, (void *)0x7e00 ) == 0 ) + { + bvr->flags |= kBVFlagForeignBoot; + } + */ + else + { + (*bvr->bv_free)(bvr); + bvr = NULL; + } + } + if (bvr) bvr->flags |= bvrFlags; + return bvr; +} + +//========================================================================== + +// HFS+ GUID in LE form +EFI_GUID const GPT_HFS_GUID = { 0x48465300, 0x0000, 0x11AA, { 0xAA, 0x11, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC } }; +// turbo - also our booter partition +EFI_GUID const GPT_BOOT_GUID = { 0x426F6F74, 0x0000, 0x11AA, { 0xAA, 0x11, 0x00, 0x30, 0x65, 0x43, 0xEC, 0xAC } }; +// turbo - or an efi system partition +EFI_GUID const GPT_EFISYS_GUID = { 0xC12A7328, 0xF81F, 0x11D2, { 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B } }; +// zef - basic data partition EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 for foreign OS support +EFI_GUID const GPT_BASICDATA_GUID = { 0xEBD0A0A2, 0xB9E5, 0x4433, { 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7 } }; +EFI_GUID const GPT_BASICDATA2_GUID = { 0xE3C9E316, 0x0B5C, 0x4DB8, { 0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE } }; + + +BVRef newGPTBVRef( int biosdev, int partno, unsigned int blkoff, + const gpt_ent * part, + FSInit initFunc, FSLoadFile loadFunc, + FSReadFile readFunc, + FSGetDirEntry getdirFunc, + FSGetFileBlock getBlockFunc, + FSGetUUID getUUIDFunc, + BVGetDescription getDescriptionFunc, + BVFree bvFreeFunc, + int probe, int type, unsigned int bvrFlags ) +{ + BVRef bvr = (BVRef) malloc( sizeof(*bvr) ); + if ( bvr ) + { + bzero(bvr, sizeof(*bvr)); + + bvr->biosdev = biosdev; + bvr->part_no = partno; + bvr->part_boff = blkoff; + bvr->fs_loadfile = loadFunc; + bvr->fs_readfile = readFunc; + bvr->fs_getdirentry = getdirFunc; + bvr->fs_getfileblock= getBlockFunc; + bvr->fs_getuuid = getUUIDFunc; + bvr->description = getDescriptionFunc; + bvr->type = type; + bvr->bv_free = bvFreeFunc; + // FIXME: UCS-2 -> UTF-8 the name + strlcpy(bvr->name, "----", DPISTRLEN); + if ( (efi_guid_compare(&GPT_BOOT_GUID, (EFI_GUID const*)part->ent_type) == 0) || + (efi_guid_compare(&GPT_HFS_GUID, (EFI_GUID const*)part->ent_type) == 0) ) + strlcpy(bvr->type_name, "GPT HFS+", DPISTRLEN); + else + strlcpy(bvr->type_name, "GPT Unknown", DPISTRLEN); + + /* + if ( part->bootid & FDISK_ACTIVE ) + bvr->flags |= kBVFlagPrimary; + */ + + // Probe the filesystem. + + if ( initFunc ) + { + bvr->flags |= kBVFlagNativeBoot; + + if ( probe && initFunc( bvr ) != 0 ) + { + // filesystem probe failed. + + DEBUG_DISK(("%s: failed probe on dev %x part %d\n", + __FUNCTION__, biosdev, partno)); + + (*bvr->bv_free)(bvr); + bvr = NULL; + } + if ( readBootSector( biosdev, blkoff, (void *)0x7e00 ) == 0 ) + { + bvr->flags |= kBVFlagBootable; + } + } + else if ( readBootSector( biosdev, blkoff, (void *)0x7e00 ) == 0 ) + { + bvr->flags |= kBVFlagForeignBoot; + } + else + { + (*bvr->bv_free)(bvr); + bvr = NULL; + } + } + if (bvr) bvr->flags |= bvrFlags; + return bvr; +} + +//========================================================================== + +/* A note on partition numbers: + * IOKit makes the primary partitions numbers 1-4, and then + * extended partitions are numbered consecutively 5 and up. + * So, for example, if you have two primary partitions and + * one extended partition they will be numbered 1, 2, 5. + */ + +static BVRef diskScanFDiskBootVolumes( int biosdev, int * countPtr ) +{ + const struct fdisk_part * part; + struct DiskBVMap * map; + int partno = -1; + BVRef bvr; +#if UFS_SUPPORT + BVRef booterUFS = NULL; +#endif + int spc; + struct driveInfo di; + boot_drive_info_t *dp; + + /* Initialize disk info */ + if (getDriveInfo(biosdev, &di) != 0) { + return NULL; + } + dp = &di.di; + spc = (dp->params.phys_spt * dp->params.phys_heads); + if (spc == 0) { + /* This is probably a CD-ROM; punt on the geometry. */ + spc = 1; + } + + do { + // Create a new mapping. + + map = (struct DiskBVMap *) malloc( sizeof(*map) ); + if ( map ) + { + map->biosdev = biosdev; + map->bvr = NULL; + map->bvrcnt = 0; + map->next = gDiskBVMap; + gDiskBVMap = map; + + // Create a record for each partition found on the disk. + + while ( getNextFDiskPartition( biosdev, &partno, &part ) ) + { + DEBUG_DISK(("%s: part %d [%x]\n", __FUNCTION__, + partno, part->systid)); + bvr = 0; + + switch ( part->systid ) + { +#if UFS_SUPPORT + case FDISK_UFS: + bvr = newFDiskBVRef( + biosdev, partno, + part->relsect + UFS_FRONT_PORCH/BPS, + part, + UFSInitPartition, + UFSLoadFile, + UFSReadFile, + UFSGetDirEntry, + UFSGetFileBlock, + UFSGetUUID, + UFSGetDescription, + UFSFree, + 0, + kBIOSDevTypeHardDrive, 0); + break; +#endif + + case FDISK_HFS: + bvr = newFDiskBVRef( + biosdev, partno, + part->relsect, + part, + HFSInitPartition, + HFSLoadFile, + HFSReadFile, + HFSGetDirEntry, + HFSGetFileBlock, + HFSGetUUID, + HFSGetDescription, + HFSFree, + 0, + kBIOSDevTypeHardDrive, 0); + break; + + // turbo - we want the booter type scanned also + case FDISK_BOOTER: + if (part->bootid & FDISK_ACTIVE) + gBIOSBootVolume = newFDiskBVRef( + biosdev, partno, + part->relsect, + part, + HFSInitPartition, + HFSLoadFile, + HFSReadFile, + HFSGetDirEntry, + HFSGetFileBlock, + HFSGetUUID, + HFSGetDescription, + HFSFree, + 0, + kBIOSDevTypeHardDrive, 0); + break; + +#if UFS_SUPPORT + case FDISK_BOOTER: + booterUFS = newFDiskBVRef( + biosdev, partno, + ((part->relsect + spc - 1) / spc) * spc, + part, + UFSInitPartition, + UFSLoadFile, + UFSReadFile, + UFSGetDirEntry, + UFSGetFileBlock, + UFSGetUUID, + UFSGetDescription, + UFSFree, + 0, + kBIOSDevTypeHardDrive, 0); + break; +#endif + + case FDISK_FAT32: + case FDISK_DOS12: + case FDISK_DOS16S: + case FDISK_DOS16B: + case FDISK_SMALLFAT32: + case FDISK_DOS16SLBA: + bvr = newFDiskBVRef( + biosdev, partno, + part->relsect, + part, + MSDOSInitPartition, + MSDOSLoadFile, + MSDOSReadFile, + MSDOSGetDirEntry, + MSDOSGetFileBlock, + MSDOSGetUUID, + MSDOSGetDescription, + MSDOSFree, + 0, + kBIOSDevTypeHardDrive, 0); + break; + + case FDISK_NTFS: + bvr = newFDiskBVRef( + biosdev, partno, + part->relsect, + part, + 0, 0, 0, 0, 0, + NTFSGetUUID, + NTFSGetDescription, + (BVFree)free, + 0, kBIOSDevTypeHardDrive, 0); + break; + + case FDISK_LINUX: + bvr = newFDiskBVRef( + biosdev, partno, + part->relsect, + part, + 0, 0, 0, 0, 0, 0, + EX2GetDescription, + (BVFree)free, + 0, kBIOSDevTypeHardDrive, 0); + break; + + default: + bvr = newFDiskBVRef( + biosdev, partno, + part->relsect, + part, + 0, 0, 0, 0, 0, 0, 0, + (BVFree)free, + 0, + kBIOSDevTypeHardDrive, 0); + break; + } + + if ( bvr ) + { + bvr->next = map->bvr; + map->bvr = bvr; + map->bvrcnt++; + } + } + +#if UFS_SUPPORT + // Booting from a CD with an UFS filesystem embedded + // in a booter partition. + + if ( booterUFS ) + { + if ( map->bvrcnt == 0 ) + { + map->bvr = booterUFS; + map->bvrcnt++; + } + else free( booterUFS ); + } +#endif + } + } while (0); + + /* + * If no FDisk partition, then we will check for + * an Apple partition map elsewhere. + */ +#if UNUSED + if (map->bvrcnt == 0) { + static struct fdisk_part cdpart; + cdpart.systid = 0xCD; + + /* Let's try assuming we are on a hybrid HFS/ISO9660 CD. */ + bvr = newFDiskBVRef( + biosdev, 0, + 0, + &cdpart, + HFSInitPartition, + HFSLoadFile, + HFSReadFile, + HFSGetDirEntry, + HFSGetFileBlock, + HFSGetUUID, + 0, + kBIOSDevTypeHardDrive); + bvr->next = map->bvr; + map->bvr = bvr; + map->bvrcnt++; + } +#endif + // Actually this should always be true given the above code + if(map == gDiskBVMap) + { + // Don't leave a null map in the chain + if(map->bvrcnt == 0 && map->bvr == NULL) + { + gDiskBVMap = map->next; + free(map); + map = NULL; + } + } + + if (countPtr) *countPtr = map ? map->bvrcnt : 0; + + return map ? map->bvr : NULL; +} + +//========================================================================== + +static BVRef diskScanAPMBootVolumes( int biosdev, int * countPtr ) +{ + struct DiskBVMap * map; + struct Block0 *block0_p; + unsigned int blksize; + unsigned int factor; + void *buffer = malloc(BPS); + + /* Check for alternate block size */ + if (readBytes( biosdev, 0, 0, BPS, buffer ) != 0) { + return NULL; + } + block0_p = buffer; + if (OSSwapBigToHostInt16(block0_p->sbSig) == BLOCK0_SIGNATURE) { + blksize = OSSwapBigToHostInt16(block0_p->sbBlkSize); + if (blksize != BPS) { + free(buffer); + buffer = malloc(blksize); + } + factor = blksize / BPS; + } else { + blksize = BPS; + factor = 1; + } + + do { + // Create a new mapping. + + map = (struct DiskBVMap *) malloc( sizeof(*map) ); + if ( map ) + { + int error; + DPME *dpme_p = (DPME *)buffer; + UInt32 i, npart = UINT_MAX; + BVRef bvr; + + map->biosdev = biosdev; + map->bvr = NULL; + map->bvrcnt = 0; + map->next = gDiskBVMap; + gDiskBVMap = map; + + for (i=0; idpme_signature) != DPME_SIGNATURE) { + break; + } + + if (i==0) { + npart = OSSwapBigToHostInt32(dpme_p->dpme_map_entries); + } + /* + printf("name = %s, %s%s %d -> %d [%d -> %d] {%d}\n", + dpme.dpme_name, dpme.dpme_type, (dpme.dpme_flags & DPME_FLAGS_BOOTABLE) ? "(bootable)" : "", + dpme.dpme_pblock_start, dpme.dpme_pblocks, + dpme.dpme_lblock_start, dpme.dpme_lblocks, + dpme.dpme_boot_block); + */ + + if (strcmp(dpme_p->dpme_type, "Apple_HFS") == 0) { + bvr = newAPMBVRef(biosdev, + i, + OSSwapBigToHostInt32(dpme_p->dpme_pblock_start) * factor, + dpme_p, + HFSInitPartition, + HFSLoadFile, + HFSReadFile, + HFSGetDirEntry, + HFSGetFileBlock, + HFSGetUUID, + HFSGetDescription, + HFSFree, + 0, + kBIOSDevTypeHardDrive, 0); + bvr->next = map->bvr; + map->bvr = bvr; + map->bvrcnt++; + } + } + } + } while (0); + + free(buffer); + + if (countPtr) *countPtr = map ? map->bvrcnt : 0; + + return map ? map->bvr : NULL; +} + +//========================================================================== + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +/* + * Trying to figure out the filsystem type of a given partition. + */ +static int probeFileSystem(int biosdev, unsigned int blkoff) +{ + // detected filesystem type; + int result = -1; + int fatbits; + + // Allocating buffer for 4 sectors. + const void * probeBuffer = malloc(PROBEFS_SIZE); + if (probeBuffer == NULL) + goto exit; + + // Reading first 4 sectors of current partition + int error = readBytes(biosdev, blkoff, 0, PROBEFS_SIZE, (void *)probeBuffer); + if (error) + goto exit; + + if (HFSProbe(probeBuffer)) + result = FDISK_HFS; + else if (EX2Probe(probeBuffer)) + result = FDISK_LINUX; + else if (NTFSProbe(probeBuffer)) + result = FDISK_NTFS; + else if (fatbits=MSDOSProbe(probeBuffer)) + { + switch (fatbits) + { + case 32: + default: + result = FDISK_FAT32; + break; + case 16: + result = FDISK_DOS16B; + break; + case 12: + result = FDISK_DOS12; + break; + } + } + else + // Couldn't detect filesystem type + result = 0; + +exit: + if (probeBuffer != NULL) free((void *)probeBuffer); + return result; +} + +static bool isPartitionUsed(gpt_ent * partition) +{ + // + // Ask whether the given partition is used. + // + + return efi_guid_is_null((EFI_GUID const*)partition->ent_type) ? false : true; +} + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +static BVRef diskScanGPTBootVolumes( int biosdev, int * countPtr ) +{ + struct DiskBVMap * map = NULL; + void *buffer = malloc(BPS); + int error; + if ( error = readBytes( biosdev, /*secno*/0, 0, BPS, buffer ) != 0) { + verbose("Failed to read boot sector from BIOS device %02xh. Error=%d\n", biosdev, error); + goto scanErr; + } + struct REAL_disk_blk0 *fdiskMap = buffer; + if ( OSSwapLittleToHostInt16(fdiskMap->signature) != DISK_SIGNATURE ) + { + verbose("Failed to find boot signature on BIOS device %02xh\n", biosdev); + goto scanErr; + } + + int fdiskID = 0; + unsigned index; + for ( index = 0; index < FDISK_NPART; index++ ) + { + if ( fdiskMap->parts[index].systid ) + { + if ( fdiskMap->parts[index].systid == 0xEE ) + { + // Fail if two 0xEE partitions are present which + // means the FDISK code will wind up parsing it. + if ( fdiskID ) goto scanErr; + + fdiskID = index + 1; + } + } + } + + if ( fdiskID == 0 ) goto scanErr; + verbose("Attempting to read GPT\n"); + + if(readBytes(biosdev, 1, 0, BPS, buffer) != 0) + goto scanErr; + + gpt_hdr *headerMap = buffer; + + // Determine whether the partition header signature is present. + + if ( memcmp(headerMap->hdr_sig, GPT_HDR_SIG, strlen(GPT_HDR_SIG)) ) + { + goto scanErr; + } + + // Determine whether the partition header size is valid. + + UInt32 headerCheck = OSSwapLittleToHostInt32(headerMap->hdr_crc_self); + UInt32 headerSize = OSSwapLittleToHostInt32(headerMap->hdr_size); + + if ( headerSize < offsetof(gpt_hdr, padding) ) + { + goto scanErr; + } + + if ( headerSize > BPS ) + { + goto scanErr; + } + + // Determine whether the partition header checksum is valid. + + headerMap->hdr_crc_self = 0; + + if ( crc32(0, headerMap, headerSize) != headerCheck ) + { + goto scanErr; + } + + // Determine whether the partition entry size is valid. + + UInt64 gptBlock = 0; + UInt32 gptCheck = 0; + UInt32 gptCount = 0; + UInt32 gptID = 0; + gpt_ent * gptMap = 0; + UInt32 gptSize = 0; + + gptBlock = OSSwapLittleToHostInt64(headerMap->hdr_lba_table); + gptCheck = OSSwapLittleToHostInt32(headerMap->hdr_crc_table); + gptCount = OSSwapLittleToHostInt32(headerMap->hdr_entries); + gptSize = OSSwapLittleToHostInt32(headerMap->hdr_entsz); + + if ( gptSize < sizeof(gpt_ent) ) + { + goto scanErr; + } + + // Allocate a buffer large enough to hold one map, rounded to a media block. + free(buffer); + buffer = NULL; + + UInt32 bufferSize = IORound(gptCount * gptSize, BPS); + if(bufferSize == 0) + goto scanErr; + buffer = malloc(bufferSize); + + if(readBytes(biosdev, gptBlock, 0, bufferSize, buffer) != 0) + goto scanErr; + + verbose("Read GPT\n"); + + // Allocate a new map for this BIOS device and insert it into the chain + map = malloc(sizeof(*map)); + map->biosdev = biosdev; + map->bvr = NULL; + map->bvrcnt = 0; + map->next = gDiskBVMap; + gDiskBVMap = map; + + // fdisk like partition type id. + int fsType = 0; + + for(gptID = 1; gptID <= gptCount; ++gptID) + { + BVRef bvr = NULL; + unsigned int bvrFlags = 0; + + // size on disk can be larger than sizeof(gpt_ent) + gptMap = (gpt_ent *) ( buffer + ( (gptID - 1) * gptSize) ); + + // NOTE: EFI_GUID's are in LE and we know we're on an x86. + // The IOGUIDPartitionScheme.cpp code uses byte-based UUIDs, we don't. + + if(isPartitionUsed(gptMap)) + { + char stringuuid[100]; + efi_guid_unparse_upper((EFI_GUID*)gptMap->ent_type, stringuuid); + verbose("Reading GPT partition %d, type %s\n", gptID, stringuuid); + + // Getting fdisk like partition type. + fsType = probeFileSystem(biosdev, gptMap->ent_lba_start); + + if ( (efi_guid_compare(&GPT_BOOT_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) || + (efi_guid_compare(&GPT_HFS_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) ) + { + bvrFlags = (efi_guid_compare(&GPT_BOOT_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) ? kBVFlagBooter : 0; + bvr = newGPTBVRef(biosdev, + gptID, + gptMap->ent_lba_start, + gptMap, + HFSInitPartition, + HFSLoadFile, + HFSReadFile, + HFSGetDirEntry, + HFSGetFileBlock, + HFSGetUUID, + HFSGetDescription, + HFSFree, + 0, + kBIOSDevTypeHardDrive, bvrFlags); + } + + // zef - foreign OS support + if ( (efi_guid_compare(&GPT_BASICDATA_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) || + (efi_guid_compare(&GPT_BASICDATA2_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) ) + { + switch (fsType) + { + case FDISK_NTFS: + bvr = newGPTBVRef(biosdev, gptID, gptMap->ent_lba_start, gptMap, + 0, 0, 0, 0, 0, 0, NTFSGetDescription, + (BVFree)free, 0, kBIOSDevTypeHardDrive, 0); + break; + + default: + bvr = newGPTBVRef(biosdev, gptID, gptMap->ent_lba_start, gptMap, + 0, 0, 0, 0, 0, 0, 0, + (BVFree)free, 0, kBIOSDevTypeHardDrive, 0); + break; + } + + } + + // turbo - save our booter partition + // zef - only on original boot device + if ( (efi_guid_compare(&GPT_EFISYS_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) ) + { + switch (fsType) + { + case FDISK_HFS: + if (readBootSector( biosdev, gptMap->ent_lba_start, (void *)0x7e00 ) == 0) + { + bvr = newGPTBVRef(biosdev, gptID, gptMap->ent_lba_start, gptMap, + HFSInitPartition, + HFSLoadFile, + HFSReadFile, + HFSGetDirEntry, + HFSGetFileBlock, + HFSGetUUID, + HFSGetDescription, + HFSFree, + 0, kBIOSDevTypeHardDrive, kBVFlagEFISystem); + } + break; + + case FDISK_FAT32: + if (testFAT32EFIBootSector( biosdev, gptMap->ent_lba_start, (void *)0x7e00 ) == 0) + { + bvr = newGPTBVRef(biosdev, gptID, gptMap->ent_lba_start, gptMap, + MSDOSInitPartition, + MSDOSLoadFile, + MSDOSReadFile, + MSDOSGetDirEntry, + MSDOSGetFileBlock, + MSDOSGetUUID, + MSDOSGetDescription, + MSDOSFree, + 0, kBIOSDevTypeHardDrive, kBVFlagEFISystem); + } + break; + + if (biosdev == gBIOSDev) + gBIOSBootVolume = bvr; + } + } + + if (bvr) + { + // Fixup bvr with the fake fdisk partition type. + if (fsType > 0) bvr->part_type = fsType; + + bvr->next = map->bvr; + map->bvr = bvr; + ++map->bvrcnt; + } + + } + } + +scanErr: + free(buffer); + + if(map) + { + if(countPtr) *countPtr = map->bvrcnt; + return map->bvr; + } + else + { + if(countPtr) *countPtr = 0; + return NULL; + } +} + +//========================================================================== + +static void scanFSLevelBVRSettings(BVRef chain) +{ + BVRef bvr; + char dirSpec[512], fileSpec[512]; + char label[BVSTRLEN]; + int ret; + long flags, time; + int fh, fileSize, error; + + for (bvr = chain; bvr; bvr = bvr->next) + { + ret = -1; + error = 0; + + // + // Check for alternate volume label on boot helper partitions. + // + if (bvr->flags & kBVFlagBooter) + { + sprintf(dirSpec, "hd(%d,%d)/System/Library/CoreServices/", BIOS_DEV_UNIT(bvr), bvr->part_no); + strcpy(fileSpec, ".disk_label.contentDetails"); + ret = GetFileInfo(dirSpec, fileSpec, &flags, &time); + if (!ret) + { + fh = open(strcat(dirSpec, fileSpec), 0); + fileSize = file_size(fh); + if (fileSize > 0 && fileSize < BVSTRLEN) + { + if (read(fh, label, fileSize) != fileSize) + error = -1; + } + else + error = -1; + + close(fh); + + if (!error) + { + label[fileSize] = '\0'; + strcpy(bvr->altlabel, label); + } + } + } + + // + // Check for SystemVersion.plist or ServerVersion.plist + // to determine if a volume hosts an installed system. + // + if (bvr->flags & kBVFlagNativeBoot) + { + sprintf(dirSpec, "hd(%d,%d)/System/Library/CoreServices/", BIOS_DEV_UNIT(bvr), bvr->part_no); + strcpy(fileSpec, "SystemVersion.plist"); + ret = GetFileInfo(dirSpec, fileSpec, &flags, &time); + + if (ret == -1) + { + strcpy(fileSpec, "ServerVersion.plist"); + ret = GetFileInfo(dirSpec, fileSpec, &flags, &time); + } + + if (!ret) + bvr->flags |= kBVFlagSystemVolume; + } + + } +} + +void rescanBIOSDevice(int biosdev) +{ + struct DiskBVMap *oldMap = diskResetBootVolumes(biosdev); + CacheReset(); + diskFreeMap(oldMap); + oldMap = NULL; + scanBootVolumes(biosdev, 0); +} + +struct DiskBVMap* diskResetBootVolumes(int biosdev) +{ + struct DiskBVMap * map; + struct DiskBVMap *prevMap = NULL; + for ( map = gDiskBVMap; map; prevMap = map, map = map->next ) { + if ( biosdev == map->biosdev ) { + break; + } + } + if(map != NULL) + { + verbose("Resetting BIOS device %xh\n", biosdev); + // Reset the biosbuf cache + cache_valid = false; + if(map == gDiskBVMap) + gDiskBVMap = map->next; + else if(prevMap != NULL) + prevMap->next = map->next; + else + stop(""); + } + // Return the old map, either to be freed, or reinserted later + return map; +} + +// Frees a DiskBVMap and all of its BootVolume's +void diskFreeMap(struct DiskBVMap *map) +{ + if(map != NULL) + { + while(map->bvr != NULL) + { + BVRef bvr = map->bvr; + map->bvr = bvr->next; + (*bvr->bv_free)(bvr); + } + free(map); + } +} + +BVRef diskScanBootVolumes( int biosdev, int * countPtr ) +{ + struct DiskBVMap * map; + BVRef bvr; + int count = 0; + + // Find an existing mapping for this device. + + for ( map = gDiskBVMap; map; map = map->next ) { + if ( biosdev == map->biosdev ) { + count = map->bvrcnt; + break; + } + } + + if (map == NULL) { + bvr = diskScanGPTBootVolumes(biosdev, &count); + if (bvr == NULL) { + bvr = diskScanFDiskBootVolumes(biosdev, &count); + } + if (bvr == NULL) { + bvr = diskScanAPMBootVolumes(biosdev, &count); + } + if (bvr) + { + scanFSLevelBVRSettings(bvr); + } + } else { + bvr = map->bvr; + } + if (countPtr) *countPtr += count; + return bvr; +} + +BVRef getBVChainForBIOSDev(int biosdev) +{ + BVRef chain = NULL; + struct DiskBVMap * map = NULL; + + for (map = gDiskBVMap; map; map = map->next) + { + if (map->biosdev == biosdev) + { + chain = map->bvr; + break; + } + } + + return chain; +} + +BVRef newFilteredBVChain(int minBIOSDev, int maxBIOSDev, unsigned int allowFlags, unsigned int denyFlags, int *count) +{ + BVRef chain = NULL; + BVRef bvr = NULL; + BVRef newBVR = NULL; + BVRef prevBVR = NULL; + + struct DiskBVMap * map = NULL; + int bvCount = 0; + + const char *raw = 0; + char* val = 0; + int len; + + getValueForKey(kHidePartition, &raw, &len, &bootInfo->bootConfig); + if(raw) + { + val = XMLDecode(raw); + } + + /* + * Traverse gDISKBVmap to get references for + * individual bvr chains of each drive. + */ + for (map = gDiskBVMap; map; map = map->next) + { + for (bvr = map->bvr; bvr; bvr = bvr->next) + { + /* + * Save the last bvr. + */ + if (newBVR) prevBVR = newBVR; + + /* + * Allocate and copy the matched bvr entry into a new one. + */ + newBVR = (BVRef) malloc(sizeof(*newBVR)); + bcopy(bvr, newBVR, sizeof(*newBVR)); + + /* + * Adjust the new bvr's fields. + */ + newBVR->next = NULL; + newBVR->filtered = true; + + if ( (!allowFlags || newBVR->flags & allowFlags) + && (!denyFlags || !(newBVR->flags & denyFlags) ) + && (newBVR->biosdev >= minBIOSDev && newBVR->biosdev <= maxBIOSDev) + ) + newBVR->visible = true; + + /* Looking for "Hide Partition" entries in 'hd(x,y)|uuid|"label" hd(m,n)|uuid|"label"' format + * to be able to hide foreign partitions from the boot menu. + */ + if ( (newBVR->flags & kBVFlagForeignBoot) ) + { + char *start, *next = val; + long len = 0; + do + { + start = strbreak(next, &next, &len); + if(len && matchVolumeToString(newBVR, start, len) ) + newBVR->visible = false; + } + while ( next && *next ); + } + + /* + * Use the first bvr entry as the starting chain pointer. + */ + if (!chain) + chain = newBVR; + + /* + * Update the previous bvr's link pointer to use the new memory area. + */ + if (prevBVR) + prevBVR->next = newBVR; + + if (newBVR->visible) + bvCount++; + } + } + +#if DEBUG + for (bvr = chain; bvr; bvr = bvr->next) + { + printf(" bvr: %d, dev: %d, part: %d, flags: %d, vis: %d\n", bvr, bvr->biosdev, bvr->part_no, bvr->flags, bvr->visible); + } + printf("count: %d\n", bvCount); + getc(); +#endif + + *count = bvCount; + + free(val); + return chain; +} + +int freeFilteredBVChain(const BVRef chain) +{ + int ret = 1; + BVRef bvr = chain; + BVRef nextBVR = NULL; + + while (bvr) + { + nextBVR = bvr->next; + + if (bvr->filtered) + { + free(bvr); + } + else + { + ret = 0; + break; + } + + bvr = nextBVR; + } + + return ret; +} + +//========================================================================== + +static const struct NamedValue fdiskTypes[] = +{ + { FDISK_NTFS, "Windows NTFS" }, + { FDISK_DOS12, "Windows FAT12" }, + { FDISK_DOS16B, "Windows FAT16" }, + { FDISK_DOS16S, "Windows FAT16" }, + { FDISK_DOS16SLBA, "Windows FAT16" }, + { FDISK_SMALLFAT32, "Windows FAT32" }, + { FDISK_FAT32, "Windows FAT32" }, + { FDISK_LINUX, "Linux" }, + { FDISK_UFS, "Apple UFS" }, + { FDISK_HFS, "Apple HFS" }, + { FDISK_BOOTER, "Apple Boot/UFS" }, + { 0xCD, "CD-ROM" }, + { 0x00, 0 } /* must be last */ +}; + +//========================================================================== + +bool matchVolumeToString( BVRef bvr, const char* match, long matchLen) +{ + char testStr[128]; + + if ( !bvr || !match || !*match) + return 0; + + if ( bvr->biosdev < 0x80 || bvr->biosdev >= 0x100 ) + return 0; + + // Try to match hd(x,y) first. + sprintf(testStr, "hd(%d,%d)", BIOS_DEV_UNIT(bvr), bvr->part_no); + if ( matchLen ? !strncmp(match, testStr, matchLen) : !strcmp(match, testStr) ) + return true; + + // Try to match volume UUID. + if ( bvr->fs_getuuid && bvr->fs_getuuid(bvr, testStr) == 0) + { + if( matchLen ? !strncmp(match, testStr, matchLen) : !strcmp(match, testStr) ) + return true; + } + + // Try to match volume label (always quoted). + if ( bvr->description ) + { + bvr->description(bvr, testStr, sizeof(testStr)-1); + if( matchLen ? !strncmp(match, testStr, matchLen) : !strcmp(match, testStr) ) + return true; + } + + return false; +} + +/* If Rename Partition has defined an alias, then extract it for description purpose + * The format for the rename string is the following: + * hd(x,y)|uuid|"label" "alias";hd(m,n)|uuid|"label" etc; ... + */ + +bool getVolumeLabelAlias(BVRef bvr, char* str, long strMaxLen) +{ + char *aliasList, *entryStart, *entryNext; + + if ( !str || strMaxLen <= 0) + return false; + + aliasList = XMLDecode(getStringForKey(kRenamePartition, &bootInfo->bootConfig)); + if ( !aliasList ) + return false; + + for ( entryStart = entryNext = aliasList; + entryNext && *entryNext; + entryStart = entryNext ) + { + char *volStart, *volEnd, *aliasStart; + long volLen, aliasLen; + + // Delimit current entry + entryNext = strchr(entryStart, ';'); + if ( entryNext ) + { + *entryNext = '\0'; + entryNext++; + } + + volStart = strbreak(entryStart, &volEnd, &volLen); + if(!volLen) + continue; + + aliasStart = strbreak(volEnd, 0, &aliasLen); + if(!aliasLen) + continue; + + if ( matchVolumeToString(bvr, volStart, volLen) ) + { + strncat(str, aliasStart, min(strMaxLen, aliasLen)); + free(aliasList); + + return true; + } + } + + free(aliasList); + return false; +} + +void getBootVolumeDescription( BVRef bvr, char * str, long strMaxLen, bool useDeviceDescription ) +{ + unsigned char type; + char *p = str; + + if(!bvr || !p || strMaxLen <= 0) + return; + + type = (unsigned char) bvr->part_type; + + if (useDeviceDescription) + { + int len = getDeviceDescription(bvr, str); + if(len >= strMaxLen) + return; + + strcpy(str + len, " "); + len++; + strMaxLen -= len; + p += len; + } + + /* See if a partition rename is preferred */ + if(getVolumeLabelAlias(bvr, p, strMaxLen)) { + strncpy(bvr->label, p, strMaxLen); + return; // we're done here no need to seek for real name + } + + // + // Get the volume label using filesystem specific functions + // or use the alternate volume label if available. + // + if (*bvr->altlabel != '\0') + strncpy(p, bvr->altlabel, strMaxLen); + else if (bvr->description) + bvr->description(bvr, p, strMaxLen); + + if (*p == '\0') { + const char * name = getNameForValue( fdiskTypes, type ); + if (name == NULL) { + name = bvr->type_name; + } + if (name == NULL) { + sprintf(p, "TYPE %02x", type); + } else { + strncpy(p, name, strMaxLen); + } + } + + // Set the devices label + sprintf(bvr->label, p); +} + +//========================================================================== +int readBootSector( int biosdev, unsigned int secno, void * buffer ) +{ + struct disk_blk0 * bootSector = (struct disk_blk0 *) buffer; + int error; + + if ( bootSector == NULL ) + { + if ( gBootSector == NULL ) + { + gBootSector = (struct disk_blk0 *) malloc(sizeof(*gBootSector)); + if ( gBootSector == NULL ) return -1; + } + bootSector = gBootSector; + } + + error = readBytes( biosdev, secno, 0, BPS, bootSector ); + if ( error || bootSector->signature != DISK_SIGNATURE ) + return -1; + + return 0; +} + +/* + * Format of boot1f32 block. + */ + +#define BOOT1F32_MAGIC "BOOT " +#define BOOT1F32_MAGICLEN 11 + +struct disk_boot1f32_blk { + unsigned char init[3]; + unsigned char fsheader[87]; + unsigned char magic[BOOT1F32_MAGICLEN]; + unsigned char bootcode[409]; + unsigned short signature; +}; + +int testFAT32EFIBootSector( int biosdev, unsigned int secno, void * buffer ) +{ + struct disk_boot1f32_blk * bootSector = (struct disk_boot1f32_blk *) buffer; + int error; + + if ( bootSector == NULL ) + { + if ( gBootSector == NULL ) + { + gBootSector = (struct disk_blk0 *) malloc(sizeof(*gBootSector)); + if ( gBootSector == NULL ) return -1; + } + bootSector = (struct disk_boot1f32_blk *) gBootSector; + } + + error = readBytes( biosdev, secno, 0, BPS, bootSector ); + if ( error || bootSector->signature != DISK_SIGNATURE + || strncmp((const char *)bootSector->magic, BOOT1F32_MAGIC, BOOT1F32_MAGICLEN) ) + return -1; + + return 0; +} + +//========================================================================== +// Handle seek request from filesystem modules. + +void diskSeek( BVRef bvr, long long position ) +{ + bvr->fs_boff = position / BPS; + bvr->fs_byteoff = position % BPS; +} + +//========================================================================== +// Handle read request from filesystem modules. + +int diskRead( BVRef bvr, long addr, long length ) +{ + return readBytes( bvr->biosdev, + bvr->fs_boff + bvr->part_boff, + bvr->fs_byteoff, + length, + (void *) addr ); +} + +int rawDiskRead( BVRef bvr, unsigned int secno, void *buffer, unsigned int len ) +{ + int secs; + unsigned char *cbuf = (unsigned char *)buffer; + unsigned int copy_len; + int rc; + + if ((len & (BPS-1)) != 0) { + error("raw disk read not sector aligned"); + return -1; + } + secno += bvr->part_boff; + + cache_valid = false; + + while (len > 0) { + secs = len / BPS; + if (secs > N_CACHE_SECS) secs = N_CACHE_SECS; + copy_len = secs * BPS; + + //printf("rdr: ebiosread(%d, %d, %d)\n", bvr->biosdev, secno, secs); + if ((rc = ebiosread(bvr->biosdev, secno, secs)) != 0) { + /* Ignore corrected ECC errors */ + if (rc != ECC_CORRECTED_ERR) { + error(" EBIOS read error: %s\n", bios_error(rc), rc); + error(" Block %d Sectors %d\n", secno, secs); + return rc; + } + } + bcopy( trackbuf, cbuf, copy_len ); + len -= copy_len; + cbuf += copy_len; + secno += secs; + spinActivityIndicator(secs); + } + + return 0; +} + +int rawDiskWrite( BVRef bvr, unsigned int secno, void *buffer, unsigned int len ) +{ + int secs; + unsigned char *cbuf = (unsigned char *)buffer; + unsigned int copy_len; + int rc; + + if ((len & (BPS-1)) != 0) { + error("raw disk write not sector aligned"); + return -1; + } + secno += bvr->part_boff; + + cache_valid = false; + + while (len > 0) { + secs = len / BPS; + if (secs > N_CACHE_SECS) secs = N_CACHE_SECS; + copy_len = secs * BPS; + + bcopy( cbuf, trackbuf, copy_len ); + //printf("rdr: ebioswrite(%d, %d, %d)\n", bvr->biosdev, secno, secs); + if ((rc = ebioswrite(bvr->biosdev, secno, secs)) != 0) { + error(" EBIOS write error: %s\n", bios_error(rc), rc); + error(" Block %d Sectors %d\n", secno, secs); + return rc; + } + len -= copy_len; + cbuf += copy_len; + secno += secs; + spinActivityIndicator(secs); + } + + return 0; +} + + +int diskIsCDROM(BVRef bvr) +{ + struct driveInfo di; + + if (getDriveInfo(bvr->biosdev, &di) == 0 && di.no_emulation) { + return 1; + } + return 0; +} + +int biosDevIsCDROM(int biosdev) +{ + struct driveInfo di; + + if (getDriveInfo(biosdev, &di) == 0 && di.no_emulation) + { + return 1; + } + return 0; +} Index: branches/Chimera/i386/libsaio/.svn/text-base/device_inject.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/device_inject.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/device_inject.c.svn-base (revision 850) @@ -0,0 +1,360 @@ +/* + * Copyright 2009 Jasmin Fazlic All rights reserved. + */ +/* + * Cleaned and merged by iNDi + */ + +#include "libsaio.h" +#include "boot.h" +#include "bootstruct.h" +#include "pci.h" +#include "pci_root.h" +#include "device_inject.h" +#include "convert.h" + +#ifndef DEBUG_INJECT +#define DEBUG_INJECT 0 +#endif + +#if DEBUG_INJECT +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif + +uint32_t devices_number = 1; +uint32_t builtin_set = 0; +struct DevPropString *string = 0; +uint8_t *stringdata = 0; +uint32_t stringlength = 0; + +char *efi_inject_get_devprop_string(uint32_t *len) +{ + if(string) { + *len = string->length; + return devprop_generate_string(string); + } + verbose("efi_inject_get_devprop_string NULL trying stringdata\n"); + return NULL; +} + +void setupDeviceProperties(Node *node) +{ + const char *val; + uint8_t *binStr; + int cnt, cnt2; + + static char DEVICE_PROPERTIES_PROP[] = "device-properties"; + + /* Generate devprop string. + */ + uint32_t strlength; + char *string = efi_inject_get_devprop_string(&strlength); + + /* Use the static "device-properties" boot config key contents if available, + * otheriwse use the generated one. + */ + if (!getValueForKey(kDeviceProperties, &val, &cnt, &bootInfo->bootConfig) && string) + { + val = (const char*)string; + cnt = strlength * 2; + } + + if (cnt > 1) + { + binStr = convertHexStr2Binary(val, &cnt2); + if (cnt2 > 0) DT__AddProperty(node, DEVICE_PROPERTIES_PROP, cnt2, binStr); + } +} + +struct DevPropString *devprop_create_string(void) +{ + string = (struct DevPropString*)malloc(sizeof(struct DevPropString)); + + if(string == NULL) + return NULL; + + memset(string, 0, sizeof(struct DevPropString)); + string->length = 12; + string->WHAT2 = 0x01000000; + return string; +} + +struct DevPropDevice *devprop_add_device(struct DevPropString *string, char *path) +{ + struct DevPropDevice *device; + const char pciroot_string[] = "PciRoot(0x"; + const char pci_device_string[] = "Pci(0x"; + + if (string == NULL || path == NULL) { + return NULL; + } + device = malloc(sizeof(struct DevPropDevice)); + + if (strncmp(path, pciroot_string, strlen(pciroot_string))) { + printf("ERROR parsing device path\n"); + return NULL; + } + + memset(device, 0, sizeof(struct DevPropDevice)); + device->acpi_dev_path._UID = getPciRootUID(); + + int numpaths = 0; + int x, curr = 0; + char buff[] = "00"; + + for (x = 0; x < strlen(path); x++) { + if (!strncmp(&path[x], pci_device_string, strlen(pci_device_string))) { + x+=strlen(pci_device_string); + curr=x; + while(path[++x] != ','); + if(x-curr == 2) + sprintf(buff, "%c%c", path[curr], path[curr+1]); + else if(x-curr == 1) + sprintf(buff, "%c", path[curr]); + else + { + printf("ERROR parsing device path\n"); + numpaths = 0; + break; + } + device->pci_dev_path[numpaths].device = ascii_hex_to_int(buff); + + x += 3; // 0x + curr = x; + while(path[++x] != ')'); + if(x-curr == 2) + sprintf(buff, "%c%c", path[curr], path[curr+1]); + else if(x-curr == 1) + sprintf(buff, "%c", path[curr]); + else + { + printf("ERROR parsing device path\n"); + numpaths = 0; + break; + } + device->pci_dev_path[numpaths].function = ascii_hex_to_int(buff); // TODO: find dev from char *path + + numpaths++; + } + } + + if(!numpaths) + return NULL; + + device->numentries = 0x00; + + device->acpi_dev_path.length = 0x0c; + device->acpi_dev_path.type = 0x02; + device->acpi_dev_path.subtype = 0x01; + device->acpi_dev_path._HID = 0xd041030a; + + device->num_pci_devpaths = numpaths; + device->length = 24 + (6*numpaths); + + int i; + + for(i = 0; i < numpaths; i++) + { + device->pci_dev_path[i].length = 0x06; + device->pci_dev_path[i].type = 0x01; + device->pci_dev_path[i].subtype = 0x01; + } + + device->path_end.length = 0x04; + device->path_end.type = 0x7f; + device->path_end.subtype = 0xff; + + device->string = string; + device->data = NULL; + string->length += device->length; + + if(!string->entries) + if((string->entries = (struct DevPropDevice**)malloc(sizeof(device)))== NULL) + return 0; + + string->entries[string->numentries++] = (struct DevPropDevice*)malloc(sizeof(device)); + string->entries[string->numentries-1] = device; + + return device; +} + +int devprop_add_value(struct DevPropDevice *device, char *nm, uint8_t *vl, uint32_t len) +{ + + if(!nm || !vl || !len) + return 0; + + uint32_t length = ((strlen(nm) * 2) + len + (2 * sizeof(uint32_t)) + 2); + uint8_t *data = (uint8_t*)malloc(length); + { + if(!data) + return 0; + + memset(data, 0, length); + uint32_t off= 0; + data[off+1] = ((strlen(nm) * 2) + 6) >> 8; + data[off] = ((strlen(nm) * 2) + 6) & 0x00FF; + + off += 4; + uint32_t i=0, l = strlen(nm); + for(i = 0 ; i < l ; i++, off += 2) + { + data[off] = *nm++; + } + + off += 2; + l = len; + uint32_t *datalength = (uint32_t*)&data[off]; + *datalength = l + 4; + off += 4; + for(i = 0 ; i < l ; i++, off++) + { + data[off] = *vl++; + } + } + + uint32_t offset = device->length - (24 + (6 * device->num_pci_devpaths)); + + uint8_t *newdata = (uint8_t*)malloc((length + offset)); + if(!newdata) + return 0; + if(device->data) + if(offset > 1) + memcpy(newdata, device->data, offset); + + memcpy(newdata + offset, data, length); + + device->length += length; + device->string->length += length; + device->numentries++; + + if(!device->data) + device->data = (uint8_t*)malloc(sizeof(uint8_t)); + else + free(device->data); + + free(data); + device->data = newdata; + + return 1; +} + +char *devprop_generate_string(struct DevPropString *string) +{ + char *buffer = (char*)malloc(string->length * 2); + char *ptr = buffer; + + if(!buffer) + return NULL; + + sprintf(buffer, "%08x%08x%04x%04x", dp_swap32(string->length), string->WHAT2, + dp_swap16(string->numentries), string->WHAT3); + buffer += 24; + int i = 0, x = 0; + + while(i < string->numentries) + { + sprintf(buffer, "%08x%04x%04x", dp_swap32(string->entries[i]->length), + dp_swap16(string->entries[i]->numentries), string->entries[i]->WHAT2); + + buffer += 16; + sprintf(buffer, "%02x%02x%04x%08x%08x", string->entries[i]->acpi_dev_path.type, + string->entries[i]->acpi_dev_path.subtype, + dp_swap16(string->entries[i]->acpi_dev_path.length), + string->entries[i]->acpi_dev_path._HID, + dp_swap32(string->entries[i]->acpi_dev_path._UID)); + + buffer += 24; + for(x=0;x < string->entries[i]->num_pci_devpaths; x++) + { + sprintf(buffer, "%02x%02x%04x%02x%02x", string->entries[i]->pci_dev_path[x].type, + string->entries[i]->pci_dev_path[x].subtype, + dp_swap16(string->entries[i]->pci_dev_path[x].length), + string->entries[i]->pci_dev_path[x].function, + string->entries[i]->pci_dev_path[x].device); + buffer += 12; + } + + sprintf(buffer, "%02x%02x%04x", string->entries[i]->path_end.type, + string->entries[i]->path_end.subtype, + dp_swap16(string->entries[i]->path_end.length)); + + buffer += 8; + uint8_t *dataptr = string->entries[i]->data; + for(x = 0; x < (string->entries[i]->length) - (24 + (6 * string->entries[i]->num_pci_devpaths)) ; x++) + { + sprintf(buffer, "%02x", *dataptr++); + buffer += 2; + } + i++; + } + return ptr; +} + +void devprop_free_string(struct DevPropString *string) +{ + if(!string) + return; + + int i; + for(i = 0; i < string->numentries; i++) + { + if(string->entries[i]) + { + if(string->entries[i]->data) + { + free(string->entries[i]->data); + string->entries[i]->data = NULL; + } + free(string->entries[i]); + string->entries[i] = NULL; + } + } + + free(string); + string = NULL; +} + +/* a fine place for this code */ + +int devprop_add_network_template(struct DevPropDevice *device, uint16_t vendor_id) +{ + if(!device) + return 0; + uint8_t builtin = 0x0; + if((vendor_id != 0x168c) && (builtin_set == 0)) + { + builtin_set = 1; + builtin = 0x01; + } + if(!devprop_add_value(device, "built-in", (uint8_t*)&builtin, 1)) + return 0; + devices_number++; + return 1; +} + +void set_eth_builtin(pci_dt_t *eth_dev) +{ + char *devicepath = get_pci_dev_path(eth_dev); + struct DevPropDevice *device = (struct DevPropDevice*)malloc(sizeof(struct DevPropDevice)); + + verbose("LAN Controller [%04x:%04x] :: %s\n", eth_dev->vendor_id, eth_dev->device_id, devicepath); + + if (!string) + string = devprop_create_string(); + + device = devprop_add_device(string, devicepath); + if(device) + { + verbose("Setting up lan keys\n"); + devprop_add_network_template(device, eth_dev->vendor_id); + stringdata = (uint8_t*)malloc(sizeof(uint8_t) * string->length); + if(stringdata) + { + memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length); + stringlength = string->length; + } + } +} Index: branches/Chimera/i386/libsaio/.svn/text-base/Makefile.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/Makefile.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/Makefile.svn-base (revision 850) @@ -0,0 +1,96 @@ + +DIR = libsaio +include ../MakePaths.dir + +UTILDIR = ../util +LIBSADIR = ../libsa +BOOT2DIR = ../boot2 +INSTALLDIR = $(DSTROOT)/System/Library/Frameworks/System.framework/Versions/B/PrivateHeaders/standalone +#SYMROOT= + +OPTIM = -Os -Oz +DEBUG = -DNOTHING +#DEBUG = -DDEBUG_CPU=1 -DDEBUG_MEM=1 -DDEBUG_SPD=1 -DDEBUG_PCI=1 -DDEBUG_SMBIOS=1 +CFLAGS = $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \ + -D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \ + -DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \ + -fno-builtin -static $(OMIT_FRAME_POINTER_CFLAG) \ + -mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \ + -march=pentium4 -msse2 -mfpmath=sse -msoft-float + +DEFINES= +CONFIG = hd +INC = -I. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(BOOT2DIR) +ifneq "" "$(wildcard /bin/mkdirs)" + MKDIRS = /bin/mkdirs +else + MKDIRS = /bin/mkdir -p +endif +AS = as +LD = ld +# LIBS= -lc_static +LIBS= + +VPATH = $(OBJROOT):$(SYMROOT) + +SAIO_OBJS = table.o asm.o bios.o biosfn.o \ + disk.o sys.o cache.o bootstruct.o \ + stringTable.o load.o pci.o allocate.o misc.o \ + ufs.o ufs_byteorder.o \ + vbe.o nbp.o hfs.o hfs_compare.o \ + xml.o ntfs.o msdos.o md5c.o device_tree.o \ + cpu.o platform.o acpi_patcher.o \ + smbios.o smbios_getters.o smbios_decode.o \ + fake_efi.o ext2fs.o \ + hpet.o dram_controllers.o spd.o usb.o pci_setup.o \ + device_inject.o nvidia.o ati.o pci_root.o \ + convert.o aml_generator.o + + +SAIO_EXTERN_OBJS = console.o + +SFILES = +CFILES = +HFILES = +EXPORTED_HFILES = +INSTALLED_HFILES = +OTHERFILES = Makefile +ALLSRC = $(SFILES) $(CFILES) \ + $(HFILES) $(OTHERFILES) +LIBS = libsaio.a +DIRS_NEEDED = $(OBJROOT) $(SYMROOT) +#GENFILES = $(SYMROOT)/saio_internal.h \ +# $(SYMROOT)/saio_external.h \ +# $(SYMROOT)/saio_defs.h \ +# $(SYMROOT)/saio_table.c + +#SIG = $(SYMROOT)/sig + +all embedtheme: $(DIRS_NEEDED) libsaio.h $(LIBS) + +#libsaio_static.a: $(SAIO_OBJS) +# rm -f $(SYMROOT)/$@ +# ar q $(SYMROOT)/$@ $(SAIO_OBJS) +# ranlib $(SYMROOT)/$@ + +libsaio.a: $(SAIO_EXTERN_OBJS) $(SAIO_OBJS) + @echo "\t[RM] $(SYMROOT)/$(@F)" + @rm -f $(SYMROOT)/$(@F) + @echo "\t[AR] $@" + @ar q $(SYMROOT)/$(@F) $^ &> /dev/null + @echo "\t[RANLIB] $@" + @ranlib $(SYMROOT)/$(@F) + +#saio_internal.h: saio_external.h +#saio_table.c: saio_external.h +#saio_defs.h: saio_external.h +#saio_external.h: saio.def +# $(SIG) -d $(SYMROOT) -n saio saio.def + +#installhdrs:: $(INSTALLDIR) +# cp $(INSTALLED_HFILES) $(INSTALLDIR) + +include ../MakeInc.dir + +# dependencies +-include $(OBJROOT)/Makedep Index: branches/Chimera/i386/libsaio/.svn/text-base/xml.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/xml.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/xml.h.svn-base (revision 850) @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#ifndef __LIBSAIO_XML_H +#define __LIBSAIO_XML_H + +enum xmltype { + kTagTypeNone = 0, + kTagTypeDict, + kTagTypeKey, + kTagTypeString, + kTagTypeInteger, + kTagTypeData, + kTagTypeDate, + kTagTypeFalse, + kTagTypeTrue, + kTagTypeArray +}; + + +struct string_ref +{ + char* string; + int id; + struct string_ref* next; +}; +typedef struct string_ref string_ref; + +extern string_ref* ref_strings; + +#define kXMLTagPList "plist " +#define kXMLTagDict "dict" +#define kXMLTagKey "key" +#define kXMLTagString "string" +#define kXMLTagInteger "integer" +#define kXMLTagData "data" +#define kXMLTagDate "date" +#define kXMLTagFalse "false/" +#define kXMLTagTrue "true/" +#define kXMLTagArray "array" + +#define kXMLStringID "ID=" +#define kXMLStringIDRef "IDREF=" + + +#define kPropCFBundleIdentifier ("CFBundleIdentifier") +#define kPropCFBundleExecutable ("CFBundleExecutable") +#define kPropOSBundleRequired ("OSBundleRequired") +#define kPropOSBundleLibraries ("OSBundleLibraries") +#define kPropIOKitPersonalities ("IOKitPersonalities") +#define kPropIONameMatch ("IONameMatch") + +/* +struct Tag { + long type; + char *string; + struct Tag *tag; + struct Tag *tagNext; +}; +typedef struct Tag Tag, *TagPtr; + */ + +extern long gImageFirstBootXAddr; +extern long gImageLastKernelAddr; + +TagPtr XMLGetProperty( TagPtr dict, const char * key ); +TagPtr XMLGetElement( TagPtr dict, int id ); +int XMLTagCount( TagPtr dict ); + +bool XMLIsType(TagPtr dict, enum xmltype type); + +bool XMLCastBoolean( TagPtr dict ); +char* XMLCastString( TagPtr dict ); +long XMLCastStringOffset(TagPtr dict); +int XMLCastInteger ( TagPtr dict ); +TagPtr XMLCastDict ( TagPtr dict ); +TagPtr XMLCastArray( TagPtr dict ); + +long XMLParseNextTag(char *buffer, TagPtr *tag); +void XMLFreeTag(TagPtr tag); +char* XMLDecode(const char *in); +//========================================================================== +// XMLParseFile +// Expects to see one dictionary in the XML file. +// Puts the first dictionary it finds in the +// tag pointer and returns 0, or returns -1 if not found. +// +long XMLParseFile( char * buffer, TagPtr * dict ); + +#endif /* __LIBSAIO_XML_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/ntfs_private.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/ntfs_private.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/ntfs_private.h.svn-base (revision 850) @@ -0,0 +1,399 @@ +/* + * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved. + * + * This file contains Original Code and/or Modifications of Original Code + * as defined in and that are subject to the Apple Public Source License + * Version 2.0 (the 'License'). You may not use this file except in + * compliance with the License. Please obtain a copy of the License at + * http://www.opensource.apple.com/apsl/ and read it before using this + * file. + * + * The Original Code and all software distributed under the License are + * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. + * Please see the License for the specific language governing rights and + * limitations under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* $NetBSD: ntfs.h,v 1.9 1999/10/31 19:45:26 jdolecek Exp $ */ + +/*- + * Copyright (c) 1998, 1999 Semen Ustimenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/fs/ntfs/ntfs.h,v 1.14 2001/11/27 00:18:33 jhb Exp $ + */ + +/*#define NTFS_DEBUG 1*/ + +#ifdef APPLE +/* We're using FreeBSD style byte order macros in the source. */ +#include +#define le16toh(x) OSSwapLittleToHostInt16(x) +#define le32toh(x) OSSwapLittleToHostInt32(x) +#define le64toh(x) OSSwapLittleToHostInt64(x) + +/* FreeBSD mutexes correspond to Darwin's simple locks */ +#define mtx_lock(lock) simple_lock(lock) +#define mtx_unlock(lock) simple_unlock(lock) +#define mtx_destroy(lock) /* Nothing. */ + +#define lockdestroy(lock) /* Nothing. */ + +#endif + +typedef u_int64_t cn_t; +typedef u_int16_t wchar; + +#pragma pack(1) +#define BBSIZE 1024 +#define BBOFF ((off_t)(0)) +#define BBLOCK ((daddr_t)(0)) +#define NTFS_MFTINO 0 +#define NTFS_VOLUMEINO 3 +#define NTFS_ATTRDEFINO 4 +#define NTFS_ROOTINO 5 +#define NTFS_BITMAPINO 6 +#define NTFS_BOOTINO 7 +#define NTFS_BADCLUSINO 8 +#define NTFS_UPCASEINO 10 +#define NTFS_MAXFILENAME 255 + +struct fixuphdr { + u_int32_t fh_magic; + u_int16_t fh_foff; + u_int16_t fh_fnum; +}; + +#define NTFS_AF_INRUN 0x00000001 +struct attrhdr { + u_int32_t a_type; + u_int32_t reclen; + u_int8_t a_flag; + u_int8_t a_namelen; + u_int8_t a_nameoff; + u_int8_t reserved1; + u_int8_t a_compression; + u_int8_t reserved2; + u_int16_t a_index; +}; +#define NTFS_A_STD 0x10 +#define NTFS_A_ATTRLIST 0x20 +#define NTFS_A_NAME 0x30 +#define NTFS_A_VOLUMENAME 0x60 +#define NTFS_A_DATA 0x80 +#define NTFS_A_INDXROOT 0x90 +#define NTFS_A_INDX 0xA0 +#define NTFS_A_INDXBITMAP 0xB0 + +#define NTFS_MAXATTRNAME 255 +struct attr { + struct attrhdr a_hdr; + union { + struct { + u_int16_t a_datalen; + u_int16_t reserved1; + u_int16_t a_dataoff; + u_int16_t a_indexed; + } a_S_r; + struct { + cn_t a_vcnstart; + cn_t a_vcnend; + u_int16_t a_dataoff; + u_int16_t a_compressalg; + u_int32_t reserved1; + u_int64_t a_allocated; + u_int64_t a_datalen; + u_int64_t a_initialized; + } a_S_nr; + } a_S; +}; +#define a_r a_S.a_S_r +#define a_nr a_S.a_S_nr + +typedef struct { + u_int64_t t_create; + u_int64_t t_write; + u_int64_t t_mftwrite; + u_int64_t t_access; +} ntfs_times_t; + +#define NTFS_FFLAG_RDONLY 0x01LL +#define NTFS_FFLAG_HIDDEN 0x02LL +#define NTFS_FFLAG_SYSTEM 0x04LL +#define NTFS_FFLAG_ARCHIVE 0x20LL +#define NTFS_FFLAG_COMPRESSED 0x0800LL +#define NTFS_FFLAG_DIR 0x10000000LL + +struct attr_name { + u_int32_t n_pnumber; /* Parent ntnode */ + u_int32_t reserved; + ntfs_times_t n_times; + u_int64_t n_size; + u_int64_t n_attrsz; + u_int64_t n_flag; + u_int8_t n_namelen; + u_int8_t n_nametype; + u_int16_t n_name[1]; +}; + +#define NTFS_IRFLAG_INDXALLOC 0x00000001 +struct attr_indexroot { + u_int32_t ir_unkn1; /* attribute type (0x30 for $FILE_NAME) */ + u_int32_t ir_unkn2; /* collation rule (0x01 for file names) */ + u_int32_t ir_size; /* size of index allocation entry */ + u_int32_t ir_unkn3; /* clusters per index record, and 3 bytes padding */ + u_int32_t ir_unkn4; /* (offset to first index entry?) always 0x10 */ + u_int32_t ir_datalen; /* (total size of index enties?) sizeof something */ + u_int32_t ir_allocated; /* (allocated size of index entries?) */ + u_int8_t ir_flag; /* 1=index allocation needed (large index) */ + u_int8_t ir_pad1; /* padding */ + u_int16_t ir_pad2; /* padding */ +}; + +struct attr_attrlist { + u_int32_t al_type; /* Attribute type */ + u_int16_t reclen; /* length of this entry */ + u_int8_t al_namelen; /* Attribute name len */ + u_int8_t al_nameoff; /* Name offset from entry start */ + u_int64_t al_vcnstart; /* VCN number */ + u_int32_t al_inumber; /* Parent ntnode */ + u_int32_t reserved; + u_int16_t al_index; /* Attribute index in MFT record */ + u_int16_t al_name[1]; /* Name */ +}; + +#define NTFS_INDXMAGIC (u_int32_t)(0x58444E49) +struct attr_indexalloc { + struct fixuphdr ia_fixup; + u_int64_t unknown1; + cn_t ia_bufcn; + u_int16_t ia_hdrsize; + u_int16_t unknown2; + u_int32_t ia_inuse; + u_int32_t ia_allocated; +}; + +#define NTFS_IEFLAG_SUBNODE 0x00000001 +#define NTFS_IEFLAG_LAST 0x00000002 + +struct attr_indexentry { + u_int32_t ie_number; + u_int32_t unknown1; + u_int16_t reclen; + u_int16_t ie_size; + u_int32_t ie_flag;/* 1 - has subnodes, 2 - last */ + u_int32_t ie_fpnumber; + u_int32_t unknown2; + ntfs_times_t ie_ftimes; + u_int64_t ie_fallocated; + u_int64_t ie_fsize; + u_int32_t ie_fflag; + u_int32_t unknown3; /* used by reparse points and external attributes? */ + u_int8_t ie_fnamelen; + u_int8_t ie_fnametype; + wchar ie_fname[NTFS_MAXFILENAME]; + /* cn_t ie_bufcn; buffer with subnodes */ +}; + +#define NTFS_FILEMAGIC (u_int32_t)(0x454C4946) +#define NTFS_FRFLAG_DIR 0x0002 +struct filerec { + struct fixuphdr fr_fixup; + u_int8_t reserved[8]; + u_int16_t fr_seqnum; /* Sequence number */ + u_int16_t fr_nlink; + u_int16_t fr_attroff; /* offset to attributes */ + u_int16_t fr_flags; /* 1-nonresident attr, 2-directory */ + u_int32_t fr_size;/* hdr + attributes */ + u_int32_t fr_allocated; /* allocated length of record */ + u_int64_t fr_mainrec; /* main record */ + u_int16_t fr_attrnum; /* maximum attr number + 1 ??? */ +}; + +#define NTFS_ATTRNAME_MAXLEN 0x40 +#define NTFS_ADFLAG_NONRES 0x0080 /* Attrib can be non resident */ +#define NTFS_ADFLAG_INDEX 0x0002 /* Attrib can be indexed */ +struct attrdef { + wchar ad_name[NTFS_ATTRNAME_MAXLEN]; + u_int32_t ad_type; + u_int32_t reserved1[2]; + u_int32_t ad_flag; + u_int64_t ad_minlen; + u_int64_t ad_maxlen; /* -1 for nonlimited */ +}; + +struct ntvattrdef { + char ad_name[0x40]; + int ad_namelen; + u_int32_t ad_type; +}; + +#define NTFS_BBID "NTFS " +#define NTFS_BBIDLEN 8 +struct bootfile { + u_int8_t reserved1[3]; /* asm jmp near ... */ + u_int8_t bf_sysid[8]; /* 'NTFS ' */ + u_int16_t bf_bps; /* bytes per sector */ + u_int8_t bf_spc; /* sectors per cluster */ + u_int8_t reserved2[7]; /* unused (zeroed) */ + u_int8_t bf_media; /* media desc. (0xF8) */ + u_int8_t reserved3[2]; + u_int16_t bf_spt; /* sectors per track */ + u_int16_t bf_heads; /* number of heads */ + u_int8_t reserver4[12]; + u_int64_t bf_spv; /* sectors per volume */ + cn_t bf_mftcn; /* $MFT cluster number */ + cn_t bf_mftmirrcn; /* $MFTMirr cn */ + u_int8_t bf_mftrecsz; /* MFT record size (clust) */ + /* 0xF6 inducates 1/4 */ + u_int8_t reserved5[3]; + u_int8_t bf_ibsz; /* index buffer size */ + u_int8_t reserved6[3]; + u_int64_t bf_volsn; /* volume ser. num. */ +}; + +/* + * Darwin's ntfs.util needs to include this file to get definitions + * for the on-disk structures. It doesn't need the ntfsmount structure. + * In fact, since it doesn't #define KERNEL, the struct netexport below + * won't be defined. + * + * So, I'm using #ifdef KERNEL around the things that are only relevant + * to the in-kernel implementation. + * + * I don't know if FreeBSD defines KERNEL, or if I need to use or + * invent a different conditional here. + */ +#ifdef KERNEL + +#define NTFS_SYSNODESNUM 0x0B +struct ntfsmount { + struct mount *ntm_mountp; /* filesystem vfs structure */ + struct bootfile ntm_bootfile; + dev_t ntm_dev; /* device mounted */ + struct vnode *ntm_devvp; /* block device mounted vnode */ + struct vnode *ntm_sysvn[NTFS_SYSNODESNUM]; + u_int32_t ntm_bpmftrec; + uid_t ntm_uid; + gid_t ntm_gid; + mode_t ntm_mode; + u_long ntm_flag; + cn_t ntm_cfree; + struct ntvattrdef *ntm_ad; /* attribute names are stored in native byte order */ + int ntm_adnum; + wchar * ntm_82u; /* 8bit to Unicode */ + char ** ntm_u28; /* Unicode to 8 bit */ +#ifdef APPLE + struct netexport ntm_export; /* NFS export information */ +#endif +}; + +#define ntm_mftcn ntm_bootfile.bf_mftcn +#define ntm_mftmirrcn ntm_bootfile.bf_mftmirrcn +#define ntm_mftrecsz ntm_bootfile.bf_mftrecsz +#define ntm_spc ntm_bootfile.bf_spc +#define ntm_bps ntm_bootfile.bf_bps + +#pragma pack() + +#define NTFS_NEXTREC(s, type) ((type)(((caddr_t) s) + le16toh((s)->reclen))) + +/* Convert mount ptr to ntfsmount ptr. */ +#define VFSTONTFS(mp) ((struct ntfsmount *)((mp)->mnt_data)) +#define VTONT(v) FTONT(VTOF(v)) +#define VTOF(v) ((struct fnode *)((v)->v_data)) +#define FTOV(f) ((f)->f_vp) +#define FTONT(f) ((f)->f_ip) +#define ntfs_cntobn(cn) ((daddr_t)(cn) * (ntmp->ntm_spc)) +#define ntfs_cntob(cn) ((off_t)(cn) * (ntmp)->ntm_spc * (ntmp)->ntm_bps) +#define ntfs_btocn(off) (cn_t)((off) / ((ntmp)->ntm_spc * (ntmp)->ntm_bps)) +#define ntfs_btocl(off) (cn_t)((off + ntfs_cntob(1) - 1) / ((ntmp)->ntm_spc * (ntmp)->ntm_bps)) +#define ntfs_btocnoff(off) (off_t)((off) % ((ntmp)->ntm_spc * (ntmp)->ntm_bps)) +#define ntfs_bntob(bn) (daddr_t)((bn) * (ntmp)->ntm_bps) + +#define ntfs_bpbl (daddr_t)((ntmp)->ntm_bps) + +#ifdef MALLOC_DECLARE +MALLOC_DECLARE(M_NTFSMNT); +MALLOC_DECLARE(M_NTFSNTNODE); +MALLOC_DECLARE(M_NTFSFNODE); +MALLOC_DECLARE(M_NTFSDIR); +MALLOC_DECLARE(M_NTFSNTHASH); +#endif + +#ifndef M_NTFSMNT +#define M_NTFSMNT M_TEMP +#endif +#ifndef M_NTFSNTNODE +#define M_NTFSNTNODE M_TEMP +#endif +#ifndef M_NTFSFNODE +#define M_NTFSFNODE M_TEMP +#endif +#ifndef M_NTFSDIR +#define M_NTFSDIR M_TEMP +#endif +#ifndef M_NTFSNTHASH +#define M_NTFSNTHASH M_TEMP +#endif +#ifndef M_NTFSRUN +#define M_NTFSRUN M_TEMP +#endif +#ifndef M_NTFSRDATA +#define M_NTFSRDATA M_TEMP +#endif +#ifndef M_NTFSNTVATTR +#define M_NTFSNTVATTR M_TEMP +#endif +#ifndef M_NTFSDECOMP +#define M_NTFSDECOMP M_TEMP +#endif +#define VT_NTFS VT_OTHER + +#if defined(NTFS_DEBUG) +#define dprintf(a) printf a +#if NTFS_DEBUG > 1 +#define ddprintf(a) printf a +#else +#define ddprintf(a) +#endif +#else +#define dprintf(a) +#define ddprintf(a) +#endif + +#ifdef APPLE +typedef int vop_t(void *); +#else +#endif +extern vop_t **ntfs_vnodeop_p; +#endif /* KERNEL */ Index: branches/Chimera/i386/libsaio/.svn/text-base/bios.s.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/bios.s.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/bios.s.svn-base (revision 850) @@ -0,0 +1,184 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright 1993 NeXT Computer, Inc. + * All rights reserved. + * + * Harness for calling real-mode BIOS functions. + */ + +/* Copyright 2007 David Elliott + 2007-12-30 dfe + - Enhanced code to use specified DS register when doing BIOS interrupt + - Fixed movl %ax,new_es bug which assembler was interpreting as + movl %eax,new_es which was overwriting the next word. + */ +#include +#include "memory.h" + +#define data32 .byte 0x66 +#define addr32 .byte 0x67 + +#define O_INT 0 +#define O_EAX 4 +#define O_EBX 8 +#define O_ECX 12 +#define O_EDX 16 +#define O_EDI 20 +#define O_ESI 24 +#define O_EBP 28 +#define O_CS 32 +#define O_DS 34 +#define O_ES 36 +#define O_FLG 38 + + .section __INIT,__data // turbo - Data that must be in the first segment + +/* Saved registers: + These used to be (and in theory ought to be) located in __DATA,__bss. + The problem is that the larger the binary grows, more of the BSS gets + pushed into the next real-mode segment. Doing it this way we waste 24 + bytes in the binary that our loader (e.g. boot1) must now load. But the + advantage is that we relocate this data to ensure it stays in the first + real-mode segment. Therefore, depending on link order, quite a lot of + new data, and possibly a lot of new executable code can be added to the + binary since with this change the BSS and most of the DATA is now only + accessed from protected mode where real-mode segment limits don't apply. + + With this change, plus the earlier change to respect DS (e.g. use huge + pointers), the binary can grow much larger, currently up to exactly 63.5k + which is the maximum that the first-stage bootsectors can handle. To get + more than that more changes are needed. In that case we would have to + play with Mach-O segments to ensure real-mode code and data got stuffed + well within the first 63.5k. Furthermore, we'd have to adjust the boot + sectors to allow them to span segments. + + Since this change alone only gains us about 4k more than where we're at + now (which is not anything to scoff at) it won't be very long before we + need to start using Mach-O segments to force the linker to locate certain + bits of code and data within the first 63.5k and modify the loaders to + be able to load more than 63.5k. + */ + .align 2 +save_eax: .space 4 + .align 2 +save_edx: .space 4 + .align 1 +save_es: .space 2 + .align 1 +save_flag: .space 2 + .align 2 +new_eax: .space 4 + .align 2 +new_edx: .space 4 + .align 1 +new_es: .space 2 + .align 1 +new_ds: .space 2 + + .section __INIT,__text // turbo - This code must reside within the first segment + + +/*============================================================================ + * Call real-mode BIOS INT functions. + * + */ +LABEL(_bios) + enter $0, $0 + pushal + + movl 8(%ebp), %edx // address of save area + movb O_INT(%edx), %al // save int number + movb %al, do_int+1 + + movl O_EBX(%edx), %ebx + movl O_ECX(%edx), %ecx + movl O_EDI(%edx), %edi + movl O_ESI(%edx), %esi + movl O_EBP(%edx), %ebp + movl %edx, save_edx + movl O_EAX(%edx), %eax + movl %eax, new_eax + movl O_EDX(%edx), %eax + movl %eax, new_edx + movw O_ES(%edx), %ax + movw %ax, new_es + movw O_DS(%edx), %ax + movw %ax, new_ds + + call __prot_to_real + + data32 + addr32 + mov OFFSET16(new_eax), %eax + data32 + addr32 + mov OFFSET16(new_edx), %edx + data32 + addr32 + mov OFFSET16(new_es), %es + + push %ds // Save DS + // Replace DS. WARNING: Don't access data until it's restored! + addr32 + data32 + mov OFFSET16(new_ds), %ds + +do_int: + int $0x00 + pop %ds // Restore DS before we do anything else + + pushf + data32 + addr32 + movl %eax, OFFSET16(save_eax) + popl %eax // actually pop %ax + addr32 + movl %eax, OFFSET16(save_flag) // actually movw + mov %es, %ax + addr32 + movl %eax, OFFSET16(save_es) // actually movw + data32 + call __real_to_prot + + movl %edx, new_edx // save new edx before clobbering + movl save_edx, %edx + movl new_edx, %eax // now move it into buffer + movl %eax, O_EDX(%edx) + movl save_eax, %eax + movl %eax, O_EAX(%edx) + movw save_es, %ax + movw %ax, O_ES(%edx) + movw save_flag, %ax + movw %ax, O_FLG(%edx) + movl %ebx, O_EBX(%edx) + movl %ecx, O_ECX(%edx) + movl %edi, O_EDI(%edx) + movl %esi, O_ESI(%edx) + movl %ebp, O_EBP(%edx) + + popal + leave + + ret Index: branches/Chimera/i386/libsaio/.svn/text-base/bootstruct.h.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/bootstruct.h.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/bootstruct.h.svn-base (revision 850) @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2002-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 2002-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ + +#ifndef __BOOTSTRUCT_H +#define __BOOTSTRUCT_H + +#include "bootargs.h" +#include "saio_types.h" +#include "bios.h" +#include "device_tree.h" + +/*! + Kernel boot args global also used by booter for its own data. + */ +extern boot_args *bootArgs; +extern boot_args_pre_lion *bootArgsPreLion; +extern Node *gMemoryMapNode; + +#define VGA_TEXT_MODE 0 + +/* + * Maximum number of boot drivers that can be loaded. + */ +#define NDRIVERS 500 + +#define CONFIG_SIZE (40 * 4096) + +/* + * Max size fo config data array, in bytes. + */ +#define IO_CONFIG_DATA_SIZE 163840 + +#define kMemoryMapCountMax 40 + +/* + * PCI bus information. + */ +typedef struct _PCI_bus_info_t { + union { + struct { + unsigned char configMethod1 :1; + unsigned char configMethod2 :1; + unsigned char :2; + unsigned char specialCycle1 :1; + unsigned char specialCycle2 :1; + } s; + unsigned char d; + } u_bus; + unsigned char maxBusNum; + unsigned char majorVersion; + unsigned char minorVersion; + unsigned char BIOSPresent; +} PCI_bus_info_t; + +typedef struct { + unsigned long address; // address where driver was loaded + unsigned long size; // number of bytes + unsigned long type; // driver type +} driver_config_t; + +/* + * INT15, E820h - Query System Address Map. + * + * Documented in ACPI Specification Rev 2.0, + * Chapter 15 (System Address Map Interfaces). + */ + +/* + * ACPI defined memory range types. + */ +enum { + kMemoryRangeUsable = 1, // RAM usable by the OS. + kMemoryRangeReserved = 2, // Reserved. (Do not use) + kMemoryRangeACPI = 3, // ACPI tables. Can be reclaimed. + kMemoryRangeNVS = 4, // ACPI NVS memory. (Do not use) + + /* Undefined types should be treated as kMemoryRangeReserved */ +}; + +/*! + PrivateBootInfo has fields used by the booter that used to be part of + KernelBootArgs_t *bootArgs. When the switch was made to EFI the structure + completely changed to boot_args *bootArgs. This (new to boot-132) structure + contains the fields the kernel no longer cares about but the booter still + uses internally. Some fields (e.g. the video information) remain interesting + to the kernel and are thus located in bootArgs although with different field names. + */ +typedef struct PrivateBootInfo { + int convmem; // conventional memory + int extmem; // extended memory +#if 0 + int numBootDrivers; // number of drivers loaded +#endif + char bootFile[128]; // kernel file name + + unsigned long memoryMapCount; + MemoryRange memoryMap[kMemoryMapCountMax]; + + PCI_bus_info_t pciInfo; + +#if 0 + driver_config_t driverConfig[NDRIVERS]; +#endif + char * configEnd; // pointer to end of config files + char config[CONFIG_SIZE]; + + config_file_t bootConfig; // boot.plist + config_file_t overrideConfig; // additional boot.plist which can override bootConfig keys + config_file_t themeConfig; // theme.plist + config_file_t smbiosConfig; // smbios.plist + config_file_t helperConfig; // boot helper partition's boot.plist + config_file_t ramdiskConfig; // RAMDisk.plist +} PrivateBootInfo_t; + +extern PrivateBootInfo_t *bootInfo; + +#endif /* __BOOTSTRUCT_H */ Index: branches/Chimera/i386/libsaio/.svn/text-base/stringTable.c.svn-base =================================================================== --- branches/Chimera/i386/libsaio/.svn/text-base/stringTable.c.svn-base (revision 0) +++ branches/Chimera/i386/libsaio/.svn/text-base/stringTable.c.svn-base (revision 850) @@ -0,0 +1,772 @@ +/* + * Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved. + * + * @APPLE_LICENSE_HEADER_START@ + * + * Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights + * Reserved. This file contains Original Code and/or Modifications of + * Original Code as defined in and that are subject to the Apple Public + * Source License Version 2.0 (the "License"). You may not use this file + * except in compliance with the License. Please obtain a copy of the + * License at http://www.apple.com/publicsource and read it before using + * this file. + * + * The Original Code and all software distributed under the License are + * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER + * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, + * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the + * License for the specific language governing rights and limitations + * under the License. + * + * @APPLE_LICENSE_HEADER_END@ + */ +/* + * Copyright 1993 NeXT, Inc. + * All rights reserved. + */ + +#include "bootstruct.h" +#include "libsaio.h" +#include "xml.h" + +extern char *Language; +extern char *LoadableFamilies; + +bool sysConfigValid; + +/* + * Compare a string to a key with quoted characters + */ +static inline int +keyncmp(const char *str, const char *key, int n) +{ + int c; + while (n--) { + c = *key++; + if (c == '\\') { + switch(c = *key++) { + case 'n': + c = '\n'; + break; + case 'r': + c = '\r'; + break; + case 't': + c = '\t'; + break; + default: + break; + } + } else if (c == '\"') { + /* Premature end of key */ + return 1; + } + if (c != *str++) { + return 1; + } + } + return 0; +} + +#if UNUSED + +static void eatThru(char val, const char **table_p) +{ + register const char *table = *table_p; + register bool found = false; + + while (*table && !found) + { + if (*table == '\\') table += 2; + else + { + if (*table == val) found = true; + table++; + } + } + *table_p = table; +} + +/* Remove key and its associated value from the table. */ + +bool +removeKeyFromTable(const char *key, char *table) +{ + register int len; + register char *tab; + char *buf; + + len = strlen(key); + tab = (char *)table; + buf = (char *)malloc(len + 3); + + sprintf(buf, "\"%s\"", key); + len = strlen(buf); + + while(*tab) { + if(strncmp(buf, tab, len) == 0) { + char c; + + while((c = *(tab + len)) != ';') { + if(c == 0) { + len = -1; + goto out; + } + len++; + } + len++; + if(*(tab + len) == '\n') len++; + goto out; + } + tab++; + } + len = -1; +out: + free(buf); + + if(len == -1) return false; + + while((*tab = *(tab + len))) { + tab++; + } + + return true; +} + +char * +newStringFromList( + char **list, + int *size +) +{ + char *begin = *list, *end; + char *newstr; + int newsize = *size; + int bufsize; + + while (*begin && newsize && isspace(*begin)) { + begin++; + newsize--; + } + end = begin; + while (*end && newsize && !isspace(*end)) { + end++; + newsize--; + } + if (begin == end) + return 0; + bufsize = end - begin + 1; + newstr = malloc(bufsize); + strlcpy(newstr, begin, bufsize); + *list = end; + *size = newsize; + return newstr; +} + +#endif + +/* + * compress == compress escaped characters to one character + */ +int stringLength(const char *table, int compress) +{ + int ret = 0; + + while (*table) + { + if (*table == '\\') + { + table += 2; + ret += 1 + (compress ? 0 : 1); + } + else + { + if (*table == '\"') return ret; + ret++; + table++; + } + } + return ret; +} + + +bool getValueForConfigTableKey(config_file_t *config, const char *key, const char **val, int *size) +{ + if (config->dictionary != 0 ) { + // Look up key in XML dictionary + TagPtr value; + value = XMLGetProperty(config->dictionary, key); + if (value != 0) { + if (value->type != kTagTypeString) { + error("Non-string tag '%s' found in config file\n", + key); + return false; + } + *val = value->string; + *size = strlen(value->string); + return true; + } + } else { + + // Legacy plist-style table + + } + + return false; +} + +#if UNUSED + +/* + * Returns a new malloc'ed string if one is found + * in the string table matching 'key'. Also translates + * \n escapes in the string. + */ +char *newStringForStringTableKey( + char *table, + char *key, + config_file_t *config +) +{ + const char *val; + char *newstr, *p; + int size; + + if (getValueForConfigTableKey(config, key, &val, &size)) { + newstr = (char *)malloc(size+1); + for (p = newstr; size; size--, p++, val++) { + if ((*p = *val) == '\\') { + switch (*++val) { + case 'r': + *p = '\r'; + break; + case 'n': + *p = '\n'; + break; + case 't': + *p = '\t'; + break; + default: + *p = *val; + break; + } + size--; + } + } + *p = '\0'; + return newstr; + } else { + return 0; + } +} + +#endif + +char * +newStringForKey(char *key, config_file_t *config) +{ + const char *val; + char *newstr; + int size; + + if (getValueForKey(key, &val, &size, config) && size) { + newstr = (char *)malloc(size + 1); + strlcpy(newstr, val, size + 1); + return newstr; + } else { + return 0; + } +} + +/* parse a command line + * in the form: [ ...] [

Chameleon è la combinazione di diverse parti del boot loader.
È basato sulle modifiche di David Elliott sull'implementazione "EFI" al progetto della Apple sul boot-132.
Chameleon presenta le seguenti caratteristiche principali:

+
+

Nuove caratteristiche di Chameleon 2.0

+
+

- Interfaccia grafica completamente personalizzabile per dare maggiori colori al Darwin Bootloader.

+

- Avviare DVD retail semplicemente caricando una immagine ramdisk senza l'utilizzo di programmi aggiuntivi.

+

- Ibernazione. Godetevi nel riprendere il vostro Mac OS X con un'immagine di anteprima.

+

- Sovrascrittura dle SMBIOS per personalizzare i valori dell'SMBIOS.

+

- Sovrascrittura della tabella DSDT, potendo selezionare una ottimizzata che risolve svariate problematiche.

+
+

- Iniezione delle Proprità delle Periferiche con stringhe EFI in device-properties.

+

- boot0 / boot1h ibrido per dischi partizionati in MBR e GPT.

+

- Riconoscimento automatico della frequenza anche sui recenti processori AMD.

+

- Supporta il RAID software di Apple.

+
+

Per maggiori informazioni, visita : http://chameleon.osx86.hu

+ + \ No newline at end of file Index: branches/Chimera/package/Resources/Italian.lproj/.svn/text-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/.svn/text-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/.svn/text-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,92 @@ +// General +"Chameleon_title" = "Chameleon"; + +"Standard_title" = "Chameleon Standard"; +"Standard_description" = "Installare Chameleon"; + +"EnhancedFAT_title" = "Chameleon EFI FAT"; +"EnhancedFAT_description" = "Installare Chameleon nella partizione di sistema EFI FAT32 (Originale)"; + +"EnhancedHFS_title" = "Chameleon EFI HFS"; +"EnhancedHFS_description" = "Installare Chameleon nella partizione di sistema EFI HFS (Consigliato se non gi HFS)"; + +// Options +"Options_title" = "Opzioni"; +"Options_description" = "Setta opzioni predefinite"; + +"GUI_title" = "GUI"; +"GUI_description" = "Disabilita l'interfaccia grafica, aggiunge GUI=n al com.apple.Boot.plist"; + +"EthernetBuiltIn_title" = "EthernetBuiltIn"; +"EthernetBuiltIn_description" = "Aggiunge EthernetBuiltIn=y al com.apple.Boot.plist, Questa opzione aggiunger 'built-in' alle periferice di rete."; + +"ForceHPET_title" = "ForceHPET"; +"ForceHPET_description" = "Aggiunge ForceHPET=y al com.apple.Boot.plist, Questa opzione abilita l'HPET sui chipset Intel, per BIOS che non includono questa opzione."; + +"ForceWake_title" = "ForceWake"; +"ForceWake_description" = "Aggiunge ForceWake=y al com.apple.Boot.plist, Questa opzione abilita la possibilit di evitare errate sleep images."; + +"EHCIacquire_title" = "EHCIacquire"; +"EHCIacquire_description" = "Aggiunge EHCIacquire=y al com.apple.Boot.plist, Questa opzione sistema eventuali propriet legati all'EHCI in alcuni BIOS."; + +"UHCIreset_title" = "UHCIreset"; +"UHCIreset_description" = "Aggiunge UHCIreset=y al com.apple.Boot.plist, Questa opzione resetter i controller UHCI prima dell'avvio di OS X."; + +"GraphicsEnabler_title" = "GraphicsEnabler"; +"GraphicsEnabler_description" = "Aggiunge GraphicsEnabler=y al com.apple.Boot.plist, Questa opzione abilita il riconoscimento automatico delle schede grafiche iniettanto le informazioni corrette."; + +// Themes +"Themes_title" = "Themes"; +"Themes_description" = "Una raccolta di temi campione"; + +"Default_title" = "Standard"; +"Default_description" = "Il tema standard usato dal bootloader, aggiunto qui per essere personalizzato."; + +"Big_title" = "Big"; +"Big_description" = "Un tema dal layout grande, per i fortunati possessori di schermi grandi"; + +"Twilight_title" = "Twilight"; +"Twilight_description" = "Un semplice tema per i fan di Twilight"; + +"Pinktink_title" = "PinkTink"; +"Pinktink_description" = "Un semplice tema con sfondo rosa e Tinkerbell"; + +"Msi_netbook_title" = "MSi Netbook"; +"Msi_netbook_description" = "Un semplice tema con il logo MSi per i netbook MSi =)"; + +"Bullet_title" = "Bullet"; +"Bullet_description" = "Un tema The Bullet by NoSmokingBandit"; + +// Extras +"Extras_title" = "Extras"; +"Extras_description" = "Una collezione di strumenti aggiuntivi"; + +"SMBios_title" = "SMBIOS Override"; +"SMBios_description" = "Abilita la sovrascrittura dell'SMBIOS di default con l'smbios.plist presente in Extra"; + +// Kexts +"Kexts_title" = "Kexts"; +"Kexts_description" = "Una collezione di utili dummy kexts compatibili con Extra"; + +"AHCIPortInjector_title" = "AHCIPort"; +"AHCIPortInjector_description" = "Aggiunge supporto AHCI per i Southbridge Intel ICH6 - ICH10, JMicron JMB383"; + +"IOAHCIBlockStorageInjector_title" = "IOAHCIBlockStorage"; +"IOAHCIBlockStorageInjector_description" = ""; + +"ATAPortInjector_title" = "IntelPIIXATA"; +"ATAPortInjector_description" = "Aggiunge supporto ATA per i Southbridge Intel ICH6 - ICH10"; + +"JMicronATAInjector_title" = "JMicronATA"; +"JMicronATAInjector_description" = "Add JMIcronATA support for Intel chipset"; + +"Disabler_title" = "Disabler"; +"Disabler_description" = "Disabilita l'AppleIntelCPUPowerManagement."; + +// Error strings +"ERROR_BOOTVOL" = "Questo software deve essere installato sul volume di avvio."; +"ERROR_INSTALL" = "Questo volume non risponde ai requisiti per questo aggiornamento."; + +"Newer_Package_Installed_message" = "A newer version of Chameleon is already installed"; +"Intel_Mac_message" = "This software cannot be installed on this computer."; + \ No newline at end of file Index: branches/Chimera/package/Resources/Italian.lproj/.svn/text-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/.svn/text-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/.svn/text-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,11 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;} +\vieww22060\viewh18360\viewkind0 +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\f0\b\fs20 \cf0 ITALIANO\ + +\b0 \ +EA0401\ +Rev. 4/1/09} \ No newline at end of file Index: branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 78 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/Italian.lproj/Welcome.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 86 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/Italian.lproj/Welcome.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Italian.lproj/Welcome.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +0dbb13e1bd6fe1cc62e6300d818e0db3 +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + + + + + + + + +907 + Index: branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,25 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;} +\margl1440\margr1440\vieww13160\viewh11700\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\ +\pard\ri0\ql\qnatural + +\fs26 \cf0 Sviluppatori: Crazor, Dense, fassl, fxtentacle, iNDi, JrCs, Kabyl, kaitek, mackerintel, mercurysquad, mozodojo, munky, rekursor, Turbo & zef \ +\ +Grazie a : asereBLN, bumby, cosmolt, dfe, Galaxy, kalyway, Krazubu, netkas, sckevyn, smith@@, THeKiNG, XyZ, blackosx +\b0\fs30 \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural +\cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 81 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/Italian.lproj/Conclusion.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 89 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/Italian.lproj/Conclusion.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Italian.lproj/Conclusion.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +6da0da86f01384d2ea7ef4437674367b +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + + + + + + + + +1092 + Index: branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Italian.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,34 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;\red255\green0\blue0;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\pard\ri0\qc + +\fs50 \cf3 Installazione terminata! +\b0\fs26 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs18 \cf0 \ +{\field{\*\fldinst{HYPERLINK "http://chameleon.osx86.hu/"}}{\fldrslt +\fs26 http://chameleon.osx86.hu/}} +\fs26 \ +{\field{\*\fldinst{HYPERLINK "http://forum.voodooprojects.org/index.php"}}{\fldrslt http://forum.voodooprojects.org/index.php}} +\b \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/Portuguese.lproj/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 68 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj +END +Description.html +K 25 +svn:wc:ra_dav:version-url +V 85 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj/Description.html +END +Localizable.strings +K 25 +svn:wc:ra_dav:version-url +V 88 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj/Localizable.strings +END +License.rtf +K 25 +svn:wc:ra_dav:version-url +V 80 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj/License.rtf +END Index: branches/Chimera/package/Resources/Portuguese.lproj/.svn/prop-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Resources/Portuguese.lproj/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/.svn/entries (revision 850) @@ -0,0 +1,136 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Portuguese.lproj +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-01T06:19:55.016590Z +468 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Description.html +file + + + + +2011-05-19T21:52:35.000000Z +396bcff7bc3a9f3bb8b2c08d17d9d57f +2010-09-01T06:19:55.016590Z +468 +blackosx + + + + + + + + + + + + + + + + + + + + + +1757 + +Welcome.rtfd +dir + +Localizable.strings +file + + + + +2011-05-19T21:52:35.000000Z +04ea0554a6ae816edea6a817c25166cd +2010-09-01T06:19:55.016590Z +468 +blackosx +has-props + + + + + + + + + + + + + + + + + + + + +7838 + +Conclusion.rtfd +dir + +License.rtf +file + + + + +2011-05-19T21:52:35.000000Z +5a44e71bd441737852c383de1636aedd +2010-09-01T06:19:55.016590Z +468 +blackosx + + + + + + + + + + + + + + + + + + + + + +323 + Index: branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/Description.html.svn-base =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/Description.html.svn-base (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/Description.html.svn-base (revision 850) @@ -0,0 +1,29 @@ + + + + + + + + + +

O Chameleon é um boot loader que combina vários componentes.
Ele é baseado na implementação de fake EFI feita por David Elliott, adicionada ao projeto boot-132 da Apple.
O Chameleon é extendido com as seguintes características chave:

+
+

Novos recursos no Chameleon 2.0

+
+

- Interface gráfica (GUI) totalmente personalizável para trazer algumas cores ao Bootloader Darwin.

+

- Inicializa DVDs retail lendo uma imagem ramdisk diretamente, sem ajuda de nenhum programa adicional.

+

- Hibernação. Aproveite continuar o seu Mac OS X com uma amostra de imagem da tela.

+

- Substituição de SMBIOS para modificar os valores de fábrica.

+

- Substituição de DSDT para usar uma tabela modificada que pode resolver diversos problemas.

+
+

- Injeção de propriedades de dispositivo através do string device-properties.

+

- boot0 / boot1h híbridos para discos particionados em MBR e GPT.

+

- Detecção automática de FSB mesmo para processadores AMD recentes.

+

- Suporte a Software RAID da Apple.

+
+

Para informações detalhadas visite: http://chameleon.osx86.hu

+ + Index: branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,92 @@ +// General +"Chameleon_title" = "Chameleon"; + +"Standard_title" = "Chameleon Padro"; +"Standard_description" = "Instalar o Chameleon"; + +"EnhancedFAT_title" = "Chameleon EFI FAT"; +"EnhancedFAT_description" = "Instalar o Chameleon na partio EFI FAT32 (Original)"; + +"EnhancedHFS_title" = "Chameleon EFI HFS"; +"EnhancedHFS_description" = "Instalar o Chameleon na partio EFI HFS (Reformatada se j no for HFS)"; + +// Options +"Options_title" = "Opes"; +"Options_description" = "Selecionar opes padro"; + +"GUI_title" = "GUI"; +"GUI_description" = "Desligar a interface grfica, adiciona GUI=n no arquivo com.apple.Boot.plist"; + +"EthernetBuiltIn_title" = "EthernetBuiltIn"; +"EthernetBuiltIn_description" = "Adicionar EthernetBuiltIn=y no arquivo com.apple.Boot.plist, esta opo vai adicionar 'built-in' nos seus dispositivos ethernet."; + +"ForceHPET_title" = "ForceHPET"; +"ForceHPET_description" = "Adicionar ForceHPET=y no arquivo com.apple.Boot.plist, esta opo habilita o HPET nos chipsets Intel, para BIOS que no incluem esta opo."; + +"ForceWake_title" = "ForceWake"; +"ForceWake_description" = "Adicionar ForceWake=y no arquivo com.apple.Boot.plist, esta opo permite que voc contorne imagens de repouso com problema."; + +"EHCIacquire_title" = "EHCIacquire"; +"EHCIacquire_description" = "Adicionar EHCIacquire=y no arquivo com.apple.Boot.plist, esta opo corrige problemas de EHCI devido a BIOS com problema."; + +"UHCIreset_title" = "UHCIreset"; +"UHCIreset_description" = "Adicionar UHCIreset=y no arquivo com.apple.Boot.plist, esta opo reinicia os controladores UHCI antes de iniciar o OS X."; + +"GraphicsEnabler_title" = "GraphicsEnabler"; +"GraphicsEnabler_description" = "Adicionar GraphicsEnabler=y no arquivo com.apple.Boot.plist, esta opo auto detecta placas NVIDIA e injeta a informao correta."; + +// Themes +"Themes_title" = "Temas"; +"Themes_description" = "Uma coleo de temas de exemplo"; + +"Default_title" = "Padro"; +"Default_description" = "O tema que embutido no boot loader, includo aqui para voc personalizar."; + +"Big_title" = "Grande"; +"Big_description" = "Um tema com leiaute maior para os sortudos com monitores grandes"; + +"Twilight_title" = "Twilight"; +"Twilight_description" = "Um tema simples para os fs de Twilight"; + +"Pinktink_title" = "PinkTink"; +"Pinktink_description" = "Um tema simples com fundo rosa e a Sininho"; + +"Msi_netbook_title" = "Netbook MSi"; +"Msi_netbook_description" = "Um logo simples para o seu netbook MSi =)"; + +"Bullet_title" = "Bullet"; +"Bullet_description" = "O tema Bullet por NoSmokingBandit"; + +// Extras +"Extras_title" = "Extras"; +"Extras_description" = "Uma coleo de adicionais teis"; + +"SMBios_title" = "Substituir SMBIOS"; +"SMBios_description" = "Instalar a substituio SMBIOS padro smbios.plist na pasta Extra"; + +// Kexts +"Kexts_title" = "Kexts"; +"Kexts_description" = "Uma coleo til de kexts com apenas plist compatveis com a pasta Extra"; + +"AHCIPortInjector_title" = "AHCIPort"; +"AHCIPortInjector_description" = "Adicionar suporte AHCI para chipsets Southbridge Intel ICH6 - ICH10, JMicron JMB383"; + +"IOAHCIBlockStorageInjector_title" = "IOAHCIBlockStorage"; +"IOAHCIBlockStorageInjector_description" = ""; + +"ATAPortInjector_title" = "IntelPIIXATA"; +"ATAPortInjector_description" = "Adicionar suporte ATA para chipsets Southbridge Intel ICH6 - ICH10"; + +"JMicronATAInjector_title" = "JMicronATA"; +"JMicronATAInjector_description" = "Adicionar suporte JMIcronATA para chipset Intel"; + +"Disabler_title" = "Disabler"; +"Disabler_description" = "Desabilitar a AppleIntelCPUPowerManagement."; + +// Error strings +"ERROR_BOOTVOL" = "Este programa deve ser instalado no volume de inicializao."; +"ERROR_INSTALL" = "Este volume no preenche os requisitos para esta atualizao."; + +"Newer_Package_Installed_message" = "Uma verso mais recente do Chameleon j est instalada"; +"Intel_Mac_message" = "Este programa no pode ser instalado neste computador."; + \ No newline at end of file Index: branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/.svn/text-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,11 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;} +\vieww22060\viewh18360\viewkind0 +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\f0\b\fs20 \cf0 PORTUGUESE\ + +\b0 \ +EA0401\ +Rev. 4/1/09} \ No newline at end of file Index: branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 81 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj/Welcome.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 89 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj/Welcome.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Portuguese.lproj/Welcome.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-01T06:19:55.016590Z +468 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +7fe4154e51c3d26f4dc82cd207dcd1d7 +2010-09-01T06:19:55.016590Z +468 +blackosx + + + + + + + + + + + + + + + + + + + + + +919 + Index: branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,26 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE% +\fs26 \cf0 \ +\ +\pard\ri0\ql\qnatural +\cf0 Desenvolvedores: Crazor, Dense, fassl, fxtentacle, iNDi, JrCs, Kabyl, kaitek, mackerintel, mercurysquad, mozodojo, munky, rekursor, Turbo & zef \ +\ +\ +Agradecimentos a: asereBLN, bumby, cosmolt, dfe, Galaxy, kalyway, Krazubu, netkas, sckevyn, smith@@, THeKiNG, XyZ, blackosx\ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 84 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj/Conclusion.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 92 +/svn/chameleon/!svn/ver/468/trunk/package/Resources/Portuguese.lproj/Conclusion.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Portuguese.lproj/Conclusion.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-01T06:19:55.016590Z +468 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +99df3e2dbbb781d577cfbd1108bf801f +2010-09-01T06:19:55.016590Z +468 +blackosx + + + + + + + + + + + + + + + + + + + + + +1098 + Index: branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Portuguese.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,34 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;\red255\green0\blue0;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\pard\ri0\qc + +\fs50 \cf3 Instala\'e7\'e3o Conclu\'edda! +\b0\fs26 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs18 \cf0 \ +{\field{\*\fldinst{HYPERLINK "http://chameleon.osx86.hu/"}}{\fldrslt +\fs26 http://chameleon.osx86.hu/}} +\fs26 \ +{\field{\*\fldinst{HYPERLINK "http://forum.voodooprojects.org/index.php"}}{\fldrslt http://forum.voodooprojects.org/index.php}} +\b \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 67 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj +END +Description.html +K 25 +svn:wc:ra_dav:version-url +V 84 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj/Description.html +END +Localizable.strings +K 25 +svn:wc:ra_dav:version-url +V 87 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj/Localizable.strings +END +License.rtf +K 25 +svn:wc:ra_dav:version-url +V 79 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj/License.rtf +END Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/Description.html.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/Description.html.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/Description.html.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 14 +svn:executable +V 1 +* +END Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,9 @@ +K 14 +svn:executable +V 1 +* +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/prop-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,9 @@ +K 14 +svn:executable +V 1 +* +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/entries (revision 850) @@ -0,0 +1,136 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Bulgarian.lproj +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-03T21:05:10.301986Z +487 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Description.html +file + + + + +2011-05-19T21:52:35.000000Z +a745088c2e75f5855ad650504387285a +2010-09-03T21:05:10.301986Z +487 +blackosx +has-props + + + + + + + + + + + + + + + + + + + + +2230 + +Welcome.rtfd +dir + +Localizable.strings +file + + + + +2011-05-19T21:52:35.000000Z +25d45a12d7d218be073918a898009480 +2010-09-03T21:05:10.301986Z +487 +blackosx +has-props + + + + + + + + + + + + + + + + + + + + +7876 + +Conclusion.rtfd +dir + +License.rtf +file + + + + +2011-05-19T21:52:35.000000Z +439757eff8200a75b1f82076b79b5c15 +2010-09-03T21:05:10.301986Z +487 +blackosx +has-props + + + + + + + + + + + + + + + + + + + + +297 + Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/Description.html.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/Description.html.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/Description.html.svn-base (revision 850) @@ -0,0 +1,30 @@ + + + + + + + + + +

Chameleon е комбинация от разбични boot loader компоненти.
Базиран е на fake EFI изпълнението на Дейвид Ейлиът добавено към проекта boot-132 на Apple.
Chameleon е разширен със следните ключови функции:

+
+

Нови функции в Chameleon 2.0

+
+

- Напълно управляем графичен интерфейс за добавяне на живи цветове към Darwin Bootloader.

+

- Boot-ва retail DVD-та чрез директно зареждане на ramdisk image без помоща на допълнителни програми.

+

- Хибернация.

+

- SMBIOS заместване, за да бъдат модифицирани оригиналните SMBIOS стойности.

+

- DSDT заместване, за да бъде използвано модифицирано DSDT, което решава множество проблеми.

+
+

- Вграждане на особеностите на различни хардуерни устройства посредством device-properties стрингове.

+

- Хибридни boot0 / boot1h за MBR и GPT разделени дискове..

+

- Автоматично разпознаване на FSB за новите AMD процесори.

+

- Поддръжка на Apple Software RAID..

+
+

За повече информация посетете: http://chameleon.osx86.hu

+ + + Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,183 @@ +// General + +"Chameleon_title" = "Chameleon"; + + + +"Standard_title" = "Chameleon Standard"; + +"Standard_description" = "!B0=40@B=> 8=AB0;8@0=5 =0 Chameleon"; + + + +"EnhancedFAT_title" = "Chameleon EFI FAT"; + +"EnhancedFAT_description" = "=AB0;8@0=5 =0 Chameleon 2 EFI A8AB5<5= 4O; ?@8 =0;8G85 =0 FAT32 4O; (?F8O)"; + + + +"EnhancedHFS_title" = "Chameleon EFI HFS"; + +"EnhancedHFS_description" = "=AB0;8@0=5 =0 Chameleon 2 EFI A8AB5<5= 4O; ?@8 =0;8G85 =0 HFS 4O; ($>@<0B8@0 A5 =0=>2>, 0:> ?>A>G5=8O 4O; =5 5 HFS)"; + + + +// Options + +"Options_title" = "?F88"; + +"Options_description" = "?F88 ?> ?>4@0718@0=5"; + + + +"GUI_title" = "GUI"; + +"GUI_description" = "@5<0E20 3@0D8G=8O 8=B5@D59A :0B> 4>102O GUI=n 2 com.apple.Boot.plist"; + + + +"EthernetBuiltIn_title" = "EthernetBuiltIn"; + +"EthernetBuiltIn_description" = ">102O EthernetBuiltIn=y 2 com.apple.Boot.plist. "078 >?F8O I5 =0?@028 '23@045=8' 20H8B5 Ethernet CAB@>9AB20."; + + + +"ForceHPET_title" = "ForceHPET"; + +"ForceHPET_description" = ">102O ForceHPET=y 2 com.apple.Boot.plist. CA:0 2 459AB285 HPET ?@8 Intel G8?A5B8 70 BIOS-8, :>8B> =5 @07?>;030B A HPET."; + + + +"ForceWake_title" = "ForceWake"; + +"ForceWake_description" = ">102O ForceWake=y 2 com.apple.Boot.plist. ?F8OB0 ?>72>;O20 40 ?@5A:>G8B5 (40 =5 70@5640B5) ?>2@545=8 '87>1@065=8O' =0 >?5@0F8>==0B0 A8AB5<0."; + + + +"EHCIacquire_title" = "EHCIacquire"; + +"EHCIacquire_description" = ">102O EHCIacquire=y 2 com.apple.Boot.plist. ?F8OB0 ?>?@02O 2AO:0:28 EHCI (USB 1.0) ?@>1;5<8 ?>@048 =5:>@5:B=> =0?8A0=8 BIOS-8."; + + + +"UHCIreset_title" = "UHCIreset"; + +"UHCIreset_description" = ">102O UHCIreset=y 2 com.apple.Boot.plist. =8F80;878@0 UHCI (USB 2.0) :>=B@>;5@8B5 ?@548 AB0@B8@0=5 =0 OS X."; + + + +"GraphicsEnabler_title" = "GraphicsEnabler"; + +"GraphicsEnabler_description" = ">102O GraphicsEnabler=y 2 com.apple.Boot.plist. 2B><0B8G=> @07?>7=020=5 =0 2845> :0@B8 A nVidia G8?A5B 8 4>102O=5 =0 AJ>B25B=0B0 70 BOE 8=D>@<0F8O."; + + + +// Themes + +"Themes_title" = ""5<8"; + +"Themes_description" = ">;5:F8O >B B5<8"; + + + +"Default_title" = "!B0=40@B=0"; + +"Default_description" = "3@045=0B0 B5<0 2 Chameleon."; + + + +"Big_title" = "Big"; + +"Big_description" = ""5<0 A 28A>:0 @57>;NF8O 70 3>;5<8 <>=8B>@8"; + + + +"Twilight_title" = "Twilight"; + +"Twilight_description" = "!5<?;0 B5<0 70 Twilight D5=>25"; + + + +"Pinktink_title" = "PinkTink"; + +"Pinktink_description" = "!5<?;0 B5<0 A @>7>2 D>= 8 Tinkerbell"; + + + +"Msi_netbook_title" = "MSi Netbook"; + +"Msi_netbook_description" = "!5<?;> MSi boot ;>3> 70 20H8O MSi =5B1C: =)"; + + + +"Bullet_title" = "Bullet"; + +"Bullet_description" = "The Bullet B5<0 >B NoSmokingBandit"; + + + +// Extras + +"Extras_title" = "Extras"; + +"Extras_description" = ">;5:F8O >B ?>;57=8 4>102:8"; + + + +"SMBios_title" = "SMBIOS Override"; + +"SMBios_description" = "=AB0;8@0 SMBIOS overrides smbios.plist ?> ?>4@0718@0=5 2 Extra"; + + + +// Kexts + +"Kexts_title" = "Kexts"; + +"Kexts_description" = ">;5:F8O >B ?>;57=8 kext->25 (AJ4J@60I8 A0<> plist), AJ2<5AB8<8 A Extra"; + + + +"AHCIPortInjector_title" = "AHCIPort"; + +"AHCIPortInjector_description" = ">102O AHCI ?>4@J6:0 70 Intel Southbridge G8?A5B8 ICH6 - ICH10, JMicron JMB383"; + + + +"IOAHCIBlockStorageInjector_title" = "IOAHCIBlockStorage"; + +"IOAHCIBlockStorageInjector_description" = ""; + + + +"ATAPortInjector_title" = "IntelPIIXATA"; + +"ATAPortInjector_description" = ">102O ATA ?>4@J6:0 70 Intel Southbridge G8?A5B8 ICH6 - ICH10"; + + + +"JMicronATAInjector_title" = "JMicronATA"; + +"JMicronATAInjector_description" = ">102O JMIcronATA ?>4@J6:0 70 Intel G8?A5B"; + + + +"Disabler_title" = "Disabler"; + +"Disabler_description" = "@5<0E20 AppleIntelCPUPowerManagement."; + + + +// Error strings + +"ERROR_BOOTVOL" = "">78 A>DBC5@ B@O120 40 1J45 8=AB0;8@0= =0 AB0@B>28O 4O;."; + +"ERROR_INSTALL" = "">78 4O; =5 >B3>20@O =0 878A:20=8OB0 70 B>20 >1=>2O20=5."; + + + +"Newer_Package_Installed_message" = "> =>20 25@A8O =0 Chameleon 25G5 5 8=AB0;8@0=0."; + +"Intel_Mac_message" = "!>DBC5@JB =5 <>65 40 1J45 8=AB0;8@0= =0 B>78 :><?NBJ@."; + + \ No newline at end of file Index: branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/.svn/text-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,7 @@ +{\rtf1\ansi\ansicpg1252\deff0{\fonttbl{\f0\fnil\fcharset0 LucidaGrande;}} +{\*\generator Msftedit 5.41.15.1515;}\viewkind4\uc1\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\lang1033\b\f0\fs20 BULGARIAN\par +\b0\par +EA0401\par +\pard Rev. 4/1/09\par +} + \ No newline at end of file Index: branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 80 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj/Welcome.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 88 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj/Welcome.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Bulgarian.lproj/Welcome.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-03T21:05:10.301986Z +487 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +9d6e29950da8f74e2d8a4fc4646534c7 +2010-09-03T21:05:10.301986Z +487 +blackosx + + + + + + + + + + + + + + + + + + + + + +1087 + Index: branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,26 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE% +\fs26 \cf0 \ +\pard\ri0\ql\qnatural +\cf0 \ +\uc0\u1056 \u1072 \u1079 \u1088 \u1072 \u1073 \u1086 \u1090 \u1077 \u1085 \u1086 \u1090 : Crazor, Dense, fassl, fxtentacle, iNDi, JrCs, Kabyl, kaitek, mackerintel, mercurysquad, mozodojo, munky, rekursor, Turbo & zef \ +\ +\ +\uc0\u1041 \u1083 \u1072 \u1075 \u1086 \u1076 \u1072 \u1088 \u1085 \u1086 \u1089 \u1090 \u1080 \u1085 \u1072 : asereBLN, bumby, cosmolt, dfe, Galaxy, kalyway, Krazubu, netkas, sckevyn, smith@@, THeKiNG, XyZ, blackosx\ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 83 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj/Conclusion.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 91 +/svn/chameleon/!svn/ver/487/trunk/package/Resources/Bulgarian.lproj/Conclusion.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Bulgarian.lproj/Conclusion.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-09-03T21:05:10.301986Z +487 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +954964f5bf1a2d9f4af650afb4545a86 +2010-09-03T21:05:10.301986Z +487 +blackosx + + + + + + + + + + + + + + + + + + + + + +1229 + Index: branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Bulgarian.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,34 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;\red255\green0\blue0;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\pard\ri0\qc + +\fs50 \cf3 \uc0\u1048 \u1085 \u1089 \u1090 \u1072 \u1083 \u1072 \u1094 \u1080 \u1103 \u1090 \u1072 \u1077 \u1079 \u1072 \u1074 \u1098 \u1088 \u1096 \u1077 \u1085 \u1072 ! +\b0\fs26 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs18 \cf0 \ +{\field{\*\fldinst{HYPERLINK "http://chameleon.osx86.hu/"}}{\fldrslt +\fs26 http://chameleon.osx86.hu/}} +\fs26 \ +{\field{\*\fldinst{HYPERLINK "http://forum.voodooprojects.org/index.php"}}{\fldrslt http://forum.voodooprojects.org/index.php}} +\b \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/French.lproj/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/French.lproj/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/French.lproj/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 64 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/French.lproj +END +Description.html +K 25 +svn:wc:ra_dav:version-url +V 79 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/French.lproj/Description.html +END +Localizable.strings +K 25 +svn:wc:ra_dav:version-url +V 82 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/French.lproj/Localizable.strings +END +License.rtf +K 25 +svn:wc:ra_dav:version-url +V 74 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/French.lproj/License.rtf +END Index: branches/Chimera/package/Resources/French.lproj/.svn/prop-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/French.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/French.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Resources/French.lproj/.svn/entries =================================================================== --- branches/Chimera/package/Resources/French.lproj/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/French.lproj/.svn/entries (revision 850) @@ -0,0 +1,136 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/French.lproj +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Description.html +file + + + + +2011-05-19T21:52:35.000000Z +b5d2c2a6924d8e1f9e5acd0ade30b2b9 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +2356 + +Welcome.rtfd +dir + +Localizable.strings +file + + + + +2011-05-19T21:52:35.000000Z +e43d9f1dd615f75b869578cfbd09ee87 +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +7964 + +Conclusion.rtfd +dir + +License.rtf +file + + + + +2011-05-19T21:52:35.000000Z +2be2557da0e20a04fa88964be8e85a30 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +358 + Index: branches/Chimera/package/Resources/French.lproj/.svn/text-base/Description.html.svn-base =================================================================== --- branches/Chimera/package/Resources/French.lproj/.svn/text-base/Description.html.svn-base (revision 0) +++ branches/Chimera/package/Resources/French.lproj/.svn/text-base/Description.html.svn-base (revision 850) @@ -0,0 +1,37 @@ + + + + + + + + + + + +

Chameleon est une conbinaison de différent composants de boot loader.

+

Il est basé sur la "fake EFI" implémentation de David Elliott ajouté au projet  Apple's boot-132.

+


+

Chameleon à été amélioré avec les fonctions clé suivantes:

+


+

Les nouvelles fonctionnalités de Chameleon 2.0

+


+

- Interface graphique entierement customisable pour apporter un peu de couleur au Darwin Bootloader.

+

- Booter un DVD Retail en chargeant directement une image RAMDISK sans l'aide de programmes tierce.

+

- Hibernation:  Appréciez  l'affichage d'un apercu d'écran durant le démarrage  après mise en veille.

+

- SMBIOS override : pour modifier les valeur d'usines du SMBIOS.

+

- DSDT override : Utilisation d'un DSDT modifié pouvant résoudre quelques problemes .

+


+

- Device Property Injection via device-properties string dans boot.plist.

+

- Hybrid boot0 / boot1h pour disque dur partionnés en MBR et GPT .

+

- Détection du FSB automatique , mème pour les CPU AMD récents.

+

- Support du Apple Software RAID .

+


+

Pour des informations plus détaillées , visitez : http://chameleon.osx86.hu

+ + Index: branches/Chimera/package/Resources/French.lproj/.svn/text-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/French.lproj/.svn/text-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/French.lproj/.svn/text-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,91 @@ +// General +"Chameleon_title" = "Chameleon"; + +"Standard_title" = "Chameleon Standard"; +"Standard_description" = "Installation Standard de Chameleon !"; + +"EnhancedFAT_title" = "Chameleon EFI FAT"; +"EnhancedFAT_description" = "Installe Chameleon sur la partition EFI (cach) Systeme FAT32 (Originale non formate)"; + +"EnhancedHFS_title" = "Chameleon EFI HFS"; +"EnhancedHFS_description" = "Installe Chameleon sur la partition EFI (cach) Systeme HFS+ (Reformater en HFS+ si elle n'y est pas dj !)"; + +// Options +"Options_title" = "Options"; +"Options_description" = "Dfinissez les options par defaut"; + +"GUI_title" = "GUI"; +"GUI_description" = "Dsactive l'interface graphique , (ajoute l'option GUI=n au fichier com.apple.Boot.plist)"; + +"EthernetBuiltIn_title" = "EthernetBuiltIn"; +"EthernetBuiltIn_description" = "ajoute EthernetBuiltIn=y au fichier com.apple.Boot.plist, cette option ajoutera 'built-in' a votre carte ethernet."; + +"ForceHPET_title" = "ForceHPET"; +"ForceHPET_description" = "ajoute ForceHPET=y to com.apple.Boot.plist, Cette option active HPET sur les chipsets intel,(pour les bios qui n'ont pas cette options)."; + +"ForceWake_title" = "ForceWake"; +"ForceWake_description" = "rveille forc, (ajoute l'option ForceWake=y au fichier com.apple.Boot.plist)"; + +"EHCIacquire_title" = "EHCIacquire"; +"EHCIacquire_description" = "fixe certains problme de branchement usb a chaud et de reconnaissance usb2 !"; + +"UHCIreset_title" = "UHCIreset"; +"UHCIreset_description" = "fixe quelques rares problmes de detection usb"; + +"GraphicsEnabler_title" = "GraphicsEnabler"; +"GraphicsEnabler_description" = "ajoute GraphicsEnabler=y au fichier com.apple.Boot.plist, cette option dtectera et activera correctement votre gpu nvidia "; + +// Themes +"Themes_title" = "Themes"; +"Themes_description" = "Une collection de themes sampl"; + +"Default_title" = "Standard"; +"Default_description" = "Ce theme est cod directement dans le fichier Boot, inclu ici pour vous comme base de customisation."; + +"Big_title" = "Big"; +"Big_description" = "UN thme avec une mise en page style large pour les gens qui ont la chance d'avoir un grand moniteur"; + +"Twilight_title" = "Twilight"; +"Twilight_description" = "Twilight thme"; + +"Pinktink_title" = "PinkTink"; +"Pinktink_description" = "Fe PinkTink comme logo de de dmarrage"; + +"Msi_netbook_title" = "MSi Netbook"; +"Msi_netbook_description" = "logo de dmarrage Msi Netbook"; + +"Bullet_title" = "Bullet"; +"Bullet_description" = "Bullet thme de NoSmokingBandit"; + +// Extras +"Extras_title" = "Extras"; +"Extras_description" = "une collection d'addons utiles"; + +"SMBios_title" = "SMBIOS Override"; +"SMBios_description" = "Installe le fichier de configuration SMBIOS smbios.plist into Extra"; + +// Kexts +"Kexts_title" = "Kexts"; +"Kexts_description" = "une collection utile de kext avec plist seulement compatible avec Extra"; + +"AHCIPortInjector_title" = "AHCIPort"; +"AHCIPortInjector_description" = "Ajoute le support AHCI pour le chipset Intel Southbridge ICH6 ICH10, JMicron JMB383"; + +"IOAHCIBlockStorageInjector_title" = "IOAHCIBlockStorage"; +"IOAHCIBlockStorageInjector_description" = "en mode ahci vos dique dur interne apparaisse orange sur votre bureau , ce fix corrige ce default !"; + +"ATAPortInjector_title" = "IntelPIIXATA"; +"ATAPortInjector_description" = "Ajoute le support du chipset Intel Southbridge ICH6 ICH10"; + +"JMicronATAInjector_title" = "JMicronATA"; +"JMicronATAInjector_description" = "Ajoute le support des ports JMIcronATA sur chipset Intel"; + +"Disabler_title" = "Disabler"; +"Disabler_description" = "empche AppleIntelCPUPowerManagement.kext de se charger."; + +// Error strings +"ERROR_BOOTVOL" = "Ce logiciel doit etre install sur le volume de dmarrage"; +"ERROR_INSTALL" = "ce volume ne runit pas les conditions requises por cette mise jour."; + +"Newer_Package_Installed_message" = "Une version plus rcente de chameleon est dja installe"; +"Intel_Mac_message" = "Ce logiciel ne peux etre install sur cet ordinateur."; Index: branches/Chimera/package/Resources/French.lproj/.svn/text-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/French.lproj/.svn/text-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/French.lproj/.svn/text-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,13 @@ +{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf430 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;} +\vieww9000\viewh8400\viewkind0 +\pard\ql\qnatural + +\f0\b\fs20 \cf0 FRAN\'c7AIS\ +\pard\qj +\cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\b0 \cf0 EA0401\ +Rev. 4/1/09} \ No newline at end of file Index: branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/French.lproj/Welcome.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 85 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/French.lproj/Welcome.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/French.lproj/Welcome.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +da2d7d6dcaf6df8eb59112bf9c96615e +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + + + + + + + + +916 + Index: branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/French.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,27 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\ +Developeurs: Crazor, Dense, fassl, fxtentacle, iNDi, JrCs, Kabyl, kaitek, mackerintel, mercurysquad, mozodojo, munky, rekursor, Turbo & zef \ +\ +\ +Remerciements : asereBLN, bumby, cosmolt, dfe, Galaxy, kalyway, Krazubu, netkas, sckevyn, smith@@, THeKiNG, XyZ, blackosx\ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010 } \ No newline at end of file Index: branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 80 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/French.lproj/Conclusion.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 88 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/French.lproj/Conclusion.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/French.lproj/Conclusion.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +b19b78a389e06b4a012b3e920e6ac550 +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + + + + + + + + +1093 + Index: branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/French.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,34 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;\red255\green0\blue0;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\pard\ri0\qc + +\fs50 \cf3 Installation compl\'e8te! +\b0\fs26 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs18 \cf0 \ +{\field{\*\fldinst{HYPERLINK "http://chameleon.osx86.hu/"}}{\fldrslt +\fs26 http://chameleon.osx86.hu/}} +\fs26 \ +{\field{\*\fldinst{HYPERLINK "http://forum.voodooprojects.org/index.php"}}{\fldrslt http://forum.voodooprojects.org/index.php}} +\b \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/Spanish.lproj/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 65 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/Spanish.lproj +END +Description.html +K 25 +svn:wc:ra_dav:version-url +V 80 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/Spanish.lproj/Description.html +END +Localizable.strings +K 25 +svn:wc:ra_dav:version-url +V 83 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/Spanish.lproj/Localizable.strings +END +License.rtf +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/Spanish.lproj/License.rtf +END Index: branches/Chimera/package/Resources/Spanish.lproj/.svn/prop-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Resources/Spanish.lproj/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/.svn/entries (revision 850) @@ -0,0 +1,136 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Spanish.lproj +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Description.html +file + + + + +2011-05-19T21:52:35.000000Z +032e1c2bab75b0091bcce146f64897d8 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +2073 + +Welcome.rtfd +dir + +Localizable.strings +file + + + + +2011-05-19T21:52:35.000000Z +70f97c2be46c7cbdd4408723ad8675d3 +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +7822 + +Conclusion.rtfd +dir + +License.rtf +file + + + + +2011-05-19T21:52:35.000000Z +06dbb6e3aac9807b984f886ac83051bf +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +322 + Index: branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/Description.html.svn-base =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/Description.html.svn-base (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/Description.html.svn-base (revision 850) @@ -0,0 +1,35 @@ + + + + + + + + + + + +

Camaleón es la combinación de varios  boot loader componentes.
+Esta basado en la implementación EFI falsa de David Elliott agregada al proyecto boot-132 de Apple.
+Camaleón esta extendido con las siguientes caracteristicas:

+


+

Adicionales en Camaleón 2.0

+


+

- GUI  totalmente personalizado para brindarle algo de color al Dawin Bootloader.

+

- Booting DVDs con simplemente cargar una imagen ramdisk sin la ayuda de programas adicionales.

+

- Hibernación. Disfrute reanudar su MAC OS X con una imagen de muestra.

+

- SMBIOS anulado para modificar la fabrica SMBIOS valores.

+

- DSDT anulado para usar un DSDT modificado y arreglado capaz de resolver varios inconvenientes.

+


+

- Injeccion Propiedades del Dispositivo por la cuerda Propiedades del Dispositivo.

+

- Hibrido boot0 / boot1h para discos MBR y GPT divididos.

+

- Codigo de detección FSB automatico para CPUs AMD recientes..

+

- Ayuda RAID para software Apple.

+


+

Para información mas detallada, visitar : http://chameleon.osx86.hu

+ + Index: branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,183 @@ +// General + +"Chameleon_title" = "Camalen"; + + + +"Standard_title" = "Camalen estandar"; + +"Standard_description" = "Instalar Camalen"; + + + +"EnhancedFAT_title" = "Camalen EFI FAT"; + +"EnhancedFAT_description" = "Instalar Camalen al Sistema EFI division FAT32 (Original)"; + + + +"EnhancedHFS_title" = "Camalen EFI HFS"; + +"EnhancedHFS_description" = "Instalar Camalen al Sistema EFI division HFS (Reformateado)"; + + + +// Options + +"Options_title" = "Opciones"; + +"Options_description" = "Configurar opciones por defecto"; + + + +"GUI_title" = "GUI"; + +"GUI_description" = "Desactivar la interfaz grafica, agregar GUI=n a com.apple.Boot.plist"; + + + +"EthernetBuiltIn_title" = "EthernetBuiltIn"; + +"EthernetBuiltIn_description" = "Add EthernetBuiltIn=y to com.apple.Boot.plist, This option will add 'built-in' to your ethernet devices."; + + + +"ForceHPET_title" = "ForceHPET"; + +"ForceHPET_description" = "Add ForceHPET=y to com.apple.Boot.plist, This option enables HPET on intel chipsets, for bioses that dont include the option."; + + + +"ForceWake_title" = "ForceWake"; + +"ForceWake_description" = "Force Wake, agregar ForceWake=y a com.apple.Boot.plist, This option enables you to bypass bad sleep images."; + + + +"EHCIacquire_title" = "EHCIadquirir"; + +"EHCIacquire_description" = "Add EHCIacquire=y to com.apple.Boot.plist, This option fixes any EHCI ownership issues due to bad bioses."; + + + +"UHCIreset_title" = "UHCIreset"; + +"UHCIreset_description" = "Add UHCIreset=y to com.apple.Boot.plist, This option will reset UHCI controllers before starting OS X."; + + + +"GraphicsEnabler_title" = "GraphicsEnabler"; + +"GraphicsEnabler_description" = "Add GraphicsEnabler=y to com.apple.Boot.plist, This option will autodetect NVIDIA based GPUs and inject the correct info."; + + + +// Themes + +"Themes_title" = "Temas"; + +"Themes_description" = "Una coleccin de Temas de muestra"; + + + +"Default_title" = "Estandar"; + +"Default_description" = "El tema estandar del booter, incluido aqui para ser personalizado"; + + + +"Big_title" = "Grande"; + +"Big_description" = "Un tema grande para la gente con suerte de monitores grandes"; + + + +"Twilight_title" = "Crepusculo"; + +"Twilight_description" = "Un tema de muestra para todo los fans de Crepusculo"; + + + +"Pinktink_title" = "PinkTink"; + +"Pinktink_description" = "Un tema de muestra con el fondo rosa y Tinkerbell"; + + + +"Msi_netbook_title" = "MSi Netbook"; + +"Msi_netbook_description" = "Tema de muestra de MSi boot logo para tu notebook =)"; + + + +"Bullet_title" = "Bullet"; + +"Bullet_description" = "El tema Bullet de Nosmokingbandit"; + + + +// Extras + +"Extras_title" = "Extras"; + +"Extras_description" = "Una coleccion de adicionales tiles"; + + + +"SMBios_title" = "Anulacion de SMBIOS"; + +"SMBios_description" = "Instalar la anulacion de SMBIOS por defecto smbios.plist en Extra"; + + + +// Kexts + +"Kexts_title" = "Kexts"; + +"Kexts_description" = "Una coleccion de tiles plist solo kexts compatibles con Extra"; + + + +"AHCIPortInjector_title" = "AHCIPuerto"; + +"AHCIPortInjector_description" = "Agregar Ayuda AHCI para los chipsets Intel Southbridge ICH6 - ICH10, JMicron JMB383"; + + + +"IOAHCIBlockStorageInjector_title" = "IOAHCIBlockStorage"; + +"IOAHCIBlockStorageInjector_description" = ""; + + + +"ATAPortInjector_title" = "IntelPIIXATA"; + +"ATAPortInjector_description" = "Agregar Ayuda ATA para los chipsets Intel Southbridge ICH6 - ICH10"; + + + +"JMicronATAInjector_title" = "JMicronATA"; + +"JMicronATAInjector_description" = "Agregar Ayuda JMIcronATA para los chipsets Intel"; + + + +"Disabler_title" = "Disabler"; + +"Disabler_description" = "Disable AppleIntelCPUPowerManagement."; + + + +// Error strings + +"ERROR_BOOTVOL" = "Este software debe ser instalado en el volumen por defecto."; + +"ERROR_INSTALL" = "Este volumen no junta los requerimientos necesarios para esta actualizacion "; + + + +"Newer_Package_Installed_message" = "Una nueva version de Camalen ya ha sido instalada."; + +"Intel_Mac_message" = "Este software no puede ser instalado."; + + \ No newline at end of file Index: branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/.svn/text-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,11 @@ +{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf430 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;} +\vieww22060\viewh18360\viewkind0 +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\f0\b\fs20 \cf0 ESPA\'d1OL\ + +\b0 \ +EA0401\ +Rev. 4/1/09} \ No newline at end of file Index: branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 78 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/Spanish.lproj/Welcome.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 86 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/Spanish.lproj/Welcome.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Spanish.lproj/Welcome.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +375a91b2c5ac48887905550b7e1a3855 +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + + + + + + + + +911 + Index: branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,25 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;} +\margl1440\margr1440\vieww13160\viewh11700\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\ +\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 Programadores: Crazor, Dense, fassl, fxtentacle, iNDi, JrCs, Kabyl, kaitek, mackerintel, mercurysquad, mozodojo, munky, rekursor, Turbo & zef \ +\ +Gracias's a : asereBLN, bumby, cosmolt, dfe, Galaxy, kalyway, Krazubu, netkas, sckevyn, smith@@, THeKiNG, XyZ, blackosx +\b0\fs30 \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural +\cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 81 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/Spanish.lproj/Conclusion.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 89 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/Spanish.lproj/Conclusion.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/Spanish.lproj/Conclusion.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +540089a6b4c9fb8e89bc41f58427d27d +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + + + + + + + + +1092 + Index: branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/Spanish.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,34 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;\red255\green0\blue0;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\pard\ri0\qc + +\fs50 \cf3 Instalaci\'f3n completa! +\b0\fs26 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs18 \cf0 \ +{\field{\*\fldinst{HYPERLINK "http://chameleon.osx86.hu/"}}{\fldrslt +\fs26 http://chameleon.osx86.hu/}} +\fs26 \ +{\field{\*\fldinst{HYPERLINK "http://forum.voodooprojects.org/index.php"}}{\fldrslt http://forum.voodooprojects.org/index.php}} +\b \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/English.lproj/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/English.lproj/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/English.lproj/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 65 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/English.lproj +END +Description.html +K 25 +svn:wc:ra_dav:version-url +V 80 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/English.lproj/Description.html +END +Localizable.strings +K 25 +svn:wc:ra_dav:version-url +V 83 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/English.lproj/Localizable.strings +END +License.rtf +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/English.lproj/License.rtf +END Index: branches/Chimera/package/Resources/English.lproj/.svn/prop-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/English.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/English.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Resources/English.lproj/.svn/entries =================================================================== --- branches/Chimera/package/Resources/English.lproj/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/English.lproj/.svn/entries (revision 850) @@ -0,0 +1,136 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/English.lproj +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Description.html +file + + + + +2011-05-19T21:52:35.000000Z +c8d4b5f686b48eef1e4c8a92596a14b9 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +1577 + +Welcome.rtfd +dir + +Localizable.strings +file + + + + +2011-05-19T21:52:35.000000Z +558bd0caadcd2f5b2867289a952e1ecb +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +7524 + +Conclusion.rtfd +dir + +License.rtf +file + + + + +2011-05-19T21:52:35.000000Z +a599dcf7ec5367f44d5746390adb92f9 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +319 + Index: branches/Chimera/package/Resources/English.lproj/.svn/text-base/Description.html.svn-base =================================================================== --- branches/Chimera/package/Resources/English.lproj/.svn/text-base/Description.html.svn-base (revision 0) +++ branches/Chimera/package/Resources/English.lproj/.svn/text-base/Description.html.svn-base (revision 850) @@ -0,0 +1,29 @@ + + + + + + + + + +

Chameleon is combination of various boot loader components.
It is based on David Elliott's fake EFI implementation added to Apple's boot-132 project.
Chameleon is extended with the following key features:

+
+

New features in Chameleon 2.0

+
+

- Fully customizable GUI to bring some color to the Darwin Bootloader.

+

- Booting retail DVDs by directly loading a ramdisk image without help of additional programs.

+

- Hibernation. Enjoy resuming your Mac OS X with a preview image.

+

- SMBIOS override to modify the factory SMBIOS values.

+

- DSDT override to use a modified fixed DSDT which can solve several issues.

+
+

- Device Property Injection via device-properties string.

+

- hybrid boot0 / boot1h for MBR and GPT partitioned disks.

+

- automatic FSB detection code even for recent AMD CPUs.

+

- Apple Software RAID support.

+
+

For detailed information, visit : http://chameleon.osx86.hu

+ + Index: branches/Chimera/package/Resources/English.lproj/.svn/text-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/English.lproj/.svn/text-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/English.lproj/.svn/text-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,92 @@ +// General +"Chameleon_title" = "Chameleon"; + +"Standard_title" = "Chameleon Standard"; +"Standard_description" = "Install Chameleon"; + +"EnhancedFAT_title" = "Chameleon EFI FAT"; +"EnhancedFAT_description" = "Install Chameleon to EFI System partition FAT32 (Original)"; + +"EnhancedHFS_title" = "Chameleon EFI HFS"; +"EnhancedHFS_description" = "Install Chameleon to EFI System partition HFS (Reformatted if not already HFS)"; + +// Options +"Options_title" = "Options"; +"Options_description" = "Set default options"; + +"GUI_title" = "GUI"; +"GUI_description" = "Disable the graphic interface, add GUI=n to com.apple.Boot.plist"; + +"EthernetBuiltIn_title" = "EthernetBuiltIn"; +"EthernetBuiltIn_description" = "Add EthernetBuiltIn=y to com.apple.Boot.plist, This option will add 'built-in' to your ethernet devices."; + +"ForceHPET_title" = "ForceHPET"; +"ForceHPET_description" = "Add ForceHPET=y to com.apple.Boot.plist, This option enables HPET on intel chipsets, for bioses that dont include the option."; + +"ForceWake_title" = "ForceWake"; +"ForceWake_description" = "Add ForceWake=y to com.apple.Boot.plist, This option enables you to bypass bad sleep images."; + +"EHCIacquire_title" = "EHCIacquire"; +"EHCIacquire_description" = "Add EHCIacquire=y to com.apple.Boot.plist, This option fixes any EHCI ownership issues due to bad bioses."; + +"UHCIreset_title" = "UHCIreset"; +"UHCIreset_description" = "Add UHCIreset=y to com.apple.Boot.plist, This option will reset UHCI controllers before starting OS X."; + +"GraphicsEnabler_title" = "GraphicsEnabler"; +"GraphicsEnabler_description" = "Add GraphicsEnabler=y to com.apple.Boot.plist, This option will autodetect NVIDIA based GPUs and inject the correct info."; + +// Themes +"Themes_title" = "Themes"; +"Themes_description" = "A collection of sample themes"; + +"Default_title" = "Standard"; +"Default_description" = "The theme thats embedded inside the booter, included here for you to customise."; + +"Big_title" = "Big"; +"Big_description" = "A theme with a large layout for you lucky people with big monitors"; + +"Twilight_title" = "Twilight"; +"Twilight_description" = "A simple theme for the Twilight fans out there"; + +"Pinktink_title" = "PinkTink"; +"Pinktink_description" = "A simple theme with a pink background and Tinkerbell"; + +"Msi_netbook_title" = "MSi Netbook"; +"Msi_netbook_description" = "A simple MSi boot logo for your MSi netbook =)"; + +"Bullet_title" = "Bullet"; +"Bullet_description" = "The Bullet theme by NoSmokingBandit"; + +// Extras +"Extras_title" = "Extras"; +"Extras_description" = "A collection of useful addons"; + +"SMBios_title" = "SMBIOS Override"; +"SMBios_description" = "Install default SMBIOS overrides smbios.plist into Extra"; + +// Kexts +"Kexts_title" = "Kexts"; +"Kexts_description" = "A collection of useful plist only kexts compatible with Extra"; + +"AHCIPortInjector_title" = "AHCIPort"; +"AHCIPortInjector_description" = "Add AHCI support for Intel Southbridge chipsets ICH6 - ICH10, JMicron JMB383"; + +"IOAHCIBlockStorageInjector_title" = "IOAHCIBlockStorage"; +"IOAHCIBlockStorageInjector_description" = ""; + +"ATAPortInjector_title" = "IntelPIIXATA"; +"ATAPortInjector_description" = "Add ATA support for Intel Southbridge chipsets ICH6 - ICH10"; + +"JMicronATAInjector_title" = "JMicronATA"; +"JMicronATAInjector_description" = "Add JMIcronATA support for Intel chipset"; + +"Disabler_title" = "Disabler"; +"Disabler_description" = "Disable AppleIntelCPUPowerManagement."; + +// Error strings +"ERROR_BOOTVOL" = "This software must be installed on the startup volume."; +"ERROR_INSTALL" = "This volume does not meet the requirements for this update."; + +"Newer_Package_Installed_message" = "A newer version of Chameleon is already installed"; +"Intel_Mac_message" = "This software cannot be installed on this computer."; + \ No newline at end of file Index: branches/Chimera/package/Resources/English.lproj/.svn/text-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/English.lproj/.svn/text-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/English.lproj/.svn/text-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,11 @@ +{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf430 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;} +\vieww22060\viewh18360\viewkind0 +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\f0\b\fs20 \cf0 ENGLISH\ + +\b0 \ +EA0401\ +Rev. 4/1/09} \ No newline at end of file Index: branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 78 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/English.lproj/Welcome.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 86 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/English.lproj/Welcome.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/English.lproj/Welcome.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +fb3022976a134b5716654c1e0270c21b +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + + + + + + + + +908 + Index: branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/English.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,26 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE% +\fs26 \cf0 \ +\pard\ri0\ql\qnatural +\cf0 \ +Developers: Crazor, Dense, fassl, fxtentacle, iNDi, JrCs, Kabyl, kaitek, mackerintel, mercurysquad, mozodojo, munky, rekursor, Turbo & zef \ +\ +\ +Thanks to : asereBLN, bumby, cosmolt, dfe, Galaxy, kalyway, Krazubu, netkas, sckevyn, smith@@, THeKiNG, XyZ, blackosx\ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 81 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/English.lproj/Conclusion.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 89 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/English.lproj/Conclusion.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/English.lproj/Conclusion.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +6a5284672babf73ef3a0e1057cc081ab +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + + + + + + + + +1090 + Index: branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/English.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,34 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;\red255\green0\blue0;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\pard\ri0\qc + +\fs50 \cf3 Installation Complete! +\b0\fs26 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs18 \cf0 \ +{\field{\*\fldinst{HYPERLINK "http://chameleon.osx86.hu/"}}{\fldrslt +\fs26 http://chameleon.osx86.hu/}} +\fs26 \ +{\field{\*\fldinst{HYPERLINK "http://forum.voodooprojects.org/index.php"}}{\fldrslt http://forum.voodooprojects.org/index.php}} +\b \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/German.lproj/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/German.lproj/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/German.lproj/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 64 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/German.lproj +END +Description.html +K 25 +svn:wc:ra_dav:version-url +V 79 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/German.lproj/Description.html +END +Localizable.strings +K 25 +svn:wc:ra_dav:version-url +V 82 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/German.lproj/Localizable.strings +END +License.rtf +K 25 +svn:wc:ra_dav:version-url +V 74 +/svn/chameleon/!svn/ver/1/trunk/package/Resources/German.lproj/License.rtf +END Index: branches/Chimera/package/Resources/German.lproj/.svn/prop-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/German.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/German.lproj/.svn/prop-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Resources/German.lproj/.svn/entries =================================================================== --- branches/Chimera/package/Resources/German.lproj/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/German.lproj/.svn/entries (revision 850) @@ -0,0 +1,136 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/German.lproj +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Description.html +file + + + + +2011-05-19T21:52:35.000000Z +06d360a12a6fdc9bacbdf3d363c16643 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +1727 + +Welcome.rtfd +dir + +Localizable.strings +file + + + + +2011-05-19T21:52:35.000000Z +2089e1863a660efdbd1687ff3d761c2b +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +7010 + +Conclusion.rtfd +dir + +License.rtf +file + + + + +2011-05-19T21:52:35.000000Z +712e3a5564f9e91444e43e83969f38f4 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +447 + Index: branches/Chimera/package/Resources/German.lproj/.svn/text-base/Description.html.svn-base =================================================================== --- branches/Chimera/package/Resources/German.lproj/.svn/text-base/Description.html.svn-base (revision 0) +++ branches/Chimera/package/Resources/German.lproj/.svn/text-base/Description.html.svn-base (revision 850) @@ -0,0 +1,29 @@ + + + + + + + + + +

Chameleon ist eine Kombination verschiedener Bootloader Komponenten.
Als Basis diente David Elliott's fake EFI Implementierung die zu Apple's boot-132 Projekt hinzugefügt wurde.
Chameleon wurde mit folgenden Hauptmerkmalen erweitert:

+
+

Neue Funktionen in Chameleon 2.0

+
+

- Vollständig anpassbare GUI um etwas Farbe in den Darwin Bootloader zu bringen.

+

- Starten von retail DVDs durch direktes Laden eines RAM-Disk Images, ohne zusätzliche Programme zu benötigen .

+

- Ruhezustand. Genießt Mac OS X mit einem Vorschau-Bild aufzuwecken.

+

- SMBIOS Override um vorgegebene SMBIOS Werte anzupassen.

+

- DSDT Override um eine angepasste DSDT, die verschiedene Probleme beheben kann, zu laden.

+
+

- Device Property Injection über device-properties string.

+

- hybrider boot0 / boot1h für MBR und GPT partitionierte Festplatten.

+

- Code zur automatischen FSB Erkennung, selbst für AMD CPUs.

+

- Apple Software RAID Unterstützung.

+
+

Für weitere Informationen besuche: http://chameleon.osx86.hu

+ + \ No newline at end of file Index: branches/Chimera/package/Resources/German.lproj/.svn/text-base/Localizable.strings.svn-base =================================================================== --- branches/Chimera/package/Resources/German.lproj/.svn/text-base/Localizable.strings.svn-base (revision 0) +++ branches/Chimera/package/Resources/German.lproj/.svn/text-base/Localizable.strings.svn-base (revision 850) @@ -0,0 +1,91 @@ +// General +"Chameleon_title" = "Chameleon"; + +"Standard_title" = "Chameleon Standard"; +"Standard_description" = "Installiere Chameleon"; + +"EnhancedFAT_title" = "Chameleon EFI FAT"; +"EnhancedFAT_description" = "Installiere Chameleon auf die EFI System partition FAT32 (Original)"; + +"EnhancedHFS_title" = "Chameleon EFI HFS"; +"EnhancedHFS_description" = "Installiere Chameleon auf die EFI System partition HFS (wird neu formatiert falls noch nicht HFS)"; + +// Options +"Options_title" = "Optionen"; +"Options_description" = "Standard Optionen festlegen"; + +"GUI_title" = "GUI"; +"GUI_description" = "Graphische Oberflche deaktivieren, fge GUI=n in die Datei com.apple.Boot.plist ein"; + +"EthernetBuiltIn_title" = "EthernetBuiltIn"; +"EthernetBuiltIn_description" = "Add EthernetBuiltIn=y to com.apple.Boot.plist, This option will add 'built-in' to your ethernet devices."; + +"ForceHPET_title" = "ForceHPET"; +"ForceHPET_description" = "Add ForceHPET=y to com.apple.Boot.plist, This option enables HPET on intel chipsets, for bioses that dont include the option."; + +"ForceWake_title" = "ForceWake"; +"ForceWake_description" = "Aufwachen erzwingen, fge ForceWake=y in die Datei com.apple.Boot.plist ein"; + +"EHCIacquire_title" = "EHCIacquire"; +"EHCIacquire_description" = ""; + +"UHCIreset_title" = "UHCIreset"; +"UHCIreset_description" = ""; + +"GraphicsEnabler_title" = "GraphicsEnabler"; +"GraphicsEnabler_description" = "Add GraphicsEnabler=y to com.apple.Boot.plist, This option will autodetect NVIDIA based GPUs and inject the correct info."; + +// Themes +"Themes_title" = "Oberflchen"; +"Themes_description" = "Eine Sammlung von Beispiel Oberflchen"; + +"Default_title" = "Standard"; +"Default_description" = "Die in Chameleon eingebettete Oberflche, als Beispiel zum Anpassen."; + +"Big_title" = "Big"; +"Big_description" = "Eine gro gehaltene Oberflche, fr die glcklichen unter euch mit groen Bildschirmen"; + +"Twilight_title" = "Twilight"; +"Twilight_description" = ""; + +"Twilight_title" = "Twilight"; +"Twilight_description" = ""; + +"Pinktink_title" = "PinkTink"; +"Pinktink_description" = ""; + +"Msi_netbook_title" = "MSi Netbook"; +"Msi_netbook_description" = ""; + +// Extras +"Extras_title" = "Extras"; +"Extras_description" = "Eine Sammlung ntzlicher Erweiterungen"; + +"SMBios_title" = "SMBIOS Override"; +"SMBios_description" = "Installiere Standard SMBIOS Overrides smbios.plist nach 'Extra'"; + +// Kexts +"Kexts_title" = "Kexte"; +"Kexts_description" = "Eine Sammlung ntzlicher plist-only Kexte, nutzbar im 'Extra' Ordner"; + +"AHCIPortInjector_title" = "AHCIPort"; +"AHCIPortInjector_description" = "AHCI Untersttzung fr Intel Southbridge Chipstze ICH6 - ICH10, JMicron JMB383"; + +"IOAHCIBlockStorageInjector_title" = "IOAHCIBlockStorage"; +"IOAHCIBlockStorageInjector_description" = ""; + +"ATAPortInjector_title" = "IntelPIIXATA"; +"ATAPortInjector_description" = "ATA Untersttzung fr Intel Southbridge Chipstze ICH6 - ICH10"; + +"JMicronATAInjector_title" = "JMicronATA"; +"JMicronATAInjector_description" = "Add JMIcronATA support for Intel chipset"; + +"Disabler_title" = "Disabler"; +"Disabler_description" = "Disable AppleIntelCPUPowerManagement."; + +// Error strings +"ERROR_BOOTVOL" = "Diese Software muss auf dem Startlaufwerk installiert werden."; +"ERROR_INSTALL" = "Dieses Laufwerk ist nicht fr dieses Update geiignet."; + +"Newer_Package_Installed_message" = "Es ist bereits eine neuere Version dieses Pakets installiert."; +"Intel_Mac_message" = "Diese Software kann auf diesem Computer nicht installiert werden."; Index: branches/Chimera/package/Resources/German.lproj/.svn/text-base/License.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/German.lproj/.svn/text-base/License.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/German.lproj/.svn/text-base/License.rtf.svn-base (revision 850) @@ -0,0 +1,13 @@ +{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf430 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;} +\vieww9000\viewh8400\viewkind0 +\deftab720 +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardeftab720\ql\qnatural + +\f0\b\fs20 \cf0 DEUTSCH\ +\ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\b0 \cf0 EA0401\ +Rev. 4/1/09} \ No newline at end of file Index: branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/German.lproj/Welcome.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 85 +/svn/chameleon/!svn/ver/259/trunk/package/Resources/German.lproj/Welcome.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/German.lproj/Welcome.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +8ab930a0bc47807aa668f660c2d74be7 +2010-07-26T07:05:10.392792Z +259 +blackosx + + + + + + + + + + + + + + + + + + + + + +905 + Index: branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/German.lproj/Welcome.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,27 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\ +Entwickler: Crazor, Dense, fassl, fxtentacle, iNDi, JrCs, Kabyl, kaitek, mackerintel, mercurysquad, mozodojo, munky, rekursor, Turbo & zef \ +\ +\ +Dank : asereBLN, bumby, cosmolt, dfe, Galaxy, kalyway, Krazubu, netkas, sckevyn, smith@@, THeKiNG, XyZ, blackosx\ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 80 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/German.lproj/Conclusion.rtfd +END +TXT.rtf +K 25 +svn:wc:ra_dav:version-url +V 88 +/svn/chameleon/!svn/ver/260/trunk/package/Resources/German.lproj/Conclusion.rtfd/TXT.rtf +END Index: branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/entries =================================================================== --- branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/entries (revision 0) +++ branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Resources/German.lproj/Conclusion.rtfd +http://forge.voodooprojects.org/svn/chameleon + + + +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +TXT.rtf +file + + + + +2011-05-19T21:52:35.000000Z +0354561c2a4e43407775f183751e550f +2010-07-26T07:18:22.080162Z +260 +blackosx + + + + + + + + + + + + + + + + + + + + + +1095 + Index: branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base =================================================================== --- branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 0) +++ branches/Chimera/package/Resources/German.lproj/Conclusion.rtfd/.svn/text-base/TXT.rtf.svn-base (revision 850) @@ -0,0 +1,34 @@ +{\rtf1\ansi\ansicpg1252\cocoartf1038\cocoasubrtf320 +{\fonttbl\f0\fnil\fcharset0 LucidaGrande;} +{\colortbl;\red255\green255\blue255;\red65\green78\blue255;\red255\green0\blue0;} +\margl1440\margr1440\vieww11660\viewh12980\viewkind0 +\pard\ri0\qc + +\f0\b\fs72 \cf0 Chameleon +\fs50 \ + +\fs26 v%CHAMELEONVERSION% r%CHAMELEONREVISION% +\fs50 \ +\ +\cf2 %CHAMELEONSTAGE%\cf0 \ +\pard\ri0\ql\qnatural + +\fs26 \cf0 \ +\pard\ri0\qc + +\fs50 \cf3 Installation abgeschlossen! +\b0\fs26 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs18 \cf0 \ +{\field{\*\fldinst{HYPERLINK "http://chameleon.osx86.hu/"}}{\fldrslt +\fs26 http://chameleon.osx86.hu/}} +\fs26 \ +{\field{\*\fldinst{HYPERLINK "http://forum.voodooprojects.org/index.php"}}{\fldrslt http://forum.voodooprojects.org/index.php}} +\b \ +\pard\tx360\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural\pardirnatural + +\b0\fs30 \cf0 \ +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\ql\qnatural + +\fs26 \cf0 Copyright \'a9 2010} \ No newline at end of file Index: branches/Chimera/package/Kexts/Disabler.kext/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 59 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/Disabler.kext +END Index: branches/Chimera/package/Kexts/Disabler.kext/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/.svn/entries (revision 850) @@ -0,0 +1,31 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/Disabler.kext +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Contents +dir + Index: branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 74 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/Disabler.kext/Contents/MacOS +END +Disabler +K 25 +svn:wc:ra_dav:version-url +V 83 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/Disabler.kext/Contents/MacOS/Disabler +END Index: branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/prop-base/Disabler.svn-base =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/prop-base/Disabler.svn-base (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/prop-base/Disabler.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/Disabler.kext/Contents/MacOS +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Disabler +file + + + + +2011-05-19T21:52:35.000000Z +f381b35eda115d0360badfe6fda79942 +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +24644 + Index: branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/text-base/Disabler.svn-base =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/text-base/Disabler.svn-base (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/Contents/MacOS/.svn/text-base/Disabler.svn-base (revision 850) @@ -0,0 +1,37 @@ + ` H __text__TEXT .__const__TEXT <h +C__constructor__TEXT\ __destructor__TEXT` __cstring__TEXTd  __data__DATA0 __common__DATAH \'T8@n1YM>" PUS]E $D$ [ÐUS]E $D$ [ÐUS] $؃[US] $x؃[US] $X$D$PH؃[UH US]TD$ PD$d$D$ [ÐUS]TD$ PD$d$D$[ÐUS]D$H $ $H ؃[US$P{1t +$؃[ÐUS]D$H $H $H 6؃[U]Ãut $H t +$H ]uÐUS]$؃[UU1pUS]$؃[U]] uu\$4$`u +t] ]uu]uU]] uu\$4$u +t] ]uu]upbrH >RDisablerrnet.osrom.kext.Disabler1.0.1v( +n^M2( +*  + +v +f +aZT +L3+' +' +u + + +|d +\E= + + + +84x ,& (% $$ # " !   c b a ` _    H  # "    !          | x t p  l h d ` \ X T P L H D @ <} 8 4| 0 , ( $    {       z                               | x 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\ No newline at end of file Index: branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 68 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/Disabler.kext/Contents +END +Info.plist +K 25 +svn:wc:ra_dav:version-url +V 79 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/Disabler.kext/Contents/Info.plist +END Index: branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/entries (revision 850) @@ -0,0 +1,65 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/Disabler.kext/Contents +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +MacOS +dir + +Info.plist +file + + + + +2011-05-19T21:52:35.000000Z +89057a1f49ba169ac610836bc02e4116 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +1371 + Index: branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/text-base/Info.plist.svn-base =================================================================== --- branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 0) +++ branches/Chimera/package/Kexts/Disabler.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 850) @@ -0,0 +1,47 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleExecutable + Disabler + CFBundleGetInfoString + Kernel Extension Disabler 1.0.1, Copyright © 2008 by Kabyl + CFBundleIdentifier + net.osrom.kext.Disabler + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + Kernel Extension Disabler + CFBundlePackageType + KEXT + CFBundleVersion + 1.0.1 + IOKitPersonalities + + IntelCPUPMDisabler + + CFBundleIdentifier + net.osrom.kext.Disabler + IOClass + Disabler + IOMatchCategory + AppleIntelCPUPowerManagement + IOProbeScore + 1000 + IOProviderClass + IOResources + IOResourceMatch + IOKit + + + OSBundleLibraries + + com.apple.kernel.iokit + 1.1 + + OSBundleRequired + Root + + Index: branches/Chimera/package/Kexts/JMicronATAInjector.kext/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/JMicronATAInjector.kext/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/JMicronATAInjector.kext/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 69 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/JMicronATAInjector.kext +END Index: branches/Chimera/package/Kexts/JMicronATAInjector.kext/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/JMicronATAInjector.kext/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/JMicronATAInjector.kext/.svn/entries (revision 850) @@ -0,0 +1,31 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/JMicronATAInjector.kext +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Contents +dir + Index: branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 78 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/JMicronATAInjector.kext/Contents +END +Info.plist +K 25 +svn:wc:ra_dav:version-url +V 89 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/JMicronATAInjector.kext/Contents/Info.plist +END Index: branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/JMicronATAInjector.kext/Contents +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Info.plist +file + + + + +2011-05-19T21:52:35.000000Z +6b4c6250ff9dce5ccb8ee663d7d0bbe4 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +1562 + Index: branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/text-base/Info.plist.svn-base =================================================================== --- branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 0) +++ branches/Chimera/package/Kexts/JMicronATAInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 850) @@ -0,0 +1,53 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleIdentifier + org.chameleon.plist.JMicronATAInjector + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + JMicron ATA Injector + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleVersion + 1.0.0 + IOKitPersonalities + + JMicronATA Driver + + CFBundleIdentifier + com.jmicron.JMicronATA + Hardware Vendor + JMicron + IOClass + JMicronATA + IOProviderClass + JMicronATAChannel + + JMicronATA PCI + + CFBundleIdentifier + com.jmicron.JMicronATA + Hardware Vendor + JMicron + IOClass + JMicronATAPCIRoot + IOPCIClassMatch + 0x01010000&0xffff0000 + IOPCIPrimaryMatch + 0x2368197b 0x2360197b&0xfff0ffff + IOProbeScore + 12000 + IOProviderClass + IOPCIDevice + + + OSBundleRequired + Local-Root + + Index: branches/Chimera/package/Kexts/AHCIPortInjector.kext/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/AHCIPortInjector.kext/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/AHCIPortInjector.kext/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 67 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/AHCIPortInjector.kext +END Index: branches/Chimera/package/Kexts/AHCIPortInjector.kext/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/AHCIPortInjector.kext/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/AHCIPortInjector.kext/.svn/entries (revision 850) @@ -0,0 +1,31 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/AHCIPortInjector.kext +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Contents +dir + Index: branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 76 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/AHCIPortInjector.kext/Contents +END +Info.plist +K 25 +svn:wc:ra_dav:version-url +V 87 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/AHCIPortInjector.kext/Contents/Info.plist +END Index: branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/AHCIPortInjector.kext/Contents +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Info.plist +file + + + + +2011-05-19T21:52:35.000000Z +b4d2dcc8c6a5563a98afe389008c1da9 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +10614 + Index: branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/text-base/Info.plist.svn-base =================================================================== --- branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 0) +++ branches/Chimera/package/Kexts/AHCIPortInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 850) @@ -0,0 +1,382 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleIdentifier + org.chameleon.plist.AHCIPortInjector + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + AHCI Chipsets Injector + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleVersion + 1.0.0 + IOKitPersonalities + + GenericAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + AHCI Standard Controller + IOClass + AppleAHCI + IOPCIClassMatch + 0x01060100&0xffffff00 + IOProbeScore + 800 + IOProviderClass + IOPCIDevice + Vendor Name + Unknown + + JMicronAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + JMB36x AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x2360197b&0xfff0ffff + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + JMicron + + ICH6 ESB2 AHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ESB2 AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x26818086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH7MAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH7-M AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x27c58086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH7MRAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH7-M RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x27c68086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH7RAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH7-R AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x27c18086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH7RRAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH7-R RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x27c38086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH8AHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH8 AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x28248086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH8MAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH8-M AHCI + IOClass + AppleICH8AHCI + IOPCIPrimaryMatch + 0x28298086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH8MRAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH8-M RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x282a8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH8RAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH8-R AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x28218086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH8RRAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH8-R RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x28228086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH9AHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH9 AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x29238086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH9MAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH9-M AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x29298086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH9MRAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH9-M RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x292c8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH9RAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH9-R AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x29228086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH9RRAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH9-R RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x29258086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH10AHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH10 AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x3A028086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH10RAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH10 RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x3A058086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH10RAHCI + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH10-R AHCI + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x3A228086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + ICH10RRAID + + CFBundleIdentifier + com.apple.driver.AppleAHCIPort + Chipset Name + ICH10-R RAID + IOClass + AppleAHCI + IOPCIPrimaryMatch + 0x3A258086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Vendor Name + Intel + + + OSBundleRequired + Local-Root + + Index: branches/Chimera/package/Kexts/ATAPortInjector.kext/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/ATAPortInjector.kext/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/ATAPortInjector.kext/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 66 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/ATAPortInjector.kext +END Index: branches/Chimera/package/Kexts/ATAPortInjector.kext/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/ATAPortInjector.kext/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/ATAPortInjector.kext/.svn/entries (revision 850) @@ -0,0 +1,31 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/ATAPortInjector.kext +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Contents +dir + Index: branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 75 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/ATAPortInjector.kext/Contents +END +Info.plist +K 25 +svn:wc:ra_dav:version-url +V 86 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/ATAPortInjector.kext/Contents/Info.plist +END Index: branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/ATAPortInjector.kext/Contents +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Info.plist +file + + + + +2011-05-19T21:52:35.000000Z +2363cce9211614418b4c21a82a334b24 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +17780 + Index: branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/text-base/Info.plist.svn-base =================================================================== --- branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 0) +++ branches/Chimera/package/Kexts/ATAPortInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 850) @@ -0,0 +1,596 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleIdentifier + org.chameleon.plist.ATAPortInjector + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + ATA Chipsets Injector + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleVersion + 1.0.0 + IOKitPersonalities + + ESB2 ATA/100 + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ESB2 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x269e8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ESB2 Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ESB2 SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x26808086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x24118086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x1f061d + + ICH0 ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH0 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x24218086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x07061d + + ICH2 ATA/100 Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH2 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x244A8086 0x244B8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ICH2 ATA/66 Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH2 ATA/66 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x24418086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x1f061d + + ICH3 ATA/100 Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH3 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x248A8086 0x248B8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ICH3 ATA/66 Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH3 ATA/66 + IOClass + AppleIntelPIIXATARoot + IOPCIClassMatch + 0x01010000&0xffff0000 + IOPCIPrimaryMatch + 0x24818086 0x24008086&0xff00ffff + IOProbeScore + 1800 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x1f061d + + ICH4 ATA/100 Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH4 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x24CB8086 0x24CA8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ICH5 ATA/100 Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH5 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x24DB8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ICH5 Serial ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH5 SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x24D18086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH6 ATA/100 Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH6 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x266f8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ICH6 Serial ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH6 SATA + IOClass + AppleIntelPIIXATARoot + IOPCIClassMatch + 0x01010000&0xffff0000 + IOPCIPrimaryMatch + 0x26528086 0x26518086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH6-M Serial ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH6-M SATA + IOClass + AppleIntelPIIXATARoot + IOPCIClassMatch + 0x01010000&0xffff0000 + IOPCIPrimaryMatch + 0x26538086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH7 ATA/100 + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH7 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x27df8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ICH7 Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH7 SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x27c08086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH7-M Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH7-M SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x27c48086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH8 2 Port Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH8 2 Port SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x28258086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH8 ATA/100 + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH8 ATA/100 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x28508086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x3f061d + + ICH8 Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH8 SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x28208086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH8-M Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH8-M SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x28288086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH9 2 Port Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH9 2PTS SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x29218086 0x29268086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH9 Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH9 SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x29208086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH9-M Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH9-M SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x29288086 0x292d8086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH10 2 Port Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH10 2PTS SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x3a068086 0x3a268086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + ICH10 Serial ATA + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + ICH10 SATA + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x3a008086 0x3a208086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + PCS Port Map + kgGTAZICkwKSBJMEkgiTCA== + Serial ATA + + Supported Transfer Modes + 0x3f061d + + PIIX ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + PIIX + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x12308086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Shared Channel Timings + + Supported Transfer Modes + 0x00061d + + PIIX3 ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + PIIX3 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x70108086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x00061d + + PIIX4 ATA Controller + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + Controller Name + PIIX4 + IOClass + AppleIntelPIIXATARoot + IOPCIPrimaryMatch + 0x71118086 + IOProbeScore + 2000 + IOProviderClass + IOPCIDevice + Supported Transfer Modes + 0x07061d + + Parallel ATA Channel Driver + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + IOClass + AppleIntelPIIXPATA + IOProbeScore + 800 + IOProviderClass + AppleIntelPIIXATAChannel + Serial ATA + + + Serial ATA Channel Driver + + CFBundleIdentifier + com.apple.driver.AppleIntelPIIXATA + IOClass + AppleIntelICHxSATA + IOProbeScore + 1000 + IOProviderClass + AppleIntelPIIXATAChannel + Serial ATA + + + + OSBundleRequired + Local-Root + + Index: branches/Chimera/package/Kexts/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 45 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts +END Index: branches/Chimera/package/Kexts/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/.svn/entries (revision 850) @@ -0,0 +1,43 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Disabler.kext +dir + +JMicronATAInjector.kext +dir + +AHCIPortInjector.kext +dir + +ATAPortInjector.kext +dir + +IOAHCIBlockStorageInjector.kext +dir + Index: branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/.svn/all-wcprops (revision 850) @@ -0,0 +1,5 @@ +K 25 +svn:wc:ra_dav:version-url +V 77 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/IOAHCIBlockStorageInjector.kext +END Index: branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/.svn/entries (revision 850) @@ -0,0 +1,31 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/IOAHCIBlockStorageInjector.kext +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Contents +dir + Index: branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/all-wcprops =================================================================== --- branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/all-wcprops (revision 0) +++ branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/all-wcprops (revision 850) @@ -0,0 +1,11 @@ +K 25 +svn:wc:ra_dav:version-url +V 86 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents +END +Info.plist +K 25 +svn:wc:ra_dav:version-url +V 97 +/svn/chameleon/!svn/ver/1/trunk/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/Info.plist +END Index: branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/entries =================================================================== --- branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/entries (revision 0) +++ branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/entries (revision 850) @@ -0,0 +1,62 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Info.plist +file + + + + +2011-05-19T21:52:35.000000Z +3ea2ee4d6f71057aa1bd3e61cad6c898 +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + + + + + + + + +1397 + Index: branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/text-base/Info.plist.svn-base =================================================================== --- branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 0) +++ branches/Chimera/package/Kexts/IOAHCIBlockStorageInjector.kext/Contents/.svn/text-base/Info.plist.svn-base (revision 850) @@ -0,0 +1,47 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleIdentifier + org.chameleon.plist.IOAHCIBlockStorageInjector + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + IOAHCIBlockStorage Fix + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleVersion + 1.1.1 + IOKitPersonalities + + AppleAHCIDiskDriver + + CFBundleIdentifier + com.apple.iokit.IOAHCIBlockStorage + IOClass + AppleAHCIDiskDriver + IOProviderClass + IOAHCIDevice + IOProbeScore + 1000 + Physical Interconnect + SATA + Physical Interconnect Location + Internal + Protocol Characteristics + + Physical Interconnect + SATA + Physical Interconnect Location + Internal + + + + OSBundleRequired + Local-Root + + Index: branches/Chimera/doc/archive/.svn/all-wcprops =================================================================== --- branches/Chimera/doc/archive/.svn/all-wcprops (revision 0) +++ branches/Chimera/doc/archive/.svn/all-wcprops (revision 850) @@ -0,0 +1,23 @@ +K 25 +svn:wc:ra_dav:version-url +V 43 +/svn/chameleon/!svn/ver/1/trunk/doc/archive +END +Users_Guide0.4.pdf +K 25 +svn:wc:ra_dav:version-url +V 62 +/svn/chameleon/!svn/ver/1/trunk/doc/archive/Users_Guide0.4.pdf +END +UsersGuide-v0.2.pdf +K 25 +svn:wc:ra_dav:version-url +V 63 +/svn/chameleon/!svn/ver/1/trunk/doc/archive/UsersGuide-v0.2.pdf +END +Users_Guide_v0.3.pdf +K 25 +svn:wc:ra_dav:version-url +V 64 +/svn/chameleon/!svn/ver/1/trunk/doc/archive/Users_Guide_v0.3.pdf +END Index: branches/Chimera/doc/archive/.svn/prop-base/Users_Guide0.4.pdf.svn-base =================================================================== --- branches/Chimera/doc/archive/.svn/prop-base/Users_Guide0.4.pdf.svn-base (revision 0) +++ branches/Chimera/doc/archive/.svn/prop-base/Users_Guide0.4.pdf.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/doc/archive/.svn/prop-base/UsersGuide-v0.2.pdf.svn-base =================================================================== --- branches/Chimera/doc/archive/.svn/prop-base/UsersGuide-v0.2.pdf.svn-base (revision 0) +++ branches/Chimera/doc/archive/.svn/prop-base/UsersGuide-v0.2.pdf.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/doc/archive/.svn/prop-base/Users_Guide_v0.3.pdf.svn-base =================================================================== --- branches/Chimera/doc/archive/.svn/prop-base/Users_Guide_v0.3.pdf.svn-base (revision 0) +++ branches/Chimera/doc/archive/.svn/prop-base/Users_Guide_v0.3.pdf.svn-base (revision 850) @@ -0,0 +1,5 @@ +K 13 +svn:mime-type +V 24 +application/octet-stream +END Index: branches/Chimera/doc/archive/.svn/entries =================================================================== --- branches/Chimera/doc/archive/.svn/entries (revision 0) +++ branches/Chimera/doc/archive/.svn/entries (revision 850) @@ -0,0 +1,130 @@ +10 + +dir +833 +http://forge.voodooprojects.org/svn/chameleon/trunk/doc/archive +http://forge.voodooprojects.org/svn/chameleon + + + +2010-01-14T01:05:41.527170Z +1 +zef + + + + + + + + + + + + + + +b5af796a-00a8-11df-919b-ffff7a100b7d + +Users_Guide0.4.pdf +file + + + + +2011-05-19T21:52:30.000000Z +41bcc59dad88594872aae77790463b71 +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +335828 + +UsersGuide-v0.2.pdf +file + + + + +2011-05-19T21:52:30.000000Z +328ae988f1b572b13b181d1f61eed13f +2010-01-14T01:05:41.527170Z +1 +zef +has-props + + + + + + + + + + + + + + + + + + + + +595461 + +Users_Guide_v0.3.pdf +file + + + + +2011-05-19T21:52:30.000000Z +437bbf681e9dd5cccac75849258e953b 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U? 1=LZ@ئ`"fd gb LV$ ;0PB 73P9as ;>m +endstream +endobj +79 0 obj +<>stream +h|@e;X!j$@gHH؜w\rXVv7_aIwt===)J@Z"C\c#beKMvL[3[=l+<5h +*5h(DwyO &CwQ*=:1'!'&IJy#$L +endstream +endobj +80 0 obj +<>/Filter/FlateDecode/ID[<6C346CB3122F446A94144E1CEC056EAF>]/Info 171 0 R/Length 267/Root 173 0 R/Size 172/Type/XRef/W[1 3 1]>>stream +hbb&FA$ɾ,b"Y$cM5$D2ȃSʺ>ʟ`fH*L?V +a#{ZH+O"`YpYF 3[ɝ`5L`p̈́"ev1#q˾@ìۉNHz"/L䋥`Hz|QLU80~?d]/i$2JSKdMX`##L1d,> +endstream +endobj +startxref +116 +%%EOF Index: branches/Chimera/doc/.svn/text-base/BootHelp.txt.svn-base =================================================================== --- branches/Chimera/doc/.svn/text-base/BootHelp.txt.svn-base (revision 0) +++ branches/Chimera/doc/.svn/text-base/BootHelp.txt.svn-base (revision 850) @@ -0,0 +1,122 @@ +The boot: prompt waits for you to type advanced startup options. +If you don't type anything, the computer continues starting up normally. It +uses the kernel and configuration files on the startup device, which it also +uses as the root device. + +Advanced startup options use the following syntax: + + [device] [arguments] + +Example arguments include + + device: rd= (e.g. rd=disk0s2) + rd=* (e.g. rd=*/PCI0@0/CHN0@0/@0:1) + + kernel: kernel name (e.g. "mach_kernel" - must be in "/" ) + + flags: -v (verbose) -s (single user mode) + -x (safe mode) -f (ignore caches) + -F (ignore "Kernel Flags" specified in boot configuration file) + + "Graphics Mode"="WIDTHxHEIGHTxDEPTH" (e.g. "1024x768x32") + + kernel flags (e.g. debug=0x144) + io=0xffffffff (defined in IOKit/IOKitDebug.h) + +Example: mach_kernel rd=disk0s1 -v "Graphics Mode"="1920x1200x32" + +If the computer won't start up properly, you may be able to start it up +using safe mode. Type -x to start up in safe mode, which ignores all +cached driver files. + +Special booter hotkeys: + F5 Rescans optical drive. + F10 Scans and displays all BIOS accessible drives. + +Special booter commands: + ?memory Displays information about the computer's memory. + ?video Displays VESA video modes supported by the computer's BIOS. + ?norescan Leaves optical drive rescan mode. + +Additional useful command-line options: + config= Use an alternate Boot.plist file. + +Options useful in the com.apple.Boot.plist file: + Wait=Yes|No Prompt for a key press before starting the kernel. + "Quiet Boot"=Yes|No Use quiet boot mode (no messages or prompt). + Timeout=8 Number of seconds to pause at the boot: prompt. + "Instant Menu"=Yes Force displaying the partition selection menu. + + "Default Partition" Sets the default boot partition, + =hd(x,y)|UUID|"Label" Specified as a disk/partition pair, an UUID, or a + label enclosed in quotes. + + "Hide Partition" Remove unwanted partition(s) from the boot menu. + =partition Specified, possibly multiple times, as hd(x,y), an + [;partition2 ...] UUID or label enclosed in quotes. + + "Rename Partition" Rename partition(s) for the boot menu. + =partition Where partition is hd(x,y), UUID or label enclosed + [;partition2 in quotes. The alias can optionally be quoted too. + ...] + + GUI=No Disable the GUI (enabled by default). + "Boot Banner"=Yes|No Show boot banner in GUI mode (enabled by default). + "Legacy Logo"=Yes|No Use the legacy grey apple logo (disabled by default). + + PciRoot= Use an alternate value for PciRoot (default value 0). + + GraphicsEnabler=Yes|No Automatic device-properties generation for gfx cards. + UseAtiROM=Yes|No Use an alternate Ati ROM image + (path: /Extra/__.rom) + UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image + (path: /Extra/_.rom) + VBIOS=Yes|No Inject VBIOS to device-properties. + + AtiConfig= Use a different card config (the list can be found in ati.c). + + EthernetBuiltIn=Yes|No Automatic "built-in"=yes device-properties generation + for ethernet interfaces. + + USBBusFix=Yes Enable all USB fixes below: + EHCIacquire=Yes Enable the EHCI fix (disabled by default). + UHCIreset=Yes Enable the UHCI fix (disabled by default). + USBLegacyOff=Yes Enable the USB Legacy fix (disabled by default). + + ForceHPET=Yes|No Force Enable HPET. + + Wake=No Disable wake up after hibernation (default: enabled). + ForceWake=Yes Force using the sleepimage (disabled by default). + WakeImage= Use an alternate sleepimage file. + (default path is /private/var/vm/sleepimage). + + DropSSDT=Yes Skip the SSDT tables while relocating the ACPI tables. + DSDT= Use an alternate DSDT.aml file + (default paths: + /DSDT.aml /Extra/DSDT.aml bt(0,0)/Extra/DSDT.aml). + + GenerateCStates=Yes Enable auto generation of Processor (C-States) and/or + GeneratePStates=Yes Performance (P-States) power states. + + EnableC2State=Yes Enable specific Processor power states, C2, + EnableC3State=Yes C3 + EnableC4State=Yes and C4. + + SMBIOS= Use an alternate SMBIOS.plist file + (default paths: + /Extra/SMBIOS.plist bt(0,0)/Extra/SMBIOS.plist). + + SMBIOSdefaults=No Don't use the Default values for SMBIOS overriding + if smbios.plist doesn't exist, factory + values are kept. + + "Scan Single Drive" Scan the drive only where the booter got loaded from. + =Yes|No Fix rescan pbs when using a DVD reader in AHCI mode. + Rescan=Yes Enable CD-ROM rescan mode. + "Rescan Prompt"=Yes Prompts for enable CD-ROM rescan mode. + SystemId= Set manually the system id UUID, + SMUUID in smbios config (reserved field) isn't used. + SystemType= Set the system type where n is between 0..6 + (default =1 (Desktop) + md0= Load raw img file into memory for use as XNU's md0 + ramdisk. /Extra/Postboot.img is used otherwise. Index: branches/Chimera/doc/.svn/text-base/README.svn-base =================================================================== --- branches/Chimera/doc/.svn/text-base/README.svn-base (revision 0) +++ branches/Chimera/doc/.svn/text-base/README.svn-base (revision 850) @@ -0,0 +1,87 @@ + + Chameleon Boot Loader + ===================== + + What is it? + ----------- + + Chameleon is combination of various boot loader components. It is based + on David Elliott's fake EFI implementation added to Apple's boot-132 + project. Chameleon is extended with the following key features: + + + Features + -------- + + - Device Property Injection via device-properties string in com.apple.Boot.plist + - hybrid boot0+boot1h loaders for both MBR and GPT partitioned disks. + - automatic FSB detection code even for recent AMD CPUs. + - Apple Software RAID support. + - stage2 loader (boot) can be placed as a regular file in the boot + partition's root folder. + + + Installation + ============ + + Normal Install (non-RAID): + -------------------------- + + Suppose that your installation is on /dev/disk0s2 + + - Install boot0 to the MBR: + sudo ./fdisk440 -f boot0 -u -y /dev/rdisk0 + + - Install boot1h to the partition's bootsector: + sudo dd if=boot1h of=/dev/rdisk0s2 + + - Install boot to the partition's root directory: + sudo cp boot / + + No need to use startupfiletool anymore! + + + RAID Install: + ------------- + + Suppose that your installation is on /dev/disk3, which is either a mirror- or a + stripeset consisting of /dev/disk0 and /dev/disk1 + + Mac OS X creates a small helper partition at the end of each RAID member disk, + namely /dev/disk0s3 and /dev/disk1s3 + + - Install boot0 to the MBR of both disks: + sudo ./fdisk440 -f boot0 -u -y /dev/rdisk0 + sudo ./fdisk440 -f boot0 -u -y /dev/rdisk1 + + - Install boot1h to the bootsector of each boot partition: + sudo dd if=boot1h of=/dev/rdisk0s3 + sudo dd if=boot1h of=/dev/rdisk1s3 + + - Install boot to both helper partition's root directories. + diskutil mount disk0s3 + cp boot /Volumes/Boot\ OSX + diskutil unmount disk0s3 + diskutil mount disk1s3 + cp boot /Volumes/Boot\ OSX + diskutil unmount disk1s3 + + Support: + -------- + + If you have any questions, issues etc. feel free to join us + at irc.voodooprojects.org #chameleon + + + Source Code + ----------- + + For downloading the source code please visit the project page at + http://chameleon.osx86.hu + + + Licensing + --------- + + Chameleon is released under the terms and conditions of + Apple Public Source License (see APPLE_LICENSE). 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It is an EFI boot loader that is designed to replace the Darwin and PC_EFI boot loaders. It has several new features including:Graphical User Interface modeCustomizable ImagesSupport for GPT/MBR partition typesRAID supportiVBORw0KGgoAAAANSUhEUgAABAAAAAMACAIAAAA12IJaAAAAGXRFWHRTb2Z0d2FyZQBBZG9iZSBJ +bWFnZVJlYWR5ccllPAABydhJREFUeNrs/WmQZNmVH3b+zzn3vufuseZWmVlZe2FtoFBAA91NtjXZ +UnWTHJFscdE2kmkkcUbkjGnMNF/GZr6MaT7OhzGbxUY2MtkMKaMojc2IklEUF0ndTfRONIAG0I1G +YakqFGqvyj0zItz9vXfvPWc+3OceHpGZ1SDZpDGRJ5DI8vD4uWeEx4vMe+/Z6IUXfx6AmRIxTr6d +vFMBfsCH3Lt37969e/fu3bt3/3D48X0iBnTtNu5cv8vr+927d+/evXv37t27d/+QenrhxZc2tw4P +3jHgvlsN9+7du3fv3r179+7dP0Seq17vEh60jdj4qHv37t27d+/evXv37h9WT7UG4MTuwRQnNwoP +2Gq4d+/evXv37t27d+/+IfN87+4BG6lCY57QSm/uJ9y7d+/evXv37t27d//Q+XUE4FTm0OlEons2 +Ge7du3fv3r179+7du3/4/Lp2+NQe4tSD791kuHfv3r179+7du3fv/uHzTHRv/6BT0QReP6wC9+7d +u3fv3r179+7dP6x+owhYzfAHjQ/YfHPv3r179+7du3fv3v1D5k91AdpE+IPSjNy7d+/evXv37t27 +d/+QeT4ZHcBGhtBm7GB9p7p37969e/fu3bt37/7h9ccRgPUG4kN2EvfdcLh37969e/fu3bt37/5h +8bxZPXDqBu7TWBTu3bt37969e/fu3bt/eD0/aHTwamTA5m1e7Rncu3fv3r179+7du3f/UHr69Gde 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+Hh4eHh4eHt6MXp8nZOw16FlW6PoC8PDw8PDw8PDw8PAm8ywrp7i3DoJehg8LeHh4eHh4eHh4eHiT ++l4HARvCCN278PDw8PDw8PDw8PBm9YaVgAURJymIXeQaY/Dw8PDw8PDw8PDwZvI8NHogXapQzwmG +QqcRhYeHh4eHh4eHh4c3kw/2ABgyh4yJRCFBBjw8PDw8PDw8PDy8+Xxw7LAhhjAcHBpkwMPDw8PD +w8PDw8Obz3PGQucPMvQm8OBhGoCHh4eHh4eHh4eHN6vXDQIWUlLoYII+RhjAw8PDw8PDw8PDw5vL +G2YB0iO6UJoRPDw8PDw8PDw8PLzJfOi6wcEMIX3fQXCngIeHh4eHh4eHh4c3r+/uAQgGEH1EEmED +Dnh4eHh4eHh4eHh4s3iuHz1g2KAwE4sSPDw8PDw8PDw8PLx5Pe9t6eCuJQP027wrZoCHh4eHh4eH +h4eHN6Vnk7OLQzoIjKsGhO1ZgIeHh4eHh4eHh4c3nf//Etp73CXrfDAAAAAASUVORK5CYIJ= +Chameleon can be installed on any BIOS bootable device such as USB flash drives, hard drives, and of course off a cd-rom.Installing ChameleonChameleon 2.0 includes it’s own installer package which will install the required boot loader components as well as the new themes onto a hard drive or other bootable device. Once the install is complete you will need to reboot your computer to use the new boot loader featuresTo get started, double click on the Chameleon Installer.iVBORw0KGgoAAAANSUhEUgAAAnEAAAG6CAIAAADoKIeFAAAB32lDQ1BJQ0MgUHJvZmlsZQAAeAGt +ksFLFHEUx78zErthLGJWRAZDqJjMxjJ7qdtuewhhhUVXzfCy/nbdlZxxmBndig5dunUrOnReJOrW +RS/hHjsUKKJpnfobJImWZfr+5seyHpQuvuHN+/we39+bee/3A3oGS667rAOwncCbfHDfeDj3yIgd +QsNNJq+gtyR8N1so5Lk6w473qabtJmWtT/7e2I2v6deNkVbs1efi1hmbOumExw8CmsnEQFVxRvKC +4qLkeuAG1NQki1qpTH5ONr3iZI78npyoKt6UvKD4i+Q1UZV7D8gpp7zkAHqcfLdc8QU5QxZlX9jk +Btm07RXW17fJo8L1uFf/Qx6Sc2GkPdsHsh9ZM9HNzbwBPqwB12U7RiTD8GPg8m9gc72bOzqIZqVd +jfuLaSvSab0bwIW3YXg0C8RuA+3vYdjaCMP2OtDzA2gei1WPtZVa+8Yf/s9a9az0wA57oEVndDqr +uUSqFNBoAnNcjGeAd/SRa0D/T6BALmagp9MdVzOkFLiYz00kLauueopS5/Oyl1d5TpHJDi5VnOkp +xj76IPLIYQJJWHzqsNTZSe38S+CWvNZo/v31QsaTFlSeRDPJrbhPvaVqLTCyvLkV0xh3xB3TsFKp +e/gHmVWEZApHLZsAAAAJcEhZcwAACxMAAAsTAQCanBgAACAASURBVHgB7L0HgF1Vuf696+lTM5lM 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+CO//k/d96t+cw7U1T9ct97TA/RMXA3dX3FF93+tfT3+RuXug+9vpV/DodtCLvIFAIHCtIwCjsETW +qJRnhxwsZ91n3MDtAmTAQTeRr8zbNipl5wd8WV7XYYoYN5cDrPYHXMDCwWwEByuwOLh12OoNx9jL +PXh0LCyhDAQCgf2DAKOn0YxRAotx9k/fUk+gwMQRWl27zcNuO/BomQAHKHz3/UGiBgso0UGDa5s+ +aI5z8GiORsiBQCCwnxEwstnBAXS/gmUQQTncf+zXPu5gv7Y1KbyD7YiiAoFAIBAIBAKBvYhA8Ohe +PGvR5kAgEAgEAoHdR4Ddj2lE8Ojun4loQSAQCAQCgcCeQwAS5dM9NPsKV3btuQ5HgwOBQCAQCAQC +gZ1CgFeD+LAdX6WlwPBHdwrVKCcQCAQCgUDgQCDgJMrLM3Q4ePRAnPXoZCAQCAQCgcCOIMCH2c0T +hUSHz0dZCL4jRUchgUAgEAgEAoHA/kbggQceeP/73890rpHo8Pno/u5z9C4QCAQCgUAgENgRBCBR +vuL+tre9DRJ98MEHjVApWbtg7EgFUUggEAgEAoFAILBfESiQqE/t0t94PrpfT3r0KxAIBAKBQGBn +EOALB7knCom6V0oF4Y/uDMpRSiAQCAQCgcC+RIAp3HvvvdeJMydRZLocPLovz3t0KhAIBAKBQGAH +EIBEC8RZIFTqKP/ar/3aW97ylh2oLYoIBAKBQCAQCAQOHgL/P+31m0OBwkolAAAAAElFTkSuQmCC +If you see this screen, you’re done with the install and everything has installed. All you need to do now is reboot and watch your computer load the new Chameleon and enjoy the extra features that it has over the previous versions!BootingChameleon is setup to automatically boot your operating system with the default settings but has the ability to pass variables to the kernel. You can pass startup options to the kernel by pressing any key when you see the boot logo and the type them to be sent to the operating system after you hit enter.Advanced OptionsAdvanced startup options use the following syntax: [device]<kernel> [arguments]Example arguments includedevice: rd= device name> rd=*<IODeviceTree path> (Device name sample rd=/dev/disk0s2)(Device tree sample rd=*/PCI0@0/CHN0@0/@0:1)Kernel: Sometimes you need to use a different kernel for testing, or you need to use the old one after an install that didn’t work the way you wanted it too =)kernel: kernel name Example: mach_kernel.voodooFlags allow you pass arguments without having to make them a permanent config settings. Examples of valid flags are:-f This forces rebuilding of extensions cache-sBoots into a single user command line mode-vVerbose, boots in text mode showing all debug info and errors-xBoots into safe mode "Graphics Mode"="1024x768x32" : Tells VESA to boot with this resolution, the x32 is bit depth and is only compatible with VESA 3.0 and uprd=disk0s1: Tells Darwin to boot from a certain partition specified in BSD format. Disk 0 specifies first HDD and s1 specifies first partition as 0 is the MBR.cpus=1: Tells the system how many CPUs or cores to use, useful for Core Duo users.platform=X86PC: Can be used if problems with normal booting, platform=ACPI: another option if normal booting fails-legacy - Boots OS X in 32bit mode rather than 64bit if 64bit is used due to a 64bit processoridehalt=0 - May stop stutteringkernel debug flags (e.g. debug=0x144) io=0xffffffff defined in IOKit/IOKitDebug.h)Example: mach_kernel rd=disk0s1 -v "Graphics Mode"="1024x768x32@85"If the computer won't start up properly, you may be able to start it up using safe mode. Use the startup command “-x” to start up in safe mode, which ignores all cached driver files.Example: -x -vSpecial booter commands: ?memory Displays information about the computer's memory ?video Displays VESA video modes supported by the computer's BIOS. ?norescan Leaves CD-ROM rescan mode.Additional useful command-line options: config=<file> Use an alternate Boot.plist file.Boot.plistOptions useful in the com.apple.Boot.plist file:"Boot Graphics"=Yes|NoUse graphics mode or text mode when starting."Quiet Boot"=Yes|NoUse quiet boot mode (no messages or prompt).Timeout=8Number of seconds to pause at the boot: prompt."Instant Menu"=YesForce displaying the partition selection menu. GUI=NoDisable the GUI (enabled by default).USBBusFix=YesEnable the EHCI and UHCI fixes (disabled by default). EHCIacquire=YesEnable the EHCI fix (disabled by default).UHCIreset=YesEnable the UHCI fix (disabled by default).Wake=NoDisable wake up after hibernation (enabled by default). ForceWake=YesForce using the sleepimage (disabled by default). WakeImage=<file>Use an alternate sleepimage file (default path is /private/var/vm/sleepimage).DropSSDT=YesSkip the SSDT tables while relocating the ACPI tables.DSDT=<file>Use an alternate DSDT.aml file (default paths are /DSDT.aml or /Extra/DSDT.aml).Rescan=YesEnable CD-ROM rescan mode."Rescan Prompt"=YesPrompts for enable CD-ROM rescan mode.ThemesChameleon 2 lets you create or customize the boot loader themes! You can edit the file in /Extra/Themes/Default/theme.plist. The following variables are changeable in the theme.plist to customize your theme.Images and ColorChameleon 2 has user replaceable images, and colors that you can customize. The images are saved in the /Extra/Themes/Default folder. All images must be in .png format .You can change the color of all the text and other widgets by using RGB color codes. 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+GYCuJEVABERABERAAqw6IAIiIAIiIAIZICABzgB0JSkCIiACIiACEmDVAREQAREQARHIAIH/Dz93 +dVWwJbMUAAAAAElFTkSuQmCC +The Chameleon screen layoutBackground Set the position of background.png within the screenbackground_pos_x<key>background_pos_x</key><string>-0</string>0 pixels from reverse origin along the x axisbackground_pos_y <key>background_pos_y</key><string>-0</string>0 pixels from reverse origin along the y axisLogoSet the position of logo.png within the screenlogo_pos_x <key>logo_pos_x</key><string>0</string>0 pixels from origin along the x axislogo_pos_y <key>logo_pos_y</key><string>0</string>0 pixels from origin along the y axisDevices Set the position of the device list within the screendevices_pos_x <key>devices_pos_x</key><string></string>blank to center on the x axisdevices_pos_y <key>logo_pos_y</key><string></string>blank to center on the y axisdevices_max_visible <key>devices_max_visible</key>maximum number of devices visible<string>4</string>devices_icon_spacing <key>devices_icon_spacing</key>spaces between the drive icons<string>20</string>devices_layout <key>devices_layout</key><string>horizontal</string>horizontal or vertical listdevices_bgcolor <key>devices_bgcolor</key><string>#000000</string>web format #RRGGBBdevices_transparency <key>devices_transparency</key><string>128</string>0 (Opaque) -> 255 (Transparent)Boot prompt Set the position of the boot prompt within the screenbootprompt_pos_x <key>bootprompt_pos_x</key><string></string>blank to center on the x axisbootprompt_pos_y <key>bootprompt_pos_y</key><string></string>blank to center on the y axisbootprompt_width <key>bootprompt_width</key><string>-20</string>20 pixels less than the screen's width windowbootprompt_height <key>bootprompt_height</key><string>20</string>20 pixel high windowbootprompt_textmargin_h <key>bootprompt_textmargin_h</key>8 pixel horizontal text margin left and right<string>8</string>bootprompt_textmargin_v <key>bootprompt_textmargin_v</key>4 px vertical text margin both top and bottom<string>4</string>bootprompt_bgcolor <key>bootprompt_bgcolor</key><string>0x333445</string>web format #RRGGBBbootprompt_transparency <key>bootprompt_transparency</key><string>0</string>0 (Opaque) -> 255 (Transparent)Info box Set the position of the info box within the screeninfobox_pos_x <key>infobox_pos_x</key><string></string>blank to center on the x axisinfobox_pos_y <key>infobox_pos_y</key><string></string>blank center on the y axisinfobox_width <key>infobox_width</key><string>550</string>550 pixels wideinfobox_height <key>infobox_height</key><string>406</string>406 pixels highinfobox_bgcolor <key>infobox_bgcolor</key><string>#333445</string>web format #RRGGBBinfobox_transparency <key>infobox_transparency</key><string>64</string>0 (Opaque) -> 255 (Transparent)Menu Set the position of the pop up menu within the screenmenu_pos_x <key>menu_pos_x</key><string></string>center on the x axismenu_pos_y <key>menu_pos_y</key><string></string>center on the y axismenu_bgcolor <key>menu_bgcolor</key><string>#111223</string>web format #RRGGBBmenu_transparency <key>menu_transparency</key><string>0</string>0 (Opaque) -> 255 (Transparent)Boot DisplaySet the display dimensions to use when booting the kernel, will attempt to find the closest one available.boot_width <key>boot_width</key><string>1280</string>1280 pixels wide screenboot_height <key>boot_height</key><string>1024</string>1024 pixels tall screenGetting in touchChameleon homepagehttp://chameleon.osx86.hu/E-mail : voodoo@mercurysquad.comHope you guys like the bootloader!We appreciate your feedback and supportPAGE PAGE 1 \ No newline at end of file Index: branches/Chimera/doc/User_Guide_src/.svn/text-base/install_start.png.svn-base =================================================================== --- branches/Chimera/doc/User_Guide_src/.svn/text-base/install_start.png.svn-base (revision 0) +++ branches/Chimera/doc/User_Guide_src/.svn/text-base/install_start.png.svn-base (revision 850) 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