Index: branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/pci_old.h
===================================================================
--- branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/pci_old.h (revision 0)
+++ branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/pci_old.h (revision 862)
@@ -0,0 +1,903 @@
+/*
+ *
+ * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.
+ *
+ */
+
+#ifndef __PCI_OLD_H
+#define __PCI_OLD_H
+
+typedef struct {
+ uint32_t :2;
+ uint32_t reg :6;
+ uint32_t func:3;
+ uint32_t dev :5;
+ uint32_t bus :8;
+ uint32_t :7;
+ uint32_t eb :1;
+} pci_addr_t;
+
+typedef union {
+ pci_addr_t bits;
+ uint32_t addr;
+} pci_dev_t;
+
+typedef struct pci_dt_t {
+ pci_dev_t dev;
+
+ uint16_t vendor_id;
+ uint16_t device_id;
+
+ union {
+ struct {
+ uint16_t vendor_id;
+ uint16_t device_id;
+ } subsys;
+
+ uint32_t subsys_id;
+ } subsys_id;
+
+ uint16_t class_id;
+
+ struct pci_dt_t *parent;
+ struct pci_dt_t *children;
+ struct pci_dt_t *next;
+} pci_dt_t;
+
+#define PCIADDR(bus, dev, func) (1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
+#define PCI_ADDR_REG 0xcf8
+#define PCI_DATA_REG 0xcfc
+
+extern pci_dt_t *root_pci_dev;
+extern uint8_t pci_config_read8(uint32_t, uint8_t);
+extern uint16_t pci_config_read16(uint32_t, uint8_t);
+extern uint32_t pci_config_read32(uint32_t, uint8_t);
+extern void pci_config_write8(uint32_t, uint8_t, uint8_t);
+extern void pci_config_write16(uint32_t, uint8_t, uint16_t);
+extern void pci_config_write32(uint32_t, uint8_t, uint32_t);
+extern char *get_pci_dev_path(pci_dt_t *);
+extern void build_pci_dt(void);
+extern void dump_pci_dt(pci_dt_t *);
+
+//-----------------------------------------------------------------------------
+// added by iNDi
+
+struct pci_rom_pci_header_t {
+ uint32_t signature; // 0x50434952 'PCIR'
+ uint16_t vendor;
+ uint16_t device;
+ uint16_t product;
+ uint16_t length;
+ uint8_t revision; // 0 = PCI 2.1
+ uint8_t class[3];
+ uint16_t rom_size;
+ uint16_t code_revision;
+ uint8_t code_type; // 0 = x86
+ uint8_t last_image; // 0x80
+ uint16_t reserverd;
+};
+
+struct pci_rom_pnp_header_t {
+ uint32_t signature; // 0x24506E50 '$PnP'
+ uint8_t revision; // 1
+ uint8_t length; //
+ uint16_t offset;
+ uint8_t checksum;
+ uint32_t identifier;
+ uint16_t manufacturer;
+ uint16_t product;
+ uint8_t class[3];
+ uint8_t indicators;
+ uint16_t boot_vector;
+ uint16_t disconnect_vector;
+ uint16_t bootstrap_vector;
+ uint16_t reserved;
+ uint16_t resource_vector;
+};
+
+struct pci_rom_bios_t {
+ uint16_t signature; // 0x55AA
+ uint8_t size; // Multiples of 512
+
+ uint8_t checksum; // 0x00
+ uint16_t pci_header;
+ uint16_t pnp_header;
+};
+
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+
+#define PCI_VENDOR_ID 0x00 /* 16 bits */
+#define PCI_DEVICE_ID 0x02 /* 16 bits */
+#define PCI_COMMAND 0x04 /* 16 bits */
+#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
+#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
+#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
+#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
+#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
+#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
+#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
+#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
+#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
+#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
+#define PCI_COMMAND_DISABLE_INTx 0x400 /* PCIE: Disable INTx interrupts */
+
+#define PCI_STATUS 0x06 /* 16 bits */
+#define PCI_STATUS_INTx 0x08 /* PCIE: INTx interrupt pending */
+#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
+#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
+#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
+#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
+#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
+#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
+#define PCI_STATUS_DEVSEL_FAST 0x000
+#define PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define PCI_STATUS_DEVSEL_SLOW 0x400
+#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+
+#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
+#define PCI_REVISION_ID 0x08 /* Revision ID */
+#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE 0x0a /* Device class */
+
+#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
+#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
+#define PCI_HEADER_TYPE 0x0e /* 8 bits */
+#define PCI_HEADER_TYPE_NORMAL 0
+#define PCI_HEADER_TYPE_BRIDGE 1
+#define PCI_HEADER_TYPE_CARDBUS 2
+
+#define PCI_BIST 0x0f /* 8 bits */
+#define PCI_BIST_CODE_MASK 0x0f /* Return result */
+#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
+#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
+
+/*
+ * Base addresses specify locations in memory or I/O space.
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back. Only
+ * 1 bits are decoded.
+ */
+#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
+#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
+#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
+#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
+#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
+#define PCI_BASE_ADDRESS_SPACE_IO 0x01
+#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
+#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
+#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
+#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
+#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
+#define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f)
+#define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03)
+/* bit 1 is reserved if address_space = 1 */
+
+/* Header type 0 (normal devices) */
+#define PCI_CARDBUS_CIS 0x28
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+#define PCI_SUBSYSTEM_ID 0x2e
+#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
+#define PCI_ROM_ADDRESS_ENABLE 0x01
+#define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff)
+
+#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
+
+/* 0x35-0x3b are reserved */
+#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
+#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
+#define PCI_MIN_GNT 0x3e /* 8 bits */
+#define PCI_MAX_LAT 0x3f /* 8 bits */
+
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
+#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
+#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
+#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
+#define PCI_IO_LIMIT 0x1d
+#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
+#define PCI_IO_RANGE_TYPE_16 0x00
+#define PCI_IO_RANGE_TYPE_32 0x01
+#define PCI_IO_RANGE_MASK ~0x0f
+#define PCI_SEC_STATUS 0x1e /* Secondary status register */
+#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
+#define PCI_MEMORY_LIMIT 0x22
+#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
+#define PCI_MEMORY_RANGE_MASK ~0x0f
+#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT 0x26
+#define PCI_PREF_RANGE_TYPE_MASK 0x0f
+#define PCI_PREF_RANGE_TYPE_32 0x00
+#define PCI_PREF_RANGE_TYPE_64 0x01
+#define PCI_PREF_RANGE_MASK ~0x0f
+#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32 0x2c
+#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16 0x32
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
+#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_BRIDGE_CONTROL 0x3e
+#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
+#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
+#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
+#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
+#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
+#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
+#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
+#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100 /* PCI-X? */
+#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200 /* PCI-X? */
+#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400 /* PCI-X? */
+#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800 /* PCI-X? */
+
+/* Header type 2 (CardBus bridges) */
+/* 0x14-0x15 reserved */
+#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
+#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
+#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
+#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
+#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
+#define PCI_CB_MEMORY_BASE_0 0x1c
+#define PCI_CB_MEMORY_LIMIT_0 0x20
+#define PCI_CB_MEMORY_BASE_1 0x24
+#define PCI_CB_MEMORY_LIMIT_1 0x28
+#define PCI_CB_IO_BASE_0 0x2c
+#define PCI_CB_IO_BASE_0_HI 0x2e
+#define PCI_CB_IO_LIMIT_0 0x30
+#define PCI_CB_IO_LIMIT_0_HI 0x32
+#define PCI_CB_IO_BASE_1 0x34
+#define PCI_CB_IO_BASE_1_HI 0x36
+#define PCI_CB_IO_LIMIT_1 0x38
+#define PCI_CB_IO_LIMIT_1_HI 0x3a
+#define PCI_CB_IO_RANGE_MASK ~0x03
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_CB_BRIDGE_CONTROL 0x3e
+#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
+#define PCI_CB_BRIDGE_CTL_SERR 0x02
+#define PCI_CB_BRIDGE_CTL_ISA 0x04
+#define PCI_CB_BRIDGE_CTL_VGA 0x08
+#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
+#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
+#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
+#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
+#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
+#define PCI_CB_SUBSYSTEM_ID 0x42
+#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
+/* 0x48-0x7f reserved */
+
+/* Capability lists */
+#define PCI_CAP_LIST_ID 0 /* Capability ID */
+#define PCI_CAP_ID_PM 0x01 /* Power Management */
+#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
+#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
+#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
+#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
+#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
+#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
+#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
+#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
+#define PCI_CAP_ID_DBG 0x0A /* Debug port */
+#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
+#define PCI_CAP_ID_HOTPLUG 0x0C /* PCI hot-plug */
+#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
+#define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */
+#define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
+#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
+#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
+#define PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
+#define PCI_CAP_ID_AF 0x13 /* Advanced features of PCI devices integrated in PCIe root cplx */
+#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
+#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF 4
+
+/* Capabilities residing in the PCI Express extended configuration space */
+
+#define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */
+#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
+#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
+#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
+#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
+#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
+#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
+#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
+#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
+#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */
+#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
+#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
+
+/* Power Management Registers */
+
+#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
+#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
+#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */
+#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */
+#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
+#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
+#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
+#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
+#define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */
+#define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */
+#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
+#define PCI_PM_CTRL 4 /* PM control and status register */
+#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
+#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
+#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
+#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */
+#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */
+#define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
+#define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */
+#define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */
+#define PCI_PM_SIZEOF 8
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION 2 /* BCD version number */
+#define PCI_AGP_RFU 3 /* Rest of capability flags */
+#define PCI_AGP_STATUS 4 /* Status register */
+#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
+#define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */
+#define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
+#define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */
+#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
+#define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */
+#define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */
+#define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */
+#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */
+#define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */
+#define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */
+#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */
+#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */
+#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */
+#define PCI_AGP_COMMAND 8 /* Control register */
+#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
+#define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
+#define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */
+#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
+#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
+#define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */
+#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */
+#define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */
+#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */
+#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */
+#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */
+#define PCI_AGP_SIZEOF 12
+
+/* Vital Product Data */
+
+#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
+#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
+#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
+#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
+
+/* Slot Identification */
+
+#define PCI_SID_ESR 2 /* Expansion Slot Register */
+#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
+#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
+
+/* Message Signaled Interrupts registers */
+
+#define PCI_MSI_FLAGS 2 /* Various flags */
+#define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */
+#define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */
+#define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */
+#define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */
+#define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */
+#define PCI_MSI_RFU 3 /* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
+#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
+#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
+#define PCI_MSI_MASK_BIT_32 12 /* per-vector masking for 32-bit devices */
+#define PCI_MSI_MASK_BIT_64 16 /* per-vector masking for 64-bit devices */
+#define PCI_MSI_PENDING_32 16 /* per-vector interrupt pending for 32-bit devices */
+#define PCI_MSI_PENDING_64 20 /* per-vector interrupt pending for 64-bit devices */
+
+/* PCI-X */
+#define PCI_PCIX_COMMAND 2 /* Command register offset */
+#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
+#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
+#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
+#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
+#define PCI_PCIX_COMMAND_RESERVED 0xf80
+#define PCI_PCIX_STATUS 4 /* Status register offset */
+#define PCI_PCIX_STATUS_FUNCTION 0x00000007
+#define PCI_PCIX_STATUS_DEVICE 0x000000f8
+#define PCI_PCIX_STATUS_BUS 0x0000ff00
+#define PCI_PCIX_STATUS_64BIT 0x00010000
+#define PCI_PCIX_STATUS_133MHZ 0x00020000
+#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
+#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
+#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
+#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
+#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
+#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
+#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
+#define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
+#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
+#define PCI_PCIX_SIZEOF 4
+
+/* PCI-X Bridges */
+#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
+#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
+#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
+#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
+#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
+#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
+#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
+#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
+#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
+#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
+#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
+#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
+#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
+#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
+#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
+#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
+#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
+#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
+#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
+#define PCI_PCIX_BRIDGE_SIZEOF 12
+
+/* PCI Express */
+#define PCI_EXP_FLAGS 0x2 /* Capabilities register */
+#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
+#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
+#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
+#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
+#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
+#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
+#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
+#define PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
+#define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
+#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
+#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
+#define PCI_EXP_DEVCAP 0x4 /* Device capabilities */
+#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
+#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
+#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
+#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
+#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
+#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
+#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
+#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
+#define PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
+#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
+#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
+#define PCI_EXP_DEVCTL 0x8 /* Device Control */
+#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
+#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
+#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
+#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
+#define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
+#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
+#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
+#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
+#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
+#define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
+#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
+#define PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
+#define PCI_EXP_DEVSTA 0xa /* Device Status */
+#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
+#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
+#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
+#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
+#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
+#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
+#define PCI_EXP_LNKCAP 0xc /* Link Capabilities */
+#define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
+#define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
+#define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
+#define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
+#define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
+#define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
+#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
+#define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
+#define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
+#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
+#define PCI_EXP_LNKCTL 0x10 /* Link Control */
+#define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
+#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
+#define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
+#define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
+#define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
+#define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
+#define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
+#define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
+#define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
+#define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
+#define PCI_EXP_LNKSTA 0x12 /* Link Status */
+#define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
+#define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
+#define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
+#define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
+#define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
+#define PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
+#define PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
+#define PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
+#define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */
+#define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
+#define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
+#define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
+#define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
+#define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
+#define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
+#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
+#define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
+#define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
+#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
+#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_SLTCTL 0x18 /* Slot Control */
+#define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
+#define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
+#define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
+#define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
+#define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
+#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
+#define PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
+#define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
+#define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
+#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
+#define PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
+#define PCI_EXP_SLTSTA 0x1a /* Slot Status */
+#define PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
+#define PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
+#define PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
+#define PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
+#define PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
+#define PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
+#define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
+#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
+#define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
+#define PCI_EXP_RTCTL 0x1c /* Root Control */
+#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
+#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
+#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
+#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
+#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
+#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
+#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
+#define PCI_EXP_RTSTA 0x20 /* Root Status */
+#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
+#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
+#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
+#define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */
+#define PCI_EXP_DEVCTL2 0x28 /* Device Control */
+#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
+#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
+#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
+#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */
+#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
+#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
+#define PCI_EXP_LNKCTL2 0x30 /* Link Control */
+#define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */
+#define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */
+#define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */
+#define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */
+#define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */
+#define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */
+#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
+#define PCI_EXP_LNKSTA2 0x32 /* Link Status */
+#define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */
+#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */
+#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
+#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */
+
+/* MSI-X */
+#define PCI_MSIX_ENABLE 0x8000
+#define PCI_MSIX_MASK 0x4000
+#define PCI_MSIX_TABSIZE 0x03ff
+#define PCI_MSIX_TABLE 4
+#define PCI_MSIX_PBA 8
+#define PCI_MSIX_BIR 0x7
+
+/* Subsystem vendor/device ID for PCI bridges */
+#define PCI_SSVID_VENDOR 4
+#define PCI_SSVID_DEVICE 6
+
+/* Advanced Error Reporting */
+#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
+#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
+#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
+#define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */
+#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
+#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
+#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
+#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
+#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
+#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
+#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
+#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
+#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
+#define PCI_ERR_UNC_ACS_VIOL 0x00200000 /* ACS Violation */
+#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
+/* Same bits as above */
+#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
+/* Same bits as above */
+#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
+#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
+#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
+#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
+#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
+#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
+#define PCI_ERR_COR_REP_ANFE 0x00002000 /* Advisory Non-Fatal Error */
+#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
+/* Same bits as above */
+#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
+#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
+#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
+#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
+#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
+#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
+#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
+#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
+#define PCI_ERR_ROOT_STATUS 48
+#define PCI_ERR_ROOT_COR_SRC 52
+#define PCI_ERR_ROOT_SRC 54
+
+/* Virtual Channel */
+#define PCI_VC_PORT_REG1 4
+#define PCI_VC_PORT_REG2 8
+#define PCI_VC_PORT_CTRL 12
+#define PCI_VC_PORT_STATUS 14
+#define PCI_VC_RES_CAP 16
+#define PCI_VC_RES_CTRL 20
+#define PCI_VC_RES_STATUS 26
+
+/* Power Budgeting */
+#define PCI_PWR_DSR 4 /* Data Select Register */
+#define PCI_PWR_DATA 8 /* Data Register */
+#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
+#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
+#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
+#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
+#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
+#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
+#define PCI_PWR_CAP 12 /* Capability */
+#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
+
+/* Access Control Services */
+#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
+#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
+#define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */
+#define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */
+#define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */
+#define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */
+#define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */
+#define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */
+#define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */
+#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
+#define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */
+#define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable */
+#define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable */
+#define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enable */
+#define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */
+#define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */
+#define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable */
+#define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */
+
+/* Alternative Routing-ID Interpretation */
+#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
+#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */
+#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
+#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
+#define PCI_ARI_CTRL 0x06 /* ARI Control Register */
+#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
+#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
+#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
+
+/* Address Translation Service */
+#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
+#define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */
+#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
+#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
+#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
+
+/* Single Root I/O Virtualization */
+#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
+#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
+#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */
+#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
+#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
+#define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */
+#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
+#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
+#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
+#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */
+#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */
+#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */
+#define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs that could be associated */
+#define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available */
+#define PCI_IOV_FDL 0x12 /* Function Dependency Link */
+#define PCI_IOV_OFFSET 0x14 /* First VF Offset */
+#define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */
+#define PCI_IOV_DID 0x1a /* VF Device ID */
+#define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */
+#define PCI_IOV_SYSPS 0x20 /* System Page Size */
+#define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */
+#define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */
+#define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset */
+#define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */
+#define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */
+
+/*
+ * The PCI interface treats multi-function devices as independent
+ * devices. The slot/function address of each device is encoded
+ * in a single byte as follows:
+ *
+ * 7:3 = slot
+ * 2:0 = function
+ */
+#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
+#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
+#define PCI_FUNC(devfn) ((devfn) & 0x07)
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED 0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
+
+#define PCI_BASE_CLASS_STORAGE 0x01
+#define PCI_CLASS_STORAGE_SCSI 0x0100
+#define PCI_CLASS_STORAGE_IDE 0x0101
+#define PCI_CLASS_STORAGE_FLOPPY 0x0102
+#define PCI_CLASS_STORAGE_IPI 0x0103
+#define PCI_CLASS_STORAGE_RAID 0x0104
+#define PCI_CLASS_STORAGE_ATA 0x0105
+#define PCI_CLASS_STORAGE_SATA 0x0106
+#define PCI_CLASS_STORAGE_SAS 0x0107
+#define PCI_CLASS_STORAGE_OTHER 0x0180
+
+#define PCI_BASE_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
+#define PCI_CLASS_NETWORK_FDDI 0x0202
+#define PCI_CLASS_NETWORK_ATM 0x0203
+#define PCI_CLASS_NETWORK_ISDN 0x0204
+#define PCI_CLASS_NETWORK_OTHER 0x0280
+
+#define PCI_BASE_CLASS_DISPLAY 0x03
+#define PCI_CLASS_DISPLAY_VGA 0x0300
+#define PCI_CLASS_DISPLAY_XGA 0x0301
+#define PCI_CLASS_DISPLAY_3D 0x0302
+#define PCI_CLASS_DISPLAY_OTHER 0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA 0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
+#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV 0x0403
+#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
+
+#define PCI_BASE_CLASS_MEMORY 0x05
+#define PCI_CLASS_MEMORY_RAM 0x0500
+#define PCI_CLASS_MEMORY_FLASH 0x0501
+#define PCI_CLASS_MEMORY_OTHER 0x0580
+
+#define PCI_BASE_CLASS_BRIDGE 0x06
+#define PCI_CLASS_BRIDGE_HOST 0x0600
+#define PCI_CLASS_BRIDGE_ISA 0x0601
+#define PCI_CLASS_BRIDGE_EISA 0x0602
+#define PCI_CLASS_BRIDGE_MC 0x0603
+#define PCI_CLASS_BRIDGE_PCI 0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
+#define PCI_CLASS_BRIDGE_NUBUS 0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY 0x0608
+#define PCI_CLASS_BRIDGE_PCI_SEMI 0x0609
+#define PCI_CLASS_BRIDGE_IB_TO_PCI 0x060a
+#define PCI_CLASS_BRIDGE_OTHER 0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION 0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MSERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM 0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
+
+#define PCI_BASE_CLASS_SYSTEM 0x08
+#define PCI_CLASS_SYSTEM_PIC 0x0800
+#define PCI_CLASS_SYSTEM_DMA 0x0801
+#define PCI_CLASS_SYSTEM_TIMER 0x0802
+#define PCI_CLASS_SYSTEM_RTC 0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
+#define PCI_CLASS_SYSTEM_OTHER 0x0880
+
+#define PCI_BASE_CLASS_INPUT 0x09
+#define PCI_CLASS_INPUT_KEYBOARD 0x0900
+#define PCI_CLASS_INPUT_PEN 0x0901
+#define PCI_CLASS_INPUT_MOUSE 0x0902
+#define PCI_CLASS_INPUT_SCANNER 0x0903
+#define PCI_CLASS_INPUT_GAMEPORT 0x0904
+#define PCI_CLASS_INPUT_OTHER 0x0980
+
+#define PCI_BASE_CLASS_DOCKING 0x0a
+#define PCI_CLASS_DOCKING_GENERIC 0x0a00
+#define PCI_CLASS_DOCKING_OTHER 0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR 0x0b
+#define PCI_CLASS_PROCESSOR_386 0x0b00
+#define PCI_CLASS_PROCESSOR_486 0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS 0x0b30
+#define PCI_CLASS_PROCESSOR_CO 0x0b40
+
+#define PCI_BASE_CLASS_SERIAL 0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
+#define PCI_CLASS_SERIAL_ACCESS 0x0c01
+#define PCI_CLASS_SERIAL_SSA 0x0c02
+#define PCI_CLASS_SERIAL_USB 0x0c03
+#define PCI_CLASS_SERIAL_FIBER 0x0c04
+#define PCI_CLASS_SERIAL_SMBUS 0x0c05
+#define PCI_CLASS_SERIAL_INFINIBAND 0x0c06
+
+#define PCI_BASE_CLASS_WIRELESS 0x0d
+#define PCI_CLASS_WIRELESS_IRDA 0x0d00
+#define PCI_CLASS_WIRELESS_CONSUMER_IR 0x0d01
+#define PCI_CLASS_WIRELESS_RF 0x0d10
+#define PCI_CLASS_WIRELESS_OTHER 0x0d80
+
+#define PCI_BASE_CLASS_INTELLIGENT 0x0e
+#define PCI_CLASS_INTELLIGENT_I2O 0x0e00
+
+#define PCI_BASE_CLASS_SATELLITE 0x0f
+#define PCI_CLASS_SATELLITE_TV 0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO 0x0f01
+#define PCI_CLASS_SATELLITE_VOICE 0x0f03
+#define PCI_CLASS_SATELLITE_DATA 0x0f04
+
+#define PCI_BASE_CLASS_CRYPT 0x10
+#define PCI_CLASS_CRYPT_NETWORK 0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1010
+#define PCI_CLASS_CRYPT_OTHER 0x1080
+
+#define PCI_BASE_CLASS_SIGNAL 0x11
+#define PCI_CLASS_SIGNAL_DPIO 0x1100
+#define PCI_CLASS_SIGNAL_PERF_CTR 0x1101
+#define PCI_CLASS_SIGNAL_SYNCHRONIZER 0x1110
+#define PCI_CLASS_SIGNAL_OTHER 0x1180
+
+#define PCI_CLASS_OTHERS 0xff
+
+/* Several ID's we need in the library */
+
+#define PCI_VENDOR_ID_APPLE 0x106b
+#define PCI_VENDOR_ID_AMD 0x1002
+#define PCI_VENDOR_ID_ATI 0x1002
+#define PCI_VENDOR_ID_INTEL 0x8086
+#define PCI_VENDOR_ID_NVIDIA 0x10de
+#define PCI_VENDOR_ID_REALTEK 0x10ec
+#define PCI_VENDOR_ID_TEXAS_INSTRUMENTS 0x104c
+#define PCI_VENDOR_ID_VIA 0x1106
+
+#endif /* !__PCI_OLD_H */
Index: branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ati.h
===================================================================
--- branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ati.h (revision 0)
+++ branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ati.h (revision 862)
@@ -0,0 +1,46 @@
+/*
+ * ATI injector
+ *
+ * Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
+ *
+ * ATI injector is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * ATI driver and injector is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with ATI injector. If not, see .
+ */
+ /*
+ * Alternatively you can choose to comply with APSL
+ */
+
+
+#ifndef __LIBSAIO_ATI_H
+#define __LIBSAIO_ATI_H
+
+bool setup_ati_devprop(pci_dt_t *ati_dev);
+
+struct ati_chipsets_t {
+ unsigned device;
+ char *name;
+};
+
+struct ati_data_key {
+ uint32_t size;
+ char *name;
+ uint8_t data[];
+};
+
+#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
+#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
+#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
+#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val)
+
+
+#endif /* !__LIBSAIO_ATI_H */
Index: branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/Readme.txt
===================================================================
--- branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/Readme.txt (revision 0)
+++ branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/Readme.txt (revision 862)
@@ -0,0 +1,12 @@
+Module: GraphicsEnablerLegacy
+
+Description: the GraphicsEnabler code ( < r784) ported to a module.
+Will most probably be turned into an ATILegacy module, or sort of...??
+Based on Meklort's work.
+
+Dependencies: none
+
+Keys: GraphicsEnabler (enabled by default)
+ UseNvidiaROM
+ VBIOS
+ UseAtiROM
\ No newline at end of file
Index: branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ATIEnablerLegacy.c
===================================================================
--- branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ATIEnablerLegacy.c (revision 0)
+++ branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ATIEnablerLegacy.c (revision 862)
@@ -0,0 +1,45 @@
+/*
+ * GraphicsEnabler Module
+ * Enabled many nvidia and ati cards to be used out of the box in
+ * OS X. This was converted from boot2 code to a boot2 module.
+ *
+ */
+
+#include "saio_internal.h"
+#include "bootstruct.h"
+#include "../modules/ATIEnablerLegacy/pci_old.h"
+#include "ati.h"
+#include "modules.h"
+
+
+#define kGraphicsEnablerKey "GraphicsEnabler" // change?
+
+void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
+
+
+void ATIEnablerLegacy_start()
+{
+ register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
+}
+
+void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
+{
+ pci_dt_t* current = arg1;
+
+ if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
+
+ char *devicepath = get_pci_dev_path(current);
+
+ bool do_gfx_devprop = true;
+ getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
+
+ //Azi: ati.c doesn't seem to have "fail" code... check better!***
+ if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI))
+ {
+ verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
+ current->vendor_id, current->device_id, devicepath);
+ setup_ati_devprop(current);
+ }
+ else
+ verbose("Not an ATI card...??\n");
+}
Index: branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/Makefile
===================================================================
--- branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/Makefile (revision 0)
+++ branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/Makefile (revision 862)
@@ -0,0 +1,41 @@
+MODULE_NAME = ATIEnablerLegacy
+MODULE_VERSION = "1.0.0"
+MODULE_COMPAT_VERSION = "1.0.0"
+MODULE_START = _$(MODULE_NAME)_start
+MODULE_DEPENDENCIES =
+
+DIR = GraphicsEnabler
+
+MODULE_OBJS = ati.o ATIEnablerLegacy.o
+
+OPTIM = -Os -Oz
+DEBUG = -DNOTHING
+#DEBUG = -DDEBUG_HELLO_WORLD=1
+CFLAGS = $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
+ -D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
+ -DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
+ -fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
+ -mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
+ -march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
+
+DEFINES=
+CONFIG = hd
+INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
+LIBS=
+
+VPATH = $(OBJROOT):$(SYMROOT)
+
+SFILES =
+CFILES =
+HFILES =
+EXPORTED_HFILES =
+INSTALLED_HFILES =
+OTHERFILES = Makefile
+ALLSRC = $(SFILES) $(CFILES) \
+ $(HFILES) $(OTHERFILES)
+DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
+
+all embedtheme: dylib
+
+
+include ../MakeInc.dir
Index: branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ati.c
===================================================================
--- branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ati.c (revision 0)
+++ branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ati.c (revision 862)
@@ -0,0 +1,783 @@
+/*
+ * ATI injector
+ *
+ * Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
+ *
+ * ATI injector is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * ATI driver and injector is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with ATI injector. If not, see .
+ */
+/*
+ * Alternatively you can choose to comply with APSL
+ */
+
+#include "bootstruct.h"
+#include "../modules/ATIEnablerLegacy/pci_old.h"
+#include "platform.h"
+#include "device_inject.h"
+#include "ati.h"
+
+#ifndef DEBUG_ATI
+#define DEBUG_ATI 0
+#endif
+
+#if DEBUG_ATI
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif
+
+#define kUseAtiROMKey "UseAtiROM"
+
+#define MAX_NUM_DCB_ENTRIES 16
+
+#define TYPE_GROUPED 0xff
+
+extern uint32_t devices_number;
+
+const char *ati_compatible_0[] = { "@0,compatible", "ATY,%s" };
+const char *ati_compatible_1[] = { "@1,compatible", "ATY,%s" };
+const char *ati_device_type_0[] = { "@0,device_type", "display" };
+const char *ati_device_type_1[] = { "@1,device_type", "display" };
+const char *ati_device_type[] = { "device_type", "ATY,%sParent" };
+const char *ati_name_0[] = { "@0,name", "ATY,%s" };
+const char *ati_name_1[] = { "@1,name", "ATY,%s" };
+const char *ati_name[] = { "name", "ATY,%sParent" };
+const char *ati_efidisplay_0[] = { "@0,ATY,EFIDisplay", "TMDSB" };
+struct ati_data_key ati_connector_type_0 = { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };
+struct ati_data_key ati_connector_type_1 = { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_display_con_fl_type_0 = { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };
+const char *ati_display_type_0[] = { "@0,display-type", "LCD" };
+const char *ati_display_type_1[] = { "@1,display-type", "NONE" };
+struct ati_data_key ati_aux_power_conn = { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_backlight_ctrl = { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_aapl01_coher = { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };
+const char *ati_card_no[] = { "ATY,Card#", "109-B77101-00" };
+const char *ati_copyright[] = { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };
+const char *ati_efi_compile_d[] = { "ATY,EFICompileDate", "Jan 26 2009" };
+struct ati_data_key ati_efi_disp_conf = { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };
+struct ati_data_key ati_efi_drv_type = { 0x01, "ATY,EFIDriverType", {0x02} };
+struct ati_data_key ati_efi_enbl_mode = { 0x01, "ATY,EFIEnabledMode", {0x01} };
+struct ati_data_key ati_efi_init_stat = { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_efi_orientation = { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };
+const char *ati_efi_version[] = { "ATY,EFIVersion", "01.00.318" };
+const char *ati_efi_versionB[] = { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };
+const char *ati_efi_versionE[] = { "ATY,EFIVersionE", "113-B7710A-318" };
+struct ati_data_key ati_mclk = { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };
+struct ati_data_key ati_mem_rev_id = { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };
+struct ati_data_key ati_mem_vend_id = { 0x02, "ATY,MemVendorID", {0x02, 0x00} };
+const char *ati_mrt[] = { "ATY,MRT", " " };
+const char *ati_romno[] = { "ATY,Rom#", "113-B7710C-176" };
+struct ati_data_key ati_sclk = { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };
+struct ati_data_key ati_vendor_id = { 0x02, "ATY,VendorID", {0x02, 0x10} };
+struct ati_data_key ati_platform_info = { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_mvad = { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };
+struct ati_data_key ati_saved_config = { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
+///non 48xx keys
+const char *ati_efidisplay_0_n4[] = { "@0,ATY,EFIDisplay", "TMDSA" };
+struct ati_data_key ati_connector_type_0_n4 = { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_connector_type_1_n4 = { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };
+struct ati_data_key ati_aapl_emc_disp_list_n4 = { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_fb_offset_n4 = { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_hwgpio_n4 = { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };
+struct ati_data_key ati_iospace_offset_n4 = { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };
+struct ati_data_key ati_mclk_n4 = { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };
+struct ati_data_key ati_sclk_n4 = { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };
+struct ati_data_key ati_refclk_n4 = { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };
+struct ati_data_key ati_regspace_offset_n4 = { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };
+struct ati_data_key ati_vram_memsize_0 = { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_vram_memsize_1 = { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_swgpio_info_n4 = { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };
+struct ati_data_key ati_efi_orientation_n4 = { 0x01, "ATY,EFIOrientation", {0x08} };
+struct ati_data_key ati_mvad_n4 = { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
+struct ati_data_key ati_saved_config_n4 = { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
+
+struct pcir_s {
+ uint32_t signature;
+ uint16_t vid;
+ uint16_t devid;
+};
+
+// Known cards as of 2008/08/26
+static struct ati_chipsets_t ATIKnownChipsets[] = {
+ { 0x00000000, "Unknown" } ,
+// { 0x10027181, "ATI Radeon 1300 Series"} ,
+ { 0x10029589, "ATI Radeon 2600 Series"} ,
+ { 0x10029588, "ATI Radeon 2600 Series"} ,
+ { 0x100294C3, "ATI Radeon 2400 Series"} ,
+ { 0x100294C4, "ATI Radeon 2400 Series"} ,
+ { 0x100294C6, "ATI Radeon 2400 Series"} ,
+ { 0x10029400, "ATI Radeon 2900 Series"} ,
+ { 0x10029405, "ATI Radeon 2900GT Series"} ,
+ { 0x10029581, "ATI Radeon 2600 Series"} ,
+ { 0x10029583, "ATI Radeon 2600 Series"} ,
+ { 0x10029586, "ATI Radeon 2600 Series"} ,
+ { 0x10029587, "ATI Radeon 2600 Series"} ,
+ { 0x100294C9, "ATI Radeon 2400 Series"} ,
+ { 0x10029501, "ATI Radeon 3800 Series"} ,
+ { 0x10029505, "ATI Radeon 3800 Series"} ,
+ { 0x10029515, "ATI Radeon 3800 Series"} ,
+ { 0x10029507, "ATI Radeon 3800 Series"} ,
+ { 0x10029500, "ATI Radeon 3800 Series"} ,
+ { 0x1002950F, "ATI Radeon 3800X2 Series"} ,
+ { 0x100295C5, "ATI Radeon 3400 Series"} ,
+ { 0x100295C7, "ATI Radeon 3400 Series"} ,
+ { 0x100295C0, "ATI Radeon 3400 Series"} ,
+ { 0x10029596, "ATI Radeon 3600 Series"} ,
+ { 0x10029590, "ATI Radeon 3600 Series"} ,
+ { 0x10029599, "ATI Radeon 3600 Series"} ,
+ { 0x10029597, "ATI Radeon 3600 Series"} ,
+ { 0x10029598, "ATI Radeon 3600 Series"} ,
+ { 0x10029442, "ATI Radeon 4850 Series"} ,
+ { 0x10029440, "ATI Radeon 4870 Series"} ,
+ { 0x1002944C, "ATI Radeon 4830 Series"} ,
+ { 0x10029460, "ATI Radeon 4890 Series"} ,
+ { 0x10029462, "ATI Radeon 4890 Series"} ,
+ { 0x10029441, "ATI Radeon 4870X2 Series"} ,
+ { 0x10029443, "ATI Radeon 4850X2 Series"} ,
+ { 0x10029444, "ATI Radeon 4800 Series"} ,
+ { 0x10029446, "ATI Radeon 4800 Series"} ,
+ { 0x1002944E, "ATI Radeon 4730 Series"} ,
+ { 0x10029450, "ATI Radeon 4800 Series"} ,
+ { 0x10029452, "ATI Radeon 4800 Series"} ,
+ { 0x10029456, "ATI Radeon 4800 Series"} ,
+ { 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,
+ { 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,
+ { 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,
+ { 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,
+ { 0x10029490, "ATI Radeon 4670 Series"} ,
+ { 0x10029498, "ATI Radeon 4650 Series"} ,
+ { 0x10029490, "ATI Radeon 4600 Series"} ,
+ { 0x10029498, "ATI Radeon 4600 Series"} ,
+ { 0x1002949E, "ATI Radeon 4600 Series"} ,
+ { 0x10029480, "ATI Radeon 4600 Series"} ,
+ { 0x10029488, "ATI Radeon 4600 Series"} ,
+ { 0x10029540, "ATI Radeon 4500 Series"} ,
+ { 0x10029541, "ATI Radeon 4500 Series"} ,
+ { 0x1002954E, "ATI Radeon 4500 Series"} ,
+ { 0x10029552, "ATI Radeon 4300 Mobility Series"} ,
+ { 0x10029553, "ATI Radeon 4500 Mobility Series"} ,
+ { 0x1002954F, "ATI Radeon 4300 Series"} ,
+ { 0x100294B3, "ATI Radeon 4770 Series"} ,
+ { 0x100294B5, "ATI Radeon 4770 Series"} ,
+ { 0x100268B8, "ATI Radeon 5700 Series"} ,
+ { 0x100268BE, "ATI Radeon 5700 Series"} ,
+ { 0x10026898, "ATI Radeon 5800 Series"} ,
+ { 0x10026899, "ATI Radeon 5800 Series"}
+};
+
+static struct ati_chipsets_t ATIKnownFramebuffers[] = {
+ { 0x00000000, "Megalodon" },
+// { 0x10027181, "Caretta" },
+ { 0x10029589, "Lamna"} ,
+ { 0x10029588, "Lamna"} ,
+ { 0x100294C3, "Iago"} ,
+ { 0x100294C4, "Iago"} ,
+ { 0x100294C6, "Iago"} ,
+ { 0x10029400, "Franklin"} ,
+ { 0x10029405, "Franklin"} ,
+ { 0x10029581, "Hypoprion"} ,
+ { 0x10029583, "Hypoprion"} ,
+ { 0x10029586, "Hypoprion"} ,
+ { 0x10029587, "Hypoprion"} ,
+ { 0x100294C9, "Iago"} ,
+ { 0x10029501, "Megalodon"} ,
+ { 0x10029505, "Megalodon"} ,
+ { 0x10029515, "Megalodon"} ,
+ { 0x10029507, "Megalodon"} ,
+ { 0x10029500, "Megalodon"} ,
+ { 0x1002950F, "Triakis"} ,
+ { 0x100295C5, "Iago"} ,
+ { 0x100295C7, "Iago"} ,
+ { 0x100295C0, "Iago"} ,
+ { 0x10029596, "Megalodon"} ,
+ { 0x10029590, "Megalodon"} ,
+ { 0x10029599, "Megalodon"} ,
+ { 0x10029597, "Megalodon"} ,
+ { 0x10029598, "Megalodon"} ,
+ { 0x10029442, "Motmot"} ,
+ { 0x10029440, "Motmot"} ,
+ { 0x1002944C, "Motmot"} ,
+ { 0x10029460, "Motmot"} ,
+ { 0x10029462, "Motmot"} ,
+ { 0x10029441, "Motmot"} ,
+ { 0x10029443, "Motmot"} ,
+ { 0x10029444, "Motmot"} ,
+ { 0x10029446, "Motmot"} ,
+ { 0x1002944E, "Motmot"} ,
+ { 0x10029450, "Motmot"} ,
+ { 0x10029452, "Motmot"} ,
+ { 0x10029456, "Motmot"} ,
+ { 0x1002944A, "Motmot"} ,
+ { 0x1002945A, "Motmot"} ,
+ { 0x1002945B, "Motmot"} ,
+ { 0x1002944B, "Motmot"} ,
+ { 0x10029490, "Peregrine"} ,
+ { 0x10029498, "Peregrine"} ,
+ { 0x1002949E, "Peregrine"} ,
+ { 0x10029480, "Peregrine"} ,
+ { 0x10029488, "Peregrine"} ,
+ { 0x10029540, "Peregrine"} ,
+ { 0x10029541, "Peregrine"} ,
+ { 0x1002954E, "Peregrine"} ,
+ { 0x10029552, "Peregrine"} ,
+ { 0x10029553, "Peregrine"} ,
+ { 0x1002954F, "Peregrine"} ,
+ { 0x100294B3, "Peregrine"},
+ { 0x100294B5, "Peregrine"},
+ { 0x100268B8, "Motmot"},
+ { 0x100268BE, "Motmot"},
+ { 0x10026898, "Motmot"},
+ { 0x10026899, "Motmot"}
+};
+
+static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
+{
+ uint32_t bar[7];
+ volatile uint32_t *regs;
+
+ bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
+ regs = (uint32_t *) (bar[2] & ~0x0f);
+
+ if (mode) {
+ if (mode != 1) {
+ return 0xe00002c7;
+ }
+ REG32W(0x179c, 0x00080000);
+ REG32W(0x1798, 0x00080721);
+ REG32W(0x17a0, 0x00080621);
+ REG32W(0x1600, 0x14030300);
+ REG32W(0x1798, 0x21);
+ REG32W(0x17a0, 0x21);
+ REG32W(0x179c, 0x00);
+ REG32W(0x17a0, 0x21);
+ REG32W(0x1798, 0x21);
+ REG32W(0x1798, 0x21);
+ } else {
+ REG32W(0x1600, 0x14030302);
+ REG32W(0x1798, 0x21);
+ REG32W(0x17a0, 0x21);
+ REG32W(0x179c, 0x00080000);
+ REG32W(0x17a0, 0x00080621);
+ REG32W(0x1798, 0x00080721);
+ REG32W(0x1798, 0x21);
+ REG32W(0x17a0, 0x21);
+ REG32W(0x179c, 0x00);
+ REG32W(0x1604, 0x0400e9fc);
+ REG32W(0x161c, 0x00);
+ REG32W(0x1620, 0x9f);
+ REG32W(0x1618, 0x00040004);
+ REG32W(0x161c, 0x00);
+ REG32W(0x1604, 0xe9fc);
+ REG32W(0x179c, 0x00080000);
+ REG32W(0x1798, 0x00080721);
+ REG32W(0x17a0, 0x00080621);
+ REG32W(0x1798, 0x21);
+ REG32W(0x17a0, 0x21);
+ REG32W(0x179c, 0x00);
+ }
+ return 0;
+}
+
+static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
+{
+ uint32_t bar[7];
+ uint32_t *BIOSBase;
+ uint32_t counter;
+ volatile uint32_t *regs;
+
+ bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
+ regs = (volatile uint32_t *) (bar[2] & ~0x0f);
+ accessROM(ati_dev, 0);
+ REG32W(0xa8, 0);
+ REG32R(0xac);
+ REG32W(0xa8, 0);
+ REG32R(0xac);
+
+ BIOSBase = malloc(0x10000);
+ REG32W(0xa8, 0);
+ BIOSBase[0] = REG32R(0xac);
+ counter = 4;
+ do {
+ REG32W(0xa8, counter);
+ BIOSBase[counter/4] = REG32R(0xac);
+ counter +=4;
+ } while (counter != 0x10000);
+ accessROM((pci_dt_t *)regs, 1);
+
+ if (*(uint16_t *)BIOSBase != 0xAA55) {
+ printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
+ return 0;
+ }
+ return (uint8_t *)BIOSBase;
+}
+
+#define R5XX_CONFIG_MEMSIZE 0x00F8 //Azi:---
+#define R6XX_CONFIG_MEMSIZE 0x5428
+
+uint32_t getvramsizekb(pci_dt_t *ati_dev)
+{
+ uint32_t bar[7];
+ uint32_t size;
+ volatile uint32_t *regs;
+
+ bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
+ regs = (uint32_t *) (bar[2] & ~0x0f);
+ if (ati_dev->device_id < 0x9400) {
+ size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
+ } else {
+ size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;
+ }
+ return size;
+}
+
+#define AVIVO_D1CRTC_CONTROL 0x6080
+#define AVIVO_CRTC_EN (1<<0)
+#define AVIVO_D2CRTC_CONTROL 0x6880
+
+static bool radeon_card_posted(pci_dt_t *ati_dev)
+{
+ // if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.
+/* char *biosimage = 0xC0000;
+
+ if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)
+ {
+ struct pci_rom_pci_header_t *rom_pci_header;
+ rom_pci_header = (struct pci_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);
+
+ if (rom_pci_header->signature == 0x52494350)
+ {
+ if (rom_pci_header->device == ati_dev->device_id)
+ {
+ return true;
+ printf("Card was POSTed\n");
+ }
+ }
+ }
+ return false;
+ printf("Card was not POSTed\n");
+ */
+ //fails yet
+ uint32_t bar[7];
+ uint32_t val;
+ volatile uint32_t *regs;
+
+ bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);
+ regs = (uint32_t *) (bar[2] & ~0x0f);
+
+ val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);
+ if (val & AVIVO_CRTC_EN) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)
+{
+ int fd;
+ int size;
+
+ if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
+ return 0;
+ }
+ size = file_size(fd);
+ if (size > bufsize) {
+ printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
+ size = bufsize;
+ }
+ size = read(fd, (char *)buf, size);
+ close(fd);
+ return size > 0 ? size : 0;
+}
+
+static char *get_ati_model(uint32_t id)
+{
+ int i;
+
+ for (i = 0; i < (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {
+ if (ATIKnownChipsets[i].device == id) {
+ return ATIKnownChipsets[i].name;
+ }
+ }
+ return ATIKnownChipsets[0].name;
+}
+
+static char *get_ati_fb(uint32_t id)
+{
+ int i;
+
+ for (i = 0; i < (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {
+ if (ATIKnownFramebuffers[i].device == id) {
+ return ATIKnownFramebuffers[i].name;
+ }
+ }
+ return ATIKnownFramebuffers[0].name;
+}
+
+static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)
+{
+ int i;
+ uint8_t *config_space;
+
+ if (!device || !ati_dev) {
+ return 0;
+ }
+ verbose("dumping pci config space, 256 bytes\n");
+ config_space = malloc(256);
+ for (i=0; i<=255; i++) {
+ config_space[i] = pci_config_read8( ati_dev->dev.addr, i);
+ }
+ devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);
+ free (config_space);
+ return 1;
+}
+
+static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)
+{
+ if(!device)
+ return 0;
+
+// if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))
+// return 0;
+// if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))
+// return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
+ return 0;
+// if(!DP_ADD_TEMP_VAL(device, ati_device_type))
+// return 0;
+// if(!DP_ADD_TEMP_VAL(device, ati_name_0))
+// return 0;
+// if(!DP_ADD_TEMP_VAL(device, ati_name_1))
+// return 0;
+// if(!DP_ADD_TEMP_VAL(device, ati_name))
+// return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))
+ return 0;
+// if(!DP_ADD_TEMP_VAL(device, ati_slot_name))
+// return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_card_no))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_copyright))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_mrt))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_romno))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_name_1))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))
+ return 0;
+ return 1;
+}
+
+static int devprop_add_ati_template(struct DevPropDevice *device)
+{
+ if(!device)
+ return 0;
+
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))
+ return 0;
+// if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))
+// return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_card_no))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_copyright))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_mrt))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_romno))
+ return 0;
+ if(!DP_ADD_TEMP_VAL(device, ati_name_1))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))
+ return 0;
+ if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))
+ return 0;
+ return 1;
+}
+
+
+bool setup_ati_devprop(pci_dt_t *ati_dev)
+{
+ struct DevPropDevice *device;
+ char *devicepath;
+ char *model;
+ char *framebuffer;
+ char tmp[64];
+ uint8_t *rom = NULL;
+ uint32_t rom_size = 0;
+ uint8_t *bios;
+ uint32_t bios_size;
+ uint32_t vram_size;
+ uint32_t boot_display;
+ uint8_t cmd;
+ bool doit;
+ bool toFree;
+
+ devicepath = get_pci_dev_path(ati_dev);
+
+ cmd = pci_config_read8(ati_dev->dev.addr, 4);
+ verbose("old pci command - %x\n", cmd);
+ if (cmd == 0) {
+ pci_config_write8(ati_dev->dev.addr, 4, 6);
+ cmd = pci_config_read8(ati_dev->dev.addr, 4);
+ verbose("new pci command - %x\n", cmd);
+ }
+
+ model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);
+ framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);
+ if (!string) {
+ string = devprop_create_string();
+ }
+ device = devprop_add_device(string, devicepath);
+ if (!device) {
+ printf("Failed initializing dev-prop string dev-entry, press any key...\n");
+ getc();
+ return false;
+ }
+
+ /* FIXME: for primary graphics card only */
+ if (radeon_card_posted(ati_dev)) {
+ boot_display = 1;
+ } else {
+ boot_display = 0;
+ }
+ verbose("boot display - %x\n", boot_display);
+ devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
+
+ if ((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') ||
+ (framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') ||
+ (framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)
+ devprop_add_ati_template_4xxx(device);
+ else {
+ devprop_add_ati_template(device);
+ vram_size = getvramsizekb(ati_dev) * 1024;
+ if ((vram_size > 0x80000000) || (vram_size == 0)) {
+ vram_size = 0x10000000; //vram reported wrong, defaulting to 256 mb
+ }
+ devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);
+ ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
+ ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;
+ ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
+ ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF;
+ DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0);
+ DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);
+ devprop_add_iopciconfigspace(device, ati_dev);
+ }
+ devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
+ devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);
+
+ //fb setup
+ sprintf(tmp, "Slot-%x",devices_number);
+ devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);
+ devices_number++;
+
+ sprintf(tmp, ati_compatible_0[1], framebuffer);
+ devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
+
+ sprintf(tmp, ati_compatible_1[1], framebuffer);
+ devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
+
+ sprintf(tmp, ati_device_type[1], framebuffer);
+ devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);
+
+ sprintf(tmp, ati_name[1], framebuffer);
+ devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);
+
+ sprintf(tmp, ati_name_0[1], framebuffer);
+ devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
+
+ sprintf(tmp, ati_name_1[1], framebuffer);
+ devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
+
+ sprintf(tmp, "bt(0,0)/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);
+ if (getBoolForKey(kUseAtiROMKey, &doit, &bootInfo->bootConfig) && doit) {
+ verbose("looking for ati video bios file %s\n", tmp);
+ rom = malloc(0x20000);
+ rom_size = load_ati_bios_file(tmp, rom, 0x20000);
+ if (rom_size > 0) {
+ verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);
+ if (rom_size > 0x10000) {
+ rom_size = 0x10000; //we dont need rest anyway;
+ }
+ } else {
+ printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);
+ }
+ }
+ if (rom_size == 0) {
+ if (boot_display) { // no custom rom
+ bios = NULL; // try to dump from legacy space, otherwise can result in 100% fan speed
+ } else {
+ // readAtomBios result in bug on some cards (100% fan speed and black screen),
+ // not using it for posted card, reading from legacy space instead
+ bios = readAtomBIOS(ati_dev);
+ }
+ } else {
+ bios = rom; //going custom rom way
+ verbose("Using rom %s\n", tmp);
+ }
+ if (bios == NULL) {
+ bios = (uint8_t *)0x000C0000;
+ toFree = false;
+ verbose("Not going to use bios image file\n");
+ } else {
+ toFree = true;
+ }
+
+ if (bios[0] == 0x55 && bios[1] == 0xaa) {
+ verbose("Found bios image\n");
+ bios_size = bios[2] * 512;
+
+ struct pci_rom_pci_header_t *rom_pci_header;
+ rom_pci_header = (struct pci_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);
+
+ if (rom_pci_header->signature == 0x52494350) {
+ if (rom_pci_header->device != ati_dev->device_id) {
+ verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device, ati_dev->device_id);
+ } else {
+ if (toFree)
+ {
+ //Azi: mmio, Memory-mapped I/O - Kabyl's smbios patcher stuff reminder.
+ verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);
+ } else {
+ verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);
+ }
+ devprop_add_value(device, "ATY,bin_image", bios, bios_size);
+ }
+ } else {
+ verbose("Wrong pci header signature %x\n", rom_pci_header->signature);
+ }
+ } else {
+ verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
+ }
+ if (toFree) {
+ free(bios);
+ }
+ stringdata = malloc(sizeof(uint8_t) * string->length);
+ memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
+ stringlength = string->length;
+
+ return true;
+}