Index: trunk/i386/libsaio/cpu.c
===================================================================
--- trunk/i386/libsaio/cpu.c	(revision 906)
+++ trunk/i386/libsaio/cpu.c	(revision 907)
@@ -136,7 +136,11 @@
 	
     p->CPU.Model += (p->CPU.ExtModel << 4);
     
-    if (p->CPU.Vendor == 0x756E6547 /* Intel */ && p->CPU.Family == 0x06 && p->CPU.Model >= 0x1a){
+    if (p->CPU.Vendor == 0x756E6547 /* Intel */ && 
+        p->CPU.Family == 0x06 && 
+        p->CPU.Model >= CPUID_MODEL_PENRYN && 
+        p->CPU.Model != CPUID_MODEL_ATOM        // MSR is *NOT* available on the Intel Atom CPU
+        ){
         msr = rdmsr64(MSR_CORE_THREAD_COUNT);									// Undocumented MSR in Nehalem and newer CPUs
         p->CPU.NoCores		= bitfield((uint32_t)msr, 31, 16);					// Using undocumented MSR to get actual values
         p->CPU.NoThreads	= bitfield((uint32_t)msr, 15,  0);					// Using undocumented MSR to get actual values
Index: trunk/i386/libsaio/cpu.h
===================================================================
--- trunk/i386/libsaio/cpu.h	(revision 906)
+++ trunk/i386/libsaio/cpu.h	(revision 907)
@@ -36,6 +36,20 @@
 #define CALIBRATE_TIME_MSEC	30		/* 30 msecs */
 #define CALIBRATE_LATCH		((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
 
+// CPUID Values
+#define CPUID_MODEL_YONAH	14
+#define CPUID_MODEL_MEROM	15
+#define CPUID_MODEL_PENRYN	23
+#define CPUID_MODEL_NEHALEM	26
+#define CPUID_MODEL_ATOM    28
+#define CPUID_MODEL_FIELDS	30	/* Lynnfield, Clarksfield, Jasper */
+#define CPUID_MODEL_DALES	31	/* Havendale, Auburndale */
+#define CPUID_MODEL_NEHALEM_EX	46
+#define CPUID_MODEL_DALES_32NM	37	/* Clarkdale, Arrandale */
+#define CPUID_MODEL_WESTMERE	44	/* Gulftown, Westmere-EP, Westmere-WS */
+#define CPUID_MODEL_WESTMERE_EX	47
+
+
 static inline uint64_t rdtsc64(void)
 {
 	uint64_t ret;