Index: trunk/i386/libsaio/acpi_patcher.c =================================================================== --- trunk/i386/libsaio/acpi_patcher.c (revision 968) +++ trunk/i386/libsaio/acpi_patcher.c (revision 969) @@ -365,11 +365,11 @@ { switch (Platform.CPU.Model) { - case 0x0D: // ? - case CPU_MODEL_YONAH: // Yonah - case CPU_MODEL_MEROM: // Merom - case CPU_MODEL_PENRYN: // Penryn - case CPU_MODEL_ATOM: // Intel Atom (45nm) + case 0x0D: // ??? + case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo + case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx + case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx + case CPU_MODEL_ATOM: // Intel Atom (45nm) { bool cpu_dynamic_fsb = false; @@ -487,15 +487,15 @@ break; } - case CPU_MODEL_FIELDS: - case CPU_MODEL_DALES: - case CPU_MODEL_DALES_32NM: - case CPU_MODEL_NEHALEM: - case CPU_MODEL_NEHALEM_EX: - case CPU_MODEL_WESTMERE: - case CPU_MODEL_WESTMERE_EX: - case CPU_MODEL_SANDY: - case CPU_MODEL_SANDY_XEON: + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 + case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 { maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)... minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff; Index: trunk/i386/libsaio/memvendors.h =================================================================== --- trunk/i386/libsaio/memvendors.h (revision 968) +++ trunk/i386/libsaio/memvendors.h (revision 969) @@ -14,7 +14,7 @@ } VenIdName; VenIdName vendorMap[] = { - { 0, 0x01, "AMD"}, + { 0, 0x01, "AMD"}, { 0, 0x02, "AMI"}, { 0, 0x83, "Fairchild"}, { 0, 0x04, "Fujitsu"}, Index: trunk/i386/libsaio/platform.h =================================================================== --- trunk/i386/libsaio/platform.h (revision 968) +++ trunk/i386/libsaio/platform.h (revision 969) @@ -23,18 +23,18 @@ #define CPUID_81 6 #define CPUID_MAX 7 -#define CPU_MODEL_YONAH 0x0E -#define CPU_MODEL_MEROM 0x0F -#define CPU_MODEL_PENRYN 0x17 -#define CPU_MODEL_NEHALEM 0x1A -#define CPU_MODEL_ATOM 0x1C -#define CPU_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield, Jasper */ -#define CPU_MODEL_DALES 0x1F /* Havendale, Auburndale */ -#define CPU_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */ -#define CPU_MODEL_SANDY 0x2a /* Sandy bridge */ -#define CPU_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP, Westmere-WS */ -#define CPU_MODEL_SANDY_XEON 0x2D -#define CPU_MODEL_NEHALEM_EX 0x2E +#define CPU_MODEL_YONAH 0x0E // Sossaman, Yonah +#define CPU_MODEL_MEROM 0x0F // Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom +#define CPU_MODEL_PENRYN 0x17 // Wolfdale, Yorkfield, Harpertown, Penryn +#define CPU_MODEL_NEHALEM 0x1A // Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown +#define CPU_MODEL_ATOM 0x1C // Atom +#define CPU_MODEL_FIELDS 0x1E // Lynnfield, Clarksfield, Jasper Forest +#define CPU_MODEL_DALES 0x1F // Havendale, Auburndale +#define CPU_MODEL_DALES_32NM 0x25 // Clarkdale, Arrandale +#define CPU_MODEL_SANDY 0x2A // Sandy Bridge +#define CPU_MODEL_WESTMERE 0x2C // Gulftown, Westmere-EP, Westmere-WS +#define CPU_MODEL_SANDY_XEON 0x2D // Sandy Bridge Xeon +#define CPU_MODEL_NEHALEM_EX 0x2E // Beckton #define CPU_MODEL_WESTMERE_EX 0x2F /* CPU Features */ Index: trunk/i386/libsaio/cpu.h =================================================================== --- trunk/i386/libsaio/cpu.h (revision 968) +++ trunk/i386/libsaio/cpu.h (revision 969) @@ -37,17 +37,17 @@ #define CALIBRATE_LATCH ((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000) // CPUID Values -#define CPUID_MODEL_YONAH 14 -#define CPUID_MODEL_MEROM 15 -#define CPUID_MODEL_PENRYN 23 -#define CPUID_MODEL_NEHALEM 26 -#define CPUID_MODEL_ATOM 28 -#define CPUID_MODEL_FIELDS 30 /* Lynnfield, Clarksfield, Jasper */ -#define CPUID_MODEL_DALES 31 /* Havendale, Auburndale */ -#define CPUID_MODEL_NEHALEM_EX 46 -#define CPUID_MODEL_DALES_32NM 37 /* Clarkdale, Arrandale */ -#define CPUID_MODEL_WESTMERE 44 /* Gulftown, Westmere-EP, Westmere-WS */ -#define CPUID_MODEL_WESTMERE_EX 47 +#define CPUID_MODEL_YONAH 14 // Intel Mobile Core Solo, Duo +#define CPUID_MODEL_MEROM 15 // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx +#define CPUID_MODEL_PENRYN 23 // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx +#define CPUID_MODEL_NEHALEM 26 // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) +#define CPUID_MODEL_ATOM 28 // Intel Atom (45nm) +#define CPUID_MODEL_FIELDS 30 // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) +#define CPUID_MODEL_DALES 31 // Havendale, Auburndale +#define CPUID_MODEL_NEHALEM_EX 46 // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x +#define CPUID_MODEL_DALES_32NM 37 // Intel Core i3, i5 LGA1156 (32nm) +#define CPUID_MODEL_WESTMERE 44 // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core +#define CPUID_MODEL_WESTMERE_EX 47 // Intel Xeon E7 static inline uint64_t rdtsc64(void) Index: trunk/i386/libsaio/smbios.c =================================================================== --- trunk/i386/libsaio/smbios.c (revision 968) +++ trunk/i386/libsaio/smbios.c (revision 969) @@ -325,30 +325,30 @@ { switch (Platform.CPU.Model) { - case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) - case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) - case 0x19: // Intel Core i5 650 @3.20 Ghz + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case 0x19: // ??? Intel Core i5 650 @3.20 GHz defaultBIOSInfo.version = kDefaultiMacNehalemBIOSVersion; defaultSystemInfo.productName = kDefaultiMacNehalem; defaultSystemInfo.family = kDefaultiMacFamily; break; - case CPU_MODEL_SANDY: - case CPU_MODEL_SANDY_XEON: + case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 defaultBIOSInfo.version = kDefaultiMacSandyBIOSVersion; defaultSystemInfo.productName = kDefaultiMacSandy; defaultSystemInfo.family = kDefaultiMacFamily; break; - case CPU_MODEL_NEHALEM: - case CPU_MODEL_NEHALEM_EX: + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x defaultBIOSInfo.version = kDefaultMacProNehalemBIOSVersion; defaultSystemInfo.productName = kDefaultMacProNehalem; defaultSystemInfo.family = kDefaultMacProFamily; break; - case CPU_MODEL_WESTMERE: - case CPU_MODEL_WESTMERE_EX: + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 defaultBIOSInfo.version = kDefaultMacProWestmereBIOSVersion; defaultBIOSInfo.releaseDate = kDefaulMacProWestmereBIOSReleaseDate; defaultSystemInfo.productName = kDefaultMacProWestmere; @@ -546,14 +546,14 @@ { switch (Platform.CPU.Model) { - case 0x19: // Intel Core i5 650 @3.20 Ghz - case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) - case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) - case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) - case CPU_MODEL_NEHALEM_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? - case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core - case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + case 0x19: // ??? Intel Core i5 650 @3.20 GHz + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) + case CPU_MODEL_DALES: + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) + case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 break; default: Index: trunk/i386/libsaio/smbios_getters.c =================================================================== --- trunk/i386/libsaio/smbios_getters.c (revision 968) +++ trunk/i386/libsaio/smbios_getters.c (revision 969) @@ -40,14 +40,14 @@ { switch (Platform.CPU.Model) { - case 0x0D: // ? + case 0x0D: // ??? case CPU_MODEL_YONAH: // Yonah 0x0E case CPU_MODEL_MEROM: // Merom 0x0F case CPU_MODEL_PENRYN: // Penryn 0x17 case CPU_MODEL_ATOM: // Atom 45nm 0x1C return false; - case 0x19: // Intel Core i5 650 @3.20 Ghz + case 0x19: // ??? Intel Core i5 650 @3.20 GHz case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm) case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ??? @@ -127,14 +127,14 @@ { switch (Platform.CPU.Model) { - case 0x0D: // ? - case CPU_MODEL_YONAH: // Yonah - case CPU_MODEL_MEROM: // Merom - case CPU_MODEL_PENRYN: // Penryn + case 0x0D: // ??? + case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo + case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx + case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx case CPU_MODEL_ATOM: // Intel Atom (45nm) return true; - case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm) + case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm) if (strstr(Platform.CPU.BrandString, "Xeon(R)")) value->word = 0x0501; // Xeon else @@ -142,23 +142,23 @@ return true; - case CPU_MODEL_FIELDS: // Lynnfield, Clarksfield, Jasper + case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm) if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) value->word = 0x601; // Core i5 else value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale) + case CPU_MODEL_DALES: // Havendale, Auburndale if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) value->word = 0x601; // Core i5 else value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 sandy bridge - case CPU_MODEL_SANDY_XEON: - case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale) + case CPU_MODEL_SANDY: // Intel Core i3, i5, i7 LGA1155 (32nm) + case CPU_MODEL_SANDY_XEON: // Intel Xeon E3 + case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm) if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) value->word = 0x901; // Core i3 else @@ -168,12 +168,12 @@ value->word = 0x0701; // Core i7 return true; - case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS) - case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ??? + case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core + case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7 value->word = 0x0501; // Core i7 return true; - case 0x19: // Intel Core i5 650 @3.20 Ghz + case 0x19: // ??? Intel Core i5 650 @3.20 GHz value->word = 0x601; // Core i5 return true; } Index: trunk/i386/boot2/boot.h =================================================================== --- trunk/i386/boot2/boot.h (revision 968) +++ trunk/i386/boot2/boot.h (revision 969) @@ -59,6 +59,15 @@ #define kBootBannerKey "Boot Banner" #define kWaitForKeypressKey "Wait" +#define kDSDT "DSDT" /* acpi_patcher.c */ +#define kDropSSDT "DropSSDT" /* acpi_patcher.c */ +#define kRestartFix "RestartFix" /* acpi_patcher.c */ +#define kGeneratePStates "GeneratePStates" /* acpi_patcher.c */ +#define kGenerateCStates "GenerateCStates" /* acpi_patcher.c */ +#define kEnableC2States "EnableC2State" /* acpi_patcher.c */ +#define kEnableC3States "EnableC3State" /* acpi_patcher.c */ +#define kEnableC4States "EnableC4State" /* acpi_patcher.c */ + #define kUseAtiROM "UseAtiROM" /* ati.c */ #define kAtiConfig "AtiConfig" /* ati.c */ #define kATYbinimage "ATYbinimage" /* ati.c */ @@ -70,14 +79,7 @@ #define karch "arch" /* boot.c */ #define kUseKernelCache "UseKernelCache" /* boot.c */ -#define kDSDT "DSDT" /* acpi_patcher.c */ -#define kDropSSDT "DropSSDT" /* acpi_patcher.c */ -#define kRestartFix "RestartFix" /* acpi_patcher.c */ -#define kGeneratePStates "GeneratePStates" /* acpi_patcher.c */ -#define kGenerateCStates "GenerateCStates" /* acpi_patcher.c */ -#define kEnableC2States "EnableC2State" /* acpi_patcher.c */ -#define kEnableC3States "EnableC3State" /* acpi_patcher.c */ -#define kEnableC4States "EnableC4State" /* acpi_patcher.c */ +#define kbusratio "busratio" /* cpu.c */ #define kDeviceProperties "device-properties" /* device_inject.c */ @@ -99,18 +101,18 @@ #define kUseMemDetect "UseMemDetect" /* platform.c */ +#define kMD0Image "md0" /* ramdisk.h */ + #define kSMBIOSdefaults "SMBIOSdefaults" /* smbios_patcher.c */ +#define kDefaultPartition "Default Partition" /* sys.c */ + #define kUSBBusFix "USBBusFix" /* usb.c */ #define kEHCIacquire "EHCIacquire" /* usb.c */ #define kUHCIreset "UHCIreset" /* usb.c */ #define kLegacyOff "USBLegacyOff" /* usb.c */ #define kEHCIhard "EHCIhard" /* usb.c */ -#define kDefaultPartition "Default Partition" /* sys.c */ -#define kMD0Image "md0" /* ramdisk.h */ -#define kbusratio "busratio" /* cpu.c */ - /* * Flags to the booter or kernel */ Index: trunk/i386/libsa/memory.h =================================================================== --- trunk/i386/libsa/memory.h (revision 968) +++ trunk/i386/libsa/memory.h (revision 969) @@ -48,7 +48,7 @@ # define BASE_SEG BOOT2_SEG #endif -#define STACK_SEG 0x1000 // zef: old STACK_SEG 0x5000 +#define STACK_SEG 0x1000 // zef: old STACK_SEG 0x5000 #define STACK_OFS 0xFFF0 // stack pointer #define BOOT1U_SEG 0x1000 Index: trunk/doc/BootHelp.txt =================================================================== --- trunk/doc/BootHelp.txt (revision 968) +++ trunk/doc/BootHelp.txt (revision 969) @@ -2,55 +2,55 @@ If you don't type anything, the computer continues starting up normally. It uses the kernel and configuration files on the startup device, which it also uses as the root device. - + Advanced startup options use the following syntax: - + [device] [arguments] - + Example arguments include - + device: rd= (e.g. rd=disk0s2) rd=* (e.g. rd=*/PCI0@0/CHN0@0/@0:1) - + kernel: kernel name (e.g. "mach_kernel" - must be in "/" ) - + flags: -v (verbose) -s (single user mode) -x (safe mode) -f (ignore caches) -F (ignore "Kernel Flags" specified in boot configuration file) - + "Graphics Mode"="WIDTHxHEIGHTxDEPTH" (e.g. "1024x768x32") - + kernel flags (e.g. debug=0x144) io=0xffffffff (defined in IOKit/IOKitDebug.h) - + Example: mach_kernel rd=disk0s1 -v "Graphics Mode"="1920x1200x32" - + If the computer won't start up properly, you may be able to start it up using safe mode. Type -x to start up in safe mode, which ignores all cached driver files. - + Special booter hotkeys: F5 Rescans optical drive. F10 Scans and displays all BIOS accessible drives. - + Special booter commands: ?memory Displays information about the computer's memory. ?video Displays VESA video modes supported by the computer's BIOS. ?norescan Leaves optical drive rescan mode. - + Additional useful command-line options: config= Use an alternate Boot.plist file. - + Options useful in the com.apple.Boot.plist file: Wait=Yes|No Prompt for a key press before starting the kernel. "Quiet Boot"=Yes|No Use quiet boot mode (no messages or prompt). Timeout=8 Number of seconds to pause at the boot: prompt. "Instant Menu"=Yes Force displaying the partition selection menu. - + "Default Partition" Sets the default boot partition, =hd(x,y)|UUID|"Label" Specified as a disk/partition pair, an UUID, or a label enclosed in quotes. - + "Hide Partition" Remove unwanted partition(s) from the boot menu. =partition Specified, possibly multiple times, as hd(x,y), an [;partition2 ...] UUID or label enclosed in quotes. @@ -59,57 +59,60 @@ =partition Where partition is hd(x,y), UUID or label enclosed [;partition2 in quotes. The alias can optionally be quoted too. ...] - + GUI=No Disable the GUI (enabled by default). "Boot Banner"=Yes|No Show boot banner in GUI mode (enabled by default). "Legacy Logo"=Yes|No Use the legacy grey apple logo (disabled by default). - + PciRoot= Use an alternate value for PciRoot (default value 0). - + + UseKernelCache=Yes|No Default is No. Yes will load pre-linked kernel and will + ignore /E/E and /S/L/E/Extensions.mkext. + GraphicsEnabler=Yes|No Automatic device-properties generation for gfx cards. - UseAtiROM=Yes|No Use an alternate Ati ROM image - (path: /Extra/__.rom) - UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image - (path: /Extra/_.rom) - VBIOS=Yes|No Inject VBIOS to device-properties. - - AtiConfig= Use a different card config (the list can be found in ati.c). - + AtiConfig= Use a different card config + UseAtiROM=Yes|No Use an alternate Ati ROM image + (path: /Extra/__.rom) + UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image + (path: /Extra/_.rom) + VBIOS=Yes|No Inject NVIDIA VBIOS into device-properties. + EthernetBuiltIn=Yes|No Automatic "built-in"=yes device-properties generation for ethernet interfaces. - + USBBusFix=Yes Enable all USB fixes below: EHCIacquire=Yes Enable the EHCI fix (disabled by default). UHCIreset=Yes Enable the UHCI fix (disabled by default). USBLegacyOff=Yes Enable the USB Legacy fix (disabled by default). - + ForceHPET=Yes|No Force Enable HPET. - + Wake=No Disable wake up after hibernation (default: enabled). ForceWake=Yes Force using the sleepimage (disabled by default). WakeImage= Use an alternate sleepimage file. (default path is /private/var/vm/sleepimage). - + DropSSDT=Yes Skip the SSDT tables while relocating the ACPI tables. DSDT= Use an alternate DSDT.aml file (default paths: /DSDT.aml /Extra/DSDT.aml bt(0,0)/Extra/DSDT.aml). - - GenerateCStates=Yes Enable auto generation of Processor (C-States) and/or - GeneratePStates=Yes Performance (P-States) power states. - - EnableC2State=Yes Enable specific Processor power states, C2, - EnableC3State=Yes C3 - EnableC4State=Yes and C4. - + + GenerateCStates=Yes Enable auto generation of processor idle sleep states + (C-States). + GeneratePStates=Yes Enable auto generation of processor power performance + states (P-States). + + EnableC2State=Yes Enable specific Processor power state, C2. + EnableC3State=Yes Enable specific Processor power state, C3. + EnableC4State=Yes Enable specific Processor power state, C4. + SMBIOS= Use an alternate SMBIOS.plist file (default paths: /Extra/SMBIOS.plist bt(0,0)/Extra/SMBIOS.plist). - - SMBIOSdefaults=No Don't use the Default values for SMBIOS overriding - if smbios.plist doesn't exist, factory - values are kept. - + + SMBIOSdefaults=No Don't use the Default values for SMBIOS overriding if + smbios.plist doesn't exist, factory values are kept. + "Scan Single Drive" Scan the drive only where the booter got loaded from. =Yes|No Fix rescan pbs when using a DVD reader in AHCI mode. Rescan=Yes Enable CD-ROM rescan mode.