Chameleon

Chameleon Svn Source Tree

Root/branches/azimutz/trunkGraphicsEnablerModules/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉value->word = Platform.CPU.FSBFrequency/1000000;␊
25␉return true;␊
26}␊
27␊
28bool getProcessorInformationMaximumClock(returnType *value)␊
29{␊
30␉value->word = Platform.CPU.CPUFrequency/1000000;␊
31␉return true;␊
32}␊
33␊
34bool getSMBOemProcessorBusSpeed(returnType *value)␊
35{␊
36␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
37␉{␉␉␊
38␉␉switch (Platform.CPU.Family) ␊
39␉␉{␊
40␉␉␉case 0x06:␊
41␉␉␉{␊
42␉␉␉␉switch (Platform.CPU.Model)␊
43␉␉␉␉{␊
44␉␉␉␉␉case 0x0D:␉␉␉␉␉// ???␊
45␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
46␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
47␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
48␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
49␉␉␉␉␉␉return false;␊
50␊
51␉␉␉␉␉case 0x19:␉␉␉␉␉// ??? Intel Core i5 650 @3.20 GHz ␊
52␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
53␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
54␉␉␉␉␉case CPU_MODEL_DALES:␊
55␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
56␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
57␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
58␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
59␉␉␉␉␉{␊
60␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
61␉␉␉␉␉␉int nhm_bus = 0x3F;␊
62␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
63␉␉␉␉␉␉unsigned long did, vid;␊
64␉␉␉␉␉␉int i;␊
65␉␉␉␉␉␉␊
66␉␉␉␉␉␉// Nehalem supports Scrubbing␊
67␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
68␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
69␉␉␉␉␉␉{␊
70␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
71␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
72␉␉␉␉␉␉␉vid &= 0xFFFF;␊
73␉␉␉␉␉␉␉did &= 0xFF00;␊
74␉␉␉␉␉␉␉␊
75␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
76␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
77␉␉␉␉␉␉}␊
78␉␉␉␉␉␉␊
79␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
80␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
81␉␉␉␉␉␉qpimult &= 0x7F;␊
82␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
83␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
84␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
85␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
86␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
87␉␉␉␉␉␉value->word = qpibusspeed;␊
88␉␉␉␉␉␉return true;␊
89␉␉␉␉␉}␊
90␉␉␉␉}␊
91␉␉␉}␊
92␉␉}␊
93␉}␊
94␉return false;␊
95}␊
96␊
97uint16_t simpleGetSMBOemProcessorType(void)␊
98{␊
99␉if (Platform.CPU.NoCores >= 4) ␊
100␉{␊
101␉␉return 0x0501;␉// Quad-Core Xeon␊
102␉}␊
103␉else if (Platform.CPU.NoCores == 1) ␊
104␉{␊
105␉␉return 0x0201;␉// Core Solo␊
106␉};␊
107␉␊
108␉return 0x0301;␉␉// Core 2 Duo␊
109}␊
110␊
111bool getSMBOemProcessorType(returnType *value)␊
112{␊
113␉static bool done = false;␉␉␊
114␉␉␊
115␉value->word = simpleGetSMBOemProcessorType();␊
116␊
117␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
118␉{␊
119␉␉if (!done)␊
120␉␉{␊
121␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
122␉␉␉done = true;␊
123␉␉}␊
124␉␉␊
125␉␉switch (Platform.CPU.Family) ␊
126␉␉{␊
127␉␉␉case 0x06:␊
128␉␉␉{␊
129␉␉␉␉switch (Platform.CPU.Model)␊
130␉␉␉␉{␊
131␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ???␊
132␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
133␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
134␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
135␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
136␉␉␉␉␉␉return true;␊
137␊
138␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
139␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
140␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
141␉␉␉␉␉␉else␊
142␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
143␊
144␉␉␉␉␉␉return true;␊
145␊
146␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
147␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
148␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
149␉␉␉␉␉␉else␊
150␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
151␉␉␉␉␉␉return true;␊
152␊
153␉␉␉␉␉case CPU_MODEL_DALES:␊
154␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
155␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
156␉␉␉␉␉␉else␊
157␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
158␉␉␉␉␉␉return true;␊
159␊
160␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
161 case CPU_MODEL_SANDY_XEON:␉␉␉// Intel Xeon E3␊
162␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
163␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
164␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
165␉␉␉␉␉␉else␊
166␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
167␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
168␉␉␉␉␉␉␉else␊
169␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
170␉␉␉␉␉␉return true;␊
171␊
172␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
173␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
174␉␉␉␉␉␉value->word = 0x0501;␉␉␉␉// Core i7␊
175␉␉␉␉␉␉return true;␊
176␊
177␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// ??? Intel Core i5 650 @3.20 GHz␊
178␉␉␉␉␉␉value->word = 0x0601;␉␉␉␉// Core i5␊
179␉␉␉␉␉␉return true;␊
180␉␉␉␉}␊
181␉␉␉}␊
182␉␉}␊
183␉}␊
184␉␊
185␉return false;␊
186}␊
187␊
188bool getSMBMemoryDeviceMemoryType(returnType *value)␊
189{␊
190␉static int idx = -1;␊
191␉int␉map;␊
192␊
193␉idx++;␊
194␉if (idx < MAX_RAM_SLOTS)␊
195␉{␊
196␉␉map = Platform.DMI.DIMM[idx];␊
197␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
198␉␉{␊
199␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
200␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
201␉␉␉return true;␊
202␉␉}␊
203␉}␊
204␉␊
205␉return false;␊
206//␉value->byte = SMB_MEM_TYPE_DDR2;␊
207//␉return true;␊
208}␊
209␊
210bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
211{␊
212␉static int idx = -1;␊
213␉int␉map;␊
214␊
215␉idx++;␊
216␉if (idx < MAX_RAM_SLOTS)␊
217␉{␊
218␉␉map = Platform.DMI.DIMM[idx];␊
219␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
220␉␉{␊
221␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
222␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
223␉␉␉return true;␊
224␉␉}␊
225␉}␊
226␊
227␉return false;␊
228//␉value->dword = 800;␊
229//␉return true;␊
230}␊
231␊
232bool getSMBMemoryDeviceManufacturer(returnType *value)␊
233{␊
234␉static int idx = -1;␊
235␉int␉map;␊
236␊
237␉idx++;␊
238␉if (idx < MAX_RAM_SLOTS)␊
239␉{␊
240␉␉map = Platform.DMI.DIMM[idx];␊
241␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
242␉␉{␊
243␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
244␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
245␉␉␉return true;␊
246␉␉}␊
247␉}␊
248␊
249␉if (!bootInfo->memDetect)␊
250␉␉return false;␊
251␉value->string = NOT_AVAILABLE;␊
252␉return true;␊
253}␊
254␉␊
255bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
256{␊
257␉static int idx = -1;␊
258␉int␉map;␊
259␊
260␉idx++;␊
261␊
262 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
263␊
264␉if (idx < MAX_RAM_SLOTS)␊
265␉{␊
266␉␉map = Platform.DMI.DIMM[idx];␊
267␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
268␉␉{␊
269␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
270␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
271␉␉␉return true;␊
272␉␉}␊
273␉}␊
274␊
275␉if (!bootInfo->memDetect)␊
276␉␉return false;␊
277␉value->string = NOT_AVAILABLE;␊
278␉return true;␊
279}␊
280␊
281bool getSMBMemoryDevicePartNumber(returnType *value)␊
282{␊
283␉static int idx = -1;␊
284␉int␉map;␊
285␊
286␉idx++;␊
287␉if (idx < MAX_RAM_SLOTS)␊
288␉{␊
289␉␉map = Platform.DMI.DIMM[idx];␊
290␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
291␉␉{␊
292␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
293␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
294␉␉␉return true;␊
295␉␉}␊
296␉}␊
297␊
298␉if (!bootInfo->memDetect)␊
299␉␉return false;␊
300␉value->string = NOT_AVAILABLE;␊
301␉return true;␊
302}␊
303␊
304␊
305// getting smbios addr with fast compare ops, late checksum testing ...␊
306#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
307static const char * const SMTAG = "_SM_";␊
308static const char* const DMITAG = "_DMI_";␊
309␊
310SMBEntryPoint *getAddressOfSmbiosTable(void)␊
311{␊
312␉SMBEntryPoint␉*smbios;␊
313␉/* ␊
314␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
315␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
316␉ */␊
317␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
318␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
319␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
320␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
321␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
322␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
323␉ {␊
324␉␉␉return smbios;␊
325␉ }␊
326␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
327␉}␊
328␉printf("ERROR: Unable to find SMBIOS!\n");␊
329␉pause();␊
330␉return NULL;␊
331}␊
332␊
333

Archive Download this file

Revision: 1040