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Source at commit 106 created 14 years 2 months ago. By diebuche, Adding 915patch and edid | |
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1 | /* Copied from 915 resolution created by steve tomljenovic␊ |
2 | * This source code is into the public domain.␊ |
3 | *␊ |
4 | * Included to Chameleon RC3 by meklort␊ |
5 | *␊ |
6 | * Included to RC4 and edited by deviato to match more intel chipsets␊ |
7 | *␊ |
8 | */␊ |
9 | ␊ |
10 | #ifndef __915_RESOLUTION_H␊ |
11 | #define __915_RESOLUTION_H␊ |
12 | ␊ |
13 | #define NEW(a) ((a *)(malloc(sizeof(a))))␊ |
14 | #define FREE(a) (free(a))␊ |
15 | ␊ |
16 | #define VBIOS_START 0xc0000␊ |
17 | #define VBIOS_SIZE 0x10000␊ |
18 | ␊ |
19 | #define FALSE 0␊ |
20 | #define TRUE 1␊ |
21 | ␊ |
22 | #define MODE_TABLE_OFFSET_845G 617␊ |
23 | ␊ |
24 | ␊ |
25 | #define ATI_SIGNATURE1 "ATI MOBILITY RADEON"␊ |
26 | #define ATI_SIGNATURE2 "ATI Technologies Inc"␊ |
27 | #define NVIDIA_SIGNATURE "NVIDIA Corp"␊ |
28 | #define INTEL_SIGNATURE "Intel Corp"␊ |
29 | ␊ |
30 | ␊ |
31 | ␊ |
32 | ␊ |
33 | typedef enum {␊ |
34 | ␉CT_UNKWN, CT_830, CT_845G, CT_855GM, CT_865G, CT_915G, CT_915GM, CT_945G, CT_945GM, CT_945GME,␊ |
35 | ␉CT_946GZ, CT_G965, CT_Q965, CT_965GM, CT_GM45, CT_G41, CT_G31, CT_G45, CT_500␊ |
36 | } chipset_type;␊ |
37 | ␊ |
38 | ␊ |
39 | typedef enum {␊ |
40 | ␉BT_UNKWN, BT_1, BT_2, BT_3␊ |
41 | } bios_type;␊ |
42 | ␊ |
43 | ␊ |
44 | typedef struct {␊ |
45 | ␉UInt8 mode;␊ |
46 | ␉UInt8 bits_per_pixel;␊ |
47 | ␉UInt16 resolution;␊ |
48 | ␉UInt8 unknown;␊ |
49 | } __attribute__((packed)) vbios_mode;␊ |
50 | ␊ |
51 | typedef struct {␊ |
52 | ␉UInt8 unknow1[2];␊ |
53 | ␉UInt8 x1;␊ |
54 | ␉UInt8 x_total;␊ |
55 | ␉UInt8 x2;␊ |
56 | ␉UInt8 y1;␊ |
57 | ␉UInt8 y_total;␊ |
58 | ␉UInt8 y2;␊ |
59 | } __attribute__((packed)) vbios_resolution_type1;␊ |
60 | ␊ |
61 | typedef struct {␊ |
62 | ␉unsigned long clock;␊ |
63 | ␉␊ |
64 | ␉UInt16 x1;␊ |
65 | ␉UInt16 htotal;␊ |
66 | ␉UInt16 x2;␊ |
67 | ␉UInt16 hblank;␊ |
68 | ␉UInt16 hsyncstart;␊ |
69 | ␉UInt16 hsyncend;␊ |
70 | ␉UInt16 y1;␊ |
71 | UInt16 vtotal;␊ |
72 | UInt16 y2;␊ |
73 | ␉UInt16 vblank;␊ |
74 | ␉UInt16 vsyncstart;␊ |
75 | ␉UInt16 vsyncend;␊ |
76 | } __attribute__((packed)) vbios_modeline_type2;␊ |
77 | ␊ |
78 | typedef struct {␊ |
79 | ␉UInt8 xchars;␊ |
80 | ␉UInt8 ychars;␊ |
81 | ␉UInt8 unknown[4];␊ |
82 | ␉␊ |
83 | ␉vbios_modeline_type2 modelines[];␊ |
84 | } __attribute__((packed)) vbios_resolution_type2;␊ |
85 | ␊ |
86 | typedef struct {␊ |
87 | ␉unsigned long clock;␊ |
88 | ␉␊ |
89 | ␉UInt16 x1;␊ |
90 | ␉UInt16 htotal;␊ |
91 | ␉UInt16 x2;␊ |
92 | ␉UInt16 hblank;␊ |
93 | ␉UInt16 hsyncstart;␊ |
94 | ␉UInt16 hsyncend;␊ |
95 | ␉␊ |
96 | ␉UInt16 y1;␊ |
97 | ␉UInt16 vtotal;␊ |
98 | ␉UInt16 y2;␊ |
99 | ␉UInt16 vblank;␊ |
100 | ␉UInt16 vsyncstart;␊ |
101 | ␉UInt16 vsyncend;␊ |
102 | ␉␊ |
103 | ␉UInt16 timing_h;␊ |
104 | ␉UInt16 timing_v;␊ |
105 | ␉␊ |
106 | ␉UInt8 unknown[6];␊ |
107 | } __attribute__((packed)) vbios_modeline_type3;␊ |
108 | ␊ |
109 | typedef struct {␊ |
110 | ␉unsigned char unknown[6];␊ |
111 | ␉␊ |
112 | vbios_modeline_type3 modelines[];␊ |
113 | } __attribute__((packed)) vbios_resolution_type3;␊ |
114 | ␊ |
115 | typedef struct {␊ |
116 | ␉UInt32 chipset_id;␊ |
117 | ␉chipset_type chipset;␊ |
118 | ␉bios_type bios;␊ |
119 | ␉␊ |
120 | ␉UInt32 bios_fd;␊ |
121 | ␉char* bios_ptr;␊ |
122 | ␉␊ |
123 | ␉vbios_mode * mode_table;␊ |
124 | ␉UInt32 mode_table_size;␊ |
125 | ␉UInt8 b1, b2;␊ |
126 | ␉␊ |
127 | ␉UInt8 unlocked;␊ |
128 | } vbios_map;␊ |
129 | ␊ |
130 | ␊ |
131 | ␊ |
132 | void display_map_info(vbios_map*);␊ |
133 | vbios_map * open_vbios(chipset_type);␊ |
134 | void close_vbios (vbios_map*);␊ |
135 | void unlock_vbios(vbios_map*);␊ |
136 | void relock_vbios(vbios_map*);␊ |
137 | void set_mode(vbios_map*, UInt32, UInt32, UInt32, UInt32, UInt32);␊ |
138 | void list_modes(vbios_map *map, UInt32 raw);␊ |
139 | ␊ |
140 | #endif␊ |
141 |