| 1 | /*␊ |
| 2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
| 3 | * AsereBLN: 2009: cleanup and bugfix␊ |
| 4 | */␊ |
| 5 | ␊ |
| 6 | #include "libsaio.h"␊ |
| 7 | #include "platform.h"␊ |
| 8 | #include "cpu.h"␊ |
| 9 | ␊ |
| 10 | #ifndef DEBUG_CPU␊ |
| 11 | #define DEBUG_CPU 0␊ |
| 12 | #endif␊ |
| 13 | ␊ |
| 14 | #if DEBUG_CPU␊ |
| 15 | #define DBG(x...)␉␉printf(x)␊ |
| 16 | #else␊ |
| 17 | #define DBG(x...)␉␉msglog(x)␊ |
| 18 | #endif␊ |
| 19 | ␊ |
| 20 | /*␊ |
| 21 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
| 22 | */␊ |
| 23 | static uint64_t measure_tsc_frequency(void)␊ |
| 24 | {␊ |
| 25 | uint64_t tscStart;␊ |
| 26 | uint64_t tscEnd;␊ |
| 27 | uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
| 28 | unsigned long pollCount;␊ |
| 29 | uint64_t retval = 0;␊ |
| 30 | int i;␊ |
| 31 | ␊ |
| 32 | /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
| 33 | * counter 2. We run this loop 3 times to make sure the cache␊ |
| 34 | * is hot and we take the minimum delta from all of the runs.␊ |
| 35 | * That is to say that we're biased towards measuring the minimum␊ |
| 36 | * number of TSC ticks that occur while waiting for the timer to␊ |
| 37 | * expire. That theoretically helps avoid inconsistencies when␊ |
| 38 | * running under a VM if the TSC is not virtualized and the host␊ |
| 39 | * steals time. The TSC is normally virtualized for VMware.␊ |
| 40 | */␊ |
| 41 | for(i = 0; i < 10; ++i)␊ |
| 42 | {␊ |
| 43 | enable_PIT2();␊ |
| 44 | set_PIT2_mode0(CALIBRATE_LATCH);␊ |
| 45 | tscStart = rdtsc64();␊ |
| 46 | pollCount = poll_PIT2_gate();␊ |
| 47 | tscEnd = rdtsc64();␊ |
| 48 | /* The poll loop must have run at least a few times for accuracy */␊ |
| 49 | if(pollCount <= 1)␊ |
| 50 | continue;␊ |
| 51 | /* The TSC must increment at LEAST once every millisecond. We␊ |
| 52 | * should have waited exactly 30 msec so the TSC delta should␊ |
| 53 | * be >= 30. Anything less and the processor is way too slow.␊ |
| 54 | */␊ |
| 55 | if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
| 56 | continue;␊ |
| 57 | // tscDelta = min(tscDelta, (tscEnd - tscStart))␊ |
| 58 | if( (tscEnd - tscStart) < tscDelta )␊ |
| 59 | tscDelta = tscEnd - tscStart;␊ |
| 60 | }␊ |
| 61 | /* tscDelta is now the least number of TSC ticks the processor made in␊ |
| 62 | * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
| 63 | * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
| 64 | * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
| 65 | * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
| 66 | * dividing by the milliseconds, we simply multiply by 1000.␊ |
| 67 | */␊ |
| 68 | ␊ |
| 69 | /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
| 70 | * that we're going to multiply by 1000 first so we do need at least some␊ |
| 71 | * arithmetic headroom. For now, 32-bit should be enough.␊ |
| 72 | * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
| 73 | */␊ |
| 74 | if(tscDelta > (1ULL<<32))␊ |
| 75 | retval = 0;␊ |
| 76 | else␊ |
| 77 | {␊ |
| 78 | retval = tscDelta * 1000 / 30;␊ |
| 79 | }␊ |
| 80 | disable_PIT2();␊ |
| 81 | return retval;␊ |
| 82 | }␊ |
| 83 | ␊ |
| 84 | /*␊ |
| 85 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
| 86 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
| 87 | * a max multi. (used to calculate the FSB freq.),␊ |
| 88 | * and a current multi. (used to calculate the CPU freq.)␊ |
| 89 | * - fsbFrequency = tscFrequency / multi␊ |
| 90 | * - cpuFrequency = fsbFrequency * multi␊ |
| 91 | */␊ |
| 92 | ␊ |
| 93 | void scan_cpu(PlatformInfo_t *p)␊ |
| 94 | {␊ |
| 95 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊ |
| 96 | ␉uint64_t␉msr;␊ |
| 97 | ␉uint8_t␉␉maxcoef, maxdiv, currcoef, currdiv;␊ |
| 98 | uint32_t␉reg[4];␊ |
| 99 | uint32_t␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
| 100 | uint32_t cores_per_package;␊ |
| 101 | uint32_t logical_per_package;␊ |
| 102 | ␉maxcoef = maxdiv = currcoef = currdiv = 0;␊ |
| 103 | ␉ ␊ |
| 104 | ␉do_cpuid(0, CPUID[0]);␊ |
| 105 | p->CPU.Vendor␉␉= CPUID[CPUID_0][1];␊ |
| 106 | ␊ |
| 107 | do_cpuid2(0x00000004, 0, CPUID[CPUID_4]);␊ |
| 108 | cores_per_package␉␉= bitfield(CPUID[CPUID_4][0], 31, 26) + 1;␊ |
| 109 | ␊ |
| 110 | /* get extended cpuid results */␊ |
| 111 | ␉do_cpuid(0x80000000, reg);␊ |
| 112 | ␉uint32_t cpuid_max_ext = reg[eax];␊ |
| 113 | ␊ |
| 114 | /* get brand string (if supported) */␊ |
| 115 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
| 116 | ␉if (cpuid_max_ext > 0x80000004) {␉␉␊ |
| 117 | char str[128], *s;␊ |
| 118 | ␉␉/*␊ |
| 119 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
| 120 | ␉␉ * be NUL terminated.␊ |
| 121 | ␉␉ */␊ |
| 122 | ␉␉do_cpuid(0x80000002, reg);␊ |
| 123 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
| 124 | ␉␉do_cpuid(0x80000003, reg);␊ |
| 125 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
| 126 | ␉␉do_cpuid(0x80000004, reg);␊ |
| 127 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
| 128 | ␉␉for (s = str; *s != '\0'; s++) {␊ |
| 129 | ␉␉␉if (*s != ' ') break;␊ |
| 130 | ␉␉}␊ |
| 131 | ␉␉␊ |
| 132 | ␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊ |
| 133 | ␉␉␊ |
| 134 | ␉␉if (!strncmp(p->CPU.BrandString, CPUID_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), (unsigned)strlen(CPUID_STRING_UNKNOWN) + 1))) {␊ |
| 135 | /*␊ |
| 136 | * This string means we have a firmware-programmable brand string,␊ |
| 137 | * and the firmware couldn't figure out what sort of CPU we have.␊ |
| 138 | */␊ |
| 139 | p->CPU.BrandString[0] = '\0';␊ |
| 140 | }␊ |
| 141 | ␉} ␊ |
| 142 | ␊ |
| 143 | /* get processor signature and decode */␊ |
| 144 | ␉do_cpuid(1, reg);␊ |
| 145 | ␉p->CPU.Signature = reg[eax];␊ |
| 146 | ␉p->CPU.Stepping = bitfield(reg[eax], 3, 0);␊ |
| 147 | ␉p->CPU.Model = bitfield(reg[eax], 7, 4);␊ |
| 148 | ␉p->CPU.Family = bitfield(reg[eax], 11, 8);␊ |
| 149 | ␉p->CPU.ExtModel = bitfield(reg[eax], 19, 16);␊ |
| 150 | ␉p->CPU.ExtFamily = bitfield(reg[eax], 27, 20);␊ |
| 151 | ␉p->CPU.Brand = bitfield(reg[ebx], 7, 0);␊ |
| 152 | ␉p->CPU.Features = quad(reg[ecx], reg[edx]);␊ |
| 153 | //p->CPU.Type = bitfield(reg[eax], 13, 12);␊ |
| 154 | ␊ |
| 155 | /* Fold extensions into family/model */␊ |
| 156 | ␉if (p->CPU.Family == 0x0f)␊ |
| 157 | ␉␉p->CPU.Family += p->CPU.ExtFamily;␊ |
| 158 | ␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊ |
| 159 | ␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
| 160 | ␊ |
| 161 | if (p->CPU.Features & CPUID_FEATURE_HTT)␊ |
| 162 | ␉␉logical_per_package =␊ |
| 163 | bitfield(reg[ebx], 23, 16);␊ |
| 164 | ␉else␊ |
| 165 | ␉␉logical_per_package = 1;␊ |
| 166 | ␊ |
| 167 | ␉if (cpuid_max_ext >= 0x80000001) {␊ |
| 168 | ␉␉do_cpuid(0x80000001, reg);␊ |
| 169 | ␉␉p->CPU.ExtFeatures =␊ |
| 170 | quad(reg[ecx], reg[edx]);␊ |
| 171 | ␊ |
| 172 | ␉}␊ |
| 173 | ␊ |
| 174 | ␉/* Fold in the Invariant TSC feature bit, if present */␊ |
| 175 | ␉if (cpuid_max_ext >= 0x80000007) {␊ |
| 176 | ␉␉do_cpuid(0x80000007, reg); ␊ |
| 177 | ␉␉p->CPU.ExtFeatures |=␊ |
| 178 | reg[edx] & (uint32_t)CPUID_EXTFEATURE_TSCI;␊ |
| 179 | ␉}␊ |
| 180 | ␊ |
| 181 | /* Find the microcode version number a.k.a. signature a.k.a. BIOS ID */␊ |
| 182 | p->CPU.MicrocodeVersion =␊ |
| 183 | (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);␊ |
| 184 | ␊ |
| 185 | if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ␊ |
| 186 | ␉␉(p->CPU.Family == 0x06)) {␊ |
| 187 | /*␊ |
| 188 | * Find the number of enabled cores and threads␊ |
| 189 | * (which determines whether SMT/Hyperthreading is active).␊ |
| 190 | */␊ |
| 191 | switch (p->CPU.Model) {␊ |
| 192 | /*␊ |
| 193 | * This should be the same as Nehalem but an A0 silicon bug returns␊ |
| 194 | * invalid data in the top 12 bits. Hence, we use only bits [19..16]␊ |
| 195 | * rather than [31..16] for core count - which actually can't exceed 8. ␊ |
| 196 | */␊ |
| 197 | case CPUID_MODEL_DALES_32NM:␊ |
| 198 | case CPUID_MODEL_WESTMERE:␊ |
| 199 | case CPUID_MODEL_WESTMERE_EX:␊ |
| 200 | {␊ |
| 201 | msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
| 202 | p->CPU.NoThreads = bitfield((uint32_t)msr, 15, 0);␊ |
| 203 | p->CPU.NoCores = bitfield((uint32_t)msr, 19, 16); ␊ |
| 204 | break;␊ |
| 205 | }␊ |
| 206 | ␊ |
| 207 | case CPUID_MODEL_NEHALEM:␊ |
| 208 | case CPUID_MODEL_FIELDS:␊ |
| 209 | case CPUID_MODEL_DALES:␊ |
| 210 | case CPUID_MODEL_NEHALEM_EX:␊ |
| 211 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
| 212 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
| 213 | {␊ |
| 214 | msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
| 215 | p->CPU.NoThreads = bitfield((uint32_t)msr, 15, 0);␊ |
| 216 | p->CPU.NoCores = bitfield((uint32_t)msr, 31, 16); ␊ |
| 217 | break;␊ |
| 218 | } ␊ |
| 219 | }␊ |
| 220 | }␊ |
| 221 | ␊ |
| 222 | if (p->CPU.NoCores == 0) {␊ |
| 223 | ␉␉p->CPU.NoThreads = cores_per_package;␊ |
| 224 | ␉␉p->CPU.NoCores = logical_per_package;␊ |
| 225 | ␉}␊ |
| 226 | ␊ |
| 227 | ␉ ␊ |
| 228 | ␉tscFrequency = measure_tsc_frequency();␊ |
| 229 | ␉fsbFrequency = 0;␊ |
| 230 | ␉cpuFrequency = 0;␊ |
| 231 | ␉␊ |
| 232 | ␉␉␊ |
| 233 | ␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ␊ |
| 234 | ␉␉((p->CPU.Family == 0x06) || ␊ |
| 235 | ␉␉ (p->CPU.Family == 0x0f)))␊ |
| 236 | ␉{␊ |
| 237 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || ␊ |
| 238 | ␉␉␉(p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊ |
| 239 | ␉␉{␊ |
| 240 | ␉␉␉/* Nehalem CPU model */␊ |
| 241 | ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPUID_MODEL_NEHALEM || ␊ |
| 242 | p->CPU.Model == CPUID_MODEL_FIELDS || ␊ |
| 243 | p->CPU.Model == CPUID_MODEL_DALES || ␊ |
| 244 | p->CPU.Model == CPUID_MODEL_DALES_32NM || ␊ |
| 245 | p->CPU.Model == CPUID_MODEL_WESTMERE ||␊ |
| 246 | p->CPU.Model == CPUID_MODEL_NEHALEM_EX ||␊ |
| 247 | p->CPU.Model == CPUID_MODEL_WESTMERE_EX ||␊ |
| 248 | p->CPU.Model == CPUID_MODEL_SANDYBRIDGE ||␊ |
| 249 | p->CPU.Model == CPUID_MODEL_JAKETOWN)) ␊ |
| 250 | ␉␉␉{␊ |
| 251 | ␉␉␉␉uint8_t␉␉bus_ratio_max = 0, bus_ratio_min = 0;␊ |
| 252 | ␉␉␉␉uint32_t␉max_ratio = 0;␊ |
| 253 | ␉␉␉␉uint64_t␉flex_ratio = 0;␊ |
| 254 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
| 255 | #if DEBUG_CPU␊ |
| 256 | ␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊ |
| 257 | #endif␊ |
| 258 | ␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊ |
| 259 | ␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊ |
| 260 | ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
| 261 | #if DEBUG_CPU␊ |
| 262 | ␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊ |
| 263 | #endif␊ |
| 264 | ␉␉␉␉if ((msr >> 16) & 0x01) {␊ |
| 265 | ␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊ |
| 266 | ␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
| 267 | ␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
| 268 | ␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
| 269 | ␉␉␉␉␉ contents. These contents cause mach_kernel to␊ |
| 270 | ␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
| 271 | ␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
| 272 | ␉␉␉␉␉ is inadvertently set to 0.␊ |
| 273 | ␉␉␉␉␉ */␊ |
| 274 | ␉␉␉␉␉if (flex_ratio == 0) {␊ |
| 275 | ␉␉␉␉␉␉/* Clear bit 16 (evidently the␊ |
| 276 | ␉␉␉␉␉␉ presence bit) */␊ |
| 277 | ␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
| 278 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
| 279 | #if DEBUG_CPU␊ |
| 280 | ␉␉␉␉␉␉DBG("Unusable flex ratio detected. MSR Patched to %08x\n", msr & 0xffffffff);␊ |
| 281 | #endif␊ |
| 282 | ␉␉␉␉␉} else {␊ |
| 283 | ␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊ |
| 284 | ␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
| 285 | ␉␉␉␉␉␉}␊ |
| 286 | ␉␉␉␉␉}␊ |
| 287 | ␉␉␉␉}␊ |
| 288 | ␉␉␉␉␊ |
| 289 | ␉␉␉␉if (bus_ratio_max) {␊ |
| 290 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
| 291 | ␉␉␉␉}␊ |
| 292 | ␉␉␉␉//valv: Turbo Ratio Limit␊ |
| 293 | ␉␉␉␉if ((p->CPU.Model != 0x2e) && (p->CPU.Model != 0x2f)) {␊ |
| 294 | ␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
| 295 | ␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
| 296 | ␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
| 297 | ␉␉␉␉} else {␊ |
| 298 | ␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
| 299 | ␉␉␉␉}␉␉␉␉␉␉␉␉␊ |
| 300 | #if DEBUG_CPU␊ |
| 301 | ␉␉␉␉DBG("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", fsbFrequency / 1000000, max_ratio);␊ |
| 302 | #endif␊ |
| 303 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
| 304 | ␉␉␉} ␊ |
| 305 | ␉␉␉else␊ |
| 306 | ␉␉␉{␊ |
| 307 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
| 308 | #if DEBUG_CPU␊ |
| 309 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊ |
| 310 | #endif␊ |
| 311 | ␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊ |
| 312 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
| 313 | ␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊ |
| 314 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
| 315 | ␉␉␉␉currdiv = (msr >> 14) & 0x01;␊ |
| 316 | ␊ |
| 317 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || ␊ |
| 318 | ␉␉␉␉␉(p->CPU.Family == 0x0f)) // This will always be model >= 3␊ |
| 319 | ␉␉␉␉{␊ |
| 320 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
| 321 | ␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊ |
| 322 | ␉␉␉␉} ␊ |
| 323 | ␉␉␉␉else ␊ |
| 324 | ␉␉␉␉{␊ |
| 325 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
| 326 | ␉␉␉␉␉/* XXX */␊ |
| 327 | ␉␉␉␉␉maxcoef = currcoef;␊ |
| 328 | ␉␉␉␉}␊ |
| 329 | ␊ |
| 330 | ␉␉␉␉if (maxcoef) ␊ |
| 331 | ␉␉␉␉{␊ |
| 332 | ␉␉␉␉␉if (maxdiv)␊ |
| 333 | ␉␉␉␉␉{␊ |
| 334 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
| 335 | ␉␉␉␉␉}␊ |
| 336 | ␉␉␉␉␉else ␊ |
| 337 | ␉␉␉␉␉{␊ |
| 338 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
| 339 | ␉␉␉␉␉}␊ |
| 340 | ␉␉␉␉␉␊ |
| 341 | ␉␉␉␉␉if (currdiv) ␊ |
| 342 | ␉␉␉␉␉{␊ |
| 343 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
| 344 | ␉␉␉␉␉}␊ |
| 345 | ␉␉␉␉␉else ␊ |
| 346 | ␉␉␉␉␉{␊ |
| 347 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
| 348 | ␉␉␉␉␉}␊ |
| 349 | #if DEBUG_CPU␊ |
| 350 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
| 351 | #endif␊ |
| 352 | ␉␉␉␉}␊ |
| 353 | ␉␉␉}␊ |
| 354 | ␉␉}␊ |
| 355 | /* Mobile CPU ? */ ␊ |
| 356 | ␉␉//Slice ␊ |
| 357 | ␉ p->CPU.isMobile = false;␊ |
| 358 | ␉␉switch (p->CPU.Model) {␊ |
| 359 | ␉␉␉case 0x0D:␊ |
| 360 | ␉␉␉␉p->CPU.isMobile = true; ␊ |
| 361 | ␉␉␉␉break;␉␉␉␊ |
| 362 | ␉␉␉case 0x02:␊ |
| 363 | ␉␉␉case 0x03:␊ |
| 364 | ␉␉␉case 0x04:␊ |
| 365 | ␉␉␉case 0x06:␉␊ |
| 366 | ␉␉␉␉p->CPU.isMobile = (rdmsr64(0x2C) & (1 << 21));␊ |
| 367 | ␉␉␉␉break;␊ |
| 368 | ␉␉␉default:␊ |
| 369 | ␉␉␉␉p->CPU.isMobile = (rdmsr64(0x17) & (1 << 28));␊ |
| 370 | ␉␉␉␉break;␊ |
| 371 | ␉␉}␊ |
| 372 | ␊ |
| 373 | ␉␉DBG("%s platform found.\n", p->CPU.isMobile?"Mobile":"Desktop");␊ |
| 374 | ␉}␊ |
| 375 | ␉␊ |
| 376 | ␉p->CPU.MaxCoef = maxcoef;␊ |
| 377 | ␉p->CPU.MaxDiv = maxdiv;␊ |
| 378 | ␉p->CPU.CurrCoef = currcoef;␊ |
| 379 | ␉p->CPU.CurrDiv = currdiv;␊ |
| 380 | ␊ |
| 381 | ␉p->CPU.TSCFrequency = (tscFrequency / 1000000) * 1000000;␊ |
| 382 | ␉p->CPU.FSBFrequency = (fsbFrequency / 1000000) * 1000000;␊ |
| 383 | ␉p->CPU.CPUFrequency = (cpuFrequency / 1000000) * 1000000;␊ |
| 384 | ␊ |
| 385 | //p->CPU.TSCFrequency = tscFrequency ;␊ |
| 386 | ␉//p->CPU.FSBFrequency = fsbFrequency ;␊ |
| 387 | ␉//p->CPU.CPUFrequency = cpuFrequency ;␊ |
| 388 | ␊ |
| 389 | ␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊ |
| 390 | ␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊ |
| 391 | ␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␉␊ |
| 392 | ␉if(p->CPU.Vendor == 0x756E6547 /* Intel */)␊ |
| 393 | ␉{␉␉␊ |
| 394 | ␉␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
| 395 | ␉␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
| 396 | ␉␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊ |
| 397 | ␉␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␉␉␊ |
| 398 | ␉}␊ |
| 399 | ␉␊ |
| 400 | ␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
| 401 | ␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
| 402 | DBG("CPU: ExtFeatures: 0x%08x\n", p->CPU.ExtFeatures); // where is SYSCALL ??␊ |
| 403 | DBG("CPU: MicrocodeVersion: %d\n", p->CPU.MicrocodeVersion);␊ |
| 404 | #if DEBUG_CPU␊ |
| 405 | ␉␉pause();␊ |
| 406 | #endif␊ |
| 407 | ␉␊ |
| 408 | }␊ |
| 409 | |
