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1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10#include "libsaio.h"␊
11#include "boot.h"␊
12#include "bootstruct.h"␊
13#include "pci.h"␊
14␊
15#ifndef DEBUG_USB␊
16#define DEBUG_USB 0␊
17#endif␊
18␊
19#if DEBUG_USB␊
20#define DBG(x...)␉printf(x)␊
21#else␊
22#define DBG(x...)␊
23#endif␊
24␊
25#define kUSBBusFix␉␉␉"USBBusFix"␉␉␉␊
26#define kEHCIacquire␉␉"EHCIacquire"␉␉␊
27#define kUHCIreset␉␉␉"UHCIreset"␉␉␉␊
28#define kLegacyOff␉␉␉"USBLegacyOff"␉␉␊
29#define kEHCIhard␉␉␉"EHCIhard"␉␉␉␊
30␊
31int usb_loop();␊
32␊
33struct pciList* usbList = NULL;␊
34␊
35int legacy_off (pci_dt_t *pci_dev);␊
36int ehci_acquire (pci_dt_t *pci_dev);␊
37int uhci_reset (pci_dt_t *pci_dev);␊
38␊
39// Add usb device to the list␊
40void notify_usb_dev(pci_dt_t *pci_dev)␊
41{␊
42␉struct pciList* current = usbList;␊
43␉if(!usbList)␊
44␉{␊
45␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊
46␉␉usbList->next = NULL;␊
47␉␉usbList->pciDev = pci_dev;␊
48␉␉␊
49␉}␊
50␉else␊
51␉{␊
52␉␉while(current != NULL && current->next != NULL)␊
53␉␉{␊
54␉␉␉current = current->next;␊
55␉␉}␊
56␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊
57␉␉current = current->next;␊
58␉␉␊
59␉␉current->pciDev = pci_dev;␊
60␉␉current->next = NULL;␊
61␉}␊
62}␊
63␊
64// Loop through the list and call the apropriate patch function␊
65int usb_loop()␊
66{␊
67␉int retVal = 1;␊
68␉bool fix_ehci = true, fix_uhci = true, fix_usb = true, fix_legacy = true;␊
69␉␊
70␉if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig))␊
71␉{␊
72␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Disable all if none set␊
73␉}␊
74␉else ␊
75␉{␊
76␉␉getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);␊
77␉␉getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);␊
78␉␉getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);␊
79␉}␊
80␉␉␉␉␊
81␉DBG("\n");␊
82␉struct pciList* current = usbList;␊
83␉␊
84␉while(current)␊
85␉{␊
86␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊
87␉␉{␊
88␉␉␉// EHCI␊
89␉␉␉case 0x20:␊
90␉␉ ␉if(fix_legacy) retVal &= legacy_off(current->pciDev);␊
91␉␉ ␉if(fix_ehci) retVal &= ehci_acquire(current->pciDev);␊
92␉␉␉␉␊
93␉␉␉␉break;␊
94␉␉␉␉␊
95␉␉␉// UHCI␊
96␉␉␉case 0x00:␊
97␉␉␉␉if (fix_uhci) retVal &= uhci_reset(current->pciDev);␊
98␊
99␉␉␉␉break;␊
100␉␉␉default:␊
101␉␉␉␉break;␊
102␉␉}␊
103␉␉␊
104␉␉current = current->next;␊
105␉}␊
106␉return retVal;␊
107}␊
108␊
109int legacy_off (pci_dt_t *pci_dev)␊
110{␊
111␉// Set usb legacy off modification by Signal64␊
112␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
113␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊
114␉// AKA: Make this run immediatly before the kernel is called␊
115␉␉␊
116␉DBG("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
117␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
118␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
119␉␊
120␉␊
121␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
122␉uint32_t capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
123␉␊
124␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
125␉uint32_t opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
126␉␊
127␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
128␉uint8_t eecp=*((unsigned char*)(capaddr + 9));␊
129␉␊
130␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
131␉␊
132␉uint32_t usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
133␉uint32_t usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
134␉uint32_t usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
135␉␊
136␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
137␉␊
138␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊
139␉uint32_t usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
140␉␊
141␉// informational only␊
142␉int isBIOSowned = !!((usblegsup) & (1 << (16)));␊
143␉int isOSowned = !!((usblegsup) & (1 << (24)));␊
144␉␊
145␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
146␉uint32_t usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
147␉␊
148␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
149␉␊
150␉// Reset registers to Legacy OFF␊
151␉DBG("Clearing USBLEGCTLSTS\n");␊
152␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
153␉␊
154␉// if delay value is in milliseconds it doesn't appear to work. ␊
155␉// setting value to anything up to 65535 does not add the expected delay here.␊
156␉delay(100);␊
157␉␊
158␉usbcmd = *((unsigned int*)(opaddr));␊
159␉usbsts = *((unsigned int*)(opaddr + 4));␊
160␉usbintr = *((unsigned int*)(opaddr + 8));␊
161␉␊
162␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
163␉␊
164␉DBG("Clearing Registers\n");␊
165␉␊
166␉// clear registers to default␊
167␉usbcmd = (usbcmd & 0xffffff00);␊
168␉*((unsigned int*)(opaddr)) = usbcmd;␊
169␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
170␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
171␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
172␉␊
173␉// get the results␊
174␉usbcmd = *((unsigned int*)(opaddr));␊
175␉usbsts = *((unsigned int*)(opaddr + 4));␊
176␉usbintr = *((unsigned int*)(opaddr + 8));␊
177␉␊
178␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
179␉␊
180␉// read 32bit USBLEGSUP (eecp+0) ␊
181␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
182␉␊
183␉// informational only␊
184␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
185␉isOSowned = !!((usblegsup) & (1 << (24)));␊
186␉␊
187␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
188␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
189␉␊
190␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
191␉␊
192␉DBG("Legacy USB Off Done\n");␉␊
193␉return 1;␊
194}␊
195␊
196int ehci_acquire (pci_dt_t *pci_dev)␊
197{␊
198␉int␉␉j, k;␉␊
199␉uint8_t␉␉legacy[8];␊
200␉bool␉␉alwaysHardBIOSReset = false;␊
201␉␉␊
202␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊
203␉␉alwaysHardBIOSReset = true;␊
204␉}␊
205␊
206␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
207␉uint32_t base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
208␊
209␉DBG("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
210␉␉pci_dev->vendor_id, pci_dev->device_id,␊
211␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
212␉␉base);␊
213␊
214␉if (*((unsigned char*)base) < 0xc)␊
215␉{␊
216␉␉DBG("Config space too small: no legacy implementation\n");␊
217␉␉return 1;␊
218␉}␊
219␉uint8_t eecp = *((unsigned char*)(base + 9));␊
220␉if (!eecp) {␊
221␉␉DBG("No extended capabilities: no legacy implementation\n");␊
222␉␉return 1;␊
223␉}␊
224␊
225␉DBG("eecp=%x\n",eecp);␊
226␊
227␉// bad way to do it␊
228␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
229␉for (j = 0; j < 8; j++) {␊
230␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
231␉␉DBG("%02x ", legacy[j]);␊
232␉}␊
233␉DBG("\n");␊
234␊
235␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
236␉//We try soft reset first - some systems hang on reboot with hard reset␊
237␉// Definitely needed during reboot on 10.4.6␊
238␊
239␉bool isOwnershipConflict = (((legacy[3] & 1) != 0) && ((legacy[2] & 1) != 0));␊
240␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
241␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
242␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
243␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
244␉␉for (k = 0; k < 25; k++) {␊
245␉␉␉for (j = 0; j < 8; j++) {␊
246␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
247␉␉␉}␊
248␉␉␉if (legacy[3] == 0) {␊
249␉␉␉␉break;␊
250␉␉␉}␊
251␉␉␉delay(10);␊
252␉␉}␊
253␉}␉␊
254␊
255␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
256␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
257␊
258␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
259␉for (k = 0; k < 25; k++) {␊
260␉␉for (j = 0;j < 8; j++) {␊
261␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
262␉␉}␊
263␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
264␉␉if (legacy[2] == 0) {␊
265␉␉␉break;␊
266␉␉}␊
267␉␉delay(10);␊
268␉}␊
269␊
270␉for (j = 0;j < 8; j++) {␊
271␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
272␉}␊
273␉isOwnershipConflict = ((legacy[2]) != 0);␊
274␉if (isOwnershipConflict) {␊
275␉␉// Soft reset has failed. Assume SMI being ignored␊
276␉␉// Hard reset␊
277␉␉// Force Clear BIOS BIT␊
278␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
279␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
280␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
281␊
282␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
283␉␉for (k = 0; k < 25; k++) {␊
284␉␉␉for (j = 0; j < 8; j++) {␊
285␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
286␉␉␉}␊
287␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
288␊
289␉␉␉if ((legacy[2]) == 0) {␊
290␉␉␉␉break;␊
291␉␉␉}␊
292␉␉␉delay(10);␉␊
293␉␉}␉␉␊
294␉␉// Disable further SMI events␊
295␉␉for (j = 4; j < 8; j++) {␊
296␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
297␉␉}␊
298␉}␊
299␊
300␉for (j = 0; j < 8; j++) {␊
301␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
302␉}␊
303␊
304␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
305␊
306␉// Final Ownership Resolution Check...␊
307␉if (legacy[2] & 1) {␉␉␉␉␉␊
308␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
309␉␉return 0;␊
310␉}␊
311␊
312␉DBG("EHCI Acquire OS Ownership done\n");␉␊
313␉return 1;␊
314}␊
315␊
316int uhci_reset (pci_dt_t *pci_dev)␊
317{␊
318␉uint32_t base, port_base;␊
319␉␊
320␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
321␉port_base = (base >> 5) & 0x07ff;␊
322␊
323␉DBG("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
324␉␉pci_dev->vendor_id, pci_dev->device_id,␊
325␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
326␉␉port_base, base);␊
327␉␊
328␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
329␊
330␉outw (port_base, 0x0002);␊
331␉delay(10);␊
332␉outw (port_base+4,0);␊
333␉delay(10);␊
334␉outw (port_base,0);␊
335␉return 1;␊
336}␊
337

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