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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
24 */␊
25static uint64_t measure_tsc_frequency(void)␊
26{␊
27 uint64_t tscStart;␊
28 uint64_t tscEnd;␊
29 uint64_t tscDelta = 0xffffffffffffffffULL;␊
30 unsigned long pollCount;␊
31 uint64_t retval = 0;␊
32 int i;␊
33␊
34 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
35 * counter 2. We run this loop 3 times to make sure the cache␊
36 * is hot and we take the minimum delta from all of the runs.␊
37 * That is to say that we're biased towards measuring the minimum␊
38 * number of TSC ticks that occur while waiting for the timer to␊
39 * expire. That theoretically helps avoid inconsistencies when␊
40 * running under a VM if the TSC is not virtualized and the host␊
41 * steals time. The TSC is normally virtualized for VMware.␊
42 */␊
43 for(i = 0; i < 10; ++i)␊
44 {␊
45 enable_PIT2();␊
46 set_PIT2_mode0(CALIBRATE_LATCH);␊
47 tscStart = rdtsc64();␊
48 pollCount = poll_PIT2_gate();␊
49 tscEnd = rdtsc64();␊
50 /* The poll loop must have run at least a few times for accuracy */␊
51 if(pollCount <= 1)␊
52 continue;␊
53 /* The TSC must increment at LEAST once every millisecond. We␊
54 * should have waited exactly 30 msec so the TSC delta should␊
55 * be >= 30. Anything less and the processor is way too slow.␊
56 */␊
57 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
58 continue;␊
59 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
60 if( (tscEnd - tscStart) < tscDelta )␊
61 tscDelta = tscEnd - tscStart;␊
62 }␊
63 /* tscDelta is now the least number of TSC ticks the processor made in␊
64 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
65 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
66 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
67 * Hz so we need to convert our milliseconds to seconds. Since we're␊
68 * dividing by the milliseconds, we simply multiply by 1000.␊
69 */␊
70␊
71 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
72 * that we're going to multiply by 1000 first so we do need at least some␊
73 * arithmetic headroom. For now, 32-bit should be enough.␊
74 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
75 */␊
76 if(tscDelta > (1ULL<<32))␊
77 retval = 0;␊
78 else␊
79 {␊
80 retval = tscDelta * 1000 / 30;␊
81 }␊
82 disable_PIT2();␊
83 return retval;␊
84}␊
85␊
86/*␊
87 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
88 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
89 * a max multi. (used to calculate the FSB freq.),␊
90 * and a current multi. (used to calculate the CPU freq.)␊
91 * - fsbFrequency = tscFrequency / multi␊
92 * - cpuFrequency = fsbFrequency * multi␊
93 */␊
94␊
95void scan_cpu(PlatformInfo_t *p)␊
96{␊
97␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
98␉uint64_t␉msr, flex_ratio;␊
99␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
100␉const char *newratio;␊
101␉int len, myfsb;␊
102␉uint8_t bus_ratio_min;␊
103␉uint32_t max_ratio, min_ratio;␊
104␊
105␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
106␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
107␊
108␉/* get cpuid values */␊
109␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
110␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
111␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
112␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
113␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
114␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
115␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
116␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
117␉}␊
118#if DEBUG_CPU␊
119␉{␊
120␉␉int␉␉i;␊
121␉␉printf("CPUID Raw Values:\n");␊
122␉␉for (i=0; i<CPUID_MAX; i++) {␊
123␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
124␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
125␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
126␉␉}␊
127␉}␊
128#endif␊
129␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
130␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
131␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
132␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
133␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
134␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
135␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
136␉␊
137 p->CPU.Model += (p->CPU.ExtModel << 4);␊
138 ␊
139 if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
140 p->CPU.Family == 0x06 && ␊
141 p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
142 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
143 ){␊
144 msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
145 p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
146 p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
147␉} else {␊
148 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
149 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
150␉}␊
151␉␊
152␉/* get brand string (if supported) */␊
153␉/* Copyright: from Apple's XNU cpuid.c */␊
154␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
155␉␉uint32_t␉reg[4];␊
156 char str[128], *s;␊
157␉␉/*␊
158␉␉ * The brand string 48 bytes (max), guaranteed to␊
159␉␉ * be NULL terminated.␊
160␉␉ */␊
161␉␉do_cpuid(0x80000002, reg);␊
162␉␉bcopy((char *)reg, &str[0], 16);␊
163␉␉do_cpuid(0x80000003, reg);␊
164␉␉bcopy((char *)reg, &str[16], 16);␊
165␉␉do_cpuid(0x80000004, reg);␊
166␉␉bcopy((char *)reg, &str[32], 16);␊
167␉␉for (s = str; *s != '\0'; s++) {␊
168␉␉␉if (*s != ' ') break;␊
169␉␉}␊
170␉␉␊
171␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
172␉␉␊
173␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
174␉␉␉ /*␊
175␉␉␉ * This string means we have a firmware-programmable brand string,␊
176␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
177␉␉␉ */␊
178␉␉␉ p->CPU.BrandString[0] = '\0';␊
179␉␉ }␊
180␉}␊
181␉␊
182␉/* setup features */␊
183␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
184␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
185␉}␊
186␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
187␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
188␉}␊
189␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
190␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
191␉}␊
192␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
193␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
194␉}␊
195␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
196␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
197␉}␊
198␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
199␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
200␉}␊
201␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
202␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
203␉}␊
204␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
205␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
206␉}␊
207␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
208␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
209␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
210␉}␊
211␊
212␉tscFrequency = measure_tsc_frequency();␊
213␉fsbFrequency = 0;␊
214␉cpuFrequency = 0;␊
215␊
216␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
217␉␉int intelCPU = p->CPU.Model;␊
218␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
219␉␉␉/* Nehalem CPU model */␊
220␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
221 p->CPU.Model == CPU_MODEL_FIELDS || ␊
222 p->CPU.Model == CPU_MODEL_DALES || ␊
223 p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
224 p->CPU.Model == CPU_MODEL_WESTMERE ||␊
225 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
226 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
227 p->CPU.Model == CPU_MODEL_SANDY ||␊
228 p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
229␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
230␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
231␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
232␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
233␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
234␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
235␉␉␉␉if ((msr >> 16) & 0x01) {␊
236␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
237␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
238␉␉␉␉␉ where the cpu multipler can't be changed to␊
239␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
240␉␉␉␉␉ contents. These contents cause mach_kernel to␊
241␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
242␉␉␉␉␉ causing the system to crash since tscGranularity␊
243␉␉␉␉␉ is inadvertently set to 0.␊
244␉␉␉␉␉*/␊
245␉␉␉␉␉if (flex_ratio == 0) {␊
246␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
247␉␉␉␉␉␉ presence bit) */␊
248␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
249␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
250␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff);␊
251␉␉␉␉␉} else {␊
252␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
253␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
254␉␉␉␉␉␉}␊
255␉␉␉␉␉}␊
256␉␉␉␉}␊
257␊
258␉␉␉␉if (bus_ratio_max) {␊
259␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
260␉␉␉␉}␊
261␉␉␉␉//valv: Turbo Ratio Limit␊
262␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
263␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
264␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
265␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
266␉␉␉␉} else {␊
267␉␉␉␉␉cpuFrequency = tscFrequency;␊
268␉␉␉␉}␊
269␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
270␉␉␉␉␉max_ratio = atoi(newratio);␊
271␉␉␉␉␉max_ratio = (max_ratio * 10);␊
272␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
273␊
274␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
275␊
276␉␉␉␉␉// extreme overclockers may love 320 ;)␊
277␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
278␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
279␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
280␉␉␉␉␉␉else maxdiv = 0;␊
281␉␉␉␉␉} else {␊
282␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
283␉␉␉␉␉}␊
284␉␉␉␉}␊
285␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
286␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
287␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
288␉␉␉␉p->CPU.MinRatio = min_ratio;␊
289␊
290␉␉␉␉myfsb = fsbFrequency / 1000000;␊
291␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
292␉␉␉␉currcoef = bus_ratio_max;␊
293␉␉␉} else {␊
294␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
295␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
296␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
297␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
298␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
299␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
300␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
301␊
302␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
303␉␉␉␉{␊
304␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
305␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
306␉␉␉␉} else {␊
307␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
308␉␉␉␉␉/* XXX */␊
309␉␉␉␉␉maxcoef = currcoef;␊
310␉␉␉␉}␊
311␊
312␉␉␉␉if (maxcoef) {␊
313␉␉␉␉␉if (maxdiv) {␊
314␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
315␉␉␉␉␉} else {␊
316␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
317␉␉␉␉␉}␊
318␉␉␉␉␉if (currdiv) {␊
319␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
320␉␉␉␉␉} else {␊
321␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
322␉␉␉␉␉}␊
323␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
324␉␉␉␉}␊
325␉␉␉}␊
326␉␉}␊
327␉␉/* Mobile CPU */␊
328␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
329␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
330␉␉}␊
331␉}␊
332#if 0␊
333␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
334␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
335␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
336␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
337␉␉␉currdiv = (msr & 0x01) * 2;␊
338␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
339␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
340␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
341␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
342␉␉␉else /* K11+ */␊
343␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
344␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
345␉␉}␊
346␊
347␉␉if (currcoef) {␊
348␉␉␉if (currdiv) {␊
349␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
350␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
351␉␉␉} else {␊
352␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
353␉␉␉␉DBG("%d\n", currcoef);␊
354␉␉␉}␊
355␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
356␉␉␉cpuFrequency = tscFrequency;␊
357␉␉}␊
358␉}␊
359␊
360␉if (!fsbFrequency) {␊
361␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
362␉␉cpuFrequency = tscFrequency;␊
363␉␉DBG("0 ! using the default value for FSB !\n");␊
364␉}␊
365#endif␊
366␊
367␉p->CPU.MaxCoef = maxcoef;␊
368␉p->CPU.MaxDiv = maxdiv;␊
369␉p->CPU.CurrCoef = currcoef;␊
370␉p->CPU.CurrDiv = currdiv;␊
371␉p->CPU.TSCFrequency = tscFrequency;␊
372␉p->CPU.FSBFrequency = fsbFrequency;␊
373␉p->CPU.CPUFrequency = cpuFrequency;␊
374␊
375␉DBG("CPU: Brand String: %s\n",␉␉␉␉p->CPU.BrandString);␊
376␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",␉p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
377␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",␉p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
378␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",␉␉p->CPU.MaxCoef, p->CPU.CurrCoef);␊
379␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",␉␉p->CPU.MaxDiv, p->CPU.CurrDiv);␊
380␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
381␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
382␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
383␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
384␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
385#if DEBUG_CPU␊
386␉pause();␊
387#endif␊
388}␊
389

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