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Root/trunk/i386/libsaio/platform.h

1/*␊
2 * platform.h␊
3 * AsereBLN: reworked and extended␊
4 *␊
5 */␊
6␊
7#ifndef __LIBSAIO_PLATFORM_H␊
8#define __LIBSAIO_PLATFORM_H␊
9␊
10//#include "libsaio.h"␊
11␊
12extern bool platformCPUFeature(uint32_t);␊
13extern void scan_platform(void);␊
14extern void dumpPhysAddr(const char * title, void * a, int len);␊
15␊
16/* CPUID Vendor */␊
17#define CPUID_VENDOR_INTEL 0x756E6547␊
18#define CPUID_VENDOR_AMD 0x68747541␊
19␊
20/* CPUID index into cpuid_raw */␊
21#define CPUID_0␉␉␉␉0␊
22#define CPUID_1␉␉␉␉1␊
23#define CPUID_2␉␉␉␉2␊
24#define CPUID_3␉␉␉␉3␊
25#define CPUID_4␉␉␉␉4␊
26#define CPUID_80␉␉␉5␊
27#define CPUID_81␉␉␉6␊
28#define CPUID_88␉␉␉7␊
29#define CPUID_MAX␉␉␉8␊
30␊
31#define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊
32#define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
33#define CPU_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊
34#define CPU_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊
35#define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Atom␊
36#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
37#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊
38#define CPU_MODEL_DALES_32NM␉0x25␉␉␉// Clarkdale, Arrandale␊
39#define CPU_MODEL_SANDY␉␉␉0x2A␉␉␉// Sandy Bridge␊
40#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
41#define CPU_MODEL_SANDY_XEON␉0x2D␉␉␉// Sandy Bridge Xeon␊
42#define CPU_MODEL_NEHALEM_EX␉0x2E␉␉␉// Beckton␊
43#define CPU_MODEL_WESTMERE_EX␉0x2F␊
44␊
45/* CPU Features */␊
46#define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
47#define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊
48#define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊
49#define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊
50#define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊
51#define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊
52#define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊
53#define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊
54#define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊
55#define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊
56␊
57/* SMBIOS Memory Types */ ␊
58#define SMB_MEM_TYPE_UNDEFINED␉0␊
59#define SMB_MEM_TYPE_OTHER␉␉1␊
60#define SMB_MEM_TYPE_UNKNOWN␉2␊
61#define SMB_MEM_TYPE_DRAM␉␉3␊
62#define SMB_MEM_TYPE_EDRAM␉␉4␊
63#define SMB_MEM_TYPE_VRAM␉␉5␊
64#define SMB_MEM_TYPE_SRAM␉␉6␊
65#define SMB_MEM_TYPE_RAM␉␉7␊
66#define SMB_MEM_TYPE_ROM␉␉8␊
67#define SMB_MEM_TYPE_FLASH␉␉9␊
68#define SMB_MEM_TYPE_EEPROM␉␉10␊
69#define SMB_MEM_TYPE_FEPROM␉␉11␊
70#define SMB_MEM_TYPE_EPROM␉␉12␊
71#define SMB_MEM_TYPE_CDRAM␉␉13␊
72#define SMB_MEM_TYPE_3DRAM␉␉14␊
73#define SMB_MEM_TYPE_SDRAM␉␉15␊
74#define SMB_MEM_TYPE_SGRAM␉␉16␊
75#define SMB_MEM_TYPE_RDRAM␉␉17␊
76#define SMB_MEM_TYPE_DDR␉␉18␊
77#define SMB_MEM_TYPE_DDR2␉␉19␊
78#define SMB_MEM_TYPE_FBDIMM␉␉20␊
79#define SMB_MEM_TYPE_DDR3␉␉24␉␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊
80␊
81/* Memory Configuration Types */ ␊
82#define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊
83#define SMB_MEM_CHANNEL_SINGLE␉␉1␊
84#define SMB_MEM_CHANNEL_DUAL␉␉2␊
85#define SMB_MEM_CHANNEL_TRIPLE␉␉3␊
86␊
87/* Maximum number of ram slots */␊
88#define MAX_RAM_SLOTS␉␉␉8␊
89#define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊
90␊
91/* Maximum number of SPD bytes */␊
92#define MAX_SPD_SIZE␉␉␉256␊
93␊
94/* Size of SMBIOS UUID in bytes */␊
95#define UUID_LEN␉␉␉16␊
96␊
97typedef struct _RamSlotInfo_t {␊
98 uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊
99 uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊
100 const char*␉␉Vendor;␊
101 const char*␉␉PartNo;␊
102 const char*␉␉SerialNo;␊
103 char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊
104 bool␉␉␉InUse;␊
105 uint8_t␉␉␉Type;␊
106 uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊
107 uint8_t␉␉␉BankConnCnt;␊
108} RamSlotInfo_t;␊
109␊
110typedef struct _PlatformInfo_t {␊
111␉struct CPU {␊
112␉␉uint32_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
113␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊
114␉␉uint32_t␉␉Signature;␉␉␉␉// Signature␊
115␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊
116␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊
117␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊
118␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊
119␉␉uint32_t␉␉ExtFamily;␉␉␉␉// Extended Family␊
120␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
121␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
122␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
123␉␉uint8_t␉␉␉MaxDiv;␊
124␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
125␉␉uint8_t␉␉␉CurrDiv;␊
126␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
127␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
128␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
129␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
130␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
131␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
132␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
133␉} CPU;␊
134␉␊
135␉struct RAM {␊
136␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
137␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
138␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
139␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
140␉␉uint8_t␉␉␉TRP;␊
141␉␉uint8_t␉␉␉RAS;␊
142␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
143␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
144␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
145␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
146␉} RAM;␊
147␉␊
148␉struct DMI {␊
149␉␉int␉␉␉MaxMemorySlots;␉␉␉␉// number of memory slots populated by SMBIOS␊
150␉␉int␉␉␉CntMemorySlots;␉␉␉␉// number of memory slots counted␊
151␉␉int␉␉␉MemoryModules;␉␉␉␉// number of memory modules installed␊
152␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉␉// Information and SPD mapping for each slot␊
153␉} DMI;␊
154␉␊
155␉uint8_t␉␉␉␉Type; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊
156␉uint8_t␉␉␉␉*UUID;␊
157} PlatformInfo_t;␊
158␊
159extern PlatformInfo_t Platform;␊
160␊
161#endif /* !__LIBSAIO_PLATFORM_H */␊
162

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