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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8//#include "mem.h"␊
9#include "smbios_getters.h"␊
10#include "cpu.h"␊
11#include "bootstruct.h"␊
12#include "boot.h"␊
13␊
14#ifndef DEBUG_CPU␊
15#define DEBUG_CPU 0␊
16#endif␊
17␊
18#if DEBUG_CPU␊
19#define DBG(x...)␉␉printf(x)␊
20#else␊
21#define DBG(x...)␉␉msglog(x)␊
22#endif␊
23␊
24/*␊
25 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
26 */␊
27static uint64_t measure_tsc_frequency(void)␊
28{␊
29 uint64_t tscStart;␊
30 uint64_t tscEnd;␊
31 uint64_t tscDelta = 0xffffffffffffffffULL;␊
32 unsigned long pollCount;␊
33 uint64_t retval = 0;␊
34 int i;␊
35␊
36 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
37 * counter 2. We run this loop 3 times to make sure the cache␊
38 * is hot and we take the minimum delta from all of the runs.␊
39 * That is to say that we're biased towards measuring the minimum␊
40 * number of TSC ticks that occur while waiting for the timer to␊
41 * expire. That theoretically helps avoid inconsistencies when␊
42 * running under a VM if the TSC is not virtualized and the host␊
43 * steals time. The TSC is normally virtualized for VMware.␊
44 */␊
45 for(i = 0; i < 10; ++i)␊
46 {␊
47 enable_PIT2();␊
48 set_PIT2_mode0(CALIBRATE_LATCH);␊
49 tscStart = rdtsc64();␊
50 pollCount = poll_PIT2_gate();␊
51 tscEnd = rdtsc64();␊
52 /* The poll loop must have run at least a few times for accuracy */␊
53 if(pollCount <= 1)␊
54 continue;␊
55 /* The TSC must increment at LEAST once every millisecond. We␊
56 * should have waited exactly 30 msec so the TSC delta should␊
57 * be >= 30. Anything less and the processor is way too slow.␊
58 */␊
59 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
60 continue;␊
61 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
62 if( (tscEnd - tscStart) < tscDelta )␊
63 tscDelta = tscEnd - tscStart;␊
64 }␊
65 /* tscDelta is now the least number of TSC ticks the processor made in␊
66 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
67 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
68 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
69 * Hz so we need to convert our milliseconds to seconds. Since we're␊
70 * dividing by the milliseconds, we simply multiply by 1000.␊
71 */␊
72␊
73 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
74 * that we're going to multiply by 1000 first so we do need at least some␊
75 * arithmetic headroom. For now, 32-bit should be enough.␊
76 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
77 */␊
78 if(tscDelta > (1ULL<<32))␊
79 retval = 0;␊
80 else␊
81 {␊
82 retval = tscDelta * 1000 / 30;␊
83 }␊
84 disable_PIT2();␊
85 return retval;␊
86}␊
87␊
88/*␊
89 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
90 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
91 * a max multi. (used to calculate the FSB freq.),␊
92 * and a current multi. (used to calculate the CPU freq.)␊
93 * - fsbFrequency = tscFrequency / multi␊
94 * - cpuFrequency = fsbFrequency * multi␊
95 */␊
96␊
97void scan_cpu(PlatformInfo_t *p)␊
98{␊
99␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
100␉uint64_t␉msr, flex_ratio;␊
101␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
102␉const char *newratio;␊
103␉int len, myfsb;␊
104␉uint8_t bus_ratio_min;␊
105␉uint32_t max_ratio, min_ratio;␊
106␊
107␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
108␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
109␊
110␉/* get cpuid values */␊
111␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
112␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
113␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
114␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
115␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
116␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
117␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
118␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
119␉}␊
120#if DEBUG_CPU␊
121␉{␊
122␉␉int␉␉i;␊
123␉␉printf("CPUID Raw Values:\n");␊
124␉␉for (i=0; i<CPUID_MAX; i++) {␊
125␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
126␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
127␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
128␉␉}␊
129␉}␊
130#endif␊
131␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
132␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
133␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
134␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
135␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
136␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
137␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
138␉␊
139 p->CPU.Model += (p->CPU.ExtModel << 4);␊
140 ␊
141 if (p->CPU.Vendor == 0x756E6547 /* Intel */ && ␊
142 p->CPU.Family == 0x06 && ␊
143 p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
144 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
145 ){␊
146 msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
147 p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
148 p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
149␉} else {␊
150 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
151 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
152␉}␊
153␉␊
154␉/* get brand string (if supported) */␊
155␉/* Copyright: from Apple's XNU cpuid.c */␊
156␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
157␉␉uint32_t␉reg[4];␊
158 char str[128], *s;␊
159␉␉/*␊
160␉␉ * The brand string 48 bytes (max), guaranteed to␊
161␉␉ * be NULL terminated.␊
162␉␉ */␊
163␉␉do_cpuid(0x80000002, reg);␊
164␉␉bcopy((char *)reg, &str[0], 16);␊
165␉␉do_cpuid(0x80000003, reg);␊
166␉␉bcopy((char *)reg, &str[16], 16);␊
167␉␉do_cpuid(0x80000004, reg);␊
168␉␉bcopy((char *)reg, &str[32], 16);␊
169␉␉for (s = str; *s != '\0'; s++) {␊
170␉␉␉if (*s != ' ') break;␊
171␉␉}␊
172␉␉␊
173␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
174␉␉␊
175␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
176␉␉␉ /*␊
177␉␉␉ * This string means we have a firmware-programmable brand string,␊
178␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
179␉␉␉ */␊
180␉␉␉ p->CPU.BrandString[0] = '\0';␊
181␉␉ }␊
182␉}␊
183␉␊
184␉/* setup features */␊
185␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
186␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
187␉}␊
188␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
189␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
190␉}␊
191␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
192␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
193␉}␊
194␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
195␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
196␉}␊
197␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
198␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
199␉}␊
200␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
201␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
202␉}␊
203␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
204␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
205␉}␊
206␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
207␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
208␉}␊
209␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
210␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
211␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
212␉}␊
213␊
214␉tscFrequency = measure_tsc_frequency();␊
215␉fsbFrequency = 0;␊
216␉cpuFrequency = 0;␊
217␊
218␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
219␉␉int intelCPU = p->CPU.Model;␊
220␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
221␉␉␉/* Nehalem CPU model */␊
222␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
223 p->CPU.Model == CPU_MODEL_FIELDS || ␊
224 p->CPU.Model == CPU_MODEL_DALES || ␊
225 p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
226 p->CPU.Model == CPU_MODEL_WESTMERE ||␊
227 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
228 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
229 p->CPU.Model == CPU_MODEL_SANDY ||␊
230 p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
231␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
232␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊
233␉␉␉␉(msr >> 32) & 0xffffffff, msr & 0xffffffff);␊
234␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
235␉␉␉␉bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)␊
236␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
237␉␉␉␉DBG("msr(0x%04x): flex_ratio %08x\n", MSR_FLEX_RATIO, msr & 0xffffffff);␊
238␉␉␉␉if ((msr >> 16) & 0x01) {␊
239␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
240␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
241␉␉␉␉␉ where the cpu multipler can't be changed to␊
242␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
243␉␉␉␉␉ contents. These contents cause mach_kernel to␊
244␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
245␉␉␉␉␉ causing the system to crash since tscGranularity␊
246␉␉␉␉␉ is inadvertently set to 0.␊
247␉␉␉␉␉*/␊
248␉␉␉␉␉if (flex_ratio == 0) {␊
249␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
250␉␉␉␉␉␉ presence bit) */␊
251␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
252␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
253␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff);␊
254␉␉␉␉␉} else {␊
255␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
256␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
257␉␉␉␉␉␉}␊
258␉␉␉␉␉}␊
259␉␉␉␉}␊
260␊
261␉␉␉␉if (bus_ratio_max) {␊
262␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
263␉␉␉␉}␊
264␉␉␉␉//valv: Turbo Ratio Limit␊
265␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
266␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
267␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
268␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
269␉␉␉␉} else {␊
270␉␉␉␉␉cpuFrequency = tscFrequency;␊
271␉␉␉␉}␊
272␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
273␉␉␉␉␉max_ratio = atoi(newratio);␊
274␉␉␉␉␉max_ratio = (max_ratio * 10);␊
275␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
276␊
277␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
278␊
279␉␉␉␉␉// extreme overclockers may love 320 ;)␊
280␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
281␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
282␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
283␉␉␉␉␉␉else maxdiv = 0;␊
284␉␉␉␉␉} else {␊
285␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
286␉␉␉␉␉}␊
287␉␉␉␉}␊
288␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
289␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
290␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
291␉␉␉␉p->CPU.MinRatio = min_ratio;␊
292␊
293␉␉␉␉myfsb = fsbFrequency / 1000000;␊
294␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
295␉␉␉␉currcoef = bus_ratio_max;␊
296␉␉␉} else {␊
297␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
298␉␉␉␉DBG("msr(0x%x): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
299␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
300␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
301␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
302␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
303␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
304␊
305␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
306␉␉␉␉{␊
307␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
308␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
309␉␉␉␉} else {␊
310␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
311␉␉␉␉␉/* XXX */␊
312␉␉␉␉␉maxcoef = currcoef;␊
313␉␉␉␉}␊
314␊
315␉␉␉␉if (maxcoef) {␊
316␉␉␉␉␉if (maxdiv) {␊
317␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
318␉␉␉␉␉} else {␊
319␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
320␉␉␉␉␉}␊
321␉␉␉␉␉if (currdiv) {␊
322␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
323␉␉␉␉␉} else {␊
324␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
325␉␉␉␉␉}␊
326␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
327␉␉␉␉}␊
328␉␉␉}␊
329␉␉}␊
330␉␉/* Mobile CPU ? */␊
331//Slice ␊
332␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
333␉␉DBG("msr(0x%04x): MSR_IA32_PLATFORM_ID 0x%08x\n", MSR_IA32_PLATFORM_ID, msr & 0xffffffff); //__LINE__ - source line number :)␊
334␉␉if (msr) {␊
335␉␉␉p->CPU.Mobile = FALSE;␊
336␉␉␉switch (p->CPU.Model) {␊
337␉␉␉␉case 0x0D:␊
338␉␉␉␉␉p->CPU.Mobile = TRUE; // CPU_FEATURE_MOBILE;␊
339␉␉␉␉␉break;␊
340␉␉␉␉case 0x0F:␊
341␉␉␉␉␉p->CPU.Mobile = FALSE; // CPU_FEATURE_MOBILE;␊
342␉␉␉␉␉break;␊
343␉␉␉␉case 0x02:␊
344␉␉␉␉case 0x03:␊
345␉␉␉␉case 0x04:␊
346␉␉␉␉case 0x06:␉␊
347␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_P4_EBC_FREQUENCY_ID) && (1 << 21));␊
348␉␉␉␉␉break;␊
349␉␉␉␉default:␊
350␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_IA32_PLATFORM_ID) && (1<<28));␊
351␉␉␉␉␉break;␊
352␉␉␉}␊
353␉␉␉if (p->CPU.Mobile) {␊
354␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
355␉␉}␊
356␉}␊
357␉␉DBG("CPU is %s\n", p->CPU.Mobile?"Mobile":"Desktop");␊
358␉␉␉␊
359␉}␊
360#if 0␊
361␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
362␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
363␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
364␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
365␉␉␉currdiv = (msr & 0x01) * 2;␊
366␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
367␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
368␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
369␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
370␉␉␉else /* K11+ */␊
371␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
372␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
373␉␉}␊
374␊
375␉␉if (currcoef) {␊
376␉␉␉if (currdiv) {␊
377␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
378␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
379␉␉␉} else {␊
380␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
381␉␉␉␉DBG("%d\n", currcoef);␊
382␉␉␉}␊
383␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
384␉␉␉cpuFrequency = tscFrequency;␊
385␉␉}␊
386␉}␊
387␊
388␉if (!fsbFrequency) {␊
389␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
390␉␉cpuFrequency = tscFrequency;␊
391␉␉DBG("0 ! using the default value for FSB !\n");␊
392␉}␊
393#endif␊
394␊
395␉p->CPU.MaxCoef = maxcoef;␊
396␉p->CPU.MaxDiv = maxdiv;␊
397␉p->CPU.CurrCoef = currcoef;␊
398␉p->CPU.CurrDiv = currdiv;␊
399␉p->CPU.TSCFrequency = tscFrequency;␊
400␉p->CPU.FSBFrequency = fsbFrequency;␊
401␉p->CPU.CPUFrequency = cpuFrequency;␊
402␉DBG("CPU: Brand: %s\n", p->CPU.BrandString);␊
403␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊
404␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊
405␉DBG("CPU: MaxCoef/CurrCoef/Turbo: 0x%x/0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef, p->CPU.MaxCoef+1);␊
406␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊
407␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
408␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
409␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
410␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
411␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
412#if DEBUG_CPU␊
413␉pause();␊
414#endif␊
415}␊
416

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