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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8//#include "mem.h"␊
9#include "smbios_getters.h"␊
10#include "cpu.h"␊
11#include "bootstruct.h"␊
12#include "boot.h"␊
13␊
14#ifndef DEBUG_CPU␊
15#define DEBUG_CPU 0␊
16#endif␊
17␊
18#if DEBUG_CPU␊
19#define DBG(x...)␉␉printf(x)␊
20#else␊
21#define DBG(x...)␉␉msglog(x)␊
22#endif␊
23␊
24/*␊
25 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
26 */␊
27static uint64_t measure_tsc_frequency(void)␊
28{␊
29 uint64_t tscStart;␊
30 uint64_t tscEnd;␊
31 uint64_t tscDelta = 0xffffffffffffffffULL;␊
32 unsigned long pollCount;␊
33 uint64_t retval = 0;␊
34 int i;␊
35␊
36 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
37 * counter 2. We run this loop 3 times to make sure the cache␊
38 * is hot and we take the minimum delta from all of the runs.␊
39 * That is to say that we're biased towards measuring the minimum␊
40 * number of TSC ticks that occur while waiting for the timer to␊
41 * expire. That theoretically helps avoid inconsistencies when␊
42 * running under a VM if the TSC is not virtualized and the host␊
43 * steals time. The TSC is normally virtualized for VMware.␊
44 */␊
45 for(i = 0; i < 10; ++i)␊
46 {␊
47 enable_PIT2();␊
48 set_PIT2_mode0(CALIBRATE_LATCH);␊
49 tscStart = rdtsc64();␊
50 pollCount = poll_PIT2_gate();␊
51 tscEnd = rdtsc64();␊
52 /* The poll loop must have run at least a few times for accuracy */␊
53 if(pollCount <= 1)␊
54 continue;␊
55 /* The TSC must increment at LEAST once every millisecond. We␊
56 * should have waited exactly 30 msec so the TSC delta should␊
57 * be >= 30. Anything less and the processor is way too slow.␊
58 */␊
59 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
60 continue;␊
61 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
62 if( (tscEnd - tscStart) < tscDelta )␊
63 tscDelta = tscEnd - tscStart;␊
64 }␊
65 /* tscDelta is now the least number of TSC ticks the processor made in␊
66 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
67 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
68 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
69 * Hz so we need to convert our milliseconds to seconds. Since we're␊
70 * dividing by the milliseconds, we simply multiply by 1000.␊
71 */␊
72␊
73 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
74 * that we're going to multiply by 1000 first so we do need at least some␊
75 * arithmetic headroom. For now, 32-bit should be enough.␊
76 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
77 */␊
78 if(tscDelta > (1ULL<<32))␊
79 retval = 0;␊
80 else␊
81 {␊
82 retval = tscDelta * 1000 / 30;␊
83 }␊
84 disable_PIT2();␊
85 return retval;␊
86}␊
87␊
88#if 0␊
89/*␊
90 * DFE: Measures the Max Performance Frequency in Hz (64-bit)␊
91 */␊
92static uint64_t measure_mperf_frequency(void)␊
93{␊
94 uint64_t mperfStart;␊
95 uint64_t mperfEnd;␊
96 uint64_t mperfDelta = 0xffffffffffffffffULL;␊
97 unsigned long pollCount;␊
98 uint64_t retval = 0;␊
99 int i;␊
100 ␊
101 /* Time how many MPERF ticks elapse in 30 msec using the 8254 PIT␊
102 * counter 2. We run this loop 3 times to make sure the cache␊
103 * is hot and we take the minimum delta from all of the runs.␊
104 * That is to say that we're biased towards measuring the minimum␊
105 * number of MPERF ticks that occur while waiting for the timer to␊
106 * expire.␊
107 */␊
108 for(i = 0; i < 10; ++i)␊
109 {␊
110 enable_PIT2();␊
111 set_PIT2_mode0(CALIBRATE_LATCH);␊
112 mperfStart = rdmsr64(MSR_AMD_MPERF);␊
113 pollCount = poll_PIT2_gate();␊
114 mperfEnd = rdmsr64(MSR_AMD_MPERF);␊
115 /* The poll loop must have run at least a few times for accuracy */␊
116 if(pollCount <= 1)␊
117 continue;␊
118 /* The MPERF must increment at LEAST once every millisecond. We␊
119 * should have waited exactly 30 msec so the MPERF delta should␊
120 * be >= 30. Anything less and the processor is way too slow.␊
121 */␊
122 if((mperfEnd - mperfStart) <= CALIBRATE_TIME_MSEC)␊
123 continue;␊
124 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
125 if( (mperfEnd - mperfStart) < mperfDelta )␊
126 mperfDelta = mperfEnd - mperfStart;␊
127 }␊
128 /* mperfDelta is now the least number of MPERF ticks the processor made in␊
129 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
130 */␊
131 ␊
132 if(mperfDelta > (1ULL<<32))␊
133 retval = 0;␊
134 else␊
135 {␊
136 retval = mperfDelta * 1000 / 30;␊
137 }␊
138 disable_PIT2();␊
139 return retval;␊
140}␊
141#endif␊
142/*␊
143 * Measures the Actual Performance Frequency in Hz (64-bit)␊
144 */␊
145static uint64_t measure_aperf_frequency(void)␊
146{␊
147 uint64_t aperfStart;␊
148 uint64_t aperfEnd;␊
149 uint64_t aperfDelta = 0xffffffffffffffffULL;␊
150 unsigned long pollCount;␊
151 uint64_t retval = 0;␊
152 int i;␊
153 ␊
154 /* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
155 * counter 2. We run this loop 3 times to make sure the cache␊
156 * is hot and we take the minimum delta from all of the runs.␊
157 * That is to say that we're biased towards measuring the minimum␊
158 * number of APERF ticks that occur while waiting for the timer to␊
159 * expire. ␊
160 */␊
161 for(i = 0; i < 10; ++i)␊
162 {␊
163 enable_PIT2();␊
164 set_PIT2_mode0(CALIBRATE_LATCH);␊
165 aperfStart = rdmsr64(MSR_AMD_APERF);␊
166 pollCount = poll_PIT2_gate();␊
167 aperfEnd = rdmsr64(MSR_AMD_APERF);␊
168 /* The poll loop must have run at least a few times for accuracy */␊
169 if(pollCount <= 1)␊
170 continue;␊
171 /* The TSC must increment at LEAST once every millisecond. We␊
172 * should have waited exactly 30 msec so the APERF delta should␊
173 * be >= 30. Anything less and the processor is way too slow.␊
174 */␊
175 if((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
176 continue;␊
177 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
178 if( (aperfEnd - aperfStart) < aperfDelta )␊
179 aperfDelta = aperfEnd - aperfStart;␊
180 }␊
181 /* mperfDelta is now the least number of MPERF ticks the processor made in␊
182 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
183 */␊
184␊
185 if(aperfDelta > (1ULL<<32))␊
186 retval = 0;␊
187 else␊
188 {␊
189 retval = aperfDelta * 1000 / 30;␊
190 }␊
191 disable_PIT2();␊
192 return retval;␊
193}␊
194␊
195␊
196/*␊
197 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
198 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
199 * a max multi. (used to calculate the FSB freq.),␊
200 * and a current multi. (used to calculate the CPU freq.)␊
201 * - fsbFrequency = tscFrequency / multi␊
202 * - cpuFrequency = fsbFrequency * multi␊
203 */␊
204␊
205void scan_cpu(PlatformInfo_t *p)␊
206{␊
207␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
208␉uint64_t␉msr, flex_ratio;␊
209␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
210␉const char *newratio;␊
211␉int len, myfsb;␊
212␉uint8_t bus_ratio_min;␊
213␉uint32_t max_ratio, min_ratio;␊
214␊
215␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
216␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
217␊
218␉/* get cpuid values */␊
219␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
220␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
221␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
222␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
223␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
224␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
225 if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊
226 do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
227 do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
228␉}␊
229 else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
230␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
231␉}␊
232 ␊
233 ␊
234#if DEBUG_CPU␊
235␉{␊
236␉␉int␉␉i;␊
237␉␉printf("CPUID Raw Values:\n");␊
238␉␉for (i=0; i<CPUID_MAX; i++) {␊
239␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
240␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
241␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
242␉␉}␊
243␉}␊
244␉␉getchar();␊
245#endif␊
246␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
247␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
248␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
249␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
250␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
251␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
252␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
253␉␊
254 p->CPU.Model += (p->CPU.ExtModel << 4);␊
255#if DEBUG_CPU␊
256␉printf("Enter cpuid_info\n");␊
257␉getchar();␊
258#endif␊
259 ␊
260 if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ␊
261 p->CPU.Family == 0x06 && ␊
262 p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
263 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
264 )␊
265 {␊
266 msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
267 p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
268 p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
269␉}␊
270 else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
271 {␊
272 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
273 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
274 }␊
275 else␊
276 {␊
277 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
278 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
279␉}␊
280#if DEBUG_CPU␊
281␉printf("...OK\n");␊
282␉getchar();␊
283#endif␊
284␉␊
285␉/* get brand string (if supported) */␊
286␉/* Copyright: from Apple's XNU cpuid.c */␊
287␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
288␉␉uint32_t␉reg[4];␊
289 char str[128], *s;␊
290␉␉/*␊
291␉␉ * The brand string 48 bytes (max), guaranteed to␊
292␉␉ * be NULL terminated.␊
293␉␉ */␊
294␉␉do_cpuid(0x80000002, reg);␊
295␉␉bcopy((char *)reg, &str[0], 16);␊
296␉␉do_cpuid(0x80000003, reg);␊
297␉␉bcopy((char *)reg, &str[16], 16);␊
298␉␉do_cpuid(0x80000004, reg);␊
299␉␉bcopy((char *)reg, &str[32], 16);␊
300␉␉for (s = str; *s != '\0'; s++) {␊
301␉␉␉if (*s != ' ') break;␊
302␉␉}␊
303␉␉␊
304␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
305␉␉␊
306␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
307␉␉␉ /*␊
308␉␉␉ * This string means we have a firmware-programmable brand string,␊
309␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
310␉␉␉ */␊
311␉␉␉ p->CPU.BrandString[0] = '\0';␊
312␉␉ }␊
313␉}␊
314#if DEBUG_CPU␊
315␉{␊
316␉␉int␉␉i;␊
317␉␉DBG("CPUID Raw Values:\n");␊
318␉␉for (i=0; i<CPUID_MAX; i++) {␊
319␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊
320␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
321␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
322␉␉}␊
323␉}␊
324␉getchar();␊
325#endif␊
326␉␊
327␉/* setup features */␊
328␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
329␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
330␉}␊
331␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
332␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
333␉}␊
334␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
335␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
336␉}␊
337␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
338␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
339␉}␊
340␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
341␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
342␉}␊
343␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
344␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
345␉}␊
346␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
347␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
348␉}␊
349␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
350␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
351␉}␊
352␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
353␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
354␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
355␉}␊
356␊
357␉tscFrequency = measure_tsc_frequency();␊
358␉fsbFrequency = 0;␊
359␉cpuFrequency = 0;␊
360␊
361␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
362//␉␉int intelCPU = p->CPU.Model;␊
363␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
364␉␉␉/* Nehalem CPU model */␊
365␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
366 p->CPU.Model == CPU_MODEL_FIELDS || ␊
367 p->CPU.Model == CPU_MODEL_DALES || ␊
368 p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
369 p->CPU.Model == CPU_MODEL_WESTMERE ||␊
370 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
371 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
372 p->CPU.Model == CPU_MODEL_SANDY ||␊
373 p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
374␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
375␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊
376␉␉␉␉(msr >> 32) & 0xffffffff, msr & 0xffffffff);␊
377␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
378 bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
379␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
380␉␉␉␉DBG("msr(0x%04x): flex_ratio %08x\n", MSR_FLEX_RATIO, msr & 0xffffffff);␊
381␉␉␉␉if ((msr >> 16) & 0x01) {␊
382␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊
383␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
384␉␉␉␉␉ where the cpu multipler can't be changed to␊
385␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
386␉␉␉␉␉ contents. These contents cause mach_kernel to␊
387␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
388␉␉␉␉␉ causing the system to crash since tscGranularity␊
389␉␉␉␉␉ is inadvertently set to 0.␊
390␉␉␉␉␉*/␊
391␉␉␉␉␉if (flex_ratio == 0) {␊
392␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
393␉␉␉␉␉␉ presence bit) */␊
394␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
395␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
396 verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
397␉␉␉␉␉} else {␊
398␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
399␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
400␉␉␉␉␉␉}␊
401␉␉␉␉␉}␊
402␉␉␉␉}␊
403␊
404␉␉␉␉if (bus_ratio_max) {␊
405␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
406␉␉␉␉}␊
407␉␉␉␉//valv: Turbo Ratio Limit␊
408␉/*␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
409␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
410␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
411␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
412␉␉␉␉} else */␊
413␉␉␉␉{␊
414␉␉␉␉␉cpuFrequency = tscFrequency;␊
415␉␉␉␉}␊
416␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
417␉␉␉␉␉max_ratio = atoi(newratio);␊
418␉␉␉␉␉max_ratio = (max_ratio * 10);␊
419␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
420␊
421␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
422␊
423␉␉␉␉␉// extreme overclockers may love 320 ;)␊
424␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
425␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
426␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
427␉␉␉␉␉␉else maxdiv = 0;␊
428␉␉␉␉␉} else {␊
429␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
430␉␉␉␉␉}␊
431␉␉␉␉}␊
432␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
433␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
434␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
435␉␉␉␉p->CPU.MinRatio = min_ratio;␊
436␊
437␉␉␉␉myfsb = fsbFrequency / 1000000;␊
438␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
439␉␉␉␉currcoef = bus_ratio_max;␊
440␉␉␉} else {␊
441␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
442␉␉␉␉DBG("msr(0x%x): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
443␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
444␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
445 maxdiv = bitfield(msr, 46, 46);␊
446␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
447 currdiv = bitfield(msr, 14, 14);␊
448␊
449␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
450␉␉␉␉{␊
451␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
452 maxcoef = bitfield(msr, 44, 40);␊
453␉␉␉␉} else {␊
454␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
455␉␉␉␉␉/* XXX */␊
456␉␉␉␉␉maxcoef = currcoef;␊
457␉␉␉␉}␊
458␊
459␉␉␉␉if (maxcoef) {␊
460␉␉␉␉␉if (maxdiv) {␊
461␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
462␉␉␉␉␉} else {␊
463␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
464␉␉␉␉␉}␊
465␉␉␉␉␉if (currdiv) {␊
466␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
467␉␉␉␉␉} else {␊
468␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
469␉␉␉␉␉}␊
470␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
471␉␉␉␉}␊
472␉␉␉}␊
473␉␉}␊
474␉␉/* Mobile CPU ? */␊
475//Slice ␊
476#if DEBUG_CPU␊
477␉pause();␊
478#endif␊
479␉␊
480␊
481␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
482␉␉DBG("msr(0x%04x): MSR_IA32_PLATFORM_ID 0x%08x\n", MSR_IA32_PLATFORM_ID, msr & 0xffffffff); //__LINE__ - source line number :)␊
483␉␉if (msr) {␊
484␉␉␉p->CPU.Mobile = FALSE;␊
485␉␉␉switch (p->CPU.Model) {␊
486␉␉␉␉case 0x0D:␊
487␉␉␉␉␉p->CPU.Mobile = TRUE; // CPU_FEATURE_MOBILE;␊
488␉␉␉␉␉break;␊
489␉␉␉␉case 0x0F:␊
490␉␉␉␉␉p->CPU.Mobile = FALSE; // CPU_FEATURE_MOBILE;␊
491␉␉␉␉␉break;␊
492␉␉␉␉case 0x02:␊
493␉␉␉␉case 0x03:␊
494␉␉␉␉case 0x04:␊
495␉␉␉␉case 0x06:␉␊
496␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_P4_EBC_FREQUENCY_ID) && (1 << 21));␊
497␉␉␉␉␉break;␊
498␉␉␉␉default:␊
499␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_IA32_PLATFORM_ID) && (1<<28));␊
500␉␉␉␉␉break;␊
501␉␉␉}␊
502␉␉␉if (p->CPU.Mobile) {␊
503␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
504␉␉}␊
505␉}␊
506␉␉DBG("CPU is %s\n", p->CPU.Mobile?"Mobile":"Desktop");␊
507␉␉␉␊
508␉}␊
509␉else if((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
510 {␊
511 switch(p->CPU.ExtFamily)␊
512 {␊
513 case 0x00: /* K8 */␊
514 msr = rdmsr64(K8_FIDVID_STATUS);␊
515 maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
516 currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
517 break;␊
518 ␊
519 case 0x01: /* K10 */␊
520 msr = rdmsr64(K10_COFVID_STATUS);␊
521 do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
522 if(bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1) // EffFreq: effective frequency interface␊
523 {␊
524 //uint64_t mperf = measure_mperf_frequency();␊
525 uint64_t aperf = measure_aperf_frequency();␊
526 cpuFrequency = aperf;␊
527 }␊
528 // NOTE: tsc runs at the maccoeff (non turbo)␊
529 // *not* at the turbo frequency.␊
530 maxcoef = bitfield(msr, 54, 49) / 2 + 4;␊
531 currcoef = bitfield(msr, 5, 0) + 0x10;␊
532 currdiv = 2 << bitfield(msr, 8, 6);␊
533 ␊
534 break;␊
535 ␊
536 case 0x05: /* K14 */␊
537 msr = rdmsr64(K10_COFVID_STATUS);␊
538 currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
539 currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
540 currdiv += bitfield(msr, 3, 0);␊
541␊
542 break;␊
543 ␊
544 case 0x02: /* K11 */␊
545 // not implimented␊
546 break;␊
547 }␊
548 ␊
549 if (maxcoef)␊
550 {␊
551 if (currdiv)␊
552 {␊
553 if(!currcoef) currcoef = maxcoef;␊
554 if(!cpuFrequency)␊
555 fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
556 else ␊
557 fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
558␊
559 DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
560 } else {␊
561 if(!cpuFrequency)␊
562 fsbFrequency = (tscFrequency / maxcoef);␊
563 else ␊
564 fsbFrequency = (cpuFrequency / maxcoef);␊
565 DBG("%d\n", currcoef);␊
566 }␊
567 }␊
568 else if (currcoef)␊
569 {␊
570 if (currdiv)␊
571 {␊
572 fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
573 DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
574 } else {␊
575 fsbFrequency = (tscFrequency / currcoef);␊
576 DBG("%d\n", currcoef);␊
577 }␊
578 }␊
579 if(!cpuFrequency) cpuFrequency = tscFrequency;␊
580 }␊
581␉p->CPU.MaxCoef = maxcoef;␊
582␉p->CPU.MaxDiv = maxdiv;␊
583␉p->CPU.CurrCoef = currcoef;␊
584␉p->CPU.CurrDiv = currdiv;␊
585␉p->CPU.TSCFrequency = tscFrequency;␊
586␉p->CPU.FSBFrequency = fsbFrequency;␊
587␉p->CPU.CPUFrequency = cpuFrequency;␊
588␉DBG("CPU: Brand: %s\n", p->CPU.BrandString);␊
589␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊
590␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊
591␉DBG("CPU: MaxCoef/CurrCoef/Turbo: 0x%x/0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef, p->CPU.MaxCoef+1);␊
592␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊
593␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
594␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
595␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
596␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
597␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
598#if DEBUG_CPU␊
599␉getchar();␊
600#endif␊
601}␊
602

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