1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | //#include "mem.h"␊ |
9 | #include "smbios_getters.h"␊ |
10 | #include "cpu.h"␊ |
11 | #include "bootstruct.h"␊ |
12 | #include "boot.h"␊ |
13 | ␊ |
14 | #ifndef DEBUG_CPU␊ |
15 | #define DEBUG_CPU 0␊ |
16 | #endif␊ |
17 | ␊ |
18 | #if DEBUG_CPU␊ |
19 | #define DBG(x...)␉␉printf(x)␊ |
20 | #else␊ |
21 | #define DBG(x...)␉␉msglog(x)␊ |
22 | #endif␊ |
23 | ␊ |
24 | /*␊ |
25 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
26 | */␊ |
27 | static uint64_t measure_tsc_frequency(void)␊ |
28 | {␊ |
29 | uint64_t tscStart;␊ |
30 | uint64_t tscEnd;␊ |
31 | uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
32 | unsigned long pollCount;␊ |
33 | uint64_t retval = 0;␊ |
34 | int i;␊ |
35 | ␊ |
36 | /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
37 | * counter 2. We run this loop 3 times to make sure the cache␊ |
38 | * is hot and we take the minimum delta from all of the runs.␊ |
39 | * That is to say that we're biased towards measuring the minimum␊ |
40 | * number of TSC ticks that occur while waiting for the timer to␊ |
41 | * expire. That theoretically helps avoid inconsistencies when␊ |
42 | * running under a VM if the TSC is not virtualized and the host␊ |
43 | * steals time. The TSC is normally virtualized for VMware.␊ |
44 | */␊ |
45 | for(i = 0; i < 10; ++i)␊ |
46 | {␊ |
47 | enable_PIT2();␊ |
48 | set_PIT2_mode0(CALIBRATE_LATCH);␊ |
49 | tscStart = rdtsc64();␊ |
50 | pollCount = poll_PIT2_gate();␊ |
51 | tscEnd = rdtsc64();␊ |
52 | /* The poll loop must have run at least a few times for accuracy */␊ |
53 | if(pollCount <= 1)␊ |
54 | continue;␊ |
55 | /* The TSC must increment at LEAST once every millisecond. We␊ |
56 | * should have waited exactly 30 msec so the TSC delta should␊ |
57 | * be >= 30. Anything less and the processor is way too slow.␊ |
58 | */␊ |
59 | if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
60 | continue;␊ |
61 | // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
62 | if( (tscEnd - tscStart) < tscDelta )␊ |
63 | tscDelta = tscEnd - tscStart;␊ |
64 | }␊ |
65 | /* tscDelta is now the least number of TSC ticks the processor made in␊ |
66 | * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
67 | * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
68 | * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
69 | * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
70 | * dividing by the milliseconds, we simply multiply by 1000.␊ |
71 | */␊ |
72 | ␊ |
73 | /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
74 | * that we're going to multiply by 1000 first so we do need at least some␊ |
75 | * arithmetic headroom. For now, 32-bit should be enough.␊ |
76 | * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
77 | */␊ |
78 | if(tscDelta > (1ULL<<32))␊ |
79 | retval = 0;␊ |
80 | else␊ |
81 | {␊ |
82 | retval = tscDelta * 1000 / 30;␊ |
83 | }␊ |
84 | disable_PIT2();␊ |
85 | return retval;␊ |
86 | }␊ |
87 | ␊ |
88 | #if 0␊ |
89 | /*␊ |
90 | * DFE: Measures the Max Performance Frequency in Hz (64-bit)␊ |
91 | */␊ |
92 | static uint64_t measure_mperf_frequency(void)␊ |
93 | {␊ |
94 | uint64_t mperfStart;␊ |
95 | uint64_t mperfEnd;␊ |
96 | uint64_t mperfDelta = 0xffffffffffffffffULL;␊ |
97 | unsigned long pollCount;␊ |
98 | uint64_t retval = 0;␊ |
99 | int i;␊ |
100 | ␊ |
101 | /* Time how many MPERF ticks elapse in 30 msec using the 8254 PIT␊ |
102 | * counter 2. We run this loop 3 times to make sure the cache␊ |
103 | * is hot and we take the minimum delta from all of the runs.␊ |
104 | * That is to say that we're biased towards measuring the minimum␊ |
105 | * number of MPERF ticks that occur while waiting for the timer to␊ |
106 | * expire.␊ |
107 | */␊ |
108 | for(i = 0; i < 10; ++i)␊ |
109 | {␊ |
110 | enable_PIT2();␊ |
111 | set_PIT2_mode0(CALIBRATE_LATCH);␊ |
112 | mperfStart = rdmsr64(MSR_AMD_MPERF);␊ |
113 | pollCount = poll_PIT2_gate();␊ |
114 | mperfEnd = rdmsr64(MSR_AMD_MPERF);␊ |
115 | /* The poll loop must have run at least a few times for accuracy */␊ |
116 | if(pollCount <= 1)␊ |
117 | continue;␊ |
118 | /* The MPERF must increment at LEAST once every millisecond. We␊ |
119 | * should have waited exactly 30 msec so the MPERF delta should␊ |
120 | * be >= 30. Anything less and the processor is way too slow.␊ |
121 | */␊ |
122 | if((mperfEnd - mperfStart) <= CALIBRATE_TIME_MSEC)␊ |
123 | continue;␊ |
124 | // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
125 | if( (mperfEnd - mperfStart) < mperfDelta )␊ |
126 | mperfDelta = mperfEnd - mperfStart;␊ |
127 | }␊ |
128 | /* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
129 | * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
130 | */␊ |
131 | ␊ |
132 | if(mperfDelta > (1ULL<<32))␊ |
133 | retval = 0;␊ |
134 | else␊ |
135 | {␊ |
136 | retval = mperfDelta * 1000 / 30;␊ |
137 | }␊ |
138 | disable_PIT2();␊ |
139 | return retval;␊ |
140 | }␊ |
141 | #endif␊ |
142 | /*␊ |
143 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
144 | */␊ |
145 | static uint64_t measure_aperf_frequency(void)␊ |
146 | {␊ |
147 | uint64_t aperfStart;␊ |
148 | uint64_t aperfEnd;␊ |
149 | uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
150 | unsigned long pollCount;␊ |
151 | uint64_t retval = 0;␊ |
152 | int i;␊ |
153 | ␊ |
154 | /* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
155 | * counter 2. We run this loop 3 times to make sure the cache␊ |
156 | * is hot and we take the minimum delta from all of the runs.␊ |
157 | * That is to say that we're biased towards measuring the minimum␊ |
158 | * number of APERF ticks that occur while waiting for the timer to␊ |
159 | * expire. ␊ |
160 | */␊ |
161 | for(i = 0; i < 10; ++i)␊ |
162 | {␊ |
163 | enable_PIT2();␊ |
164 | set_PIT2_mode0(CALIBRATE_LATCH);␊ |
165 | aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
166 | pollCount = poll_PIT2_gate();␊ |
167 | aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
168 | /* The poll loop must have run at least a few times for accuracy */␊ |
169 | if(pollCount <= 1)␊ |
170 | continue;␊ |
171 | /* The TSC must increment at LEAST once every millisecond. We␊ |
172 | * should have waited exactly 30 msec so the APERF delta should␊ |
173 | * be >= 30. Anything less and the processor is way too slow.␊ |
174 | */␊ |
175 | if((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
176 | continue;␊ |
177 | // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
178 | if( (aperfEnd - aperfStart) < aperfDelta )␊ |
179 | aperfDelta = aperfEnd - aperfStart;␊ |
180 | }␊ |
181 | /* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
182 | * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
183 | */␊ |
184 | ␊ |
185 | if(aperfDelta > (1ULL<<32))␊ |
186 | retval = 0;␊ |
187 | else␊ |
188 | {␊ |
189 | retval = aperfDelta * 1000 / 30;␊ |
190 | }␊ |
191 | disable_PIT2();␊ |
192 | return retval;␊ |
193 | }␊ |
194 | ␊ |
195 | ␊ |
196 | /*␊ |
197 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
198 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
199 | * a max multi. (used to calculate the FSB freq.),␊ |
200 | * and a current multi. (used to calculate the CPU freq.)␊ |
201 | * - fsbFrequency = tscFrequency / multi␊ |
202 | * - cpuFrequency = fsbFrequency * multi␊ |
203 | */␊ |
204 | ␊ |
205 | void scan_cpu(PlatformInfo_t *p)␊ |
206 | {␊ |
207 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊ |
208 | ␉uint64_t␉msr, flex_ratio;␊ |
209 | ␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊ |
210 | ␉const char *newratio;␊ |
211 | ␉int len, myfsb;␊ |
212 | ␉uint8_t bus_ratio_min;␊ |
213 | ␉uint32_t max_ratio, min_ratio;␊ |
214 | ␊ |
215 | ␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊ |
216 | ␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊ |
217 | ␊ |
218 | ␉/* get cpuid values */␊ |
219 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
220 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
221 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊ |
222 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊ |
223 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
224 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
225 | if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊ |
226 | do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
227 | do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
228 | ␉}␊ |
229 | else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊ |
230 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
231 | ␉}␊ |
232 | ␊ |
233 | ␊ |
234 | #if DEBUG_CPU␊ |
235 | ␉{␊ |
236 | ␉␉int␉␉i;␊ |
237 | ␉␉printf("CPUID Raw Values:\n");␊ |
238 | ␉␉for (i=0; i<CPUID_MAX; i++) {␊ |
239 | ␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
240 | ␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
241 | ␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
242 | ␉␉}␊ |
243 | ␉}␊ |
244 | ␉␉getchar();␊ |
245 | #endif␊ |
246 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
247 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
248 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
249 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
250 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
251 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
252 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
253 | ␉␊ |
254 | p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
255 | #if DEBUG_CPU␊ |
256 | ␉printf("Enter cpuid_info\n");␊ |
257 | ␉getchar();␊ |
258 | #endif␊ |
259 | ␊ |
260 | if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ␊ |
261 | p->CPU.Family == 0x06 && ␊ |
262 | p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊ |
263 | p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊ |
264 | )␊ |
265 | {␊ |
266 | msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊ |
267 | p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊ |
268 | p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊ |
269 | ␉}␊ |
270 | else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊ |
271 | {␊ |
272 | p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
273 | p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
274 | }␊ |
275 | else␊ |
276 | {␊ |
277 | p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊ |
278 | p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
279 | ␉}␊ |
280 | #if DEBUG_CPU␊ |
281 | ␉printf("...OK\n");␊ |
282 | ␉getchar();␊ |
283 | #endif␊ |
284 | ␉␊ |
285 | ␉/* get brand string (if supported) */␊ |
286 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
287 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊ |
288 | ␉␉uint32_t␉reg[4];␊ |
289 | char str[128], *s;␊ |
290 | ␉␉/*␊ |
291 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
292 | ␉␉ * be NULL terminated.␊ |
293 | ␉␉ */␊ |
294 | ␉␉do_cpuid(0x80000002, reg);␊ |
295 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
296 | ␉␉do_cpuid(0x80000003, reg);␊ |
297 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
298 | ␉␉do_cpuid(0x80000004, reg);␊ |
299 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
300 | ␉␉for (s = str; *s != '\0'; s++) {␊ |
301 | ␉␉␉if (*s != ' ') break;␊ |
302 | ␉␉}␊ |
303 | ␉␉␊ |
304 | ␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊ |
305 | ␉␉␊ |
306 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
307 | ␉␉␉ /*␊ |
308 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
309 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
310 | ␉␉␉ */␊ |
311 | ␉␉␉ p->CPU.BrandString[0] = '\0';␊ |
312 | ␉␉ }␊ |
313 | ␉}␊ |
314 | ␉␊ |
315 | ␉/* setup features */␊ |
316 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
317 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
318 | ␉}␊ |
319 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
320 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
321 | ␉}␊ |
322 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
323 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
324 | ␉}␊ |
325 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
326 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
327 | ␉}␊ |
328 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
329 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
330 | ␉}␊ |
331 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
332 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
333 | ␉}␊ |
334 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊ |
335 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
336 | ␉}␊ |
337 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
338 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
339 | ␉}␊ |
340 | ␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
341 | ␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊ |
342 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
343 | ␉}␊ |
344 | ␊ |
345 | ␉tscFrequency = measure_tsc_frequency();␊ |
346 | ␉fsbFrequency = 0;␊ |
347 | ␉cpuFrequency = 0;␊ |
348 | ␊ |
349 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊ |
350 | //␉␉int intelCPU = p->CPU.Model;␊ |
351 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊ |
352 | ␉␉␉/* Nehalem CPU model */␊ |
353 | ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊ |
354 | p->CPU.Model == CPU_MODEL_FIELDS || ␊ |
355 | p->CPU.Model == CPU_MODEL_DALES || ␊ |
356 | p->CPU.Model == CPU_MODEL_DALES_32NM || ␊ |
357 | p->CPU.Model == CPU_MODEL_WESTMERE ||␊ |
358 | p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊ |
359 | p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊ |
360 | p->CPU.Model == CPU_MODEL_SANDY ||␊ |
361 | p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊ |
362 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
363 | ␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊ |
364 | ␉␉␉␉(msr >> 32) & 0xffffffff, msr & 0xffffffff);␊ |
365 | ␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊ |
366 | bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊ |
367 | ␉␉␉//␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
368 | ␉␉␉ msr = 0;␊ |
369 | ␉␉␉␉DBG("msr(0x%04x): flex_ratio %08x\n", MSR_FLEX_RATIO, msr & 0xffffffff);␊ |
370 | ␉␉␉␉if ((msr >> 16) & 0x01) {␊ |
371 | ␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊ |
372 | ␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
373 | ␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
374 | ␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
375 | ␉␉␉␉␉ contents. These contents cause mach_kernel to␊ |
376 | ␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
377 | ␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
378 | ␉␉␉␉␉ is inadvertently set to 0.␊ |
379 | ␉␉␉␉␉*/␊ |
380 | ␉␉␉␉␉if (flex_ratio == 0) {␊ |
381 | ␉␉␉␉␉␉/* Clear bit 16 (evidently the␊ |
382 | ␉␉␉␉␉␉ presence bit) */␊ |
383 | ␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
384 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
385 | verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
386 | ␉␉␉␉␉} else {␊ |
387 | ␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊ |
388 | ␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
389 | ␉␉␉␉␉␉}␊ |
390 | ␉␉␉␉␉}␊ |
391 | ␉␉␉␉}␊ |
392 | ␊ |
393 | ␉␉␉␉if (bus_ratio_max) {␊ |
394 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
395 | ␉␉␉␉}␊ |
396 | ␉␉␉␉//valv: Turbo Ratio Limit␊ |
397 | ␉/*␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊ |
398 | ␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
399 | ␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
400 | ␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
401 | ␉␉␉␉} else */␊ |
402 | ␉␉␉␉{␊ |
403 | ␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
404 | ␉␉␉␉}␊ |
405 | ␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊ |
406 | ␉␉␉␉␉max_ratio = atoi(newratio);␊ |
407 | ␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
408 | ␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊ |
409 | ␊ |
410 | ␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
411 | ␊ |
412 | ␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
413 | ␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊ |
414 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
415 | ␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊ |
416 | ␉␉␉␉␉␉else maxdiv = 0;␊ |
417 | ␉␉␉␉␉} else {␊ |
418 | ␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
419 | ␉␉␉␉␉}␊ |
420 | ␉␉␉␉}␊ |
421 | ␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
422 | ␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
423 | ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
424 | ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
425 | ␊ |
426 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
427 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊ |
428 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
429 | ␉␉␉} else {␊ |
430 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
431 | ␉␉␉␉DBG("msr(0x%x): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
432 | ␉␉␉␉currcoef = bitfield(msr, 12, 8);␊ |
433 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
434 | maxdiv = bitfield(msr, 46, 46);␊ |
435 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
436 | currdiv = bitfield(msr, 14, 14);␊ |
437 | ␊ |
438 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊ |
439 | ␉␉␉␉{␊ |
440 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
441 | maxcoef = bitfield(msr, 44, 40);␊ |
442 | ␉␉␉␉} else {␊ |
443 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
444 | ␉␉␉␉␉/* XXX */␊ |
445 | ␉␉␉␉␉maxcoef = currcoef;␊ |
446 | ␉␉␉␉}␊ |
447 | ␊ |
448 | ␉␉␉␉if (maxcoef) {␊ |
449 | ␉␉␉␉␉if (maxdiv) {␊ |
450 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
451 | ␉␉␉␉␉} else {␊ |
452 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
453 | ␉␉␉␉␉}␊ |
454 | ␉␉␉␉␉if (currdiv) {␊ |
455 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
456 | ␉␉␉␉␉} else {␊ |
457 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
458 | ␉␉␉␉␉}␊ |
459 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
460 | ␉␉␉␉}␊ |
461 | ␉␉␉}␊ |
462 | ␉␉}␊ |
463 | ␉␉/* Mobile CPU ? */␊ |
464 | //Slice - no more needed␊ |
465 | #if 0 // DEBUG_CPU␊ |
466 | ␉pause();␊ |
467 | ␊ |
468 | ␉␊ |
469 | ␊ |
470 | ␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊ |
471 | ␉␉DBG("msr(0x%04x): MSR_IA32_PLATFORM_ID 0x%08x\n", MSR_IA32_PLATFORM_ID, msr & 0xffffffff); //__LINE__ - source line number :)␊ |
472 | ␉␉if (msr) {␊ |
473 | ␉␉␉p->CPU.Mobile = FALSE;␊ |
474 | ␉␉␉switch (p->CPU.Model) {␊ |
475 | ␉␉␉␉case 0x0D:␊ |
476 | ␉␉␉␉␉p->CPU.Mobile = TRUE; // CPU_FEATURE_MOBILE;␊ |
477 | ␉␉␉␉␉break;␊ |
478 | ␉␉␉␉case 0x0F:␊ |
479 | ␉␉␉␉␉p->CPU.Mobile = FALSE; // CPU_FEATURE_MOBILE;␊ |
480 | ␉␉␉␉␉break;␊ |
481 | ␉␉␉␉case 0x02:␊ |
482 | ␉␉␉␉case 0x03:␊ |
483 | ␉␉␉␉case 0x04:␊ |
484 | ␉␉␉␉case 0x06:␉␊ |
485 | ␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_P4_EBC_FREQUENCY_ID) && (1 << 21));␊ |
486 | ␉␉␉␉␉break;␊ |
487 | ␉␉␉␉default:␊ |
488 | ␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_IA32_PLATFORM_ID) && (1<<28));␊ |
489 | ␉␉␉␉␉break;␊ |
490 | ␉␉␉}␊ |
491 | ␉␉␉if (p->CPU.Mobile) {␊ |
492 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
493 | ␉␉}␊ |
494 | ␉}␊ |
495 | ␉␉DBG("CPU is %s\n", p->CPU.Mobile?"Mobile":"Desktop");␊ |
496 | ␉␉␉␊ |
497 | ␉}␊ |
498 | ␉else if((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
499 | {␊ |
500 | switch(p->CPU.ExtFamily)␊ |
501 | {␊ |
502 | case 0x00: /* K8 */␊ |
503 | msr = rdmsr64(K8_FIDVID_STATUS);␊ |
504 | maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
505 | currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
506 | break;␊ |
507 | ␊ |
508 | case 0x01: /* K10 */␊ |
509 | msr = rdmsr64(K10_COFVID_STATUS);␊ |
510 | do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
511 | if(bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1) // EffFreq: effective frequency interface␊ |
512 | {␊ |
513 | //uint64_t mperf = measure_mperf_frequency();␊ |
514 | uint64_t aperf = measure_aperf_frequency();␊ |
515 | cpuFrequency = aperf;␊ |
516 | }␊ |
517 | // NOTE: tsc runs at the maccoeff (non turbo)␊ |
518 | // *not* at the turbo frequency.␊ |
519 | maxcoef = bitfield(msr, 54, 49) / 2 + 4;␊ |
520 | currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
521 | currdiv = 2 << bitfield(msr, 8, 6);␊ |
522 | ␊ |
523 | break;␊ |
524 | ␊ |
525 | case 0x05: /* K14 */␊ |
526 | msr = rdmsr64(K10_COFVID_STATUS);␊ |
527 | currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
528 | currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
529 | currdiv += bitfield(msr, 3, 0);␊ |
530 | ␊ |
531 | break;␊ |
532 | ␊ |
533 | case 0x02: /* K11 */␊ |
534 | // not implimented␊ |
535 | break;␊ |
536 | }␊ |
537 | ␊ |
538 | if (maxcoef)␊ |
539 | {␊ |
540 | if (currdiv)␊ |
541 | {␊ |
542 | if(!currcoef) currcoef = maxcoef;␊ |
543 | if(!cpuFrequency)␊ |
544 | fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
545 | else ␊ |
546 | fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
547 | ␊ |
548 | DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
549 | } else {␊ |
550 | if(!cpuFrequency)␊ |
551 | fsbFrequency = (tscFrequency / maxcoef);␊ |
552 | else ␊ |
553 | fsbFrequency = (cpuFrequency / maxcoef);␊ |
554 | DBG("%d\n", currcoef);␊ |
555 | }␊ |
556 | }␊ |
557 | else if (currcoef)␊ |
558 | {␊ |
559 | if (currdiv)␊ |
560 | {␊ |
561 | fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
562 | DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
563 | } else {␊ |
564 | fsbFrequency = (tscFrequency / currcoef);␊ |
565 | DBG("%d\n", currcoef);␊ |
566 | }␊ |
567 | }␊ |
568 | if(!cpuFrequency) cpuFrequency = tscFrequency;␊ |
569 | }␊ |
570 | #endif ␊ |
571 | ␉p->CPU.MaxCoef = maxcoef;␊ |
572 | ␉p->CPU.MaxDiv = maxdiv;␊ |
573 | ␉p->CPU.CurrCoef = currcoef;␊ |
574 | ␉p->CPU.CurrDiv = currdiv;␊ |
575 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
576 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
577 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
578 | ␉DBG("CPU: Brand: %s\n", p->CPU.BrandString);␊ |
579 | ␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊ |
580 | ␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊ |
581 | ␉DBG("CPU: MaxCoef/CurrCoef/Turbo: 0x%x/0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef, p->CPU.MaxCoef+1);␊ |
582 | ␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊ |
583 | ␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊ |
584 | ␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊ |
585 | ␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊ |
586 | ␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊ |
587 | ␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊ |
588 | #if DEBUG_CPU␊ |
589 | ␉getchar();␊ |
590 | #endif␊ |
591 | }␊ |
592 | |