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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8//#include "mem.h"␊
9#include "smbios_getters.h"␊
10#include "cpu.h"␊
11#include "bootstruct.h"␊
12#include "boot.h"␊
13␊
14#ifndef DEBUG_CPU␊
15#define DEBUG_CPU 1␊
16#endif␊
17␊
18#if DEBUG_CPU␊
19#define DBG(x...)␉␉printf(x)␊
20#else␊
21#define DBG(x...)␉␉msglog(x)␊
22#endif␊
23␊
24/*␊
25 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
26 */␊
27static uint64_t measure_tsc_frequency(void)␊
28{␊
29 uint64_t tscStart;␊
30 uint64_t tscEnd;␊
31 uint64_t tscDelta = 0xffffffffffffffffULL;␊
32 unsigned long pollCount;␊
33 uint64_t retval = 0;␊
34 int i;␊
35␊
36 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
37 * counter 2. We run this loop 3 times to make sure the cache␊
38 * is hot and we take the minimum delta from all of the runs.␊
39 * That is to say that we're biased towards measuring the minimum␊
40 * number of TSC ticks that occur while waiting for the timer to␊
41 * expire. That theoretically helps avoid inconsistencies when␊
42 * running under a VM if the TSC is not virtualized and the host␊
43 * steals time. The TSC is normally virtualized for VMware.␊
44 */␊
45 for(i = 0; i < 10; ++i)␊
46 {␊
47 enable_PIT2();␊
48 set_PIT2_mode0(CALIBRATE_LATCH);␊
49 tscStart = rdtsc64();␊
50 pollCount = poll_PIT2_gate();␊
51 tscEnd = rdtsc64();␊
52 /* The poll loop must have run at least a few times for accuracy */␊
53 if(pollCount <= 1)␊
54 continue;␊
55 /* The TSC must increment at LEAST once every millisecond. We␊
56 * should have waited exactly 30 msec so the TSC delta should␊
57 * be >= 30. Anything less and the processor is way too slow.␊
58 */␊
59 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
60 continue;␊
61 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
62 if( (tscEnd - tscStart) < tscDelta )␊
63 tscDelta = tscEnd - tscStart;␊
64 }␊
65 /* tscDelta is now the least number of TSC ticks the processor made in␊
66 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
67 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
68 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
69 * Hz so we need to convert our milliseconds to seconds. Since we're␊
70 * dividing by the milliseconds, we simply multiply by 1000.␊
71 */␊
72␊
73 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
74 * that we're going to multiply by 1000 first so we do need at least some␊
75 * arithmetic headroom. For now, 32-bit should be enough.␊
76 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
77 */␊
78 if(tscDelta > (1ULL<<32))␊
79 retval = 0;␊
80 else␊
81 {␊
82 retval = tscDelta * 1000 / 30;␊
83 }␊
84 disable_PIT2();␊
85 return retval;␊
86}␊
87␊
88#if 0␊
89/*␊
90 * DFE: Measures the Max Performance Frequency in Hz (64-bit)␊
91 */␊
92static uint64_t measure_mperf_frequency(void)␊
93{␊
94 uint64_t mperfStart;␊
95 uint64_t mperfEnd;␊
96 uint64_t mperfDelta = 0xffffffffffffffffULL;␊
97 unsigned long pollCount;␊
98 uint64_t retval = 0;␊
99 int i;␊
100 ␊
101 /* Time how many MPERF ticks elapse in 30 msec using the 8254 PIT␊
102 * counter 2. We run this loop 3 times to make sure the cache␊
103 * is hot and we take the minimum delta from all of the runs.␊
104 * That is to say that we're biased towards measuring the minimum␊
105 * number of MPERF ticks that occur while waiting for the timer to␊
106 * expire.␊
107 */␊
108 for(i = 0; i < 10; ++i)␊
109 {␊
110 enable_PIT2();␊
111 set_PIT2_mode0(CALIBRATE_LATCH);␊
112 mperfStart = rdmsr64(MSR_AMD_MPERF);␊
113 pollCount = poll_PIT2_gate();␊
114 mperfEnd = rdmsr64(MSR_AMD_MPERF);␊
115 /* The poll loop must have run at least a few times for accuracy */␊
116 if(pollCount <= 1)␊
117 continue;␊
118 /* The MPERF must increment at LEAST once every millisecond. We␊
119 * should have waited exactly 30 msec so the MPERF delta should␊
120 * be >= 30. Anything less and the processor is way too slow.␊
121 */␊
122 if((mperfEnd - mperfStart) <= CALIBRATE_TIME_MSEC)␊
123 continue;␊
124 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
125 if( (mperfEnd - mperfStart) < mperfDelta )␊
126 mperfDelta = mperfEnd - mperfStart;␊
127 }␊
128 /* mperfDelta is now the least number of MPERF ticks the processor made in␊
129 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
130 */␊
131 ␊
132 if(mperfDelta > (1ULL<<32))␊
133 retval = 0;␊
134 else␊
135 {␊
136 retval = mperfDelta * 1000 / 30;␊
137 }␊
138 disable_PIT2();␊
139 return retval;␊
140}␊
141#endif␊
142/*␊
143 * Measures the Actual Performance Frequency in Hz (64-bit)␊
144 */␊
145static uint64_t measure_aperf_frequency(void)␊
146{␊
147 uint64_t aperfStart;␊
148 uint64_t aperfEnd;␊
149 uint64_t aperfDelta = 0xffffffffffffffffULL;␊
150 unsigned long pollCount;␊
151 uint64_t retval = 0;␊
152 int i;␊
153 ␊
154 /* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
155 * counter 2. We run this loop 3 times to make sure the cache␊
156 * is hot and we take the minimum delta from all of the runs.␊
157 * That is to say that we're biased towards measuring the minimum␊
158 * number of APERF ticks that occur while waiting for the timer to␊
159 * expire. ␊
160 */␊
161 for(i = 0; i < 10; ++i)␊
162 {␊
163 enable_PIT2();␊
164 set_PIT2_mode0(CALIBRATE_LATCH);␊
165 aperfStart = rdmsr64(MSR_AMD_APERF);␊
166 pollCount = poll_PIT2_gate();␊
167 aperfEnd = rdmsr64(MSR_AMD_APERF);␊
168 /* The poll loop must have run at least a few times for accuracy */␊
169 if(pollCount <= 1)␊
170 continue;␊
171 /* The TSC must increment at LEAST once every millisecond. We␊
172 * should have waited exactly 30 msec so the APERF delta should␊
173 * be >= 30. Anything less and the processor is way too slow.␊
174 */␊
175 if((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
176 continue;␊
177 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
178 if( (aperfEnd - aperfStart) < aperfDelta )␊
179 aperfDelta = aperfEnd - aperfStart;␊
180 }␊
181 /* mperfDelta is now the least number of MPERF ticks the processor made in␊
182 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
183 */␊
184␊
185 if(aperfDelta > (1ULL<<32))␊
186 retval = 0;␊
187 else␊
188 {␊
189 retval = aperfDelta * 1000 / 30;␊
190 }␊
191 disable_PIT2();␊
192 return retval;␊
193}␊
194␊
195␊
196/*␊
197 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
198 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
199 * a max multi. (used to calculate the FSB freq.),␊
200 * and a current multi. (used to calculate the CPU freq.)␊
201 * - fsbFrequency = tscFrequency / multi␊
202 * - cpuFrequency = fsbFrequency * multi␊
203 */␊
204␊
205void scan_cpu(PlatformInfo_t *p)␊
206{␊
207␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
208␉uint64_t␉msr, flex_ratio;␊
209␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
210␉const char *newratio;␊
211␉int len, myfsb;␊
212␉uint8_t bus_ratio_min;␊
213␉uint32_t max_ratio, min_ratio;␊
214␊
215␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
216␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
217␊
218␉/* get cpuid values */␊
219␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
220␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
221␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
222␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
223␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
224␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
225 if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊
226 do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
227 do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
228␉}␊
229 else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
230␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
231␉}␊
232 ␊
233 ␊
234#if DEBUG_CPU␊
235␉{␊
236␉␉int␉␉i;␊
237␉␉printf("CPUID Raw Values:\n");␊
238␉␉for (i=0; i<CPUID_MAX; i++) {␊
239␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
240␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
241␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
242␉␉}␊
243␉}␊
244␉␉getchar();␊
245#endif␊
246␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
247␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
248␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
249␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
250␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
251␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
252␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
253␉␊
254 p->CPU.Model += (p->CPU.ExtModel << 4);␊
255#if DEBUG_CPU␊
256␉printf("Enter cpuid_info\n");␊
257␉getchar();␊
258#endif␊
259 ␊
260 if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ␊
261 p->CPU.Family == 0x06 && ␊
262 p->CPU.Model >= CPUID_MODEL_NEHALEM && ␊
263 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU␊
264 )␊
265 {␊
266 msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
267 p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
268 p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
269␉}␊
270 else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
271 {␊
272 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
273 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
274 }␊
275 else␊
276 {␊
277 p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
278 p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
279␉}␊
280#if DEBUG_CPU␊
281␉printf("...OK\n");␊
282␉getchar();␊
283#endif␊
284␉␊
285␉/* get brand string (if supported) */␊
286␉/* Copyright: from Apple's XNU cpuid.c */␊
287␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
288␉␉uint32_t␉reg[4];␊
289 char str[128], *s;␊
290␉␉/*␊
291␉␉ * The brand string 48 bytes (max), guaranteed to␊
292␉␉ * be NULL terminated.␊
293␉␉ */␊
294␉␉do_cpuid(0x80000002, reg);␊
295␉␉bcopy((char *)reg, &str[0], 16);␊
296␉␉do_cpuid(0x80000003, reg);␊
297␉␉bcopy((char *)reg, &str[16], 16);␊
298␉␉do_cpuid(0x80000004, reg);␊
299␉␉bcopy((char *)reg, &str[32], 16);␊
300␉␉for (s = str; *s != '\0'; s++) {␊
301␉␉␉if (*s != ' ') break;␊
302␉␉}␊
303␉␉␊
304␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
305␉␉␊
306␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
307␉␉␉ /*␊
308␉␉␉ * This string means we have a firmware-programmable brand string,␊
309␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
310␉␉␉ */␊
311␉␉␉ p->CPU.BrandString[0] = '\0';␊
312␉␉ }␊
313␉}␊
314␉␊
315␉/* setup features */␊
316␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
317␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
318␉}␊
319␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
320␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
321␉}␊
322␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
323␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
324␉}␊
325␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
326␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
327␉}␊
328␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
329␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
330␉}␊
331␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
332␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
333␉}␊
334␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
335␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
336␉}␊
337␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
338␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
339␉}␊
340␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
341␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
342␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
343␉}␊
344␊
345␉tscFrequency = measure_tsc_frequency();␊
346␉fsbFrequency = 0;␊
347␉cpuFrequency = 0;␊
348␊
349␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06)␊
350␉␉␉␉␉␉␉␉␉␉␉|| (p->CPU.Family == 0x0f)))␊
351␉{␊
352//␉␉int intelCPU = p->CPU.Model;␊
353␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊
354␉␉{␊
355␉␉␉/* Nehalem CPU model */␊
356␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
357 p->CPU.Model == CPU_MODEL_FIELDS || ␊
358 p->CPU.Model == CPU_MODEL_DALES || ␊
359 p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
360 p->CPU.Model == CPU_MODEL_WESTMERE ||␊
361 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
362 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
363 p->CPU.Model == CPU_MODEL_SANDY ||␊
364 p->CPU.Model == CPU_MODEL_SANDY_XEON))␊
365␉␉␉{␊
366␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
367␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊
368␉␉␉␉(msr >> 32) & 0xffffffff, msr & 0xffffffff);␊
369␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
370 bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
371␉␉␉//␉msr = rdmsr64(MSR_FLEX_RATIO);␊
372␉␉␉ msr = 0;␊
373␉␉␉␉DBG("msr(0x%04x): flex_ratio %08x\n", MSR_FLEX_RATIO, msr & 0xffffffff);␊
374␉␉␉␉if ((msr >> 16) & 0x01) {␊
375␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊
376␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
377␉␉␉␉␉ where the cpu multipler can't be changed to␊
378␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
379␉␉␉␉␉ contents. These contents cause mach_kernel to␊
380␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
381␉␉␉␉␉ causing the system to crash since tscGranularity␊
382␉␉␉␉␉ is inadvertently set to 0.␊
383␉␉␉␉␉*/␊
384␉␉␉␉␉if (flex_ratio == 0) {␊
385␉␉␉␉␉␉/* Clear bit 16 (evidently the␊
386␉␉␉␉␉␉ presence bit) */␊
387␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
388␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
389 verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
390␉␉␉␉␉} else {␊
391␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
392␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
393␉␉␉␉␉␉}␊
394␉␉␉␉␉}␊
395␉␉␉␉}␊
396␊
397␉␉␉␉if (bus_ratio_max) {␊
398␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
399␉␉␉␉}␊
400␉␉␉␉//valv: Turbo Ratio Limit␊
401␉/*␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
402␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
403␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
404␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
405␉␉␉␉} else */␊
406␉␉//␉␉{␊
407␉␉␉␉␉cpuFrequency = tscFrequency;␊
408␉␉//␉␉}␊
409␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
410␉␉␉␉␉max_ratio = atoi(newratio);␊
411␉␉␉␉␉max_ratio = (max_ratio * 10);␊
412␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
413␊
414␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
415␊
416␉␉␉␉␉// extreme overclockers may love 320 ;)␊
417␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
418␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
419␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
420␉␉␉␉␉␉else maxdiv = 0;␊
421␉␉␉␉␉} else {␊
422␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
423␉␉␉␉␉}␊
424␉␉␉␉}␊
425␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
426␉␉␉␉/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
427␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
428␉␉␉␉p->CPU.MinRatio = min_ratio;␊
429␊
430␉␉␉␉myfsb = fsbFrequency / 1000000;␊
431␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
432␉␉␉␉currcoef = bus_ratio_max;␊
433␉␉␉} else {␊
434␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
435␉␉␉␉DBG("msr(0x%x): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
436␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
437␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
438 maxdiv = bitfield(msr, 46, 46);␊
439␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
440 currdiv = bitfield(msr, 14, 14);␊
441␊
442␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
443␉␉␉␉{␊
444␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
445 maxcoef = bitfield(msr, 44, 40);␊
446␉␉␉␉} else {␊
447␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
448␉␉␉␉␉/* XXX */␊
449␉␉␉␉␉maxcoef = currcoef;␊
450␉␉␉␉}␊
451␊
452␉␉␉␉if (maxcoef) {␊
453␉␉␉␉␉if (maxdiv) {␊
454␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
455␉␉␉␉␉} else {␊
456␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
457␉␉␉␉␉}␊
458␉␉␉␉␉if (currdiv) {␊
459␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
460␉␉␉␉␉} else {␊
461␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
462␉␉␉␉␉}␊
463␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
464␉␉␉␉}␊
465␉␉␉}␊
466␉␉}␊
467␉␉/* Mobile CPU ? */␊
468//Slice - no more needed␊
469#if 0 // DEBUG_CPU␊
470␉pause();␊
471␊
472␉␊
473␊
474␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊
475␉␉DBG("msr(0x%04x): MSR_IA32_PLATFORM_ID 0x%08x\n", MSR_IA32_PLATFORM_ID, msr & 0xffffffff); //__LINE__ - source line number :)␊
476␉␉if (msr) {␊
477␉␉␉p->CPU.Mobile = FALSE;␊
478␉␉␉switch (p->CPU.Model) {␊
479␉␉␉␉case 0x0D:␊
480␉␉␉␉␉p->CPU.Mobile = TRUE; // CPU_FEATURE_MOBILE;␊
481␉␉␉␉␉break;␊
482␉␉␉␉case 0x0F:␊
483␉␉␉␉␉p->CPU.Mobile = FALSE; // CPU_FEATURE_MOBILE;␊
484␉␉␉␉␉break;␊
485␉␉␉␉case 0x02:␊
486␉␉␉␉case 0x03:␊
487␉␉␉␉case 0x04:␊
488␉␉␉␉case 0x06:␉␊
489␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_P4_EBC_FREQUENCY_ID) && (1 << 21));␊
490␉␉␉␉␉break;␊
491␉␉␉␉default:␊
492␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_IA32_PLATFORM_ID) && (1<<28));␊
493␉␉␉␉␉break;␊
494␉␉␉}␊
495␉␉␉if (p->CPU.Mobile) {␊
496␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
497␉␉}␊
498␉}␊
499␉␉DBG("CPU is %s\n", p->CPU.Mobile?"Mobile":"Desktop");␊
500#endif␉␉␊
501␉}␊
502␉else if((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
503 {␊
504 switch(p->CPU.ExtFamily)␊
505 {␊
506 case 0x00: /* K8 */␊
507 msr = rdmsr64(K8_FIDVID_STATUS);␊
508 maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
509 currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
510 break;␊
511 ␊
512 case 0x01: /* K10 */␊
513 msr = rdmsr64(K10_COFVID_STATUS);␊
514 do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
515 if(bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1) // EffFreq: effective frequency interface␊
516 {␊
517 //uint64_t mperf = measure_mperf_frequency();␊
518 uint64_t aperf = measure_aperf_frequency();␊
519 cpuFrequency = aperf;␊
520 }␊
521 // NOTE: tsc runs at the maccoeff (non turbo)␊
522 // *not* at the turbo frequency.␊
523 maxcoef = bitfield(msr, 54, 49) / 2 + 4;␊
524 currcoef = bitfield(msr, 5, 0) + 0x10;␊
525 currdiv = 2 << bitfield(msr, 8, 6);␊
526 ␊
527 break;␊
528 ␊
529 case 0x05: /* K14 */␊
530 msr = rdmsr64(K10_COFVID_STATUS);␊
531 currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
532 currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
533 currdiv += bitfield(msr, 3, 0);␊
534␊
535 break;␊
536 ␊
537 case 0x02: /* K11 */␊
538 // not implimented␊
539 break;␊
540 }␊
541 ␊
542 if (maxcoef)␊
543 {␊
544 if (currdiv)␊
545 {␊
546 if(!currcoef) currcoef = maxcoef;␊
547 if(!cpuFrequency)␊
548 fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
549 else ␊
550 fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
551␊
552 DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
553 } else {␊
554 if(!cpuFrequency)␊
555 fsbFrequency = (tscFrequency / maxcoef);␊
556 else ␊
557 fsbFrequency = (cpuFrequency / maxcoef);␊
558 DBG("%d\n", currcoef);␊
559 }␊
560 }␊
561 else if (currcoef)␊
562 {␊
563 if (currdiv)␊
564 {␊
565 fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
566 DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
567 } else {␊
568 fsbFrequency = (tscFrequency / currcoef);␊
569 DBG("%d\n", currcoef);␊
570 }␊
571 }␊
572 if(!cpuFrequency) cpuFrequency = tscFrequency;␊
573 }␊
574 ␊
575␉p->CPU.MaxCoef = maxcoef;␊
576␉p->CPU.MaxDiv = maxdiv;␊
577␉p->CPU.CurrCoef = currcoef;␊
578␉p->CPU.CurrDiv = currdiv;␊
579␉p->CPU.TSCFrequency = tscFrequency;␊
580␉p->CPU.FSBFrequency = fsbFrequency;␊
581␉p->CPU.CPUFrequency = cpuFrequency;␊
582␉DBG("CPU: Brand: %s\n", p->CPU.BrandString);␊
583␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊
584␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊
585␉DBG("CPU: MaxCoef/CurrCoef/Turbo: 0x%x/0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef, p->CPU.MaxCoef+1);␊
586␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊
587␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
588␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
589␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
590␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
591␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
592#if DEBUG_CPU␊
593␉getchar();␊
594#endif␊
595}␊
596

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