Chameleon

Chameleon Svn Source Tree

Root/branches/JrCs/i386/include/IOKit/pci/IOPCIDevice.h

1/*
2 * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22
23
24#ifndef _IOKIT_IOPCIDEVICE_H
25#define _IOKIT_IOPCIDEVICE_H
26
27#include <IOKit/IOService.h>
28
29/* Definitions of PCI Config Registers */
30enum {
31 kIOPCIConfigVendorID = 0x00,
32 kIOPCIConfigDeviceID = 0x02,
33 kIOPCIConfigCommand = 0x04,
34 kIOPCIConfigStatus = 0x06,
35 kIOPCIConfigRevisionID = 0x08,
36 kIOPCIConfigClassCode = 0x09,
37 kIOPCIConfigCacheLineSize = 0x0C,
38 kIOPCIConfigLatencyTimer = 0x0D,
39 kIOPCIConfigHeaderType = 0x0E,
40 kIOPCIConfigBIST = 0x0F,
41 kIOPCIConfigBaseAddress0 = 0x10,
42 kIOPCIConfigBaseAddress1 = 0x14,
43 kIOPCIConfigBaseAddress2 = 0x18,
44 kIOPCIConfigBaseAddress3 = 0x1C,
45 kIOPCIConfigBaseAddress4 = 0x20,
46 kIOPCIConfigBaseAddress5 = 0x24,
47 kIOPCIConfigCardBusCISPtr = 0x28,
48 kIOPCIConfigSubSystemVendorID = 0x2C,
49 kIOPCIConfigSubSystemID = 0x2E,
50 kIOPCIConfigExpansionROMBase = 0x30,
51 kIOPCIConfigCapabilitiesPtr = 0x34,
52 kIOPCIConfigInterruptLine = 0x3C,
53 kIOPCIConfigInterruptPin = 0x3D,
54 kIOPCIConfigMinimumGrant = 0x3E,
55 kIOPCIConfigMaximumLatency = 0x3F
56};
57
58/* Definitions of Capabilities PCI Config Register */
59enum {
60 kIOPCICapabilityIDOffset = 0x00,
61 kIOPCINextCapabilityOffset = 0x01,
62
63 kIOPCIPowerManagementCapability = 0x01,
64 kIOPCIAGPCapability = 0x02,
65 kIOPCIVitalProductDataCapability = 0x03,
66 kIOPCISlotIDCapability = 0x04,
67 kIOPCIMSICapability = 0x05,
68 kIOPCICPCIHotswapCapability = 0x06,
69 kIOPCIPCIXCapability = 0x07,
70 kIOPCILDTCapability = 0x08,
71 kIOPCIVendorSpecificCapability = 0x09,
72 kIOPCIDebugPortCapability = 0x0a,
73 kIOPCICPCIResourceControlCapability = 0x0b,
74 kIOPCIHotplugCapability = 0x0c,
75 kIOPCIAGP8Capability = 0x0e,
76 kIOPCISecureCapability = 0x0f,
77 kIOPCIPCIExpressCapability = 0x10,
78 kIOPCIMSIXCapability = 0x11,
79
80 kIOPCIExpressErrorReportingCapability = -1UL,
81 kIOPCIExpressVirtualChannelCapability = -2UL,
82 kIOPCIExpressDeviceSerialNumberCapability = -3UL,
83 kIOPCIExpressPowerBudgetCapability = -4UL
84};
85
86/* Space definitions */
87enum {
88 kIOPCIConfigSpace = 0,
89 kIOPCIIOSpace = 1,
90 kIOPCI32BitMemorySpace = 2,
91 kIOPCI64BitMemorySpace = 3
92};
93
94/* Command register definitions */
95enum {
96 kIOPCICommandIOSpace = 0x0001,
97 kIOPCICommandMemorySpace = 0x0002,
98 kIOPCICommandBusMaster = 0x0004,
99 kIOPCICommandSpecialCycles = 0x0008,
100 kIOPCICommandMemWrInvalidate = 0x0010,
101 kIOPCICommandPaletteSnoop = 0x0020,
102 kIOPCICommandParityError = 0x0040,
103 kIOPCICommandAddressStepping = 0x0080,
104 kIOPCICommandSERR = 0x0100,
105 kIOPCICommandFastBack2Back = 0x0200,
106 kIOPCICommandInterruptDisable = 0x0400
107};
108
109/* Status register definitions */
110enum {
111 kIOPCIStatusCapabilities = 0x0010,
112 kIOPCIStatusPCI66 = 0x0020,
113 kIOPCIStatusUDF = 0x0040,
114 kIOPCIStatusFastBack2Back = 0x0080,
115 kIOPCIStatusDevSel0 = 0x0000,
116 kIOPCIStatusDevSel1 = 0x0200,
117 kIOPCIStatusDevSel2 = 0x0400,
118 kIOPCIStatusDevSel3 = 0x0600,
119 kIOPCIStatusTargetAbortCapable = 0x0800,
120 kIOPCIStatusTargetAbortActive = 0x1000,
121 kIOPCIStatusMasterAbortActive = 0x2000,
122 kIOPCIStatusSERRActive = 0x4000,
123 kIOPCIStatusParityErrActive = 0x8000
124};
125
126// constants which are part of the PCI Bus Power Management Spec.
127enum
128{
129 // capabilities bits in the 16 bit capabilities register
130 kPCIPMCPMESupportFromD3Cold = 0x8000,
131 kPCIPMCPMESupportFromD3Hot = 0x4000,
132 kPCIPMCPMESupportFromD2 = 0x2000,
133 kPCIPMCPMESupportFromD1 = 0x1000,
134 kPCIPMCPMESupportFromD0 = 0x0800,
135 kPCIPMCD2Support = 0x0400,
136 kPCIPMCD1Support = 0x0200,
137
138 kPCIPMCD3Support = 0x0001
139};
140
141enum
142{
143 // bits in the power management control/status register
144 kPCIPMCSPMEStatus = 0x8000,
145 kPCIPMCSPMEEnable = 0x0100,
146 kPCIPMCSPowerStateMask = 0x0003,
147 kPCIPMCSPowerStateD3 = 0x0003,
148 kPCIPMCSPowerStateD2 = 0x0002,
149 kPCIPMCSPowerStateD1 = 0x0001,
150 kPCIPMCSPowerStateD0 = 0x0000,
151
152 kPCIPMCSDefaultEnableBits = (~(IOOptionBits)0)
153};
154
155union IOPCIAddressSpace {
156 UInt32 bits;
157 struct {
158#if __BIG_ENDIAN__
159 unsigned int reloc:1;
160 unsigned int prefetch:1;
161 unsigned int t:1;
162 unsigned int resv:3;
163 unsigned int space:2;
164 unsigned int busNum:8;
165 unsigned int deviceNum:5;
166 unsigned int functionNum:3;
167 unsigned int registerNum:8;
168#elif __LITTLE_ENDIAN__
169 unsigned int registerNum:8;
170 unsigned int functionNum:3;
171 unsigned int deviceNum:5;
172 unsigned int busNum:8;
173 unsigned int space:2;
174 unsigned int resv:3;
175 unsigned int t:1;
176 unsigned int prefetch:1;
177 unsigned int reloc:1;
178#endif
179 } s;
180 struct {
181#if __BIG_ENDIAN__
182 unsigned int resv:4;
183 unsigned int registerNumExtended:4;
184 unsigned int busNum:8;
185 unsigned int deviceNum:5;
186 unsigned int functionNum:3;
187 unsigned int registerNum:8;
188#elif __LITTLE_ENDIAN__
189 unsigned int registerNum:8;
190 unsigned int functionNum:3;
191 unsigned int deviceNum:5;
192 unsigned int busNum:8;
193 unsigned int registerNumExtended:4;
194 unsigned int resv:4;
195#endif
196 } es;
197};
198
199struct IOPCIPhysicalAddress {
200 IOPCIAddressSpace physHi;
201 UInt32 physMid;
202 UInt32 physLo;
203 UInt32 lengthHi;
204 UInt32 lengthLo;
205};
206
207// IOPCIDevice matching property names
208#define kIOPCIMatchKey "IOPCIMatch"
209#define kIOPCIPrimaryMatchKey "IOPCIPrimaryMatch"
210#define kIOPCISecondaryMatchKey "IOPCISecondaryMatch"
211#define kIOPCIClassMatchKey "IOPCIClassMatch"
212
213// property to control PCI default config space save on sleep
214#define kIOPMPCIConfigSpaceVolatileKey "IOPMPCIConfigSpaceVolatile"
215
216// pci express link status
217#define kIOPCIExpressLinkStatusKey "IOPCIExpressLinkStatus"
218// pci express link capabilities
219#define kIOPCIExpressLinkCapabilitiesKey "IOPCIExpressLinkCapabilities"
220
221#ifndef kIOPlatformDeviceASPMEnableKey
222#define kIOPlatformDeviceASPMEnableKey "IOPlatformDeviceASPMEnable"
223#endif
224
225#ifndef kIOPCIDeviceASPMSupportedKey
226#define kIOPCIDeviceASPMSupportedKey "pci-aspm-supported"
227#endif
228
229#define kIOPCIPMEOptionsKey "IOPCIPMEOptions"
230
231
232enum {
233 kIOPCIDevicePowerStateCount = 3,
234 kIOPCIDeviceOffState = 0,
235 kIOPCIDeviceDozeState = 1,
236 kIOPCIDeviceOnState = 2,
237};
238
239enum
240{
241 // bits getInterruptType result
242 kIOInterruptTypePCIMessaged = 0x00010000
243};
244
245class IOPCIBridge;
246class IOPCI2PCIBridge;
247class IOPCIMessagedInterruptController;
248
249/*! @class IOPCIDevice : public IOService
250 @abstract An IOService class representing a PCI device.
251 @discussion The discovery of a PCI device by the PCI bus family results in an instance of the IOPCIDevice being created and published. It provides services for looking up and mapping memory mapped hardware, and access to the PCI configuration and I/O spaces.
252
253<br><br>Matching Supported by IOPCIDevice<br><br>
254
255Two types of matching are available, OpenFirmware name matching and PCI register matching. Currently, only one of these two matching schemes can be used in the same property table.
256
257<br><br>OpenFirmware Name Matching<br><br>
258
259IOService performs matching based on the IONameMatch property (see IOService). IOPCIDevices created with OpenFirmware device tree entries will name match based on the standard OpenFirmware name matching properties.
260
261<br><br>PCI Register Matching<br><br>
262
263A PCI device driver can also match on the values of certain config space registers.
264
265In each case, several matching values can be specified, and an optional mask for the value of the config space register may follow the value, preceded by an '&' character.
266<br>
267<br>
268 kIOPCIMatchKey, "IOPCIMatch"
269<br>
270The kIOPCIMatchKey property matches the vendor and device ID (0x00) register, or the subsystem register (0x2c).
271<br>
272<br>
273 kIOPCIPrimaryMatchKey, "IOPCIPrimaryMatch"
274<br>
275The kIOPCIPrimaryMatchKey property matches the vendor and device ID (0x00) register.
276<br>
277<br>
278 kIOPCISecondaryMatchKey, "IOPCISecondaryMatch"
279<br>
280The kIOPCISecondaryMatchKey property matches the subsystem register (0x2c).
281<br>
282<br>
283 kIOPCIClassMatchKey, "IOPCIClassMatch"
284<br>
285The kIOPCIClassMatchKey property matches the class code register (0x08). The default mask for this register is 0xffffff00.
286<br>
287<br>
288Examples:
289<br>
290<br>
291 &ltkey&gtIOPCIMatch&lt/key&gt <br>
292 &ltstring&gt0x00261011&lt/string&gt
293<br>
294Matches a device whose vendor ID is 0x1011, and device ID is 0x0026, including subsystem IDs.
295<br>
296<br>
297 &ltkey&gtIOPCIMatch&lt/key&gt <br>
298 &ltstring&gt0x00789004&0x00ffffff 0x78009004&0x0xff00ffff&lt/string&gt
299<br>
300Matches with any device with a vendor ID of 0x9004, and a device ID of 0xzz78 or 0x78zz, where 'z' is don't care.
301<br>
302<br>
303 &ltkey&gtIOPCIClassMatch&lt/key&gt <br>
304 &ltstring&gt0x02000000&0xffff0000&lt/string&gt
305<br>
306<br>
307Matches a device whose class code is 0x0200zz, an ethernet device.
308
309*/
310
311class IOPCIDevice : public IOService
312{
313 OSDeclareDefaultStructors(IOPCIDevice)
314
315 friend class IOPCIBridge;
316 friend class IOPCI2PCIBridge;
317 friend class IOPCIMessagedInterruptController;
318
319protected:
320 IOPCIBridge * parent;
321 IOMemoryMap * ioMap;
322 OSObject * slotNameProperty;
323
324/*! @var reserved
325 Reserved for future use. (Internal use only) */
326 struct IOPCIDeviceExpansionData * reserved;
327
328public:
329 IOPCIAddressSpace space;
330 UInt32 * savedConfig;
331
332public:
333 /* IOService/IORegistryEntry methods */
334
335 virtual bool init( OSDictionary * propTable );
336 virtual bool init( IORegistryEntry * from,
337 const IORegistryPlane * inPlane );
338 virtual void free();
339 virtual bool attach( IOService * provider );
340 virtual void detach( IOService * provider );
341
342 virtual IOReturn newUserClient( task_t owningTask, void * securityID,
343 UInt32 type, OSDictionary * properties,
344 IOUserClient ** handler );
345
346 virtual IOReturn powerStateWillChangeTo (IOPMPowerFlags capabilities,
347 unsigned long stateNumber,
348 IOService* whatDevice);
349 virtual IOReturn setPowerState( unsigned long, IOService * );
350
351 virtual bool compareName( OSString * name, OSString ** matched = 0 ) const;
352 virtual bool matchPropertyTable( OSDictionary * table,
353 SInt32 * score );
354 virtual IOService * matchLocation( IOService * client );
355 virtual IOReturn getResources( void );
356 virtual IOReturn setProperties(OSObject * properties);
357 virtual IOReturn callPlatformFunction(const OSSymbol * functionName,
358 bool waitForFunction,
359 void * p1, void * p2,
360 void * p3, void * p4);
361 virtual IOReturn callPlatformFunction(const char * functionName,
362 bool waitForFunction,
363 void * p1, void * p2,
364 void * p3, void * p4);
365
366 /* Config space accessors */
367
368 virtual UInt32 configRead32( IOPCIAddressSpace space, UInt8 offset );
369 virtual void configWrite32( IOPCIAddressSpace space,
370 UInt8 offset, UInt32 data );
371 virtual UInt16 configRead16( IOPCIAddressSpace space, UInt8 offset );
372 virtual void configWrite16( IOPCIAddressSpace space,
373 UInt8 offset, UInt16 data );
374 virtual UInt8 configRead8( IOPCIAddressSpace space, UInt8 offset );
375 virtual void configWrite8( IOPCIAddressSpace space,
376 UInt8 offset, UInt8 data );
377
378/*! @function configRead32
379 @abstract Reads a 32-bit value from the PCI device's configuration space.
380 @discussion This method reads a 32-bit configuration space register on the device and returns its value.
381 @param offset An 8-bit offset into configuration space, of which bits 0-1 are ignored.
382 @result An 32-bit value in host byte order (big endian on PPC). */
383
384 virtual UInt32 configRead32( UInt8 offset );
385
386/*! @function configRead16
387 @abstract Reads a 16-bit value from the PCI device's configuration space.
388 @discussion This method reads a 16-bit configuration space register on the device and returns its value.
389 @param offset An 8-bit offset into configuration space, of which bit 0 is ignored.
390 @result An 16-bit value in host byte order (big endian on PPC). */
391
392 virtual UInt16 configRead16( UInt8 offset );
393
394/*! @function configRead8
395 @abstract Reads a 8-bit value from the PCI device's configuration space.
396 @discussion This method reads a 8-bit configuration space register on the device and returns its value.
397 @param offset An 8-bit offset into configuration space.
398 @result An 8-bit value. */
399
400 virtual UInt8 configRead8( UInt8 offset );
401
402/*! @function configWrite32
403 @abstract Writes a 32-bit value to the PCI device's configuration space.
404 @discussion This method write a 32-bit value to a configuration space register on the device.
405 @param offset An 8-bit offset into configuration space, of which bits 0-1 are ignored.
406 @param data An 32-bit value to be written in host byte order (big endian on PPC). */
407
408 virtual void configWrite32( UInt8 offset, UInt32 data );
409
410/*! @function configWrite16
411 @abstract Writes a 16-bit value to the PCI device's configuration space.
412 @discussion This method write a 16-bit value to a configuration space register on the device.
413 @param offset An 8-bit offset into configuration space, of which bit 0 is ignored.
414 @param data An 16-bit value to be written in host byte order (big endian on PPC). */
415
416 virtual void configWrite16( UInt8 offset, UInt16 data );
417
418/*! @function configWrite8
419 @abstract Writes a 8-bit value to the PCI device's configuration space.
420 @discussion This method write a 8-bit value to a configuration space register on the device.
421 @param offset An 8-bit offset into configuration space.
422 @param data An 8-bit value to be written. */
423
424 virtual void configWrite8( UInt8 offset, UInt8 data );
425
426 virtual IOReturn saveDeviceState( IOOptionBits options = 0 );
427 virtual IOReturn restoreDeviceState( IOOptionBits options = 0 );
428
429/*! @function setConfigBits
430 @abstract Sets masked bits in a configuration space register.
431 @discussion This method sets masked bits in a configuration space register on the device by reading and writing the register. The value of the masked bits before the write is returned.
432 @param offset An 8-bit offset into configuration space, of which bits 0-1 are ignored.
433 @param mask An 32-bit mask indicating which bits in the value parameter are valid.
434 @param data An 32-bit value to be written in host byte order (big endian on PPC).
435 @result The value of the register masked with the mask before the write. */
436
437 virtual UInt32 setConfigBits( UInt8 offset, UInt32 mask, UInt32 value );
438
439/*! @function setMemoryEnable
440 @abstract Sets the device's memory space response.
441 @discussion This method sets the memory space response bit in the device's command config space register to the passed value, and returns the previous state of the enable.
442 @param enable True or false to enable or disable the memory space response.
443 @result True if the memory space response was previously enabled, false otherwise. */
444
445 virtual bool setMemoryEnable( bool enable );
446
447/*! @function setIOEnable
448 @abstract Sets the device's I/O space response.
449 @discussion This method sets the I/O space response bit in the device's command config space register to the passed value, and returns the previous state of the enable. The exclusive option allows only one exclusive device on the bus to be enabled concurrently, this should be only for temporary access.
450 @param enable True or false to enable or disable the I/O space response.
451 @param exclusive If true, only one setIOEnable with the exclusive flag set will be allowed at a time on the bus, this should be only for temporary access.
452 @result True if the I/O space response was previously enabled, false otherwise. */
453
454 virtual bool setIOEnable( bool enable, bool exclusive = false );
455
456/*! @function setBusMasterEnable
457 @abstract Sets the device's bus master enable.
458 @discussion This method sets the bus master enable bit in the device's command config space register to the passed value, and returns the previous state of the enable.
459 @param enable True or false to enable or disable bus mastering.
460 @result True if bus mastering was previously enabled, false otherwise. */
461
462 virtual bool setBusMasterEnable( bool enable );
463
464/*! @function findPCICapability
465 @abstract Search configuration space for a PCI capability register.
466 @discussion This method searches the device's config space for a PCI capability register matching the passed capability ID, if the device supports PCI capabilities. To search for PCI Express extended capabilities or for multiple capablities with the same ID, use the extendedFindPCICapability() method.
467 @param capabilityID An 8-bit PCI capability ID.
468 @param offset An optional pointer to return the offset into config space where the capability was found.
469 @result The 32-bit value of the capability register if one was found, zero otherwise. */
470
471 virtual UInt32 findPCICapability( UInt8 capabilityID, UInt8 * offset = 0 );
472
473/*! @function getBusNumber
474 @abstract Accessor to return the PCI device's assigned bus number.
475 @discussion This method is an accessor to return the PCI device's assigned bus number.
476 @result The 8-bit value of device's PCI bus number. */
477
478 virtual UInt8 getBusNumber( void );
479
480/*! @function getDeviceNumber
481 @abstract Accessor to return the PCI device's device number.
482 @discussion This method is an accessor to return the PCI device's device number.
483 @result The 5-bit value of device's device number. */
484
485 virtual UInt8 getDeviceNumber( void );
486
487/*! @function getFunctionNumber
488 @abstract Accessor to return the PCI device's function number.
489 @discussion This method is an accessor to return the PCI device's function number.
490 @result The 3-bit value of device's function number. */
491
492 virtual UInt8 getFunctionNumber( void );
493
494 /* Device memory accessors */
495
496/*! @function getDeviceMemoryWithRegister
497 @abstract Returns an instance of IODeviceMemory representing one of the device's memory mapped ranges.
498 @discussion This method will return a pointer to an instance of IODeviceMemory for the physical memory range that was assigned to the configuration space base address register passed in. It is analogous to IOService::getDeviceMemoryWithIndex.
499 @param reg The 8-bit configuration space register that is the base address register for the desired range.
500 @result A pointer to an instance of IODeviceMemory, or zero no such range was found. The IODeviceMemory is retained by the provider, so is valid while attached, or while any mappings to it exist. It should not be released by the caller. */
501
502 virtual IODeviceMemory * getDeviceMemoryWithRegister( UInt8 reg );
503
504/*! @function mapDeviceMemoryWithRegister
505 @abstract Maps a physical range of the device.
506 @discussion This method will create a mapping for the IODeviceMemory for the physical memory range that was assigned to the configuration space base address register passed in, with IODeviceMemory::map(options). The mapping is represented by the returned instance of IOMemoryMap, which should not be released until the mapping is no longer required. This method is analogous to IOService::mapDeviceMemoryWithIndex.
507 @param reg The 8-bit configuration space register that is the base address register for the desired range.
508 @param options Options to be passed to the IOMemoryDescriptor::map() method.
509 @result An instance of IOMemoryMap, or zero if the index is beyond the count available. The mapping should be released only when access to it is no longer required. */
510
511 virtual IOMemoryMap * mapDeviceMemoryWithRegister( UInt8 reg,
512 IOOptionBits options = 0 );
513
514/*! @function ioDeviceMemory
515 @abstract Accessor to the I/O space aperture for the bus.
516 @discussion This method will return a reference to the IODeviceMemory for the I/O aperture of the bus the device is on.
517 @result A pointer to an IODeviceMemory object for the I/O aperture. The IODeviceMemory is retained by the provider, so is valid while attached, or while any mappings to it exist. It should not be released by the caller. */
518
519 virtual IODeviceMemory * ioDeviceMemory( void );
520
521 /* I/O space accessors */
522
523/*! @function ioWrite32
524 @abstract Writes a 32-bit value to an I/O space aperture.
525 @discussion This method will write a 32-bit value to a 4 byte aligned offset in an I/O space aperture. If a map object is passed in, the value is written relative to it, otherwise to the value is written relative to the I/O space aperture for the bus. This function encapsulates the differences between architectures in generating I/O space operations. An eieio instruction is included on PPC.
526 @param offset An offset into a bus or device's I/O space aperture.
527 @param value The value to be written in host byte order (big endian on PPC).
528 @param map If the offset is relative to the beginning of a device's aperture, an IOMemoryMap object for that object should be passed in. Otherwise, passing zero will write the value relative to the beginning of the bus' I/O space. */
529
530 virtual void ioWrite32( UInt16 offset, UInt32 value,
531 IOMemoryMap * map = 0 );
532
533/*! @function ioWrite16
534 @abstract Writes a 16-bit value to an I/O space aperture.
535 @discussion This method will write a 16-bit value to a 2 byte aligned offset in an I/O space aperture. If a map object is passed in, the value is written relative to it, otherwise to the value is written relative to the I/O space aperture for the bus. This function encapsulates the differences between architectures in generating I/O space operations. An eieio instruction is included on PPC.
536 @param offset An offset into a bus or device's I/O space aperture.
537 @param value The value to be written in host byte order (big endian on PPC).
538 @param map If the offset is relative to the beginning of a device's aperture, an IOMemoryMap object for that object should be passed in. Otherwise, passing zero will write the value relative to the beginning of the bus' I/O space. */
539
540 virtual void ioWrite16( UInt16 offset, UInt16 value,
541 IOMemoryMap * map = 0 );
542
543/*! @function ioWrite8
544 @abstract Writes a 8-bit value to an I/O space aperture.
545 @discussion This method will write a 8-bit value to an offset in an I/O space aperture. If a map object is passed in, the value is written relative to it, otherwise to the value is written relative to the I/O space aperture for the bus. This function encapsulates the differences between architectures in generating I/O space operations. An eieio instruction is included on PPC.
546 @param offset An offset into a bus or device's I/O space aperture.
547 @param value The value to be written in host byte order (big endian on PPC).
548 @param map If the offset is relative to the beginning of a device's aperture, an IOMemoryMap object for that object should be passed in. Otherwise, passing zero will write the value relative to the beginning of the bus' I/O space. */
549
550 virtual void ioWrite8( UInt16 offset, UInt8 value,
551 IOMemoryMap * map = 0 );
552
553/*! @function ioRead32
554 @abstract Reads a 32-bit value from an I/O space aperture.
555 @discussion This method will read a 32-bit value from a 4 byte aligned offset in an I/O space aperture. If a map object is passed in, the value is read relative to it, otherwise to the value is read relative to the I/O space aperture for the bus. This function encapsulates the differences between architectures in generating I/O space operations. An eieio instruction is included on PPC.
556 @param offset An offset into a bus or device's I/O space aperture.
557 @param map If the offset is relative to the beginning of a device's aperture, an IOMemoryMap object for that object should be passed in. Otherwise, passing zero will write the value relative to the beginning of the bus' I/O space.
558 @result The value read in host byte order (big endian on PPC). */
559
560 virtual UInt32 ioRead32( UInt16 offset, IOMemoryMap * map = 0 );
561
562/*! @function ioRead16
563 @abstract Reads a 16-bit value from an I/O space aperture.
564 @discussion This method will read a 16-bit value from a 2 byte aligned offset in an I/O space aperture. If a map object is passed in, the value is read relative to it, otherwise to the value is read relative to the I/O space aperture for the bus. This function encapsulates the differences between architectures in generating I/O space operations. An eieio instruction is included on PPC.
565 @param offset An offset into a bus or device's I/O space aperture.
566 @param map If the offset is relative to the beginning of a device's aperture, an IOMemoryMap object for that object should be passed in. Otherwise, passing zero will write the value relative to the beginning of the bus' I/O space.
567 @result The value read in host byte order (big endian on PPC). */
568
569 virtual UInt16 ioRead16( UInt16 offset, IOMemoryMap * map = 0 );
570
571/*! @function ioRead8
572 @abstract Reads a 8-bit value from an I/O space aperture.
573 @discussion This method will read a 8-bit value from an offset in an I/O space aperture. If a map object is passed in, the value is read relative to it, otherwise to the value is read relative to the I/O space aperture for the bus. This function encapsulates the differences between architectures in generating I/O space operations. An eieio instruction is included on PPC.
574 @param offset An offset into a bus or device's I/O space aperture.
575 @param map If the offset is relative to the beginning of a device's aperture, an IOMemoryMap object for that object should be passed in. Otherwise, passing zero will write the value relative to the beginning of the bus' I/O space.
576 @result The value read. */
577
578 virtual UInt8 ioRead8( UInt16 offset, IOMemoryMap * map = 0 );
579
580 OSMetaClassDeclareReservedUsed(IOPCIDevice, 0);
581/*! @function hasPCIPowerManagement
582 @abstract determine whether or not the device supports PCI Bus Power Management.
583 @discussion This method will look at the device's capabilties registers and determine whether or not the device supports the PCI BUS Power Management Specification.
584 @param state(optional) Check for support of a specific state (e.g. kPCIPMCPMESupportFromD3Cold). If state is not suuplied or is 0, then check for a property in the registry which tells which state the hardware expects the device to go to during sleep.
585 @result true if the specified state is supported */
586 virtual bool hasPCIPowerManagement(IOOptionBits state = 0);
587
588 OSMetaClassDeclareReservedUsed(IOPCIDevice, 1);
589/*! @function enablePCIPowerManagement
590 @abstract enable PCI power management for sleep state
591 @discussion This method will enable PCI Bus Powermanagement when going to sleep mode.
592 @param state(optional) Enables PCI Power Management by placing the function in the given state (e.g. kPCIPMCSPowerStateD3). If state is not specified or is 0xffffffff, then the IOPCIDevice determines the desired state. If state is kPCIPMCSPowerStateD0 (0) then PCI Power Management is disabled.
593 @result kIOReturnSuccess if there were no errors */
594 virtual IOReturn enablePCIPowerManagement(IOOptionBits state = 0xffffffff);
595
596 OSMetaClassDeclareReservedUsed(IOPCIDevice, 2);
597/*! @function extendedFindPCICapability
598 @abstract Search configuration space for a PCI capability register.
599 @discussion This method searches the device's config space for a PCI capability register matching the passed capability ID, if the device supports PCI capabilities.
600 @param capabilityID A PCI capability ID. PCI Express devices may support extended capabilities in config space starting at offset 0x100. To search this space, the ID passed should be the negated value of the PCI-SIG assigned ID for the extended capability.
601 @param offset An optional in/out parameter to return the offset into config space where the capability was found, and to set the start point of the next search. Initialize the offset to zero before the first call to extendedFindPCICapability() and subsequent calls will find all capabilty blocks that may exist on the device with the same ID.
602 @result The 32-bit value of the capability register if one was found, zero otherwise. */
603
604 virtual UInt32 extendedFindPCICapability( UInt32 capabilityID, IOByteCount * offset = 0 );
605
606 // Unused Padding
607 OSMetaClassDeclareReservedUnused(IOPCIDevice, 3);
608 OSMetaClassDeclareReservedUnused(IOPCIDevice, 4);
609 OSMetaClassDeclareReservedUnused(IOPCIDevice, 5);
610 OSMetaClassDeclareReservedUnused(IOPCIDevice, 6);
611 OSMetaClassDeclareReservedUnused(IOPCIDevice, 7);
612 OSMetaClassDeclareReservedUnused(IOPCIDevice, 8);
613 OSMetaClassDeclareReservedUnused(IOPCIDevice, 9);
614 OSMetaClassDeclareReservedUnused(IOPCIDevice, 10);
615 OSMetaClassDeclareReservedUnused(IOPCIDevice, 11);
616 OSMetaClassDeclareReservedUnused(IOPCIDevice, 12);
617 OSMetaClassDeclareReservedUnused(IOPCIDevice, 13);
618 OSMetaClassDeclareReservedUnused(IOPCIDevice, 14);
619 OSMetaClassDeclareReservedUnused(IOPCIDevice, 15);
620
621public:
622
623/*! @function extendedConfigRead32
624 @abstract Reads a 32-bit value from the PCI device's configuration space.
625 @discussion This method reads a 32-bit configuration space register on the device and returns its value.
626 @param offset A byte offset into configuration space, of which bits 0-1 are ignored.
627 @result An 32-bit value in host byte order (big endian on PPC). */
628
629 UInt32 extendedConfigRead32( IOByteCount offset );
630
631/*! @function extendedConfigRead16
632 @abstract Reads a 16-bit value from the PCI device's configuration space.
633 @discussion This method reads a 16-bit configuration space register on the device and returns its value.
634 @param offset A byte offset into configuration space, of which bit 0 is ignored.
635 @result An 16-bit value in host byte order (big endian on PPC). */
636
637 UInt16 extendedConfigRead16( IOByteCount offset );
638
639/*! @function extendedConfigRead8
640 @abstract Reads a 8-bit value from the PCI device's configuration space.
641 @discussion This method reads a 8-bit configuration space register on the device and returns its value.
642 @param offset A byte offset into configuration space.
643 @result An 8-bit value. */
644
645 UInt8 extendedConfigRead8( IOByteCount offset );
646
647/*! @function extendedConfigWrite32
648 @abstract Writes a 32-bit value to the PCI device's configuration space.
649 @discussion This method writes a 32-bit value to a configuration space register on the device.
650 @param offset A byte offset into configuration space, of which bits 0-1 are ignored.
651 @param data An 32-bit value to be written in host byte order (big endian on PPC). */
652
653 void extendedConfigWrite32( IOByteCount offset, UInt32 data );
654
655/*! @function extendedConfigWrite16
656 @abstract Writes a 16-bit value to the PCI device's configuration space.
657 @discussion This method writes a 16-bit value to a configuration space register on the device.
658 @param offset A byte offset into configuration space, of which bit 0 is ignored.
659 @param data An 16-bit value to be written in host byte order (big endian on PPC). */
660
661 void extendedConfigWrite16( IOByteCount offset, UInt16 data );
662
663/*! @function extendedConfigWrite8
664 @abstract Writes a 8-bit value to the PCI device's configuration space.
665 @discussion This method writes a 8-bit value to a configuration space register on the device.
666 @param offset A byte offset into configuration space.
667 @param data An 8-bit value to be written. */
668
669 void extendedConfigWrite8( IOByteCount offset, UInt8 data );
670};
671
672#endif /* ! _IOKIT_IOPCIDEVICE_H */
673
674

Archive Download this file

Revision: 1466