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1/*␊
2 * Copyright (c) 2009 Evan Lojewski. All rights reserved.␊
3 *␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "modules.h"␊
8#include "boot.h"␊
9#include "bootstruct.h"␊
10#include "pci.h"␊
11#include "hpet.h"␊
12␊
13#ifndef DEBUG_HPET␊
14#define DEBUG_HPET 0␊
15#endif␊
16␊
17#if DEBUG_HPET␊
18#define DBG(x...) printf(x)␊
19#else␊
20#define DBG(x...)␊
21#endif␊
22␊
23static void force_enable_hpet_intel(pci_dt_t *lpc_dev);␊
24static void force_enable_hpet_via(pci_dt_t *lpc_dev);␊
25static void force_enable_hpet(pci_dt_t *lpc_dev);␊
26␊
27␊
28void HPET_hook(void* arg1, void* arg2, void* arg3, void* arg4, void* arg5, void* arg6)␊
29{␊
30␉pci_dt_t* current = arg1;␊
31␉␊
32␉if(current->class_id != PCI_CLASS_BRIDGE_ISA) return;␊
33␉␊
34␉␊
35␉force_enable_hpet(current);␊
36}␊
37␊
38void HPET_start()␊
39{␊
40␉bool enable = true;␊
41␉getBoolForKey(EnableHPETModule, &enable, &bootInfo->bootConfig);␊
42␉␊
43␉if (enable)␉␊
44␉␉register_hook_callback("PCIDevice", &HPET_hook);␊
45}␊
46␊
47/*␊
48 * Force HPET enabled␊
49 *␊
50 * via fix from http://forum.voodooprojects.org/index.php/topic,1596.0.html␊
51 */␊
52␊
53static struct lpc_controller_t lpc_controllers_intel[] = {␊
54␉␊
55␉// Default unknown chipset␊
56␉{ 0, 0, "" },␊
57␉␊
58␉// Intel␊
59␉{ 0x8086, 0x24dc, "ICH5" },␊
60␉{ 0x8086, 0x2640, "ICH6" },␊
61␉{ 0x8086, 0x2641, "ICH6M" },␊
62␉␊
63␉{ 0x8086, 0x27b0, "ICH7 DH" },␊
64␉{ 0x8086, 0x27b8, "ICH7" },␊
65␉{ 0x8086, 0x27b9, "ICH7M" },␊
66␉{ 0x8086, 0x27bd, "ICH7M DH" },␊
67␊
68␉{ 0x8086, 0x27bc, "NM10" },␊
69␊
70␉{ 0x8086, 0x2810, "ICH8R" },␊
71␉{ 0x8086, 0x2811, "ICH8M-E" },␊
72␉{ 0x8086, 0x2812, "ICH8DH" },␊
73␉{ 0x8086, 0x2814, "ICH8DO" },␊
74␉{ 0x8086, 0x2815, "ICH8M" },␊
75␉␊
76␉{ 0x8086, 0x2912, "ICH9DH" },␊
77␉{ 0x8086, 0x2914, "ICH9DO" },␊
78␉{ 0x8086, 0x2916, "ICH9R" },␊
79␉{ 0x8086, 0x2917, "ICH9M-E" },␊
80␉{ 0x8086, 0x2918, "ICH9" },␊
81␉{ 0x8086, 0x2919, "ICH9M" },␊
82␉␊
83␉{ 0x8086, 0x3a14, "ICH10DO" },␊
84␉{ 0x8086, 0x3a16, "ICH10R" },␊
85␉{ 0x8086, 0x3a18, "ICH10" },␊
86␉{ 0x8086, 0x3a1a, "ICH10D" },␊
87};␊
88␊
89static struct lpc_controller_t lpc_controllers_via[] = {␊
90␉// Default unknown chipset␊
91␉{ 0, 0, "" },␊
92␉␊
93␉{ 0x1106, 0x3372, "VT8237S" },␊
94};␊
95␊
96␊
97static void force_enable_hpet(pci_dt_t *lpc_dev)␊
98{␊
99␉switch(lpc_dev->vendor_id)␊
100␉{␊
101␉␉case 0x8086:␊
102␉␉␉force_enable_hpet_intel(lpc_dev);␊
103␉␉␉break;␊
104␉␉␉␊
105␉␉case 0x1106:␊
106␉␉␉force_enable_hpet_via(lpc_dev);␊
107␉␉␉break;␊
108␉␉default:␊
109␉␉␉break;␊
110␉}␊
111␉␊
112␉␊
113#if DEBUG_HPET␊
114␉printf("Press [Enter] to continue...\n");␊
115␉getc();␊
116#endif␊
117}␊
118␊
119static void force_enable_hpet_via(pci_dt_t *lpc_dev)␊
120{␊
121␉uint32_t␉val, hpet_address = 0xFED00000;␊
122␉unsigned int i;␊
123␉␊
124␉for(i = 1; i < sizeof(lpc_controllers_via) / sizeof(lpc_controllers_via[0]); i++)␊
125␉{␊
126␉␉if (␉(lpc_controllers_via[i].vendor == lpc_dev->vendor_id) ␊
127␉␉␉&& (lpc_controllers_via[i].device == lpc_dev->device_id))␊
128␉␉{␉␊
129␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊
130␉␉␉␊
131␉␉␉DBG("VIA %s LPC Interface [%04x:%04x], MMIO\n", ␊
132␉␉␉␉lpc_controllers_via[i].name, lpc_dev->vendor_id, lpc_dev->device_id);␊
133␉␉␉␊
134␉␉␉if (val & 0x80)␊
135␉␉␉{␊
136␉␉␉␉hpet_address = (val & ~0x3ff);␊
137␉␉␉␉DBG("HPET at 0x%lx\n", hpet_address);␊
138␉␉␉}␊
139␉␉␉else ␊
140␉␉␉{␊
141␉␉␉␉val = 0xfed00000 | 0x80;␊
142␉␉␉␉pci_config_write32(lpc_dev->dev.addr, 0x68, val);␊
143␉␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊
144␉␉␉␉if (val & 0x80)␊
145␉␉␉␉{␊
146␉␉␉␉␉hpet_address = (val & ~0x3ff);␊
147␉␉␉␉␉DBG("Force enabled HPET at 0x%lx\n", hpet_address);␊
148␉␉␉␉}␊
149␉␉␉␉else␊
150␉␉␉␉{␊
151␉␉␉␉␉DBG("Unable to enable HPET");␊
152␉␉␉␉}␊
153␉␉␉}␊
154␉␉}␊
155␉}␊
156}␊
157␊
158␊
159␊
160static void force_enable_hpet_intel(pci_dt_t *lpc_dev)␊
161{␊
162␉uint32_t␉val, hpet_address = 0xFED00000;␊
163␉unsigned int i;␊
164␉void␉␉*rcba;␊
165␉␊
166␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊
167␉for(i = 1; i < sizeof(lpc_controllers_intel) / sizeof(lpc_controllers_intel[0]); i++)␊
168␉{␊
169␉␉if (␉(lpc_controllers_intel[i].vendor == lpc_dev->vendor_id) ␊
170␉␉␉&& (lpc_controllers_intel[i].device == lpc_dev->device_id))␊
171␉␉{␉␊
172␉␉␉␊
173␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊
174␉␉␉␊
175␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊
176␉␉␉␉lpc_controllers_intel[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊
177␉␉␉␊
178␉␉␉if (rcba == 0)␊
179␉␉␉␉DBG(" RCBA disabled; cannot force enable HPET\n");␊
180␉␉␉else␊
181␉␉␉{␊
182␉␉␉␉val = REG32(rcba, 0x3404);␊
183␉␉␉␉if (val & 0x80)␊
184␉␉␉␉{␊
185␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊
186␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊
187␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
188␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊
189␉␉␉␉}␊
190␉␉␉␉else␊
191␉␉␉␉{␊
192␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊
193␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊
194␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊
195␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊
196␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊
197␉␉␉␉}␊
198␉␉␉␉␊
199␉␉␉␉// verify if the job is done␊
200␉␉␉␉val = REG32(rcba, 0x3404);␊
201#if DEBUG_HPET␉␊
202␉␉␉␉if (!(val & 0x80))␊
203␉␉␉␉␉printf(" Failed to force enable HPET\n");␊
204#endif␊
205/*␊
206#define HPET_CONFIG 0x10 // General configuration register ␊
207#define HPET_CNF_LEG_RT 0x00000002␊
208#define HPET_CNF_ENABLE 0x00000001␊
209 ␊
210 val = REG32(hpet_address, HPET_CONFIG);␊
211 val &= ~HPET_CNF_LEG_RT;␊
212 val |= HPET_CNF_ENABLE;␊
213 REG32(hpet_address, HPET_CONFIG) = val;␊
214*/␊
215␉␉␉}␊
216␉␉␉break;␊
217␉␉␉␊
218␉␉}␊
219␉}␊
220}

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