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Root/branches/cparm/i386/modules/Memory/dram_controllers.c

1/*␊
2 * dram controller access and scan from the pci host controller␊
3 * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work␊
4 * original source comes from:␊
5 *␊
6 * memtest86␊
7 *␊
8 * Released under version 2 of the Gnu Public License.␊
9 * By Chris Brady, cbrady@sgi.com␊
10 * ----------------------------------------------------␊
11 * MemTest86+ V4.00 Specific code (GPL V2.0)␊
12 * By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
13 * http://www.canardpc.com - http://www.memtest.org␊
14 */␊
15␊
16#include "libsaio.h"␊
17#include "bootstruct.h"␊
18#include "pci.h"␊
19#include "platform.h"␊
20#include "dram_controllers.h"␊
21␊
22#ifndef DEBUG_DRAM␊
23#define DEBUG_DRAM 0␊
24#endif␊
25␊
26#if DEBUG_DRAM␊
27#define DBG(x...) printf(x)␊
28#else␊
29#define DBG(x...)␊
30#endif␊
31static void setup_p35(pci_dt_t *dram_dev);␊
32static void setup_nhm(pci_dt_t *dram_dev);␊
33static void get_fsb_i965(pci_dt_t *dram_dev);␊
34static void get_fsb_im965(pci_dt_t *dram_dev);␊
35static void get_fsb_nhm(pci_dt_t *dram_dev);␊
36static void get_timings_i965(pci_dt_t *dram_dev);␊
37static void get_timings_im965(pci_dt_t *dram_dev);␊
38static void get_timings_p35(pci_dt_t *dram_dev);␊
39static void get_timings_nhm(pci_dt_t *dram_dev);␊
40␊
41/*␊
42 * Initialise memory controller functions␊
43 */␊
44␊
45// Setup P35 Memory Controller␊
46static void setup_p35(pci_dt_t *dram_dev)␊
47{␊
48␉uint32_t dev0;␊
49␉␊
50␉// Activate MMR I/O␊
51␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
52␉if (!(dev0 & 0x1))␊
53␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊
54}␊
55␊
56int nhm_bus = 0x3F;␊
57␊
58␊
59// Setup Nehalem Integrated Memory Controller␊
60static void setup_nhm(pci_dt_t *dram_dev)␊
61{␊
62 static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
63␉unsigned long did, vid;␊
64␉int i;␊
65␉␊
66␉// Nehalem supports Scrubbing␊
67␉// First, locate the PCI bus where the MCH is located␊
68␉for(i = 0; (unsigned)i < sizeof(possible_nhm_bus); i++)␊
69␉{␊
70␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊
71␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊
72␉␉vid &= 0xFFFF;␊
73␉␉did &= 0xFF00;␊
74␉␉␊
75␉␉if(vid == 0x8086 && did >= 0x2C00)␊
76␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
77␉}␊
78}␊
79␊
80/*␊
81 * Retrieve memory controller fsb functions␊
82 */␊
83␊
84␊
85// Get i965 Memory Speed␊
86static void get_fsb_i965(pci_dt_t *dram_dev)␊
87{␊
88␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
89␊
90␉long *ptr;␊
91␉␊
92␉// Find Ratio␊
93␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
94␉dev0 &= 0xFFFFC000;␊
95␉ptr = (long*)(dev0 + 0xC00);␊
96␉mch_cfg = *ptr & 0xFFFF;␊
97␉␊
98␉mch_ratio = 100000;␊
99␉␊
100␉switch (mch_cfg & 7)␊
101␉{␊
102␉␉case 0: mch_fsb = 1066; break;␊
103␉␉case 1: mch_fsb = 533; break;␊
104␉ default: ␊
105␉␉case 2: mch_fsb = 800; break;␊
106␉␉case 3: mch_fsb = 667; break;␉␉␊
107␉␉case 4: mch_fsb = 1333; break;␊
108␉␉case 6: mch_fsb = 1600; break;␉␉␉␉␉␊
109␉}␊
110␉␊
111␉DBG("mch_fsb %d\n", mch_fsb);␊
112␉␊
113␉switch (mch_fsb)␊
114␉{␊
115␉␉case 533:␊
116␉␉␉switch ((mch_cfg >> 4) & 7)␊
117␉␉{␊
118␉␉␉case 1:␉mch_ratio = 200000; break;␊
119␉␉␉case 2:␉mch_ratio = 250000; break;␊
120␉␉␉case 3:␉mch_ratio = 300000; break;␊
121␉␉}␊
122␉␉␉break;␊
123␉␉␉␊
124␉␉default:␊
125␉␉case 800:␊
126␉␉␉switch ((mch_cfg >> 4) & 7)␊
127␉␉{␊
128␉␉␉case 0:␉mch_ratio = 100000; break;␊
129␉␉␉case 1:␉mch_ratio = 125000; break;␊
130␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊
131␉␉␉case 3:␉mch_ratio = 200000; break;␊
132␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊
133␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊
134␉␉}␊
135␉␉␉break;␊
136␉␉␉␊
137␉␉case 1066:␊
138␉␉␉switch ((mch_cfg >> 4) & 7)␊
139␉␉{␊
140␉␉␉case 1:␉mch_ratio = 100000; break;␊
141␉␉␉case 2:␉mch_ratio = 125000; break;␊
142␉␉␉case 3:␉mch_ratio = 150000; break;␊
143␉␉␉case 4:␉mch_ratio = 200000; break;␊
144␉␉␉case 5:␉mch_ratio = 250000; break;␊
145␉␉}␊
146␉␉␉break;␊
147␉␉␉␊
148␉␉case 1333:␊
149␉␉␉switch ((mch_cfg >> 4) & 7)␊
150␉␉{␊
151␉␉␉case 2:␉mch_ratio = 100000; break;␊
152␉␉␉case 3:␉mch_ratio = 120000; break;␊
153␉␉␉case 4:␉mch_ratio = 160000; break;␊
154␉␉␉case 5:␉mch_ratio = 200000; break;␊
155␉␉}␊
156␉␉␉break;␊
157␉␉␉␊
158␉␉case 1600:␊
159␉␉␉switch ((mch_cfg >> 4) & 7)␊
160␉␉{␊
161␉␉␉case 3:␉mch_ratio = 100000; break;␊
162␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊
163␉␉␉case 5:␉mch_ratio = 150000; break;␊
164␉␉␉case 6:␉mch_ratio = 200000; break;␊
165␉␉}␊
166␉␉␉break;␊
167␉}␊
168␉␊
169␉DBG("mch_ratio %d\n", mch_ratio);␊
170␊
171␉// Compute RAM Frequency␊
172␉Platform->RAM.Frequency = (Platform->CPU.FSBFrequency * mch_ratio) / 100000;␊
173␉␊
174␉DBG("ram_fsb %d\n", Platform->RAM.Frequency);␊
175␊
176}␊
177␊
178// Get i965m Memory Speed␊
179static void get_fsb_im965(pci_dt_t *dram_dev)␊
180{␊
181␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
182␊
183␉long *ptr;␊
184␉␊
185␉// Find Ratio␊
186␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
187␉dev0 &= 0xFFFFC000;␊
188␉ptr = (long*)(dev0 + 0xC00);␊
189␉mch_cfg = *ptr & 0xFFFF;␊
190␉␊
191␉mch_ratio = 100000;␊
192␉␊
193␉switch (mch_cfg & 7)␊
194␉{␊
195␉␉case 1: mch_fsb = 533; break;␊
196␉␉default: ␊
197␉␉case 2:␉mch_fsb = 800; break;␊
198␉␉case 3:␉mch_fsb = 667; break;␉␉␉␉␊
199␉␉case 6:␉mch_fsb = 1066; break;␉␉␉␊
200␉}␊
201␉␊
202␉switch (mch_fsb)␊
203␉{␊
204␉␉case 533:␊
205␉␉␉switch ((mch_cfg >> 4) & 7)␊
206␉␉␉{␊
207␉␉␉␉case 1:␉mch_ratio = 125000; break;␊
208␉␉␉␉case 2:␉mch_ratio = 150000; break;␊
209␉␉␉␉case 3:␉mch_ratio = 200000; break;␊
210␉␉␉}␊
211␉␉␉break;␊
212␉␉␉␊
213␉␉case 667:␊
214␉␉␉switch ((mch_cfg >> 4)& 7)␊
215␉␉␉{␊
216␉␉␉␉case 1:␉mch_ratio = 100000; break;␊
217␉␉␉␉case 2:␉mch_ratio = 120000; break;␊
218␉␉␉␉case 3:␉mch_ratio = 160000; break;␊
219␉␉␉␉case 4:␉mch_ratio = 200000; break;␊
220␉␉␉␉case 5:␉mch_ratio = 240000; break;␊
221␉␉␉}␊
222␉␉␉break;␊
223␉␉␉␊
224␉␉default:␊
225␉␉case 800:␊
226␉␉␉switch ((mch_cfg >> 4) & 7)␊
227␉␉␉{␊
228␉␉␉␉case 1:␉mch_ratio = 83333; break; // 0.833333333␊
229␉␉␉␉case 2:␉mch_ratio = 100000; break;␊
230␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊
231␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊
232␉␉␉␉case 5:␉mch_ratio = 200000; break;␊
233␉␉␉}␊
234␉␉␉break;␊
235␉␉case 1066:␊
236␉␉␉switch ((mch_cfg >> 4)&7) {␊
237␉␉␉␉case 5:␉mch_ratio = 150000; break;␊
238␉␉␉␉case 6:␉mch_ratio = 200000; break;␊
239␉␉␉}␊
240␉␉␉␊
241␉}␊
242␉␊
243␉// Compute RAM Frequency␊
244␉Platform->RAM.Frequency = (Platform->CPU.FSBFrequency * mch_ratio) / 100000;␊
245}␊
246␊
247␊
248// Get iCore7 Memory Speed␊
249static void get_fsb_nhm(pci_dt_t *dram_dev)␊
250{␊
251␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊
252␉␊
253␉// Get the clock ratio␊
254␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊
255␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊
256␉␊
257␉// Compute RAM Frequency␊
258␉Platform->RAM.Frequency = Platform->CPU.FSBFrequency * mch_ratio / 2;␊
259}␊
260 ␊
261/*␊
262 * Retrieve memory controller info functions␊
263 */␊
264␊
265// Get i965 Memory Timings␊
266static void get_timings_i965(pci_dt_t *dram_dev)␊
267{ ␊
268␉// Thanks for CDH optis␊
269␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊
270␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
271␊
272␉long *ptr;␊
273␉␊
274␉// Read MMR Base Address␊
275␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
276␉dev0 &= 0xFFFFC000;␊
277␉␊
278␉ptr = (long*)(dev0 + 0x260);␊
279␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
280␉␊
281␉ptr = (long*)(dev0 + 0x660);␊
282␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
283␉␊
284␉// If DIMM 0 not populated, check DIMM 1␊
285␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
286␉␊
287␉ptr = (long*)(dev0 + offset + 0x29C);␊
288␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
289␉␊
290␉ptr = (long*)(dev0 + offset + 0x250);␉␊
291␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
292␉␊
293␉ptr = (long*)(dev0 + offset + 0x252);␊
294␉ACT_Register = *ptr & 0xFFFFFFFF;␊
295␉␊
296␉ptr = (long*)(dev0 + offset + 0x258);␊
297␉Read_Register = *ptr & 0xFFFFFFFF;␊
298␉␊
299␉ptr = (long*)(dev0 + offset + 0x244);␊
300␉Misc_Register = *ptr & 0xFFFFFFFF;␊
301␉␊
302␉// 965 Series only support DDR2␊
303␉Platform->RAM.Type = SMB_MEM_TYPE_DDR2;␊
304␉␊
305␉// CAS Latency (tCAS)␊
306␉Platform->RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3;␊
307␉␊
308␉// RAS-To-CAS (tRCD)␊
309␉Platform->RAM.TRC = (Read_Register >> 16) & 0xF;␊
310␉␊
311␉// RAS Precharge (tRP)␊
312␉Platform->RAM.TRP = (ACT_Register >> 13) & 0xF;␊
313␉␊
314␉// RAS Active to precharge (tRAS)␊
315␉Platform->RAM.RAS = (Precharge_Register >> 11) & 0x1F;␊
316␉␊
317␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF))␊
318␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
319␉else␊
320␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
321}␊
322␊
323// Get im965 Memory Timings␊
324static void get_timings_im965(pci_dt_t *dram_dev)␊
325{␊
326␉// Thanks for CDH optis␊
327␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊
328␉long *ptr;␊
329␉␊
330␉// Read MMR Base Address␊
331␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
332␉dev0 &= 0xFFFFC000;␊
333␉␊
334␉ptr = (long*)(dev0 + 0x1200);␊
335␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
336␉␊
337␉ptr = (long*)(dev0 + 0x1300);␊
338␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
339␉␊
340␉// If DIMM 0 not populated, check DIMM 1␊
341␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊
342␉␊
343␉ptr = (long*)(dev0 + offset + 0x121C);␊
344␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
345␉␊
346␉ptr = (long*)(dev0 + offset + 0x1214);␉␊
347␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
348␉␊
349␉// Series only support DDR2␊
350␉Platform->RAM.Type = SMB_MEM_TYPE_DDR2;␊
351␉␊
352␉// CAS Latency (tCAS)␊
353␉Platform->RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3;␊
354␉␊
355␉// RAS-To-CAS (tRCD)␊
356␉Platform->RAM.TRC = ((Precharge_Register >> 5) & 7) + 2;␊
357␉␊
358␉// RAS Precharge (tRP)␊
359␉Platform->RAM.TRP= (Precharge_Register & 7) + 2;␊
360␉␊
361␉// RAS Active to precharge (tRAS)␊
362␉Platform->RAM.RAS = (Precharge_Register >> 21) & 0x1F;␊
363␉␊
364␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) ␊
365␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
366␉else␊
367␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
368}␊
369␊
370// Get P35 Memory Timings␊
371static void get_timings_p35(pci_dt_t *dram_dev)␊
372{ ␊
373␉// Thanks for CDH optis␊
374␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊
375␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
376␉long *ptr;␊
377␉␊
378␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊
379␉//Device_ID &= 0xFFFF;␊
380␉␊
381␉// Now, read MMR Base Address␊
382␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
383␉dev0 &= 0xFFFFC000;␊
384␉␊
385␉ptr = (long*)(dev0 + 0x260);␊
386␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
387␉␊
388␉ptr = (long*)(dev0 + 0x660);␊
389␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
390␉␊
391␉// If DIMM 0 not populated, check DIMM 1␊
392␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
393␉␊
394␉ptr = (long*)(dev0 + offset + 0x265);␊
395␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
396␉␊
397␉ptr = (long*)(dev0 + offset + 0x25D);␉␊
398␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
399␉␊
400␉ptr = (long*)(dev0 + offset + 0x252);␊
401␉ACT_Register = *ptr & 0xFFFFFFFF;␊
402␉␊
403␉ptr = (long*)(dev0 + offset + 0x258);␊
404␉Read_Register = *ptr & 0xFFFFFFFF;␊
405␉␊
406␉ptr = (long*)(dev0 + offset + 0x244);␊
407␉Misc_Register = *ptr & 0xFFFFFFFF;␊
408␉␊
409␉ptr = (long*)(dev0 + offset + 0x1E8);␊
410␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
411␉␊
412␉// On P45, check 1A8␊
413␉if(dram_dev->device_id > 0x2E00) {␊
414␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊
415␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
416␉␉Memory_Check >>= 2;␊
417␉␉Memory_Check &= 1;␊
418␉␉Memory_Check = !Memory_Check;␊
419␉} else {␊
420␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊
421␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␉␊
422␉}␊
423␉␊
424␉// Determine DDR-II or DDR-III␊
425␉if (Memory_Check & 1)␊
426␉␉Platform->RAM.Type = SMB_MEM_TYPE_DDR2;␊
427␉else␊
428␉␉Platform->RAM.Type = SMB_MEM_TYPE_DDR3;␊
429␉␊
430␉// CAS Latency (tCAS)␊
431␉if(dram_dev->device_id > 0x2E00)␊
432␉␉Platform->RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊
433␉else␊
434␉␉Platform->RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊
435␉␊
436␉// RAS-To-CAS (tRCD)␊
437␉Platform->RAM.TRC = (Read_Register >> 17) & 0xF;␊
438␉␊
439␉// RAS Precharge (tRP)␊
440␉Platform->RAM.TRP = (ACT_Register >> 13) & 0xF;␊
441␉␊
442␉// RAS Active to precharge (tRAS)␊
443␉Platform->RAM.RAS = Precharge_Register & 0x3F;␊
444␉␊
445␉// Channel configuration␊
446␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) ␊
447␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
448␉else␊
449␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
450}␊
451␊
452// Get Nehalem Memory Timings␊
453static void get_timings_nhm(pci_dt_t *dram_dev)␊
454{␊
455␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊
456␉int fvc_bn = 4;␊
457␉␊
458␉// Find which channels are populated␊
459␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊
460␉mc_control = (mc_control >> 8) & 0x7;␊
461␉␊
462␉// DDR-III␊
463␉Platform->RAM.Type = SMB_MEM_TYPE_DDR3;␊
464␉␊
465␉// Get the first valid channel␊
466␉if(mc_control & 1)␊
467␉␉fvc_bn = 4; ␊
468␉else if(mc_control & 2)␊
469␉␉fvc_bn = 5; ␊
470␉else if(mc_control & 7) ␊
471␉␉fvc_bn = 6; ␊
472␉␊
473␉// Now, detect timings␊
474␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊
475␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊
476␉␊
477␉// CAS Latency (tCAS)␊
478␉Platform->RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4;␊
479␉␊
480␉// RAS-To-CAS (tRCD)␊
481␉Platform->RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
482␉␊
483␉// RAS Active to precharge (tRAS)␊
484␉Platform->RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F;␊
485␉␊
486␉// RAS Precharge (tRP)␊
487␉Platform->RAM.TRP = mc_channel_bank_timing & 0xF; ␊
488␉␉␊
489␉// Single , Dual or Triple Channels␊
490␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊
491␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
492␉else if (mc_control == 7)␊
493␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_TRIPLE;␊
494␉else␊
495␉␉Platform->RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
496}␊
497␊
498static struct mem_controller_t dram_controllers[] = {␊
499␊
500␉// Default unknown chipset␊
501␉{ 0, 0, "",␉NULL, NULL, NULL },␊
502␊
503␉// Intel␊
504␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊
505␊
506␉{ 0x8086, 0x1A30, "i845",␉NULL, NULL, NULL },␊
507␉␊
508␉{ 0x8086, 0x2970, "i946PL/GZ",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
509␉{ 0x8086, 0x2990, "Q963/Q965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
510␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
511␊
512␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
513␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
514␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965, get_timings_im965 },␉␊
515␊
516␉{ 0x8086, 0x29B0, "Q35",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
517␉{ 0x8086, 0x29C0, "P35/G33",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
518␉{ 0x8086, 0x29D0, "Q33",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
519␉{ 0x8086, 0x29E0, "X38/X48",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␉␉␊
520␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
521␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
522␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
523␉{ 0x8086, 0x2E30, "G41",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
524␉␊
525␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
526␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
527␉{ 0x8086, 0x3400, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉ get_timings_nhm },␊
528␉{ 0x8086, 0x3401, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
529␉{ 0x8086, 0x3402, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
530␉{ 0x8086, 0x3403, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
531␉{ 0x8086, 0x3404, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
532␉{ 0x8086, 0x3405, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
533␉{ 0x8086, 0x3406, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
534␉{ 0x8086, 0x3407, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
535␉␊
536};␊
537␊
538static const char *memory_channel_types[] =␊
539{␊
540␉"Unknown", "Single", "Dual", "Triple"␊
541};␉␉␉␊
542␊
543void scan_dram_controller(pci_dt_t *dram_dev)␊
544{␊
545␉int i;␊
546␉for(i = 1; (unsigned)i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)␊
547␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) ␊
548␉␉␉␉&& (dram_controllers[i].device == dram_dev->device_id))␊
549␉␉{␊
550␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊
551␉␉␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel " : "" ,␊
552␉␉␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊
553␉␉␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊
554␉␉␉␊
555␉␉␉if (dram_controllers[i].initialise != NULL)␊
556␉␉␉␉dram_controllers[i].initialise(dram_dev);␊
557␉␉␉␉␉␉␉␊
558␉␉␉if (dram_controllers[i].poll_timings != NULL)␊
559␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊
560␉␉␉␉␉␉␉␉␊
561␉␉␉if (dram_controllers[i].poll_speed != NULL)␊
562␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊
563␉␉␉ ␊
564 verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", ␊
565 (uint32_t)Platform->RAM.Frequency / 1000000,␊
566 (uint32_t)Platform->RAM.Frequency / 500000,␊
567 memory_channel_types[Platform->RAM.Channels]␊
568␉␉␉␉␉,Platform->RAM.CAS, Platform->RAM.TRC, Platform->RAM.TRP, Platform->RAM.RAS␊
569␉␉␉␉␉,Platform->RAM.CAS, Platform->RAM.TRC, Platform->RAM.TRP, Platform->RAM.RAS␊
570␉␉␉␉␉);␊
571#if DEBUG_DRAM␊
572␉␉␉ getc();␊
573#endif␊
574␉␉␉␊
575␉␉}␉␊
576}␉␊
577

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