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Root/trunk/i386/libsaio/smbios_getters.c

1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␉␉␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's. ␊
34␉␉␉␉␉case CPU_MODEL_SANDY_XEON: ␊
35␉␉␉␉␉case CPU_MODEL_SANDY:␊
36␉␉␉␉␉␉value->word = 0;␊
37␉␉␉␉␉␉break;␊
38␉␉␉␉␉default:␊
39␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
40␉␉␉␉}␊
41␉␉␉}␊
42␉␉␉␉break;␊
43␉␉␉␉␊
44␉␉␉default:␊
45␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊
46␉␉}␊
47␉}␊
48␉return true;␊
49}␊
50␊
51bool getProcessorInformationMaximumClock(returnType *value)␊
52{␊
53␉value->word = Platform.CPU.CPUFrequency/1000000;␊
54␉return true;␊
55}␊
56␊
57bool getSMBOemProcessorBusSpeed(returnType *value)␊
58{␊
59␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
60␉{␉␉␊
61␉␉switch (Platform.CPU.Family) ␊
62␉␉{␊
63␉␉␉case 0x06:␊
64␉␉␉{␊
65␉␉␉␉switch (Platform.CPU.Model)␊
66␉␉␉␉{␊
67␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
68␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
69␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
70␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
71␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
72␉␉␉␉␉␉return false;␊
73␊
74␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
75␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
76␉␉␉␉␉case CPU_MODEL_DALES:␊
77␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
78␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
79␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
80␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
81␉␉␉␉␉{␊
82␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
83␉␉␉␉␉␉int nhm_bus = 0x3F;␊
84␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
85␉␉␉␉␉␉unsigned long did, vid;␊
86␉␉␉␉␉␉int i;␊
87␉␉␉␉␉␉␊
88␉␉␉␉␉␉// Nehalem supports Scrubbing␊
89␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
90␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
91␉␉␉␉␉␉{␊
92␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
93␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
94␉␉␉␉␉␉␉vid &= 0xFFFF;␊
95␉␉␉␉␉␉␉did &= 0xFF00;␊
96␉␉␉␉␉␉␉␊
97␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
98␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
99␉␉␉␉␉␉}␊
100␉␉␉␉␉␉␊
101␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
102␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
103␉␉␉␉␉␉qpimult &= 0x7F;␊
104␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
105␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
106␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
107␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
108␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
109␉␉␉␉␉␉value->word = qpibusspeed;␊
110␉␉␉␉␉␉return true;␊
111␉␉␉␉␉}␊
112␉␉␉␉}␊
113␉␉␉}␊
114␉␉}␊
115␉}␊
116␉return false;␊
117}␊
118␊
119uint16_t simpleGetSMBOemProcessorType(void)␊
120{␊
121␉if (Platform.CPU.NoCores >= 4) ␊
122␉{␊
123␉␉return 0x0501;␉// Quad-Core Xeon␊
124␉}␊
125␉else if (Platform.CPU.NoCores == 1) ␊
126␉{␊
127␉␉return 0x0201;␉// Core Solo␊
128␉};␊
129␉␊
130␉return 0x0301;␉␉// Core 2 Duo␊
131}␊
132␊
133bool getSMBOemProcessorType(returnType *value)␊
134{␊
135␉static bool done = false;␉␉␊
136␉␉␊
137␉value->word = simpleGetSMBOemProcessorType();␊
138␊
139␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
140␉{␊
141␉␉if (!done)␊
142␉␉{␊
143␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
144␉␉␉done = true;␊
145␉␉}␊
146␉␉␊
147␉␉switch (Platform.CPU.Family) ␊
148␉␉{␊
149␉␉␉case 0x06:␊
150␉␉␉{␊
151␉␉␉␉switch (Platform.CPU.Model)␊
152␉␉␉␉{␊
153␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
154␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
155␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
156␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
157␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
158␉␉␉␉␉␉return true;␊
159␊
160␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
161␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
162␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
163␉␉␉␉␉␉else␊
164␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
165␉␉␉␉␉␉return true;␊
166␊
167␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
168␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
169␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
170␉␉␉␉␉␉else␊
171␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
172␉␉␉␉␉␉return true;␊
173␊
174␉␉␉␉␉case CPU_MODEL_DALES:␊
175␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
176␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
177␉␉␉␉␉␉else␊
178␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
179␉␉␉␉␉␉return true;␊
180␊
181␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
182 case CPU_MODEL_SANDY_XEON:␉␉␉// Intel Xeon E3␊
183␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
184␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
185␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
186␉␉␉␉␉␉else␊
187␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
188␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
189␉␉␉␉␉␉␉else␊
190␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
191␉␉␉␉␉␉return true;␊
192␊
193␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
194␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
195␉␉␉␉␉␉value->word = 0x0501;␉␉␉␉// Core i7␊
196␉␉␉␉␉␉return true;␊
197␉␉␉␉}␊
198␉␉␉}␊
199␉␉}␊
200␉}␊
201␉␊
202␉return false;␊
203}␊
204␊
205bool getSMBMemoryDeviceMemoryType(returnType *value)␊
206{␊
207␉static int idx = -1;␊
208␉int␉map;␊
209␊
210␉idx++;␊
211␉if (idx < MAX_RAM_SLOTS)␊
212␉{␊
213␉␉map = Platform.DMI.DIMM[idx];␊
214␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
215␉␉{␊
216␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
217␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
218␉␉␉return true;␊
219␉␉}␊
220␉}␊
221␉␊
222␉return false;␊
223//␉value->byte = SMB_MEM_TYPE_DDR2;␊
224//␉return true;␊
225}␊
226␊
227bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
228{␊
229␉static int idx = -1;␊
230␉int␉map;␊
231␊
232␉idx++;␊
233␉if (idx < MAX_RAM_SLOTS)␊
234␉{␊
235␉␉map = Platform.DMI.DIMM[idx];␊
236␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
237␉␉{␊
238␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
239␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
240␉␉␉return true;␊
241␉␉}␊
242␉}␊
243␊
244␉return false;␊
245//␉value->dword = 800;␊
246//␉return true;␊
247}␊
248␊
249bool getSMBMemoryDeviceManufacturer(returnType *value)␊
250{␊
251␉static int idx = -1;␊
252␉int␉map;␊
253␊
254␉idx++;␊
255␉if (idx < MAX_RAM_SLOTS)␊
256␉{␊
257␉␉map = Platform.DMI.DIMM[idx];␊
258␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
259␉␉{␊
260␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
261␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
262␉␉␉return true;␊
263␉␉}␊
264␉}␊
265␊
266␉if (!bootInfo->memDetect)␊
267␉␉return false;␊
268␉value->string = NOT_AVAILABLE;␊
269␉return true;␊
270}␊
271␉␊
272bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
273{␊
274␉static int idx = -1;␊
275␉int␉map;␊
276␊
277␉idx++;␊
278␊
279 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
280␊
281␉if (idx < MAX_RAM_SLOTS)␊
282␉{␊
283␉␉map = Platform.DMI.DIMM[idx];␊
284␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
285␉␉{␊
286␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
287␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
288␉␉␉return true;␊
289␉␉}␊
290␉}␊
291␊
292␉if (!bootInfo->memDetect)␊
293␉␉return false;␊
294␉value->string = NOT_AVAILABLE;␊
295␉return true;␊
296}␊
297␊
298bool getSMBMemoryDevicePartNumber(returnType *value)␊
299{␊
300␉static int idx = -1;␊
301␉int␉map;␊
302␊
303␉idx++;␊
304␉if (idx < MAX_RAM_SLOTS)␊
305␉{␊
306␉␉map = Platform.DMI.DIMM[idx];␊
307␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
308␉␉{␊
309␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
310␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
311␉␉␉return true;␊
312␉␉}␊
313␉}␊
314␊
315␉if (!bootInfo->memDetect)␊
316␉␉return false;␊
317␉value->string = NOT_AVAILABLE;␊
318␉return true;␊
319}␊
320␊
321␊
322// getting smbios addr with fast compare ops, late checksum testing ...␊
323#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
324static const char * const SMTAG = "_SM_";␊
325static const char* const DMITAG = "_DMI_";␊
326␊
327SMBEntryPoint *getAddressOfSmbiosTable(void)␊
328{␊
329␉SMBEntryPoint␉*smbios;␊
330␉/* ␊
331␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
332␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
333␉ */␊
334␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
335␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
336␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
337␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
338␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
339␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
340␉ {␊
341␉␉␉return smbios;␊
342␉ }␊
343␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
344␉}␊
345␉printf("ERROR: Unable to find SMBIOS!\n");␊
346␉pause();␊
347␉return NULL;␊
348}␊
349␊
350

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