| 1 | /*␊ |
| 2 | *␊ |
| 3 | *␊ |
| 4 | */␊ |
| 5 | ␊ |
| 6 | #ifndef __LIBSAIO_SPD_H␊ |
| 7 | #define __LIBSAIO_SPD_H␊ |
| 8 | ␊ |
| 9 | #include "platform.h"␊ |
| 10 | ␊ |
| 11 | extern void scan_spd(PlatformInfo_t *p);␊ |
| 12 | ␊ |
| 13 | #if 0 // Old structures and functions␊ |
| 14 | ␊ |
| 15 | #include "libsaio.h"␊ |
| 16 | ␊ |
| 17 | void scan_smbus_controller(pci_dt_t *smbus_dev);␊ |
| 18 | ␊ |
| 19 | struct smbus_controllers_t {␊ |
| 20 | ␉uint32_t␉vendor;␊ |
| 21 | ␉uint32_t␉device;␊ |
| 22 | ␉char␉␉*name;␊ |
| 23 | void (*read_smb)(pci_dt_t *smbus_dev);␊ |
| 24 | };␊ |
| 25 | ␊ |
| 26 | ␊ |
| 27 | /*␊ |
| 28 | * Serial Presence Detect (SPD) data stored on SDRAM modules.␊ |
| 29 | *␊ |
| 30 | * Datasheet:␊ |
| 31 | * - Name: PC SDRAM Serial Presence Detect (SPD) Specification␊ |
| 32 | * Revision 1.2A, December, 1997␊ |
| 33 | * - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf␊ |
| 34 | *␊ |
| 35 | * Datasheet (alternative):␊ |
| 36 | * - Name: SERIAL PRESENCE DETECT STANDARD, General Standard␊ |
| 37 | * JEDEC Standard No. 21-C␊ |
| 38 | * - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF␊ |
| 39 | */␊ |
| 40 | ␊ |
| 41 | ␊ |
| 42 | /* Byte numbers. */␊ |
| 43 | #define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */␊ |
| 44 | #define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */␊ |
| 45 | #define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */␊ |
| 46 | #define SPD_NUM_ROWS 3 /* Number of row address bits */␊ |
| 47 | #define SPD_NUM_COLUMNS 4 /* Number of column address bits */␊ |
| 48 | #define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */␊ |
| 49 | #define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */␊ |
| 50 | #define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */␊ |
| 51 | #define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */␊ |
| 52 | #define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */␊ |
| 53 | #define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */␊ |
| 54 | #define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */␊ |
| 55 | #define SPD_REFRESH 12 /* Refresh rate/type */␊ |
| 56 | #define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */␊ |
| 57 | #define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */␊ |
| 58 | #define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */␊ |
| 59 | #define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */␊ |
| 60 | #define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */␊ |
| 61 | #define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */␊ |
| 62 | #define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */␊ |
| 63 | #define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */␊ |
| 64 | #define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */␊ |
| 65 | #define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */␊ |
| 66 | #define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */␊ |
| 67 | #define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */␊ |
| 68 | #define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */␊ |
| 69 | #define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */␊ |
| 70 | #define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */␊ |
| 71 | #define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */␊ |
| 72 | #define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */␊ |
| 73 | #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */␊ |
| 74 | #define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */␊ |
| 75 | #define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */␊ |
| 76 | #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */␊ |
| 77 | #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */␊ |
| 78 | #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */␊ |
| 79 | #define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */␊ |
| 80 | #define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */␊ |
| 81 | #define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */␊ |
| 82 | #define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */␊ |
| 83 | #define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */␊ |
| 84 | #define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */␊ |
| 85 | #define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */␊ |
| 86 | #define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */␊ |
| 87 | #define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */␊ |
| 88 | #define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */␊ |
| 89 | #define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */␊ |
| 90 | #define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */␊ |
| 91 | #define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */␊ |
| 92 | #define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */␊ |
| 93 | #define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */␊ |
| 94 | #define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */␊ |
| 95 | #define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */␊ |
| 96 | #define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */␊ |
| 97 | #define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */␊ |
| 98 | #define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */␊ |
| 99 | #define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */␊ |
| 100 | #define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */␊ |
| 101 | ␊ |
| 102 | /* DRAM specifications use the following naming conventions for SPD locations */␊ |
| 103 | #define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME␊ |
| 104 | #define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE␊ |
| 105 | #define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY␊ |
| 106 | #define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY␊ |
| 107 | #define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE␊ |
| 108 | #define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME␊ |
| 109 | #define SPD_tRC␉␉␉␉␉␉␉␉41␉/* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */␊ |
| 110 | #define SPD_tRFC␉␉␉␉␉␉␉42␉/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */␊ |
| 111 | ␊ |
| 112 | ␊ |
| 113 | /* SPD_MEMORY_TYPE values. */␊ |
| 114 | #define SPD_MEMORY_TYPE_FPM_DRAM␉␉␉1␊ |
| 115 | #define SPD_MEMORY_TYPE_EDO␉␉␉␉␉2␊ |
| 116 | #define SPD_MEMORY_TYPE_PIPELINED_NIBBLE␉3␊ |
| 117 | #define SPD_MEMORY_TYPE_SDRAM␉␉␉␉4␊ |
| 118 | #define SPD_MEMORY_TYPE_MULTIPLEXED_ROM␉␉5␊ |
| 119 | #define SPD_MEMORY_TYPE_SGRAM_DDR␉␉␉6␊ |
| 120 | #define SPD_MEMORY_TYPE_SDRAM_DDR␉␉␉7␊ |
| 121 | #define SPD_MEMORY_TYPE_SDRAM_DDR2␉␉␉8␊ |
| 122 | #define SPD_MEMORY_TYPE_SDRAM_DDR3␉␉␉0xb␊ |
| 123 | ␊ |
| 124 | /* SPD_MODULE_VOLTAGE values. */␊ |
| 125 | #define SPD_VOLTAGE_TTL␉␉␉␉␉␉0 /* 5.0 Volt/TTL */␊ |
| 126 | #define SPD_VOLTAGE_LVTTL␉␉␉␉␉1 /* LVTTL */␊ |
| 127 | #define SPD_VOLTAGE_HSTL␉␉␉␉␉2 /* HSTL 1.5 */␊ |
| 128 | #define SPD_VOLTAGE_SSTL3␉␉␉␉␉3 /* SSTL 3.3 */␊ |
| 129 | #define SPD_VOLTAGE_SSTL2␉␉␉␉␉4 /* SSTL 2.5 */␊ |
| 130 | ␊ |
| 131 | /* SPD_DIMM_CONFIG_TYPE values. */␊ |
| 132 | #define ERROR_SCHEME_NONE␉␉␉␉␉0␊ |
| 133 | #define ERROR_SCHEME_PARITY␉␉␉␉␉1␊ |
| 134 | #define ERROR_SCHEME_ECC␉␉␉␉␉2␊ |
| 135 | ␊ |
| 136 | /* SPD_ACCEPTABLE_CAS_LATENCIES values. */␊ |
| 137 | // TODO: Check values.␊ |
| 138 | #define SPD_CAS_LATENCY_1_0␉␉␉␉␉0x01␊ |
| 139 | #define SPD_CAS_LATENCY_1_5␉␉␉␉␉0x02␊ |
| 140 | #define SPD_CAS_LATENCY_2_0␉␉␉␉␉0x04␊ |
| 141 | #define SPD_CAS_LATENCY_2_5␉␉␉␉␉0x08␊ |
| 142 | #define SPD_CAS_LATENCY_3_0␉␉␉␉␉0x10␊ |
| 143 | #define SPD_CAS_LATENCY_3_5␉␉␉␉␉0x20␊ |
| 144 | #define SPD_CAS_LATENCY_4_0␉␉␉␉␉0x40␊ |
| 145 | ␊ |
| 146 | #define SPD_CAS_LATENCY_DDR2_3␉␉␉␉(1 << 3)␊ |
| 147 | #define SPD_CAS_LATENCY_DDR2_4␉␉␉␉(1 << 4)␊ |
| 148 | #define SPD_CAS_LATENCY_DDR2_5␉␉␉␉(1 << 5)␊ |
| 149 | #define SPD_CAS_LATENCY_DDR2_6␉␉␉␉(1 << 6)␊ |
| 150 | ␊ |
| 151 | /* SPD_SUPPORTED_BURST_LENGTHS values. */␊ |
| 152 | #define SPD_BURST_LENGTH_1␉␉␉␉␉1␊ |
| 153 | #define SPD_BURST_LENGTH_2␉␉␉␉␉2␊ |
| 154 | #define SPD_BURST_LENGTH_4␉␉␉␉␉4␊ |
| 155 | #define SPD_BURST_LENGTH_8␉␉␉␉␉8␊ |
| 156 | #define SPD_BURST_LENGTH_PAGE␉␉␉␉(1 << 7)␊ |
| 157 | ␊ |
| 158 | /* SPD_MODULE_ATTRIBUTES values. */␊ |
| 159 | #define MODULE_BUFFERED␉␉␉␉␉␉1␊ |
| 160 | #define MODULE_REGISTERED␉␉␉␉␉2␊ |
| 161 | ␊ |
| 162 | #endif␊ |
| 163 | ␊ |
| 164 | #endif /* !__LIBSAIO_SPD_H */␊ |
| 165 | |
