Chameleon

Chameleon Svn Source Tree

Root/branches/meklort/i386/libsaio/usb.c

Source at commit 155 created 13 years 11 months ago.
By meklort, Support files updated (headers, memory map to fit large ramdisks, etc)
1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10#include "libsaio.h"␊
11#include "boot.h"␊
12#include "bootstruct.h"␊
13#include "pci.h"␊
14␊
15#ifndef DEBUG_USB␊
16#define DEBUG_USB 0␊
17#endif␊
18␊
19#if DEBUG_USB␊
20#define DBG(x...)␉printf(x)␊
21#else␊
22#define DBG(x...)␊
23#endif␊
24␊
25␊
26struct pciList␊
27{␊
28␉pci_dt_t* pciDev;␊
29␉struct pciList* next;␊
30};␊
31␊
32struct pciList* usbList = NULL;␊
33␊
34int legacy_off (pci_dt_t *pci_dev);␊
35int ehci_acquire (pci_dt_t *pci_dev);␊
36int uhci_reset (pci_dt_t *pci_dev);␊
37␊
38void notify_usb_dev(pci_dt_t *pci_dev)␊
39{␊
40␉struct pciList* current = usbList;␊
41␉if(!usbList)␊
42␉{␊
43␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊
44␉␉usbList->next = NULL;␊
45␉␉usbList->pciDev = pci_dev;␊
46␉}␊
47␉else {␊
48␉␉while(current != NULL && current->next != NULL)␊
49␉␉{␊
50␉␉␉current = current->next;␊
51␉␉}␊
52␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊
53␉␉current = current->next;␊
54␉␉␊
55␉␉current->pciDev = pci_dev;␊
56␉␉current->next = NULL;␊
57␉}␊
58␊
59␉␊
60␉␊
61␉␊
62}␊
63␊
64int usb_loop()␊
65{␊
66␉bool fix_ehci, fix_uhci, fix_usb, fix_legacy;␊
67␉fix_ehci = fix_uhci = fix_usb = fix_legacy;␊
68␉if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig) && fix_usb) {␊
69␉␉fix_ehci = fix_uhci = fix_legacy = true;␊
70␉} else {␊
71␉␉getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);␊
72␉␉getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);␊
73␉␉getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);␊
74␊
75␉}␊
76␊
77␉␊
78␉struct pciList* current = usbList;␊
79␉while(current)␊
80␉{␊
81␉␉uhci_reset(current->pciDev);␊
82␉␉legacy_off(current->pciDev);␊
83␉␉ehci_acquire(current->pciDev);␊
84␉␉␊
85␉␉current = current->next;␊
86␉}␊
87␉return 1;␊
88}␊
89␊
90int legacy_off (pci_dt_t *pci_dev)␊
91{␊
92␉// Set usb legacy off modification by Signal64␊
93␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
94␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊
95␉// AKA: Make this run immediatly before the kernel is calles␊
96␉uint32_t␉capaddr, opaddr; ␉␉␊
97␉uint8_t␉␉eecp;␉␉␉␊
98␉uint32_t␉usbcmd, usbsts, usbintr;␉␉␉␊
99␉uint32_t␉usblegsup, usblegctlsts;␉␉␊
100␉␊
101␉int isOSowned;␊
102␉int isBIOSowned;␊
103␉␊
104␉verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
105␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
106␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
107␉␊
108␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
109␉capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
110␉␊
111␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
112␉opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
113␉␊
114␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
115␉eecp=*((unsigned char*)(capaddr + 9));␊
116␉␊
117␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
118␉␊
119␉usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
120␉usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
121␉usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
122␉␊
123␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
124␉␊
125␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊
126␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
127␉␊
128␉// informational only␊
129␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
130␉isOSowned = !!((usblegsup) & (1 << (24)));␊
131␉␊
132␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
133␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
134␉␊
135␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
136␉␊
137␉// Reset registers to Legacy OFF␊
138␉DBG("Clearing USBLEGCTLSTS\n");␊
139␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
140␉␊
141␉// if delay value is in milliseconds it doesn't appear to work. ␊
142␉// setting value to anything up to 65535 does not add the expected delay here.␊
143␉delay(100);␊
144␉␊
145␉usbcmd = *((unsigned int*)(opaddr));␊
146␉usbsts = *((unsigned int*)(opaddr + 4));␊
147␉usbintr = *((unsigned int*)(opaddr + 8));␊
148␉␊
149␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
150␉␊
151␉DBG("Clearing Registers\n");␊
152␉␊
153␉// clear registers to default␊
154␉usbcmd = (usbcmd & 0xffffff00);␊
155␉*((unsigned int*)(opaddr)) = usbcmd;␊
156␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
157␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
158␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
159␉␊
160␉// get the results␊
161␉usbcmd = *((unsigned int*)(opaddr));␊
162␉usbsts = *((unsigned int*)(opaddr + 4));␊
163␉usbintr = *((unsigned int*)(opaddr + 8));␊
164␉␊
165␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
166␉␊
167␉// read 32bit USBLEGSUP (eecp+0) ␊
168␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
169␉␊
170␉// informational only␊
171␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
172␉isOSowned = !!((usblegsup) & (1 << (24)));␊
173␉␊
174␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
175␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
176␉␊
177␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
178␉␊
179␉verbose("Legacy USB Off Done\n");␉␊
180␉return 1;␊
181}␊
182␊
183␊
184␊
185int ehci_acquire (pci_dt_t *pci_dev)␊
186{␊
187␉int␉␉j, k;␊
188␉uint32_t␉base;␊
189␉uint8_t␉␉eecp;␊
190␉uint8_t␉␉legacy[8];␊
191␉bool␉␉isOwnershipConflict;␉␊
192␉bool␉␉alwaysHardBIOSReset;␊
193␊
194␉alwaysHardBIOSReset = false;␉␊
195␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊
196␉␉alwaysHardBIOSReset = true;␊
197␉}␊
198␊
199␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
200␉base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
201␊
202␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
203␉␉pci_dev->vendor_id, pci_dev->device_id,␊
204␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
205␉␉base);␊
206␊
207␉if (*((unsigned char*)base) < 0xc)␊
208␉{␊
209␉␉DBG("Config space too small: no legacy implementation\n");␊
210␉␉return 1;␊
211␉}␊
212␉eecp = *((unsigned char*)(base + 9));␊
213␉if (!eecp) {␊
214␉␉DBG("No extended capabilities: no legacy implementation\n");␊
215␉␉return 1;␊
216␉}␊
217␊
218␉DBG("eecp=%x\n",eecp);␊
219␊
220␉// bad way to do it␊
221␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
222␉for (j = 0; j < 8; j++) {␊
223␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
224␉␉DBG("%02x ", legacy[j]);␊
225␉}␊
226␉DBG("\n");␊
227␊
228␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
229␉//We try soft reset first - some systems hang on reboot with hard reset␊
230␉// Definitely needed during reboot on 10.4.6␊
231␊
232␉isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊
233␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
234␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
235␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
236␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
237␉␉for (k = 0; k < 25; k++) {␊
238␉␉␉for (j = 0; j < 8; j++) {␊
239␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
240␉␉␉}␊
241␉␉␉if (legacy[3] == 0) {␊
242␉␉␉␉break;␊
243␉␉␉}␊
244␉␉␉delay(10);␊
245␉␉}␊
246␉}␉␊
247␊
248␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
249␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
250␊
251␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
252␉for (k = 0; k < 25; k++) {␊
253␉␉for (j = 0;j < 8; j++) {␊
254␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
255␉␉}␊
256␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
257␉␉if (legacy[2] == 0) {␊
258␉␉␉break;␊
259␉␉}␊
260␉␉delay(10);␊
261␉}␊
262␊
263␉for (j = 0;j < 8; j++) {␊
264␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
265␉}␊
266␉isOwnershipConflict = ((legacy[2]) != 0);␊
267␉if (isOwnershipConflict) {␊
268␉␉// Soft reset has failed. Assume SMI being ignored␊
269␉␉// Hard reset␊
270␉␉// Force Clear BIOS BIT␊
271␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
272␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
273␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
274␊
275␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
276␉␉for (k = 0; k < 25; k++) {␊
277␉␉␉for (j = 0; j < 8; j++) {␊
278␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
279␉␉␉}␊
280␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
281␊
282␉␉␉if ((legacy[2]) == 0) {␊
283␉␉␉␉break;␊
284␉␉␉}␊
285␉␉␉delay(10);␉␊
286␉␉}␉␉␊
287␉␉// Disable further SMI events␊
288␉␉for (j = 4; j < 8; j++) {␊
289␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
290␉␉}␊
291␉}␊
292␊
293␉for (j = 0; j < 8; j++) {␊
294␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
295␉}␊
296␊
297␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
298␊
299␉// Final Ownership Resolution Check...␊
300␉if (legacy[2] & 1) {␉␉␉␉␉␊
301␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
302␉␉return 0;␊
303␉}␊
304␊
305␉DBG("EHCI Acquire OS Ownership done\n");␉␊
306␉return 1;␊
307}␊
308␊
309int uhci_reset (pci_dt_t *pci_dev)␊
310{␊
311␉uint32_t base, port_base;␊
312␉␊
313␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
314␉port_base = (base >> 5) & 0x07ff;␊
315␊
316␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
317␉␉pci_dev->vendor_id, pci_dev->device_id,␊
318␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
319␉␉port_base, base);␊
320␉␊
321␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
322␊
323␉outw (port_base, 0x0002);␊
324␉delay(10);␊
325␉outw (port_base+4,0);␊
326␉delay(10);␊
327␉outw (port_base,0);␊
328␉return 1;␊
329}␊
330

Archive Download this file

Revision: 155