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Root/branches/ErmaC/Modules/i386/modules/NVIDIAGraphicsEnabler/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51//#include "boot.h"␊
52#include "libsa.h"␊
53#include "saio_internal.h"␊
54#include "bootstruct.h"␊
55#include "pci.h"␊
56#include "platform.h"␊
57#include "device_inject.h"␊
58#include "nvidia.h"␊
59␊
60#ifndef DEBUG_NVIDIA␊
61#define DEBUG_NVIDIA 0␊
62#endif␊
63␊
64#if DEBUG_NVIDIA␊
65#define DBG(x...)␉printf(x)␊
66#else␊
67#define DBG(x...)␊
68#endif␊
69␊
70#define kUseNvidiaROM␉␉␉␉"UseNvidiaROM"␊
71#define kVBIOS␉␉␉␉␉␉"VBIOS"␊
72#define kDcfg0␉␉␉␉␉␉"display_0"␊
73#define kDcfg1␉␉␉␉␉␉"display_1"␊
74␊
75#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
76#define PATCH_ROM_SUCCESS␉␉␉1␊
77#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
78#define PATCH_ROM_FAILED␉␉␉0␊
79#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
80#define TYPE_GROUPED␉␉␉␉0xff␊
81␊
82extern uint32_t devices_number;␊
83␊
84const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
85const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
86const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
87const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
88const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
89const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
90const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
91const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
92␊
93static uint8_t default_NVCAP[]= {␊
94␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
95␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
96␉0x00, 0x00, 0x00, 0x00␊
97};␊
98␊
99#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
100␊
101static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
102static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
103␊
104#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
105#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
106␊
107static struct nv_chipsets_t NVKnownChipsets[] = {␊
108␉{ 0x00000000, "Unknown" },␊
109// temporary placement␊
110␉// { 0x10DE0DF4, "GeForce GT 450M" }, //Azi + issue #99␊
111␉// { 0x10DE1251, "GeForce GTX 560M" }, // Asus G74SX␊
112//========================================␊
113␉// 0040 - 004F␉␊
114␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
115␉{ 0x10DE0041, "GeForce 6800" },␊
116␉{ 0x10DE0042, "GeForce 6800 LE" },␊
117␉{ 0x10DE0043, "GeForce 6800 XE" },␊
118␉{ 0x10DE0044, "GeForce 6800 XT" },␊
119␉{ 0x10DE0045, "GeForce 6800 GT" },␊
120␉{ 0x10DE0046, "GeForce 6800 GT" },␊
121␉{ 0x10DE0047, "GeForce 6800 GS" },␊
122␉{ 0x10DE0048, "GeForce 6800 XT" },␊
123␉{ 0x10DE004D, "Quadro FX 3400" },␊
124␉{ 0x10DE004E, "Quadro FX 4000" },␊
125␉// 0050 - 005F␊
126␉// 0060 - 006F␉␊
127␉// 0070 - 007F␉␊
128␉// 0080 - 008F␉␊
129␉// 0090 - 009F␉␊
130␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
131␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
132␉{ 0x10DE0092, "GeForce 7800 GT" },␊
133␉{ 0x10DE0093, "GeForce 7800 GS" },␊
134␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
135␉{ 0x10DE0098, "GeForce Go 7800" },␊
136␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
137␉{ 0x10DE009D, "Quadro FX 4500" },␊
138␉// 00A0 - 00AF␉␊
139␉// 00B0 - 00BF␉␊
140␉// 00C0 - 00CF␉␊
141␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
142␉{ 0x10DE00C1, "GeForce 6800" },␊
143␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
144␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
145␉{ 0x10DE00C8, "GeForce Go 6800" },␊
146␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
147␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
148␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
149␉{ 0x10DE00CE, "Quadro FX 1400" },␊
150␉// 00D0 - 00DF␉␊
151␉// 00E0 - 00EF␉␊
152␉// 00F0 - 00FF␉␊
153␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
154␉{ 0x10DE00F2, "GeForce 6600" },␊
155␉{ 0x10DE00F3, "GeForce 6200" },␊
156␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
157␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
158␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
159␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
160␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
161␉// 0100 - 010F␉␊
162␉// 0110 - 011F␉␊
163␉// 0120 - 012F␉␊
164␉// 0130 - 013F␉␊
165␉// 0140 - 014F␉␊
166␉{ 0x10DE0140, "GeForce 6600 GT" },␊
167␉{ 0x10DE0141, "GeForce 6600" },␊
168␉{ 0x10DE0142, "GeForce 6600 LE" },␊
169␉{ 0x10DE0143, "GeForce 6600 VE" },␊
170␉{ 0x10DE0144, "GeForce Go 6600" },␊
171␉{ 0x10DE0145, "GeForce 6610 XL" },␊
172␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
173␉{ 0x10DE0147, "GeForce 6700 XL" },␊
174␉{ 0x10DE0148, "GeForce Go 6600" },␊
175␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
176␉{ 0x10DE014A, "Quadro NVS 440" },␊
177␉{ 0x10DE014C, "Quadro FX 550" },␊
178␉{ 0x10DE014D, "Quadro FX 550" },␊
179␉{ 0x10DE014E, "Quadro FX 540" },␊
180␉{ 0x10DE014F, "GeForce 6200" },␊
181␉// 0150 - 015F␉␊
182␉// 0160 - 016F␉␊
183␉{ 0x10DE0160, "GeForce 6500" },␊
184␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
185␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
186␉{ 0x10DE0163, "GeForce 6200 LE" },␊
187␉{ 0x10DE0164, "GeForce Go 6200" },␊
188␉{ 0x10DE0165, "Quadro NVS 285" },␊
189␉{ 0x10DE0166, "GeForce Go 6400" },␊
190␉{ 0x10DE0167, "GeForce Go 6200" },␊
191␉{ 0x10DE0168, "GeForce Go 6400" },␊
192␉{ 0x10DE0169, "GeForce 6250" },␊
193␉{ 0x10DE016A, "GeForce 7100 GS" },␊
194␉// 0170 - 017F␉␊
195␉// 0180 - 018F␉␊
196␉// 0190 - 019F␉␉␊
197␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
198␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
199␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
200␉{ 0x10DE0197, "Tesla C870" },␊
201␉{ 0x10DE019D, "Quadro FX 5600" },␊
202␉{ 0x10DE019E, "Quadro FX 4600" },␊
203␉// 01A0 - 01AF␉␊
204␉// 01B0 - 01BF␉␊
205␉// 01C0 - 01CF␉␊
206␉// 01D0 - 01DF␉␉␊
207␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
208␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
209␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
210␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
211␉{ 0x10DE01D6, "GeForce Go 7200" },␊
212␉{ 0x10DE01D7, "GeForce Go 7300" },␊
213␉{ 0x10DE01D8, "GeForce Go 7400" },␊
214␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
215␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
216␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
217␉{ 0x10DE01DC, "Quadro FX 350M" },␊
218␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
219␉{ 0x10DE01DE, "Quadro FX 350" },␊
220␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
221␉// 01E0 - 01EF␉␊
222␉// 01F0 - 01FF␊
223␉// 0200 - 020F␉␊
224␉// 0210 - 021F␉␊
225␉{ 0x10DE0211, "GeForce 6800" },␊
226␉{ 0x10DE0212, "GeForce 6800 LE" },␊
227␉{ 0x10DE0215, "GeForce 6800 GT" },␊
228␉{ 0x10DE0218, "GeForce 6800 XT" },␊
229␉// 0220 - 022F␉␊
230␉{ 0x10DE0221, "GeForce 6200" },␊
231␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
232␉// 0230 - 023F␉␊
233␉// 0240 - 024F␉␊
234␉{ 0x10DE0240, "GeForce 6150" },␊
235␉{ 0x10DE0241, "GeForce 6150 LE" },␊
236␉{ 0x10DE0242, "GeForce 6100" },␊
237␉{ 0x10DE0244, "GeForce Go 6150" },␊
238␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
239␉{ 0x10DE0247, "GeForce Go 6100" },␊
240␉// 0250 - 025F␉␊
241␉// 0260 - 026F␉␊
242␉// 0270 - 027F␉␊
243␉// 0280 - 028F␉␉␊
244␉// 0290 - 029F␉␊
245␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
246␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
247␉{ 0x10DE0292, "GeForce 7900 GS" },␊
248␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
249␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
250␉{ 0x10DE0295, "GeForce 7950 GT" },␊
251␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
252␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
253␉{ 0x10DE029A, "Quadro FX 2500M" },␊
254␉{ 0x10DE029B, "Quadro FX 1500M" },␊
255␉{ 0x10DE029C, "Quadro FX 5500" },␊
256␉{ 0x10DE029D, "Quadro FX 3500" },␊
257␉{ 0x10DE029E, "Quadro FX 1500" },␊
258␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
259␉// 02A0 - 02AF␉␊
260␉// 02B0 - 02BF␉␊
261␉// 02C0 - 02CF␉␊
262␉// 02D0 - 02DF␉␉␊
263␉// 02E0 - 02EF␉␉␊
264␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
265␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
266␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
267␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
268␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
269␉// 02F0 - 02FF␉␉␊
270␉// 0300 - 030F␉␉␊
271␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
272␉{ 0x10DE0302, "GeForce FX 5800" },␊
273␉{ 0x10DE0308, "Quadro FX 2000" },␊
274␉{ 0x10DE0309, "Quadro FX 1000" },␊
275␉// 0310 - 031F␉␉␊
276␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
277␉{ 0x10DE0312, "GeForce FX 5600" },␊
278␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
279␉{ 0x10DE031A, "GeForce FX Go5600" },␊
280␉{ 0x10DE031B, "GeForce FX Go5650" },␊
281␉{ 0x10DE031C, "Quadro FX Go700" },␊
282␉// 0320 - 032F␉␉␊
283␉{ 0x10DE0324, "GeForce FX Go5200" },␊
284␉{ 0x10DE0325, "GeForce FX Go5250" },␊
285␉{ 0x10DE0326, "GeForce FX 5500" },␊
286␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
287␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
288␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
289␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
290␉{ 0x10DE032D, "GeForce FX Go5100" },␊
291␉// 0330 - 033F␊
292␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
293␉{ 0x10DE0331, "GeForce FX 5900" },␊
294␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
295␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
296␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
297␉{ 0x10DE0338, "Quadro FX 3000" },␊
298␉{ 0x10DE033F, "Quadro FX 700" },␊
299␉// 0340 - 034F␊
300␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
301␉{ 0x10DE0342, "GeForce FX 5700" },␊
302␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
303␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
304␉{ 0x10DE0347, "GeForce FX Go5700" },␊
305␉{ 0x10DE0348, "GeForce FX Go5700" },␊
306␉{ 0x10DE034C, "Quadro FX Go1000" },␊
307␉{ 0x10DE034E, "Quadro FX 1100" },␊
308␉// 0350 - 035F␉␊
309␉// 0360 - 036F␉␊
310␉// 0370 - 037F␉␊
311␉// 0380 - 038F␉␉␉␊
312␉{ 0x10DE038B, "GeForce 7650 GS" },␊
313␉// 0390 - 039F␊
314␉{ 0x10DE0390, "GeForce 7650 GS" },␊
315␉{ 0x10DE0391, "GeForce 7600 GT" },␊
316␉{ 0x10DE0392, "GeForce 7600 GS" },␊
317␉{ 0x10DE0393, "GeForce 7300 GT" },␊
318␉{ 0x10DE0394, "GeForce 7600 LE" },␊
319␉{ 0x10DE0395, "GeForce 7300 GT" },␊
320␉{ 0x10DE0397, "GeForce Go 7700" },␊
321␉{ 0x10DE0398, "GeForce Go 7600" },␊
322␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
323␉{ 0x10DE039A, "Quadro NVS 300M" },␊
324␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
325␉{ 0x10DE039C, "Quadro FX 550M" },␊
326␉{ 0x10DE039E, "Quadro FX 560" },␊
327␉// 03A0 - 03AF␉␊
328␉// 03B0 - 03BF␉␊
329␉// 03C0 - 03CF␉␊
330␉// 03D0 - 03DF␉␉␉␊
331␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
332␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
333␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
334␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
335␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
336␉// 03E0 - 03EF␊
337␉// 03F0 - 03FF␊
338␉// 0400 - 040F␉␉␊
339␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
340␉{ 0x10DE0401, "GeForce 8600 GT" },␊
341␉{ 0x10DE0402, "GeForce 8600 GT" },␊
342␉{ 0x10DE0403, "GeForce 8600 GS" },␊
343␉{ 0x10DE0404, "GeForce 8400 GS" },␊
344␉{ 0x10DE0405, "GeForce 9500M GS" },␊
345␉{ 0x10DE0406, "GeForce 8300 GS" },␊
346␉{ 0x10DE0407, "GeForce 8600M GT" },␊
347␉{ 0x10DE0408, "GeForce 9650M GS" },␊
348␉{ 0x10DE0409, "GeForce 8700M GT" },␊
349␉{ 0x10DE040A, "Quadro FX 370" },␊
350␉{ 0x10DE040B, "Quadro NVS 320M" },␊
351␉{ 0x10DE040C, "Quadro FX 570M" },␊
352␉{ 0x10DE040D, "Quadro FX 1600M" },␊
353␉{ 0x10DE040E, "Quadro FX 570" },␊
354␉{ 0x10DE040F, "Quadro FX 1700" },␊
355␉// 0410 - 041F␉␊
356␉{ 0x10DE0410, "GeForce GT 330" },␊
357␉// 0420 - 042F␉␊
358␉{ 0x10DE0420, "GeForce 8400 SE" },␊
359␉{ 0x10DE0421, "GeForce 8500 GT" },␊
360␉{ 0x10DE0422, "GeForce 8400 GS" },␊
361␉{ 0x10DE0423, "GeForce 8300 GS" },␊
362␉{ 0x10DE0424, "GeForce 8400 GS" },␊
363␉{ 0x10DE0425, "GeForce 8600M GS" },␊
364␉{ 0x10DE0426, "GeForce 8400M GT" },␊
365␉{ 0x10DE0427, "GeForce 8400M GS" },␊
366␉{ 0x10DE0428, "GeForce 8400M G" },␊
367␉{ 0x10DE0429, "Quadro NVS 140M" },␊
368␉{ 0x10DE042A, "Quadro NVS 130M" },␊
369␉{ 0x10DE042B, "Quadro NVS 135M" },␊
370␉{ 0x10DE042C, "GeForce 9400 GT" },␊
371␉{ 0x10DE042D, "Quadro FX 360M" },␊
372␉{ 0x10DE042E, "GeForce 9300M G" },␊
373␉{ 0x10DE042F, "Quadro NVS 290" },␊
374␉// 0430 - 043F␊
375␉// 0440 - 044F␊
376␉// 0450 - 045F␊
377␉// 0460 - 046F␊
378␉// 0470 - 047F␊
379␉// 0480 - 048F␊
380␉// 0490 - 049F␊
381␉// 04A0 - 04AF␊
382␉// 04B0 - 04BF␊
383␉// 04C0 - 04CF␊
384␉// 04D0 - 04DF␊
385␉// 04E0 - 04EF␊
386␉// 04F0 - 04FF␊
387␉// 0500 - 050F␉␊
388␉// 0510 - 051F␉␊
389␉// 0520 - 052F␉␊
390␉// 0530 - 053F␉␊
391␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
392␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
393␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
394␉// 0540 - 054F␊
395␉// 0550 - 055F␊
396␉// 0560 - 056F␊
397␉// 0570 - 057F␊
398␉// 0580 - 058F␊
399␉// 0590 - 059F␊
400␉// 05A0 - 05AF␊
401␉// 05B0 - 05BF␊
402␉// 05C0 - 05CF␊
403␉// 05D0 - 05DF␊
404␉// 05E0 - 05EF␉␊
405␉{ 0x10DE05E0, "GeForce GTX 295" },␊
406␉{ 0x10DE05E1, "GeForce GTX 280" },␊
407␉{ 0x10DE05E2, "GeForce GTX 260" },␊
408␉{ 0x10DE05E3, "GeForce GTX 285" },␊
409␉{ 0x10DE05E6, "GeForce GTX 275" },␊
410␉{ 0x10DE05E7, "Tesla C1060" }, // ErmaC␊
411␉{ 0x10DE05EA, "GeForce GTX 260" },␊
412␉{ 0x10DE05EB, "GeForce GTX 295" },␊
413␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
414␉// 05F0 - 05FF␉␉␊
415␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
416␉{ 0x10DE05F9, "Quadro CX" },␊
417␉{ 0x10DE05FD, "Quadro FX 5800" },␊
418␉{ 0x10DE05FE, "Quadro FX 4800" },␊
419␉{ 0x10DE05FF, "Quadro FX 3800" },␊
420␉// 0600 - 060F␉␊
421␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
422␉{ 0x10DE0601, "GeForce 9800 GT" },␊
423␉{ 0x10DE0602, "GeForce 8800 GT" },␊
424␉{ 0x10DE0603, "GeForce GT 230" },␊
425␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
426␉{ 0x10DE0605, "GeForce 9800 GT" },␊
427␉{ 0x10DE0606, "GeForce 8800 GS" },␊
428␉{ 0x10DE0607, "GeForce GTS 240" },␊
429␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
430␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
431␉{ 0x10DE060A, "GeForce GTX 280M" },␊
432␉{ 0x10DE060B, "GeForce 9800M GT" },␊
433␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
434␉{ 0x10DE060D, "GeForce 8800 GS" },␊
435␉{ 0x10DE060F, "GeForce GTX 285M" },␊
436␉// 0610 - 061F␉␊
437␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
438␉{ 0x10DE0611, "GeForce 8800 GT" },␊
439␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
440␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
441␉{ 0x10DE0614, "GeForce 9800 GT" },␊
442␉{ 0x10DE0615, "GeForce GTS 250" },␊
443␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
444␉{ 0x10DE0618, "GeForce GTX 260M" },␊
445␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
446␉{ 0x10DE061A, "Quadro FX 3700" },␊
447␉{ 0x10DE061B, "Quadro VX 200" },␊
448␉{ 0x10DE061C, "Quadro FX 3600M" },␊
449␉{ 0x10DE061D, "Quadro FX 2800M" },␊
450␉{ 0x10DE061E, "Quadro FX 3700M" }, // ErmaC␊
451␉{ 0x10DE061F, "Quadro FX 3800M" },␊
452␉// 0620 - 062F␉␊
453␉{ 0x10DE0621, "GeForce GT 230" }, // ErmaC␊
454␉{ 0x10DE0622, "GeForce 9600 GT" },␊
455␉{ 0x10DE0623, "GeForce 9600 GS" },␊
456␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
457␉{ 0x10DE0626, "GeForce GT 130" },␊
458␉{ 0x10DE0627, "GeForce GT 140" },␊
459␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
460␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
461␉{ 0x10DE062B, "GeForce 9800M GS" }, // ErmaC␊
462␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
463␉{ 0x10DE062D, "GeForce 9600 GT" },␊
464␉{ 0x10DE062E, "GeForce 9600 GT" },␊
465␉// 0630 - 063F␉␊
466␉{ 0x10DE0631, "GeForce GTS 160M" },␊
467␉{ 0x10DE0632, "GeForce GTS 150M" },␊
468␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
469␉{ 0x10DE0637, "GeForce 9600 GT" },␊
470␉{ 0x10DE0638, "Quadro FX 1800" },␊
471␉{ 0x10DE063A, "Quadro FX 2700M" },␊
472␉// 0640 - 064F␉␊
473␉{ 0x10DE0640, "GeForce 9500 GT" },␊
474␉{ 0x10DE0641, "GeForce 9400 GT" },␊
475␉{ 0x10DE0642, "GeForce 8400 GS" },␊
476␉{ 0x10DE0643, "GeForce 9500 GT" },␊
477␉{ 0x10DE0644, "GeForce 9500 GS" },␊
478␉{ 0x10DE0645, "GeForce 9500 GS" },␊
479␉{ 0x10DE0646, "GeForce GT 120" },␊
480␉{ 0x10DE0647, "GeForce 9600M GT" },␊
481␉{ 0x10DE0648, "GeForce 9600M GS" },␊
482␉{ 0x10DE0649, "GeForce 9600M GT" },␊
483␉{ 0x10DE064A, "GeForce 9700M GT" },␊
484␉{ 0x10DE064B, "GeForce 9500M G" },␊
485␉{ 0x10DE064C, "GeForce 9650M GT" },␊
486␉// 0650 - 065F␉␉␊
487␉{ 0x10DE0651, "GeForce G 110M" },␊
488␉{ 0x10DE0652, "GeForce GT 130M" },␊
489␉{ 0x10DE0653, "GeForce GT 120M" },␊
490␉{ 0x10DE0654, "GeForce GT 220M" },␊
491␉{ 0x10DE0655, "GeForce GT 120" }, // ErmaC␊
492␉{ 0x10DE0656, "GeForce 9650 S" },␊
493␉{ 0x10DE0658, "Quadro FX 380" },␊
494␉{ 0x10DE0659, "Quadro FX 580" },␊
495␉{ 0x10DE065A, "Quadro FX 1700M" },␊
496␉{ 0x10DE065B, "GeForce 9400 GT" },␊
497␉{ 0x10DE065C, "Quadro FX 770M" },␊
498␉{ 0x10DE065F, "GeForce G210" },␊
499␉// 0660 - 066F␊
500␉// 0670 - 067F␊
501␉// 0680 - 068F␊
502␉// 0690 - 069F␊
503␉// 06A0 - 06AF␊
504␉// 06B0 - 06BF␊
505␉// 06C0 - 06CF␊
506␉{ 0x10DE06C0, "GeForce GTX 480" },␊
507␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
508␉{ 0x10DE06C4, "GeForce GTX 465" },␊
509␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
510␉{ 0x10DE06CD, "GeForce GTX 470" },␊
511␉// 06D0 - 06DF␊
512␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
513␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
514␉{ 0x10DE06D2, "Tesla M2070" },␊
515␉{ 0x10DE06D8, "Quadro 6000" },␊
516␉{ 0x10DE06D9, "Quadro 5000" },␊
517␉{ 0x10DE06DA, "Quadro 5000M" },␊
518␉{ 0x10DE06DC, "Quadro 6000" },␊
519␉{ 0x10DE06DD, "Quadro 4000" },␊
520␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
521␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
522␉{ 0x10DE06DF, "Tesla M2070-Q" }, // ErmaC␊
523␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
524␉// 06E0 - 06EF␉␊
525␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
526␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
527␉{ 0x10DE06E2, "GeForce 8400" },␊
528␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
529␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
530␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
531␉{ 0x10DE06E6, "GeForce G100" },␊
532␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
533␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
534␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
535␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
536␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
537␉{ 0x10DE06EC, "GeForce G 105M" },␊
538␉{ 0x10DE06EF, "GeForce G 103M" },␊
539␉// 06F0 - 06FF␉␊
540␉{ 0x10DE06F1, "GeForce G105M" }, // ErmaC␊
541␉{ 0x10DE06F8, "Quadro NVS 420" },␊
542␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
543␉{ 0x10DE06FA, "Quadro NVS 450" },␊
544␉{ 0x10DE06FB, "Quadro FX 370M" },␊
545␉{ 0x10DE06FD, "Quadro NVS 295" },␊
546␉{ 0x10DE06FF, "HICx16 + Graphics" }, // ErmaC␊
547␉// 0700 - 070F␊
548␉// 0710 - 071F␊
549␉// 0720 - 072F␊
550␉// 0730 - 073F␊
551␉// 0740 - 074F␊
552␉// 0750 - 075F␊
553␉// 0760 - 076F␊
554␉// 0770 - 077F␊
555␉// 0780 - 078F␊
556␉// 0790 - 079F␊
557␉// 07A0 - 07AF␊
558␉// 07B0 - 07BF␊
559␉// 07C0 - 07CF␊
560␉// 07D0 - 07DF␉␊
561␉// 07E0 - 07EF␉␉␊
562␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
563␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
564␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
565␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
566␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
567␉// 07F0 - 07FF␉␊
568␉// 0800 - 080F␊
569␉// 0810 - 081F␊
570␉// 0820 - 082F␊
571␉// 0830 - 083F␊
572␉// 0840 - 084F␊
573␉{ 0x10DE0840, "GeForce 8200M" }, // ErmaC␊
574␉{ 0x10DE0844, "GeForce 9100M G" },␊
575␉{ 0x10DE0845, "GeForce 8200M G" },␊
576␉{ 0x10DE0846, "GeForce 9200" },␊
577␉{ 0x10DE0847, "GeForce 9100" },␊
578␉{ 0x10DE0848, "GeForce 8300" },␊
579␉{ 0x10DE0849, "GeForce 8200" },␊
580␉{ 0x10DE084A, "nForce 730a" },␊
581␉{ 0x10DE084B, "GeForce 9200" },␊
582␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
583␉{ 0x10DE084D, "nForce 750a SLI" },␊
584␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
585␉// 0850 - 085F␊
586␉// 0860 - 086F␉␊
587␉{ 0x10DE0860, "GeForce 9400" },␊
588␉{ 0x10DE0861, "GeForce 9400" },␊
589␉{ 0x10DE0862, "GeForce 9400M G" },␊
590␉{ 0x10DE0863, "GeForce 9400M" },␊
591␉{ 0x10DE0864, "GeForce 9300" },␊
592␉{ 0x10DE0865, "ION" },␊
593␉{ 0x10DE0866, "GeForce 9400M G" },␊
594␉{ 0x10DE0867, "GeForce 9400" },␊
595␉{ 0x10DE0868, "nForce 760i SLI" },␊
596␉{ 0x10DE0869, "GeForce 9400" }, // ErmaC␊
597␉{ 0x10DE086A, "GeForce 9400" },␊
598␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
599␉{ 0x10DE086D, "GeForce 9200" },␊
600␉{ 0x10DE086E, "GeForce 9100M G" },␊
601␉{ 0x10DE086F, "GeForce 8200M G" },␊
602␉// 0870 - 087F␉␊
603␉{ 0x10DE0870, "GeForce 9400M" },␊
604␉{ 0x10DE0871, "GeForce 9200" },␊
605␉{ 0x10DE0872, "GeForce G102M" },␊
606␉{ 0x10DE0873, "GeForce G102M" },␊
607␉{ 0x10DE0874, "ION 9300M" },␉␊
608␉{ 0x10DE0876, "ION" },␊
609␉{ 0x10DE087A, "GeForce 9400" },␊
610␉{ 0x10DE087D, "ION 9400M" },␊
611␉{ 0x10DE087E, "ION LE" },␊
612␉{ 0x10DE087F, "ION LE" },␊
613␉// 0880 - 088F␊
614␉// 0890 - 089F␊
615␉// 08A0 - 08AF␊
616␉{ 0x10DE08A0, "GeForce 320M" }, // ErmaC␊
617␉{ 0x10DE08A4, "GeForce 320M" }, // ErmaC␊
618␉// 08B0 - 08BF␊
619␉// 08C0 - 08CF␊
620␉// 08D0 - 08DF␉␊
621␉// 08E0 - 08EF␉␉␉␊
622␉// 08F0 - 08FF␊
623␉// 0900 - 090F␊
624␉// 0910 - 091F␊
625␉// 0920 - 092F␊
626␉// 0930 - 093F␊
627␉// 0940 - 094F␊
628␉// 0950 - 095F␊
629␉// 0960 - 096F␊
630␉// 0970 - 097F␊
631␉// 0980 - 098F␊
632␉// 0990 - 099F␊
633␉// 09A0 - 09AF␊
634␉// 09B0 - 09BF␊
635␉// 09C0 - 09CF␊
636␉// 09D0 - 09DF␉␊
637␉// 09E0 - 09EF␊
638␉// 09F0 - 09FF␊
639␉// 0A00 - 0A0F␊
640␉// 0A10 - 0A1F␊
641␉// 0A20 - 0A2F␊
642␉{ 0x10DE0A20, "GeForce GT220" },␊
643␉{ 0x10DE0A22, "GeForce 315" },␊
644␉{ 0x10DE0A23, "GeForce 210" },␊
645␉{ 0x10DE0A26, "GeForce 405" }, // ErmaC␊
646␉{ 0x10DE0A27, "GeForce 405" }, // ErmaC␊
647␉{ 0x10DE0A28, "GeForce GT 230M" },␊
648␉{ 0x10DE0A29, "GeForce GT 330M" },␊
649␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
650␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
651␉{ 0x10DE0A2C, "NVS 5100M" },␊
652␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊
653␉// 0A30 - 0A3F␉␊
654␉{ 0x10DE0A34, "GeForce GT 240M" },␊
655␉{ 0x10DE0A35, "GeForce GT 325M" },␊
656␉{ 0x10DE0A38, "Quadro 400" }, // ErmaC␊
657␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
658␉// 0A40 - 0A4F␊
659␉// 0A50 - 0A5F␊
660␉// 0A60 - 0A6F␊
661␉{ 0x10DE0A60, "GeForce G210" },␊
662␉{ 0x10DE0A62, "GeForce 205" },␊
663␉{ 0x10DE0A63, "GeForce 310" },␊
664␉{ 0x10DE0A64, "ION" },␊
665␉{ 0x10DE0A65, "GeForce 210" },␊
666␉{ 0x10DE0A66, "GeForce 310" },␊
667␉{ 0x10DE0A67, "GeForce 315" },␊
668␉{ 0x10DE0A68, "GeForce G105M" },␊
669␉{ 0x10DE0A69, "GeForce G105M" },␊
670␉{ 0x10DE0A6A, "NVS 2100M" },␊
671␉{ 0x10DE0A6C, "NVS 3100M" },␊
672␉{ 0x10DE0A6E, "GeForce 305M" },␊
673␉{ 0x10DE0A6F, "ION" },␉␊
674␉// 0A70 - 0A7F␊
675␉{ 0x10DE0A70, "GeForce 310M" },␊
676␉{ 0x10DE0A71, "GeForce 305M" },␊
677␉{ 0x10DE0A72, "GeForce 310M" },␊
678␉{ 0x10DE0A73, "GeForce 305M" },␊
679␉{ 0x10DE0A74, "GeForce G210M" },␊
680␉{ 0x10DE0A75, "GeForce G310M" },␊
681␉{ 0x10DE0A76, "ION" }, // ErmaC␊
682␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
683␉{ 0x10DE0A7A, "GeForce 315M" }, // ErmaC␊
684␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
685␉// 0A80 - 0A8F␊
686␉// 0A90 - 0A9F␊
687␉// 0AA0 - 0AAF␊
688␉// 0AB0 - 0ABF␊
689␉// 0AC0 - 0ACF␊
690␉// 0AD0 - 0ADF␉␊
691␉// 0AE0 - 0AEF␊
692␉// 0AF0 - 0AFF␊
693␉// 0B00 - 0B0F␊
694␉// 0B10 - 0B1F␊
695␉// 0B20 - 0B2F␊
696␉// 0B30 - 0B3F␊
697␉// 0B40 - 0B4F␊
698␉// 0B50 - 0B5F␊
699␉// 0B60 - 0B6F␊
700␉// 0B70 - 0B7F␊
701␉// 0B80 - 0B8F␊
702␉// 0B90 - 0B9F␊
703␉// 0BA0 - 0BAF␊
704␉// 0BB0 - 0BBF␊
705␉// 0BC0 - 0BCF␊
706␉// 0BD0 - 0BDF␉␊
707␉// 0BE0 - 0BEF␊
708␉// 0BF0 - 0BFF␊
709␉// 0C00 - 0C0F␊
710␉// 0C10 - 0C1F␊
711␉// 0C20 - 0C2F␊
712␉// 0C30 - 0C3F␊
713␉// 0C40 - 0C4F␊
714␉// 0C50 - 0C5F␊
715␉// 0C60 - 0C6F␊
716␉// 0C70 - 0C7F␊
717␉// 0C80 - 0C8F␊
718␉// 0C90 - 0C9F␊
719␉// 0CA0 - 0CAF␊
720␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
721␉{ 0x10DE0CA2, "GeForce GT 320" },␊
722␉{ 0x10DE0CA3, "GeForce GT 240" },␊
723␉{ 0x10DE0CA4, "GeForce GT 340" },␊
724␉{ 0x10DE0CA5, "GeForce GT 220" }, // ErmaC␊
725␉{ 0x10DE0CA7, "GeForce GT 330" },␊
726␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
727␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
728␉{ 0x10DE0CAC, "GeForce GT 220" }, // ErmaC␊
729␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
730␉// 0CB0 - 0CBF␉␊
731␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
732␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
733␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
734␉// 0CC0 - 0CCF␊
735␉// 0CD0 - 0CDF␉␊
736␉// 0CE0 - 0CEF␊
737␉// 0CF0 - 0CFF␊
738␉// 0D00 - 0D0F␊
739␉// 0D10 - 0D1F␊
740␉// 0D20 - 0D2F␊
741␉// 0D30 - 0D3F␊
742␉// 0D40 - 0D4F␊
743␉// 0D50 - 0D5F␊
744␉// 0D60 - 0D6F␊
745␉// 0D70 - 0D7F␊
746␉// 0D80 - 0D8F␊
747␉// 0D90 - 0D9F␊
748␉// 0DA0 - 0DAF␉␊
749␉// 0DB0 - 0DBF␊
750␉// 0DC0 - 0DCF␊
751␉{ 0x10DE0DC0, "GeForce GT 440" },␊
752␉{ 0x10DE0DC1, "D12-P1-35" },␊
753␉{ 0x10DE0DC2, "D12-P1-35" },␊
754␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
755␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
756␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
757␉{ 0x10DE0DCA, "GF10x" },␊
758␉{ 0x10DE0DCD, "GeForce GT 555M" }, // ErmaC␊
759␉{ 0x10DE0DCE, "GeForce GT 555M" }, // ErmaC␊
760␉// 0DD0 - 0DDF␉␊
761␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
762␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
763␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
764␉{ 0x10DE0DD6, "GeForce GT 550M" }, // ErmaC␊
765␉{ 0x10DE0DD8, "Quadro 2000" },␊
766␉{ 0x10DE0DDA, "Quadro 2000M" }, // ErmaC␊
767␉{ 0x10DE0DDE, "GF106-ES" },␊
768␉{ 0x10DE0DDF, "GF106-INT" },␊
769␉// 0DE0 - 0DEF␉␊
770␉{ 0x10DE0DE0, "GeForce GT 440" },␊
771␉{ 0x10DE0DE1, "GeForce GT 430" },␊
772␉{ 0x10DE0DE2, "GeForce GT 420" },␊
773␉{ 0x10DE0DE5, "GeForce GT 530" },␊
774␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
775␉{ 0x10DE0DEC, "GeForce GT 525M" }, // ErmaC␊
776␉{ 0x10DE0DED, "GeForce GT 520M" }, // ErmaC␊
777␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
778␉// 0DF0 - 0DFF␉␊
779␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
780␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
781␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
782␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
783␉{ 0x10DE0DF4, "GeForce GT 540M" }, // ErmaC␊
784␉{ 0x10DE0DF5, "GeForce GT 525M" }, // ErmaC␊
785␉{ 0x10DE0DF6, "GeForce GT 550M" }, // ErmaC␊
786␉{ 0x10DE0DF7, "GeForce GT 520M" }, // ErmaC␊
787␉{ 0x10DE0DF8, "Quadro 600" },␊
788␉{ 0x10DE0DFA, "Quadro 1000M" }, // ErmaC␊
789␉{ 0x10DE0DFE, "GF108 ES" },␊
790␉{ 0x10DE0DFF, "GF108 INT" },␊
791␉// 0E00 - 0E0F␊
792␉// 0E10 - 0E1F␊
793␉// 0E20 - 0E2F␊
794␉{ 0x10DE0E21, "D12U-25" },␊
795␉{ 0x10DE0E22, "GeForce GTX 460" },␊
796␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
797␉{ 0x10DE0E24, "GeForce GTX 460" },␊
798␉{ 0x10DE0E25, "D12U-50" },␊
799␉// 0E30 - 0E3F␉␊
800␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
801␉{ 0x10DE0E31, "GeForce GTX 485M" }, // ErmaC␊
802␉{ 0x10DE0E38, "GF104GL" },␊
803␉{ 0x10DE0E3A, "Quadro 3000M" }, // ErmaC␊
804␉{ 0x10DE0E3B, "Quadro 4000M" }, // ErmaC␊
805␉{ 0x10DE0E3E, "GF104-ES" },␊
806␉{ 0x10DE0E3F, "GF104-INT" },␊
807␉// 0E40 - 0E4F␉␊
808␉// 0E50 - 0E5F␊
809␉// 0E60 - 0E6F␊
810␉// 0E70 - 0E7F␊
811␉// 0E80 - 0E8F␊
812␉// 0E90 - 0E9F␊
813␉// 0EA0 - 0EAF␊
814␉// 0EB0 - 0EBF␊
815␉// 0EC0 - 0ECF␊
816␉// 0ED0 - 0EDF␉␊
817␉// 0EE0 - 0EEF␊
818␉// 0EF0 - 0EFF␊
819␉// 0F00 - 0F0F␊
820␉// 0F10 - 0F1F␊
821␉// 0F20 - 0F2F␊
822␉// 0F30 - 0F3F␊
823␉// 0F40 - 0F4F␊
824␉// 0F50 - 0F5F␊
825␉// 0F60 - 0F6F␊
826␉// 0F70 - 0F7F␊
827␉// 0F80 - 0F8F␊
828␉// 0F90 - 0F9F␊
829␉// 0FA0 - 0FAF␊
830␉// 0FB0 - 0FBF␊
831␉// 0FC0 - 0FCF␊
832␉// 0FD0 - 0FDF␊
833␉// 0FE0 - 0FEF␊
834␉// 0FF0 - 0FFF␊
835␉// 1000 - 100F␊
836␉// 1010 - 101F␊
837␉// 1020 - 102F␊
838␉// 1030 - 103F␊
839␉// 1040 - 104F␊
840␉{ 0x10DE1040, "GeForce GT 520" },␊
841␉// 1050 - 105F␊
842␉{ 0x10DE1050, "GeForce GT 520M" },␊
843␉{ 0x10DE1054, "GeForce GT 410M" }, // ErmaC␊
844␉{ 0x10DE1056, "NVS 4200M" }, // ErmaC␊
845␉{ 0x10DE1057, "NVS 4200M" }, // ErmaC␊
846␉// 1060 - 106F␊
847␉// 1070 - 107F␊
848␉{ 0x10DE107F, "NVIDIA GF119-ES" }, // ErmaC␊
849␉// 1080 - 108F␊
850␉{ 0x10DE1080, "GeForce GTX 580" },␊
851␉{ 0x10DE1081, "GeForce GTX 570" },␊
852␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
853␉{ 0x10DE1083, "D13U" },␊
854␉{ 0x10DE1084, "GeForce GTX 560" }, // ErmaC␊
855␉{ 0x10DE1086, "GeForce GTX 570" }, // ErmaC␊
856␉{ 0x10DE1087, "GeForce GTX 560 Ti-448" }, // ErmaC␊
857␉{ 0x10DE1088, "GeForce GTX 590" },␊
858␉{ 0x10DE1089, "GeForce GTX 580" }, // ErmaC␊
859␉{ 0x10DE108B, "GeForce GTX 590" }, // ErmaC␊
860␉// 1090 - 109F␉␊
861␉{ 0x10DE1091, "Tesla M2090" }, // ErmaC␊
862␉{ 0x10DE1098, "D13U" },␊
863␉{ 0x10DE109A, "Quadro 5010M" }, // ErmaC␊
864␉{ 0x10DE109B, "Quadro 7000" }, // ErmaC␊
865␉// 10A0 - 10AF␊
866␉// 10B0 - 10BF␊
867␉// 10C0 - 10CF␊
868␉{ 0x10DE10C0, "GeForce 9300 GS" }, // ErmaC␊
869␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
870␉{ 0x10DE10C5, "GeForce 405" }, // ErmaC␊
871␉// 10D0 - 10DF␊
872␉{ 0x10DE10D8, "NVS 300" }, // ErmaC␊
873␉// 1200 - ␊
874␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
875␉{ 0x10DE1201, "GeForce GTX 560" }, // ErmaC␊
876␉{ 0x10DE1241, "GeForce GT 545" }, // ErmaC␊
877␉{ 0x10DE1243, "GeForce GT 545" }, // ErmaC␊
878␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
879␉{ 0x10DE1245, "GeForce GTS 450" },␊
880␉{ 0x10DE1251, "GeForce GTX 560M" }, // ErmaC␊
881};␊
882␊
883static uint16_t swap16(uint16_t x)␊
884{␊
885␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
886}␊
887␊
888static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
889{␊
890␉uint8_t ret[2];␊
891␊
892␉ret[0] = ptr[offset+1];␊
893␉ret[1] = ptr[offset];␊
894␊
895␉return *((uint16_t*)&ret);␊
896}␊
897␊
898#if 0␊
899static uint32_t swap32(uint32_t x)␊
900{␊
901␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
902}␊
903␊
904static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
905{ ␊
906␉return ptr[offset];␊
907}␊
908␊
909static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
910{␊
911␉uint8_t ret[4];␊
912␊
913␉ret[0] = ptr[offset+3];␊
914␉ret[1] = ptr[offset+2];␊
915␉ret[2] = ptr[offset+1];␊
916␉ret[3] = ptr[offset];␊
917␊
918␉return *((uint32_t*)&ret);␊
919}␊
920#endif␊
921␊
922static int patch_nvidia_rom(uint8_t *rom)␊
923{␊
924␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
925␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
926␉␉return PATCH_ROM_FAILED;␊
927␉}␊
928␉␊
929␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
930␊
931␉if (!dcbptr) {␊
932␉␉printf("no dcb table found\n");␊
933␉␉return PATCH_ROM_FAILED;␊
934␉}␊
935//␉else␊
936//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
937␉ ␊
938␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
939␉uint8_t dcbtable_version = dcbtable[0];␊
940␉uint8_t headerlength␉ = 0;␊
941␉uint8_t numentries␉␉ = 0;␊
942␉uint8_t recordlength␉ = 0;␊
943␉␊
944␉if (dcbtable_version >= 0x20)␊
945␉{␊
946␉␉uint32_t sig;␊
947␉␉␊
948␉␉if (dcbtable_version >= 0x30)␊
949␉␉{␊
950␉␉␉headerlength = dcbtable[1];␊
951␉␉␉numentries␉ = dcbtable[2];␊
952␉␉␉recordlength = dcbtable[3];␊
953␊
954␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
955␉␉}␊
956␉␉else␊
957␉␉{␊
958␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
959␉␉␉headerlength = 8;␊
960␉␉}␊
961␉␉␊
962␉␉if (sig != 0x4edcbdcb)␊
963␉␉{␊
964␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
965␉␉␉return PATCH_ROM_FAILED;␊
966␉␉}␊
967␉}␊
968␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
969␉{␊
970␉␉char sig[8] = { 0 };␊
971␉␉␊
972␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
973␉␉recordlength = 10;␊
974␉␉␊
975␉␉if (strcmp(sig, "DEV_REC"))␊
976␉␉{␊
977␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
978␉␉␉return PATCH_ROM_FAILED;␊
979␉␉}␊
980␉}␊
981␉else␊
982␉{␊
983␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
984␉␉return PATCH_ROM_FAILED;␊
985␉}␊
986␉␊
987␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
988␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
989␉␊
990␉uint8_t num_outputs = 0, i = 0;␊
991␉␊
992␉struct dcbentry␊
993␉{␊
994␉␉uint8_t type;␊
995␉␉uint8_t index;␊
996␉␉uint8_t *heads;␊
997␉} entries[numentries];␊
998␉␊
999␉for (i = 0; i < numentries; i++)␊
1000␉{␊
1001␉␉uint32_t connection;␊
1002␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
1003␊
1004␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1005␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1006␉␉␉continue;␊
1007␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1008␉␉␉continue;␊
1009␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1010␉␉␉continue;␊
1011␉␉␊
1012␉␉entries[num_outputs].type = connection & 0xf;␊
1013␉␉entries[num_outputs].index = num_outputs;␊
1014␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1015␉}␊
1016␉␊
1017␉int has_lvds = false;␊
1018␉uint8_t channel1 = 0, channel2 = 0;␊
1019␉␊
1020␉for (i = 0; i < num_outputs; i++)␊
1021␉{␊
1022␉␉if (entries[i].type == 3)␊
1023␉␉{␊
1024␉␉␉has_lvds = true;␊
1025␉␉␉//printf("found LVDS\n");␊
1026␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1027␉␉␉entries[i].type = TYPE_GROUPED;␊
1028␉␉}␊
1029␉}␊
1030␉␊
1031␉// if we have a LVDS output, we group the rest to the second channel␊
1032␉if (has_lvds)␊
1033␉{␊
1034␉␉for (i = 0; i < num_outputs; i++)␊
1035␉␉{␊
1036␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1037␉␉␉␉continue;␊
1038␉␉␉␊
1039␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1040␉␉␉entries[i].type = TYPE_GROUPED;␊
1041␉␉}␊
1042␉}␊
1043␉else␊
1044␉{␊
1045␉␉int x;␊
1046␉␉// we loop twice as we need to generate two channels␊
1047␉␉for (x = 0; x <= 1; x++)␊
1048␉␉{␊
1049␉␉␉for (i=0; i<num_outputs; i++)␊
1050␉␉␉{␊
1051␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1052␉␉␉␉␉continue;␊
1053␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1054␉␉␉␉// we always group ANALOG and TMDS␊
1055␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1056␉␉␉␉if (i && entries[i].type == 0x2)␊
1057␉␉␉␉{␊
1058␉␉␉␉␉switch (x)␊
1059␉␉␉␉␉{␊
1060␉␉␉␉␉␉case 0:␊
1061␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1062␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1063␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1064␉␉␉␉␉␉␉␊
1065␉␉␉␉␉␉␉if ( entries[i-1].type == 0x0 )␊
1066␉␉␉␉␉␉␉{␊
1067␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1068␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1069␉␉␉␉␉␉␉}␊
1070␉␉␉␉␉␉␉// group TV as well if there is one␊
1071␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1072␉␉␉␉␉␉␉{␊
1073␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1074␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1075␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1076␉␉␉␉␉␉␉}␊
1077␉␉␉␉␉␉␉break;␊
1078␉␉␉␉␉␉␊
1079␉␉␉␉␉␉case 1:␊
1080␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1081␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1082␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1083␉␉␉␉␉␉␉␊
1084␉␉␉␉␉␉␉if ( entries[i - 1].type == 0x0 )␊
1085␉␉␉␉␉␉␉{␊
1086␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1087␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1088␉␉␉␉␉␉␉}␊
1089␉␉␉␉␉␉␉// group TV as well if there is one␊
1090␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1091␉␉␉␉␉␉␉{␊
1092␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1093␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1094␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1095␉␉␉␉␉␉␉}␊
1096␉␉␉␉␉␉␉break;␊
1097␉␉␉␉␉}␊
1098␉␉␉␉␉break;␊
1099␉␉␉␉}␊
1100␉␉␉}␊
1101␉␉}␊
1102␉}␊
1103␉␊
1104␉// if we have left ungrouped outputs merge them to the empty channel␊
1105␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1106␉togroup = &channel2;␊
1107␉␊
1108␉for (i = 0; i < num_outputs; i++)␊
1109␉{␊
1110␉␉if (entries[i].type != TYPE_GROUPED)␊
1111␉␉{␊
1112␉␉␉//printf("%d not grouped\n", i);␊
1113␉␉␉if (togroup)␊
1114␉␉␉{␊
1115␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1116␉␉␉}␊
1117␉␉␉entries[i].type = TYPE_GROUPED;␊
1118␉␉}␊
1119␉}␊
1120␉␊
1121␉if (channel1 > channel2)␊
1122␉{␊
1123␉␉uint8_t buff = channel1;␊
1124␉␉channel1 = channel2;␊
1125␉␉channel2 = buff;␊
1126␉}␊
1127␉␊
1128␉default_NVCAP[6] = channel1;␊
1129␉default_NVCAP[8] = channel2;␊
1130␉␊
1131␉// patching HEADS␊
1132␉for (i = 0; i < num_outputs; i++)␊
1133␉{␊
1134␉␉if (channel1 & (1 << i))␊
1135␉␉{␊
1136␉␉␉*entries[i].heads = 1;␊
1137␉␉}␊
1138␉␉else if(channel2 & (1 << i))␊
1139␉␉{␊
1140␉␉␉*entries[i].heads = 2;␊
1141␉␉}␊
1142␉}␊
1143␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1144}␊
1145␊
1146static char *get_nvidia_model(uint32_t id)␊
1147{␊
1148␉int i;␊
1149␉␊
1150␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1151␉␉if (NVKnownChipsets[i].device == id)␊
1152␉␉{␊
1153␉␉␉return NVKnownChipsets[i].name;␊
1154␉␉}␊
1155␉}␊
1156␉return NVKnownChipsets[0].name;␊
1157}␊
1158␊
1159static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1160{␊
1161␉int fd;␊
1162␉int size;␊
1163␉␊
1164␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1165␉{␊
1166␉␉return 0;␊
1167␉}␊
1168␉␊
1169␉size = file_size(fd);␊
1170␉␊
1171␉if (size > bufsize)␊
1172␉{␊
1173␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1174␉␉␉␉filename, bufsize);␊
1175␉␉size = bufsize;␊
1176␉}␊
1177␉size = read(fd, (char *)buf, size);␊
1178␉close(fd);␊
1179␉␊
1180␉return size > 0 ? size : 0;␊
1181}␊
1182␊
1183static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1184{␊
1185␉char tmp[16];␊
1186␉␊
1187␉if (!device)␊
1188␉␉return 0;␊
1189␉␊
1190␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1191␉␉return 0;␊
1192␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1193␉␉return 0;␊
1194␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1195␉␉return 0;␊
1196␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1197␉␉return 0;␊
1198␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1199␉␉return 0;␊
1200␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1201␉␉return 0;␊
1202␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1203␉␉return 0;␊
1204␉␊
1205␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1206␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1207␉sprintf(tmp, "Slot-%x",devices_number);␊
1208␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1209␉devices_number++;␊
1210␉␊
1211␉return 1;␊
1212}␊
1213␊
1214int hex2bin(const char *hex, uint8_t *bin, int len)␊
1215{␊
1216␉char␉*p;␊
1217␉int␉␉i;␊
1218␉char␉buf[3];␊
1219␉␊
1220␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1221␉␉printf("[ERROR] bin2hex input error\n");␊
1222␉␉return -1;␊
1223␉}␊
1224␉␊
1225␉buf[2] = '\0';␊
1226␉p = (char *) hex;␊
1227␉␊
1228␉for (i = 0; i < len; i++)␊
1229␉{␊
1230␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1231␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1232␉␉␉return -2;␊
1233␉␉}␊
1234␉␉buf[0] = *p++;␊
1235␉␉buf[1] = *p++;␊
1236␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1237␉}␊
1238␉return 0;␊
1239}␊
1240␊
1241unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1242{␊
1243␉unsigned long long vram_size = 0;␊
1244␉␊
1245␉if (nvCardType < NV_ARCH_50)␊
1246␉{␊
1247␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1248␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1249␉}␊
1250␉else if (nvCardType < NV_ARCH_C0)␊
1251␉{␊
1252␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1253␉␉vram_size |= (vram_size & 0xff) << 32;␊
1254␉␉vram_size &= 0xffffffff00ll;␊
1255␉}␊
1256␉else // >= NV_ARCH_C0␊
1257␉{␊
1258␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1259␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1260␉}␊
1261␉␊
1262␉// Workaround for 9600M GT, GT 420/430/440 & GT 525M␊
1263␉switch (nvda_dev->device_id)␊
1264␉{␊
1265␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT␊
1266␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
1267␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1268␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1269␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M␊
1270␉␉default: break;␊
1271␉}␊
1272␉␊
1273␉return vram_size;␊
1274}␊
1275␊
1276bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1277{␊
1278␉struct DevPropDevice␉*device;␊
1279␉char␉␉␉␉␉*devicepath;␊
1280␉option_rom_pci_header_t *rom_pci_header;␊
1281␉volatile uint8_t␉␉*regs;␊
1282␉uint8_t␉␉␉␉␉*rom;␊
1283␉uint8_t␉␉␉␉␉*nvRom;␊
1284␉uint8_t␉␉␉␉␉nvCardType;␊
1285␉unsigned long long␉␉videoRam;␊
1286␉uint32_t␉␉␉␉nvBiosOveride;␊
1287␉uint32_t␉␉␉␉bar[7];␊
1288␉uint32_t␉␉␉␉boot_display;␊
1289␉int␉␉␉␉␉␉nvPatch;␊
1290␉int␉␉␉␉␉␉len;␊
1291␉char␉␉␉␉␉biosVersion[32];␊
1292␉char␉␉␉␉␉nvFilename[32];␊
1293␉char␉␉␉␉␉kNVCAP[12];␊
1294␉char␉␉␉␉␉*model;␊
1295␉const char␉␉␉␉*value;␊
1296␉bool␉␉␉␉␉doit;␊
1297␉␊
1298␉devicepath = get_pci_dev_path(nvda_dev);␊
1299␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1300␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1301␉␊
1302␉// get card type␊
1303␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1304␉␊
1305␉// Amount of VRAM in kilobytes␊
1306␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1307␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1308␉␊
1309␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
1310␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
1311␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1312␉␉␉devicepath);␊
1313␉␊
1314␉rom = malloc(NVIDIA_ROM_SIZE);␊
1315␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1316␉␉␉(uint16_t)nvda_dev->device_id);␊
1317␉␊
1318␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1319␉{␊
1320␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1321␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1322␉␉␊
1323␉␉if (nvBiosOveride > 0)␊
1324␉␉{␊
1325␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1326␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1327␉␉}␊
1328␉␉else␊
1329␉␉{␊
1330␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1331␉␉␉return false;␊
1332␉␉}␊
1333␉}␊
1334␉else␊
1335␉{␊
1336␉␉// Otherwise read bios from card␊
1337␉␉nvBiosOveride = 0;␊
1338␉␉␊
1339␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1340␉␉␊
1341␉␉// PRAMIN first␊
1342␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1343␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1344␉␉␊
1345␉␉// Valid Signature ?␊
1346␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1347␉␉{␊
1348␉␉␉// PROM next␊
1349␉␉␉// Enable PROM access␊
1350␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1351␉␉␉␊
1352␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1353␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1354␉␉␉␊
1355␉␉␉// disable PROM access␊
1356␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1357␉␉␉␊
1358␉␉␉// Valid Signature ?␊
1359␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1360␉␉␉{␊
1361␉␉␉␉// 0xC0000 last␊
1362␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1363␉␉␉␉␊
1364␉␉␉␉// Valid Signature ?␊
1365␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1366␉␉␉␉{␊
1367␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1368␉␉␉␉␉return false;␊
1369␉␉␉␉}␊
1370␉␉␉␉else␊
1371␉␉␉␉{␊
1372␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1373␉␉␉␉}␊
1374␉␉␉}␊
1375␉␉␉else␊
1376␉␉␉{␊
1377␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1378␉␉␉}␊
1379␉␉}␊
1380␉␉else␊
1381␉␉{␊
1382␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1383␉␉}␊
1384␉}␊
1385␉␊
1386␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1387␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1388␉␉//return false;␊
1389␉}␊
1390␉␊
1391␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1392␉␊
1393␉// check for 'PCIR' sig␊
1394␉if (rom_pci_header->signature == 0x50434952)␊
1395␉{␊
1396␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1397␉␉{␊
1398␉␉␉// Get Model from the OpROM␊
1399␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1400␉␉}␊
1401␉␉else␊
1402␉␉{␊
1403␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1404␉␉}␊
1405␉}␊
1406␉␊
1407␉if (!string) {␊
1408␉␉string = devprop_create_string();␊
1409␉}␊
1410␉device = devprop_add_device(string, devicepath);␊
1411␉␊
1412␉/* FIXME: for primary graphics card only */␊
1413␉boot_display = 1;␊
1414␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1415␉␊
1416␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1417␉␉uint8_t built_in = 0x01;␊
1418␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1419␉}␊
1420␉␊
1421␉// get bios version␊
1422␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1423␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1424␉␊
1425␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1426␉␊
1427␉int i, version_start;␊
1428␉int crlf_count = 0;␊
1429␉␊
1430␉// only search the first 384 bytes␊
1431␉for (i = 0; i < 0x180; i++)␊
1432␉{␊
1433␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1434␉␉{␊
1435␉␉␉crlf_count++;␊
1436␉␉␉// second 0x0D0A was found, extract bios version␊
1437␉␉␉if (crlf_count == 2)␊
1438␉␉␉{␊
1439␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1440␉␉␉␉␊
1441␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1442␉␉␉␉{␊
1443␉␉␉␉␉// find start␊
1444␉␉␉␉␉if (rom[version_start] == 0x00)␊
1445␉␉␉␉␉{␊
1446␉␉␉␉␉␉version_start++;␊
1447␉␉␉␉␉␉␊
1448␉␉␉␉␉␉// strip "Version "␊
1449␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1450␉␉␉␉␉␉{␊
1451␉␉␉␉␉␉␉version_start += 8;␊
1452␉␉␉␉␉␉}␊
1453␉␉␉␉␉␉␊
1454␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1455␉␉␉␉␉␉break;␊
1456␉␉␉␉␉}␊
1457␉␉␉␉}␊
1458␉␉␉␉break;␊
1459␉␉␉}␊
1460␉␉}␊
1461␉}␊
1462␉␊
1463␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1464␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1465␉␊
1466␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1467␉{␊
1468␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1469␉␉␊
1470␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1471␉␉{␊
1472␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1473␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1474␉␉}␊
1475␉}␊
1476␉␊
1477␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1478␉{␊
1479␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1480␉␉␊
1481␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1482␉␉{␊
1483␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1484␉␉␉␊
1485␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1486␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1487␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1488␉␉}␊
1489␉}␊
1490␉␊
1491␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1492␉{␊
1493␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1494␉␉␊
1495␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1496␉␉{␊
1497␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1498␉␉␉␊
1499␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1500␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1501␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1502␉␉}␊
1503␉}␊
1504␉␊
1505#if DEBUG_NVCAP␊
1506␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1507␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1508␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1509␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1510␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1511␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1512#endif␊
1513␉␊
1514␉devprop_add_nvidia_template(device);␊
1515␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1516␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1517␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1518␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1519␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1520␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1521␉␊
1522␉//add HDMI Audio back to nvidia␊
1523␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1524//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1525//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1526␉//end Nvidia HDMI Audio␊
1527␉␊
1528␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1529␉{␊
1530␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1531␉}␊
1532␉␊
1533␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1534␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1535␉stringlength = string->length;␊
1536␉␊
1537␉return true;␊
1538}␊
1539

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