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Root/branches/valv/i386/libsaio/nvidia.c

1/*␊
2 * NVidia injector␊
3 *␊
4 * Copyright (C) 2009 Jasmin Fazlic, iNDi␊
5 *␊
6 * NVidia injector is free software: you can redistribute it and/or modify␊
7 * it under the terms of the GNU General Public License as published by␊
8 * the Free Software Foundation, either version 3 of the License, or␊
9 * (at your option) any later version.␊
10 *␊
11 * NVidia driver and injector is distributed in the hope that it will be useful,␊
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 * GNU General Public License for more details.␊
15 *␊
16 * You should have received a copy of the GNU General Public License␊
17 * along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "libsaio.h"␊
52#include "boot.h"␊
53#include "bootstruct.h"␊
54#include "pci.h"␊
55#include "platform.h"␊
56#include "device_inject.h"␊
57#include "nvidia.h"␊
58␊
59#ifndef DEBUG_NVIDIA␊
60#define DEBUG_NVIDIA 0␊
61#endif␊
62␊
63#if DEBUG_NVIDIA␊
64#define DBG(x...)␉printf(x)␊
65#else␊
66#define DBG(x...)␊
67#endif␊
68␊
69#define NVIDIA_ROM_SIZE 0x10000␊
70#define PATCH_ROM_SUCCESS 1␊
71#define PATCH_ROM_SUCCESS_HAS_LVDS 2␊
72#define PATCH_ROM_FAILED 0␊
73#define MAX_NUM_DCB_ENTRIES 16␊
74␊
75#define TYPE_GROUPED 0xff␊
76␊
77extern uint32_t devices_number;␊
78␊
79const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac" };␊
80const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac" };␊
81const char *nvidia_device_type_0[]␉=␉{ "@0,device_type",␉"display" };␊
82const char *nvidia_device_type_1[]␉=␉{ "@1,device_type",␉"display" };␊
83const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent" };␊
84const char *nvidia_name_0[]␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
85const char *nvidia_name_1[]␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
86const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name",␉"Slot-1" };␊
87␊
88static uint8_t default_NVCAP[]= {␊
89␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
90␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
91␉0x00, 0x00, 0x00, 0x00␊
92};␊
93␊
94#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
95␊
96static struct nv_chipsets_t NVKnownChipsets[] = {␊
97␉{ 0x00000000, "Unknown" },␊
98␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
99␉{ 0x10DE0041, "GeForce 6800" },␊
100␉{ 0x10DE0042, "GeForce 6800 LE" },␊
101␉{ 0x10DE0043, "GeForce 6800 XE" },␊
102␉{ 0x10DE0044, "GeForce 6800 XT" },␊
103␉{ 0x10DE0045, "GeForce 6800 GT" },␊
104␉{ 0x10DE0046, "GeForce 6800 GT" },␊
105␉{ 0x10DE0047, "GeForce 6800 GS" },␊
106␉{ 0x10DE0048, "GeForce 6800 XT" },␊
107␉{ 0x10DE004D, "Quadro FX 3400" },␊
108␉{ 0x10DE004E, "Quadro FX 4000" },␊
109␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
110␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
111␉{ 0x10DE0092, "GeForce 7800 GT" },␊
112␉{ 0x10DE0093, "GeForce 7800 GS" },␊
113␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
114␉{ 0x10DE0098, "GeForce Go 7800" },␊
115␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
116␉{ 0x10DE009D, "Quadro FX 4500" },␊
117␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
118␉{ 0x10DE00C1, "GeForce 6800" },␊
119␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
120␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
121␉{ 0x10DE00C8, "GeForce Go 6800" },␊
122␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
123␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
124␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
125␉{ 0x10DE00CE, "Quadro FX 1400" },␊
126␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
127␉{ 0x10DE00F2, "GeForce 6600" },␊
128␉{ 0x10DE00F3, "GeForce 6200" },␊
129␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
130␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
131␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
132␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
133␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
134␉{ 0x10DE0140, "GeForce 6600 GT" },␊
135␉{ 0x10DE0141, "GeForce 6600" },␊
136␉{ 0x10DE0142, "GeForce 6600 LE" },␊
137␉{ 0x10DE0143, "GeForce 6600 VE" },␊
138␉{ 0x10DE0144, "GeForce Go 6600" },␊
139␉{ 0x10DE0145, "GeForce 6610 XL" },␊
140␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
141␉{ 0x10DE0147, "GeForce 6700 XL" },␊
142␉{ 0x10DE0148, "GeForce Go 6600" },␊
143␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
144␉{ 0x10DE014A, "Quadro NVS 440" },␊
145␉{ 0x10DE014C, "Quadro FX 550" },␊
146␉{ 0x10DE014D, "Quadro FX 550" },␊
147␉{ 0x10DE014E, "Quadro FX 540" },␊
148␉{ 0x10DE014F, "GeForce 6200" },␊
149␉{ 0x10DE0160, "GeForce 6500" },␊
150␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
151␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
152␉{ 0x10DE0163, "GeForce 6200 LE" },␊
153␉{ 0x10DE0164, "GeForce Go 6200" },␊
154␉{ 0x10DE0165, "Quadro NVS 285" },␊
155␉{ 0x10DE0166, "GeForce Go 6400" },␊
156␉{ 0x10DE0167, "GeForce Go 6200" },␊
157␉{ 0x10DE0168, "GeForce Go 6400" },␊
158␉{ 0x10DE0169, "GeForce 6250" },␊
159␉{ 0x10DE016A, "GeForce 7100 GS" },␊
160␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
161␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
162␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
163␉{ 0x10DE0197, "Tesla C870" },␊
164␉{ 0x10DE019D, "Quadro FX 5600" },␊
165␉{ 0x10DE019E, "Quadro FX 4600" },␊
166␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
167␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
168␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
169␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
170␉{ 0x10DE01D6, "GeForce Go 7200" },␊
171␉{ 0x10DE01D7, "GeForce Go 7300" },␊
172␉{ 0x10DE01D8, "GeForce Go 7400" },␊
173␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
174␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
175␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
176␉{ 0x10DE01DC, "Quadro FX 350M" },␊
177␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
178␉{ 0x10DE01DE, "Quadro FX 350" },␊
179␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
180␉{ 0x10DE0211, "GeForce 6800" },␊
181␉{ 0x10DE0212, "GeForce 6800 LE" },␊
182␉{ 0x10DE0215, "GeForce 6800 GT" },␊
183␉{ 0x10DE0218, "GeForce 6800 XT" },␊
184␉{ 0x10DE0221, "GeForce 6200" },␊
185␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
186␉{ 0x10DE0240, "GeForce 6150" },␊
187␉{ 0x10DE0241, "GeForce 6150 LE" },␊
188␉{ 0x10DE0242, "GeForce 6100" },␊
189␉{ 0x10DE0244, "GeForce Go 6150" },␊
190␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
191␉{ 0x10DE0247, "GeForce Go 6100" },␊
192␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
193␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
194␉{ 0x10DE0292, "GeForce 7900 GS" },␊
195␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
196␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
197␉{ 0x10DE0295, "GeForce 7950 GT" },␊
198␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
199␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
200␉{ 0x10DE029A, "Quadro FX 2500M" },␊
201␉{ 0x10DE029B, "Quadro FX 1500M" },␊
202␉{ 0x10DE029C, "Quadro FX 5500" },␊
203␉{ 0x10DE029D, "Quadro FX 3500" },␊
204␉{ 0x10DE029E, "Quadro FX 1500" },␊
205␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
206␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
207␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
208␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
209␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
210␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
211␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
212␉{ 0x10DE0302, "GeForce FX 5800" },␊
213␉{ 0x10DE0308, "Quadro FX 2000" },␊
214␉{ 0x10DE0309, "Quadro FX 1000" },␊
215␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
216␉{ 0x10DE0312, "GeForce FX 5600" },␊
217␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
218␉{ 0x10DE031A, "GeForce FX Go5600" },␊
219␉{ 0x10DE031B, "GeForce FX Go5650" },␊
220␉{ 0x10DE031C, "Quadro FX Go700" },␊
221␉{ 0x10DE0324, "GeForce FX Go5200" },␊
222␉{ 0x10DE0325, "GeForce FX Go5250" },␊
223␉{ 0x10DE0326, "GeForce FX 5500" },␊
224␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
225␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
226␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
227␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
228␉{ 0x10DE032D, "GeForce FX Go5100" },␊
229␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
230␉{ 0x10DE0331, "GeForce FX 5900" },␊
231␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
232␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
233␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
234␉{ 0x10DE0338, "Quadro FX 3000" },␊
235␉{ 0x10DE033F, "Quadro FX 700" },␊
236␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
237␉{ 0x10DE0342, "GeForce FX 5700" },␊
238␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
239␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
240␉{ 0x10DE0347, "GeForce FX Go5700" },␊
241␉{ 0x10DE0348, "GeForce FX Go5700" },␊
242␉{ 0x10DE034C, "Quadro FX Go1000" },␊
243␉{ 0x10DE034E, "Quadro FX 1100" },␊
244␉{ 0x10DE038B, "GeForce 7650 GS" },␊
245␉{ 0x10DE0390, "GeForce 7650 GS" },␊
246␉{ 0x10DE0391, "GeForce 7600 GT" },␊
247␉{ 0x10DE0392, "GeForce 7600 GS" },␊
248␉{ 0x10DE0393, "GeForce 7300 GT" },␊
249␉{ 0x10DE0394, "GeForce 7600 LE" },␊
250␉{ 0x10DE0395, "GeForce 7300 GT" },␊
251␉{ 0x10DE0397, "GeForce Go 7700" },␊
252␉{ 0x10DE0398, "GeForce Go 7600" },␊
253␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
254␉{ 0x10DE039A, "Quadro NVS 300M" },␊
255␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
256␉{ 0x10DE039C, "Quadro FX 550M" },␊
257␉{ 0x10DE039E, "Quadro FX 560" },␊
258␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
259␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
260␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
261␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
262␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
263␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
264␉{ 0x10DE0401, "GeForce 8600 GT" },␊
265␉{ 0x10DE0402, "GeForce 8600 GT" },␊
266␉{ 0x10DE0403, "GeForce 8600 GS" },␊
267␉{ 0x10DE0404, "GeForce 8400 GS" },␊
268␉{ 0x10DE0405, "GeForce 9500M GS" },␊
269␉{ 0x10DE0406, "GeForce 8300 GS" },␊
270␉{ 0x10DE0407, "GeForce 8600M GT" },␊
271␉{ 0x10DE0408, "GeForce 9650M GS" },␊
272␉{ 0x10DE0409, "GeForce 8700M GT" },␊
273␉{ 0x10DE040A, "Quadro FX 370" },␊
274␉{ 0x10DE040B, "Quadro NVS 320M" },␊
275␉{ 0x10DE040C, "Quadro FX 570M" },␊
276␉{ 0x10DE040D, "Quadro FX 1600M" },␊
277␉{ 0x10DE040E, "Quadro FX 570" },␊
278␉{ 0x10DE040F, "Quadro FX 1700" },␊
279␉{ 0x10DE0410, "GeForce GT 330" },␊
280␉{ 0x10DE0420, "GeForce 8400 SE" },␊
281␉{ 0x10DE0421, "GeForce 8500 GT" },␊
282␉{ 0x10DE0422, "GeForce 8400 GS" },␊
283␉{ 0x10DE0423, "GeForce 8300 GS" },␊
284␉{ 0x10DE0424, "GeForce 8400 GS" },␊
285␉{ 0x10DE0425, "GeForce 8600M GS" },␊
286␉{ 0x10DE0426, "GeForce 8400M GT" },␊
287␉{ 0x10DE0427, "GeForce 8400M GS" },␊
288␉{ 0x10DE0428, "GeForce 8400M G" },␊
289␉{ 0x10DE0429, "Quadro NVS 140M" },␊
290␉{ 0x10DE042A, "Quadro NVS 130M" },␊
291␉{ 0x10DE042B, "Quadro NVS 135M" },␊
292␉{ 0x10DE042C, "GeForce 9400 GT" },␊
293␉{ 0x10DE042D, "Quadro FX 360M" },␊
294␉{ 0x10DE042E, "GeForce 9300M G" },␊
295␉{ 0x10DE042F, "Quadro NVS 290" },␊
296␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
297␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
298␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
299␉{ 0x10DE05E0, "GeForce GTX 295" },␊
300␉{ 0x10DE05E1, "GeForce GTX 280" },␊
301␉{ 0x10DE05E2, "GeForce GTX 260" },␊
302␉{ 0x10DE05E3, "GeForce GTX 285" },␊
303␉{ 0x10DE05E6, "GeForce GTX 275" },␊
304␉{ 0x10DE05EA, "GeForce GTX 260" },␊
305␉{ 0x10DE05EB, "GeForce GTX 295" },␊
306␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
307␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
308␉{ 0x10DE05F9, "Quadro CX" },␊
309␉{ 0x10DE05FD, "Quadro FX 5800" },␊
310␉{ 0x10DE05FE, "Quadro FX 4800" },␊
311␉{ 0x10DE05FF, "Quadro FX 3800" },␊
312 ␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
313␉{ 0x10DE0601, "GeForce 9800 GT" },␊
314␉{ 0x10DE0602, "GeForce 8800 GT" },␊
315␉{ 0x10DE0603, "GeForce GT 230" },␊
316␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
317␉{ 0x10DE0605, "GeForce 9800 GT" },␊
318␉{ 0x10DE0606, "GeForce 8800 GS" },␊
319␉{ 0x10DE0607, "GeForce GTS 240" },␊
320␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
321␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
322␉{ 0x10DE060A, "GeForce GTX 280M" },␊
323␉{ 0x10DE060B, "GeForce 9800M GT" },␊
324␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
325␉{ 0x10DE060D, "GeForce 8800 GS" },␊
326␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
327␉{ 0x10DE0611, "GeForce 8800 GT" },␊
328␉{ 0x10DE0612, "GeForce 9800 GTX / GeForce 9800 GTX+" },␊
329␉{ 0x10DE0614, "GeForce 9800 GT" },␊
330␉{ 0x10DE0615, "GeForce GTS 250" },␊
331␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
332␉{ 0x10DE0618, "GeForce GTX 260M" },␉␊
333␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
334␉{ 0x10DE061A, "Quadro FX 3700" },␊
335␉{ 0x10DE061B, "Quadro VX 200" },␊
336␉{ 0x10DE061C, "Quadro FX 3600M" },␊
337␉{ 0x10DE061D, "Quadro FX 2800M" },␊
338␉{ 0x10DE061F, "Quadro FX 3800M" },␊
339␉{ 0x10DE0622, "GeForce 9600 GT" },␊
340␉{ 0x10DE0623, "GeForce 9600 GS" },␊
341␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
342␉{ 0x10DE0626, "GeForce GT 130" },␊
343␉{ 0x10DE0627, "GeForce GT 140" },␊
344␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
345␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
346␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
347␉{ 0x10DE062D, "GeForce 9600 GT" },␊
348␉{ 0x10DE062E, "GeForce 9600 GT" },␊
349␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
350␉{ 0x10DE0637, "GeForce 9600 GT" },␊
351␉{ 0x10DE0638, "Quadro FX 1800" },␊
352␉{ 0x10DE0640, "GeForce 9500 GT" },␊
353␉{ 0x10DE0641, "GeForce 9400 GT" },␊
354␉{ 0x10DE0642, "GeForce 8400 GS" },␊
355␉{ 0x10DE0643, "GeForce 9500 GT" },␊
356␉{ 0x10DE0644, "GeForce 9500 GS" },␊
357␉{ 0x10DE0645, "GeForce 9500 GS" },␊
358␉{ 0x10DE0646, "GeForce GT 120" },␊
359␉{ 0x10DE0647, "GeForce 9600M GT" },␊
360␉{ 0x10DE0648, "GeForce 9600M GS" },␊
361␉{ 0x10DE0649, "GeForce 9600M GT" },␊
362␉{ 0x10DE064A, "GeForce 9700M GT" },␊
363␉{ 0x10DE064B, "GeForce 9500M G" },␊
364␉{ 0x10DE064C, "GeForce 9650M GT" },␊
365␉{ 0x10DE0652, "GeForce GT 130M" },␊
366␉{ 0x10DE0658, "Quadro FX 380" },␊
367␉{ 0x10DE0659, "Quadro FX 580" },␊
368␉{ 0x10DE065A, "Quadro FX 1700M" },␊
369␉{ 0x10DE065B, "GeForce 9400 GT" },␊
370␉{ 0x10DE065C, "Quadro FX 770M" },␊
371␉{ 0x10DE065F, "GeForce G210" },␊
372␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
373␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
374␉{ 0x10DE06E2, "GeForce 8400" },␊
375␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
376␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
377␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
378␉{ 0x10DE06E6, "GeForce G100" },␊
379␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
380␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
381␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
382␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
383␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
384␉{ 0x10DE06EC, "GeForce G 105M" },␊
385␉{ 0x10DE06EF, "GeForce G 103M" },␊
386␉{ 0x10DE06F8, "Quadro NVS 420" },␊
387␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
388␉{ 0x10DE06FA, "Quadro NVS 450" },␊
389␉{ 0x10DE06FD, "Quadro NVS 295" },␊
390␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
391␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
392␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
393␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
394␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
395␉{ 0x10DE0846, "GeForce 9200" },␊
396␉{ 0x10DE0847, "GeForce 9100" },␊
397␉{ 0x10DE0848, "GeForce 8300" },␊
398␉{ 0x10DE0849, "GeForce 8200" },␊
399␉{ 0x10DE084A, "nForce 730a" },␊
400␉{ 0x10DE084B, "GeForce 9200" },␊
401␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
402␉{ 0x10DE084D, "nForce 750a SLI" },␊
403␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
404␉{ 0x10DE0860, "GeForce 9400" },␊
405␉{ 0x10DE0861, "GeForce 9400" },␊
406␉{ 0x10DE0864, "GeForce 9300" },␊
407␉{ 0x10DE0865, "ION" },␊
408␉{ 0x10DE0868, "nForce 760i SLI" },␊
409␉{ 0x10DE086A, "GeForce 9400" },␊
410␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
411␉{ 0x10DE086D, "GeForce 9200" },␊
412␉{ 0x10DE0871, "GeForce 9200" },␊
413␉{ 0x10DE0874, "ION" },␊
414␉{ 0x10DE0876, "ION" },␊
415␉{ 0x10DE087A, "GeForce 9400" },␊
416 { 0x10DE087D, "ION 9400M" },␊
417 { 0x10DE087E, "ION LE" },␊
418␉{ 0x10DE087F, "ION LE" },␊
419␉{ 0x10DE0A20, "GeForce GT220" },␊
420␉{ 0x10DE0A23, "GeForce 210" },␊
421␉{ 0x10DE0A28, "GeForce GT 230M" },␊
422␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
423␉{ 0x10DE0A34, "GeForce GT 240M" },␊
424␉{ 0x10DE0A60, "GeForce G210" },␊
425␉{ 0x10DE0A62, "GeForce 205" },␊
426␉{ 0x10DE0A63, "GeForce 310" },␊
427␉{ 0x10DE0A64, "ION" },␊
428␉{ 0x10DE0A65, "GeForce 210" },␊
429␉{ 0x10DE0A66, "GeForce 310" },␊
430␉{ 0x10DE0A74, "GeForce G210M" },␊
431␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
432␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
433␉{ 0x10DE0CA2, "GeForce GT 320" },␊
434␉{ 0x10DE0CA3, "GeForce GT 240" },␊
435␉{ 0x10DE0CA4, "GeForce GT 340" },␊
436␉{ 0x10DE0CA7, "GeForce GT 330" },␊
437␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
438␉{ 0x10DE0CA9, "GeForce GTS 250M" }␊
439};␊
440␊
441static uint16_t swap16(uint16_t x)␊
442{␊
443␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
444}␊
445␊
446static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
447{␊
448␉uint8_t ret[2];␊
449␉ret[0] = ptr[offset+1];␊
450␉ret[1] = ptr[offset];␊
451␉return *((uint16_t*)&ret);␊
452}␊
453␊
454#if 0␊
455static uint32_t swap32(uint32_t x)␊
456{␊
457␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
458}␊
459␊
460static uint8_t read8(uint8_t *ptr, uint16_t offset)␊
461{ ␊
462␉return ptr[offset];␊
463}␊
464␊
465static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
466{␊
467␉uint8_t ret[4];␊
468␉ret[0] = ptr[offset+3];␊
469␉ret[1] = ptr[offset+2];␊
470␉ret[2] = ptr[offset+1];␊
471␉ret[3] = ptr[offset];␊
472␉return *((uint32_t*)&ret);␊
473}␊
474#endif␊
475␊
476static int patch_nvidia_rom(uint8_t *rom)␊
477{␊
478␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
479␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
480␉␉return PATCH_ROM_FAILED;␊
481␉}␊
482␉␊
483␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
484␉if(!dcbptr) {␊
485␉␉printf("no dcb table found\n");␊
486␉␉return PATCH_ROM_FAILED;␊
487␉}/* else␊
488␉ printf("dcb table at offset 0x%04x\n", dcbptr);␊
489␉ */␊
490␉uint8_t *dcbtable = &rom[dcbptr];␊
491␉uint8_t dcbtable_version = dcbtable[0];␊
492␉uint8_t headerlength = 0;␊
493␉uint8_t recordlength = 0;␊
494␉uint8_t numentries = 0;␊
495␉␊
496␉if(dcbtable_version >= 0x20) {␊
497␉␉uint32_t sig;␊
498␉␉␊
499␉␉if(dcbtable_version >= 0x30) {␊
500␉␉␉headerlength = dcbtable[1];␊
501␉␉␉numentries = dcbtable[2];␊
502␉␉␉recordlength = dcbtable[3];␊
503␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
504␉␉} else {␊
505␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
506␉␉␉headerlength = 8;␊
507␉␉}␊
508␉␉if (sig != 0x4edcbdcb) {␊
509␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊
510␉␉␉return PATCH_ROM_FAILED;␊
511␉␉}␊
512␉} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */␊
513␉␉char sig[8] = { 0 };␊
514␉␉␊
515␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
516␉␉recordlength = 10;␊
517␉␉if (strcmp(sig, "DEV_REC")) {␊
518␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
519␉␉␉return PATCH_ROM_FAILED;␊
520␉␉}␊
521␉} else {␊
522␉␉return PATCH_ROM_FAILED;␊
523␉}␊
524␉␊
525␉if(numentries >= MAX_NUM_DCB_ENTRIES)␊
526␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
527␉␊
528␉uint8_t num_outputs = 0, i=0;␊
529␉struct dcbentry {␊
530␉␉uint8_t type;␊
531␉␉uint8_t index;␊
532␉␉uint8_t *heads;␊
533␉} entries[numentries];␊
534␉␊
535␉for (i = 0; i < numentries; i++) {␊
536␉␉uint32_t connection;␊
537␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
538␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
539␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
540␉␉␉continue;␊
541␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
542␉␉␉continue;␊
543␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
544␉␉␉continue;␊
545␉␉␊
546␉␉entries[num_outputs].type = connection & 0xf;␊
547␉␉entries[num_outputs].index = num_outputs;␊
548␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
549␊
550␉}␊
551␉␊
552␉int has_lvds = false;␊
553␉uint8_t channel1 = 0, channel2 = 0;␊
554␉␊
555␉for(i=0; i<num_outputs; i++) {␊
556␉␉if(entries[i].type == 3) {␊
557␉␉␉has_lvds = true;␊
558␉␉␉//printf("found LVDS\n");␊
559␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
560␉␉␉entries[i].type = TYPE_GROUPED;␊
561␉␉}␊
562␉}␊
563␉// if we have a LVDS output, we group the rest to the second channel␊
564␉if(has_lvds) {␊
565␉␉for(i=0; i<num_outputs; i++) {␊
566␉␉␉if(entries[i].type == TYPE_GROUPED)␊
567␉␉␉␉continue;␊
568␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
569␉␉␉entries[i].type = TYPE_GROUPED;␊
570␉␉}␊
571␉} else {␊
572␉␉//␊
573␉␉int x;␊
574␉␉// we loop twice as we need to generate two channels␊
575␉␉for(x=0; x<=1; x++) {␊
576␉␉␉for(i=0; i<num_outputs; i++) {␊
577␉␉␉␉if(entries[i].type == TYPE_GROUPED)␊
578␉␉␉␉␉continue;␊
579␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
580␉␉␉␉// we always group ANALOG and TMDS␊
581␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
582␉␉␉␉if(i && entries[i].type == 0x2) {␊
583␉␉␉␉␉switch (x) {␊
584␉␉␉␉␉␉case 0:␊
585␉␉␉␉␉␉␉//printf("group channel 1\n");␊
586␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
587␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
588␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
589␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
590␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
591␉␉␉␉␉␉␉}␊
592␉␉␉␉␉␉␉// group TV as well if there is one␊
593␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
594␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
595␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
596␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
597␉␉␉␉␉␉␉}␊
598␉␉␉␉␉␉␉break;␊
599␉␉␉␉␉␉case 1:␊
600␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
601␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
602␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
603␉␉␉␉␉␉␉if((entries[i-1].type == 0x0)) {␊
604␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
605␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
606␉␉␉␉␉␉␉}␊
607␉␉␉␉␉␉␉// group TV as well if there is one␊
608␉␉␉␉␉␉␉if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {␊
609␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
610␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
611␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
612␉␉␉␉␉␉␉}␊
613␉␉␉␉␉␉␉break;␊
614␉␉␉␉␉␉␉␊
615␉␉␉␉␉}␊
616␉␉␉␉␉break;␊
617␉␉␉␉}␊
618␉␉␉}␊
619␉␉}␊
620␉}␊
621␉␊
622␉// if we have left ungrouped outputs merge them to the empty channel␊
623␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
624␉togroup = &channel2;␊
625␉for(i=0; i<num_outputs;i++)␊
626␉␉if(entries[i].type != TYPE_GROUPED) {␊
627␉␉␉//printf("%d not grouped\n", i);␊
628␉␉␉if(togroup)␊
629␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
630␉␉␉entries[i].type = TYPE_GROUPED;␊
631␉␉}␊
632␉␊
633␉if(channel1 > channel2) {␊
634␉␉uint8_t buff = channel1;␊
635␉␉channel1 = channel2;␊
636␉␉channel2 = buff;␊
637␉}␊
638␉␊
639␉default_NVCAP[6] = channel1;␊
640␉default_NVCAP[8] = channel2;␊
641␉␊
642␉// patching HEADS␊
643␉for(i=0; i<num_outputs;i++) {␊
644␉␉if(channel1 & (1 << i))␊
645␉␉␉*entries[i].heads = 1;␊
646␉␉else if(channel2 & (1 << i))␊
647␉␉␉*entries[i].heads = 2;␊
648␉}␊
649␉␊
650␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
651}␊
652␊
653static char *get_nvidia_model(uint32_t id) {␊
654␉int␉i;␊
655␊
656␉for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
657␉␉if (NVKnownChipsets[i].device == id) {␊
658␉␉␉return NVKnownChipsets[i].name;␊
659␉␉}␊
660␉}␊
661␉return NVKnownChipsets[0].name;␊
662}␊
663␊
664static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
665{␊
666␉int␉fd;␊
667␉int␉size;␊
668␊
669␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {␊
670␉␉return 0;␊
671␉}␊
672␉size = file_size(fd);␊
673␉if (size > bufsize) {␊
674␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);␊
675␉␉size = bufsize;␊
676␉}␊
677␉size = read(fd, (char *)buf, size);␊
678␉close(fd);␊
679␉return size > 0 ? size : 0;␊
680}␊
681␊
682static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
683{␊
684␉char␉tmp[16]; ␊
685␊
686␉if(!device)␊
687␉␉return 0;␊
688␊
689␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
690␉␉return 0;␊
691␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
692␉␉return 0;␊
693␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
694␉␉return 0;␊
695␉if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
696␉␉return 0;␊
697␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
698␉␉return 0;␊
699␉if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
700␉␉return 0;␊
701␉if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
702␉␉return 0;␊
703␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
704␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
705␉sprintf(tmp, "Slot-%x",devices_number);␊
706␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
707␉devices_number++;␊
708␊
709␉return 1;␊
710}␊
711␊
712int hex2bin(const char *hex, uint8_t *bin, int len)␊
713{␊
714␉char␉*p;␊
715␉int␉i;␊
716␉char␉buf[3];␊
717 ␊
718␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
719␉␉printf("[ERROR] bin2hex input error\n");␊
720␉␉return -1;␊
721␉}␊
722 ␊
723␉buf[2] = '\0';␊
724␉p = (char *) hex;␊
725␉for (i=0; i<len; i++) {␊
726␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
727␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
728␉␉␉return -2;␊
729␉␉}␊
730␉␉buf[0] = *p++;␊
731␉␉buf[1] = *p++;␊
732␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
733␉}␊
734␉return 0;␊
735}␊
736␊
737bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
738{␊
739␉struct DevPropDevice␉␉*device;␊
740␉char␉␉␉␉*devicepath;␊
741␉struct pci_rom_pci_header_t␉*rom_pci_header;␉␊
742␉volatile uint8_t␉␉*regs;␊
743␉uint8_t␉␉␉␉*rom;␊
744␉uint8_t␉␉␉␉*nvRom;␊
745␉uint32_t␉␉␉videoRam;␊
746␉uint32_t␉␉␉nvBiosOveride;␊
747␉uint32_t␉␉␉bar[7];␊
748␉uint32_t␉␉␉boot_display;␊
749␉int␉␉␉␉nvPatch;␊
750␉int␉␉␉␉len;␊
751␉char␉␉␉␉biosVersion[32];␊
752␉char␉␉␉␉nvFilename[32];␊
753␉char␉␉␉␉kNVCAP[12];␊
754␉char␉␉␉␉*model;␊
755␉const char␉␉␉*value;␊
756␉bool␉␉␉␉doit;␊
757␊
758␉devicepath = get_pci_dev_path(nvda_dev);␊
759␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
760␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
761␊
762␉// Amount of VRAM in kilobytes␊
763␉videoRam = (REG32(0x10020c) & 0xfff00000) >> 10;␊
764␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
765␊
766␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n", ␊
767␉␉model, (videoRam / 1024),␊
768␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
769␉␉devicepath);␊
770␊
771␉rom = malloc(NVIDIA_ROM_SIZE);␊
772␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);␊
773␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {␊
774␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
775␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
776␉␉if (nvBiosOveride > 0) {␊
777␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
778␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
779␉␉} else {␊
780␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
781␉␉␉return false;␊
782␉␉}␊
783␉} else {␊
784␉␉// Otherwise read bios from card␊
785␉␉nvBiosOveride = 0;␊
786␊
787␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
788␊
789␉␉// PRAMIN first␊
790␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
791␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
792␉␉␊
793␉␉// Valid Signature ?␊
794␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
795␉␉␉// PROM next␊
796␉␉␉// Enable PROM access␊
797␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
798␊
799␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
800␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
801␉␉␉␊
802␉␉␉// disable PROM access␊
803␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␉␊
804␊
805␉␉␉// Valid Signature ?␊
806␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
807␉␉␉␉// 0xC0000 last␊
808␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
809␉␉␉␉␊
810␉␉␉␉// Valid Signature ?␊
811␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa) {␊
812␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
813␉␉␉␉␉return false;␊
814␉␉␉␉} else {␊
815␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
816␉␉␉␉}␊
817␉␉␉} else {␊
818␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
819␉␉␉}␊
820␉␉} else {␊
821␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
822␉␉}␊
823␉}␊
824␊
825␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
826␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
827␉␉return false;␊
828␉}␊
829␊
830␉rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
831␊
832␉// check for 'PCIR' sig␊
833␉if (rom_pci_header->signature == 0x50434952) {␊
834␉␉if (rom_pci_header->device != nvda_dev->device_id) {␊
835␉␉␉// Get Model from the OpROM␊
836␉␉␉model = get_nvidia_model((rom_pci_header->vendor << 16) | rom_pci_header->device);␊
837␉␉} else {␊
838␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
839␉␉}␊
840␉}␊
841␊
842␉if (!string) {␊
843␉␉string = devprop_create_string();␊
844␉}␊
845␉device = devprop_add_device(string, devicepath);␊
846␊
847␉/* FIXME: for primary graphics card only */␊
848␉boot_display = 1;␊
849␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
850␊
851␉if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
852␉␉uint8_t built_in = 0x01;␊
853␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
854␉}␊
855␊
856␉videoRam *= 1024;␊
857␉sprintf(biosVersion, "xx.xx.xx - %s", (nvBiosOveride > 0) ? nvFilename : "internal");␊
858␊
859␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
860␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {␊
861␉␉uint8_t␉new_NVCAP[NVCAP_LEN];␊
862 ␊
863␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {␊
864␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
865␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
866␉␉}␊
867␉}␊
868␊
869 #if DEBUG_NVCAP␊
870 printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
871␉␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
872␉␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
873␉␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
874␉␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
875␉␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
876#endif␊
877 ␊
878␉␊
879␉devprop_add_nvidia_template(device);␊
880␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
881␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
882␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
883␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
884␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {␊
885␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
886␉}␊
887␊
888␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
889␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
890␉stringlength = string->length;␊
891␊
892␉return true;␊
893}␊
894

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