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Root/branches/cparm/i386/modules/Memory/dram_controllers.c

1/*␊
2 * dram controller access and scan from the pci host controller␊
3 * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work␊
4 * original source comes from:␊
5 *␊
6 * memtest86␊
7 *␊
8 * Released under version 2 of the Gnu Public License.␊
9 * By Chris Brady, cbrady@sgi.com␊
10 * ----------------------------------------------------␊
11 * MemTest86+ V4.00 Specific code (GPL V2.0)␊
12 * By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
13 * http://www.canardpc.com - http://www.memtest.org␊
14 */␊
15␊
16#include "libsaio.h"␊
17#include "bootstruct.h"␊
18#include "pci.h"␊
19#include "platform.h"␊
20#include "dram_controllers.h"␊
21␊
22#ifndef DEBUG_DRAM␊
23#define DEBUG_DRAM 0␊
24#endif␊
25␊
26#if DEBUG_DRAM␊
27#define DBG(x...) printf(x)␊
28#else␊
29#define DBG(x...)␊
30#endif␊
31static void setup_p35(pci_dt_t *dram_dev);␊
32static void setup_nhm(pci_dt_t *dram_dev);␊
33static void get_fsb_i965(pci_dt_t *dram_dev);␊
34static void get_fsb_im965(pci_dt_t *dram_dev);␊
35static void get_fsb_nhm(pci_dt_t *dram_dev);␊
36static void get_timings_i965(pci_dt_t *dram_dev);␊
37static void get_timings_im965(pci_dt_t *dram_dev);␊
38static void get_timings_p35(pci_dt_t *dram_dev);␊
39static void get_timings_nhm(pci_dt_t *dram_dev);␊
40␊
41/*␊
42 * Initialise memory controller functions␊
43 */␊
44␊
45// Setup P35 Memory Controller␊
46static void setup_p35(pci_dt_t *dram_dev)␊
47{␊
48␉uint32_t dev0;␊
49␉␊
50␉// Activate MMR I/O␊
51␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
52␉if (!(dev0 & 0x1))␊
53␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊
54}␊
55␊
56int nhm_bus = 0x3F;␊
57␊
58␊
59// Setup Nehalem Integrated Memory Controller␊
60static void setup_nhm(pci_dt_t *dram_dev)␊
61{␊
62 static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
63␉unsigned long did, vid;␊
64␉int i;␊
65␉␊
66␉// Nehalem supports Scrubbing␊
67␉// First, locate the PCI bus where the MCH is located␊
68␉for(i = 0; (unsigned)i < sizeof(possible_nhm_bus); i++)␊
69␉{␊
70␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊
71␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊
72␉␉vid &= 0xFFFF;␊
73␉␉did &= 0xFF00;␊
74␉␉␊
75␉␉if(vid == 0x8086 && did >= 0x2C00)␊
76␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
77␉}␊
78}␊
79␊
80/*␊
81 * Retrieve memory controller fsb functions␊
82 */␊
83␊
84␊
85// Get i965 Memory Speed␊
86static void get_fsb_i965(pci_dt_t *dram_dev)␊
87{␊
88␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
89␊
90␉long *ptr;␊
91␉␊
92␉// Find Ratio␊
93␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
94␉dev0 &= 0xFFFFC000;␊
95␉ptr = (long*)(dev0 + 0xC00);␊
96␉mch_cfg = *ptr & 0xFFFF;␊
97␉␊
98␉mch_ratio = 100000;␊
99␉␊
100␉switch (mch_cfg & 7)␊
101␉{␊
102␉␉case 0: mch_fsb = 1066; break;␊
103␉␉case 1: mch_fsb = 533; break;␊
104␉ default: ␊
105␉␉case 2: mch_fsb = 800; break;␊
106␉␉case 3: mch_fsb = 667; break;␉␉␊
107␉␉case 4: mch_fsb = 1333; break;␊
108␉␉case 6: mch_fsb = 1600; break;␉␉␉␉␉␊
109␉}␊
110␉␊
111␉DBG("mch_fsb %d\n", mch_fsb);␊
112␉␊
113␉switch (mch_fsb)␊
114␉{␊
115␉␉case 533:␊
116␉␉␉switch ((mch_cfg >> 4) & 7)␊
117␉␉{␊
118␉␉␉case 1:␉mch_ratio = 200000; break;␊
119␉␉␉case 2:␉mch_ratio = 250000; break;␊
120␉␉␉case 3:␉mch_ratio = 300000; break;␊
121␉␉}␊
122␉␉␉break;␊
123␉␉␉␊
124␉␉default:␊
125␉␉case 800:␊
126␉␉␉switch ((mch_cfg >> 4) & 7)␊
127␉␉{␊
128␉␉␉case 0:␉mch_ratio = 100000; break;␊
129␉␉␉case 1:␉mch_ratio = 125000; break;␊
130␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊
131␉␉␉case 3:␉mch_ratio = 200000; break;␊
132␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊
133␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊
134␉␉}␊
135␉␉␉break;␊
136␉␉␉␊
137␉␉case 1066:␊
138␉␉␉switch ((mch_cfg >> 4) & 7)␊
139␉␉{␊
140␉␉␉case 1:␉mch_ratio = 100000; break;␊
141␉␉␉case 2:␉mch_ratio = 125000; break;␊
142␉␉␉case 3:␉mch_ratio = 150000; break;␊
143␉␉␉case 4:␉mch_ratio = 200000; break;␊
144␉␉␉case 5:␉mch_ratio = 250000; break;␊
145␉␉}␊
146␉␉␉break;␊
147␉␉␉␊
148␉␉case 1333:␊
149␉␉␉switch ((mch_cfg >> 4) & 7)␊
150␉␉{␊
151␉␉␉case 2:␉mch_ratio = 100000; break;␊
152␉␉␉case 3:␉mch_ratio = 120000; break;␊
153␉␉␉case 4:␉mch_ratio = 160000; break;␊
154␉␉␉case 5:␉mch_ratio = 200000; break;␊
155␉␉}␊
156␉␉␉break;␊
157␉␉␉␊
158␉␉case 1600:␊
159␉␉␉switch ((mch_cfg >> 4) & 7)␊
160␉␉{␊
161␉␉␉case 3:␉mch_ratio = 100000; break;␊
162␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊
163␉␉␉case 5:␉mch_ratio = 150000; break;␊
164␉␉␉case 6:␉mch_ratio = 200000; break;␊
165␉␉}␊
166␉␉␉break;␊
167␉}␊
168␉␊
169␉DBG("mch_ratio %d\n", mch_ratio);␊
170␊
171␉// Compute RAM Frequency ␊
172 safe_set_env(envRamFrequency, ((get_env(envFSBFreq) * mch_ratio) / 100000));␊
173␉␊
174␉DBG("ram_fsb %d\n", (uint32_t)get_env(envRamFrequency));␊
175␊
176}␊
177␊
178// Get i965m Memory Speed␊
179static void get_fsb_im965(pci_dt_t *dram_dev)␊
180{␊
181␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
182␊
183␉long *ptr;␊
184␉␊
185␉// Find Ratio␊
186␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
187␉dev0 &= 0xFFFFC000;␊
188␉ptr = (long*)(dev0 + 0xC00);␊
189␉mch_cfg = *ptr & 0xFFFF;␊
190␉␊
191␉mch_ratio = 100000;␊
192␉␊
193␉switch (mch_cfg & 7)␊
194␉{␊
195␉␉case 1: mch_fsb = 533; break;␊
196␉␉default: ␊
197␉␉case 2:␉mch_fsb = 800; break;␊
198␉␉case 3:␉mch_fsb = 667; break;␉␉␉␉␊
199␉␉case 6:␉mch_fsb = 1066; break;␉␉␉␊
200␉}␊
201␉␊
202␉switch (mch_fsb)␊
203␉{␊
204␉␉case 533:␊
205␉␉␉switch ((mch_cfg >> 4) & 7)␊
206␉␉␉{␊
207␉␉␉␉case 1:␉mch_ratio = 125000; break;␊
208␉␉␉␉case 2:␉mch_ratio = 150000; break;␊
209␉␉␉␉case 3:␉mch_ratio = 200000; break;␊
210␉␉␉}␊
211␉␉␉break;␊
212␉␉␉␊
213␉␉case 667:␊
214␉␉␉switch ((mch_cfg >> 4)& 7)␊
215␉␉␉{␊
216␉␉␉␉case 1:␉mch_ratio = 100000; break;␊
217␉␉␉␉case 2:␉mch_ratio = 120000; break;␊
218␉␉␉␉case 3:␉mch_ratio = 160000; break;␊
219␉␉␉␉case 4:␉mch_ratio = 200000; break;␊
220␉␉␉␉case 5:␉mch_ratio = 240000; break;␊
221␉␉␉}␊
222␉␉␉break;␊
223␉␉␉␊
224␉␉default:␊
225␉␉case 800:␊
226␉␉␉switch ((mch_cfg >> 4) & 7)␊
227␉␉␉{␊
228␉␉␉␉case 1:␉mch_ratio = 83333; break; // 0.833333333␊
229␉␉␉␉case 2:␉mch_ratio = 100000; break;␊
230␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊
231␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊
232␉␉␉␉case 5:␉mch_ratio = 200000; break;␊
233␉␉␉}␊
234␉␉␉break;␊
235␉␉case 1066:␊
236␉␉␉switch ((mch_cfg >> 4)&7) {␊
237␉␉␉␉case 5:␉mch_ratio = 150000; break;␊
238␉␉␉␉case 6:␉mch_ratio = 200000; break;␊
239␉␉␉}␊
240␉␉␉␊
241␉}␊
242␉␊
243␉// Compute RAM Frequency␊
244␉safe_set_env(envRamFrequency, ((get_env(envFSBFreq) * mch_ratio) / 100000));␊
245␉␊
246␉DBG("ram_fsb %d\n", (uint32_t)get_env(envRamFrequency));␊
247}␊
248␊
249␊
250// Get iCore7 Memory Speed␊
251static void get_fsb_nhm(pci_dt_t *dram_dev)␊
252{␊
253␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊
254␉␊
255␉// Get the clock ratio␊
256␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊
257␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊
258␉␊
259␉// Compute RAM Frequency␊
260 safe_set_env(envRamFrequency, ((get_env(envFSBFreq) * mch_ratio) / 2));␊
261␉␊
262␉DBG("ram_fsb %d\n", (uint32_t)get_env(envRamFrequency));␉␊
263}␊
264 ␊
265/*␊
266 * Retrieve memory controller info functions␊
267 */␊
268␊
269// Get i965 Memory Timings␊
270static void get_timings_i965(pci_dt_t *dram_dev)␊
271{ ␊
272␉// Thanks for CDH optis␊
273␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊
274␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
275␊
276␉long *ptr;␊
277␉␊
278␉// Read MMR Base Address␊
279␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
280␉dev0 &= 0xFFFFC000;␊
281␉␊
282␉ptr = (long*)(dev0 + 0x260);␊
283␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
284␉␊
285␉ptr = (long*)(dev0 + 0x660);␊
286␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
287␉␊
288␉// If DIMM 0 not populated, check DIMM 1␊
289␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
290␉␊
291␉ptr = (long*)(dev0 + offset + 0x29C);␊
292␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
293␉␊
294␉ptr = (long*)(dev0 + offset + 0x250);␉␊
295␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
296␉␊
297␉ptr = (long*)(dev0 + offset + 0x252);␊
298␉ACT_Register = *ptr & 0xFFFFFFFF;␊
299␉␊
300␉ptr = (long*)(dev0 + offset + 0x258);␊
301␉Read_Register = *ptr & 0xFFFFFFFF;␊
302␉␊
303␉ptr = (long*)(dev0 + offset + 0x244);␊
304␉Misc_Register = *ptr & 0xFFFFFFFF;␊
305␉␊
306␉// 965 Series only support DDR2␊
307 safe_set_env(envRamType,SMB_MEM_TYPE_DDR2);␊
308␉␊
309␉// CAS Latency (tCAS)␊
310 safe_set_env(envRamCas,((ODT_Control_Register >> 17) & 7) + 3);␊
311␊
312␉// RAS-To-CAS (tRCD)␊
313 safe_set_env(envRamTrc,(Read_Register >> 16) & 0xF);␊
314␊
315␉// RAS Precharge (tRP)␊
316 safe_set_env(envRamTrp,(ACT_Register >> 13) & 0xF);␊
317␊
318␉// RAS Active to precharge (tRAS)␊
319 safe_set_env(envRamRas,(Precharge_Register >> 11) & 0x1F);␊
320␉␊
321␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF))␊
322␉␉safe_set_env(envRamChannels, SMB_MEM_CHANNEL_DUAL);␊
323␉else␊
324 safe_set_env(envRamChannels, SMB_MEM_CHANNEL_SINGLE);␊
325}␊
326␊
327// Get im965 Memory Timings␊
328static void get_timings_im965(pci_dt_t *dram_dev)␊
329{␊
330␉// Thanks for CDH optis␊
331␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊
332␉long *ptr;␊
333␉␊
334␉// Read MMR Base Address␊
335␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
336␉dev0 &= 0xFFFFC000;␊
337␉␊
338␉ptr = (long*)(dev0 + 0x1200);␊
339␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
340␉␊
341␉ptr = (long*)(dev0 + 0x1300);␊
342␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
343␉␊
344␉// If DIMM 0 not populated, check DIMM 1␊
345␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊
346␉␊
347␉ptr = (long*)(dev0 + offset + 0x121C);␊
348␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
349␉␊
350␉ptr = (long*)(dev0 + offset + 0x1214);␉␊
351␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
352␉␊
353␉// Series only support DDR2␊
354 safe_set_env(envRamType,SMB_MEM_TYPE_DDR2);␊
355␊
356␉// CAS Latency (tCAS)␊
357 safe_set_env(envRamCas,((ODT_Control_Register >> 23) & 7) + 3);␊
358␊
359␉// RAS-To-CAS (tRCD)␊
360 safe_set_env(envRamTrc,((Precharge_Register >> 5) & 7) + 2);␊
361␊
362␉// RAS Precharge (tRP)␊
363 safe_set_env(envRamTrp,(Precharge_Register & 7) + 2);␊
364␊
365␉// RAS Active to precharge (tRAS)␊
366 safe_set_env(envRamRas,(Precharge_Register >> 21) & 0x1F);␊
367␊
368␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) ␊
369 safe_set_env(envRamChannels, SMB_MEM_CHANNEL_DUAL);␊
370␉else␊
371 safe_set_env(envRamChannels, SMB_MEM_CHANNEL_SINGLE);␊
372}␊
373␊
374// Get P35 Memory Timings␊
375static void get_timings_p35(pci_dt_t *dram_dev)␊
376{ ␊
377␉// Thanks for CDH optis␊
378␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊
379␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
380␉long *ptr;␊
381␉␊
382␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊
383␉//Device_ID &= 0xFFFF;␊
384␉␊
385␉// Now, read MMR Base Address␊
386␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
387␉dev0 &= 0xFFFFC000;␊
388␉␊
389␉ptr = (long*)(dev0 + 0x260);␊
390␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
391␉␊
392␉ptr = (long*)(dev0 + 0x660);␊
393␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
394␉␊
395␉// If DIMM 0 not populated, check DIMM 1␊
396␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
397␉␊
398␉ptr = (long*)(dev0 + offset + 0x265);␊
399␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
400␉␊
401␉ptr = (long*)(dev0 + offset + 0x25D);␉␊
402␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
403␉␊
404␉ptr = (long*)(dev0 + offset + 0x252);␊
405␉ACT_Register = *ptr & 0xFFFFFFFF;␊
406␉␊
407␉ptr = (long*)(dev0 + offset + 0x258);␊
408␉Read_Register = *ptr & 0xFFFFFFFF;␊
409␉␊
410␉ptr = (long*)(dev0 + offset + 0x244);␊
411␉Misc_Register = *ptr & 0xFFFFFFFF;␊
412␉␊
413␉ptr = (long*)(dev0 + offset + 0x1E8);␊
414␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
415␉␊
416␉// On P45, check 1A8␊
417␉if(dram_dev->device_id > 0x2E00) {␊
418␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊
419␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
420␉␉Memory_Check >>= 2;␊
421␉␉Memory_Check &= 1;␊
422␉␉Memory_Check = !Memory_Check;␊
423␉} else {␊
424␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊
425␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␉␊
426␉}␊
427␉␊
428␉// Determine DDR-II or DDR-III␊
429␉if (Memory_Check & 1)␊
430 safe_set_env(envRamType,SMB_MEM_TYPE_DDR2);␊
431␉else␊
432 safe_set_env(envRamType,SMB_MEM_TYPE_DDR3);␊
433␉␊
434␉// CAS Latency (tCAS)␊
435␉if(dram_dev->device_id > 0x2E00)␊
436 safe_set_env(envRamCas,((ODT_Control_Register >> 8) & 0x3F) - 6);␊
437␉else␊
438 safe_set_env(envRamCas,((ODT_Control_Register >> 8) & 0x3F) - 9);␊
439␉␊
440␉// RAS-To-CAS (tRCD)␊
441 safe_set_env(envRamTrc,(Read_Register >> 17) & 0xF);␊
442␊
443␉// RAS Precharge (tRP)␊
444 safe_set_env(envRamTrp,(ACT_Register >> 13) & 0xF);␊
445␉␊
446␉// RAS Active to precharge (tRAS)␊
447 safe_set_env(envRamRas,(Precharge_Register & 0x3F));␊
448␊
449␉// Channel configuration␊
450␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) ␊
451 safe_set_env(envRamChannels, SMB_MEM_CHANNEL_DUAL);␊
452 else␊
453 safe_set_env(envRamChannels, SMB_MEM_CHANNEL_SINGLE);␊
454}␊
455␊
456// Get Nehalem Memory Timings␊
457static void get_timings_nhm(pci_dt_t *dram_dev)␊
458{␊
459␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊
460␉int fvc_bn = 4;␊
461␉␊
462␉// Find which channels are populated␊
463␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊
464␉mc_control = (mc_control >> 8) & 0x7;␊
465␉␊
466␉// DDR-III␊
467 safe_set_env(envRamType,SMB_MEM_TYPE_DDR3);␊
468␊
469␉// Get the first valid channel␊
470␉if(mc_control & 1)␊
471␉␉fvc_bn = 4; ␊
472␉else if(mc_control & 2)␊
473␉␉fvc_bn = 5; ␊
474␉else if(mc_control & 7) ␊
475␉␉fvc_bn = 6; ␊
476␉␊
477␉// Now, detect timings␊
478␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊
479␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊
480␉␊
481␉// CAS Latency (tCAS)␊
482 safe_set_env(envRamCas,((mc_channel_mrs_value >> 4) & 0xF ) + 4);␊
483␊
484␉// RAS-To-CAS (tRCD)␊
485 safe_set_env(envRamTrc,(mc_channel_bank_timing >> 9) & 0xF);␊
486␊
487␉// RAS Active to precharge (tRAS)␊
488 safe_set_env(envRamRas,(mc_channel_bank_timing >> 4) & 0x1F);␊
489␊
490␉// RAS Precharge (tRP)␊
491 safe_set_env(envRamTrp,mc_channel_bank_timing & 0xF);␊
492␊
493␉// Single , Dual or Triple Channels␊
494␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊
495 safe_set_env(envRamChannels, SMB_MEM_CHANNEL_SINGLE);␊
496␉else if (mc_control == 7)␊
497␉␉safe_set_env(envRamChannels, SMB_MEM_CHANNEL_TRIPLE);␊
498␉else␊
499 safe_set_env(envRamChannels, SMB_MEM_CHANNEL_DUAL);␊
500}␊
501␊
502static struct mem_controller_t dram_controllers[] = {␊
503␊
504␉// Default unknown chipset␊
505␉{ 0, 0, "",␉NULL, NULL, NULL },␊
506␊
507␉// Intel␊
508␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊
509␊
510␉{ 0x8086, 0x1A30, "i845",␉NULL, NULL, NULL },␊
511␉␊
512␉{ 0x8086, 0x2970, "i946PL/GZ",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
513␉{ 0x8086, 0x2990, "Q963/Q965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
514␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
515␊
516␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
517␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
518␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965, get_timings_im965 },␉␊
519␊
520␉{ 0x8086, 0x29B0, "Q35",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
521␉{ 0x8086, 0x29C0, "P35/G33",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
522␉{ 0x8086, 0x29D0, "Q33",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
523␉{ 0x8086, 0x29E0, "X38/X48",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␉␉␊
524␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
525␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
526␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
527␉{ 0x8086, 0x2E30, "G41",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
528␉␊
529␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
530␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
531␉{ 0x8086, 0x3400, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉ get_timings_nhm },␊
532␉{ 0x8086, 0x3401, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
533␉{ 0x8086, 0x3402, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
534␉{ 0x8086, 0x3403, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
535␉{ 0x8086, 0x3404, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
536␉{ 0x8086, 0x3405, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
537␉{ 0x8086, 0x3406, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
538␉{ 0x8086, 0x3407, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
539␉␊
540};␊
541␊
542static const char *memory_channel_types[] =␊
543{␊
544␉"Unknown", "Single", "Dual", "Triple"␊
545};␉␉␉␊
546␊
547void scan_dram_controller(pci_dt_t *dram_dev)␊
548{␊
549␉int i;␊
550␉for(i = 1; (unsigned)i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)␊
551␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) ␊
552␉␉␉␉&& (dram_controllers[i].device == dram_dev->device_id))␊
553␉␉{␊
554␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊
555␉␉␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel " : "" ,␊
556␉␉␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊
557␉␉␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊
558␉␉␉␊
559␉␉␉if (dram_controllers[i].initialise != NULL)␊
560␉␉␉␉dram_controllers[i].initialise(dram_dev);␊
561␉␉␉␉␉␉␉␊
562␉␉␉if (dram_controllers[i].poll_timings != NULL)␊
563␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊
564␉␉␉␉␉␉␉␉␊
565␉␉␉if (dram_controllers[i].poll_speed != NULL)␊
566␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊
567␉␉␉ ␊
568 verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", ␊
569 (uint32_t)get_env(envRamFrequency) / 1000000,␊
570 (uint32_t)get_env(envFSBFreq) / 500000,␊
571 memory_channel_types[get_env(envRamChannels)]␊
572␉␉␉␉␉,(uint32_t)get_env(envRamCas),(uint32_t) get_env(envRamTrc), (uint32_t)get_env(envRamTrp),(uint32_t) get_env(envRamRas)␊
573␉␉␉␉␉,(uint32_t)get_env(envRamCas),(uint32_t) get_env(envRamTrc),(uint32_t) get_env(envRamTrp), (uint32_t)get_env(envRamRas)␊
574␉␉␉␉␉);␊
575#if DEBUG_DRAM␊
576␉␉␉ getc();␊
577#endif␊
578␉␉␉␊
579␉␉}␉␊
580}␉␊
581

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