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Root/branches/ErmaC/Trunk/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74␊
75extern uint32_t devices_number;␊
76␊
77const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
78const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
79const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
80const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
81const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
82/*␊
83 TODO: http://forge.voodooprojects.org/p/chameleon/issues/193/␊
84 const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
85 */␊
86const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
87const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
88const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
89␊
90// uint8_t display_cfg_0[]␉␉␉=␉{0x03, 0x01, 0x03, 0x00};␊
91// uint8_t display_cfg_1[]␉␉␉=␉{0xff, 0xff, 0x00, 0x01};␊
92// uint8_t connector_type_1[] ␉␉=␉{0x00, 0x08, 0x00, 0x00};␊
93␊
94static uint8_t default_NVCAP[]= {␊
95␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
96␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
97␉0x00, 0x00, 0x00, 0x00␊
98};␊
99␊
100static uint8_t default_NVPM[]= {␊
101 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
102 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
103 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
104 0x00, 0x00, 0x00, 0x00␊
105};␊
106␊
107#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
108#define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊
109␊
110static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
111static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
112␊
113#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
114#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
115␊
116static struct nv_chipsets_t NVKnownChipsets[] = {␊
117␉{ 0x00000000, "Unknown" },␊
118//========================================␊
119␉// 0040 - 004F␉␊
120␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
121␉{ 0x10DE0041, "GeForce 6800" },␊
122␉{ 0x10DE0042, "GeForce 6800 LE" },␊
123␉{ 0x10DE0043, "GeForce 6800 XE" },␊
124␉{ 0x10DE0044, "GeForce 6800 XT" },␊
125␉{ 0x10DE0045, "GeForce 6800 GT" },␊
126␉{ 0x10DE0046, "GeForce 6800 GT" },␊
127␉{ 0x10DE0047, "GeForce 6800 GS" },␊
128␉{ 0x10DE0048, "GeForce 6800 XT" },␊
129␉{ 0x10DE004D, "Quadro FX 3400" },␊
130␉{ 0x10DE004E, "Quadro FX 4000" },␊
131␉// 0050 - 005F␊
132␉// 0060 - 006F␉␊
133␉// 0070 - 007F␉␊
134␉// 0080 - 008F␉␊
135␉// 0090 - 009F␉␊
136␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
137␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
138␉{ 0x10DE0092, "GeForce 7800 GT" },␊
139␉{ 0x10DE0093, "GeForce 7800 GS" },␊
140␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
141␉{ 0x10DE0098, "GeForce Go 7800" },␊
142␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
143␉{ 0x10DE009D, "Quadro FX 4500" },␊
144␉// 00A0 - 00AF␉␊
145␉// 00B0 - 00BF␉␊
146␉// 00C0 - 00CF␉␊
147␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
148␉{ 0x10DE00C1, "GeForce 6800" },␊
149␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
150␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
151␉{ 0x10DE00C8, "GeForce Go 6800" },␊
152␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
153␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
154␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
155␉{ 0x10DE00CE, "Quadro FX 1400" },␊
156␉// 00D0 - 00DF␉␊
157␉// 00E0 - 00EF␉␊
158␉// 00F0 - 00FF␉␊
159␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
160␉{ 0x10DE00F2, "GeForce 6600" },␊
161␉{ 0x10DE00F3, "GeForce 6200" },␊
162␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
163␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
164␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
165␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
166␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
167␉// 0100 - 010F␉␊
168␉// 0110 - 011F␉␊
169␉// 0120 - 012F␉␊
170␉// 0130 - 013F␉␊
171␉// 0140 - 014F␉␊
172␉{ 0x10DE0140, "GeForce 6600 GT" },␊
173␉{ 0x10DE0141, "GeForce 6600" },␊
174␉{ 0x10DE0142, "GeForce 6600 LE" },␊
175␉{ 0x10DE0143, "GeForce 6600 VE" },␊
176␉{ 0x10DE0144, "GeForce Go 6600" },␊
177␉{ 0x10DE0145, "GeForce 6610 XL" },␊
178␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
179␉{ 0x10DE0147, "GeForce 6700 XL" },␊
180␉{ 0x10DE0148, "GeForce Go 6600" },␊
181␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
182␉{ 0x10DE014A, "Quadro NVS 440" },␊
183␉{ 0x10DE014C, "Quadro FX 550" },␊
184␉{ 0x10DE014D, "Quadro FX 550" },␊
185␉{ 0x10DE014E, "Quadro FX 540" },␊
186␉{ 0x10DE014F, "GeForce 6200" },␊
187␉// 0150 - 015F␉␊
188␉// 0160 - 016F␉␊
189␉{ 0x10DE0160, "GeForce 6500" },␊
190␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
191␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
192␉{ 0x10DE0163, "GeForce 6200 LE" },␊
193␉{ 0x10DE0164, "GeForce Go 6200" },␊
194␉{ 0x10DE0165, "Quadro NVS 285" },␊
195␉{ 0x10DE0166, "GeForce Go 6400" },␊
196␉{ 0x10DE0167, "GeForce Go 6200" },␊
197␉{ 0x10DE0168, "GeForce Go 6400" },␊
198␉{ 0x10DE0169, "GeForce 6250" },␊
199␉{ 0x10DE016A, "GeForce 7100 GS" },␊
200␉// 0170 - 017F␉␊
201␉// 0180 - 018F␉␊
202␉// 0190 - 019F␉␉␊
203␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
204␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
205␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
206␉{ 0x10DE0197, "Tesla C870" },␊
207␉{ 0x10DE019D, "Quadro FX 5600" },␊
208␉{ 0x10DE019E, "Quadro FX 4600" },␊
209␉// 01A0 - 01AF␉␊
210␉// 01B0 - 01BF␉␊
211␉// 01C0 - 01CF␉␊
212␉// 01D0 - 01DF␉␉␊
213␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
214␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
215␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
216␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
217␉{ 0x10DE01D6, "GeForce Go 7200" },␊
218␉{ 0x10DE01D7, "GeForce Go 7300" },␊
219␉{ 0x10DE01D8, "GeForce Go 7400" },␊
220␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
221␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
222␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
223␉{ 0x10DE01DC, "Quadro FX 350M" },␊
224␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
225␉{ 0x10DE01DE, "Quadro FX 350" },␊
226␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
227␉// 01E0 - 01EF␉␊
228␉// 01F0 - 01FF␊
229␉// 0200 - 020F␉␊
230␉// 0210 - 021F␉␊
231␉{ 0x10DE0211, "GeForce 6800" },␊
232␉{ 0x10DE0212, "GeForce 6800 LE" },␊
233␉{ 0x10DE0215, "GeForce 6800 GT" },␊
234␉{ 0x10DE0218, "GeForce 6800 XT" },␊
235␉// 0220 - 022F␉␊
236␉{ 0x10DE0221, "GeForce 6200" },␊
237␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
238␉// 0230 - 023F␉␊
239␉// 0240 - 024F␉␊
240␉{ 0x10DE0240, "GeForce 6150" },␊
241␉{ 0x10DE0241, "GeForce 6150 LE" },␊
242␉{ 0x10DE0242, "GeForce 6100" },␊
243␉{ 0x10DE0244, "GeForce Go 6150" },␊
244␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
245␉{ 0x10DE0247, "GeForce Go 6100" },␊
246␉// 0250 - 025F␉␊
247␉// 0260 - 026F␉␊
248␉// 0270 - 027F␉␊
249␉// 0280 - 028F␉␉␊
250␉// 0290 - 029F␉␊
251␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
252␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
253␉{ 0x10DE0292, "GeForce 7900 GS" },␊
254␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
255␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
256␉{ 0x10DE0295, "GeForce 7950 GT" },␊
257␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
258␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
259␉{ 0x10DE029A, "Quadro FX 2500M" },␊
260␉{ 0x10DE029B, "Quadro FX 1500M" },␊
261␉{ 0x10DE029C, "Quadro FX 5500" },␊
262␉{ 0x10DE029D, "Quadro FX 3500" },␊
263␉{ 0x10DE029E, "Quadro FX 1500" },␊
264␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
265␉// 02A0 - 02AF␉␊
266␉// 02B0 - 02BF␉␊
267␉// 02C0 - 02CF␉␊
268␉// 02D0 - 02DF␉␉␊
269␉// 02E0 - 02EF␉␉␊
270␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
271␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
272␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
273␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
274␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
275␉// 02F0 - 02FF␉␉␊
276␉// 0300 - 030F␉␉␊
277␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
278␉{ 0x10DE0302, "GeForce FX 5800" },␊
279␉{ 0x10DE0308, "Quadro FX 2000" },␊
280␉{ 0x10DE0309, "Quadro FX 1000" },␊
281␉// 0310 - 031F␉␉␊
282␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
283␉{ 0x10DE0312, "GeForce FX 5600" },␊
284␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
285␉{ 0x10DE031A, "GeForce FX Go5600" },␊
286␉{ 0x10DE031B, "GeForce FX Go5650" },␊
287␉{ 0x10DE031C, "Quadro FX Go700" },␊
288␉// 0320 - 032F␉␉␊
289␉{ 0x10DE0324, "GeForce FX Go5200" },␊
290␉{ 0x10DE0325, "GeForce FX Go5250" },␊
291␉{ 0x10DE0326, "GeForce FX 5500" },␊
292␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
293␉{ 0x10DE0329, "GeForce FX Go5200" }, //␊
294␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
295␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
296␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
297␉{ 0x10DE032D, "GeForce FX Go5100" },␊
298␉// 0330 - 033F␊
299␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
300␉{ 0x10DE0331, "GeForce FX 5900" },␊
301␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
302␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
303␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
304␉{ 0x10DE0338, "Quadro FX 3000" },␊
305␉{ 0x10DE033F, "Quadro FX 700" },␊
306␉// 0340 - 034F␊
307␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
308␉{ 0x10DE0342, "GeForce FX 5700" },␊
309␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
310␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
311␉{ 0x10DE0347, "GeForce FX Go5700" },␊
312␉{ 0x10DE0348, "GeForce FX Go5700" },␊
313␉{ 0x10DE034C, "Quadro FX Go1000" },␊
314␉{ 0x10DE034E, "Quadro FX 1100" },␊
315␉// 0350 - 035F␉␊
316␉// 0360 - 036F␉␊
317␉// 0370 - 037F␉␊
318␉// 0380 - 038F␉␉␉␊
319␉{ 0x10DE038B, "GeForce 7650 GS" },␊
320␉// 0390 - 039F␊
321␉{ 0x10DE0390, "GeForce 7650 GS" },␊
322␉{ 0x10DE0391, "GeForce 7600 GT" },␊
323␉{ 0x10DE0392, "GeForce 7600 GS" },␊
324␉{ 0x10DE0393, "GeForce 7300 GT" },␊
325␉{ 0x10DE0394, "GeForce 7600 LE" },␊
326␉{ 0x10DE0395, "GeForce 7300 GT" },␊
327␉{ 0x10DE0397, "GeForce Go 7700" },␊
328␉{ 0x10DE0398, "GeForce Go 7600" },␊
329␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
330␉{ 0x10DE039A, "Quadro NVS 300M" },␊
331␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
332␉{ 0x10DE039C, "Quadro FX 550M" },␊
333␉{ 0x10DE039E, "Quadro FX 560" },␊
334␉// 03A0 - 03AF␉␊
335␉// 03B0 - 03BF␉␊
336␉// 03C0 - 03CF␉␊
337␉// 03D0 - 03DF␉␉␉␊
338␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
339␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
340␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
341␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
342␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
343␉// 03E0 - 03EF␊
344␉// 03F0 - 03FF␊
345␉// 0400 - 040F␉␉␊
346␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
347␉{ 0x10DE0401, "GeForce 8600 GT" },␊
348␉{ 0x10DE0402, "GeForce 8600 GT" },␊
349␉{ 0x10DE0403, "GeForce 8600 GS" },␊
350␉{ 0x10DE0404, "GeForce 8400 GS" },␊
351␉{ 0x10DE0405, "GeForce 9500M GS" },␊
352␉{ 0x10DE0406, "GeForce 8300 GS" },␊
353␉{ 0x10DE0407, "GeForce 8600M GT" },␊
354␉{ 0x10DE0408, "GeForce 9650M GS" },␊
355␉{ 0x10DE0409, "GeForce 8700M GT" },␊
356␉{ 0x10DE040A, "Quadro FX 370" },␊
357␉{ 0x10DE040B, "Quadro NVS 320M" },␊
358␉{ 0x10DE040C, "Quadro FX 570M" },␊
359␉{ 0x10DE040D, "Quadro FX 1600M" },␊
360␉{ 0x10DE040E, "Quadro FX 570" },␊
361␉{ 0x10DE040F, "Quadro FX 1700" },␊
362␉// 0410 - 041F␉␊
363␉{ 0x10DE0410, "GeForce GT 330" },␊
364␉// 0420 - 042F␉␊
365␉{ 0x10DE0420, "GeForce 8400 SE" },␊
366␉{ 0x10DE0421, "GeForce 8500 GT" },␊
367␉{ 0x10DE0422, "GeForce 8400 GS" },␊
368␉{ 0x10DE0423, "GeForce 8300 GS" },␊
369␉{ 0x10DE0424, "GeForce 8400 GS" },␊
370␉{ 0x10DE0425, "GeForce 8600M GS" },␊
371␉{ 0x10DE0426, "GeForce 8400M GT" },␊
372␉{ 0x10DE0427, "GeForce 8400M GS" },␊
373␉{ 0x10DE0428, "GeForce 8400M G" },␊
374␉{ 0x10DE0429, "Quadro NVS 140M" },␊
375␉{ 0x10DE042A, "Quadro NVS 130M" },␊
376␉{ 0x10DE042B, "Quadro NVS 135M" },␊
377␉{ 0x10DE042C, "GeForce 9400 GT" },␊
378␉{ 0x10DE042D, "Quadro FX 360M" },␊
379␉{ 0x10DE042E, "GeForce 9300M G" },␊
380␉{ 0x10DE042F, "Quadro NVS 290" },␊
381␉// 0430 - 043F␊
382␉// 0440 - 044F␊
383␉// 0450 - 045F␊
384␉// 0460 - 046F␊
385␉// 0470 - 047F␊
386␉// 0480 - 048F␊
387␉// 0490 - 049F␊
388␉// 04A0 - 04AF␊
389␉// 04B0 - 04BF␊
390␉// 04C0 - 04CF␊
391␉// 04D0 - 04DF␊
392␉// 04E0 - 04EF␊
393␉// 04F0 - 04FF␊
394␉// 0500 - 050F␉␊
395␉// 0510 - 051F␉␊
396␉// 0520 - 052F␉␊
397␉// 0530 - 053F␉␊
398␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
399␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
400␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
401␉// 0540 - 054F␊
402␉// 0550 - 055F␊
403␉// 0560 - 056F␊
404␉// 0570 - 057F␊
405␉// 0580 - 058F␊
406␉// 0590 - 059F␊
407␉// 05A0 - 05AF␊
408␉// 05B0 - 05BF␊
409␉// 05C0 - 05CF␊
410␉// 05D0 - 05DF␊
411␉// 05E0 - 05EF␉␊
412␉{ 0x10DE05E0, "GeForce GTX 295" },␊
413␉{ 0x10DE05E1, "GeForce GTX 280" },␊
414␉{ 0x10DE05E2, "GeForce GTX 260" },␊
415␉{ 0x10DE05E3, "GeForce GTX 285" },␊
416␉{ 0x10DE05E6, "GeForce GTX 275" },␊
417␉{ 0x10DE05E7, "Tesla C1060" },␊
418␉{ 0x10DE05EA, "GeForce GTX 260" },␊
419␉{ 0x10DE05EB, "GeForce GTX 295" },␊
420␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
421␉// 05F0 - 05FF␉␉␊
422␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
423␉{ 0x10DE05F9, "Quadro CX" },␊
424␉{ 0x10DE05FD, "Quadro FX 5800" },␊
425␉{ 0x10DE05FE, "Quadro FX 4800" },␊
426␉{ 0x10DE05FF, "Quadro FX 3800" },␊
427␉// 0600 - 060F␉␊
428␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
429␉{ 0x10DE0601, "GeForce 9800 GT" },␊
430␉{ 0x10DE0602, "GeForce 8800 GT" },␊
431␉{ 0x10DE0603, "GeForce GT 230" },␊
432␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
433␉{ 0x10DE0605, "GeForce 9800 GT" },␊
434␉{ 0x10DE0606, "GeForce 8800 GS" },␊
435␉{ 0x10DE0607, "GeForce GTS 240" },␊
436␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
437␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
438␉{ 0x10DE060A, "GeForce GTX 280M" },␊
439␉{ 0x10DE060B, "GeForce 9800M GT" },␊
440␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
441␉{ 0x10DE060D, "GeForce 8800 GS" },␊
442␉{ 0x10DE060F, "GeForce GTX 285M" },␊
443␉// 0610 - 061F␉␊
444␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
445␉{ 0x10DE0611, "GeForce 8800 GT" },␊
446␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
447␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
448␉{ 0x10DE0614, "GeForce 9800 GT" },␊
449␉{ 0x10DE0615, "GeForce GTS 250" },␊
450␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
451␉{ 0x10DE0618, "GeForce GTX 260M" },␊
452␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
453␉{ 0x10DE061A, "Quadro FX 3700" },␊
454␉{ 0x10DE061B, "Quadro VX 200" },␊
455␉{ 0x10DE061C, "Quadro FX 3600M" },␊
456␉{ 0x10DE061D, "Quadro FX 2800M" },␊
457␉{ 0x10DE061E, "Quadro FX 3700M" },␊
458␉{ 0x10DE061F, "Quadro FX 3800M" },␊
459␉// 0620 - 062F␉␊
460//␉{ 0x10DE0620, "Unknown" },␊
461␉{ 0x10DE0621, "GeForce GT 230" },␊
462␉{ 0x10DE0622, "GeForce 9600 GT" },␊
463␉{ 0x10DE0623, "GeForce 9600 GS" },␊
464␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
465␉{ 0x10DE0626, "GeForce GT 130" },␊
466␉{ 0x10DE0627, "GeForce GT 140" },␊
467␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
468//␉{ 0x10DE0629, "Unknown" },␊
469␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
470␉{ 0x10DE062B, "GeForce 9800M GS" },␊
471␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
472␉{ 0x10DE062D, "GeForce 9600 GT" },␊
473␉{ 0x10DE062E, "GeForce 9600 GT" },␊
474//␉{ 0x10DE062F, "Unknown" },␊
475␉// 0630 - 063F␉␊
476//␉{ 0x10DE0630, "Unknown" },␊
477␉{ 0x10DE0631, "GeForce GTS 160M" },␊
478␉{ 0x10DE0632, "GeForce GTS 150M" },␊
479//␉{ 0x10DE0633, "Unknown" },␊
480//␉{ 0x10DE0634, "Unknown" },␊
481␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
482//␉{ 0x10DE0636, "Unknown" },␊
483␉{ 0x10DE0637, "GeForce 9600 GT" },␊
484␉{ 0x10DE0638, "Quadro FX 1800" },␊
485//␉{ 0x10DE0639, "Unknown" },␊
486␉{ 0x10DE063A, "Quadro FX 2700M" },␊
487//␉{ 0x10DE063B, "Unknown" },␊
488//␉{ 0x10DE063C, "Unknown" },␊
489//␉{ 0x10DE063D, "Unknown" },␊
490//␉{ 0x10DE063E, "Unknown" },␊
491//␉{ 0x10DE063F, "Unknown" },␊
492␉// 0640 - 064F␉␊
493␉{ 0x10DE0640, "GeForce 9500 GT" },␊
494␉{ 0x10DE0641, "GeForce 9400 GT" },␊
495␉{ 0x10DE0642, "GeForce 8400 GS" },␊
496␉{ 0x10DE0643, "GeForce 9500 GT" },␊
497␉{ 0x10DE0644, "GeForce 9500 GS" },␊
498␉{ 0x10DE0645, "GeForce 9500 GS" },␊
499␉{ 0x10DE0646, "GeForce GT 120" },␊
500␉{ 0x10DE0647, "GeForce 9600M GT" },␊
501␉{ 0x10DE0648, "GeForce 9600M GS" },␊
502␉{ 0x10DE0649, "GeForce 9600M GT" },␊
503␉{ 0x10DE064A, "GeForce 9700M GT" },␊
504␉{ 0x10DE064B, "GeForce 9500M G" },␊
505␉{ 0x10DE064C, "GeForce 9650M GT" },␊
506␉// 0650 - 065F␉␉␊
507␉{ 0x10DE0651, "GeForce G 110M" },␊
508␉{ 0x10DE0652, "GeForce GT 130M" },␊
509␉{ 0x10DE0653, "GeForce GT 120M" },␊
510␉{ 0x10DE0654, "GeForce GT 220M" },␊
511␉{ 0x10DE0655, "GeForce GT 120" },␊
512␉{ 0x10DE0656, "GeForce 9650 S" },␊
513␉{ 0x10DE0658, "Quadro FX 380" },␊
514␉{ 0x10DE0659, "Quadro FX 580" },␊
515␉{ 0x10DE065A, "Quadro FX 1700M" },␊
516␉{ 0x10DE065B, "GeForce 9400 GT" },␊
517␉{ 0x10DE065C, "Quadro FX 770M" },␊
518␉{ 0x10DE065F, "GeForce G210" },␊
519␉// 0660 - 066F␊
520␉// 0670 - 067F␊
521␉// 0680 - 068F␊
522␉// 0690 - 069F␊
523␉// 06A0 - 06AF␊
524␉// 06B0 - 06BF␊
525␉// 06C0 - 06CF␊
526␉{ 0x10DE06C0, "GeForce GTX 480" },␊
527␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
528␉{ 0x10DE06C4, "GeForce GTX 465" },␊
529␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
530␉{ 0x10DE06CD, "GeForce GTX 470" },␊
531␉// 06D0 - 06DF␊
532␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
533␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
534␉{ 0x10DE06D2, "Tesla M2070" },␊
535␉{ 0x10DE06D8, "Quadro 6000" },␊
536␉{ 0x10DE06D9, "Quadro 5000" },␊
537␉{ 0x10DE06DA, "Quadro 5000M" },␊
538␉{ 0x10DE06DC, "Quadro 6000" },␊
539␉{ 0x10DE06DD, "Quadro 4000" },␊
540␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
541␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
542␉{ 0x10DE06DF, "Tesla M2070-Q" },␊
543␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
544␉// 06E0 - 06EF␉␊
545␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
546␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
547␉{ 0x10DE06E2, "GeForce 8400" },␊
548␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
549␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
550␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
551␉{ 0x10DE06E6, "GeForce G100" },␊
552␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
553␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
554␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
555␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
556␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
557␉{ 0x10DE06EC, "GeForce G 105M" },␊
558␉{ 0x10DE06EF, "GeForce G 103M" },␊
559␉// 06F0 - 06FF␉␊
560␉{ 0x10DE06F1, "GeForce G105M" },␊
561␉{ 0x10DE06F8, "Quadro NVS 420" },␊
562␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
563␉{ 0x10DE06FA, "Quadro NVS 450" },␊
564␉{ 0x10DE06FB, "Quadro FX 370M" },␊
565␉{ 0x10DE06FD, "Quadro NVS 295" },␊
566␉{ 0x10DE06FF, "HICx16 + Graphics" },␊
567␉// 0700 - 070F␊
568␉// 0710 - 071F␊
569␉// 0720 - 072F␊
570␉// 0730 - 073F␊
571␉// 0740 - 074F␊
572␉// 0750 - 075F␊
573␉// 0760 - 076F␊
574␉// 0770 - 077F␊
575␉// 0780 - 078F␊
576␉// 0790 - 079F␊
577␉// 07A0 - 07AF␊
578␉// 07B0 - 07BF␊
579␉// 07C0 - 07CF␊
580␉// 07D0 - 07DF␉␊
581␉// 07E0 - 07EF␉␉␊
582␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
583␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
584␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
585␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
586␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
587␉// 07F0 - 07FF␉␊
588␉// 0800 - 080F␊
589␉// 0810 - 081F␊
590␉// 0820 - 082F␊
591␉// 0830 - 083F␊
592␉// 0840 - 084F␊
593␉{ 0x10DE0840, "GeForce 8200M" },␊
594␉{ 0x10DE0844, "GeForce 9100M G" },␊
595␉{ 0x10DE0845, "GeForce 8200M G" },␊
596␉{ 0x10DE0846, "GeForce 9200" },␊
597␉{ 0x10DE0847, "GeForce 9100" },␊
598␉{ 0x10DE0848, "GeForce 8300" },␊
599␉{ 0x10DE0849, "GeForce 8200" },␊
600␉{ 0x10DE084A, "nForce 730a" },␊
601␉{ 0x10DE084B, "GeForce 9200" },␊
602␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
603␉{ 0x10DE084D, "nForce 750a SLI" },␊
604␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
605␉// 0850 - 085F␊
606//␉{ 0x10DE0850, "Unknown" },␊
607//␉{ 0x10DE0851, "Unknown" },␊
608//␉{ 0x10DE0852, "Unknown" },␊
609//␉{ 0x10DE0853, "Unknown" },␊
610//␉{ 0x10DE0854, "Unknown" },␊
611//␉{ 0x10DE0855, "Unknown" },␊
612//␉{ 0x10DE0856, "Unknown" },␊
613//␉{ 0x10DE0857, "Unknown" },␊
614//␉{ 0x10DE0858, "Unknown" },␊
615//␉{ 0x10DE0859, "Unknown" },␊
616//␉{ 0x10DE085A, "Unknown" },␊
617//␉{ 0x10DE085B, "Unknown" },␊
618//␉{ 0x10DE085C, "Unknown" },␊
619//␉{ 0x10DE085D, "Unknown" },␊
620//␉{ 0x10DE085E, "Unknown" },␊
621//␉{ 0x10DE085F, "Unknown" },␊
622␉// 0860 - 086F␉␊
623␉{ 0x10DE0860, "GeForce 9300" }, //␊
624␉{ 0x10DE0861, "GeForce 9400" },␊
625␉{ 0x10DE0862, "GeForce 9400M G" },␊
626␉{ 0x10DE0863, "GeForce 9400M" },␊
627␉{ 0x10DE0864, "GeForce 9300" },␊
628␉{ 0x10DE0865, "GeForce 9300" }, //␊
629␉{ 0x10DE0866, "GeForce 9400M G" },␊
630␉{ 0x10DE0867, "GeForce 9400" },␊
631␉{ 0x10DE0868, "nForce 760i SLI" },␊
632␉{ 0x10DE0869, "GeForce 9400" },␊
633␉{ 0x10DE086A, "GeForce 9400" },␊
634␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
635␉{ 0x10DE086D, "GeForce 9200" },␊
636␉{ 0x10DE086E, "GeForce 9100M G" },␊
637␉{ 0x10DE086F, "GeForce 8200M G" },␊
638␉// 0870 - 087F␉␊
639␉{ 0x10DE0870, "GeForce 9400M" },␊
640␉{ 0x10DE0871, "GeForce 9200" },␊
641␉{ 0x10DE0872, "GeForce G102M" },␊
642␉{ 0x10DE0873, "GeForce G102M" },␊
643␉{ 0x10DE0874, "ION 9300M" },␉␊
644␉{ 0x10DE0876, "GeForce 9400M" }, //␊
645␉{ 0x10DE087A, "GeForce 9400" },␊
646␉{ 0x10DE087D, "ION 9400M" },␊
647␉{ 0x10DE087E, "ION LE" },␊
648␉{ 0x10DE087F, "ION LE" },␊
649␉// 0880 - 088F␊
650␉// 0890 - 089F␊
651␉// 08A0 - 08AF␊
652␉{ 0x10DE08A0, "GeForce 320M" },␊
653//␉{ 0x10DE08A1, "Unknown" },␊
654//␉{ 0x10DE08A2, "Unknown" },␊
655␉{ 0x10DE08A3, "GeForce 320M" },␊
656␉{ 0x10DE08A4, "GeForce 320M" },␊
657//␉{ 0x10DE08A5, "Unknown" },␊
658␉// 08B0 - 08BF␊
659//␉{ 0x10DE08B0, "Unknown" },␊
660//␉{ 0x10DE08B1, "Unknown" },␊
661//␉{ 0x10DE08B2, "Unknown" },␊
662//␉{ 0x10DE08B3, "Unknown" },␊
663␉// 08C0 - 08CF␊
664␉// 08D0 - 08DF␉␊
665␉// 08E0 - 08EF␉␉␉␊
666␉// 08F0 - 08FF␊
667␉// 0900 - 090F␊
668␉// 0910 - 091F␊
669␉// 0920 - 092F␊
670␉// 0930 - 093F␊
671␉// 0940 - 094F␊
672␉// 0950 - 095F␊
673␉// 0960 - 096F␊
674␉// 0970 - 097F␊
675␉// 0980 - 098F␊
676␉// 0990 - 099F␊
677␉// 09A0 - 09AF␊
678␉// 09B0 - 09BF␊
679␉// 09C0 - 09CF␊
680␉// 09D0 - 09DF␉␊
681␉// 09E0 - 09EF␊
682␉// 09F0 - 09FF␊
683␉// 0A00 - 0A0F␊
684␉// 0A10 - 0A1F␊
685␉// 0A20 - 0A2F␊
686␉{ 0x10DE0A20, "GeForce GT 220" }, // subsystem 10de:0a20:1043:8311␊
687␉{ 0x10DE0A22, "GeForce 315" },␊
688␉{ 0x10DE0A23, "GeForce 210" },␊
689␉{ 0x10DE0A26, "GeForce 405" },␊
690␉{ 0x10DE0A27, "GeForce 405" },␊
691␉{ 0x10DE0A28, "GeForce GT 230M" },␊
692␉{ 0x10DE0A29, "GeForce GT 330M" },␊
693␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
694␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
695␉{ 0x10DE0A2C, "NVS 5100M" },␊
696␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊
697␉// 0A30 - 0A3F␉␊
698␉{ 0x10DE0A34, "GeForce GT 240M" },␊
699␉{ 0x10DE0A35, "GeForce GT 325M" },␊
700␉{ 0x10DE0A38, "Quadro 400" },␊
701␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
702//␉{ 0x10DE0A3D, "Unknown" },␊
703//␉{ 0x10DE0A3F, "Unknown" },␊
704␉// 0A40 - 0A4F␊
705␉// 0A50 - 0A5F␊
706␉// 0A60 - 0A6F␊
707␉{ 0x10DE0A60, "GeForce G210" },␊
708␉{ 0x10DE0A62, "GeForce 205" },␊
709␉{ 0x10DE0A63, "GeForce 310" },␊
710␉{ 0x10DE0A64, "ION" },␊
711␉{ 0x10DE0A65, "GeForce 210" }, // subsystem 10de:0a65:1043:8334␊
712␉{ 0x10DE0A66, "GeForce 310" },␊
713␉{ 0x10DE0A67, "GeForce 315" },␊
714␉{ 0x10DE0A68, "GeForce G105M" },␊
715␉{ 0x10DE0A69, "GeForce G105M" },␊
716␉{ 0x10DE0A6A, "NVS 2100M" },␊
717␉{ 0x10DE0A6C, "NVS 3100M" }, // subsystem 10de:0a6c:1028:040b & 10de:0a6c:17aa:2142␊
718␉{ 0x10DE0A6E, "GeForce 305M" },␊
719␉{ 0x10DE0A6F, "ION" },␉␊
720␉// 0A70 - 0A7F␊
721␉{ 0x10DE0A70, "GeForce 310M" },␊
722␉{ 0x10DE0A71, "GeForce 305M" },␊
723␉{ 0x10DE0A72, "GeForce 310M" },␊
724␉{ 0x10DE0A73, "GeForce 305M" },␊
725␉{ 0x10DE0A74, "GeForce G210M" },␊
726␉{ 0x10DE0A75, "GeForce G310M" },␊
727␉{ 0x10DE0A76, "ION" },␊
728␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
729//␉{ 0x10DE0A79, "Unknown" },␊
730␉{ 0x10DE0A7A, "GeForce 315M" },␊
731␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
732//␉{ 0x10DE0A7D, "Unknown" },␊
733//␉{ 0x10DE0A7E, "Unknown" },␊
734//␉{ 0x10DE0A7F, "Unknown" },␊
735␉// 0A80 - 0A8F␊
736␉// 0A90 - 0A9F␊
737␉// 0AA0 - 0AAF␊
738␉// 0AB0 - 0ABF␊
739␉// 0AC0 - 0ACF␊
740␉// 0AD0 - 0ADF␉␊
741␉// 0AE0 - 0AEF␊
742␉// 0AF0 - 0AFF␊
743␉// 0B00 - 0B0F␊
744␉// 0B10 - 0B1F␊
745␉// 0B20 - 0B2F␊
746␉// 0B30 - 0B3F␊
747␉// 0B40 - 0B4F␊
748␉// 0B50 - 0B5F␊
749␉// 0B60 - 0B6F␊
750␉// 0B70 - 0B7F␊
751␉// 0B80 - 0B8F␊
752␉// 0B90 - 0B9F␊
753␉// 0BA0 - 0BAF␊
754␉// 0BB0 - 0BBF␊
755␉// 0BC0 - 0BCF␊
756␉// 0BD0 - 0BDF␉␊
757␉// 0BE0 - 0BEF␊
758␉// 0BF0 - 0BFF␊
759␉// 0C00 - 0C0F␊
760␉// 0C10 - 0C1F␊
761␉// 0C20 - 0C2F␊
762␉// 0C30 - 0C3F␊
763␉// 0C40 - 0C4F␊
764␉// 0C50 - 0C5F␊
765␉// 0C60 - 0C6F␊
766␉// 0C70 - 0C7F␊
767␉// 0C80 - 0C8F␊
768␉// 0C90 - 0C9F␊
769␉// 0CA0 - 0CAF␊
770␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
771␉{ 0x10DE0CA2, "GeForce GT 320" },␊
772␉{ 0x10DE0CA3, "GeForce GT 240" },␊
773␉{ 0x10DE0CA4, "GeForce GT 340" },␊
774␉{ 0x10DE0CA5, "GeForce GT 220" },␊
775␉{ 0x10DE0CA7, "GeForce GT 330" },␊
776␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
777␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
778␉{ 0x10DE0CAC, "GeForce GT 220" },␊
779//␉{ 0x10DE0CAD, "Unknown" },␊
780//␉{ 0x10DE0CAE, "Unknown" },␊
781␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
782␉// 0CB0 - 0CBF␉␊
783␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
784␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
785␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
786␉// 0CC0 - 0CCF␊
787␉// 0CD0 - 0CDF␉␊
788␉// 0CE0 - 0CEF␊
789␉// 0CF0 - 0CFF␊
790␉// 0D00 - 0D0F␊
791␉// 0D10 - 0D1F␊
792␉// 0D20 - 0D2F␊
793␉// 0D30 - 0D3F␊
794␉// 0D40 - 0D4F␊
795␉// 0D50 - 0D5F␊
796␉// 0D60 - 0D6F␊
797␉// 0D70 - 0D7F␊
798␉// 0D80 - 0D8F␊
799␉// 0D90 - 0D9F␊
800␉// 0DA0 - 0DAF␉␊
801␉// 0DB0 - 0DBF␊
802␉// 0DC0 - 0DCF␊
803␉{ 0x10DE0DC0, "GeForce GT 440" },␊
804␉{ 0x10DE0DC1, "D12-P1-35" },␊
805␉{ 0x10DE0DC2, "D12-P1-35" },␊
806␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
807␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
808␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
809␉{ 0x10DE0DCA, "GF10x" },␊
810//␉{ 0x10DE0DCC, "Unknown" },␊
811␉{ 0x10DE0DCD, "GeForce GT 555M" },␊
812␉{ 0x10DE0DCE, "GeForce GT 555M" },␊
813//␉{ 0x10DE0DCF, "Unknown" },␊
814␉// 0DD0 - 0DDF␉␊
815//␉{ 0x10DE0DD0, "Unknown" },␊
816␉{ 0x10DE0DD1, "GeForce GTX 460M" }, // subsystem 10de:0dd1:1558:8687␊
817␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
818␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
819␉{ 0x10DE0DD6, "GeForce GT 550M" },␊
820␉{ 0x10DE0DD8, "Quadro 2000" },␊
821␉{ 0x10DE0DDA, "Quadro 2000M" },␊
822␉{ 0x10DE0DDE, "GF106-ES" },␊
823␉{ 0x10DE0DDF, "GF106-INT" },␊
824␉// 0DE0 - 0DEF␉␊
825␉{ 0x10DE0DE0, "GeForce GT 440" },␊
826␉{ 0x10DE0DE1, "GeForce GT 430" }, // subsystem 10de:0de1:3842:1430␊
827␉{ 0x10DE0DE2, "GeForce GT 420" },␊
828␉{ 0x10DE0DE5, "GeForce GT 530" },␊
829//␉{ 0x10DE0DE8, "Unknown" },␊
830␉{ 0x10DE0DE9, "GeForce GT 600M" }, //␊
831␉{ 0x10DE0DEA, "GeForce GT 610M" },␊
832␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
833␉{ 0x10DE0DEC, "GeForce GT 525M" },␊
834␉{ 0x10DE0DED, "GeForce GT 520M" },␊
835␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
836//␉{ 0x10DE0DEF, "Unknown" },␊
837␉// 0DF0 - 0DFF␉␊
838␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
839␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
840␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
841␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
842␉{ 0x10DE0DF4, "GeForce GT 540M" },␊
843␉{ 0x10DE0DF5, "GeForce GT 525M" },␊
844␉{ 0x10DE0DF6, "GeForce GT 550M" },␊
845␉{ 0x10DE0DF7, "GeForce GT 520M" },␊
846␉{ 0x10DE0DF8, "Quadro 600" },␊
847//␉{ 0x10DE0DF9, "Unknown" },␊
848␉{ 0x10DE0DFA, "Quadro 1000M" },␊
849//␉{ 0x10DE0DFC, "Unknown" },␊
850␉{ 0x10DE0DFE, "GF108 ES" },␊
851␉{ 0x10DE0DFF, "GF108 INT" },␊
852␉// 0E00 - 0E0F␊
853␉// 0E10 - 0E1F␊
854␉// 0E20 - 0E2F␊
855␉{ 0x10DE0E21, "D12U-25" },␊
856␉{ 0x10DE0E22, "GeForce GTX 460" }, // subsystem 10de:0e22:1462:2322␊
857␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
858␉{ 0x10DE0E24, "GeForce GTX 460" },␊
859␉{ 0x10DE0E25, "D12U-50" },␊
860␉// 0E30 - 0E3F␉␊
861␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
862␉{ 0x10DE0E31, "GeForce GTX 485M" },␊
863//␉{ 0x10DE0E32, "Unknown" },␊
864␉{ 0x10DE0E38, "GF104GL" },␊
865␉{ 0x10DE0E3A, "Quadro 3000M" },␊
866␉{ 0x10DE0E3B, "Quadro 4000M" },␊
867␉{ 0x10DE0E3E, "GF104-ES" },␊
868␉{ 0x10DE0E3F, "GF104-INT" },␊
869␉// 0E40 - 0E4F␉␊
870␉// 0E50 - 0E5F␊
871␉// 0E60 - 0E6F␊
872␉// 0E70 - 0E7F␊
873␉// 0E80 - 0E8F␊
874␉// 0E90 - 0E9F␊
875␉// 0EA0 - 0EAF␊
876␉// 0EB0 - 0EBF␊
877␉// 0EC0 - 0ECF␊
878␉// 0ED0 - 0EDF␉␊
879␉// 0EE0 - 0EEF␊
880␉// 0EF0 - 0EFF␊
881␉// 0F00 - 0F0F␊
882␉// 0F10 - 0F1F␊
883␉// 0F20 - 0F2F␊
884␉// 0F30 - 0F3F␊
885␉// 0F40 - 0F4F␊
886␉// 0F50 - 0F5F␊
887␉// 0F60 - 0F6F␊
888␉// 0F70 - 0F7F␊
889␉// 0F80 - 0F8F␊
890␉// 0F90 - 0F9F␊
891␉// 0FA0 - 0FAF␊
892␉// 0FB0 - 0FBF␊
893␉// 0FC0 - 0FCF␊
894␉// 0FD0 - 0FDF␊
895␉{ 0x10DE0FD2, "GeForce GT 640M" },␊
896␉// 0FE0 - 0FEF␊
897␉// 0FF0 - 0FFF␊
898␉// 1000 - 100F␊
899␉// 1010 - 101F␊
900␉// 1020 - 102F␊
901␉// 1030 - 103F␊
902␉// 1040 - 104F␊
903␉{ 0x10DE1040, "GeForce GT 520" },␊
904␉// 1050 - 105F␊
905␉{ 0x10DE1050, "GeForce GT 520M" },␊
906␉{ 0x10DE1051, "GeForce GT 520MX" },␊
907//␉{ 0x10DE1052, "Unknown" },␊
908␉{ 0x10DE1054, "GeForce GT 410M" },␊
909␉{ 0x10DE1055, "GeForce 410M" },␊
910␉{ 0x10DE1056, "Quadro NVS 4200M" },␊
911␉{ 0x10DE1057, "Quadro NVS 4200M" },␊
912//␉{ 0x10DE1058, "Unknown" },␊
913//␉{ 0x10DE1059, "Unknown" },␊
914//␉{ 0x10DE105A, "Unknown" },␊
915␉// 1060 - 106F␊
916␉// 1070 - 107F␊
917//␉{ 0x10DE107D, "Unknown" },␊
918//␉{ 0x10DE107E, "Unknown" },␊
919␉{ 0x10DE107F, "NVIDIA GF119-ES" },␊
920␉// 1080 - 108F␊
921␉{ 0x10DE1080, "GeForce GTX 580" },␊
922␉{ 0x10DE1081, "GeForce GTX 570" }, // subsystem 10de:1081:10de:087e␊
923␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
924␉{ 0x10DE1083, "D13U" },␊
925␉{ 0x10DE1084, "GeForce GTX 560" },␊
926␉{ 0x10DE1086, "GeForce GTX 570" },␊
927␉{ 0x10DE1087, "GeForce GTX 560 Ti-448" },␊
928␉{ 0x10DE1088, "GeForce GTX 590" },␊
929␉{ 0x10DE1089, "GeForce GTX 580" },␊
930␉{ 0x10DE108B, "GeForce GTX 590" },␊
931␉// 1090 - 109F␉␊
932␉{ 0x10DE1091, "Tesla M2090" },␊
933␉{ 0x10DE1094, "Tesla M2075 Dual-Slot Computing Processor Module" },␊
934␉{ 0x10DE1096, "Tesla C2075" },␊
935␉{ 0x10DE1098, "D13U" },␊
936␉{ 0x10DE109A, "Quadro 5010M" },␊
937␉{ 0x10DE109B, "Quadro 7000" },␊
938␉// 10A0 - 10AF␊
939␉// 10B0 - 10BF␊
940␉// 10C0 - 10CF␊
941␉{ 0x10DE10C0, "GeForce 9300 GS" },␊
942␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
943//␉{ 0x10DE10C4, "Unknown" },␊
944␉{ 0x10DE10C5, "GeForce 405" },␊
945␉// 10D0 - 10DF␊
946␉{ 0x10DE10D8, "NVS 300" },␊
947␉// 1100 - ␊
948␊
949␉// 1200 - ␊
950␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
951␉{ 0x10DE1201, "GeForce GTX 560" },␊
952␉{ 0x10DE1205, "GeForce GTX 460 v2" },␊
953␉{ 0x10DE1208, "GeForce GTX 560 SE" },␊
954␉{ 0x10DE1210, "GeForce GTX 570M" },␊
955␉{ 0x10DE1211, "GeForce GTX 580M" },␊
956␉{ 0x10DE1212, "GeForce GTX 675M" },␊
957␉{ 0x10DE1213, "GeForce GTX 670M" },␊
958//␉{ 0x10DE1240, "Unknown" },␊
959␉{ 0x10DE1241, "GeForce GT 545" },␊
960␉{ 0x10DE1243, "GeForce GT 545" },␊
961␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
962␉{ 0x10DE1245, "GeForce GTS 450" },␊
963␉{ 0x10DE1246, "GeForce GTX 550M" },␊
964␉{ 0x10DE1247, "GeForce GTX 555M" },␊
965␉{ 0x10DE1248, "GeForce GTX 555M" },␊
966␉{ 0x10DE124D, "GeForce GTX 555M" },␊
967//␉{ 0x10DE1250, "Unknown" },␊
968␉{ 0x10DE1251, "GeForce GTX 560M" },␊
969};␊
970␊
971static uint16_t swap16(uint16_t x)␊
972{␊
973␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
974}␊
975␊
976static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
977{␊
978␉uint8_t ret[2];␊
979␊
980␉ret[0] = ptr[offset+1];␊
981␉ret[1] = ptr[offset];␊
982␊
983␉return *((uint16_t*)&ret);␊
984}␊
985␊
986#if 0␊
987static uint32_t swap32(uint32_t x)␊
988{␊
989␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
990}␊
991␊
992static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
993{ ␊
994␉return ptr[offset];␊
995}␊
996␊
997static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
998{␊
999␉uint8_t ret[4];␊
1000␊
1001␉ret[0] = ptr[offset+3];␊
1002␉ret[1] = ptr[offset+2];␊
1003␉ret[2] = ptr[offset+1];␊
1004␉ret[3] = ptr[offset];␊
1005␊
1006␉return *((uint32_t*)&ret);␊
1007}␊
1008#endif␊
1009␊
1010static int patch_nvidia_rom(uint8_t *rom)␊
1011{␊
1012␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
1013␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
1014␉␉return PATCH_ROM_FAILED;␊
1015␉}␊
1016␉␊
1017␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
1018␊
1019␉if (!dcbptr) {␊
1020␉␉printf("no dcb table found\n");␊
1021␉␉return PATCH_ROM_FAILED;␊
1022␉}␊
1023//␉else␊
1024//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
1025␉ ␊
1026␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
1027␉uint8_t dcbtable_version = dcbtable[0];␊
1028␉uint8_t headerlength␉ = 0;␊
1029␉uint8_t numentries␉␉ = 0;␊
1030␉uint8_t recordlength␉ = 0;␊
1031␉␊
1032␉if (dcbtable_version >= 0x20)␊
1033␉{␊
1034␉␉uint32_t sig;␊
1035␉␉␊
1036␉␉if (dcbtable_version >= 0x30)␊
1037␉␉{␊
1038␉␉␉headerlength = dcbtable[1];␊
1039␉␉␉numentries␉ = dcbtable[2];␊
1040␉␉␉recordlength = dcbtable[3];␊
1041␊
1042␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
1043␉␉}␊
1044␉␉else␊
1045␉␉{␊
1046␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
1047␉␉␉headerlength = 8;␊
1048␉␉}␊
1049␉␉␊
1050␉␉if (sig != 0x4edcbdcb)␊
1051␉␉{␊
1052␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
1053␉␉␉return PATCH_ROM_FAILED;␊
1054␉␉}␊
1055␉}␊
1056␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
1057␉{␊
1058␉␉char sig[8] = { 0 };␊
1059␉␉␊
1060␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
1061␉␉recordlength = 10;␊
1062␉␉␊
1063␉␉if (strcmp(sig, "DEV_REC"))␊
1064␉␉{␊
1065␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
1066␉␉␉return PATCH_ROM_FAILED;␊
1067␉␉}␊
1068␉}␊
1069␉else␊
1070␉{␊
1071␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
1072␉␉return PATCH_ROM_FAILED;␊
1073␉}␊
1074␉␊
1075␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
1076␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
1077␉␊
1078␉uint8_t num_outputs = 0, i = 0;␊
1079␉␊
1080␉struct dcbentry␊
1081␉{␊
1082␉␉uint8_t type;␊
1083␉␉uint8_t index;␊
1084␉␉uint8_t *heads;␊
1085␉} entries[numentries];␊
1086␉␊
1087␉for (i = 0; i < numentries; i++)␊
1088␉{␊
1089␉␉uint32_t connection;␊
1090␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
1091␊
1092␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1093␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1094␉␉␉continue;␊
1095␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1096␉␉␉continue;␊
1097␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1098␉␉␉continue;␊
1099␉␉␊
1100␉␉entries[num_outputs].type = connection & 0xf;␊
1101␉␉entries[num_outputs].index = num_outputs;␊
1102␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1103␉}␊
1104␉␊
1105␉int has_lvds = false;␊
1106␉uint8_t channel1 = 0, channel2 = 0;␊
1107␉␊
1108␉for (i = 0; i < num_outputs; i++)␊
1109␉{␊
1110␉␉if (entries[i].type == 3)␊
1111␉␉{␊
1112␉␉␉has_lvds = true;␊
1113␉␉␉//printf("found LVDS\n");␊
1114␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1115␉␉␉entries[i].type = TYPE_GROUPED;␊
1116␉␉}␊
1117␉}␊
1118␉␊
1119␉// if we have a LVDS output, we group the rest to the second channel␊
1120␉if (has_lvds)␊
1121␉{␊
1122␉␉for (i = 0; i < num_outputs; i++)␊
1123␉␉{␊
1124␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1125␉␉␉␉continue;␊
1126␉␉␉␊
1127␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1128␉␉␉entries[i].type = TYPE_GROUPED;␊
1129␉␉}␊
1130␉}␊
1131␉else␊
1132␉{␊
1133␉␉int x;␊
1134␉␉// we loop twice as we need to generate two channels␊
1135␉␉for (x = 0; x <= 1; x++)␊
1136␉␉{␊
1137␉␉␉for (i=0; i<num_outputs; i++)␊
1138␉␉␉{␊
1139␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1140␉␉␉␉␉continue;␊
1141␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1142␉␉␉␉// we always group ANALOG and TMDS␊
1143␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1144␉␉␉␉if (i && entries[i].type == 0x2)␊
1145␉␉␉␉{␊
1146␉␉␉␉␉switch (x)␊
1147␉␉␉␉␉{␊
1148␉␉␉␉␉␉case 0:␊
1149␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1150␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1151␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1152␉␉␉␉␉␉␉␊
1153␉␉␉␉␉␉␉if ( entries[i-1].type == 0x0 )␊
1154␉␉␉␉␉␉␉{␊
1155␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1156␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1157␉␉␉␉␉␉␉}␊
1158␉␉␉␉␉␉␉// group TV as well if there is one␊
1159␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1160␉␉␉␉␉␉␉{␊
1161␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1162␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1163␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1164␉␉␉␉␉␉␉}␊
1165␉␉␉␉␉␉␉break;␊
1166␉␉␉␉␉␉␊
1167␉␉␉␉␉␉case 1:␊
1168␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1169␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1170␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1171␉␉␉␉␉␉␉␊
1172␉␉␉␉␉␉␉if ( entries[i - 1].type == 0x0 )␊
1173␉␉␉␉␉␉␉{␊
1174␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1175␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1176␉␉␉␉␉␉␉}␊
1177␉␉␉␉␉␉␉// group TV as well if there is one␊
1178␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1179␉␉␉␉␉␉␉{␊
1180␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1181␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1182␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1183␉␉␉␉␉␉␉}␊
1184␉␉␉␉␉␉␉break;␊
1185␉␉␉␉␉}␊
1186␉␉␉␉␉break;␊
1187␉␉␉␉}␊
1188␉␉␉}␊
1189␉␉}␊
1190␉}␊
1191␉␊
1192␉// if we have left ungrouped outputs merge them to the empty channel␊
1193␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1194␉togroup = &channel2;␊
1195␉␊
1196␉for (i = 0; i < num_outputs; i++)␊
1197␉{␊
1198␉␉if (entries[i].type != TYPE_GROUPED)␊
1199␉␉{␊
1200␉␉␉//printf("%d not grouped\n", i);␊
1201␉␉␉if (togroup)␊
1202␉␉␉{␊
1203␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1204␉␉␉}␊
1205␉␉␉entries[i].type = TYPE_GROUPED;␊
1206␉␉}␊
1207␉}␊
1208␉␊
1209␉if (channel1 > channel2)␊
1210␉{␊
1211␉␉uint8_t buff = channel1;␊
1212␉␉channel1 = channel2;␊
1213␉␉channel2 = buff;␊
1214␉}␊
1215␉␊
1216␉default_NVCAP[6] = channel1;␊
1217␉default_NVCAP[8] = channel2;␊
1218␉␊
1219␉// patching HEADS␊
1220␉for (i = 0; i < num_outputs; i++)␊
1221␉{␊
1222␉␉if (channel1 & (1 << i))␊
1223␉␉{␊
1224␉␉␉*entries[i].heads = 1;␊
1225␉␉}␊
1226␉␉else if(channel2 & (1 << i))␊
1227␉␉{␊
1228␉␉␉*entries[i].heads = 2;␊
1229␉␉}␊
1230␉}␊
1231␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1232}␊
1233␊
1234static char *get_nvidia_model(uint32_t id)␊
1235{␊
1236␉int i;␊
1237␉␊
1238␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1239␉␉if (NVKnownChipsets[i].device == id)␊
1240␉␉{␊
1241␉␉␉return NVKnownChipsets[i].name;␊
1242␉␉}␊
1243␉}␊
1244␉return NVKnownChipsets[0].name;␊
1245}␊
1246␊
1247static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1248{␊
1249␉int fd;␊
1250␉int size;␊
1251␉␊
1252␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1253␉{␊
1254␉␉return 0;␊
1255␉}␊
1256␉␊
1257␉size = file_size(fd);␊
1258␉␊
1259␉if (size > bufsize)␊
1260␉{␊
1261␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1262␉␉␉␉filename, bufsize);␊
1263␉␉size = bufsize;␊
1264␉}␊
1265␉size = read(fd, (char *)buf, size);␊
1266␉close(fd);␊
1267␉␊
1268␉return size > 0 ? size : 0;␊
1269}␊
1270␊
1271static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1272{␊
1273␉char tmp[16];␊
1274␉␊
1275␉if (!device)␊
1276␉␉return 0;␊
1277␉␊
1278␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1279␉␉return 0;␊
1280␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1281␉␉return 0;␊
1282␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1283␉␉return 0;␊
1284␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1285␉␉return 0;␊
1286␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1287␉␉return 0;␊
1288␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1289␉␉return 0;␊
1290␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1291␉␉return 0;␊
1292␉␊
1293␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1294␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1295␉sprintf(tmp, "Slot-%x",devices_number);␊
1296␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1297␉devices_number++;␊
1298␉␊
1299␉return 1;␊
1300}␊
1301␊
1302int hex2bin(const char *hex, uint8_t *bin, int len)␊
1303{␊
1304␉char␉*p;␊
1305␉int␉␉i;␊
1306␉char␉buf[3];␊
1307␉␊
1308␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1309␉␉printf("[ERROR] bin2hex input error\n");␊
1310␉␉return -1;␊
1311␉}␊
1312␉␊
1313␉buf[2] = '\0';␊
1314␉p = (char *) hex;␊
1315␉␊
1316␉for (i = 0; i < len; i++)␊
1317␉{␊
1318␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1319␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1320␉␉␉return -2;␊
1321␉␉}␊
1322␉␉buf[0] = *p++;␊
1323␉␉buf[1] = *p++;␊
1324␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1325␉}␊
1326␉return 0;␊
1327}␊
1328␊
1329unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1330{␊
1331␉unsigned long long vram_size = 0;␊
1332␉␊
1333␉if (nvCardType < NV_ARCH_50)␊
1334␉{␊
1335␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1336␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1337␉}␊
1338␉else if (nvCardType < NV_ARCH_C0)␊
1339␉{␊
1340␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1341␉␉vram_size |= (vram_size & 0xff) << 32;␊
1342␉␉vram_size &= 0xffffffff00ll;␊
1343␉}␊
1344␉else // >= NV_ARCH_C0␊
1345␉{␊
1346␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1347␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1348␉}␊
1349␉␊
1350␉// Workaround for 9600M GT, GT 210/420/430/440 & GT 525M␊
1351␉switch (nvda_dev->device_id)␊
1352␉{␊
1353␉␉case 0x0647: vram_size = 512*1024*1024; break;␉// 9600M GT 0647␊
1354␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT 0649␊
1355␉␉case 0x0A65: vram_size = 1024*1024*1024; break; // GT 210␊
1356␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
1357␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1358␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1359␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M 0DEC␊
1360␉␉case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M 0DF5␊
1361␉␉default: break;␊
1362␉}␊
1363␉␊
1364␉return vram_size;␊
1365}␊
1366␊
1367bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1368{␊
1369␉struct DevPropDevice␉*device;␊
1370␉char␉␉␉␉␉*devicepath;␊
1371␉option_rom_pci_header_t *rom_pci_header;␊
1372␉volatile uint8_t␉␉*regs;␊
1373␉uint8_t␉␉␉␉␉*rom;␊
1374␉uint8_t␉␉␉␉␉*nvRom;␊
1375␉uint8_t␉␉␉␉␉nvCardType;␊
1376␉unsigned long long␉␉videoRam;␊
1377␉uint32_t␉␉␉␉nvBiosOveride;␊
1378␉uint32_t␉␉␉␉bar[7];␊
1379␉uint32_t␉␉␉␉boot_display;␊
1380␉int␉␉␉␉␉␉nvPatch;␊
1381␉int␉␉␉␉␉␉len;␊
1382␉char␉␉␉␉␉biosVersion[32];␊
1383␉char␉␉␉␉␉nvFilename[32];␊
1384␉char␉␉␉␉␉kNVCAP[12];␊
1385␉char␉␉␉␉␉*model;␊
1386␉const char␉␉␉␉*value;␊
1387␉bool␉␉␉␉␉doit;␊
1388␉␊
1389␉devicepath = get_pci_dev_path(nvda_dev);␊
1390␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1391␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1392␉␊
1393␉// get card type␊
1394␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1395␉␊
1396␉// Amount of VRAM in kilobytes␊
1397␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1398␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1399␉␊
1400␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
1401␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
1402␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1403␉␉␉devicepath);␊
1404␉␊
1405␉rom = malloc(NVIDIA_ROM_SIZE);␊
1406␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1407␉␉␉(uint16_t)nvda_dev->device_id);␊
1408␉␊
1409␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1410␉{␊
1411␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1412␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1413␉␉␊
1414␉␉if (nvBiosOveride > 0)␊
1415␉␉{␊
1416␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1417␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1418␉␉}␊
1419␉␉else␊
1420␉␉{␊
1421␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1422␉␉␉return false;␊
1423␉␉}␊
1424␉}␊
1425␉else␊
1426␉{␊
1427␉␉// Otherwise read bios from card␊
1428␉␉nvBiosOveride = 0;␊
1429␉␉␊
1430␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1431␉␉␊
1432␉␉// PRAMIN first␊
1433␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1434␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1435␉␉␊
1436␉␉// Valid Signature ?␊
1437␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1438␉␉{␊
1439␉␉␉// PROM next␊
1440␉␉␉// Enable PROM access␊
1441␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1442␉␉␉␊
1443␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1444␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1445␉␉␉␊
1446␉␉␉// disable PROM access␊
1447␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1448␉␉␉␊
1449␉␉␉// Valid Signature ?␊
1450␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1451␉␉␉{␊
1452␉␉␉␉// 0xC0000 last␊
1453␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1454␉␉␉␉␊
1455␉␉␉␉// Valid Signature ?␊
1456␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1457␉␉␉␉{␊
1458␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1459␉␉␉␉␉return false;␊
1460␉␉␉␉}␊
1461␉␉␉␉else␊
1462␉␉␉␉{␊
1463␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1464␉␉␉␉}␊
1465␉␉␉}␊
1466␉␉␉else␊
1467␉␉␉{␊
1468␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1469␉␉␉}␊
1470␉␉}␊
1471␉␉else␊
1472␉␉{␊
1473␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1474␉␉}␊
1475␉}␊
1476␉␊
1477␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1478␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1479␉␉//return false;␊
1480␉}␊
1481␉␊
1482␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1483␉␊
1484␉// check for 'PCIR' sig␊
1485␉if (rom_pci_header->signature == 0x50434952)␊
1486␉{␊
1487␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1488␉␉{␊
1489␉␉␉// Get Model from the OpROM␊
1490␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1491␉␉}␊
1492␉␉else␊
1493␉␉{␊
1494␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1495␉␉}␊
1496␉}␊
1497␉␊
1498␉if (!string) {␊
1499␉␉string = devprop_create_string();␊
1500␉}␊
1501␉device = devprop_add_device(string, devicepath);␊
1502␉␊
1503␉/* FIXME: for primary graphics card only */␊
1504␉boot_display = 1;␊
1505␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1506␉␊
1507␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1508␉␉uint8_t built_in = 0x01;␊
1509␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1510␉}␊
1511␉␊
1512␉// get bios version␊
1513␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1514␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1515␉␊
1516␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1517␉␊
1518␉int i, version_start;␊
1519␉int crlf_count = 0;␊
1520␉␊
1521␉// only search the first 384 bytes␊
1522␉for (i = 0; i < 0x180; i++)␊
1523␉{␊
1524␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1525␉␉{␊
1526␉␉␉crlf_count++;␊
1527␉␉␉// second 0x0D0A was found, extract bios version␊
1528␉␉␉if (crlf_count == 2)␊
1529␉␉␉{␊
1530␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1531␉␉␉␉␊
1532␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1533␉␉␉␉{␊
1534␉␉␉␉␉// find start␊
1535␉␉␉␉␉if (rom[version_start] == 0x00)␊
1536␉␉␉␉␉{␊
1537␉␉␉␉␉␉version_start++;␊
1538␉␉␉␉␉␉␊
1539␉␉␉␉␉␉// strip "Version "␊
1540␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1541␉␉␉␉␉␉{␊
1542␉␉␉␉␉␉␉version_start += 8;␊
1543␉␉␉␉␉␉}␊
1544␉␉␉␉␉␉␊
1545␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1546␉␉␉␉␉␉break;␊
1547␉␉␉␉␉}␊
1548␉␉␉␉}␊
1549␉␉␉␉break;␊
1550␉␉␉}␊
1551␉␉}␊
1552␉}␊
1553␉␊
1554␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1555␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1556␉␊
1557␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1558␉{␊
1559␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1560␉␉␊
1561␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1562␉␉{␊
1563␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1564␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1565␉␉}␊
1566␉}␊
1567␉␊
1568␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1569␉{␊
1570␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1571␉␉␊
1572␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1573␉␉{␊
1574␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1575␉␉␉␊
1576␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1577␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1578␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1579␉␉}␊
1580␉}␊
1581␉␊
1582␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1583␉{␊
1584␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1585␉␉␊
1586␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1587␉␉{␊
1588␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1589␉␉␉␊
1590␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1591␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1592␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1593␉␉}␊
1594␉}␊
1595␉␊
1596#if DEBUG_NVCAP␊
1597␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1598␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1599␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1600␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1601␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1602␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1603#endif␊
1604␉␊
1605␉devprop_add_nvidia_template(device);␊
1606␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1607␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1608␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1609␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1610 //␉devprop_add_value(device, "@1,connector-type", connector_type_1, 4); // fixme␊
1611 //␉devprop_add_value(device, "@0,display-cfg", display_cfg_0, 4);␊
1612 //␉devprop_add_value(device, "@1,display-cfg", display_cfg_1, 4);␊
1613␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊
1614␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1615␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1616␉␊
1617␉//add HDMI Audio back to nvidia␊
1618␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1619//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1620//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1621␉//end Nvidia HDMI Audio␊
1622␉␊
1623␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1624␉{␊
1625␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1626␉}␊
1627␉␊
1628␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1629␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1630␉stringlength = string->length;␊
1631␉␊
1632␉return true;␊
1633}␊
1634

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