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Root/branches/ErmaC/Trunk/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74␊
75extern uint32_t devices_number;␊
76␊
77const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
78const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
79const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊
80const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊
81const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
82const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
83const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
84const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
85const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
86␊
87// uint8_t display_cfg_0[]␉␉␉=␉{0x03, 0x01, 0x03, 0x00};␊
88// uint8_t display_cfg_1[]␉␉␉=␉{0xff, 0xff, 0x00, 0x01};␊
89// uint8_t connector_type_1[] ␉␉=␉{0x00, 0x08, 0x00, 0x00};␊
90␊
91static uint8_t default_NVCAP[]= {␊
92␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
93␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
94␉0x00, 0x00, 0x00, 0x00␊
95};␊
96␊
97static uint8_t default_NVPM[]= {␊
98 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
99 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
101 0x00, 0x00, 0x00, 0x00␊
102};␊
103␊
104#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
105#define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊
106␊
107static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
108static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
109␊
110#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
111#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
112␊
113static struct nv_chipsets_t NVKnownChipsets[] = {␊
114␉{ 0x00000000, "Unknown" },␊
115//========================================␊
116␉// 0040 - 004F␉␊
117␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
118␉{ 0x10DE0041, "GeForce 6800" },␊
119␉{ 0x10DE0042, "GeForce 6800 LE" },␊
120␉{ 0x10DE0043, "GeForce 6800 XE" },␊
121␉{ 0x10DE0044, "GeForce 6800 XT" },␊
122␉{ 0x10DE0045, "GeForce 6800 GT" },␊
123␉{ 0x10DE0046, "GeForce 6800 GT" },␊
124␉{ 0x10DE0047, "GeForce 6800 GS" },␊
125␉{ 0x10DE0048, "GeForce 6800 XT" },␊
126␉{ 0x10DE004D, "Quadro FX 3400" },␊
127␉{ 0x10DE004E, "Quadro FX 4000" },␊
128␉// 0050 - 005F␊
129␉// 0060 - 006F␉␊
130␉// 0070 - 007F␉␊
131␉// 0080 - 008F␉␊
132␉// 0090 - 009F␉␊
133␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
134␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
135␉{ 0x10DE0092, "GeForce 7800 GT" },␊
136␉{ 0x10DE0093, "GeForce 7800 GS" },␊
137␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
138␉{ 0x10DE0098, "GeForce Go 7800" },␊
139␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
140␉{ 0x10DE009D, "Quadro FX 4500" },␊
141␉// 00A0 - 00AF␉␊
142␉// 00B0 - 00BF␉␊
143␉// 00C0 - 00CF␉␊
144␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
145␉{ 0x10DE00C1, "GeForce 6800" },␊
146␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
147␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
148␉{ 0x10DE00C8, "GeForce Go 6800" },␊
149␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
150␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
151␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
152␉{ 0x10DE00CE, "Quadro FX 1400" },␊
153␉// 00D0 - 00DF␉␊
154␉// 00E0 - 00EF␉␊
155␉// 00F0 - 00FF␉␊
156␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
157␉{ 0x10DE00F2, "GeForce 6600" },␊
158␉{ 0x10DE00F3, "GeForce 6200" },␊
159␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
160␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
161␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
162␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
163␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
164␉// 0100 - 010F␉␊
165␉// 0110 - 011F␉␊
166␉// 0120 - 012F␉␊
167␉// 0130 - 013F␉␊
168␉// 0140 - 014F␉␊
169␉{ 0x10DE0140, "GeForce 6600 GT" },␊
170␉{ 0x10DE0141, "GeForce 6600" },␊
171␉{ 0x10DE0142, "GeForce 6600 LE" },␊
172␉{ 0x10DE0143, "GeForce 6600 VE" },␊
173␉{ 0x10DE0144, "GeForce Go 6600" },␊
174␉{ 0x10DE0145, "GeForce 6610 XL" },␊
175␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
176␉{ 0x10DE0147, "GeForce 6700 XL" },␊
177␉{ 0x10DE0148, "GeForce Go 6600" },␊
178␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
179␉{ 0x10DE014A, "Quadro NVS 440" },␊
180␉{ 0x10DE014C, "Quadro FX 550" },␊
181␉{ 0x10DE014D, "Quadro FX 550" },␊
182␉{ 0x10DE014E, "Quadro FX 540" },␊
183␉{ 0x10DE014F, "GeForce 6200" },␊
184␉// 0150 - 015F␉␊
185␉// 0160 - 016F␉␊
186␉{ 0x10DE0160, "GeForce 6500" },␊
187␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
188␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
189␉{ 0x10DE0163, "GeForce 6200 LE" },␊
190␉{ 0x10DE0164, "GeForce Go 6200" },␊
191␉{ 0x10DE0165, "Quadro NVS 285" },␊
192␉{ 0x10DE0166, "GeForce Go 6400" },␊
193␉{ 0x10DE0167, "GeForce Go 6200" },␊
194␉{ 0x10DE0168, "GeForce Go 6400" },␊
195␉{ 0x10DE0169, "GeForce 6250" },␊
196␉{ 0x10DE016A, "GeForce 7100 GS" },␊
197␉// 0170 - 017F␉␊
198␉// 0180 - 018F␉␊
199␉// 0190 - 019F␉␉␊
200␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
201␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
202␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
203␉{ 0x10DE0197, "Tesla C870" },␊
204␉{ 0x10DE019D, "Quadro FX 5600" },␊
205␉{ 0x10DE019E, "Quadro FX 4600" },␊
206␉// 01A0 - 01AF␉␊
207␉// 01B0 - 01BF␉␊
208␉// 01C0 - 01CF␉␊
209␉// 01D0 - 01DF␉␉␊
210␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
211␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
212␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
213␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
214␉{ 0x10DE01D6, "GeForce Go 7200" },␊
215␉{ 0x10DE01D7, "GeForce Go 7300" },␊
216␉{ 0x10DE01D8, "GeForce Go 7400" },␊
217␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
218␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
219␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
220␉{ 0x10DE01DC, "Quadro FX 350M" },␊
221␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
222␉{ 0x10DE01DE, "Quadro FX 350" },␊
223␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
224␉// 01E0 - 01EF␉␊
225␉// 01F0 - 01FF␊
226␉// 0200 - 020F␉␊
227␉// 0210 - 021F␉␊
228␉{ 0x10DE0211, "GeForce 6800" },␊
229␉{ 0x10DE0212, "GeForce 6800 LE" },␊
230␉{ 0x10DE0215, "GeForce 6800 GT" },␊
231␉{ 0x10DE0218, "GeForce 6800 XT" },␊
232␉// 0220 - 022F␉␊
233␉{ 0x10DE0221, "GeForce 6200" },␊
234␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
235␉// 0230 - 023F␉␊
236␉// 0240 - 024F␉␊
237␉{ 0x10DE0240, "GeForce 6150" },␊
238␉{ 0x10DE0241, "GeForce 6150 LE" },␊
239␉{ 0x10DE0242, "GeForce 6100" },␊
240␉{ 0x10DE0244, "GeForce Go 6150" },␊
241␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
242␉{ 0x10DE0247, "GeForce Go 6100" },␊
243␉// 0250 - 025F␉␊
244␉// 0260 - 026F␉␊
245␉// 0270 - 027F␉␊
246␉// 0280 - 028F␉␉␊
247␉// 0290 - 029F␉␊
248␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
249␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
250␉{ 0x10DE0292, "GeForce 7900 GS" },␊
251␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
252␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
253␉{ 0x10DE0295, "GeForce 7950 GT" },␊
254␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
255␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
256␉{ 0x10DE029A, "Quadro FX 2500M" },␊
257␉{ 0x10DE029B, "Quadro FX 1500M" },␊
258␉{ 0x10DE029C, "Quadro FX 5500" },␊
259␉{ 0x10DE029D, "Quadro FX 3500" },␊
260␉{ 0x10DE029E, "Quadro FX 1500" },␊
261␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
262␉// 02A0 - 02AF␉␊
263␉// 02B0 - 02BF␉␊
264␉// 02C0 - 02CF␉␊
265␉// 02D0 - 02DF␉␉␊
266␉// 02E0 - 02EF␉␉␊
267␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
268␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
269␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
270␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
271␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
272␉// 02F0 - 02FF␉␉␊
273␉// 0300 - 030F␉␉␊
274␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
275␉{ 0x10DE0302, "GeForce FX 5800" },␊
276␉{ 0x10DE0308, "Quadro FX 2000" },␊
277␉{ 0x10DE0309, "Quadro FX 1000" },␊
278␉// 0310 - 031F␉␉␊
279␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
280␉{ 0x10DE0312, "GeForce FX 5600" },␊
281␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
282␉{ 0x10DE031A, "GeForce FX Go5600" },␊
283␉{ 0x10DE031B, "GeForce FX Go5650" },␊
284␉{ 0x10DE031C, "Quadro FX Go700" },␊
285␉// 0320 - 032F␉␉␊
286␉{ 0x10DE0324, "GeForce FX Go5200" },␊
287␉{ 0x10DE0325, "GeForce FX Go5250" },␊
288␉{ 0x10DE0326, "GeForce FX 5500" },␊
289␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
290␉{ 0x10DE0329, "GeForce FX Go5200" }, //␊
291␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
292␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
293␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
294␉{ 0x10DE032D, "GeForce FX Go5100" },␊
295␉// 0330 - 033F␊
296␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
297␉{ 0x10DE0331, "GeForce FX 5900" },␊
298␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
299␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
300␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
301␉{ 0x10DE0338, "Quadro FX 3000" },␊
302␉{ 0x10DE033F, "Quadro FX 700" },␊
303␉// 0340 - 034F␊
304␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
305␉{ 0x10DE0342, "GeForce FX 5700" },␊
306␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
307␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
308␉{ 0x10DE0347, "GeForce FX Go5700" },␊
309␉{ 0x10DE0348, "GeForce FX Go5700" },␊
310␉{ 0x10DE034C, "Quadro FX Go1000" },␊
311␉{ 0x10DE034E, "Quadro FX 1100" },␊
312␉// 0350 - 035F␉␊
313␉// 0360 - 036F␉␊
314␉// 0370 - 037F␉␊
315␉// 0380 - 038F␉␉␉␊
316␉{ 0x10DE038B, "GeForce 7650 GS" },␊
317␉// 0390 - 039F␊
318␉{ 0x10DE0390, "GeForce 7650 GS" },␊
319␉{ 0x10DE0391, "GeForce 7600 GT" },␊
320␉{ 0x10DE0392, "GeForce 7600 GS" },␊
321␉{ 0x10DE0393, "GeForce 7300 GT" },␊
322␉{ 0x10DE0394, "GeForce 7600 LE" },␊
323␉{ 0x10DE0395, "GeForce 7300 GT" },␊
324␉{ 0x10DE0397, "GeForce Go 7700" },␊
325␉{ 0x10DE0398, "GeForce Go 7600" },␊
326␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
327␉{ 0x10DE039A, "Quadro NVS 300M" },␊
328␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
329␉{ 0x10DE039C, "Quadro FX 550M" },␊
330␉{ 0x10DE039E, "Quadro FX 560" },␊
331␉// 03A0 - 03AF␉␊
332␉// 03B0 - 03BF␉␊
333␉// 03C0 - 03CF␉␊
334␉// 03D0 - 03DF␉␉␉␊
335␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
336␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
337␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
338␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
339␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
340␉// 03E0 - 03EF␊
341␉// 03F0 - 03FF␊
342␉// 0400 - 040F␉␉␊
343␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
344␉{ 0x10DE0401, "GeForce 8600 GT" },␊
345␉{ 0x10DE0402, "GeForce 8600 GT" },␊
346␉{ 0x10DE0403, "GeForce 8600 GS" },␊
347␉{ 0x10DE0404, "GeForce 8400 GS" },␊
348␉{ 0x10DE0405, "GeForce 9500M GS" },␊
349␉{ 0x10DE0406, "GeForce 8300 GS" },␊
350␉{ 0x10DE0407, "GeForce 8600M GT" },␊
351␉{ 0x10DE0408, "GeForce 9650M GS" },␊
352␉{ 0x10DE0409, "GeForce 8700M GT" },␊
353␉{ 0x10DE040A, "Quadro FX 370" },␊
354␉{ 0x10DE040B, "Quadro NVS 320M" },␊
355␉{ 0x10DE040C, "Quadro FX 570M" },␊
356␉{ 0x10DE040D, "Quadro FX 1600M" },␊
357␉{ 0x10DE040E, "Quadro FX 570" },␊
358␉{ 0x10DE040F, "Quadro FX 1700" },␊
359␉// 0410 - 041F␉␊
360␉{ 0x10DE0410, "GeForce GT 330" },␊
361␉// 0420 - 042F␉␊
362␉{ 0x10DE0420, "GeForce 8400 SE" },␊
363␉{ 0x10DE0421, "GeForce 8500 GT" },␊
364␉{ 0x10DE0422, "GeForce 8400 GS" },␊
365␉{ 0x10DE0423, "GeForce 8300 GS" },␊
366␉{ 0x10DE0424, "GeForce 8400 GS" },␊
367␉{ 0x10DE0425, "GeForce 8600M GS" },␊
368␉{ 0x10DE0426, "GeForce 8400M GT" },␊
369␉{ 0x10DE0427, "GeForce 8400M GS" },␊
370␉{ 0x10DE0428, "GeForce 8400M G" },␊
371␉{ 0x10DE0429, "Quadro NVS 140M" },␊
372␉{ 0x10DE042A, "Quadro NVS 130M" },␊
373␉{ 0x10DE042B, "Quadro NVS 135M" },␊
374␉{ 0x10DE042C, "GeForce 9400 GT" },␊
375␉{ 0x10DE042D, "Quadro FX 360M" },␊
376␉{ 0x10DE042E, "GeForce 9300M G" },␊
377␉{ 0x10DE042F, "Quadro NVS 290" },␊
378␉// 0430 - 043F␊
379␉// 0440 - 044F␊
380␉// 0450 - 045F␊
381␉// 0460 - 046F␊
382␉// 0470 - 047F␊
383␉// 0480 - 048F␊
384␉// 0490 - 049F␊
385␉// 04A0 - 04AF␊
386␉// 04B0 - 04BF␊
387␉// 04C0 - 04CF␊
388␉// 04D0 - 04DF␊
389␉// 04E0 - 04EF␊
390␉// 04F0 - 04FF␊
391␉// 0500 - 050F␉␊
392␉// 0510 - 051F␉␊
393␉// 0520 - 052F␉␊
394␉// 0530 - 053F␉␊
395␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
396␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
397␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
398␉// 0540 - 054F␊
399␉// 0550 - 055F␊
400␉// 0560 - 056F␊
401␉// 0570 - 057F␊
402␉// 0580 - 058F␊
403␉// 0590 - 059F␊
404␉// 05A0 - 05AF␊
405␉// 05B0 - 05BF␊
406␉// 05C0 - 05CF␊
407␉// 05D0 - 05DF␊
408␉// 05E0 - 05EF␉␊
409␉{ 0x10DE05E0, "GeForce GTX 295" },␊
410␉{ 0x10DE05E1, "GeForce GTX 280" },␊
411␉{ 0x10DE05E2, "GeForce GTX 260" },␊
412␉{ 0x10DE05E3, "GeForce GTX 285" },␊
413␉{ 0x10DE05E6, "GeForce GTX 275" },␊
414␉{ 0x10DE05E7, "Tesla C1060" },␊
415␉{ 0x10DE05EA, "GeForce GTX 260" },␊
416␉{ 0x10DE05EB, "GeForce GTX 295" },␊
417␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
418␉// 05F0 - 05FF␉␉␊
419␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
420␉{ 0x10DE05F9, "Quadro CX" },␊
421␉{ 0x10DE05FD, "Quadro FX 5800" },␊
422␉{ 0x10DE05FE, "Quadro FX 4800" },␊
423␉{ 0x10DE05FF, "Quadro FX 3800" },␊
424␉// 0600 - 060F␉␊
425␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
426␉{ 0x10DE0601, "GeForce 9800 GT" },␊
427␉{ 0x10DE0602, "GeForce 8800 GT" },␊
428␉{ 0x10DE0603, "GeForce GT 230" },␊
429␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
430␉{ 0x10DE0605, "GeForce 9800 GT" },␊
431␉{ 0x10DE0606, "GeForce 8800 GS" },␊
432␉{ 0x10DE0607, "GeForce GTS 240" },␊
433␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
434␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
435␉{ 0x10DE060A, "GeForce GTX 280M" },␊
436␉{ 0x10DE060B, "GeForce 9800M GT" },␊
437␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
438␉{ 0x10DE060D, "GeForce 8800 GS" },␊
439␉{ 0x10DE060F, "GeForce GTX 285M" },␊
440␉// 0610 - 061F␉␊
441␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
442␉{ 0x10DE0611, "GeForce 8800 GT" },␊
443␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
444␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
445␉{ 0x10DE0614, "GeForce 9800 GT" },␊
446␉{ 0x10DE0615, "GeForce GTS 250" },␊
447␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
448␉{ 0x10DE0618, "GeForce GTX 260M" },␊
449␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
450␉{ 0x10DE061A, "Quadro FX 3700" },␊
451␉{ 0x10DE061B, "Quadro VX 200" },␊
452␉{ 0x10DE061C, "Quadro FX 3600M" },␊
453␉{ 0x10DE061D, "Quadro FX 2800M" },␊
454␉{ 0x10DE061E, "Quadro FX 3700M" },␊
455␉{ 0x10DE061F, "Quadro FX 3800M" },␊
456␉// 0620 - 062F␉␊
457//␉{ 0x10DE0620, "Unknown" },␊
458␉{ 0x10DE0621, "GeForce GT 230" },␊
459␉{ 0x10DE0622, "GeForce 9600 GT" },␊
460␉{ 0x10DE0623, "GeForce 9600 GS" },␊
461␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
462␉{ 0x10DE0626, "GeForce GT 130" },␊
463␉{ 0x10DE0627, "GeForce GT 140" },␊
464␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
465//␉{ 0x10DE0629, "Unknown" },␊
466␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
467␉{ 0x10DE062B, "GeForce 9800M GS" },␊
468␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
469␉{ 0x10DE062D, "GeForce 9600 GT" },␊
470␉{ 0x10DE062E, "GeForce 9600 GT" },␊
471//␉{ 0x10DE062F, "Unknown" },␊
472␉// 0630 - 063F␉␊
473//␉{ 0x10DE0630, "Unknown" },␊
474␉{ 0x10DE0631, "GeForce GTS 160M" },␊
475␉{ 0x10DE0632, "GeForce GTS 150M" },␊
476//␉{ 0x10DE0633, "Unknown" },␊
477//␉{ 0x10DE0634, "Unknown" },␊
478␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
479//␉{ 0x10DE0636, "Unknown" },␊
480␉{ 0x10DE0637, "GeForce 9600 GT" },␊
481␉{ 0x10DE0638, "Quadro FX 1800" },␊
482//␉{ 0x10DE0639, "Unknown" },␊
483␉{ 0x10DE063A, "Quadro FX 2700M" },␊
484//␉{ 0x10DE063B, "Unknown" },␊
485//␉{ 0x10DE063C, "Unknown" },␊
486//␉{ 0x10DE063D, "Unknown" },␊
487//␉{ 0x10DE063E, "Unknown" },␊
488//␉{ 0x10DE063F, "Unknown" },␊
489␉// 0640 - 064F␉␊
490␉{ 0x10DE0640, "GeForce 9500 GT" },␊
491␉{ 0x10DE0641, "GeForce 9400 GT" },␊
492␉{ 0x10DE0642, "GeForce 8400 GS" },␊
493␉{ 0x10DE0643, "GeForce 9500 GT" },␊
494␉{ 0x10DE0644, "GeForce 9500 GS" },␊
495␉{ 0x10DE0645, "GeForce 9500 GS" },␊
496␉{ 0x10DE0646, "GeForce GT 120" },␊
497␉{ 0x10DE0647, "GeForce 9600M GT" },␊
498␉{ 0x10DE0648, "GeForce 9600M GS" },␊
499␉{ 0x10DE0649, "GeForce 9600M GT" },␊
500␉{ 0x10DE064A, "GeForce 9700M GT" },␊
501␉{ 0x10DE064B, "GeForce 9500M G" },␊
502␉{ 0x10DE064C, "GeForce 9650M GT" },␊
503␉// 0650 - 065F␉␉␊
504␉{ 0x10DE0651, "GeForce G 110M" },␊
505␉{ 0x10DE0652, "GeForce GT 130M" },␊
506␉{ 0x10DE0653, "GeForce GT 120M" },␊
507␉{ 0x10DE0654, "GeForce GT 220M" },␊
508␉{ 0x10DE0655, "GeForce GT 120" },␊
509␉{ 0x10DE0656, "GeForce 9650 S" },␊
510␉{ 0x10DE0658, "Quadro FX 380" },␊
511␉{ 0x10DE0659, "Quadro FX 580" },␊
512␉{ 0x10DE065A, "Quadro FX 1700M" },␊
513␉{ 0x10DE065B, "GeForce 9400 GT" },␊
514␉{ 0x10DE065C, "Quadro FX 770M" },␊
515␉{ 0x10DE065F, "GeForce G210" },␊
516␉// 0660 - 066F␊
517␉// 0670 - 067F␊
518␉// 0680 - 068F␊
519␉// 0690 - 069F␊
520␉// 06A0 - 06AF␊
521␉// 06B0 - 06BF␊
522␉// 06C0 - 06CF␊
523␉{ 0x10DE06C0, "GeForce GTX 480" },␊
524␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
525␉{ 0x10DE06C4, "GeForce GTX 465" },␊
526␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
527␉{ 0x10DE06CD, "GeForce GTX 470" },␊
528␉// 06D0 - 06DF␊
529␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
530␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
531␉{ 0x10DE06D2, "Tesla M2070" },␊
532␉{ 0x10DE06D8, "Quadro 6000" },␊
533␉{ 0x10DE06D9, "Quadro 5000" },␊
534␉{ 0x10DE06DA, "Quadro 5000M" },␊
535␉{ 0x10DE06DC, "Quadro 6000" },␊
536␉{ 0x10DE06DD, "Quadro 4000" },␊
537␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
538␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
539␉{ 0x10DE06DF, "Tesla M2070-Q" },␊
540␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
541␉// 06E0 - 06EF␉␊
542␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
543␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
544␉{ 0x10DE06E2, "GeForce 8400" },␊
545␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
546␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
547␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
548␉{ 0x10DE06E6, "GeForce G100" },␊
549␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
550␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
551␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
552␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
553␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
554␉{ 0x10DE06EC, "GeForce G 105M" },␊
555␉{ 0x10DE06EF, "GeForce G 103M" },␊
556␉// 06F0 - 06FF␉␊
557␉{ 0x10DE06F1, "GeForce G105M" },␊
558␉{ 0x10DE06F8, "Quadro NVS 420" },␊
559␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
560␉{ 0x10DE06FA, "Quadro NVS 450" },␊
561␉{ 0x10DE06FB, "Quadro FX 370M" },␊
562␉{ 0x10DE06FD, "Quadro NVS 295" },␊
563␉{ 0x10DE06FF, "HICx16 + Graphics" },␊
564␉// 0700 - 070F␊
565␉// 0710 - 071F␊
566␉// 0720 - 072F␊
567␉// 0730 - 073F␊
568␉// 0740 - 074F␊
569␉// 0750 - 075F␊
570␉// 0760 - 076F␊
571␉// 0770 - 077F␊
572␉// 0780 - 078F␊
573␉// 0790 - 079F␊
574␉// 07A0 - 07AF␊
575␉// 07B0 - 07BF␊
576␉// 07C0 - 07CF␊
577␉// 07D0 - 07DF␉␊
578␉// 07E0 - 07EF␉␉␊
579␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
580␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
581␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
582␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
583␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
584␉// 07F0 - 07FF␉␊
585␉// 0800 - 080F␊
586␉// 0810 - 081F␊
587␉// 0820 - 082F␊
588␉// 0830 - 083F␊
589␉// 0840 - 084F␊
590␉{ 0x10DE0840, "GeForce 8200M" },␊
591␉{ 0x10DE0844, "GeForce 9100M G" },␊
592␉{ 0x10DE0845, "GeForce 8200M G" },␊
593␉{ 0x10DE0846, "GeForce 9200" },␊
594␉{ 0x10DE0847, "GeForce 9100" },␊
595␉{ 0x10DE0848, "GeForce 8300" },␊
596␉{ 0x10DE0849, "GeForce 8200" },␊
597␉{ 0x10DE084A, "nForce 730a" },␊
598␉{ 0x10DE084B, "GeForce 9200" },␊
599␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
600␉{ 0x10DE084D, "nForce 750a SLI" },␊
601␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
602␉// 0850 - 085F␊
603//␉{ 0x10DE0850, "Unknown" },␊
604//␉{ 0x10DE0851, "Unknown" },␊
605//␉{ 0x10DE0852, "Unknown" },␊
606//␉{ 0x10DE0853, "Unknown" },␊
607//␉{ 0x10DE0854, "Unknown" },␊
608//␉{ 0x10DE0855, "Unknown" },␊
609//␉{ 0x10DE0856, "Unknown" },␊
610//␉{ 0x10DE0857, "Unknown" },␊
611//␉{ 0x10DE0858, "Unknown" },␊
612//␉{ 0x10DE0859, "Unknown" },␊
613//␉{ 0x10DE085A, "Unknown" },␊
614//␉{ 0x10DE085B, "Unknown" },␊
615//␉{ 0x10DE085C, "Unknown" },␊
616//␉{ 0x10DE085D, "Unknown" },␊
617//␉{ 0x10DE085E, "Unknown" },␊
618//␉{ 0x10DE085F, "Unknown" },␊
619␉// 0860 - 086F␉␊
620␉{ 0x10DE0860, "GeForce 9300" }, //␊
621␉{ 0x10DE0861, "GeForce 9400" },␊
622␉{ 0x10DE0862, "GeForce 9400M G" },␊
623␉{ 0x10DE0863, "GeForce 9400M" },␊
624␉{ 0x10DE0864, "GeForce 9300" },␊
625␉{ 0x10DE0865, "GeForce 9300" }, //␊
626␉{ 0x10DE0866, "GeForce 9400M G" },␊
627␉{ 0x10DE0867, "GeForce 9400" },␊
628␉{ 0x10DE0868, "nForce 760i SLI" },␊
629␉{ 0x10DE0869, "GeForce 9400" },␊
630␉{ 0x10DE086A, "GeForce 9400" },␊
631␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
632␉{ 0x10DE086D, "GeForce 9200" },␊
633␉{ 0x10DE086E, "GeForce 9100M G" },␊
634␉{ 0x10DE086F, "GeForce 8200M G" },␊
635␉// 0870 - 087F␉␊
636␉{ 0x10DE0870, "GeForce 9400M" },␊
637␉{ 0x10DE0871, "GeForce 9200" },␊
638␉{ 0x10DE0872, "GeForce G102M" },␊
639␉{ 0x10DE0873, "GeForce G102M" },␊
640␉{ 0x10DE0874, "ION 9300M" },␉␊
641␉{ 0x10DE0876, "GeForce 9400M" }, //␊
642␉{ 0x10DE087A, "GeForce 9400" },␊
643␉{ 0x10DE087D, "ION 9400M" },␊
644␉{ 0x10DE087E, "ION LE" },␊
645␉{ 0x10DE087F, "ION LE" },␊
646␉// 0880 - 088F␊
647␉// 0890 - 089F␊
648␉// 08A0 - 08AF␊
649␉{ 0x10DE08A0, "GeForce 320M" },␊
650//␉{ 0x10DE08A1, "Unknown" },␊
651//␉{ 0x10DE08A2, "Unknown" },␊
652␉{ 0x10DE08A3, "GeForce 320M" },␊
653␉{ 0x10DE08A4, "GeForce 320M" },␊
654//␉{ 0x10DE08A5, "Unknown" },␊
655␉// 08B0 - 08BF␊
656//␉{ 0x10DE08B0, "Unknown" },␊
657//␉{ 0x10DE08B1, "Unknown" },␊
658//␉{ 0x10DE08B2, "Unknown" },␊
659//␉{ 0x10DE08B3, "Unknown" },␊
660␉// 08C0 - 08CF␊
661␉// 08D0 - 08DF␉␊
662␉// 08E0 - 08EF␉␉␉␊
663␉// 08F0 - 08FF␊
664␉// 0900 - 090F␊
665␉// 0910 - 091F␊
666␉// 0920 - 092F␊
667␉// 0930 - 093F␊
668␉// 0940 - 094F␊
669␉// 0950 - 095F␊
670␉// 0960 - 096F␊
671␉// 0970 - 097F␊
672␉// 0980 - 098F␊
673␉// 0990 - 099F␊
674␉// 09A0 - 09AF␊
675␉// 09B0 - 09BF␊
676␉// 09C0 - 09CF␊
677␉// 09D0 - 09DF␉␊
678␉// 09E0 - 09EF␊
679␉// 09F0 - 09FF␊
680␉// 0A00 - 0A0F␊
681␉// 0A10 - 0A1F␊
682␉// 0A20 - 0A2F␊
683␉{ 0x10DE0A20, "GeForce GT 220" }, // subsystem 10de:0a20:1043:8311␊
684␉{ 0x10DE0A22, "GeForce 315" },␊
685␉{ 0x10DE0A23, "GeForce 210" },␊
686␉{ 0x10DE0A26, "GeForce 405" },␊
687␉{ 0x10DE0A27, "GeForce 405" },␊
688␉{ 0x10DE0A28, "GeForce GT 230M" },␊
689␉{ 0x10DE0A29, "GeForce GT 330M" },␊
690␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
691␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
692␉{ 0x10DE0A2C, "NVS 5100M" },␊
693␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊
694␉// 0A30 - 0A3F␉␊
695␉{ 0x10DE0A34, "GeForce GT 240M" },␊
696␉{ 0x10DE0A35, "GeForce GT 325M" },␊
697␉{ 0x10DE0A38, "Quadro 400" },␊
698␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
699//␉{ 0x10DE0A3D, "Unknown" },␊
700//␉{ 0x10DE0A3F, "Unknown" },␊
701␉// 0A40 - 0A4F␊
702␉// 0A50 - 0A5F␊
703␉// 0A60 - 0A6F␊
704␉{ 0x10DE0A60, "GeForce G210" },␊
705␉{ 0x10DE0A62, "GeForce 205" },␊
706␉{ 0x10DE0A63, "GeForce 310" },␊
707␉{ 0x10DE0A64, "ION" },␊
708␉{ 0x10DE0A65, "GeForce 210" }, // subsystem 10de:0a65:1043:8334␊
709␉{ 0x10DE0A66, "GeForce 310" },␊
710␉{ 0x10DE0A67, "GeForce 315" },␊
711␉{ 0x10DE0A68, "GeForce G105M" },␊
712␉{ 0x10DE0A69, "GeForce G105M" },␊
713␉{ 0x10DE0A6A, "NVS 2100M" },␊
714␉{ 0x10DE0A6C, "NVS 3100M" }, // subsystem 10de:0a6c:1028:040b & 10de:0a6c:17aa:2142␊
715␉{ 0x10DE0A6E, "GeForce 305M" },␊
716␉{ 0x10DE0A6F, "ION" },␉␊
717␉// 0A70 - 0A7F␊
718␉{ 0x10DE0A70, "GeForce 310M" },␊
719␉{ 0x10DE0A71, "GeForce 305M" },␊
720␉{ 0x10DE0A72, "GeForce 310M" },␊
721␉{ 0x10DE0A73, "GeForce 305M" },␊
722␉{ 0x10DE0A74, "GeForce G210M" },␊
723␉{ 0x10DE0A75, "GeForce G310M" },␊
724␉{ 0x10DE0A76, "ION" },␊
725␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
726//␉{ 0x10DE0A79, "Unknown" },␊
727␉{ 0x10DE0A7A, "GeForce 315M" },␊
728␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
729//␉{ 0x10DE0A7D, "Unknown" },␊
730//␉{ 0x10DE0A7E, "Unknown" },␊
731//␉{ 0x10DE0A7F, "Unknown" },␊
732␉// 0A80 - 0A8F␊
733␉// 0A90 - 0A9F␊
734␉// 0AA0 - 0AAF␊
735␉// 0AB0 - 0ABF␊
736␉// 0AC0 - 0ACF␊
737␉// 0AD0 - 0ADF␉␊
738␉// 0AE0 - 0AEF␊
739␉// 0AF0 - 0AFF␊
740␉// 0B00 - 0B0F␊
741␉// 0B10 - 0B1F␊
742␉// 0B20 - 0B2F␊
743␉// 0B30 - 0B3F␊
744␉// 0B40 - 0B4F␊
745␉// 0B50 - 0B5F␊
746␉// 0B60 - 0B6F␊
747␉// 0B70 - 0B7F␊
748␉// 0B80 - 0B8F␊
749␉// 0B90 - 0B9F␊
750␉// 0BA0 - 0BAF␊
751␉// 0BB0 - 0BBF␊
752␉// 0BC0 - 0BCF␊
753␉// 0BD0 - 0BDF␉␊
754␉// 0BE0 - 0BEF␊
755␉// 0BF0 - 0BFF␊
756␉// 0C00 - 0C0F␊
757␉// 0C10 - 0C1F␊
758␉// 0C20 - 0C2F␊
759␉// 0C30 - 0C3F␊
760␉// 0C40 - 0C4F␊
761␉// 0C50 - 0C5F␊
762␉// 0C60 - 0C6F␊
763␉// 0C70 - 0C7F␊
764␉// 0C80 - 0C8F␊
765␉// 0C90 - 0C9F␊
766␉// 0CA0 - 0CAF␊
767␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
768␉{ 0x10DE0CA2, "GeForce GT 320" },␊
769␉{ 0x10DE0CA3, "GeForce GT 240" },␊
770␉{ 0x10DE0CA4, "GeForce GT 340" },␊
771␉{ 0x10DE0CA5, "GeForce GT 220" },␊
772␉{ 0x10DE0CA7, "GeForce GT 330" },␊
773␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
774␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
775␉{ 0x10DE0CAC, "GeForce GT 220" },␊
776//␉{ 0x10DE0CAD, "Unknown" },␊
777//␉{ 0x10DE0CAE, "Unknown" },␊
778␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
779␉// 0CB0 - 0CBF␉␊
780␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
781␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
782␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
783␉// 0CC0 - 0CCF␊
784␉// 0CD0 - 0CDF␉␊
785␉// 0CE0 - 0CEF␊
786␉// 0CF0 - 0CFF␊
787␉// 0D00 - 0D0F␊
788␉// 0D10 - 0D1F␊
789␉// 0D20 - 0D2F␊
790␉// 0D30 - 0D3F␊
791␉// 0D40 - 0D4F␊
792␉// 0D50 - 0D5F␊
793␉// 0D60 - 0D6F␊
794␉// 0D70 - 0D7F␊
795␉// 0D80 - 0D8F␊
796␉// 0D90 - 0D9F␊
797␉// 0DA0 - 0DAF␉␊
798␉// 0DB0 - 0DBF␊
799␉// 0DC0 - 0DCF␊
800␉{ 0x10DE0DC0, "GeForce GT 440" },␊
801␉{ 0x10DE0DC1, "D12-P1-35" },␊
802␉{ 0x10DE0DC2, "D12-P1-35" },␊
803␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
804␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
805␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
806␉{ 0x10DE0DCA, "GF10x" },␊
807//␉{ 0x10DE0DCC, "Unknown" },␊
808␉{ 0x10DE0DCD, "GeForce GT 555M" },␊
809␉{ 0x10DE0DCE, "GeForce GT 555M" },␊
810//␉{ 0x10DE0DCF, "Unknown" },␊
811␉// 0DD0 - 0DDF␉␊
812//␉{ 0x10DE0DD0, "Unknown" },␊
813␉{ 0x10DE0DD1, "GeForce GTX 460M" }, // subsystem 10de:0dd1:1558:8687␊
814␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
815␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
816␉{ 0x10DE0DD6, "GeForce GT 550M" },␊
817␉{ 0x10DE0DD8, "Quadro 2000" },␊
818␉{ 0x10DE0DDA, "Quadro 2000M" },␊
819␉{ 0x10DE0DDE, "GF106-ES" },␊
820␉{ 0x10DE0DDF, "GF106-INT" },␊
821␉// 0DE0 - 0DEF␉␊
822␉{ 0x10DE0DE0, "GeForce GT 440" },␊
823␉{ 0x10DE0DE1, "GeForce GT 430" }, // subsystem 10de:0de1:3842:1430␊
824␉{ 0x10DE0DE2, "GeForce GT 420" },␊
825␉{ 0x10DE0DE5, "GeForce GT 530" },␊
826//␉{ 0x10DE0DE8, "Unknown" },␊
827␉{ 0x10DE0DE9, "GeForce GT 600M" }, //␊
828␉{ 0x10DE0DEA, "GeForce GT 610M" },␊
829␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
830␉{ 0x10DE0DEC, "GeForce GT 525M" },␊
831␉{ 0x10DE0DED, "GeForce GT 520M" },␊
832␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
833//␉{ 0x10DE0DEF, "Unknown" },␊
834␉// 0DF0 - 0DFF␉␊
835␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
836␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
837␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
838␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
839␉{ 0x10DE0DF4, "GeForce GT 540M" },␊
840␉{ 0x10DE0DF5, "GeForce GT 525M" },␊
841␉{ 0x10DE0DF6, "GeForce GT 550M" },␊
842␉{ 0x10DE0DF7, "GeForce GT 520M" },␊
843␉{ 0x10DE0DF8, "Quadro 600" },␊
844//␉{ 0x10DE0DF9, "Unknown" },␊
845␉{ 0x10DE0DFA, "Quadro 1000M" },␊
846//␉{ 0x10DE0DFC, "Unknown" },␊
847␉{ 0x10DE0DFE, "GF108 ES" },␊
848␉{ 0x10DE0DFF, "GF108 INT" },␊
849␉// 0E00 - 0E0F␊
850␉// 0E10 - 0E1F␊
851␉// 0E20 - 0E2F␊
852␉{ 0x10DE0E21, "D12U-25" },␊
853␉{ 0x10DE0E22, "GeForce GTX 460" }, // subsystem 10de:0e22:1462:2322␊
854␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
855␉{ 0x10DE0E24, "GeForce GTX 460" },␊
856␉{ 0x10DE0E25, "D12U-50" },␊
857␉// 0E30 - 0E3F␉␊
858␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
859␉{ 0x10DE0E31, "GeForce GTX 485M" },␊
860//␉{ 0x10DE0E32, "Unknown" },␊
861␉{ 0x10DE0E38, "GF104GL" },␊
862␉{ 0x10DE0E3A, "Quadro 3000M" },␊
863␉{ 0x10DE0E3B, "Quadro 4000M" },␊
864␉{ 0x10DE0E3E, "GF104-ES" },␊
865␉{ 0x10DE0E3F, "GF104-INT" },␊
866␉// 0E40 - 0E4F␉␊
867␉// 0E50 - 0E5F␊
868␉// 0E60 - 0E6F␊
869␉// 0E70 - 0E7F␊
870␉// 0E80 - 0E8F␊
871␉// 0E90 - 0E9F␊
872␉// 0EA0 - 0EAF␊
873␉// 0EB0 - 0EBF␊
874␉// 0EC0 - 0ECF␊
875␉// 0ED0 - 0EDF␉␊
876␉// 0EE0 - 0EEF␊
877␉// 0EF0 - 0EFF␊
878␉// 0F00 - 0F0F␊
879␉// 0F10 - 0F1F␊
880␉// 0F20 - 0F2F␊
881␉// 0F30 - 0F3F␊
882␉// 0F40 - 0F4F␊
883␉// 0F50 - 0F5F␊
884␉// 0F60 - 0F6F␊
885␉// 0F70 - 0F7F␊
886␉// 0F80 - 0F8F␊
887␉// 0F90 - 0F9F␊
888␉// 0FA0 - 0FAF␊
889␉// 0FB0 - 0FBF␊
890␉// 0FC0 - 0FCF␊
891␉// 0FD0 - 0FDF␊
892␉{ 0x10DE0FD2, "GeForce GT 640M" },␊
893␉// 0FE0 - 0FEF␊
894␉// 0FF0 - 0FFF␊
895␉// 1000 - 100F␊
896␉// 1010 - 101F␊
897␉// 1020 - 102F␊
898␉// 1030 - 103F␊
899␉// 1040 - 104F␊
900␉{ 0x10DE1040, "GeForce GT 520" },␊
901␉// 1050 - 105F␊
902␉{ 0x10DE1050, "GeForce GT 520M" },␊
903␉{ 0x10DE1051, "GeForce GT 520MX" },␊
904//␉{ 0x10DE1052, "Unknown" },␊
905␉{ 0x10DE1054, "GeForce GT 410M" },␊
906␉{ 0x10DE1055, "GeForce 410M" },␊
907␉{ 0x10DE1056, "Quadro NVS 4200M" },␊
908␉{ 0x10DE1057, "Quadro NVS 4200M" },␊
909//␉{ 0x10DE1058, "Unknown" },␊
910//␉{ 0x10DE1059, "Unknown" },␊
911//␉{ 0x10DE105A, "Unknown" },␊
912␉// 1060 - 106F␊
913␉// 1070 - 107F␊
914//␉{ 0x10DE107D, "Unknown" },␊
915//␉{ 0x10DE107E, "Unknown" },␊
916␉{ 0x10DE107F, "NVIDIA GF119-ES" },␊
917␉// 1080 - 108F␊
918␉{ 0x10DE1080, "GeForce GTX 580" },␊
919␉{ 0x10DE1081, "GeForce GTX 570" }, // subsystem 10de:1081:10de:087e␊
920␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
921␉{ 0x10DE1083, "D13U" },␊
922␉{ 0x10DE1084, "GeForce GTX 560" },␊
923␉{ 0x10DE1086, "GeForce GTX 570" },␊
924␉{ 0x10DE1087, "GeForce GTX 560 Ti-448" },␊
925␉{ 0x10DE1088, "GeForce GTX 590" },␊
926␉{ 0x10DE1089, "GeForce GTX 580" },␊
927␉{ 0x10DE108B, "GeForce GTX 590" },␊
928␉// 1090 - 109F␉␊
929␉{ 0x10DE1091, "Tesla M2090" },␊
930␉{ 0x10DE1094, "Tesla M2075 Dual-Slot Computing Processor Module" },␊
931␉{ 0x10DE1096, "Tesla C2075" },␊
932␉{ 0x10DE1098, "D13U" },␊
933␉{ 0x10DE109A, "Quadro 5010M" },␊
934␉{ 0x10DE109B, "Quadro 7000" },␊
935␉// 10A0 - 10AF␊
936␉// 10B0 - 10BF␊
937␉// 10C0 - 10CF␊
938␉{ 0x10DE10C0, "GeForce 9300 GS" },␊
939␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
940//␉{ 0x10DE10C4, "Unknown" },␊
941␉{ 0x10DE10C5, "GeForce 405" },␊
942␉// 10D0 - 10DF␊
943␉{ 0x10DE10D8, "NVS 300" },␊
944␉// 1100 - ␊
945␊
946␉// 1200 - ␊
947␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
948␉{ 0x10DE1201, "GeForce GTX 560" },␊
949␉{ 0x10DE1205, "GeForce GTX 460 v2" },␊
950␉{ 0x10DE1208, "GeForce GTX 560 SE" },␊
951␉{ 0x10DE1210, "GeForce GTX 570M" },␊
952␉{ 0x10DE1211, "GeForce GTX 580M" },␊
953␉{ 0x10DE1212, "GeForce GTX 675M" },␊
954␉{ 0x10DE1213, "GeForce GTX 670M" },␊
955//␉{ 0x10DE1240, "Unknown" },␊
956␉{ 0x10DE1241, "GeForce GT 545" },␊
957␉{ 0x10DE1243, "GeForce GT 545" },␊
958␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
959␉{ 0x10DE1245, "GeForce GTS 450" },␊
960␉{ 0x10DE1246, "GeForce GTX 550M" },␊
961␉{ 0x10DE1247, "GeForce GTX 555M" },␊
962␉{ 0x10DE1248, "GeForce GTX 555M" },␊
963␉{ 0x10DE124D, "GeForce GTX 555M" },␊
964//␉{ 0x10DE1250, "Unknown" },␊
965␉{ 0x10DE1251, "GeForce GTX 560M" },␊
966};␊
967␊
968static uint16_t swap16(uint16_t x)␊
969{␊
970␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
971}␊
972␊
973static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
974{␊
975␉uint8_t ret[2];␊
976␊
977␉ret[0] = ptr[offset+1];␊
978␉ret[1] = ptr[offset];␊
979␊
980␉return *((uint16_t*)&ret);␊
981}␊
982␊
983#if 0␊
984static uint32_t swap32(uint32_t x)␊
985{␊
986␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
987}␊
988␊
989static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
990{ ␊
991␉return ptr[offset];␊
992}␊
993␊
994static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
995{␊
996␉uint8_t ret[4];␊
997␊
998␉ret[0] = ptr[offset+3];␊
999␉ret[1] = ptr[offset+2];␊
1000␉ret[2] = ptr[offset+1];␊
1001␉ret[3] = ptr[offset];␊
1002␊
1003␉return *((uint32_t*)&ret);␊
1004}␊
1005#endif␊
1006␊
1007static int patch_nvidia_rom(uint8_t *rom)␊
1008{␊
1009␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
1010␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
1011␉␉return PATCH_ROM_FAILED;␊
1012␉}␊
1013␉␊
1014␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
1015␊
1016␉if (!dcbptr) {␊
1017␉␉printf("no dcb table found\n");␊
1018␉␉return PATCH_ROM_FAILED;␊
1019␉}␊
1020//␉else␊
1021//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
1022␉ ␊
1023␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
1024␉uint8_t dcbtable_version = dcbtable[0];␊
1025␉uint8_t headerlength␉ = 0;␊
1026␉uint8_t numentries␉␉ = 0;␊
1027␉uint8_t recordlength␉ = 0;␊
1028␉␊
1029␉if (dcbtable_version >= 0x20)␊
1030␉{␊
1031␉␉uint32_t sig;␊
1032␉␉␊
1033␉␉if (dcbtable_version >= 0x30)␊
1034␉␉{␊
1035␉␉␉headerlength = dcbtable[1];␊
1036␉␉␉numentries␉ = dcbtable[2];␊
1037␉␉␉recordlength = dcbtable[3];␊
1038␊
1039␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
1040␉␉}␊
1041␉␉else␊
1042␉␉{␊
1043␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
1044␉␉␉headerlength = 8;␊
1045␉␉}␊
1046␉␉␊
1047␉␉if (sig != 0x4edcbdcb)␊
1048␉␉{␊
1049␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
1050␉␉␉return PATCH_ROM_FAILED;␊
1051␉␉}␊
1052␉}␊
1053␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
1054␉{␊
1055␉␉char sig[8] = { 0 };␊
1056␉␉␊
1057␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
1058␉␉recordlength = 10;␊
1059␉␉␊
1060␉␉if (strcmp(sig, "DEV_REC"))␊
1061␉␉{␊
1062␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
1063␉␉␉return PATCH_ROM_FAILED;␊
1064␉␉}␊
1065␉}␊
1066␉else␊
1067␉{␊
1068␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
1069␉␉return PATCH_ROM_FAILED;␊
1070␉}␊
1071␉␊
1072␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
1073␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
1074␉␊
1075␉uint8_t num_outputs = 0, i = 0;␊
1076␉␊
1077␉struct dcbentry␊
1078␉{␊
1079␉␉uint8_t type;␊
1080␉␉uint8_t index;␊
1081␉␉uint8_t *heads;␊
1082␉} entries[numentries];␊
1083␉␊
1084␉for (i = 0; i < numentries; i++)␊
1085␉{␊
1086␉␉uint32_t connection;␊
1087␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
1088␊
1089␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1090␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1091␉␉␉continue;␊
1092␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1093␉␉␉continue;␊
1094␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1095␉␉␉continue;␊
1096␉␉␊
1097␉␉entries[num_outputs].type = connection & 0xf;␊
1098␉␉entries[num_outputs].index = num_outputs;␊
1099␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1100␉}␊
1101␉␊
1102␉int has_lvds = false;␊
1103␉uint8_t channel1 = 0, channel2 = 0;␊
1104␉␊
1105␉for (i = 0; i < num_outputs; i++)␊
1106␉{␊
1107␉␉if (entries[i].type == 3)␊
1108␉␉{␊
1109␉␉␉has_lvds = true;␊
1110␉␉␉//printf("found LVDS\n");␊
1111␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1112␉␉␉entries[i].type = TYPE_GROUPED;␊
1113␉␉}␊
1114␉}␊
1115␉␊
1116␉// if we have a LVDS output, we group the rest to the second channel␊
1117␉if (has_lvds)␊
1118␉{␊
1119␉␉for (i = 0; i < num_outputs; i++)␊
1120␉␉{␊
1121␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1122␉␉␉␉continue;␊
1123␉␉␉␊
1124␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1125␉␉␉entries[i].type = TYPE_GROUPED;␊
1126␉␉}␊
1127␉}␊
1128␉else␊
1129␉{␊
1130␉␉int x;␊
1131␉␉// we loop twice as we need to generate two channels␊
1132␉␉for (x = 0; x <= 1; x++)␊
1133␉␉{␊
1134␉␉␉for (i=0; i<num_outputs; i++)␊
1135␉␉␉{␊
1136␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1137␉␉␉␉␉continue;␊
1138␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1139␉␉␉␉// we always group ANALOG and TMDS␊
1140␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1141␉␉␉␉if (i && entries[i].type == 0x2)␊
1142␉␉␉␉{␊
1143␉␉␉␉␉switch (x)␊
1144␉␉␉␉␉{␊
1145␉␉␉␉␉␉case 0:␊
1146␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1147␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1148␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1149␉␉␉␉␉␉␉␊
1150␉␉␉␉␉␉␉if ( entries[i-1].type == 0x0 )␊
1151␉␉␉␉␉␉␉{␊
1152␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1153␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1154␉␉␉␉␉␉␉}␊
1155␉␉␉␉␉␉␉// group TV as well if there is one␊
1156␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1157␉␉␉␉␉␉␉{␊
1158␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1159␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1160␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1161␉␉␉␉␉␉␉}␊
1162␉␉␉␉␉␉␉break;␊
1163␉␉␉␉␉␉␊
1164␉␉␉␉␉␉case 1:␊
1165␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1166␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1167␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1168␉␉␉␉␉␉␉␊
1169␉␉␉␉␉␉␉if ( entries[i - 1].type == 0x0 )␊
1170␉␉␉␉␉␉␉{␊
1171␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1172␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1173␉␉␉␉␉␉␉}␊
1174␉␉␉␉␉␉␉// group TV as well if there is one␊
1175␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1176␉␉␉␉␉␉␉{␊
1177␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1178␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1179␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1180␉␉␉␉␉␉␉}␊
1181␉␉␉␉␉␉␉break;␊
1182␉␉␉␉␉}␊
1183␉␉␉␉␉break;␊
1184␉␉␉␉}␊
1185␉␉␉}␊
1186␉␉}␊
1187␉}␊
1188␉␊
1189␉// if we have left ungrouped outputs merge them to the empty channel␊
1190␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1191␉togroup = &channel2;␊
1192␉␊
1193␉for (i = 0; i < num_outputs; i++)␊
1194␉{␊
1195␉␉if (entries[i].type != TYPE_GROUPED)␊
1196␉␉{␊
1197␉␉␉//printf("%d not grouped\n", i);␊
1198␉␉␉if (togroup)␊
1199␉␉␉{␊
1200␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1201␉␉␉}␊
1202␉␉␉entries[i].type = TYPE_GROUPED;␊
1203␉␉}␊
1204␉}␊
1205␉␊
1206␉if (channel1 > channel2)␊
1207␉{␊
1208␉␉uint8_t buff = channel1;␊
1209␉␉channel1 = channel2;␊
1210␉␉channel2 = buff;␊
1211␉}␊
1212␉␊
1213␉default_NVCAP[6] = channel1;␊
1214␉default_NVCAP[8] = channel2;␊
1215␉␊
1216␉// patching HEADS␊
1217␉for (i = 0; i < num_outputs; i++)␊
1218␉{␊
1219␉␉if (channel1 & (1 << i))␊
1220␉␉{␊
1221␉␉␉*entries[i].heads = 1;␊
1222␉␉}␊
1223␉␉else if(channel2 & (1 << i))␊
1224␉␉{␊
1225␉␉␉*entries[i].heads = 2;␊
1226␉␉}␊
1227␉}␊
1228␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1229}␊
1230␊
1231static char *get_nvidia_model(uint32_t id)␊
1232{␊
1233␉int i;␊
1234␉␊
1235␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1236␉␉if (NVKnownChipsets[i].device == id)␊
1237␉␉{␊
1238␉␉␉return NVKnownChipsets[i].name;␊
1239␉␉}␊
1240␉}␊
1241␉return NVKnownChipsets[0].name;␊
1242}␊
1243␊
1244static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1245{␊
1246␉int fd;␊
1247␉int size;␊
1248␉␊
1249␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1250␉{␊
1251␉␉return 0;␊
1252␉}␊
1253␉␊
1254␉size = file_size(fd);␊
1255␉␊
1256␉if (size > bufsize)␊
1257␉{␊
1258␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1259␉␉␉␉filename, bufsize);␊
1260␉␉size = bufsize;␊
1261␉}␊
1262␉size = read(fd, (char *)buf, size);␊
1263␉close(fd);␊
1264␉␊
1265␉return size > 0 ? size : 0;␊
1266}␊
1267␊
1268static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1269{␊
1270␉char tmp[16];␊
1271␉␊
1272␉if (!device)␊
1273␉␉return 0;␊
1274␉␊
1275␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1276␉␉return 0;␊
1277␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1278␉␉return 0;␊
1279␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1280␉␉return 0;␊
1281␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1282␉␉return 0;␊
1283␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1284␉␉return 0;␊
1285␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1286␉␉return 0;␊
1287␉if (devices_number == 1)␊
1288␉{␊
1289␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1290␉␉ return 0;␊
1291␉}␊
1292␉else␊
1293␉{␊
1294␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
1295␉␉ return 0;␊
1296␉}␊
1297␉␊
1298␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1299␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1300␉sprintf(tmp, "Slot-%x",devices_number);␊
1301␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1302␉devices_number++;␊
1303␉␊
1304␉return 1;␊
1305}␊
1306␊
1307int hex2bin(const char *hex, uint8_t *bin, int len)␊
1308{␊
1309␉char␉*p;␊
1310␉int␉␉i;␊
1311␉char␉buf[3];␊
1312␉␊
1313␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1314␉␉printf("[ERROR] bin2hex input error\n");␊
1315␉␉return -1;␊
1316␉}␊
1317␉␊
1318␉buf[2] = '\0';␊
1319␉p = (char *) hex;␊
1320␉␊
1321␉for (i = 0; i < len; i++)␊
1322␉{␊
1323␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1324␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1325␉␉␉return -2;␊
1326␉␉}␊
1327␉␉buf[0] = *p++;␊
1328␉␉buf[1] = *p++;␊
1329␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1330␉}␊
1331␉return 0;␊
1332}␊
1333␊
1334unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1335{␊
1336␉unsigned long long vram_size = 0;␊
1337␉␊
1338␉if (nvCardType < NV_ARCH_50)␊
1339␉{␊
1340␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1341␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1342␉}␊
1343␉else if (nvCardType < NV_ARCH_C0)␊
1344␉{␊
1345␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1346␉␉vram_size |= (vram_size & 0xff) << 32;␊
1347␉␉vram_size &= 0xffffffff00ll;␊
1348␉}␊
1349␉else // >= NV_ARCH_C0␊
1350␉{␊
1351␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1352␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1353␉}␊
1354␉␊
1355␉// Workaround for 9600M GT, GT 210/420/430/440 & GT 525M␊
1356␉switch (nvda_dev->device_id)␊
1357␉{␊
1358␉␉case 0x0647: vram_size = 512*1024*1024; break;␉// 9600M GT 0647␊
1359␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT 0649␊
1360␉␉case 0x0A65: vram_size = 1024*1024*1024; break; // GT 210␊
1361␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
1362␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1363␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1364␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M 0DEC␊
1365␉␉case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M 0DF5␊
1366␉␉default: break;␊
1367␉}␊
1368␉␊
1369␉return vram_size;␊
1370}␊
1371␊
1372bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1373{␊
1374␉struct DevPropDevice␉*device;␊
1375␉char␉␉␉␉␉*devicepath;␊
1376␉option_rom_pci_header_t *rom_pci_header;␊
1377␉volatile uint8_t␉␉*regs;␊
1378␉uint8_t␉␉␉␉␉*rom;␊
1379␉uint8_t␉␉␉␉␉*nvRom;␊
1380␉uint8_t␉␉␉␉␉nvCardType;␊
1381␉unsigned long long␉␉videoRam;␊
1382␉uint32_t␉␉␉␉nvBiosOveride;␊
1383␉uint32_t␉␉␉␉bar[7];␊
1384␉uint32_t␉␉␉␉boot_display;␊
1385␉int␉␉␉␉␉␉nvPatch;␊
1386␉int␉␉␉␉␉␉len;␊
1387␉char␉␉␉␉␉biosVersion[32];␊
1388␉char␉␉␉␉␉nvFilename[32];␊
1389␉char␉␉␉␉␉kNVCAP[12];␊
1390␉char␉␉␉␉␉*model;␊
1391␉const char␉␉␉␉*value;␊
1392␉bool␉␉␉␉␉doit;␊
1393␉␊
1394␉devicepath = get_pci_dev_path(nvda_dev);␊
1395␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1396␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1397␉␊
1398␉// get card type␊
1399␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1400␉␊
1401␉// Amount of VRAM in kilobytes␊
1402␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1403␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1404␉␊
1405␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
1406␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
1407␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1408␉␉␉devicepath);␊
1409␉␊
1410␉rom = malloc(NVIDIA_ROM_SIZE);␊
1411␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1412␉␉␉(uint16_t)nvda_dev->device_id);␊
1413␉␊
1414␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1415␉{␊
1416␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1417␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1418␉␉␊
1419␉␉if (nvBiosOveride > 0)␊
1420␉␉{␊
1421␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1422␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1423␉␉}␊
1424␉␉else␊
1425␉␉{␊
1426␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1427␉␉␉return false;␊
1428␉␉}␊
1429␉}␊
1430␉else␊
1431␉{␊
1432␉␉// Otherwise read bios from card␊
1433␉␉nvBiosOveride = 0;␊
1434␉␉␊
1435␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1436␉␉␊
1437␉␉// PRAMIN first␊
1438␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1439␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1440␉␉␊
1441␉␉// Valid Signature ?␊
1442␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1443␉␉{␊
1444␉␉␉// PROM next␊
1445␉␉␉// Enable PROM access␊
1446␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1447␉␉␉␊
1448␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1449␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1450␉␉␉␊
1451␉␉␉// disable PROM access␊
1452␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1453␉␉␉␊
1454␉␉␉// Valid Signature ?␊
1455␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1456␉␉␉{␊
1457␉␉␉␉// 0xC0000 last␊
1458␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1459␉␉␉␉␊
1460␉␉␉␉// Valid Signature ?␊
1461␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1462␉␉␉␉{␊
1463␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1464␉␉␉␉␉return false;␊
1465␉␉␉␉}␊
1466␉␉␉␉else␊
1467␉␉␉␉{␊
1468␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1469␉␉␉␉}␊
1470␉␉␉}␊
1471␉␉␉else␊
1472␉␉␉{␊
1473␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1474␉␉␉}␊
1475␉␉}␊
1476␉␉else␊
1477␉␉{␊
1478␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1479␉␉}␊
1480␉}␊
1481␉␊
1482␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1483␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1484␉␉//return false;␊
1485␉}␊
1486␉␊
1487␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1488␉␊
1489␉// check for 'PCIR' sig␊
1490␉if (rom_pci_header->signature == 0x50434952)␊
1491␉{␊
1492␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1493␉␉{␊
1494␉␉␉// Get Model from the OpROM␊
1495␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1496␉␉}␊
1497␉␉else␊
1498␉␉{␊
1499␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1500␉␉}␊
1501␉}␊
1502␉␊
1503␉if (!string) {␊
1504␉␉string = devprop_create_string();␊
1505␉}␊
1506␉device = devprop_add_device(string, devicepath);␊
1507␉␊
1508␉/* FIXME: for primary graphics card only */␊
1509␉boot_display = 1;␊
1510␉if (devices_number == 1)␊
1511␉{␊
1512␉ devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1513␉}␊
1514␉␊
1515␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1516␉␉uint8_t built_in = 0x01;␊
1517␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1518␉}␊
1519␊
1520␉// get bios version␊
1521␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1522␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1523␉␊
1524␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1525␉␊
1526␉int i, version_start;␊
1527␉int crlf_count = 0;␊
1528␉␊
1529␉// only search the first 384 bytes␊
1530␉for (i = 0; i < 0x180; i++)␊
1531␉{␊
1532␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1533␉␉{␊
1534␉␉␉crlf_count++;␊
1535␉␉␉// second 0x0D0A was found, extract bios version␊
1536␉␉␉if (crlf_count == 2)␊
1537␉␉␉{␊
1538␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1539␉␉␉␉␊
1540␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1541␉␉␉␉{␊
1542␉␉␉␉␉// find start␊
1543␉␉␉␉␉if (rom[version_start] == 0x00)␊
1544␉␉␉␉␉{␊
1545␉␉␉␉␉␉version_start++;␊
1546␉␉␉␉␉␉␊
1547␉␉␉␉␉␉// strip "Version "␊
1548␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1549␉␉␉␉␉␉{␊
1550␉␉␉␉␉␉␉version_start += 8;␊
1551␉␉␉␉␉␉}␊
1552␉␉␉␉␉␉␊
1553␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1554␉␉␉␉␉␉break;␊
1555␉␉␉␉␉}␊
1556␉␉␉␉}␊
1557␉␉␉␉break;␊
1558␉␉␉}␊
1559␉␉}␊
1560␉}␊
1561␉␊
1562␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1563␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1564␉␊
1565␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1566␉{␊
1567␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1568␉␉␊
1569␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1570␉␉{␊
1571␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1572␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1573␉␉}␊
1574␉}␊
1575␉␊
1576␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1577␉{␊
1578␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1579␉␉␊
1580␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1581␉␉{␊
1582␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1583␉␉␉␊
1584␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1585␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1586␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1587␉␉}␊
1588␉}␊
1589␉␊
1590␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1591␉{␊
1592␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1593␉␉␊
1594␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1595␉␉{␊
1596␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1597␉␉␉␊
1598␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1599␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1600␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1601␉␉}␊
1602␉}␊
1603␉␊
1604#if DEBUG_NVCAP␊
1605␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1606␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1607␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1608␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1609␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1610␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1611#endif␊
1612␉␊
1613␉devprop_add_nvidia_template(device);␊
1614␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1615␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1616␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1617␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1618 //␉devprop_add_value(device, "@1,connector-type", connector_type_1, 4); // fixme␊
1619 //␉devprop_add_value(device, "@0,display-cfg", display_cfg_0, 4);␊
1620 //␉devprop_add_value(device, "@1,display-cfg", display_cfg_1, 4);␊
1621␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊
1622␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1623␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1624␉␊
1625␉//add HDMI Audio back to nvidia␊
1626␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1627//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1628//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1629␉//end Nvidia HDMI Audio␊
1630␉␊
1631␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1632␉{␊
1633␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1634␉}␊
1635␉␊
1636␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1637␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1638␉stringlength = string->length;␊
1639␉␊
1640␉return true;␊
1641}␊
1642

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