Chameleon

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Root/branches/Chimera/i386/libsaio/nvidia.c

1/*
2 *NVidia injector
3 *
4 *Copyright (C) 2009Jasmin Fazlic, iNDi
5 *
6 *NVidia injector is free software: you can redistribute it and/or modify
7 *it under the terms of the GNU General Public License as published by
8 *the Free Software Foundation, either version 3 of the License, or
9 *(at your option) any later version.
10 *
11 *NVidia driver and injector is distributed in the hope that it will be useful,
12 *but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *GNU General Public License for more details.
15 *
16 *You should have received a copy of the GNU General Public License
17 *along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
18 */
19/*
20 * Alternatively you can choose to comply with APSL
21 */
22
23
24/*
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
26 *
27 *
28 * Copyright 2005-2006 Erik Waling
29 * Copyright 2006 Stephane Marchesin
30 * Copyright 2007-2009 Stuart Bennett
31 *
32 * Permission is hereby granted, free of charge, to any person obtaining a
33 * copy of this software and associated documentation files (the "Software"),
34 * to deal in the Software without restriction, including without limitation
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
36 * and/or sell copies of the Software, and to permit persons to whom the
37 * Software is furnished to do so, subject to the following conditions:
38 *
39 * The above copyright notice and this permission notice shall be included in
40 * all copies or substantial portions of the Software.
41 *
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
48 * SOFTWARE.
49 */
50
51#include "boot.h"
52#include "bootstruct.h"
53#include "pci.h"
54#include "platform.h"
55#include "device_inject.h"
56#include "nvidia.h"
57
58#ifndef DEBUG_NVIDIA
59#define DEBUG_NVIDIA 0
60#endif
61
62#if DEBUG_NVIDIA
63#define DBG(x...)printf(x)
64#else
65#define DBG(x...)
66#endif
67
68#define NVIDIA_ROM_SIZE0x10000
69#define PATCH_ROM_SUCCESS1
70#define PATCH_ROM_SUCCESS_HAS_LVDS2
71#define PATCH_ROM_FAILED0
72#define MAX_NUM_DCB_ENTRIES16
73#define TYPE_GROUPED0xff
74
75extern uint32_t devices_number;
76
77const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
78const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
79const char *nvidia_device_type_0[]={ "@0,device_type", "display" };
80const char *nvidia_device_type_1[]={ "@1,device_type", "display" };
81const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
82const char *nvidia_device_type_child[]={ "device_type","NVDA,Child" };
83const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
84const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
85const char *nvidia_slot_name[]={ "AAPL,slot-name", "Slot-1" };
86
87static uint8_t default_NVCAP[]= {
880x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
890x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
900x00, 0x00, 0x00, 0x00
91};
92
93#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
94
95static uint8_t default_dcfg_0[]={0xff, 0xff, 0xff, 0xff};
96static uint8_t default_dcfg_1[]={0xff, 0xff, 0xff, 0xff};
97
98#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )
99#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )
100
101static struct nv_chipsets_t NVKnownChipsets[] = {
102{ 0x00000000, "Unknown" },
103//========================================
104// 0040 - 004F
105{ 0x10DE0040, "GeForce 6800 Ultra" },
106{ 0x10DE0041, "GeForce 6800" },
107{ 0x10DE0042, "GeForce 6800 LE" },
108{ 0x10DE0043, "GeForce 6800 XE" },
109{ 0x10DE0044, "GeForce 6800 XT" },
110{ 0x10DE0045, "GeForce 6800 GT" },
111{ 0x10DE0046, "GeForce 6800 GT" },
112{ 0x10DE0047, "GeForce 6800 GS" },
113{ 0x10DE0048, "GeForce 6800 XT" },
114{ 0x10DE004D, "Quadro FX 3400" },
115{ 0x10DE004E, "Quadro FX 4000" },
116// 0050 - 005F
117// 0060 - 006F
118// 0070 - 007F
119// 0080 - 008F
120// 0090 - 009F
121{ 0x10DE0090, "GeForce 7800 GTX" },
122{ 0x10DE0091, "GeForce 7800 GTX" },
123{ 0x10DE0092, "GeForce 7800 GT" },
124{ 0x10DE0093, "GeForce 7800 GS" },
125{ 0x10DE0095, "GeForce 7800 SLI" },
126{ 0x10DE0098, "GeForce Go 7800" },
127{ 0x10DE0099, "GeForce Go 7800 GTX" },
128{ 0x10DE009D, "Quadro FX 4500" },
129// 00A0 - 00AF
130// 00B0 - 00BF
131// 00C0 - 00CF
132{ 0x10DE00C0, "GeForce 6800 GS" },
133{ 0x10DE00C1, "GeForce 6800" },
134{ 0x10DE00C2, "GeForce 6800 LE" },
135{ 0x10DE00C3, "GeForce 6800 XT" },
136{ 0x10DE00C8, "GeForce Go 6800" },
137{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
138{ 0x10DE00CC, "Quadro FX Go1400" },
139{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
140{ 0x10DE00CE, "Quadro FX 1400" },
141// 00D0 - 00DF
142// 00E0 - 00EF
143// 00F0 - 00FF
144{ 0x10DE00F1, "GeForce 6600 GT" },
145{ 0x10DE00F2, "GeForce 6600" },
146{ 0x10DE00F3, "GeForce 6200" },
147{ 0x10DE00F4, "GeForce 6600 LE" },
148{ 0x10DE00F5, "GeForce 7800 GS" },
149{ 0x10DE00F6, "GeForce 6800 GS/XT" },
150{ 0x10DE00F8, "Quadro FX 3400/4400" },
151{ 0x10DE00F9, "GeForce 6800 Series GPU" },
152// 0100 - 010F
153// 0110 - 011F
154// 0120 - 012F
155// 0130 - 013F
156// 0140 - 014F
157{ 0x10DE0140, "GeForce 6600 GT" },
158{ 0x10DE0141, "GeForce 6600" },
159{ 0x10DE0142, "GeForce 6600 LE" },
160{ 0x10DE0143, "GeForce 6600 VE" },
161{ 0x10DE0144, "GeForce Go 6600" },
162{ 0x10DE0145, "GeForce 6610 XL" },
163{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
164{ 0x10DE0147, "GeForce 6700 XL" },
165{ 0x10DE0148, "GeForce Go 6600" },
166{ 0x10DE0149, "GeForce Go 6600 GT" },
167{ 0x10DE014A, "Quadro NVS 440" },
168{ 0x10DE014C, "Quadro FX 550" },
169{ 0x10DE014D, "Quadro FX 550" },
170{ 0x10DE014E, "Quadro FX 540" },
171{ 0x10DE014F, "GeForce 6200" },
172// 0150 - 015F
173// 0160 - 016F
174{ 0x10DE0160, "GeForce 6500" },
175{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
176{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
177{ 0x10DE0163, "GeForce 6200 LE" },
178{ 0x10DE0164, "GeForce Go 6200" },
179{ 0x10DE0165, "Quadro NVS 285" },
180{ 0x10DE0166, "GeForce Go 6400" },
181{ 0x10DE0167, "GeForce Go 6200" },
182{ 0x10DE0168, "GeForce Go 6400" },
183{ 0x10DE0169, "GeForce 6250" },
184{ 0x10DE016A, "GeForce 7100 GS" },
185// 0170 - 017F
186// 0180 - 018F
187// 0190 - 019F
188{ 0x10DE0191, "GeForce 8800 GTX" },
189{ 0x10DE0193, "GeForce 8800 GTS" },
190{ 0x10DE0194, "GeForce 8800 Ultra" },
191{ 0x10DE0197, "Tesla C870" },
192{ 0x10DE019D, "Quadro FX 5600" },
193{ 0x10DE019E, "Quadro FX 4600" },
194// 01A0 - 01AF
195// 01B0 - 01BF
196// 01C0 - 01CF
197// 01D0 - 01DF
198{ 0x10DE01D0, "GeForce 7350 LE" },
199{ 0x10DE01D1, "GeForce 7300 LE" },
200{ 0x10DE01D2, "GeForce 7550 LE" },
201{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },
202{ 0x10DE01D6, "GeForce Go 7200" },
203{ 0x10DE01D7, "GeForce Go 7300" },
204{ 0x10DE01D8, "GeForce Go 7400" },
205{ 0x10DE01D9, "GeForce Go 7400 GS" },
206{ 0x10DE01DA, "Quadro NVS 110M" },
207{ 0x10DE01DB, "Quadro NVS 120M" },
208{ 0x10DE01DC, "Quadro FX 350M" },
209{ 0x10DE01DD, "GeForce 7500 LE" },
210{ 0x10DE01DE, "Quadro FX 350" },
211{ 0x10DE01DF, "GeForce 7300 GS" },
212// 01E0 - 01EF
213// 01F0 - 01FF
214// 0200 - 020F
215// 0210 - 021F
216{ 0x10DE0211, "GeForce 6800" },
217{ 0x10DE0212, "GeForce 6800 LE" },
218{ 0x10DE0215, "GeForce 6800 GT" },
219{ 0x10DE0218, "GeForce 6800 XT" },
220// 0220 - 022F
221{ 0x10DE0221, "GeForce 6200" },
222{ 0x10DE0222, "GeForce 6200 A-LE" },
223// 0230 - 023F
224// 0240 - 024F
225{ 0x10DE0240, "GeForce 6150" },
226{ 0x10DE0241, "GeForce 6150 LE" },
227{ 0x10DE0242, "GeForce 6100" },
228{ 0x10DE0244, "GeForce Go 6150" },
229{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },
230{ 0x10DE0247, "GeForce Go 6100" },
231// 0250 - 025F
232// 0260 - 026F
233// 0270 - 027F
234// 0280 - 028F
235// 0290 - 029F
236{ 0x10DE0290, "GeForce 7900 GTX" },
237{ 0x10DE0291, "GeForce 7900 GT/GTO" },
238{ 0x10DE0292, "GeForce 7900 GS" },
239{ 0x10DE0293, "GeForce 7950 GX2" },
240{ 0x10DE0294, "GeForce 7950 GX2" },
241{ 0x10DE0295, "GeForce 7950 GT" },
242{ 0x10DE0298, "GeForce Go 7900 GS" },
243{ 0x10DE0299, "GeForce Go 7900 GTX" },
244{ 0x10DE029A, "Quadro FX 2500M" },
245{ 0x10DE029B, "Quadro FX 1500M" },
246{ 0x10DE029C, "Quadro FX 5500" },
247{ 0x10DE029D, "Quadro FX 3500" },
248{ 0x10DE029E, "Quadro FX 1500" },
249{ 0x10DE029F, "Quadro FX 4500 X2" },
250// 02A0 - 02AF
251// 02B0 - 02BF
252// 02C0 - 02CF
253// 02D0 - 02DF
254// 02E0 - 02EF
255{ 0x10DE02E0, "GeForce 7600 GT" },
256{ 0x10DE02E1, "GeForce 7600 GS" },
257{ 0x10DE02E2, "GeForce 7300 GT" },
258{ 0x10DE02E3, "GeForce 7900 GS" },
259{ 0x10DE02E4, "GeForce 7950 GT" },
260// 02F0 - 02FF
261// 0300 - 030F
262{ 0x10DE0301, "GeForce FX 5800 Ultra" },
263{ 0x10DE0302, "GeForce FX 5800" },
264{ 0x10DE0308, "Quadro FX 2000" },
265{ 0x10DE0309, "Quadro FX 1000" },
266// 0310 - 031F
267{ 0x10DE0311, "GeForce FX 5600 Ultra" },
268{ 0x10DE0312, "GeForce FX 5600" },
269{ 0x10DE0314, "GeForce FX 5600XT" },
270{ 0x10DE031A, "GeForce FX Go5600" },
271{ 0x10DE031B, "GeForce FX Go5650" },
272{ 0x10DE031C, "Quadro FX Go700" },
273// 0320 - 032F
274{ 0x10DE0324, "GeForce FX Go5200" },
275{ 0x10DE0325, "GeForce FX Go5250" },
276{ 0x10DE0326, "GeForce FX 5500" },
277{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
278{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
279{ 0x10DE032B, "Quadro FX 500/600 PCI" },
280{ 0x10DE032C, "GeForce FX Go53xx Series" },
281{ 0x10DE032D, "GeForce FX Go5100" },
282// 0330 - 033F
283{ 0x10DE0330, "GeForce FX 5900 Ultra" },
284{ 0x10DE0331, "GeForce FX 5900" },
285{ 0x10DE0332, "GeForce FX 5900XT" },
286{ 0x10DE0333, "GeForce FX 5950 Ultra" },
287{ 0x10DE0334, "GeForce FX 5900ZT" },
288{ 0x10DE0338, "Quadro FX 3000" },
289{ 0x10DE033F, "Quadro FX 700" },
290// 0340 - 034F
291{ 0x10DE0341, "GeForce FX 5700 Ultra" },
292{ 0x10DE0342, "GeForce FX 5700" },
293{ 0x10DE0343, "GeForce FX 5700LE" },
294{ 0x10DE0344, "GeForce FX 5700VE" },
295{ 0x10DE0347, "GeForce FX Go5700" },
296{ 0x10DE0348, "GeForce FX Go5700" },
297{ 0x10DE034C, "Quadro FX Go1000" },
298{ 0x10DE034E, "Quadro FX 1100" },
299// 0350 - 035F
300// 0360 - 036F
301// 0370 - 037F
302// 0380 - 038F
303{ 0x10DE038B, "GeForce 7650 GS" },
304// 0390 - 039F
305{ 0x10DE0390, "GeForce 7650 GS" },
306{ 0x10DE0391, "GeForce 7600 GT" },
307{ 0x10DE0392, "GeForce 7600 GS" },
308{ 0x10DE0393, "GeForce 7300 GT" },
309{ 0x10DE0394, "GeForce 7600 LE" },
310{ 0x10DE0395, "GeForce 7300 GT" },
311{ 0x10DE0397, "GeForce Go 7700" },
312{ 0x10DE0398, "GeForce Go 7600" },
313{ 0x10DE0399, "GeForce Go 7600 GT"},
314{ 0x10DE039A, "Quadro NVS 300M" },
315{ 0x10DE039B, "GeForce Go 7900 SE" },
316{ 0x10DE039C, "Quadro FX 550M" },
317{ 0x10DE039E, "Quadro FX 560" },
318// 03A0 - 03AF
319// 03B0 - 03BF
320// 03C0 - 03CF
321// 03D0 - 03DF
322{ 0x10DE03D0, "GeForce 6150SE nForce 430" },
323{ 0x10DE03D1, "GeForce 6100 nForce 405" },
324{ 0x10DE03D2, "GeForce 6100 nForce 400" },
325{ 0x10DE03D5, "GeForce 6100 nForce 420" },
326{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },
327// 03E0 - 03EF
328// 03F0 - 03FF
329// 0400 - 040F
330{ 0x10DE0400, "GeForce 8600 GTS" },
331{ 0x10DE0401, "GeForce 8600 GT" },
332{ 0x10DE0402, "GeForce 8600 GT" },
333{ 0x10DE0403, "GeForce 8600 GS" },
334{ 0x10DE0404, "GeForce 8400 GS" },
335{ 0x10DE0405, "GeForce 9500M GS" },
336{ 0x10DE0406, "GeForce 8300 GS" },
337{ 0x10DE0407, "GeForce 8600M GT" },
338{ 0x10DE0408, "GeForce 9650M GS" },
339{ 0x10DE0409, "GeForce 8700M GT" },
340{ 0x10DE040A, "Quadro FX 370" },
341{ 0x10DE040B, "Quadro NVS 320M" },
342{ 0x10DE040C, "Quadro FX 570M" },
343{ 0x10DE040D, "Quadro FX 1600M" },
344{ 0x10DE040E, "Quadro FX 570" },
345{ 0x10DE040F, "Quadro FX 1700" },
346// 0410 - 041F
347{ 0x10DE0410, "GeForce GT 330" },
348// 0420 - 042F
349{ 0x10DE0420, "GeForce 8400 SE" },
350{ 0x10DE0421, "GeForce 8500 GT" },
351{ 0x10DE0422, "GeForce 8400 GS" },
352{ 0x10DE0423, "GeForce 8300 GS" },
353{ 0x10DE0424, "GeForce 8400 GS" },
354{ 0x10DE0425, "GeForce 8600M GS" },
355{ 0x10DE0426, "GeForce 8400M GT" },
356{ 0x10DE0427, "GeForce 8400M GS" },
357{ 0x10DE0428, "GeForce 8400M G" },
358{ 0x10DE0429, "Quadro NVS 140M" },
359{ 0x10DE042A, "Quadro NVS 130M" },
360{ 0x10DE042B, "Quadro NVS 135M" },
361{ 0x10DE042C, "GeForce 9400 GT" },
362{ 0x10DE042D, "Quadro FX 360M" },
363{ 0x10DE042E, "GeForce 9300M G" },
364{ 0x10DE042F, "Quadro NVS 290" },
365// 0430 - 043F
366// 0440 - 044F
367// 0450 - 045F
368// 0460 - 046F
369// 0470 - 047F
370// 0480 - 048F
371// 0490 - 049F
372// 04A0 - 04AF
373// 04B0 - 04BF
374// 04C0 - 04CF
375// 04D0 - 04DF
376// 04E0 - 04EF
377// 04F0 - 04FF
378// 0500 - 050F
379// 0510 - 051F
380// 0520 - 052F
381// 0530 - 053F
382{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
383{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
384{ 0x10DE053E, "GeForce 7025 / nForce 630a" },
385// 0540 - 054F
386// 0550 - 055F
387// 0560 - 056F
388// 0570 - 057F
389// 0580 - 058F
390// 0590 - 059F
391// 05A0 - 05AF
392// 05B0 - 05BF
393// 05C0 - 05CF
394// 05D0 - 05DF
395// 05E0 - 05EF
396{ 0x10DE05E0, "GeForce GTX 295" },
397{ 0x10DE05E1, "GeForce GTX 280" },
398{ 0x10DE05E2, "GeForce GTX 260" },
399{ 0x10DE05E3, "GeForce GTX 285" },
400{ 0x10DE05E6, "GeForce GTX 275" },
401 { 0x10DE05E7, "Tesla C1060" },
402{ 0x10DE05EA, "GeForce GTX 260" },
403{ 0x10DE05EB, "GeForce GTX 295" },
404{ 0x10DE05ED, "Quadroplex 2200 D2" },
405// 05F0 - 05FF
406{ 0x10DE05F8, "Quadroplex 2200 S4" },
407{ 0x10DE05F9, "Quadro CX" },
408{ 0x10DE05FD, "Quadro FX 5800" },
409{ 0x10DE05FE, "Quadro FX 4800" },
410{ 0x10DE05FF, "Quadro FX 3800" },
411// 0600 - 060F
412{ 0x10DE0600, "GeForce 8800 GTS 512" },
413{ 0x10DE0601, "GeForce 9800 GT" },
414{ 0x10DE0602, "GeForce 8800 GT" },
415{ 0x10DE0603, "GeForce GT 230" },
416{ 0x10DE0604, "GeForce 9800 GX2" },
417{ 0x10DE0605, "GeForce 9800 GT" },
418{ 0x10DE0606, "GeForce 8800 GS" },
419{ 0x10DE0607, "GeForce GTS 240" },
420{ 0x10DE0608, "GeForce 9800M GTX" },
421{ 0x10DE0609, "GeForce 8800M GTS" },
422{ 0x10DE060A, "GeForce GTX 280M" },
423{ 0x10DE060B, "GeForce 9800M GT" },
424{ 0x10DE060C, "GeForce 8800M GTX" },
425{ 0x10DE060D, "GeForce 8800 GS" },
426{ 0x10DE060F, "GeForce GTX 285M" },
427// 0610 - 061F
428{ 0x10DE0610, "GeForce 9600 GSO" },
429{ 0x10DE0611, "GeForce 8800 GT" },
430{ 0x10DE0612, "GeForce 9800 GTX" },
431{ 0x10DE0613, "GeForce 9800 GTX+" },
432{ 0x10DE0614, "GeForce 9800 GT" },
433{ 0x10DE0615, "GeForce GTS 250" },
434{ 0x10DE0617, "GeForce 9800M GTX" },
435{ 0x10DE0618, "GeForce GTX 260M" },
436{ 0x10DE0619, "Quadro FX 4700 X2" },
437{ 0x10DE061A, "Quadro FX 3700" },
438{ 0x10DE061B, "Quadro VX 200" },
439{ 0x10DE061C, "Quadro FX 3600M" },
440{ 0x10DE061D, "Quadro FX 2800M" },
441 { 0x10DE061E, "Quadro FX 3700M" },
442{ 0x10DE061F, "Quadro FX 3800M" },
443// 0620 - 062F
444 { 0x10DE0621, "GeForce GT 230" },
445{ 0x10DE0622, "GeForce 9600 GT" },
446{ 0x10DE0623, "GeForce 9600 GS" },
447{ 0x10DE0625, "GeForce 9600 GSO 512"},
448{ 0x10DE0626, "GeForce GT 130" },
449{ 0x10DE0627, "GeForce GT 140" },
450{ 0x10DE0628, "GeForce 9800M GTS" },
451{ 0x10DE062A, "GeForce 9700M GTS" },
452 { 0x10DE062B, "GeForce 9800M GS" },
453{ 0x10DE062C, "GeForce 9800M GTS" },
454{ 0x10DE062D, "GeForce 9600 GT" },
455{ 0x10DE062E, "GeForce 9600 GT" },
456// 0630 - 063F
457{ 0x10DE0631, "GeForce GTS 160M" },
458{ 0x10DE0632, "GeForce GTS 150M" },
459{ 0x10DE0635, "GeForce 9600 GSO" },
460{ 0x10DE0637, "GeForce 9600 GT" },
461{ 0x10DE0638, "Quadro FX 1800" },
462{ 0x10DE063A, "Quadro FX 2700M" },
463// 0640 - 064F
464{ 0x10DE0640, "GeForce 9500 GT" },
465{ 0x10DE0641, "GeForce 9400 GT" },
466{ 0x10DE0642, "GeForce 8400 GS" },
467{ 0x10DE0643, "GeForce 9500 GT" },
468{ 0x10DE0644, "GeForce 9500 GS" },
469{ 0x10DE0645, "GeForce 9500 GS" },
470{ 0x10DE0646, "GeForce GT 120" },
471{ 0x10DE0647, "GeForce 9600M GT" },
472{ 0x10DE0648, "GeForce 9600M GS" },
473{ 0x10DE0649, "GeForce 9600M GT" },
474{ 0x10DE064A, "GeForce 9700M GT" },
475{ 0x10DE064B, "GeForce 9500M G" },
476{ 0x10DE064C, "GeForce 9650M GT" },
477// 0650 - 065F
478{ 0x10DE0651, "GeForce G 110M" },
479{ 0x10DE0652, "GeForce GT 130M" },
480{ 0x10DE0653, "GeForce GT 120M" },
481{ 0x10DE0654, "GeForce GT 220M" },
482 { 0x10DE0655, "GeForce GT 120" },
483{ 0x10DE0656, "GeForce 9650 S" },
484{ 0x10DE0658, "Quadro FX 380" },
485{ 0x10DE0659, "Quadro FX 580" },
486{ 0x10DE065A, "Quadro FX 1700M" },
487{ 0x10DE065B, "GeForce 9400 GT" },
488{ 0x10DE065C, "Quadro FX 770M" },
489{ 0x10DE065F, "GeForce G210" },
490// 0660 - 066F
491// 0670 - 067F
492// 0680 - 068F
493// 0690 - 069F
494// 06A0 - 06AF
495// 06B0 - 06BF
496// 06C0 - 06CF
497{ 0x10DE06C0, "GeForce GTX 480" },
498{ 0x10DE06C3, "GeForce GTX D12U" },
499{ 0x10DE06C4, "GeForce GTX 465" },
500{ 0x10DE06CA, "GeForce GTX 480M" },
501{ 0x10DE06CD, "GeForce GTX 470" },
502// 06D0 - 06DF
503{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
504{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
505{ 0x10DE06D2, "Tesla M2070" },
506{ 0x10DE06D8, "Quadro 6000" },
507{ 0x10DE06D9, "Quadro 5000" },
508{ 0x10DE06DA, "Quadro 5000M" },
509{ 0x10DE06DC, "Quadro 6000" },
510{ 0x10DE06DD, "Quadro 4000" },
511{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
512{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
513{ 0x10DE06DF, "Tesla M2070-Q" },
514// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
515// 06E0 - 06EF
516{ 0x10DE06E0, "GeForce 9300 GE" },
517{ 0x10DE06E1, "GeForce 9300 GS" },
518{ 0x10DE06E2, "GeForce 8400" },
519{ 0x10DE06E3, "GeForce 8400 SE" },
520{ 0x10DE06E4, "GeForce 8400 GS" },
521{ 0x10DE06E5, "GeForce 9300M GS" },
522{ 0x10DE06E6, "GeForce G100" },
523{ 0x10DE06E7, "GeForce 9300 SE" },
524{ 0x10DE06E8, "GeForce 9200M GS" },
525{ 0x10DE06E9, "GeForce 9300M GS" },
526{ 0x10DE06EA, "Quadro NVS 150M" },
527{ 0x10DE06EB, "Quadro NVS 160M" },
528{ 0x10DE06EC, "GeForce G 105M" },
529{ 0x10DE06EF, "GeForce G 103M" },
530// 06F0 - 06FF
531 { 0x10DE06F1, "GeForce G105M" },
532{ 0x10DE06F8, "Quadro NVS 420" },
533{ 0x10DE06F9, "Quadro FX 370 LP" },
534{ 0x10DE06FA, "Quadro NVS 450" },
535{ 0x10DE06FB, "Quadro FX 370M" },
536{ 0x10DE06FD, "Quadro NVS 295" },
537 { 0x10DE06FF, "HICx16 + Graphics" },
538// 0700 - 070F
539// 0710 - 071F
540// 0720 - 072F
541// 0730 - 073F
542// 0740 - 074F
543// 0750 - 075F
544// 0760 - 076F
545// 0770 - 077F
546// 0780 - 078F
547// 0790 - 079F
548// 07A0 - 07AF
549// 07B0 - 07BF
550// 07C0 - 07CF
551// 07D0 - 07DF
552// 07E0 - 07EF
553{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },
554{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },
555{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },
556{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },
557{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },
558// 07F0 - 07FF
559// 0800 - 080F
560// 0810 - 081F
561// 0820 - 082F
562// 0830 - 083F
563// 0840 - 084F
564 { 0x10DE0840, "GeForce 8200M" },
565{ 0x10DE0844, "GeForce 9100M G" },
566{ 0x10DE0845, "GeForce 8200M G" },
567{ 0x10DE0846, "GeForce 9200" },
568{ 0x10DE0847, "GeForce 9100" },
569{ 0x10DE0848, "GeForce 8300" },
570{ 0x10DE0849, "GeForce 8200" },
571{ 0x10DE084A, "nForce 730a" },
572{ 0x10DE084B, "GeForce 9200" },
573{ 0x10DE084C, "nForce 980a/780a SLI" },
574{ 0x10DE084D, "nForce 750a SLI" },
575{ 0x10DE084F, "GeForce 8100 / nForce 720a" },
576// 0850 - 085F
577// 0860 - 086F
578{ 0x10DE0860, "GeForce 9400" },
579{ 0x10DE0861, "GeForce 9400" },
580{ 0x10DE0862, "GeForce 9400M G" },
581{ 0x10DE0863, "GeForce 9400M" },
582{ 0x10DE0864, "GeForce 9300" },
583{ 0x10DE0865, "ION" },
584{ 0x10DE0866, "GeForce 9400M G" },
585{ 0x10DE0867, "GeForce 9400" },
586{ 0x10DE0868, "nForce 760i SLI" },
587 { 0x10DE0869, "GeForce 9400" },
588{ 0x10DE086A, "GeForce 9400" },
589{ 0x10DE086C, "GeForce 9300 / nForce 730i" },
590{ 0x10DE086D, "GeForce 9200" },
591{ 0x10DE086E, "GeForce 9100M G" },
592{ 0x10DE086F, "GeForce 8200M G" },
593// 0870 - 087F
594{ 0x10DE0870, "GeForce 9400M" },
595{ 0x10DE0871, "GeForce 9200" },
596{ 0x10DE0872, "GeForce G102M" },
597{ 0x10DE0873, "GeForce G102M" },
598{ 0x10DE0874, "ION 9300M" },
599{ 0x10DE0876, "ION" },
600{ 0x10DE087A, "GeForce 9400" },
601{ 0x10DE087D, "ION 9400M" },
602{ 0x10DE087E, "ION LE" },
603{ 0x10DE087F, "ION LE" },
604// 0880 - 088F
605// 0890 - 089F
606// 08A0 - 08AF
607 { 0x10DE08A0, "GeForce 320M" },
608{ 0x10DE08A4, "GeForce 320M" },
609{ 0x10DE08A5, "GeForce 320M" },
610// 08B0 - 08BF
611// 08C0 - 08CF
612// 08D0 - 08DF
613// 08E0 - 08EF
614// 08F0 - 08FF
615// 0900 - 090F
616// 0910 - 091F
617// 0920 - 092F
618// 0930 - 093F
619// 0940 - 094F
620// 0950 - 095F
621// 0960 - 096F
622// 0970 - 097F
623// 0980 - 098F
624// 0990 - 099F
625// 09A0 - 09AF
626// 09B0 - 09BF
627// 09C0 - 09CF
628// 09D0 - 09DF
629// 09E0 - 09EF
630// 09F0 - 09FF
631// 0A00 - 0A0F
632// 0A10 - 0A1F
633// 0A20 - 0A2F
634{ 0x10DE0A20, "GeForce GT220" },
635{ 0x10DE0A22, "GeForce 315" },
636{ 0x10DE0A23, "GeForce 210" },
637 { 0x10DE0A26, "GeForce 405" },
638{ 0x10DE0A27, "GeForce 405" },
639{ 0x10DE0A28, "GeForce GT 230M" },
640{ 0x10DE0A29, "GeForce GT 330M" },
641{ 0x10DE0A2A, "GeForce GT 230M" },
642{ 0x10DE0A2B, "GeForce GT 330M" },
643{ 0x10DE0A2C, "NVS 5100M" },
644{ 0x10DE0A2D, "GeForce GT 320M" },
645// 0A30 - 0A3F
646{ 0x10DE0A34, "GeForce GT 240M" },
647{ 0x10DE0A35, "GeForce GT 325M" },
648 { 0x10DE0A38, "Quadro 400" },
649{ 0x10DE0A3C, "Quadro FX 880M" },
650// 0A40 - 0A4F
651// 0A50 - 0A5F
652// 0A60 - 0A6F
653{ 0x10DE0A60, "GeForce G210" },
654{ 0x10DE0A62, "GeForce 205" },
655{ 0x10DE0A63, "GeForce 310" },
656{ 0x10DE0A64, "ION" },
657{ 0x10DE0A65, "GeForce 210" },
658{ 0x10DE0A66, "GeForce 310" },
659{ 0x10DE0A67, "GeForce 315" },
660{ 0x10DE0A68, "GeForce G105M" },
661{ 0x10DE0A69, "GeForce G105M" },
662{ 0x10DE0A6A, "NVS 2100M" },
663{ 0x10DE0A6C, "NVS 3100M" },
664{ 0x10DE0A6E, "GeForce 305M" },
665{ 0x10DE0A6F, "ION" },
666// 0A70 - 0A7F
667{ 0x10DE0A70, "GeForce 310M" },
668{ 0x10DE0A71, "GeForce 305M" },
669{ 0x10DE0A72, "GeForce 310M" },
670{ 0x10DE0A73, "GeForce 305M" },
671{ 0x10DE0A74, "GeForce G210M" },
672{ 0x10DE0A75, "GeForce G310M" },
673 { 0x10DE0A76, "ION" },
674{ 0x10DE0A78, "Quadro FX 380 LP" },
675 { 0x10DE0A7A, "GeForce 315M" },
676{ 0x10DE0A7C, "Quadro FX 380M" },
677// 0A80 - 0A8F
678// 0A90 - 0A9F
679// 0AA0 - 0AAF
680// 0AB0 - 0ABF
681// 0AC0 - 0ACF
682// 0AD0 - 0ADF
683// 0AE0 - 0AEF
684// 0AF0 - 0AFF
685// 0B00 - 0B0F
686// 0B10 - 0B1F
687// 0B20 - 0B2F
688// 0B30 - 0B3F
689// 0B40 - 0B4F
690// 0B50 - 0B5F
691// 0B60 - 0B6F
692// 0B70 - 0B7F
693// 0B80 - 0B8F
694// 0B90 - 0B9F
695// 0BA0 - 0BAF
696// 0BB0 - 0BBF
697// 0BC0 - 0BCF
698// 0BD0 - 0BDF
699// 0BE0 - 0BEF
700// 0BF0 - 0BFF
701// 0C00 - 0C0F
702// 0C10 - 0C1F
703// 0C20 - 0C2F
704// 0C30 - 0C3F
705// 0C40 - 0C4F
706// 0C50 - 0C5F
707// 0C60 - 0C6F
708// 0C70 - 0C7F
709// 0C80 - 0C8F
710// 0C90 - 0C9F
711// 0CA0 - 0CAF
712{ 0x10DE0CA0, "GeForce GT 330 " },
713{ 0x10DE0CA2, "GeForce GT 320" },
714{ 0x10DE0CA3, "GeForce GT 240" },
715{ 0x10DE0CA4, "GeForce GT 340" },
716 { 0x10DE0CA5, "GeForce GT 220" },
717{ 0x10DE0CA7, "GeForce GT 330" },
718{ 0x10DE0CA8, "GeForce GTS 260M" },
719{ 0x10DE0CA9, "GeForce GTS 250M" },
720{ 0x10DE0CAC, "GeForce GT 220" },
721{ 0x10DE0CAF, "GeForce GT 335M" },
722// 0CB0 - 0CBF
723{ 0x10DE0CB0, "GeForce GTS 350M" },
724{ 0x10DE0CB1, "GeForce GTS 360M" },
725{ 0x10DE0CBC, "Quadro FX 1800M" },
726// 0CC0 - 0CCF
727// 0CD0 - 0CDF
728// 0CE0 - 0CEF
729// 0CF0 - 0CFF
730// 0D00 - 0D0F
731// 0D10 - 0D1F
732// 0D20 - 0D2F
733// 0D30 - 0D3F
734// 0D40 - 0D4F
735// 0D50 - 0D5F
736// 0D60 - 0D6F
737// 0D70 - 0D7F
738// 0D80 - 0D8F
739// 0D90 - 0D9F
740// 0DA0 - 0DAF
741// 0DB0 - 0DBF
742// 0DC0 - 0DCF
743{ 0x10DE0DC0, "GeForce GT 440" },
744{ 0x10DE0DC1, "D12-P1-35" },
745{ 0x10DE0DC2, "D12-P1-35" },
746{ 0x10DE0DC4, "GeForce GTS 450" },
747{ 0x10DE0DC5, "GeForce GTS 450" },
748{ 0x10DE0DC6, "GeForce GTS 450" },
749{ 0x10DE0DCA, "GF10x" },
750{ 0x10DE0DCD, "GeForce GT 555M" },
751{ 0x10DE0DCE, "GeForce GT 555M" },
752// 0DD0 - 0DDF
753{ 0x10DE0DD1, "GeForce GTX 460M" },
754{ 0x10DE0DD2, "GeForce GT 445M" },
755{ 0x10DE0DD3, "GeForce GT 435M" },
756{ 0x10DE0DD6, "GeForce GT 550M" },
757{ 0x10DE0DD8, "Quadro 2000" },
758{ 0x10DE0DDA, "Quadro 2000M" },
759{ 0x10DE0DDE, "GF106-ES" },
760{ 0x10DE0DDF, "GF106-INT" },
761// 0DE0 - 0DEF
762{ 0x10DE0DE0, "GeForce GT 440" },
763{ 0x10DE0DE1, "GeForce GT 430" },
764{ 0x10DE0DE2, "GeForce GT 420" },
765{ 0x10DE0DE4, "GeForce GT 520" },
766{ 0x10DE0DE5, "GeForce GT 530" },
767{ 0x10DE0DE9, "GeForce GT 630M" },
768{ 0x10DE0DEB, "GeForce GT 555M" },
769{ 0x10DE0DEC, "GeForce GT 525M" },
770{ 0x10DE0DED, "GeForce GT 520M" },
771{ 0x10DE0DEE, "GeForce GT 415M" },
772// 0DF0 - 0DFF
773{ 0x10DE0DF0, "GeForce GT 425M" },
774{ 0x10DE0DF1, "GeForce GT 420M" },
775{ 0x10DE0DF2, "GeForce GT 435M" },
776{ 0x10DE0DF3, "GeForce GT 420M" },
777{ 0x10DE0DF4, "GeForce GT 540M" },
778{ 0x10DE0DF5, "GeForce GT 525M" },
779{ 0x10DE0DF6, "GeForce GT 550M" },
780{ 0x10DE0DF7, "GeForce GT 520M" },
781{ 0x10DE0DF8, "Quadro 600" },
782{ 0x10DE0DFA, "Quadro 1000M" },
783{ 0x10DE0DFC, "NVS 5200M" },
784{ 0x10DE0DFE, "GF108 ES" },
785{ 0x10DE0DFF, "GF108 INT" },
786// 0E00 - 0E0F
787// 0E10 - 0E1F
788// 0E20 - 0E2F
789{ 0x10DE0E21, "D12U-25" },
790{ 0x10DE0E22, "GeForce GTX 460" },
791{ 0x10DE0E23, "GeForce GTX 460 SE" },
792{ 0x10DE0E24, "GeForce GTX 460" },
793{ 0x10DE0E25, "D12U-50" },
794// 0E30 - 0E3F
795{ 0x10DE0E30, "GeForce GTX 470M" },
796{ 0x10DE0E31, "GeForce GTX 485M" },
797{ 0x10DE0E38, "GF104GL" },
798{ 0x10DE0E3A, "Quadro 3000M" },
799{ 0x10DE0E3B, "Quadro 4000M" },
800{ 0x10DE0E3E, "GF104-ES" },
801{ 0x10DE0E3F, "GF104-INT" },
802// 0E40 - 0E4F
803// 0E50 - 0E5F
804// 0E60 - 0E6F
805// 0E70 - 0E7F
806// 0E80 - 0E8F
807// 0E90 - 0E9F
808// 0EA0 - 0EAF
809// 0EB0 - 0EBF
810// 0EC0 - 0ECF
811// 0ED0 - 0EDF
812// 0EE0 - 0EEF
813// 0EF0 - 0EFF
814// 0F00 - 0F0F
815// 0F10 - 0F1F
816// 0F20 - 0F2F
817// 0F30 - 0F3F
818// 0F40 - 0F4F
819// 0F50 - 0F5F
820// 0F60 - 0F6F
821// 0F70 - 0F7F
822// 0F80 - 0F8F
823// 0F90 - 0F9F
824// 0FA0 - 0FAF
825// 0FB0 - 0FBF
826// 0FC0 - 0FCF
827// 0FD0 - 0FDF
828// 0FE0 - 0FEF
829// 0FF0 - 0FFF
830// 1000 - 100F
831// 1010 - 101F
832// 1020 - 102F
833// 1030 - 103F
834// 1040 - 104F
835{ 0x10DE1040, "GeForce GT 520" },
836{ 0x10DE1042, "GeForce 510" },
837{ 0x10DE1049, "GeForce GT 620" },
838// 1050 - 105F
839{ 0x10DE1050, "GeForce GT 520M" },
840 { 0x10DE1051, "GeForce GT 520MX" },
841{ 0x10DE1054, "GeForce GT 410M" },
842{ 0x10DE1055, "GeForce 410M" },
843{ 0x10DE1056, "Quadro NVS 4200M" },
844{ 0x10DE1057, "Quadro NVS 4200M" },
845// 1060 - 106F
846// 1070 - 107F
847{ 0x10DE107F, "NVIDIA GF119-ES" },
848// 1080 - 108F
849{ 0x10DE1080, "GeForce GTX 580" },
850{ 0x10DE1081, "GeForce GTX 570" },
851{ 0x10DE1082, "GeForce GTX 560 Ti" },
852{ 0x10DE1083, "D13U" },
853 { 0x10DE1084, "GeForce GTX 560" },
854{ 0x10DE1086, "GeForce GTX 570" },
855 { 0x10DE1087, "GeForce GTX 560 Ti 448 Cores" },
856{ 0x10DE1088, "GeForce GTX 590" },
857 { 0x10DE1089, "GeForce GTX 580" },
858{ 0x10DE108B, "GeForce GTX 590" },
859// 1090 - 109F
860 { 0x10DE1091, "Tesla M2090" },
861{ 0x10DE1094, "Tesla M2075" },
862{ 0x10DE1096, "Tesla C2075" },
863{ 0x10DE1098, "D13U" },
864{ 0x10DE109A, "Quadro 5010M" },
865{ 0x10DE109B, "Quadro 7000" },
866// 10A0 - 10AF
867// 10B0 - 10BF
868// 10C0 - 10CF
869 { 0x10DE10C0, "GeForce 9300 GS" },
870{ 0x10DE10C3, "GeForce 8400 GS" },
871{ 0x10DE10C5, "GeForce 405" },
872 // 10D0 - 10DF
873 { 0x10DE10D8, "NVS 300" },
874// 10E0 - 10EF
875// 10F0 - 10FF
876// 1100 - 110F
877// 1110 - 111F
878// 1120 - 112F
879// 1130 - 113F
880// 1140 - 114F
881// 1150 - 115F
882// 1160 - 116F
883// 1170 - 117F
884// 1180 - 118F
885{ 0x10DE1180, "GeForce GTX 680" },
886// 1190 - 119F
887// 11A0 - 11AF
888// 11B0 - 11BF
889// 11C0 - 11CF
890// 11D0 - 11DF
891// 11E0 - 11EF
892// 11F0 - 11FF
893// 1200 - 120F
894{ 0x10DE1200, "GeForce GTX 560 Ti" },
895{ 0x10DE1201, "GeForce GTX 560" },
896{ 0x10DE1203, "GeForce GTX 460 SE v2" },
897// 1210 - 121F
898{ 0x10DE1210, "GeForce GTX 570M" },
899{ 0x10DE1211, "GeForce GTX 580M" },
900// 1220 - 122F
901// 1230 - 123F
902// 1240 - 124F
903 { 0x10DE1241, "GeForce GT 545" },
904{ 0x10DE1243, "GeForce GT 545" },
905{ 0x10DE1244, "GeForce GTX 550 Ti" },
906{ 0x10DE1245, "GeForce GTS 450" },
907{ 0x10DE1247, "GeForce GT 555M" },
908// 1250 - 125F
909{ 0x10DE1251, "GeForce GTX 560M" },
910// 1260 - 126F
911// 1270 - 127F
912// 1280 - 128F
913// 1290 - 129F
914// 12A0 - 12AF
915// 12B0 - 12BF
916// 12C0 - 12CF
917// 12D0 - 12DF
918// 12E0 - 12EF
919// 12F0 - 12FF
920};
921
922static uint16_t swap16(uint16_t x)
923{
924return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
925}
926
927static uint16_t read16(uint8_t *ptr, uint16_t offset)
928{
929uint8_t ret[2];
930
931ret[0] = ptr[offset+1];
932ret[1] = ptr[offset];
933
934return *((uint16_t*)&ret);
935}
936
937#if 0
938static uint32_t swap32(uint32_t x)
939{
940return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
941}
942
943static uint8_tread8(uint8_t *ptr, uint16_t offset)
944{
945return ptr[offset];
946}
947
948static uint32_t read32(uint8_t *ptr, uint16_t offset)
949{
950uint8_t ret[4];
951
952ret[0] = ptr[offset+3];
953ret[1] = ptr[offset+2];
954ret[2] = ptr[offset+1];
955ret[3] = ptr[offset];
956
957return *((uint32_t*)&ret);
958}
959#endif
960
961static int patch_nvidia_rom(uint8_t *rom)
962{
963if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
964printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
965return PATCH_ROM_FAILED;
966}
967
968uint16_t dcbptr = swap16(read16(rom, 0x36));
969
970if (!dcbptr) {
971printf("no dcb table found\n");
972return PATCH_ROM_FAILED;
973}
974//else
975//printf("dcb table at offset 0x%04x\n", dcbptr);
976
977uint8_t *dcbtable = &rom[dcbptr];
978uint8_t dcbtable_version = dcbtable[0];
979uint8_t headerlength = 0;
980uint8_t numentries = 0;
981uint8_t recordlength = 0;
982
983if (dcbtable_version >= 0x20)
984{
985uint32_t sig;
986
987if (dcbtable_version >= 0x30)
988{
989headerlength = dcbtable[1];
990numentries = dcbtable[2];
991recordlength = dcbtable[3];
992
993sig = *(uint32_t *)&dcbtable[6];
994}
995else
996{
997sig = *(uint32_t *)&dcbtable[4];
998headerlength = 8;
999}
1000
1001if (sig != 0x4edcbdcb)
1002{
1003printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48
1004return PATCH_ROM_FAILED;
1005}
1006}
1007else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */
1008{
1009char sig[8] = { 0 };
1010
1011strncpy(sig, (char *)&dcbtable[-7], 7);
1012recordlength = 10;
1013
1014if (strcmp(sig, "DEV_REC"))
1015{
1016printf("Bad Display Configuration Block signature (%s)\n", sig);
1017return PATCH_ROM_FAILED;
1018}
1019}
1020else
1021{
1022printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
1023return PATCH_ROM_FAILED;
1024}
1025
1026if (numentries >= MAX_NUM_DCB_ENTRIES)
1027numentries = MAX_NUM_DCB_ENTRIES;
1028
1029uint8_t num_outputs = 0, i = 0;
1030
1031struct dcbentry
1032{
1033uint8_t type;
1034uint8_t index;
1035uint8_t *heads;
1036} entries[numentries];
1037
1038for (i = 0; i < numentries; i++)
1039{
1040uint32_t connection;
1041connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
1042
1043/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
1044if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
1045continue;
1046if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
1047continue;
1048if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
1049continue;
1050
1051entries[num_outputs].type = connection & 0xf;
1052entries[num_outputs].index = num_outputs;
1053entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
1054}
1055
1056int has_lvds = false;
1057uint8_t channel1 = 0, channel2 = 0;
1058
1059for (i = 0; i < num_outputs; i++)
1060{
1061if (entries[i].type == 3)
1062{
1063has_lvds = true;
1064//printf("found LVDS\n");
1065channel1 |= ( 0x1 << entries[i].index);
1066entries[i].type = TYPE_GROUPED;
1067}
1068}
1069
1070// if we have a LVDS output, we group the rest to the second channel
1071if (has_lvds)
1072{
1073for (i = 0; i < num_outputs; i++)
1074{
1075if (entries[i].type == TYPE_GROUPED)
1076continue;
1077
1078channel2 |= ( 0x1 << entries[i].index);
1079entries[i].type = TYPE_GROUPED;
1080}
1081}
1082else
1083{
1084int x;
1085// we loop twice as we need to generate two channels
1086for (x = 0; x <= 1; x++)
1087{
1088for (i=0; i<num_outputs; i++)
1089{
1090if (entries[i].type == TYPE_GROUPED)
1091continue;
1092// if type is TMDS, the prior output is ANALOG
1093// we always group ANALOG and TMDS
1094// if there is a TV output after TMDS, we group it to that channel as well
1095if (i && entries[i].type == 0x2)
1096{
1097switch (x)
1098{
1099case 0:
1100//printf("group channel 1\n");
1101channel1 |= ( 0x1 << entries[i].index);
1102entries[i].type = TYPE_GROUPED;
1103
1104if ((entries[i-1].type == 0x0))
1105{
1106channel1 |= ( 0x1 << entries[i-1].index);
1107entries[i-1].type = TYPE_GROUPED;
1108}
1109// group TV as well if there is one
1110if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
1111{
1112//printf("group tv1\n");
1113channel1 |= ( 0x1 << entries[i+1].index);
1114entries[i+1].type = TYPE_GROUPED;
1115}
1116break;
1117
1118case 1:
1119//printf("group channel 2 : %d\n", i);
1120channel2 |= ( 0x1 << entries[i].index);
1121entries[i].type = TYPE_GROUPED;
1122
1123if ((entries[i - 1].type == 0x0))
1124{
1125channel2 |= ( 0x1 << entries[i-1].index);
1126entries[i-1].type = TYPE_GROUPED;
1127}
1128// group TV as well if there is one
1129if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
1130{
1131//printf("group tv2\n");
1132channel2 |= ( 0x1 << entries[i+1].index);
1133entries[i+1].type = TYPE_GROUPED;
1134}
1135break;
1136}
1137break;
1138}
1139}
1140}
1141}
1142
1143// if we have left ungrouped outputs merge them to the empty channel
1144uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
1145togroup = &channel2;
1146
1147for (i = 0; i < num_outputs; i++)
1148{
1149if (entries[i].type != TYPE_GROUPED)
1150{
1151//printf("%d not grouped\n", i);
1152if (togroup)
1153{
1154*togroup |= ( 0x1 << entries[i].index);
1155}
1156entries[i].type = TYPE_GROUPED;
1157}
1158}
1159
1160if (channel1 > channel2)
1161{
1162uint8_t buff = channel1;
1163channel1 = channel2;
1164channel2 = buff;
1165}
1166
1167default_NVCAP[6] = channel1;
1168default_NVCAP[8] = channel2;
1169
1170// patching HEADS
1171for (i = 0; i < num_outputs; i++)
1172{
1173if (channel1 & (1 << i))
1174{
1175*entries[i].heads = 1;
1176}
1177else if(channel2 & (1 << i))
1178{
1179*entries[i].heads = 2;
1180}
1181}
1182return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
1183}
1184
1185static char *get_nvidia_model(uint32_t id)
1186{
1187int i;
1188
1189for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
1190if (NVKnownChipsets[i].device == id)
1191{
1192return NVKnownChipsets[i].name;
1193}
1194}
1195return NVKnownChipsets[0].name;
1196}
1197
1198static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
1199{
1200int fd;
1201int size;
1202
1203if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)
1204{
1205return 0;
1206}
1207
1208size = file_size(fd);
1209
1210if (size > bufsize)
1211{
1212printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",
1213filename, bufsize);
1214size = bufsize;
1215}
1216size = read(fd, (char *)buf, size);
1217close(fd);
1218
1219return size > 0 ? size : 0;
1220}
1221
1222static int devprop_add_nvidia_template(struct DevPropDevice *device)
1223{
1224char tmp[16];
1225
1226if (!device)
1227return 0;
1228
1229if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
1230return 0;
1231if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
1232return 0;
1233if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))
1234return 0;
1235if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
1236return 0;
1237if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
1238return 0;
1239if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))
1240return 0;
1241if (devices_number == 1)
1242{
1243if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))
1244return 0;
1245}
1246else
1247{
1248if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))
1249return 0;
1250}
1251
1252// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
1253// len = sprintf(tmp, "Slot-%x", devices_number);
1254sprintf(tmp, "Slot-%x",devices_number);
1255devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
1256devices_number++;
1257
1258return 1;
1259}
1260
1261int hex2bin(const char *hex, uint8_t *bin, int len)
1262{
1263char*p;
1264inti;
1265charbuf[3];
1266
1267if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
1268printf("[ERROR] bin2hex input error\n");
1269return -1;
1270}
1271
1272buf[2] = '\0';
1273p = (char *) hex;
1274
1275for (i = 0; i < len; i++)
1276{
1277if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
1278printf("[ERROR] bin2hex '%s' syntax error\n", hex);
1279return -2;
1280}
1281buf[0] = *p++;
1282buf[1] = *p++;
1283bin[i] = (unsigned char) strtoul(buf, NULL, 16);
1284}
1285return 0;
1286}
1287
1288unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
1289{
1290unsigned long long vram_size = 0;
1291
1292if (nvCardType < NV_ARCH_50)
1293{
1294vram_size = REG32(NV04_PFB_FIFO_DATA);
1295vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
1296}
1297else if (nvCardType < NV_ARCH_C0)
1298{
1299vram_size = REG32(NV04_PFB_FIFO_DATA);
1300vram_size |= (vram_size & 0xff) << 32;
1301vram_size &= 0xffffffff00ll;
1302}
1303else // >= NV_ARCH_C0
1304{
1305vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
1306vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
1307}
1308
1309// Workaround for 9600M GT, GT 420/430/440 & GT 525M/540M
1310switch (nvda_dev->device_id)
1311{
1312case 0x0649: vram_size = 512*1024*1024; break;// 9600M GT
1313case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440
1314case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430
1315case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420
1316case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M
1317case 0x0DF4: vram_size = 1024*1024*1024; break; // GT 540M
1318 case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M
1319default: break;
1320}
1321
1322return vram_size;
1323}
1324
1325bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
1326{
1327struct DevPropDevice*device;
1328char*devicepath;
1329option_rom_pci_header_t *rom_pci_header;
1330volatile uint8_t*regs;
1331uint8_t*rom;
1332uint8_t*nvRom;
1333uint8_tnvCardType;
1334unsigned long longvideoRam;
1335uint32_tnvBiosOveride;
1336uint32_tbar[7];
1337uint32_tboot_display;
1338intnvPatch;
1339intlen;
1340charbiosVersion[32];
1341charnvFilename[32];
1342charkNVCAP[12];
1343char*model;
1344const char*value;
1345booldoit;
1346
1347devicepath = get_pci_dev_path(nvda_dev);
1348bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
1349regs = (uint8_t *) (bar[0] & ~0x0f);
1350
1351// get card type
1352nvCardType = (REG32(0) >> 20) & 0x1ff;
1353
1354// Amount of VRAM in kilobytes
1355videoRam = mem_detect(regs, nvCardType, nvda_dev);
1356model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
1357
1358verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
1359model, (uint32_t)(videoRam / 1024 / 1024),
1360(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
1361devicepath);
1362
1363rom = malloc(NVIDIA_ROM_SIZE);
1364sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,
1365(uint16_t)nvda_dev->device_id);
1366
1367if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)
1368{
1369verbose("Looking for nvidia video bios file %s\n", nvFilename);
1370nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
1371
1372if (nvBiosOveride > 0)
1373{
1374verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
1375DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
1376}
1377else
1378{
1379printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
1380return false;
1381}
1382}
1383else
1384{
1385// Otherwise read bios from card
1386nvBiosOveride = 0;
1387
1388// TODO: we should really check for the signature before copying the rom, i think.
1389
1390// PRAMIN first
1391nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
1392bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
1393
1394// Valid Signature ?
1395if (rom[0] != 0x55 && rom[1] != 0xaa)
1396{
1397// PROM next
1398// Enable PROM access
1399(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
1400
1401nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
1402bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
1403
1404// disable PROM access
1405(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
1406
1407// Valid Signature ?
1408if (rom[0] != 0x55 && rom[1] != 0xaa)
1409{
1410// 0xC0000 last
1411bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
1412
1413// Valid Signature ?
1414if (rom[0] != 0x55 && rom[1] != 0xaa)
1415{
1416printf("ERROR: Unable to locate nVidia Video BIOS\n");
1417return false;
1418}
1419else
1420{
1421DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
1422}
1423}
1424else
1425{
1426DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
1427}
1428}
1429else
1430{
1431DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
1432}
1433}
1434
1435if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
1436printf("ERROR: nVidia ROM Patching Failed!\n");
1437//return false;
1438}
1439
1440rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
1441
1442// check for 'PCIR' sig
1443if (rom_pci_header->signature == 0x50434952)
1444{
1445if (rom_pci_header->device_id != nvda_dev->device_id)
1446{
1447// Get Model from the OpROM
1448model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
1449}
1450else
1451{
1452printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
1453}
1454}
1455
1456if (!string) {
1457string = devprop_create_string();
1458}
1459device = devprop_add_device(string, devicepath);
1460
1461/* FIXME: for primary graphics card only */
1462boot_display = 1;
1463if (devices_number == 1)
1464{
1465devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
1466}
1467
1468if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
1469uint8_t built_in = 0x01;
1470devprop_add_value(device, "@0,built-in", &built_in, 1);
1471}
1472
1473// get bios version
1474const int MAX_BIOS_VERSION_LENGTH = 32;
1475char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
1476
1477memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
1478
1479int i, version_start;
1480int crlf_count = 0;
1481
1482// only search the first 384 bytes
1483for (i = 0; i < 0x180; i++)
1484{
1485if (rom[i] == 0x0D && rom[i+1] == 0x0A)
1486{
1487crlf_count++;
1488// second 0x0D0A was found, extract bios version
1489if (crlf_count == 2)
1490{
1491if (rom[i-1] == 0x20) i--; // strip last " "
1492
1493for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)
1494{
1495// find start
1496if (rom[version_start] == 0x00)
1497{
1498version_start++;
1499
1500// strip "Version "
1501if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)
1502{
1503version_start += 8;
1504}
1505
1506strncpy(version_str, (const char*)rom+version_start, i-version_start);
1507break;
1508}
1509}
1510break;
1511}
1512}
1513}
1514
1515sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
1516sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
1517
1518if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)
1519{
1520uint8_t new_NVCAP[NVCAP_LEN];
1521
1522if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)
1523{
1524verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
1525memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
1526}
1527}
1528
1529if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)
1530{
1531uint8_t new_dcfg0[DCFG0_LEN];
1532
1533if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)
1534{
1535memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);
1536
1537verbose("Using user supplied @0,display-cfg\n");
1538printf("@0,display-cfg: %02x%02x%02x%02x\n",
1539 default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);
1540}
1541}
1542
1543if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)
1544{
1545uint8_t new_dcfg1[DCFG1_LEN];
1546
1547if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)
1548{
1549memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);
1550
1551verbose("Using user supplied @1,display-cfg\n");
1552printf("@1,display-cfg: %02x%02x%02x%02x\n",
1553 default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);
1554}
1555}
1556
1557#if DEBUG_NVCAP
1558printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
1559default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
1560default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
1561default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
1562default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
1563default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
1564#endif
1565
1566devprop_add_nvidia_template(device);
1567devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
1568devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
1569devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
1570devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
1571devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);
1572devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);
1573
1574//add HDMI Audio back to nvidia
1575//http://forge.voodooprojects.org/p/chameleon/issues/67/
1576//uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};
1577//devprop_add_value(device, "@1,connector-type",connector_type_1, 4);
1578//end Nvidia HDMI Audio
1579
1580if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)
1581{
1582devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
1583}
1584
1585stringdata = malloc(sizeof(uint8_t) * string->length);
1586memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
1587stringlength = string->length;
1588
1589return true;
1590}
1591

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Revision: 1909