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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉value->word = Platform.CPU.FSBFrequency/1000000;␊
25␉return true;␊
26}␊
27␊
28bool getProcessorInformationMaximumClock(returnType *value)␊
29{␊
30␉value->word = Platform.CPU.CPUFrequency/1000000;␊
31␉return true;␊
32}␊
33␊
34bool getSMBOemProcessorBusSpeed(returnType *value)␊
35{␊
36␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
37␉{␉␉␊
38␉␉switch (Platform.CPU.Family) ␊
39␉␉{␊
40␉␉␉case 0x06:␊
41␉␉␉{␊
42␉␉␉␉switch (Platform.CPU.Model)␊
43␉␉␉␉{␊
44␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
45␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
46␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
47␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
48␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
49␉␉␉␉␉␉return false;␊
50␊
51␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
52␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
53␉␉␉␉␉case CPU_MODEL_DALES:␊
54␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
55␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
56␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
57␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
58␉␉␉␉␉{␊
59␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
60␉␉␉␉␉␉int nhm_bus = 0x3F;␊
61␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
62␉␉␉␉␉␉unsigned long did, vid;␊
63␉␉␉␉␉␉int i;␊
64␉␉␉␉␉␉␊
65␉␉␉␉␉␉// Nehalem supports Scrubbing␊
66␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
67␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
68␉␉␉␉␉␉{␊
69␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
70␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
71␉␉␉␉␉␉␉vid &= 0xFFFF;␊
72␉␉␉␉␉␉␉did &= 0xFF00;␊
73␉␉␉␉␉␉␉␊
74␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
75␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
76␉␉␉␉␉␉}␊
77␉␉␉␉␉␉␊
78␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
79␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
80␉␉␉␉␉␉qpimult &= 0x7F;␊
81␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
82␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
83␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
84␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
85␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
86␉␉␉␉␉␉value->word = qpibusspeed;␊
87␉␉␉␉␉␉return true;␊
88␉␉␉␉␉}␊
89␉␉␉␉}␊
90␉␉␉}␊
91␉␉}␊
92␉}␊
93␉return false;␊
94}␊
95␊
96uint16_t simpleGetSMBOemProcessorType(void)␊
97{␊
98␉if (Platform.CPU.NoCores >= 4) ␊
99␉{␊
100␉␉return 0x0501;␉// Quad-Core Xeon␊
101␉}␊
102␉else if (Platform.CPU.NoCores == 1) ␊
103␉{␊
104␉␉return 0x0201;␉// Core Solo␊
105␉};␊
106␉␊
107␉return 0x0301;␉␉// Core 2 Duo␊
108}␊
109␊
110bool getSMBOemProcessorType(returnType *value)␊
111{␊
112␉static bool done = false;␉␉␊
113␉␉␊
114␉value->word = simpleGetSMBOemProcessorType();␊
115␊
116␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
117␉{␊
118␉␉if (!done)␊
119␉␉{␊
120␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
121␉␉␉done = true;␊
122␉␉}␊
123␉␉␊
124␉␉switch (Platform.CPU.Family) ␊
125␉␉{␊
126␉␉␉case 0x06:␊
127␉␉␉{␊
128␉␉␉␉switch (Platform.CPU.Model)␊
129␉␉␉␉{␊
130␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊
131␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊
132␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
133␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
134␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
135␉␉␉␉␉␉return true;␊
136␊
137␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
138␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
139␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
140␉␉␉␉␉␉else␊
141␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
142␉␉␉␉␉␉return true;␊
143␊
144␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
145␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
146␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
147␉␉␉␉␉␉else␊
148␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
149␉␉␉␉␉␉return true;␊
150␊
151␉␉␉␉␉case CPU_MODEL_DALES:␊
152␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
153␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
154␉␉␉␉␉␉else␊
155␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
156␉␉␉␉␉␉return true;␊
157␊
158␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
159␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
160␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
161␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
162␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
163␉␉␉␉␉␉else␊
164␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
165␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
166␉␉␉␉␉␉␉else␊
167␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
168␉␉␉␉␉␉return true;␊
169␊
170␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
171␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
172 case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
173␉␉␉␉␉␉value->word = 0x0501;␉␉␉␉// Core i7␊
174␉␉␉␉␉␉return true;␊
175␉␉␉␉}␊
176␉␉␉}␊
177␉␉}␊
178␉}␊
179␉␊
180␉return false;␊
181}␊
182␊
183bool getSMBMemoryDeviceMemoryType(returnType *value)␊
184{␊
185␉static int idx = -1;␊
186␉int␉map;␊
187␊
188␉idx++;␊
189␉if (idx < MAX_RAM_SLOTS)␊
190␉{␊
191␉␉map = Platform.DMI.DIMM[idx];␊
192␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
193␉␉{␊
194␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
195␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
196␉␉␉return true;␊
197␉␉}␊
198␉}␊
199␉␊
200␉return false;␊
201//␉value->byte = SMB_MEM_TYPE_DDR2;␊
202//␉return true;␊
203}␊
204␊
205bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
206{␊
207␉static int idx = -1;␊
208␉int␉map;␊
209␊
210␉idx++;␊
211␉if (idx < MAX_RAM_SLOTS)␊
212␉{␊
213␉␉map = Platform.DMI.DIMM[idx];␊
214␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
215␉␉{␊
216␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
217␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
218␉␉␉return true;␊
219␉␉}␊
220␉}␊
221␊
222␉return false;␊
223//␉value->dword = 800;␊
224//␉return true;␊
225}␊
226␊
227bool getSMBMemoryDeviceManufacturer(returnType *value)␊
228{␊
229␉static int idx = -1;␊
230␉int␉map;␊
231␊
232␉idx++;␊
233␉if (idx < MAX_RAM_SLOTS)␊
234␉{␊
235␉␉map = Platform.DMI.DIMM[idx];␊
236␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
237␉␉{␊
238␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
239␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
240␉␉␉return true;␊
241␉␉}␊
242␉}␊
243␊
244␉if (!bootInfo->memDetect)␊
245␉␉return false;␊
246␉value->string = NOT_AVAILABLE;␊
247␉return true;␊
248}␊
249␉␊
250bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
251{␊
252␉static int idx = -1;␊
253␉int␉map;␊
254␊
255␉idx++;␊
256␊
257 DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
258␊
259␉if (idx < MAX_RAM_SLOTS)␊
260␉{␊
261␉␉map = Platform.DMI.DIMM[idx];␊
262␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
263␉␉{␊
264␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
265␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
266␉␉␉return true;␊
267␉␉}␊
268␉}␊
269␊
270␉if (!bootInfo->memDetect)␊
271␉␉return false;␊
272␉value->string = NOT_AVAILABLE;␊
273␉return true;␊
274}␊
275␊
276bool getSMBMemoryDevicePartNumber(returnType *value)␊
277{␊
278␉static int idx = -1;␊
279␉int␉map;␊
280␊
281␉idx++;␊
282␉if (idx < MAX_RAM_SLOTS)␊
283␉{␊
284␉␉map = Platform.DMI.DIMM[idx];␊
285␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
286␉␉{␊
287␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
288␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
289␉␉␉return true;␊
290␉␉}␊
291␉}␊
292␊
293␉if (!bootInfo->memDetect)␊
294␉␉return false;␊
295␉value->string = NOT_AVAILABLE;␊
296␉return true;␊
297}␊
298␊
299␊
300// getting smbios addr with fast compare ops, late checksum testing ...␊
301#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
302static const char * const SMTAG = "_SM_";␊
303static const char* const DMITAG = "_DMI_";␊
304␊
305SMBEntryPoint *getAddressOfSmbiosTable(void)␊
306{␊
307␉SMBEntryPoint␉*smbios;␊
308␉/* ␊
309␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
310␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
311␉ */␊
312␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
313␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
314␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
315␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
316␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
317␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
318␉ {␊
319␉␉␉return smbios;␊
320␉ }␊
321␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
322␉}␊
323␉printf("ERROR: Unable to find SMBIOS!\n");␊
324␉pause();␊
325␉return NULL;␊
326}␊
327␊
328

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