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Root/branches/ErmaC/Trunk/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74␊
75extern uint32_t devices_number;␊
76␊
77const char *nvidia_compatible_0[] =␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
78const char *nvidia_compatible_1[] =␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
79const char *nvidia_device_type_0[] =␉{ "@0,device_type", "display"␉␉ };␊
80const char *nvidia_device_type_1[] =␉{ "@1,device_type", "display"␉␉ };␊
81const char *nvidia_device_type[] =␉{ "device_type",␉"NVDA,Parent"␉ };␊
82const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
83const char *nvidia_name_0[] =␉{ "@0,name",␉␉"NVDA,Display-A" };␊
84const char *nvidia_name_1[] =␉{ "@1,name",␉␉"NVDA,Display-B" };␊
85const char *nvidia_slot_name[] =␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
86␊
87// uint8_t display_cfg_0[]␉␉␉=␉{0x03, 0x01, 0x03, 0x00};␊
88// uint8_t display_cfg_1[]␉␉␉=␉{0xff, 0xff, 0x00, 0x01};␊
89// uint8_t connector_type_1[]␉␉=␉{0x00, 0x08, 0x00, 0x00};␊
90␊
91static uint8_t default_NVCAP[]= {␊
92␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
93␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
94␉0x00, 0x00, 0x00, 0x00␊
95};␊
96␊
97static uint8_t default_NVPM[]= {␊
98 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
99 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊
101 0x00, 0x00, 0x00, 0x00␊
102};␊
103␊
104#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
105#define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊
106␊
107static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
108static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
109␊
110#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
111#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
112␊
113static struct nv_chipsets_t NVKnownChipsets[] = {␊
114␉{ 0x00000000, "Unknown" },␊
115//========================================␊
116␉// 0000 - 0040␉␊
117//␉{ 0x10DE0001, "NVIDIA HDMI Audio" },␊
118//␉{ 0x10DE0002, "NVIDIA HDMI Audio" },␊
119//␉{ 0x10DE0003, "NVIDIA HDMI Audio" },␊
120//␉{ 0x10DE0005, "NVIDIA HDMI Audio" },␊
121//␉{ 0x10DE0006, "NVIDIA HDMI Audio" },␊
122//␉{ 0x10DE0007, "NVIDIA HDMI Audio" },␊
123//␉{ 0x10DE0008, "NVIDIA HDMI Audio" },␊
124//␉{ 0x10DE0009, "NVIDIA HDMI Audio" },␊
125//␉{ 0x10DE000A, "NVIDIA HDMI Audio" },␊
126//␉{ 0x10DE000B, "NVIDIA HDMI Audio" },␊
127//␉{ 0x10DE000C, "NVIDIA HDMI Audio" },␊
128//␉{ 0x10DE000D, "NVIDIA HDMI Audio" },␊
129//␉{ 0x10DE0010, "NVIDIA HDMI Audio" },␊
130//␉{ 0x10DE0011, "NVIDIA HDMI Audio" },␊
131//␉{ 0x10DE0012, "NVIDIA HDMI Audio" },␊
132//␉{ 0x10DE0014, "NVIDIA HDMI Audio" },␊
133//␉{ 0x10DE0018, "NVIDIA HDMI Audio" },␊
134␉// 0040 - 004F␉␊
135␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
136␉{ 0x10DE0041, "GeForce 6800" },␊
137␉{ 0x10DE0042, "GeForce 6800 LE" },␊
138␉{ 0x10DE0043, "GeForce 6800 XE" },␊
139␉{ 0x10DE0044, "GeForce 6800 XT" },␊
140␉{ 0x10DE0045, "GeForce 6800 GT" },␊
141␉{ 0x10DE0046, "GeForce 6800 GT" },␊
142␉{ 0x10DE0047, "GeForce 6800 GS" },␊
143␉{ 0x10DE0048, "GeForce 6800 XT" },␊
144␉{ 0x10DE004D, "Quadro FX 3400" },␊
145␉{ 0x10DE004E, "Quadro FX 4000" },␊
146␉// 0050 - 005F␊
147//␉{ 0x10DE0059, "CK804 AC'97 Audio Controller" },␊
148␉// 0060 - 006F␊
149//␉{ 0x10DE006A, "nForce2 AC97 Audio Controler (MCP)" },␊
150//␉{ 0x10DE0067, "NVIDIA HDMI Audio" },␊
151//␉{ 0x10DE0073, "NVIDIA HDMI Audio" },␊
152␉// 0070 - 007F␊
153␉// 0080 - 008F␊
154␉// 0090 - 009F␊
155␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
156␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
157␉{ 0x10DE0092, "GeForce 7800 GT" },␊
158␉{ 0x10DE0093, "GeForce 7800 GS" },␊
159␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
160␉{ 0x10DE0098, "GeForce Go 7800" },␊
161␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
162␉{ 0x10DE009D, "Quadro FX 4500" },␊
163␉// 00A0 - 00AF␉␊
164␉// 00B0 - 00BF␉␊
165␉// 00C0 - 00CF␉␊
166␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
167␉{ 0x10DE00C1, "GeForce 6800" },␊
168␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
169␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
170␉{ 0x10DE00C8, "GeForce Go 6800" },␊
171␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
172␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
173␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
174␉{ 0x10DE00CE, "Quadro FX 1400" },␊
175//␉{ 0x10DE00DA, "nForce3 Audio" },␊
176␉// 00D0 - 00DF␉␊
177␉// 00E0 - 00EF␉␊
178␉// 00F0 - 00FF␉␊
179␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
180␉{ 0x10DE00F2, "GeForce 6600" },␊
181␉{ 0x10DE00F3, "GeForce 6200" },␊
182␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
183␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
184␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
185␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
186␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
187␉// 0100 - 010F␉␊
188␉// 0110 - 011F␉␊
189␉// 0120 - 012F␉␊
190␉// 0130 - 013F␉␊
191␉// 0140 - 014F␉␊
192␉{ 0x10DE0140, "GeForce 6600 GT" },␊
193␉{ 0x10DE0141, "GeForce 6600" },␊
194␉{ 0x10DE0142, "GeForce 6600 LE" },␊
195␉{ 0x10DE0143, "GeForce 6600 VE" },␊
196␉{ 0x10DE0144, "GeForce Go 6600" },␊
197␉{ 0x10DE0145, "GeForce 6610 XL" },␊
198␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
199␉{ 0x10DE0147, "GeForce 6700 XL" },␊
200␉{ 0x10DE0148, "GeForce Go 6600" },␊
201␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
202␉{ 0x10DE014A, "Quadro NVS 440" },␊
203␉{ 0x10DE014C, "Quadro FX 550" },␊
204␉{ 0x10DE014D, "Quadro FX 550" },␊
205␉{ 0x10DE014E, "Quadro FX 540" },␊
206␉{ 0x10DE014F, "GeForce 6200" },␊
207␉// 0150 - 015F␉␊
208␉// 0160 - 016F␉␊
209␉{ 0x10DE0160, "GeForce 6500" },␊
210␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
211␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
212␉{ 0x10DE0163, "GeForce 6200 LE" },␊
213␉{ 0x10DE0164, "GeForce Go 6200" },␊
214␉{ 0x10DE0165, "Quadro NVS 285" },␊
215␉{ 0x10DE0166, "GeForce Go 6400" },␊
216␉{ 0x10DE0167, "GeForce Go 6200" },␊
217␉{ 0x10DE0168, "GeForce Go 6400" },␊
218␉{ 0x10DE0169, "GeForce 6250" },␊
219␉{ 0x10DE016A, "GeForce 7100 GS" },␊
220␉{ 0x10DE016C, "NVIDIA NV44GLM" }, //␊
221␉{ 0x10DE016D, "NVIDIA NV44GLM" }, //␊
222␉// 0170 - 017F␉␊
223␉// 0180 - 018F␉␊
224␉// 0190 - 019F␉␉␊
225␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
226␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
227␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
228␉{ 0x10DE0197, "Tesla C870" },␊
229␉{ 0x10DE019D, "Quadro FX 5600" },␊
230␉{ 0x10DE019E, "Quadro FX 4600" },␊
231␉// 01A0 - 01AF␊
232␉// 01B0 - 01BF␊
233//␉{ 0x10DE01B1, "nForce AC'97 Audio Controller" },␊
234␉// 01C0 - 01CF␊
235␉// 01D0 - 01DF␊
236␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
237␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
238␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
239␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
240␉{ 0x10DE01D6, "GeForce Go 7200" },␊
241␉{ 0x10DE01D7, "GeForce Go 7300" },␊
242␉{ 0x10DE01D8, "GeForce Go 7400" },␊
243␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
244␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
245␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
246␉{ 0x10DE01DC, "Quadro FX 350M" },␊
247␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
248␉{ 0x10DE01DE, "Quadro FX 350" },␊
249␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
250␉// 01E0 - 01EF␉␊
251␉// 01F0 - 01FF␊
252␉{ 0x10DE01F0, "GeForce4 MX" }, //␊
253␉// 0200 - 020F␉␊
254␉// 0210 - 021F␉␊
255␉{ 0x10DE0211, "GeForce 6800" },␊
256␉{ 0x10DE0212, "GeForce 6800 LE" },␊
257␉{ 0x10DE0215, "GeForce 6800 GT" },␊
258␉{ 0x10DE0218, "GeForce 6800 XT" },␊
259␉// 0220 - 022F␊
260␉{ 0x10DE0221, "GeForce 6200" },␊
261␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
262␉{ 0x10DE0228, "NVIDIA NV44M" }, // ␊
263␉// 0230 - 023F␊
264␉// 0240 - 024F␊
265␉{ 0x10DE0240, "GeForce 6150" },␊
266␉{ 0x10DE0241, "GeForce 6150 LE" },␊
267␉{ 0x10DE0242, "GeForce 6100" },␊
268␉{ 0x10DE0243, "NVIDIA C51" }, //␊
269␉{ 0x10DE0244, "GeForce Go 6150" },␊
270␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
271␉{ 0x10DE0247, "GeForce Go 6100" },␊
272␉// 0250 - 025F␊
273␉{ 0x10DE025B, "Quadro4 700 XGL" }, //␊
274␉// 0260 - 026F␊
275␉// 0270 - 027F␊
276␉// 0280 - 028F␊
277␉// 0290 - 029F␊
278␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
279␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
280␉{ 0x10DE0292, "GeForce 7900 GS" },␊
281␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
282␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
283␉{ 0x10DE0295, "GeForce 7950 GT" },␊
284␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
285␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
286␉{ 0x10DE029A, "Quadro FX 2500M" },␊
287␉{ 0x10DE029B, "Quadro FX 1500M" },␊
288␉{ 0x10DE029C, "Quadro FX 5500" },␊
289␉{ 0x10DE029D, "Quadro FX 3500" },␊
290␉{ 0x10DE029E, "Quadro FX 1500" },␊
291␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
292␉// 02A0 - 02AF␊
293␉// 02B0 - 02BF␊
294␉// 02C0 - 02CF␊
295␉// 02D0 - 02DF␊
296␉// 02E0 - 02EF␊
297␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
298␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
299␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
300␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
301␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
302␉// 02F0 - 02FF␊
303␉// 0300 - 030F␊
304␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
305␉{ 0x10DE0302, "GeForce FX 5800" },␊
306␉{ 0x10DE0308, "Quadro FX 2000" },␊
307␉{ 0x10DE0309, "Quadro FX 1000" },␊
308␉// 0310 - 031F␊
309␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
310␉{ 0x10DE0312, "GeForce FX 5600" },␊
311␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
312␉{ 0x10DE031A, "GeForce FX Go5600" },␊
313␉{ 0x10DE031B, "GeForce FX Go5650" },␊
314␉{ 0x10DE031C, "Quadro FX Go700" },␊
315␉// 0320 - 032F␊
316␉{ 0x10DE0320, "GeForce FX 5200" }, //␊
317␉{ 0x10DE0321, "GeForce FX 5200 Ultra" }, //␊
318␉{ 0x10DE0322, "GeForce FX 5200" }, //␊
319␉{ 0x10DE0323, "GeForce FX 5200 LE" }, //␊
320␉{ 0x10DE0324, "GeForce FX Go5200" },␊
321␉{ 0x10DE0325, "GeForce FX Go5250" },␊
322␉{ 0x10DE0326, "GeForce FX 5500" },␊
323␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
324␉{ 0x10DE0329, "GeForce FX Go5200" }, //␊
325␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
326␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
327␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
328␉{ 0x10DE032D, "GeForce FX Go5100" },␊
329//␉{ 0x10DE032F, "NVIDIA NV34GL" },//␊
330␉// 0330 - 033F␊
331␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
332␉{ 0x10DE0331, "GeForce FX 5900" },␊
333␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
334␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
335␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
336␉{ 0x10DE0338, "Quadro FX 3000" },␊
337␉{ 0x10DE033F, "Quadro FX 700" },␊
338␉// 0340 - 034F␊
339␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
340␉{ 0x10DE0342, "GeForce FX 5700" },␊
341␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
342␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
343//␉{ 0x10DE0345, "NVIDIA NV36.5" }, //␊
344␉{ 0x10DE0347, "GeForce FX Go5700" },␊
345␉{ 0x10DE0348, "GeForce FX Go5700" },␊
346//␉{ 0x10DE0349, "NVIDIA NV36M Pro" }, //␊
347//␉{ 0x10DE034B, "NVIDIA NV36MAP" }, //␊
348␉{ 0x10DE034C, "Quadro FX Go1000" },␊
349␉{ 0x10DE034E, "Quadro FX 1100" },␊
350//␉{ 0x10DE034F, "NVIDIA NV36GL" }, //␊
351␉// 0350 - 035F␊
352␉// 0360 - 036F␊
353␉// 0370 - 037F␊
354␉// 0380 - 038F␊
355␉{ 0x10DE038B, "GeForce 7650 GS" },␊
356␉// 0390 - 039F␊
357␉{ 0x10DE0390, "GeForce 7650 GS" },␊
358␉{ 0x10DE0391, "GeForce 7600 GT" },␊
359␉{ 0x10DE0392, "GeForce 7600 GS" },␊
360␉{ 0x10DE0393, "GeForce 7300 GT" },␊
361␉{ 0x10DE0394, "GeForce 7600 LE" },␊
362␉{ 0x10DE0395, "GeForce 7300 GT" },␊
363␉{ 0x10DE0397, "GeForce Go 7700" },␊
364␉{ 0x10DE0398, "GeForce Go 7600" },␊
365␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
366␉{ 0x10DE039A, "Quadro NVS 300M" },␊
367␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
368␉{ 0x10DE039C, "Quadro FX 560M" },␊
369␉{ 0x10DE039E, "Quadro FX 560" },␊
370␉// 03A0 - 03AF␊
371␉// 03B0 - 03BF␊
372␉// 03C0 - 03CF␊
373␉// 03D0 - 03DF␊
374␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
375␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
376␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
377␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
378␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
379␉// 03E0 - 03EF␊
380␉// 03F0 - 03FF␊
381␉// 0400 - 040F␊
382␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
383␉{ 0x10DE0401, "GeForce 8600 GT" },␊
384␉{ 0x10DE0402, "GeForce 8600 GT" },␊
385␉{ 0x10DE0403, "GeForce 8600 GS" },␊
386␉{ 0x10DE0404, "GeForce 8400 GS" },␊
387␉{ 0x10DE0405, "GeForce 9500M GS" },␊
388␉{ 0x10DE0406, "GeForce 8300 GS" },␊
389␉{ 0x10DE0407, "GeForce 8600M GT" },␊
390␉{ 0x10DE0408, "GeForce 9650M GS" },␊
391␉{ 0x10DE0409, "GeForce 8700M GT" },␊
392␉{ 0x10DE040A, "Quadro FX 370" },␊
393␉{ 0x10DE040B, "Quadro NVS 320M" },␊
394␉{ 0x10DE040C, "Quadro FX 570M" },␊
395␉{ 0x10DE040D, "Quadro FX 1600M" },␊
396␉{ 0x10DE040E, "Quadro FX 570" },␊
397␉{ 0x10DE040F, "Quadro FX 1700" },␊
398␉// 0410 - 041F␊
399␉{ 0x10DE0410, "GeForce GT 330" },␊
400␉// 0420 - 042F␊
401␉{ 0x10DE0420, "GeForce 8400 SE" },␊
402␉{ 0x10DE0421, "GeForce 8500 GT" },␊
403␉{ 0x10DE0422, "GeForce 8400 GS" },␊
404␉{ 0x10DE0423, "GeForce 8300 GS" },␊
405␉{ 0x10DE0424, "GeForce 8400 GS" },␊
406␉{ 0x10DE0425, "GeForce 8600M GS" },␊
407␉{ 0x10DE0426, "GeForce 8400M GT" },␊
408␉{ 0x10DE0427, "GeForce 8400M GS" },␊
409␉{ 0x10DE0428, "GeForce 8400M G" },␊
410␉{ 0x10DE0429, "Quadro NVS 140M" },␊
411␉{ 0x10DE042A, "Quadro NVS 130M" },␊
412␉{ 0x10DE042B, "Quadro NVS 135M" },␊
413␉{ 0x10DE042C, "GeForce 9400 GT" },␊
414␉{ 0x10DE042D, "Quadro FX 360M" },␊
415␉{ 0x10DE042E, "GeForce 9300M G" },␊
416␉{ 0x10DE042F, "Quadro NVS 290" },␊
417␉// 0430 - 043F␊
418␉// 0440 - 044F␊
419␉// 0450 - 045F␊
420␉// 0460 - 046F␊
421␉// 0470 - 047F␊
422␉// 0480 - 048F␊
423␉// 0490 - 049F␊
424␉// 04A0 - 04AF␊
425␉// 04B0 - 04BF␊
426␉// 04C0 - 04CF␊
427␉{ 0x10DE04C0, "NVIDIA G78" }, //␊
428␉{ 0x10DE04C1, "NVIDIA G78" }, //␊
429␉{ 0x10DE04C2, "NVIDIA G78" }, //␊
430␉{ 0x10DE04C3, "NVIDIA G78" }, //␊
431␉{ 0x10DE04C4, "NVIDIA G78" }, //␊
432␉{ 0x10DE04C5, "NVIDIA G78" }, //␊
433␉{ 0x10DE04C6, "NVIDIA G78" }, //␊
434␉{ 0x10DE04C7, "NVIDIA G78" }, //␊
435␉{ 0x10DE04C8, "NVIDIA G78" }, //␊
436␉{ 0x10DE04C9, "NVIDIA G78" }, //␊
437␉{ 0x10DE04CA, "NVIDIA G78" }, //␊
438␉{ 0x10DE04CB, "NVIDIA G78" }, //␊
439␉{ 0x10DE04CC, "NVIDIA G78" }, //␊
440␉{ 0x10DE04CD, "NVIDIA G78" }, //␊
441␉{ 0x10DE04CE, "NVIDIA G78" }, //␊
442␉{ 0x10DE04CF, "NVIDIA G78" }, //␊
443␉// 04D0 - 04DF␊
444␉// 04E0 - 04EF␊
445␉// 04F0 - 04FF␊
446␉// 0500 - 050F␊
447␉// 0510 - 051F␊
448␉// 0520 - 052F␊
449␉// 0530 - 053F␊
450␉{ 0x10DE0530, "GeForce 7190M / nForce 650M" },␊
451␉{ 0x10DE0531, "GeForce 7150M / nForce 630M" },␊
452␉{ 0x10DE0533, "GeForce 7000M / nForce 610M" },␊
453␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
454␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
455␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
456␉// 0540 - 054F␊
457␉// 0550 - 055F␊
458␉// 0560 - 056F␊
459␉// 0570 - 057F␊
460␉// 0580 - 058F␊
461␉// 0590 - 059F␊
462␉// 05A0 - 05AF␊
463␉// 05B0 - 05BF␊
464␉// 05C0 - 05CF␊
465␉// 05D0 - 05DF␊
466␉// 05E0 - 05EF␊
467␉{ 0x10DE05E0, "GeForce GTX 295" },␊
468␉{ 0x10DE05E1, "GeForce GTX 280" },␊
469␉{ 0x10DE05E2, "GeForce GTX 260" },␊
470␉{ 0x10DE05E3, "GeForce GTX 285" },␊
471␉{ 0x10DE05E4, "NVIDIA GT200" }, //␊
472␉{ 0x10DE05E5, "NVIDIA GT200" }, //␊
473␉{ 0x10DE05E6, "GeForce GTX 275" },␊
474␉{ 0x10DE05E7, "Tesla C1060" },␊
475␉{ 0x10DE05E8, "NVIDIA GT200" }, //␊
476␉{ 0x10DE05E9, "NVIDIA GT200" }, //␊
477␉{ 0x10DE05EA, "GeForce GTX 260" },␊
478␉{ 0x10DE05EB, "GeForce GTX 295" },␊
479␉{ 0x10DE05EC, "NVIDIA GT200" }, //␊
480␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
481␉{ 0x10DE05EE, "NVIDIA GT200" }, //␊
482␉{ 0x10DE05EF, "NVIDIA GT200" }, //␊
483␉// 05F0 - 05FF␊
484␉{ 0x10DE05F0, "NVIDIA GT200" }, //␊
485␉{ 0x10DE05F1, "NVIDIA GT200" }, //␊
486␉{ 0x10DE05F2, "NVIDIA GT200" }, //␊
487␉{ 0x10DE05F3, "NVIDIA GT200" }, //␊
488␉{ 0x10DE05F4, "NVIDIA GT200" }, //␊
489␉{ 0x10DE05F5, "NVIDIA GT200" }, //␊
490␉{ 0x10DE05F6, "NVIDIA GT200" }, //␊
491␉{ 0x10DE05F7, "NVIDIA GT200" }, //␊
492␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
493␉{ 0x10DE05F9, "Quadro CX" },␊
494␉{ 0x10DE05FA, "NVIDIA GT200" }, //␊
495␉{ 0x10DE05FB, "NVIDIA GT200" }, //␊
496␉{ 0x10DE05FC, "NVIDIA GT200" }, //␊
497␉{ 0x10DE05FD, "Quadro FX 5800" },␊
498␉{ 0x10DE05FE, "Quadro FX 4800" },␊
499␉{ 0x10DE05FF, "Quadro FX 3800" },␊
500␉// 0600 - 060F␊
501␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
502␉{ 0x10DE0601, "GeForce 9800 GT" },␊
503␉{ 0x10DE0602, "GeForce 8800 GT" },␊
504␉{ 0x10DE0603, "GeForce GT 230" },␊
505␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
506␉{ 0x10DE0605, "GeForce 9800 GT" },␊
507␉{ 0x10DE0606, "GeForce 8800 GS" },␊
508␉{ 0x10DE0607, "GeForce GTS 240" },␊
509␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
510␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
511␉{ 0x10DE060A, "GeForce GTX 280M" },␊
512␉{ 0x10DE060B, "GeForce 9800M GT" },␊
513␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
514␉{ 0x10DE060D, "GeForce 8800 GS" },␊
515␉{ 0x10DE060F, "GeForce GTX 285M" },␊
516␉// 0610 - 061F␊
517␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
518␉{ 0x10DE0611, "GeForce 8800 GT" },␊
519␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
520␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
521␉{ 0x10DE0614, "GeForce 9800 GT" },␊
522␉{ 0x10DE0615, "GeForce GTS 250" },␊
523␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
524␉{ 0x10DE0618, "GeForce GTX 260M" },␊
525␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
526␉{ 0x10DE061A, "Quadro FX 3700" },␊
527␉{ 0x10DE061B, "Quadro VX 200" },␊
528␉{ 0x10DE061C, "Quadro FX 3600M" },␊
529␉{ 0x10DE061D, "Quadro FX 2800M" },␊
530␉{ 0x10DE061E, "Quadro FX 3700M" },␊
531␉{ 0x10DE061F, "Quadro FX 3800M" },␊
532␉// 0620 - 062F␊
533␉{ 0x10DE0620, "NVIDIA G94" }, // GeForce 8100/8200/8300␊
534␉{ 0x10DE0621, "GeForce GT 230" },␊
535␉{ 0x10DE0622, "GeForce 9600 GT" },␊
536␉{ 0x10DE0623, "GeForce 9600 GS" },␊
537␉{ 0x10DE0624, "NVIDIA G94" }, //␊
538␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
539␉{ 0x10DE0626, "GeForce GT 130" },␊
540␉{ 0x10DE0627, "GeForce GT 140" },␊
541␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
542␉{ 0x10DE0629, "NVIDIA G94" }, //␊
543␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
544␉{ 0x10DE062B, "GeForce 9800M GS" },␊
545␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
546␉{ 0x10DE062D, "GeForce 9600 GT" },␊
547␉{ 0x10DE062E, "GeForce 9600 GT" },␊
548␉{ 0x10DE062F, "GeForce 9800 S" }, //␊
549␉// 0630 - 063F␊
550␉{ 0x10DE0630, "NVIDIA G94" }, //␊
551␉{ 0x10DE0631, "GeForce GTS 160M" },␊
552␉{ 0x10DE0632, "GeForce GTS 150M" },␊
553␉{ 0x10DE0633, "NVIDIA G94" }, //␊
554␉{ 0x10DE0634, "NVIDIA G94" }, //␊
555␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
556␉{ 0x10DE0636, "NVIDIA G94" }, //␊
557␉{ 0x10DE0637, "GeForce 9600 GT" },␊
558␉{ 0x10DE0638, "Quadro FX 1800" },␊
559␉{ 0x10DE0639, "NVIDIA G94" }, //␊
560␉{ 0x10DE063A, "Quadro FX 2700M" },␊
561␉{ 0x10DE063B, "NVIDIA G94" }, //␊
562␉{ 0x10DE063C, "NVIDIA G94" }, //␊
563␉{ 0x10DE063D, "NVIDIA G94" }, //␊
564␉{ 0x10DE063E, "NVIDIA G94" }, //␊
565␉{ 0x10DE063F, "NVIDIA G94" }, //␊
566␉// 0640 - 064F␊
567␉{ 0x10DE0640, "GeForce 9500 GT" },␊
568␉{ 0x10DE0641, "GeForce 9400 GT" },␊
569␉{ 0x10DE0642, "GeForce 8400 GS" },␊
570␉{ 0x10DE0643, "GeForce 9500 GT" },␊
571␉{ 0x10DE0644, "GeForce 9500 GS" },␊
572␉{ 0x10DE0645, "GeForce 9500 GS" },␊
573␉{ 0x10DE0646, "GeForce GT 120" },␊
574␉{ 0x10DE0647, "GeForce 9600M GT" },␊
575␉{ 0x10DE0648, "GeForce 9600M GS" },␊
576␉{ 0x10DE0649, "GeForce 9600M GT" },␊
577␉{ 0x10DE064A, "GeForce 9700M GT" },␊
578␉{ 0x10DE064B, "GeForce 9500M G" },␊
579␉{ 0x10DE064C, "GeForce 9650M GT" },␊
580␉// 0650 - 065F␊
581␉{ 0x10DE0650, "NVIDIA G96-825" }, //␊
582␉{ 0x10DE0651, "GeForce G 110M" },␊
583␉{ 0x10DE0652, "GeForce GT 130M" },␊
584␉{ 0x10DE0653, "GeForce GT 120M" },␊
585␉{ 0x10DE0654, "GeForce GT 220M" },␊
586␉{ 0x10DE0655, "GeForce GT 120" },␊
587␉{ 0x10DE0656, "GeForce 9650 S" },␊
588␉{ 0x10DE0657, "NVIDIA G96" }, //␊
589␉{ 0x10DE0658, "Quadro FX 380" },␊
590␉{ 0x10DE0659, "Quadro FX 580" },␊
591␉{ 0x10DE065A, "Quadro FX 1700M" },␊
592␉{ 0x10DE065B, "GeForce 9400 GT" },␊
593␉{ 0x10DE065C, "Quadro FX 770M" },␊
594␉{ 0x10DE065D, "NVIDIA G96" }, //␊
595␉{ 0x10DE065E, "NVIDIA G96" }, //␊
596␉{ 0x10DE065F, "GeForce G210" },␊
597␉// 0660 - 066F␊
598␉// 0670 - 067F␊
599␉// 0680 - 068F␊
600␉// 0690 - 069F␊
601␉// 06A0 - 06AF␊
602␉{ 0x10DE06A0, "NVIDIA GT214" }, //␊
603␉// 06B0 - 06BF␊
604␉{ 0x10DE06B0, "NVIDIA GT214" }, //␊
605␉// 06C0 - 06CF␊
606␉{ 0x10DE06C0, "GeForce GTX 480" },␊
607␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
608␉{ 0x10DE06C4, "GeForce GTX 465" },␊
609␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
610␉{ 0x10DE06CD, "GeForce GTX 470" },␊
611␉// 06D0 - 06DF␊
612␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
613␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
614␉{ 0x10DE06D2, "Tesla M2070" },␊
615␉{ 0x10DE06D8, "Quadro 6000" },␊
616␉{ 0x10DE06D9, "Quadro 5000" },␊
617␉{ 0x10DE06DA, "Quadro 5000M" },␊
618␉{ 0x10DE06DC, "Quadro 6000" },␊
619␉{ 0x10DE06DD, "Quadro 4000" },␊
620␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
621␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
622␉{ 0x10DE06DF, "Tesla M2070-Q" },␊
623␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
624␉// 06E0 - 06EF␊
625␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
626␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
627␉{ 0x10DE06E2, "GeForce 8400" },␊
628␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
629␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
630␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
631␉{ 0x10DE06E6, "GeForce G100" },␊
632␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
633␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
634␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
635␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
636␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
637␉{ 0x10DE06EC, "GeForce G 105M" },␊
638␉{ 0x10DE06ED, "NVIDIA G98" }, //␊
639␉{ 0x10DE06EF, "GeForce G 103M" },␊
640␉// 06F0 - 06FF␊
641␉{ 0x10DE06F0, "NVIDIA G98" }, //␊
642␉{ 0x10DE06F1, "GeForce G105M" },␊
643␉{ 0x10DE06F2, "NVIDIA G98" }, //␊
644␉{ 0x10DE06F3, "NVIDIA G98" }, //␊
645␉{ 0x10DE06F4, "NVIDIA G98" }, //␊
646␉{ 0x10DE06F5, "NVIDIA G98" }, //␊
647␉{ 0x10DE06F6, "NVIDIA G98" }, //␊
648␉{ 0x10DE06F7, "NVIDIA G98" }, //␊
649␉{ 0x10DE06F8, "Quadro NVS 420" },␊
650␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
651␉{ 0x10DE06FA, "Quadro NVS 450" },␊
652␉{ 0x10DE06FB, "Quadro FX 370M" },␊
653␉{ 0x10DE06FC, "NVIDIA G98" }, //␊
654␉{ 0x10DE06FD, "Quadro NVS 295" },␊
655␉{ 0x10DE06FE, "NVIDIA G98" }, //␊
656␉{ 0x10DE06FF, "HICx16 + Graphics" },␊
657␉// 0700 - 070F␊
658␉// 0710 - 071F␊
659␉// 0720 - 072F␊
660␉// 0730 - 073F␊
661␉// 0740 - 074F␊
662␉// 0750 - 075F␊
663//␉{ 0x10DE0759, "nVidia Standard Dual Channel PCI IDE Controller" },␊
664␉// 0760 - 076F␊
665␉// 0770 - 077F␊
666//␉{ 0x10DE0774, "nVidia Microsoft UAA Bus Driver for High Definition Audio" },␊
667//␉{ 0x10DE077B, "nVidia Standard OpenHCD USB Host Controller" },␊
668//␉{ 0x10DE077C, "nVidia Standard Enhanced PCI to USB Host Controller" },␊
669//␉{ 0x10DE077D, "nVidia Standard OpenHCD USB Host Controller" },␊
670//␉{ 0x10DE077E, "nVidia Standard Enhanced PCI to USB Host Controller" },␊
671␉// 0780 - 078F␊
672␉// 0790 - 079F␊
673␉// 07A0 - 07AF␊
674␉// 07B0 - 07BF␊
675␉// 07C0 - 07CF␊
676␉// 07D0 - 07DF␊
677␉// 07E0 - 07EF␊
678␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
679␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
680␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
681␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
682//␉{ 0x10DE07E4, "NVIDIA MCP73" },␊
683␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
684//␉{ 0x10DE07E6, "NVIDIA MCP73" },␊
685//␉{ 0x10DE07E7, "NVIDIA MCP73" },␊
686//␉{ 0x10DE07E8, "NVIDIA MCP73" },␊
687//␉{ 0x10DE07E9, "NVIDIA MCP73" },␊
688//␉{ 0x10DE07EA, "NVIDIA MCP73" },␊
689//␉{ 0x10DE07EB, "NVIDIA MCP73" },␊
690//␉{ 0x10DE07ED, "NVIDIA MCP73" },␊
691//␉{ 0x10DE07EE, "NVIDIA MCP73" },␊
692//␉{ 0x10DE07EF, "NVIDIA MCP73" },␊
693␉// 07F0 - 07FF␊
694␉// 0800 - 080F␊
695␉// 0810 - 081F␊
696␉// 0820 - 082F␊
697␉// 0830 - 083F␊
698␉// 0840 - 084F␊
699␉{ 0x10DE0840, "GeForce 8200M" },␊
700//␉{ 0x10DE0841, "NVIDIA MCP77/78" },␊
701//␉{ 0x10DE0842, "NVIDIA MCP77/78" },␊
702␉{ 0x10DE0844, "GeForce 9100M G" },␊
703␉{ 0x10DE0845, "GeForce 8200M G" },␊
704␉{ 0x10DE0846, "GeForce 9200" },␊
705␉{ 0x10DE0847, "GeForce 9100" },␊
706␉{ 0x10DE0848, "GeForce 8300" },␊
707␉{ 0x10DE0849, "GeForce 8200" },␊
708␉{ 0x10DE084A, "nForce 730a" },␊
709␉{ 0x10DE084B, "GeForce 9200" },␊
710␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
711␉{ 0x10DE084D, "nForce 750a SLI" },␊
712␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
713␉// 0850 - 085F␊
714//␉{ 0x10DE0850, "NVIDIA MCP77/78" },␊
715//␉{ 0x10DE0851, "NVIDIA MCP77/78" },␊
716//␉{ 0x10DE0852, "NVIDIA MCP77/78" },␊
717//␉{ 0x10DE0853, "NVIDIA MCP77/78" },␊
718//␉{ 0x10DE0854, "NVIDIA MCP77/78" },␊
719//␉{ 0x10DE0855, "NVIDIA MCP77/78" },␊
720//␉{ 0x10DE0856, "NVIDIA MCP77/78" },␊
721//␉{ 0x10DE0857, "NVIDIA MCP77/78" },␊
722//␉{ 0x10DE0858, "NVIDIA MCP77/78" },␊
723//␉{ 0x10DE0859, "NVIDIA MCP77/78" },␊
724//␉{ 0x10DE085A, "NVIDIA MCP77/78" },␊
725//␉{ 0x10DE085B, "NVIDIA MCP77/78" },␊
726//␉{ 0x10DE085C, "NVIDIA MCP77/78" },␊
727//␉{ 0x10DE085D, "NVIDIA MCP77/78" },␊
728//␉{ 0x10DE085E, "NVIDIA MCP77/78" },␊
729//␉{ 0x10DE085F, "NVIDIA MCP77/78" },␊
730␉// 0860 - 086F␊
731␉{ 0x10DE0860, "GeForce 9300" }, //␊
732␉{ 0x10DE0861, "GeForce 9400" },␊
733␉{ 0x10DE0862, "GeForce 9400M G" },␊
734␉{ 0x10DE0863, "GeForce 9400M" },␊
735␉{ 0x10DE0864, "GeForce 9300" },␊
736␉{ 0x10DE0865, "GeForce 9300" }, //␊
737␉{ 0x10DE0866, "GeForce 9400M G" },␊
738␉{ 0x10DE0867, "GeForce 9400" },␊
739␉{ 0x10DE0868, "nForce 760i SLI" },␊
740␉{ 0x10DE0869, "GeForce 9400" },␊
741␉{ 0x10DE086A, "GeForce 9400" },␊
742␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
743␉{ 0x10DE086D, "GeForce 9200" },␊
744␉{ 0x10DE086E, "GeForce 9100M G" },␊
745␉{ 0x10DE086F, "GeForce 8200M G" },␊
746␉// 0870 - 087F␊
747␉{ 0x10DE0870, "GeForce 9400M" },␊
748␉{ 0x10DE0871, "GeForce 9200" },␊
749␉{ 0x10DE0872, "GeForce G102M" },␊
750␉{ 0x10DE0873, "GeForce G102M" },␊
751␉{ 0x10DE0874, "ION 9300M" },␉␊
752␉{ 0x10DE0876, "ION 9400M" }, //␊
753␉{ 0x10DE087A, "GeForce 9400" },␊
754␉{ 0x10DE087D, "ION 9400M" },␊
755␉{ 0x10DE087E, "ION LE" },␊
756␉{ 0x10DE087F, "ION LE" },␊
757␉// 0880 - 088F␊
758␉// 0890 - 089F␊
759␉// 08A0 - 08AF␊
760␉{ 0x10DE08A0, "GeForce 320M" },␊
761//␉{ 0x10DE08A1, "NVIDIA MCP89-MZT" },␊
762//␉{ 0x10DE08A2, "NVIDIA MCP89-EPT" },␊
763␉{ 0x10DE08A3, "GeForce 320M" },␊
764␉{ 0x10DE08A4, "GeForce 320M" },␊
765␉{ 0x10DE08A5, "GeForce 320M" },␊
766␉// 08B0 - 08BF␊
767//␉{ 0x10DE08B0, "Unknown" },␊
768␉{ 0x10DE08B1, "GeForce 300M" },␊
769//␉{ 0x10DE08B2, "NVIDIA MCP83-MJ" },␊
770//␉{ 0x10DE08B3, "NVIDIA MCP89 MM9" },␊
771␉// 08C0 - 08CF␊
772␉// 08D0 - 08DF␊
773␉// 08E0 - 08EF␊
774␉// 08F0 - 08FF␊
775␉// 0900 - 090F␊
776␉// 0910 - 091F␊
777␉// 0920 - 092F␊
778␉// 0930 - 093F␊
779␉// 0940 - 094F␊
780␉// 0950 - 095F␊
781␉// 0960 - 096F␊
782␉// 0970 - 097F␊
783␉// 0980 - 098F␊
784␉// 0990 - 099F␊
785␉// 09A0 - 09AF␊
786␉// 09B0 - 09BF␊
787␉// 09C0 - 09CF␊
788␉// 09D0 - 09DF␊
789␉// 09E0 - 09EF␊
790␉// 09F0 - 09FF␊
791␉// 0A00 - 0A0F␊
792//␉{ 0x10DE0A00, "NVIDIA GT212" },␊
793␉// 0A10 - 0A1F␊
794//␉{ 0x10DE0A10, "NVIDIA GT212" },␊
795␉// 0A20 - 0A2F␊
796␉{ 0x10DE0A20, "GeForce GT 220" }, // subsystem 10de:0a20:1043:8311␊
797//␉{ 0x10DE0A21, "NVIDIA D10M2-20" },␊
798␉{ 0x10DE0A22, "GeForce 315" },␊
799␉{ 0x10DE0A23, "GeForce 210" },␊
800␉{ 0x10DE0A26, "GeForce 405" },␊
801␉{ 0x10DE0A27, "GeForce 405" },␊
802␉{ 0x10DE0A28, "GeForce GT 230M" },␊
803␉{ 0x10DE0A29, "GeForce GT 330M" },␊
804␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
805␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
806␉{ 0x10DE0A2C, "NVS 5100M" },␊
807␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊
808␉// 0A30 - 0A3F␊
809//␉{ 0x10DE0A30, "NVIDIA GT216" },␊
810␉{ 0x10DE0A34, "GeForce GT 240M" },␊
811␉{ 0x10DE0A35, "GeForce GT 325M" },␊
812␉{ 0x10DE0A38, "Quadro 400" },␊
813␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
814//␉{ 0x10DE0A3D, "NVIDIA N10P-ES" },␊
815//␉{ 0x10DE0A3F, "NVIDIA GT216-INT" },␊
816␉// 0A40 - 0A4F␊
817␉// 0A50 - 0A5F␊
818␉// 0A60 - 0A6F␊
819␉{ 0x10DE0A60, "GeForce G210" },␊
820//␉{ 0x10DE0A61, "NVIDIA NVS 2100" },␊
821␉{ 0x10DE0A62, "GeForce 205" },␊
822␉{ 0x10DE0A63, "GeForce 310" },␊
823␉{ 0x10DE0A64, "ION" },␊
824␉{ 0x10DE0A65, "GeForce 210" }, // subsystem 10de:0a65:1043:8334␊
825␉{ 0x10DE0A66, "GeForce 310" },␊
826␉{ 0x10DE0A67, "GeForce 315" },␊
827␉{ 0x10DE0A68, "GeForce G105M" },␊
828␉{ 0x10DE0A69, "GeForce G105M" },␊
829␉{ 0x10DE0A6A, "NVS 2100M" },␊
830␉{ 0x10DE0A6C, "NVS 3100M" }, // subsystem 10de:0a6c:1028:040b & 10de:0a6c:17aa:2142␊
831␉{ 0x10DE0A6E, "GeForce 305M" },␊
832␉{ 0x10DE0A6F, "ION" },␉␊
833␉// 0A70 - 0A7F␊
834␉{ 0x10DE0A70, "GeForce 310M" },␊
835␉{ 0x10DE0A71, "GeForce 305M" },␊
836␉{ 0x10DE0A72, "GeForce 310M" },␊
837␉{ 0x10DE0A73, "GeForce 305M" },␊
838␉{ 0x10DE0A74, "GeForce G210M" },␊
839␉{ 0x10DE0A75, "GeForce G310M" },␊
840␉{ 0x10DE0A76, "ION" },␊
841␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
842//␉{ 0x10DE0A79, "Unknown" },␊
843␉{ 0x10DE0A7A, "GeForce 315M" },␊
844␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
845//␉{ 0x10DE0A7D, "NVIDIA GT218-ES" },␊
846//␉{ 0x10DE0A7E, "NVIDIA GT218-INT-S" },␊
847//␉{ 0x10DE0A7F, "NVIDIA GT218-INT-B" },␊
848␉// 0A80 - 0A8F␊
849␉// 0A90 - 0A9F␊
850␉// 0AA0 - 0AAF␊
851␉// 0AB0 - 0ABF␊
852␉// 0AC0 - 0ACF␊
853␉// 0AD0 - 0ADF␊
854␉// 0AE0 - 0AEF␊
855␉// 0AF0 - 0AFF␊
856␉// 0B00 - 0B0F␊
857␉// 0B10 - 0B1F␊
858␉// 0B20 - 0B2F␊
859␉// 0B30 - 0B3F␊
860␉// 0B40 - 0B4F␊
861␉// 0B50 - 0B5F␊
862␉// 0B60 - 0B6F␊
863␉// 0B70 - 0B7F␊
864␉// 0B80 - 0B8F␊
865␉// 0B90 - 0B9F␊
866␉// 0BA0 - 0BAF␊
867␉// 0BB0 - 0BBF␊
868␉// 0BC0 - 0BCF␊
869␉// 0BD0 - 0BDF␊
870␉// 0BE0 - 0BEF␊
871//␉{ 0x10DE0BE4, "nVidia High Definition Audio Controller" },␊
872␉// 0BF0 - 0BFF␊
873␉// 0C00 - 0C0F␊
874␉// 0C10 - 0C1F␊
875␉// 0C20 - 0C2F␊
876␉// 0C30 - 0C3F␊
877␉// 0C40 - 0C4F␊
878␉// 0C50 - 0C5F␊
879␉// 0C60 - 0C6F␊
880␉// 0C70 - 0C7F␊
881␉// 0C80 - 0C8F␊
882␉// 0C90 - 0C9F␊
883␉// 0CA0 - 0CAF␊
884␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
885␉{ 0x10DE0CA2, "GeForce GT 320" },␊
886␉{ 0x10DE0CA3, "GeForce GT 240" },␊
887␉{ 0x10DE0CA4, "GeForce GT 340" },␊
888␉{ 0x10DE0CA5, "GeForce GT 220" },␊
889␉{ 0x10DE0CA7, "GeForce GT 330" },␊
890␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
891␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
892␉{ 0x10DE0CAC, "GeForce GT 220" },␊
893//␉{ 0x10DE0CAD, "NVIDIA N10E-ES" },␊
894//␉{ 0x10DE0CAE, "NVIDIA GT215-INT" },␊
895␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
896␉// 0CB0 - 0CBF␉␊
897␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
898␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
899␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
900␉// 0CC0 - 0CCF␊
901␉// 0CD0 - 0CDF␊
902␉// 0CE0 - 0CEF␊
903␉// 0CF0 - 0CFF␊
904␉// 0D00 - 0D0F␊
905␉// 0D10 - 0D1F␊
906␉// 0D20 - 0D2F␊
907␉// 0D30 - 0D3F␊
908␉// 0D40 - 0D4F␊
909␉// 0D50 - 0D5F␊
910␉// 0D60 - 0D6F␊
911␉// 0D70 - 0D7F␊
912␉// 0D80 - 0D8F␊
913␉// 0D90 - 0D9F␊
914␉// 0DA0 - 0DAF␊
915␉// 0DB0 - 0DBF␊
916␉// 0DC0 - 0DCF␊
917␉{ 0x10DE0DC0, "GeForce GT 440" },␊
918␉{ 0x10DE0DC1, "D12-P1-35" },␊
919␉{ 0x10DE0DC2, "D12-P1-35" },␊
920␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
921␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
922␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
923␉{ 0x10DE0DCA, "GF10x" },␊
924//␉{ 0x10DE0DCC, "Unknown" },␊
925␉{ 0x10DE0DCD, "GeForce GT 555M" },␊
926␉{ 0x10DE0DCE, "GeForce GT 555M" },␊
927//␉{ 0x10DE0DCF, "Unknown" },␊
928␉// 0DD0 - 0DDF␉␊
929//␉{ 0x10DE0DD0, "Unknown" },␊
930␉{ 0x10DE0DD1, "GeForce GTX 460M" }, // subsystem 10de:0dd1:1558:8687␊
931␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
932␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
933␉{ 0x10DE0DD6, "GeForce GT 550M" },␊
934␉{ 0x10DE0DD8, "Quadro 2000" },␊
935␉{ 0x10DE0DDA, "Quadro 2000M" },␊
936␉{ 0x10DE0DDE, "GF106-ES" },␊
937␉{ 0x10DE0DDF, "GF106-INT" },␊
938␉// 0DE0 - 0DEF␊
939␉{ 0x10DE0DE0, "GeForce GT 440" },␊
940␉{ 0x10DE0DE1, "GeForce GT 430" }, // subsystem 10de:0de1:3842:1430␊
941␉{ 0x10DE0DE2, "GeForce GT 420" },␊
942␉{ 0x10DE0DE4, "GeForce GT 520" },␊
943␉{ 0x10DE0DE5, "GeForce GT 530" },␊
944␉{ 0x10DE0DE8, "GeForce GT 620M" },␊
945␉{ 0x10DE0DE9, "GeForce GT 630M" },␊
946␉{ 0x10DE0DEA, "GeForce GT 610M" },␊
947␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
948␉{ 0x10DE0DEC, "GeForce GT 525M" },␊
949␉{ 0x10DE0DED, "GeForce GT 520M" },␊
950␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
951//␉{ 0x10DE0DEF, "Unknown" },␊
952␉// 0DF0 - 0DFF␉␊
953␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
954␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
955␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
956␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
957␉{ 0x10DE0DF4, "GeForce GT 540M" },␊
958␉{ 0x10DE0DF5, "GeForce GT 525M" },␊
959␉{ 0x10DE0DF6, "GeForce GT 550M" },␊
960␉{ 0x10DE0DF7, "GeForce GT 520M" },␊
961␉{ 0x10DE0DF8, "Quadro 600" },␊
962//␉{ 0x10DE0DF9, "Unknown" },␊
963␉{ 0x10DE0DFA, "Quadro 1000M" },␊
964␉{ 0x10DE0DFC, "NVS 5200M" },␊
965␉{ 0x10DE0DFE, "GF108 ES" },␊
966␉{ 0x10DE0DFF, "GF108 INT" },␊
967␉// 0E00 - 0E0F␊
968␉// 0E10 - 0E1F␊
969␉// 0E20 - 0E2F␊
970␉{ 0x10DE0E21, "D12U-25" },␊
971␉{ 0x10DE0E22, "GeForce GTX 460" }, // subsystem 10de:0e22:1462:2322␊
972␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
973␉{ 0x10DE0E24, "GeForce GTX 460" },␊
974␉{ 0x10DE0E25, "D12U-50" },␊
975␉// 0E30 - 0E3F␊
976␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
977␉{ 0x10DE0E31, "GeForce GTX 485M" },␊
978//␉{ 0x10DE0E32, "Unknown" },␊
979␉{ 0x10DE0E38, "GF104GL" },␊
980␉{ 0x10DE0E3A, "Quadro 3000M" },␊
981␉{ 0x10DE0E3B, "Quadro 4000M" },␊
982␉{ 0x10DE0E3E, "GF104-ES" },␊
983␉{ 0x10DE0E3F, "GF104-INT" },␊
984␉// 0E40 - 0E4F␊
985␉// 0E50 - 0E5F␊
986␉// 0E60 - 0E6F␊
987␉// 0E70 - 0E7F␊
988␉// 0E80 - 0E8F␊
989␉// 0E90 - 0E9F␊
990␉// 0EA0 - 0EAF␊
991␉// 0EB0 - 0EBF␊
992␉// 0EC0 - 0ECF␊
993␉// 0ED0 - 0EDF␊
994␉// 0EE0 - 0EEF␊
995␉// 0EF0 - 0EFF␊
996␉// 0F00 - 0F0F␊
997␉// 0F10 - 0F1F␊
998␉// 0F20 - 0F2F␊
999␉// 0F30 - 0F3F␊
1000␉// 0F40 - 0F4F␊
1001␉// 0F50 - 0F5F␊
1002␉// 0F60 - 0F6F␊
1003␉// 0F70 - 0F7F␊
1004␉// 0F80 - 0F8F␊
1005␉// 0F90 - 0F9F␊
1006␉// 0FA0 - 0FAF␊
1007␉// 0FB0 - 0FBF␊
1008␉// 0FC0 - 0FCF␊
1009␉// 0FD0 - 0FDF␊
1010␉{ 0x10DE0FD1, "GeForce GT 650M" },␊
1011␉{ 0x10DE0FD2, "GeForce GT 640M" },␊
1012␉{ 0x10DE0FD4, "GeForce GTX 660M" },␊
1013␉// 0FE0 - 0FEF␊
1014␉// 0FF0 - 0FFF␊
1015␉// 1000 - 100F␊
1016␉// 1010 - 101F␊
1017␉// 1020 - 102F␊
1018␉// 1030 - 103F␊
1019␉// 1040 - 104F␊
1020␉{ 0x10DE1040, "GeForce GT 520" },␊
1021␉{ 0x10DE1042, "GeForce 510" },␊
1022␉{ 0x10DE1049, "GeForce GT 620" },␊
1023␉// 1050 - 105F␊
1024␉{ 0x10DE1050, "GeForce GT 520M" },␊
1025␉{ 0x10DE1051, "GeForce GT 520MX" },␊
1026//␉{ 0x10DE1052, "Unknown" },␊
1027␉{ 0x10DE1054, "GeForce GT 410M" },␊
1028␉{ 0x10DE1055, "GeForce 410M" },␊
1029␉{ 0x10DE1056, "Quadro NVS 4200M" },␊
1030␉{ 0x10DE1057, "Quadro NVS 4200M" },␊
1031␉{ 0x10DE1058, "GeForce 610M" },␊
1032//␉{ 0x10DE1059, "AUDIO" },␊
1033␉{ 0x10DE105A, "GeForce 610M" },␊
1034␉// 1060 - 106F␊
1035␉// 1070 - 107F␊
1036//␉{ 0x10DE107D, "Unknown" },␊
1037//␉{ 0x10DE107E, "Unknown" },␊
1038␉{ 0x10DE107F, "NVIDIA GF119-ES" },␊
1039␉// 1080 - 108F␊
1040␉{ 0x10DE1080, "GeForce GTX 580" },␊
1041␉{ 0x10DE1081, "GeForce GTX 570" }, // subsystem 10de:1081:10de:087e␊
1042␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
1043␉{ 0x10DE1083, "D13U" },␊
1044␉{ 0x10DE1084, "GeForce GTX 560" },␊
1045␉{ 0x10DE1086, "GeForce GTX 570" },␊
1046␉{ 0x10DE1087, "GeForce GTX 560 Ti-448" },␊
1047␉{ 0x10DE1088, "GeForce GTX 590" },␊
1048␉{ 0x10DE1089, "GeForce GTX 580" },␊
1049␉{ 0x10DE108B, "GeForce GTX 590" },␊
1050␉// 1090 - 109F␊
1051␉{ 0x10DE1091, "Tesla M2090" },␊
1052␉{ 0x10DE1094, "Tesla M2075 Dual-Slot Computing Processor Module" },␊
1053␉{ 0x10DE1096, "Tesla C2075" },␊
1054␉{ 0x10DE1098, "D13U" },␊
1055␉{ 0x10DE109A, "Quadro 5010M" },␊
1056␉{ 0x10DE109B, "Quadro 7000" },␊
1057␉// 10A0 - 10AF␊
1058␉// 10B0 - 10BF␊
1059␉// 10C0 - 10CF␊
1060␉{ 0x10DE10C0, "GeForce 9300 GS" },␊
1061␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
1062//␉{ 0x10DE10C4, "NVIDIA ION" },␊
1063␉{ 0x10DE10C5, "GeForce 405" },␊
1064␉// 10D0 - 10DF␊
1065␉{ 0x10DE10D8, "NVS 300" },␊
1066␉// 10E0 - 10EF␊
1067␉// 10F0 - 10FF␊
1068␉// 1100 - 110F␊
1069␉// 1110 - 111F␊
1070␉// 1120 - 112F␊
1071␉// 1130 - 113F␊
1072␉// 1140 - 114F␊
1073␉// 1150 - 115F␊
1074␉// 1160 - 116F␊
1075␉// 1170 - 117F␊
1076␉// 1180 - 118F␊
1077␉{ 0x10DE1180, "GeForce GTX 680" },␊
1078␉// 1190 - 119F␊
1079␉// 11A0 - 11AF␊
1080␉// 11B0 - 11BF␊
1081␉// 11C0 - 11CF␊
1082␉// 11D0 - 11DF␊
1083␉// 11E0 - 11EF␊
1084␉// 11F0 - 11FF␊
1085␉// 1200 - 120F␊
1086␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
1087␉{ 0x10DE1201, "GeForce GTX 560" },␊
1088␉{ 0x10DE1203, "GeForce GTX 460 SE v2" },␊
1089␉{ 0x10DE1205, "GeForce GTX 460 v2" },␊
1090␉{ 0x10DE1208, "GeForce GTX 560 SE" },␊
1091␉{ 0x10DE1210, "GeForce GTX 570M" },␊
1092␉{ 0x10DE1211, "GeForce GTX 580M" },␊
1093␉{ 0x10DE1212, "GeForce GTX 675M" },␊
1094␉{ 0x10DE1213, "GeForce GTX 670M" },␊
1095␉{ 0x10DE1240, "GeForce GT 620M" },␊
1096␉{ 0x10DE1241, "GeForce GT 545" },␊
1097␉{ 0x10DE1243, "GeForce GT 545" },␊
1098␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
1099␉{ 0x10DE1245, "GeForce GTS 450" },␊
1100␉{ 0x10DE1246, "GeForce GTX 550M" },␊
1101␉{ 0x10DE1247, "GeForce GT 555M" },␊
1102␉{ 0x10DE1248, "GeForce GTX 555M" },␊
1103␉{ 0x10DE124D, "GeForce GTX 555M" },␊
1104//␉{ 0x10DE1250, "Unknown" },␊
1105␉{ 0x10DE1251, "GeForce GTX 560M" },␊
1106␉// 1260 - 126F␊
1107␉// 1270 - 127F␊
1108␉// 1280 - 128F␊
1109␉// 1290 - 129F␊
1110␉// 12A0 - 12AF␊
1111␉// 12B0 - 12BF␊
1112␉// 12C0 - 12CF␊
1113␉// 12D0 - 12DF␊
1114␉// 12E0 - 12EF␊
1115␉// 12F0 - 12FF␊
1116//␉{ 0x10DE8001, "NVIDIA HDMI Audio" },␊
1117//␉{ 0x10DE8067, "NVIDIA HDMI Audio" },␊
1118//␉{ 0x10DE8073, "NVIDIA HDMI Audio" },␊
1119};␊
1120␊
1121static uint16_t swap16(uint16_t x)␊
1122{␊
1123␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
1124}␊
1125␊
1126static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
1127{␊
1128␉uint8_t ret[2];␊
1129␊
1130␉ret[0] = ptr[offset+1];␊
1131␉ret[1] = ptr[offset];␊
1132␊
1133␉return *((uint16_t*)&ret);␊
1134}␊
1135␊
1136#if 0␊
1137static uint32_t swap32(uint32_t x)␊
1138{␊
1139␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
1140}␊
1141␊
1142static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
1143{ ␊
1144␉return ptr[offset];␊
1145}␊
1146␊
1147static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
1148{␊
1149␉uint8_t ret[4];␊
1150␊
1151␉ret[0] = ptr[offset+3];␊
1152␉ret[1] = ptr[offset+2];␊
1153␉ret[2] = ptr[offset+1];␊
1154␉ret[3] = ptr[offset];␊
1155␊
1156␉return *((uint32_t*)&ret);␊
1157}␊
1158#endif␊
1159␊
1160static int patch_nvidia_rom(uint8_t *rom)␊
1161{␊
1162␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
1163␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
1164␉␉return PATCH_ROM_FAILED;␊
1165␉}␊
1166␉␊
1167␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
1168␊
1169␉if (!dcbptr) {␊
1170␉␉printf("no dcb table found\n");␊
1171␉␉return PATCH_ROM_FAILED;␊
1172␉}␊
1173//␉else␊
1174//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
1175␉ ␊
1176␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
1177␉uint8_t dcbtable_version = dcbtable[0];␊
1178␉uint8_t headerlength␉ = 0;␊
1179␉uint8_t numentries␉␉ = 0;␊
1180␉uint8_t recordlength␉ = 0;␊
1181␉␊
1182␉if (dcbtable_version >= 0x20)␊
1183␉{␊
1184␉␉uint32_t sig;␊
1185␉␉␊
1186␉␉if (dcbtable_version >= 0x30)␊
1187␉␉{␊
1188␉␉␉headerlength = dcbtable[1];␊
1189␉␉␉numentries␉ = dcbtable[2];␊
1190␉␉␉recordlength = dcbtable[3];␊
1191␊
1192␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
1193␉␉}␊
1194␉␉else␊
1195␉␉{␊
1196␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
1197␉␉␉headerlength = 8;␊
1198␉␉}␊
1199␉␉␊
1200␉␉if (sig != 0x4edcbdcb)␊
1201␉␉{␊
1202␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
1203␉␉␉return PATCH_ROM_FAILED;␊
1204␉␉}␊
1205␉}␊
1206␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
1207␉{␊
1208␉␉char sig[8] = { 0 };␊
1209␉␉␊
1210␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
1211␉␉recordlength = 10;␊
1212␉␉␊
1213␉␉if (strcmp(sig, "DEV_REC"))␊
1214␉␉{␊
1215␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
1216␉␉␉return PATCH_ROM_FAILED;␊
1217␉␉}␊
1218␉}␊
1219␉else␊
1220␉{␊
1221␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
1222␉␉return PATCH_ROM_FAILED;␊
1223␉}␊
1224␉␊
1225␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
1226␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
1227␉␊
1228␉uint8_t num_outputs = 0, i = 0;␊
1229␉␊
1230␉struct dcbentry␊
1231␉{␊
1232␉␉uint8_t type;␊
1233␉␉uint8_t index;␊
1234␉␉uint8_t *heads;␊
1235␉} entries[numentries];␊
1236␉␊
1237␉for (i = 0; i < numentries; i++)␊
1238␉{␊
1239␉␉uint32_t connection;␊
1240␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
1241␊
1242␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1243␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1244␉␉␉continue;␊
1245␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1246␉␉␉continue;␊
1247␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1248␉␉␉continue;␊
1249␉␉␊
1250␉␉entries[num_outputs].type = connection & 0xf;␊
1251␉␉entries[num_outputs].index = num_outputs;␊
1252␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1253␉}␊
1254␉␊
1255␉int has_lvds = false;␊
1256␉uint8_t channel1 = 0, channel2 = 0;␊
1257␉␊
1258␉for (i = 0; i < num_outputs; i++)␊
1259␉{␊
1260␉␉if (entries[i].type == 3)␊
1261␉␉{␊
1262␉␉␉has_lvds = true;␊
1263␉␉␉//printf("found LVDS\n");␊
1264␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1265␉␉␉entries[i].type = TYPE_GROUPED;␊
1266␉␉}␊
1267␉}␊
1268␉␊
1269␉// if we have a LVDS output, we group the rest to the second channel␊
1270␉if (has_lvds)␊
1271␉{␊
1272␉␉for (i = 0; i < num_outputs; i++)␊
1273␉␉{␊
1274␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1275␉␉␉␉continue;␊
1276␉␉␉␊
1277␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1278␉␉␉entries[i].type = TYPE_GROUPED;␊
1279␉␉}␊
1280␉}␊
1281␉else␊
1282␉{␊
1283␉␉int x;␊
1284␉␉// we loop twice as we need to generate two channels␊
1285␉␉for (x = 0; x <= 1; x++)␊
1286␉␉{␊
1287␉␉␉for (i=0; i<num_outputs; i++)␊
1288␉␉␉{␊
1289␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1290␉␉␉␉␉continue;␊
1291␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1292␉␉␉␉// we always group ANALOG and TMDS␊
1293␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1294␉␉␉␉if (i && entries[i].type == 0x2)␊
1295␉␉␉␉{␊
1296␉␉␉␉␉switch (x)␊
1297␉␉␉␉␉{␊
1298␉␉␉␉␉␉case 0:␊
1299␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1300␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1301␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1302␉␉␉␉␉␉␉␊
1303␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊
1304␉␉␉␉␉␉␉{␊
1305␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1306␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1307␉␉␉␉␉␉␉}␊
1308␉␉␉␉␉␉␉// group TV as well if there is one␊
1309␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1310␉␉␉␉␉␉␉{␊
1311␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1312␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1313␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1314␉␉␉␉␉␉␉}␊
1315␉␉␉␉␉␉␉break;␊
1316␉␉␉␉␉␉␊
1317␉␉␉␉␉␉case 1:␊
1318␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1319␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1320␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1321␉␉␉␉␉␉␉␊
1322␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊
1323␉␉␉␉␉␉␉{␊
1324␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1325␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1326␉␉␉␉␉␉␉}␊
1327␉␉␉␉␉␉␉// group TV as well if there is one␊
1328␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1329␉␉␉␉␉␉␉{␊
1330␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1331␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1332␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1333␉␉␉␉␉␉␉}␊
1334␉␉␉␉␉␉␉break;␊
1335␉␉␉␉␉}␊
1336␉␉␉␉␉break;␊
1337␉␉␉␉}␊
1338␉␉␉}␊
1339␉␉}␊
1340␉}␊
1341␉␊
1342␉// if we have left ungrouped outputs merge them to the empty channel␊
1343␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1344␉togroup = &channel2;␊
1345␉␊
1346␉for (i = 0; i < num_outputs; i++)␊
1347␉{␊
1348␉␉if (entries[i].type != TYPE_GROUPED)␊
1349␉␉{␊
1350␉␉␉//printf("%d not grouped\n", i);␊
1351␉␉␉if (togroup)␊
1352␉␉␉{␊
1353␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1354␉␉␉}␊
1355␉␉␉entries[i].type = TYPE_GROUPED;␊
1356␉␉}␊
1357␉}␊
1358␉␊
1359␉if (channel1 > channel2)␊
1360␉{␊
1361␉␉uint8_t buff = channel1;␊
1362␉␉channel1 = channel2;␊
1363␉␉channel2 = buff;␊
1364␉}␊
1365␉␊
1366␉default_NVCAP[6] = channel1;␊
1367␉default_NVCAP[8] = channel2;␊
1368␉␊
1369␉// patching HEADS␊
1370␉for (i = 0; i < num_outputs; i++)␊
1371␉{␊
1372␉␉if (channel1 & (1 << i))␊
1373␉␉{␊
1374␉␉␉*entries[i].heads = 1;␊
1375␉␉}␊
1376␉␉else if(channel2 & (1 << i))␊
1377␉␉{␊
1378␉␉␉*entries[i].heads = 2;␊
1379␉␉}␊
1380␉}␊
1381␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1382}␊
1383␊
1384static char *get_nvidia_model(uint32_t id)␊
1385{␊
1386␉int i;␊
1387␉␊
1388␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1389␉␉if (NVKnownChipsets[i].device == id)␊
1390␉␉{␊
1391␉␉␉return NVKnownChipsets[i].name;␊
1392␉␉}␊
1393␉}␊
1394␉return NVKnownChipsets[0].name;␊
1395}␊
1396␊
1397static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1398{␊
1399␉int fd;␊
1400␉int size;␊
1401␉␊
1402␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1403␉{␊
1404␉␉return 0;␊
1405␉}␊
1406␉␊
1407␉size = file_size(fd);␊
1408␉␊
1409␉if (size > bufsize)␊
1410␉{␊
1411␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1412␉␉␉␉filename, bufsize);␊
1413␉␉size = bufsize;␊
1414␉}␊
1415␉size = read(fd, (char *)buf, size);␊
1416␉close(fd);␊
1417␉␊
1418␉return size > 0 ? size : 0;␊
1419}␊
1420␊
1421static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1422{␊
1423␉char tmp[16];␊
1424␉␊
1425␉if (!device)␊
1426␉␉return 0;␊
1427␉␊
1428␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1429␉␉return 0;␊
1430␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1431␉␉return 0;␊
1432␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1433␉␉return 0;␊
1434␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1435␉␉return 0;␊
1436␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1437␉␉return 0;␊
1438␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1439␉␉return 0;␊
1440␉if (devices_number == 1)␊
1441␉{␊
1442␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1443␉␉ return 0;␊
1444␉}␊
1445␉else␊
1446␉{␊
1447␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
1448␉␉ return 0;␊
1449␉}␊
1450␉␊
1451␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1452␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1453␉sprintf(tmp, "Slot-%x",devices_number);␊
1454␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1455␉devices_number++;␊
1456␉␊
1457␉return 1;␊
1458}␊
1459␊
1460int hex2bin(const char *hex, uint8_t *bin, int len)␊
1461{␊
1462␉char␉*p;␊
1463␉int␉␉i;␊
1464␉char␉buf[3];␊
1465␉␊
1466␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1467␉␉printf("[ERROR] bin2hex input error\n");␊
1468␉␉return -1;␊
1469␉}␊
1470␉␊
1471␉buf[2] = '\0';␊
1472␉p = (char *) hex;␊
1473␉␊
1474␉for (i = 0; i < len; i++)␊
1475␉{␊
1476␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1477␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1478␉␉␉return -2;␊
1479␉␉}␊
1480␉␉buf[0] = *p++;␊
1481␉␉buf[1] = *p++;␊
1482␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1483␉}␊
1484␉return 0;␊
1485}␊
1486␊
1487unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1488{␊
1489␉unsigned long long vram_size = 0;␊
1490␉␊
1491␉if (nvCardType < NV_ARCH_50)␊
1492␉{␊
1493␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1494␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1495␉}␊
1496␉else if (nvCardType < NV_ARCH_C0)␊
1497␉{␊
1498␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1499␉␉vram_size |= (vram_size & 0xff) << 32;␊
1500␉␉vram_size &= 0xffffffff00ll;␊
1501␉}␊
1502␉else // >= NV_ARCH_C0␊
1503␉{␊
1504␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1505␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1506␉}␊
1507␉␊
1508␉// Workaround for 9600M GT, GT 210/420/430/440/525M & 540M␊
1509␉switch (nvda_dev->device_id)␊
1510␉{␊
1511␉␉case 0x0647: vram_size = 512*1024*1024; break;␉// 9600M GT 0647␊
1512␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT 0649␊
1513␉␉case 0x0A65: vram_size = 1024*1024*1024; break; // GT 210␊
1514␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
1515␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
1516␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
1517␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M 0DEC␊
1518␉␉case 0x0DF4: vram_size = 1024*1024*1024; break; // GT 540M␊
1519␉␉case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M 0DF5␊
1520␉␉default: break;␊
1521␉}␊
1522␉␊
1523␉return vram_size;␊
1524}␊
1525␊
1526bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1527{␊
1528␉struct DevPropDevice␉*device;␊
1529␉char␉␉␉␉␉*devicepath;␊
1530␉option_rom_pci_header_t *rom_pci_header;␊
1531␉volatile uint8_t␉␉*regs;␊
1532␉uint8_t␉␉␉␉␉*rom;␊
1533␉uint8_t␉␉␉␉␉*nvRom;␊
1534␉uint8_t␉␉␉␉␉nvCardType;␊
1535␉unsigned long long␉␉videoRam;␊
1536␉uint32_t␉␉␉␉nvBiosOveride;␊
1537␉uint32_t␉␉␉␉bar[7];␊
1538␉uint32_t␉␉␉␉boot_display;␊
1539␉int␉␉␉␉␉␉nvPatch;␊
1540␉int␉␉␉␉␉␉len;␊
1541␉char␉␉␉␉␉biosVersion[32];␊
1542␉char␉␉␉␉␉nvFilename[32];␊
1543␉char␉␉␉␉␉kNVCAP[12];␊
1544␉char␉␉␉␉␉*model;␊
1545␉const char␉␉␉␉*value;␊
1546␉bool␉␉␉␉␉doit;␊
1547␉␊
1548␉devicepath = get_pci_dev_path(nvda_dev);␊
1549␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1550␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1551␉␊
1552␉// get card type␊
1553␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1554␉␊
1555␉// Amount of VRAM in kilobytes␊
1556␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1557␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1558␉␊
1559␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
1560␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊
1561␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1562␉␉␉devicepath);␊
1563␉␊
1564␉rom = malloc(NVIDIA_ROM_SIZE);␊
1565␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1566␉␉␉(uint16_t)nvda_dev->device_id);␊
1567␉␊
1568␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1569␉{␊
1570␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1571␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1572␉␉␊
1573␉␉if (nvBiosOveride > 0)␊
1574␉␉{␊
1575␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1576␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1577␉␉}␊
1578␉␉else␊
1579␉␉{␊
1580␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1581␉␉␉return false;␊
1582␉␉}␊
1583␉}␊
1584␉else␊
1585␉{␊
1586␉␉// Otherwise read bios from card␊
1587␉␉nvBiosOveride = 0;␊
1588␉␉␊
1589␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1590␉␉␊
1591␉␉// PRAMIN first␊
1592␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1593␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1594␉␉␊
1595␉␉// Valid Signature ?␊
1596␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1597␉␉{␊
1598␉␉␉// PROM next␊
1599␉␉␉// Enable PROM access␊
1600␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1601␉␉␉␊
1602␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1603␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1604␉␉␉␊
1605␉␉␉// disable PROM access␊
1606␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1607␉␉␉␊
1608␉␉␉// Valid Signature ?␊
1609␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1610␉␉␉{␊
1611␉␉␉␉// 0xC0000 last␊
1612␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1613␉␉␉␉␊
1614␉␉␉␉// Valid Signature ?␊
1615␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1616␉␉␉␉{␊
1617␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1618␉␉␉␉␉return false;␊
1619␉␉␉␉}␊
1620␉␉␉␉else␊
1621␉␉␉␉{␊
1622␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1623␉␉␉␉}␊
1624␉␉␉}␊
1625␉␉␉else␊
1626␉␉␉{␊
1627␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1628␉␉␉}␊
1629␉␉}␊
1630␉␉else␊
1631␉␉{␊
1632␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1633␉␉}␊
1634␉}␊
1635␉␊
1636␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1637␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1638␉␉//return false;␊
1639␉}␊
1640␉␊
1641␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1642␉␊
1643␉// check for 'PCIR' sig␊
1644␉if (rom_pci_header->signature == 0x50434952)␊
1645␉{␊
1646␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1647␉␉{␊
1648␉␉␉// Get Model from the OpROM␊
1649␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1650␉␉}␊
1651␉␉else␊
1652␉␉{␊
1653␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1654␉␉}␊
1655␉}␊
1656␉␊
1657␉if (!string) {␊
1658␉␉string = devprop_create_string();␊
1659␉}␊
1660␉device = devprop_add_device(string, devicepath);␊
1661␉␊
1662␉/* FIXME: for primary graphics card only */␊
1663␉boot_display = 1;␊
1664␉if (devices_number == 1)␊
1665␉{␊
1666␉ devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1667␉}␊
1668␉␊
1669␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1670␉␉uint8_t built_in = 0x01;␊
1671␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1672␉}␊
1673␊
1674␉// get bios version␊
1675␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1676␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1677␉␊
1678␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1679␉␊
1680␉int i, version_start;␊
1681␉int crlf_count = 0;␊
1682␉␊
1683␉// only search the first 384 bytes␊
1684␉for (i = 0; i < 0x180; i++)␊
1685␉{␊
1686␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1687␉␉{␊
1688␉␉␉crlf_count++;␊
1689␉␉␉// second 0x0D0A was found, extract bios version␊
1690␉␉␉if (crlf_count == 2)␊
1691␉␉␉{␊
1692␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1693␉␉␉␉␊
1694␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1695␉␉␉␉{␊
1696␉␉␉␉␉// find start␊
1697␉␉␉␉␉if (rom[version_start] == 0x00)␊
1698␉␉␉␉␉{␊
1699␉␉␉␉␉␉version_start++;␊
1700␉␉␉␉␉␉␊
1701␉␉␉␉␉␉// strip "Version "␊
1702␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1703␉␉␉␉␉␉{␊
1704␉␉␉␉␉␉␉version_start += 8;␊
1705␉␉␉␉␉␉}␊
1706␉␉␉␉␉␉␊
1707␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1708␉␉␉␉␉␉break;␊
1709␉␉␉␉␉}␊
1710␉␉␉␉}␊
1711␉␉␉␉break;␊
1712␉␉␉}␊
1713␉␉}␊
1714␉}␊
1715␉␊
1716␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1717␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1718␉␊
1719␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1720␉{␊
1721␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1722␉␉␊
1723␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1724␉␉{␊
1725␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1726␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1727␉␉}␊
1728␉}␊
1729␉␊
1730␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1731␉{␊
1732␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1733␉␉␊
1734␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1735␉␉{␊
1736␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1737␉␉␉␊
1738␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1739␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1740␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1741␉␉}␊
1742␉}␊
1743␉␊
1744␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1745␉{␊
1746␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1747␉␉␊
1748␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1749␉␉{␊
1750␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1751␉␉␉␊
1752␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1753␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1754␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1755␉␉}␊
1756␉}␊
1757␉␊
1758#if DEBUG_NVCAP␊
1759␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1760␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1761␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1762␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1763␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1764␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1765#endif␊
1766␉␊
1767␉devprop_add_nvidia_template(device);␊
1768␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1769␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1770␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1771␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1772 //␉devprop_add_value(device, "@1,connector-type", connector_type_1, 4); // fixme␊
1773 //␉devprop_add_value(device, "@0,display-cfg", display_cfg_0, 4);␊
1774 //␉devprop_add_value(device, "@1,display-cfg", display_cfg_1, 4);␊
1775␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊
1776␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1777␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1778␉␊
1779␉//add HDMI Audio back to nvidia␊
1780␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1781//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1782//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1783␉//end Nvidia HDMI Audio␊
1784␉␊
1785␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1786␉{␊
1787␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1788␉}␊
1789␉␊
1790␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1791␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1792␉stringlength = string->length;␊
1793␉␊
1794␉return true;␊
1795}␊
1796

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