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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#ifndef __LIBSAIO_CPU_H␊
7#define __LIBSAIO_CPU_H␊
8␊
9//#include "libsaio.h"␊
10␊
11extern void scan_cpu(PlatformInfo_t *);␊
12␊
13#define bit(n)␉␉␉(1ULL << (n))␊
14#define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊
15#define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊
16␊
17#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊
18␊
19#define␉MSR_IA32_PERF_STATUS␉0x00000198␊
20#define MSR_IA32_PERF_CONTROL␉0x199␊
21#define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
22#define MSR_FLEX_RATIO␉␉␉0x194␊
23#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
24#define␉MSR_PLATFORM_INFO␉␉0xCE␊
25#define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊
26#define MSR_IA32_PLATFORM_ID␉0x17␊
27␊
28#define K8_FIDVID_STATUS␉␉0xC0010042␊
29#define K10_COFVID_STATUS␉␉0xC0010071␊
30␊
31#define MSR_AMD_MPERF 0x000000E7␊
32#define MSR_AMD_APERF 0x000000E8␊
33␊
34#define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊
35␊
36// DFE: This constant comes from older xnu:␊
37#define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊
38␊
39// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊
40#define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
41#define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
42␊
43// CPUID Values␊
44#define CPUID_MODEL_YONAH␉␉14␉// Intel Mobile Core Solo, Duo␊
45#define CPUID_MODEL_MEROM␉␉15␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
46#define CPUID_MODEL_PENRYN␉␉23␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
47#define CPUID_MODEL_NEHALEM␉␉26␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
48#define CPUID_MODEL_ATOM␉␉28␉// Intel Atom (45nm)␊
49#define CPUID_MODEL_FIELDS␉␉30␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
50#define CPUID_MODEL_DALES␉␉31␉// Havendale, Auburndale␊
51#define CPUID_MODEL_DALES_32NM␉␉37␉// Intel Core i3, i5 LGA1156 (32nm)␊
52#define CPUID_MODEL_SANDYBRIDGE␉␉42␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
53#define CPUID_MODEL_WESTMERE␉␉44␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
54#define CPUID_MODEL_JAKETOWN␉␉45␉// Intel Xeon E5 LGA2011 (22nm)␊
55#define CPUID_MODEL_NEHALEM_EX␉␉46␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
56#define CPUID_MODEL_WESTMERE_EX␉␉47␉// Intel Xeon E7␊
57#define CPUID_MODEL_IVYBRIDGE␉␉58␉// Intel Core i5, i7 LGA1155 (22nm)␊
58␊
59␊
60static inline uint64_t rdtsc64(void)␊
61{␊
62␉uint64_t ret;␊
63␉__asm__ volatile("rdtsc" : "=A" (ret));␊
64␉return ret;␊
65}␊
66␊
67static inline uint64_t rdmsr64(uint32_t msr)␊
68{␊
69 uint64_t ret;␊
70 __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊
71 return ret;␊
72}␊
73␊
74static inline void wrmsr64(uint32_t msr, uint64_t val)␊
75{␊
76␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊
77}␊
78␊
79static inline void intel_waitforsts(void) {␊
80␉uint32_t inline_timeout = 100000;␊
81␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊
82}␊
83␊
84static inline void do_cpuid(uint32_t selector, uint32_t *data)␊
85{␊
86␉asm volatile ("cpuid"␊
87␉␉␉␉ : "=a" (data[0]),␊
88␉␉␉␉ "=b" (data[1]),␊
89␉␉␉␉ "=c" (data[2]),␊
90␉␉␉␉ "=d" (data[3])␊
91␉␉␉␉ : "a" (selector));␊
92}␊
93␊
94static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊
95{␊
96␉asm volatile ("cpuid"␊
97␉␉␉␉ : "=a" (data[0]),␊
98␉␉␉␉ "=b" (data[1]),␊
99␉␉␉␉ "=c" (data[2]),␊
100␉␉␉␉ "=d" (data[3])␊
101␉␉␉␉ : "a" (selector), "c" (selector2));␊
102}␊
103␊
104// DFE: enable_PIT2 and disable_PIT2 come from older xnu␊
105␊
106/*␊
107 * Enable or disable timer 2.␊
108 * Port 0x61 controls timer 2:␊
109 * bit 0 gates the clock,␊
110 * bit 1 gates output to speaker.␊
111 */␊
112inline static void␊
113enable_PIT2(void)␊
114{␊
115 /* Enable gate, disable speaker */␊
116 __asm__ volatile(␊
117␉␉␉␉␉ " inb $0x61,%%al \n\t"␊
118␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊
119␉␉␉␉␉ " or $1,%%al \n\t"␊
120␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊
121␉␉␉␉␉ : : : "%al" );␊
122}␊
123␊
124inline static void␊
125disable_PIT2(void)␊
126{␊
127 /* Disable gate and output to speaker */␊
128 __asm__ volatile(␊
129␉␉␉␉␉ " inb $0x61,%%al \n\t"␊
130␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊
131␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊
132␉␉␉␉␉ : : : "%al" );␊
133}␊
134␊
135// DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊
136// roughly based on Linux code␊
137␊
138/* Set the 8254 channel 2 to mode 0 with the specified value.␊
139 In mode 0, the counter will initially set its gate low when the␊
140 timer expires. For this to be useful, you ought to set it high␊
141 before calling this function. The enable_PIT2 function does this.␊
142 */␊
143static inline void set_PIT2_mode0(uint16_t value)␊
144{␊
145 __asm__ volatile(␊
146␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊
147␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊
148␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊
149␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊
150␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊
151␉␉␉␉␉ " outb␉%%al,$0x42"␊
152␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊
153}␊
154␊
155/* Returns the number of times the loop ran before the PIT2 signaled */␊
156static inline unsigned long poll_PIT2_gate(void)␊
157{␊
158 unsigned long count = 0;␊
159 unsigned char nmi_sc_val;␊
160 do {␊
161 ++count;␊
162 __asm__ volatile(␊
163␉␉␉␉␉␉ "inb␉$0x61,%0"␊
164␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊
165 } while( (nmi_sc_val & 0x20) == 0);␊
166 return count;␊
167}␊
168␊
169inline static void␊
170set_PIT2(int value)␊
171{␊
172/*␊
173 * First, tell the clock we are going to write 16 bits to the counter␊
174 * and enable one-shot mode (command 0xB8 to port 0x43)␊
175 * Then write the two bytes into the PIT2 clock register (port 0x42).␊
176 * Loop until the value is "realized" in the clock,␊
177 * this happens on the next tick.␊
178 */␊
179 asm volatile(␊
180 " movb $0xB8,%%al \n\t"␊
181 " outb %%al,$0x43 \n\t"␊
182 " movb %%dl,%%al \n\t"␊
183 " outb %%al,$0x42 \n\t"␊
184 " movb %%dh,%%al \n\t"␊
185 " outb %%al,$0x42 \n"␊
186"1: inb $0x42,%%al \n\t" ␊
187 " inb $0x42,%%al \n\t"␊
188 " cmp %%al,%%dh \n\t"␊
189 " jne 1b"␊
190 : : "d"(value) : "%al");␊
191}␊
192␊
193␊
194inline static uint64_t␊
195get_PIT2(unsigned int *value)␊
196{␊
197 register uint64_t result;␊
198/*␊
199 * This routine first latches the time (command 0x80 to port 0x43),␊
200 * then gets the time stamp so we know how long the read will take later.␊
201 * Read (from port 0x42) and return the current value of the timer.␊
202 */␊
203#ifdef __i386__␊
204 asm volatile(␊
205 " xorl %%ecx,%%ecx \n\t"␊
206 " movb $0x80,%%al \n\t"␊
207 " outb %%al,$0x43 \n\t"␊
208 " rdtsc \n\t"␊
209 " pushl %%eax \n\t"␊
210 " inb $0x42,%%al \n\t"␊
211 " movb %%al,%%cl \n\t"␊
212 " inb $0x42,%%al \n\t"␊
213 " movb %%al,%%ch \n\t"␊
214 " popl %%eax "␊
215 : "=A"(result), "=c"(*value));␊
216#else /* __x86_64__ */␊
217 asm volatile(␊
218␉␉" xorq %%rcx,%%rcx \n\t"␊
219␉␉" movb $0x80,%%al \n\t"␊
220␉␉" outb %%al,$0x43 \n\t"␊
221␉␉" rdtsc \n\t"␊
222␉␉" pushq %%rax \n\t"␊
223␉␉" inb $0x42,%%al \n\t"␊
224␉␉" movb %%al,%%cl \n\t"␊
225␉␉" inb $0x42,%%al \n\t"␊
226␉␉" movb %%al,%%ch \n\t"␊
227␉␉" popq %%rax "␊
228␉␉: "=A"(result), "=c"(*value));␊
229#endif␊
230␊
231 return result;␊
232}␊
233␊
234␊
235␊
236#endif /* !__LIBSAIO_CPU_H */␊
237

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