1 | /*␊ |
2 | *␉NVidia injector␊ |
3 | *␊ |
4 | *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊ |
5 | *␊ |
6 | *␉NVidia injector is free software: you can redistribute it and/or modify␊ |
7 | *␉it under the terms of the GNU General Public License as published by␊ |
8 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
9 | *␉(at your option) any later version.␊ |
10 | *␊ |
11 | *␉NVidia driver and injector is distributed in the hope that it will be useful,␊ |
12 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
13 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
14 | *␉GNU General Public License for more details.␊ |
15 | *␊ |
16 | *␉You should have received a copy of the GNU General Public License␊ |
17 | *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊ |
18 | */ ␊ |
19 | /*␊ |
20 | * Alternatively you can choose to comply with APSL␊ |
21 | */␊ |
22 | ␊ |
23 | ␊ |
24 | /*␊ |
25 | * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊ |
26 | *␊ |
27 | *␊ |
28 | * Copyright 2005-2006 Erik Waling␊ |
29 | * Copyright 2006 Stephane Marchesin␊ |
30 | * Copyright 2007-2009 Stuart Bennett␊ |
31 | *␊ |
32 | * Permission is hereby granted, free of charge, to any person obtaining a␊ |
33 | * copy of this software and associated documentation files (the "Software"),␊ |
34 | * to deal in the Software without restriction, including without limitation␊ |
35 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
36 | * and/or sell copies of the Software, and to permit persons to whom the␊ |
37 | * Software is furnished to do so, subject to the following conditions:␊ |
38 | *␊ |
39 | * The above copyright notice and this permission notice shall be included in␊ |
40 | * all copies or substantial portions of the Software.␊ |
41 | *␊ |
42 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊ |
43 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊ |
44 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊ |
45 | * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊ |
46 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊ |
47 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊ |
48 | * SOFTWARE.␊ |
49 | */␊ |
50 | ␊ |
51 | #include "boot.h"␊ |
52 | #include "bootstruct.h"␊ |
53 | #include "pci.h"␊ |
54 | #include "platform.h"␊ |
55 | #include "device_inject.h"␊ |
56 | #include "nvidia.h"␊ |
57 | ␊ |
58 | #ifndef DEBUG_NVIDIA␊ |
59 | #define DEBUG_NVIDIA 0␊ |
60 | #endif␊ |
61 | ␊ |
62 | #if DEBUG_NVIDIA␊ |
63 | #define DBG(x...)␉printf(x)␊ |
64 | #else␊ |
65 | #define DBG(x...)␊ |
66 | #endif␊ |
67 | ␊ |
68 | #define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊ |
69 | #define PATCH_ROM_SUCCESS␉␉␉1␊ |
70 | #define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊ |
71 | #define PATCH_ROM_FAILED␉␉␉0␊ |
72 | #define MAX_NUM_DCB_ENTRIES␉␉␉16␊ |
73 | #define TYPE_GROUPED␉␉␉␉0xff␊ |
74 | ␊ |
75 | extern uint32_t devices_number;␊ |
76 | ␊ |
77 | const char *nvidia_compatible_0[] =␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊ |
78 | const char *nvidia_compatible_1[] =␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊ |
79 | const char *nvidia_device_type_0[] =␉{ "@0,device_type", "display"␉␉ };␊ |
80 | const char *nvidia_device_type_1[] =␉{ "@1,device_type", "display"␉␉ };␊ |
81 | const char *nvidia_device_type[] =␉{ "device_type",␉"NVDA,Parent"␉ };␊ |
82 | const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊ |
83 | const char *nvidia_name_0[] =␉{ "@0,name",␉␉"NVDA,Display-A" };␊ |
84 | const char *nvidia_name_1[] =␉{ "@1,name",␉␉"NVDA,Display-B" };␊ |
85 | const char *nvidia_slot_name[] =␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊ |
86 | ␊ |
87 | static uint8_t default_NVCAP[]= {␊ |
88 | ␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊ |
89 | ␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊ |
90 | ␉0x00, 0x00, 0x00, 0x00␊ |
91 | };␊ |
92 | ␊ |
93 | #define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊ |
94 | ␊ |
95 | static uint8_t default_dcfg_0[]␉␉=␉{0x03, 0x01, 0x03, 0x00};␊ |
96 | static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0x00, 0x01};␊ |
97 | ␊ |
98 | // uint8_t connector_type_1[]␉␉=␉{0x00, 0x08, 0x00, 0x00};␊ |
99 | ␊ |
100 | #define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊ |
101 | #define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊ |
102 | ␊ |
103 | static uint8_t default_NVPM[]= {␊ |
104 | 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
105 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
106 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
107 | 0x00, 0x00, 0x00, 0x00␊ |
108 | };␊ |
109 | ␊ |
110 | #define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊ |
111 | ␊ |
112 | static struct nv_chipsets_t NVKnownChipsets[] = {␊ |
113 | ␉{ 0x00000000,␉"Unknown" },␊ |
114 | //========================================␊ |
115 | ␉// 0000 - 0040␉␊ |
116 | ␉// 0040 - 004F␉␊ |
117 | ␉{ 0x10DE0040,␉"GeForce 6800 Ultra" },␊ |
118 | ␉{ 0x10DE0041,␉"GeForce 6800" },␊ |
119 | ␉{ 0x10DE0042,␉"GeForce 6800 LE" },␊ |
120 | ␉{ 0x10DE0043,␉"GeForce 6800 XE" },␊ |
121 | ␉{ 0x10DE0044,␉"GeForce 6800 XT" },␊ |
122 | ␉{ 0x10DE0045,␉"GeForce 6800 GT" },␊ |
123 | ␉{ 0x10DE0046,␉"GeForce 6800 GT" },␊ |
124 | ␉{ 0x10DE0047,␉"GeForce 6800 GS" },␊ |
125 | ␉{ 0x10DE0048,␉"GeForce 6800 XT" },␊ |
126 | ␉{ 0x10DE004D,␉"Quadro FX 3400" },␊ |
127 | ␉{ 0x10DE004E,␉"Quadro FX 4000" },␊ |
128 | ␉// 0050 - 005F␊ |
129 | ␉// 0060 - 006F␊ |
130 | ␉// 0070 - 007F␊ |
131 | ␉// 0080 - 008F␊ |
132 | ␉// 0090 - 009F␊ |
133 | ␉{ 0x10DE0090,␉"GeForce 7800 GTX" },␊ |
134 | ␉{ 0x10DE0091,␉"GeForce 7800 GTX" },␊ |
135 | ␉{ 0x10DE0092,␉"GeForce 7800 GT" },␊ |
136 | ␉{ 0x10DE0093,␉"GeForce 7800 GS" },␊ |
137 | ␉{ 0x10DE0095,␉"GeForce 7800 SLI" },␊ |
138 | ␉{ 0x10DE0098,␉"GeForce Go 7800" },␊ |
139 | ␉{ 0x10DE0099,␉"GeForce Go 7800 GTX" },␊ |
140 | ␉{ 0x10DE009D,␉"Quadro FX 4500" },␊ |
141 | ␉// 00A0 - 00AF␉␊ |
142 | ␉// 00B0 - 00BF␉␊ |
143 | ␉// 00C0 - 00CF␉␊ |
144 | ␉{ 0x10DE00C0,␉"GeForce 6800 GS" },␊ |
145 | ␉{ 0x10DE00C1,␉"GeForce 6800" },␊ |
146 | ␉{ 0x10DE00C2,␉"GeForce 6800 LE" },␊ |
147 | ␉{ 0x10DE00C3,␉"GeForce 6800 XT" },␊ |
148 | ␉{ 0x10DE00C8,␉"GeForce Go 6800" },␊ |
149 | ␉{ 0x10DE00C9,␉"GeForce Go 6800 Ultra" },␊ |
150 | ␉{ 0x10DE00CC,␉"Quadro FX Go1400" },␊ |
151 | ␉{ 0x10DE00CD,␉"Quadro FX 3450/4000 SDI" },␊ |
152 | ␉{ 0x10DE00CE,␉"Quadro FX 1400" },␊ |
153 | ␉// 00D0 - 00DF␉␊ |
154 | ␉// 00E0 - 00EF␉␊ |
155 | ␉// 00F0 - 00FF␉␊ |
156 | ␉{ 0x10DE00F1,␉"GeForce 6600 GT" },␊ |
157 | ␉{ 0x10DE00F2,␉"GeForce 6600" },␊ |
158 | ␉{ 0x10DE00F3,␉"GeForce 6200" },␊ |
159 | ␉{ 0x10DE00F4,␉"GeForce 6600 LE" },␊ |
160 | ␉{ 0x10DE00F5,␉"GeForce 7800 GS" },␊ |
161 | ␉{ 0x10DE00F6,␉"GeForce 6800 GS/XT" },␊ |
162 | ␉{ 0x10DE00F8,␉"Quadro FX 3400/4400" },␊ |
163 | ␉{ 0x10DE00F9,␉"GeForce 6800 Series GPU" },␊ |
164 | ␉// 0100 - 010F␉␊ |
165 | ␉// 0110 - 011F␉␊ |
166 | ␉// 0120 - 012F␉␊ |
167 | ␉// 0130 - 013F␉␊ |
168 | ␉// 0140 - 014F␉␊ |
169 | ␉{ 0x10DE0140,␉"GeForce 6600 GT" },␊ |
170 | ␉{ 0x10DE0141,␉"GeForce 6600" },␊ |
171 | ␉{ 0x10DE0142,␉"GeForce 6600 LE" },␊ |
172 | ␉{ 0x10DE0143,␉"GeForce 6600 VE" },␊ |
173 | ␉{ 0x10DE0144,␉"GeForce Go 6600" },␊ |
174 | ␉{ 0x10DE0145,␉"GeForce 6610 XL" },␊ |
175 | ␉{ 0x10DE0146,␉"GeForce Go 6600 TE/6200 TE" },␊ |
176 | ␉{ 0x10DE0147,␉"GeForce 6700 XL" },␊ |
177 | ␉{ 0x10DE0148,␉"GeForce Go 6600" },␊ |
178 | ␉{ 0x10DE0149,␉"GeForce Go 6600 GT" },␊ |
179 | ␉{ 0x10DE014A,␉"Quadro NVS 440" },␊ |
180 | ␉{ 0x10DE014C,␉"Quadro FX 550" },␊ |
181 | ␉{ 0x10DE014D,␉"Quadro FX 550" },␊ |
182 | ␉{ 0x10DE014E,␉"Quadro FX 540" },␊ |
183 | ␉{ 0x10DE014F,␉"GeForce 6200" },␊ |
184 | ␉// 0150 - 015F␉␊ |
185 | ␉// 0160 - 016F␉␊ |
186 | ␉{ 0x10DE0160,␉"GeForce 6500" },␊ |
187 | ␉{ 0x10DE0161,␉"GeForce 6200 TurboCache(TM)" },␊ |
188 | ␉{ 0x10DE0162,␉"GeForce 6200SE TurboCache(TM)" },␊ |
189 | ␉{ 0x10DE0163,␉"GeForce 6200 LE" },␊ |
190 | ␉{ 0x10DE0164,␉"GeForce Go 6200" },␊ |
191 | ␉{ 0x10DE0165,␉"Quadro NVS 285" },␊ |
192 | ␉{ 0x10DE0166,␉"GeForce Go 6400" },␊ |
193 | ␉{ 0x10DE0167,␉"GeForce Go 6200" },␊ |
194 | ␉{ 0x10DE0168,␉"GeForce Go 6400" },␊ |
195 | ␉{ 0x10DE0169,␉"GeForce 6250" },␊ |
196 | ␉{ 0x10DE016A,␉"GeForce 7100 GS" },␊ |
197 | ␉{ 0x10DE016C,␉"NVIDIA NV44GLM" },␊ |
198 | ␉{ 0x10DE016D,␉"NVIDIA NV44GLM" },␊ |
199 | ␉// 0170 - 017F␉␊ |
200 | ␉// 0180 - 018F␉␊ |
201 | ␉// 0190 - 019F␉␉␊ |
202 | ␉{ 0x10DE0191,␉"GeForce 8800 GTX" },␊ |
203 | ␉{ 0x10DE0193,␉"GeForce 8800 GTS" },␊ |
204 | ␉{ 0x10DE0194,␉"GeForce 8800 Ultra" },␊ |
205 | ␉{ 0x10DE0197,␉"Tesla C870" },␊ |
206 | ␉{ 0x10DE019D,␉"Quadro FX 5600" },␊ |
207 | ␉{ 0x10DE019E,␉"Quadro FX 4600" },␊ |
208 | ␉// 01A0 - 01AF␊ |
209 | ␉// 01B0 - 01BF␊ |
210 | ␉// 01C0 - 01CF␊ |
211 | ␉// 01D0 - 01DF␊ |
212 | ␉{ 0x10DE01D0,␉"GeForce 7350 LE" },␊ |
213 | ␉{ 0x10DE01D1,␉"GeForce 7300 LE" },␊ |
214 | ␉{ 0x10DE01D2,␉"GeForce 7550 LE" },␊ |
215 | ␉{ 0x10DE01D3,␉"GeForce 7300 SE/7200 GS" },␊ |
216 | ␉{ 0x10DE01D6,␉"GeForce Go 7200" },␊ |
217 | ␉{ 0x10DE01D7,␉"GeForce Go 7300" },␊ |
218 | ␉{ 0x10DE01D8,␉"GeForce Go 7400" },␊ |
219 | ␉{ 0x10DE01D9,␉"GeForce Go 7400 GS" },␊ |
220 | ␉{ 0x10DE01DA,␉"Quadro NVS 110M" },␊ |
221 | ␉{ 0x10DE01DB,␉"Quadro NVS 120M" },␊ |
222 | ␉{ 0x10DE01DC,␉"Quadro FX 350M" },␊ |
223 | ␉{ 0x10DE01DD,␉"GeForce 7500 LE" },␊ |
224 | ␉{ 0x10DE01DE,␉"Quadro FX 350" },␊ |
225 | ␉{ 0x10DE01DF,␉"GeForce 7300 GS" },␊ |
226 | ␉// 01E0 - 01EF␉␊ |
227 | ␉// 01F0 - 01FF␊ |
228 | ␉{ 0x10DE01F0,␉"GeForce4 MX" },␊ |
229 | ␉// 0200 - 020F␉␊ |
230 | ␉// 0210 - 021F␉␊ |
231 | ␉{ 0x10DE0211,␉"GeForce 6800" },␊ |
232 | ␉{ 0x10DE0212,␉"GeForce 6800 LE" },␊ |
233 | ␉{ 0x10DE0215,␉"GeForce 6800 GT" },␊ |
234 | ␉{ 0x10DE0218,␉"GeForce 6800 XT" },␊ |
235 | ␉// 0220 - 022F␊ |
236 | ␉{ 0x10DE0221,␉"GeForce 6200" },␊ |
237 | ␉{ 0x10DE0222,␉"GeForce 6200 A-LE" },␊ |
238 | ␉{ 0x10DE0228,␉"NVIDIA NV44M" },␊ |
239 | ␉// 0230 - 023F␊ |
240 | ␉// 0240 - 024F␊ |
241 | ␉{ 0x10DE0240,␉"GeForce 6150" },␊ |
242 | ␉{ 0x10DE0241,␉"GeForce 6150 LE" },␊ |
243 | ␉{ 0x10DE0242,␉"GeForce 6100" },␊ |
244 | ␉{ 0x10DE0243,␉"NVIDIA C51" },␊ |
245 | ␉{ 0x10DE0244,␉"GeForce Go 6150" },␊ |
246 | ␉{ 0x10DE0245,␉"Quadro NVS 210S / GeForce 6150LE" },␊ |
247 | ␉{ 0x10DE0247,␉"GeForce Go 6100" },␊ |
248 | ␉// 0250 - 025F␊ |
249 | ␉{ 0x10DE025B,␉"Quadro4 700 XGL" },␊ |
250 | ␉// 0260 - 026F␊ |
251 | ␉// 0270 - 027F␊ |
252 | ␉// 0280 - 028F␊ |
253 | ␉// 0290 - 029F␊ |
254 | ␉{ 0x10DE0290,␉"GeForce 7900 GTX" },␊ |
255 | ␉{ 0x10DE0291,␉"GeForce 7900 GT/GTO" },␊ |
256 | ␉{ 0x10DE0292,␉"GeForce 7900 GS" },␊ |
257 | ␉{ 0x10DE0293,␉"GeForce 7950 GX2" },␊ |
258 | ␉{ 0x10DE0294,␉"GeForce 7950 GX2" },␊ |
259 | ␉{ 0x10DE0295,␉"GeForce 7950 GT" },␊ |
260 | ␉{ 0x10DE0298,␉"GeForce Go 7900 GS" },␊ |
261 | ␉{ 0x10DE0299,␉"GeForce Go 7900 GTX" },␊ |
262 | ␉{ 0x10DE029A,␉"Quadro FX 2500M" },␊ |
263 | ␉{ 0x10DE029B,␉"Quadro FX 1500M" },␊ |
264 | ␉{ 0x10DE029C,␉"Quadro FX 5500" },␊ |
265 | ␉{ 0x10DE029D,␉"Quadro FX 3500" },␊ |
266 | ␉{ 0x10DE029E,␉"Quadro FX 1500" },␊ |
267 | ␉{ 0x10DE029F,␉"Quadro FX 4500 X2" },␊ |
268 | ␉// 02A0 - 02AF␊ |
269 | ␉// 02B0 - 02BF␊ |
270 | ␉// 02C0 - 02CF␊ |
271 | ␉// 02D0 - 02DF␊ |
272 | ␉// 02E0 - 02EF␊ |
273 | ␉{ 0x10DE02E0,␉"GeForce 7600 GT" },␊ |
274 | ␉{ 0x10DE02E1,␉"GeForce 7600 GS" },␊ |
275 | ␉{ 0x10DE02E2,␉"GeForce 7300 GT" },␊ |
276 | ␉{ 0x10DE02E3,␉"GeForce 7900 GS" },␊ |
277 | ␉{ 0x10DE02E4,␉"GeForce 7950 GT" },␊ |
278 | ␉// 02F0 - 02FF␊ |
279 | ␉// 0300 - 030F␊ |
280 | ␉{ 0x10DE0301,␉"GeForce FX 5800 Ultra" },␊ |
281 | ␉{ 0x10DE0302,␉"GeForce FX 5800" },␊ |
282 | ␉{ 0x10DE0308,␉"Quadro FX 2000" },␊ |
283 | ␉{ 0x10DE0309,␉"Quadro FX 1000" },␊ |
284 | ␉// 0310 - 031F␊ |
285 | ␉{ 0x10DE0311,␉"GeForce FX 5600 Ultra" },␊ |
286 | ␉{ 0x10DE0312,␉"GeForce FX 5600" },␊ |
287 | ␉{ 0x10DE0314,␉"GeForce FX 5600XT" },␊ |
288 | ␉{ 0x10DE031A,␉"GeForce FX Go5600" },␊ |
289 | ␉{ 0x10DE031B,␉"GeForce FX Go5650" },␊ |
290 | ␉{ 0x10DE031C,␉"Quadro FX Go700" },␊ |
291 | ␉// 0320 - 032F␊ |
292 | ␉{ 0x10DE0320,␉"GeForce FX 5200" },␊ |
293 | ␉{ 0x10DE0321,␉"GeForce FX 5200 Ultra" },␊ |
294 | ␉{ 0x10DE0322,␉"GeForce FX 5200" },␊ |
295 | ␉{ 0x10DE0323,␉"GeForce FX 5200 LE" },␊ |
296 | ␉{ 0x10DE0324,␉"GeForce FX Go5200" },␊ |
297 | ␉{ 0x10DE0325,␉"GeForce FX Go5250" },␊ |
298 | ␉{ 0x10DE0326,␉"GeForce FX 5500" },␊ |
299 | ␉{ 0x10DE0328,␉"GeForce FX Go5200 32M/64M" },␊ |
300 | ␉{ 0x10DE0329,␉"GeForce FX Go5200" },␊ |
301 | ␉{ 0x10DE032A,␉"Quadro NVS 55/280 PCI" },␊ |
302 | ␉{ 0x10DE032B,␉"Quadro FX 500/600 PCI" },␊ |
303 | ␉{ 0x10DE032C,␉"GeForce FX Go53xx Series" },␊ |
304 | ␉{ 0x10DE032D,␉"GeForce FX Go5100" },␊ |
305 | ␉// { 0x10DE032F,␉"NVIDIA NV34GL" },␊ |
306 | ␉// 0330 - 033F␊ |
307 | ␉{ 0x10DE0330,␉"GeForce FX 5900 Ultra" },␊ |
308 | ␉{ 0x10DE0331,␉"GeForce FX 5900" },␊ |
309 | ␉{ 0x10DE0332,␉"GeForce FX 5900XT" },␊ |
310 | ␉{ 0x10DE0333,␉"GeForce FX 5950 Ultra" },␊ |
311 | ␉{ 0x10DE0334,␉"GeForce FX 5900ZT" },␊ |
312 | ␉{ 0x10DE0338,␉"Quadro FX 3000" },␊ |
313 | ␉{ 0x10DE033F,␉"Quadro FX 700" },␊ |
314 | ␉// 0340 - 034F␊ |
315 | ␉{ 0x10DE0341,␉"GeForce FX 5700 Ultra" },␊ |
316 | ␉{ 0x10DE0342,␉"GeForce FX 5700" },␊ |
317 | ␉{ 0x10DE0343,␉"GeForce FX 5700LE" },␊ |
318 | ␉{ 0x10DE0344,␉"GeForce FX 5700VE" },␊ |
319 | ␉// { 0x10DE0345,␉"NVIDIA NV36.5" },␊ |
320 | ␉{ 0x10DE0347,␉"GeForce FX Go5700" },␊ |
321 | ␉{ 0x10DE0348,␉"GeForce FX Go5700" },␊ |
322 | ␉// { 0x10DE0349,␉"NVIDIA NV36M Pro" },␊ |
323 | ␉// { 0x10DE034B,␉"NVIDIA NV36MAP" },␊ |
324 | ␉{ 0x10DE034C,␉"Quadro FX Go1000" },␊ |
325 | ␉{ 0x10DE034E,␉"Quadro FX 1100" },␊ |
326 | ␉// { 0x10DE034F,␉"NVIDIA NV36GL" },␊ |
327 | ␉// 0350 - 035F␊ |
328 | ␉// 0360 - 036F␊ |
329 | ␉// 0370 - 037F␊ |
330 | ␉// 0380 - 038F␊ |
331 | ␉{ 0x10DE038B,␉"GeForce 7650 GS" },␊ |
332 | ␉// 0390 - 039F␊ |
333 | ␉{ 0x10DE0390,␉"GeForce 7650 GS" },␊ |
334 | ␉{ 0x10DE0391,␉"GeForce 7600 GT" },␊ |
335 | ␉{ 0x10DE0392,␉"GeForce 7600 GS" },␊ |
336 | ␉{ 0x10DE0393,␉"GeForce 7300 GT" },␊ |
337 | ␉{ 0x10DE0394,␉"GeForce 7600 LE" },␊ |
338 | ␉{ 0x10DE0395,␉"GeForce 7300 GT" },␊ |
339 | ␉{ 0x10DE0397,␉"GeForce Go 7700" },␊ |
340 | ␉{ 0x10DE0398,␉"GeForce Go 7600" },␊ |
341 | ␉{ 0x10DE0399,␉"GeForce Go 7600 GT"},␊ |
342 | ␉{ 0x10DE039A,␉"Quadro NVS 300M" },␊ |
343 | ␉{ 0x10DE039B,␉"GeForce Go 7900 SE" },␊ |
344 | ␉{ 0x10DE039C,␉"Quadro FX 560M" },␊ |
345 | ␉{ 0x10DE039E,␉"Quadro FX 560" },␊ |
346 | ␉// 03A0 - 03AF␊ |
347 | ␉// 03B0 - 03BF␊ |
348 | ␉// 03C0 - 03CF␊ |
349 | ␉// 03D0 - 03DF␊ |
350 | ␉{ 0x10DE03D0,␉"GeForce 6150SE nForce 430" },␊ |
351 | ␉{ 0x10DE03D1,␉"GeForce 6100 nForce 405" },␊ |
352 | ␉{ 0x10DE03D2,␉"GeForce 6100 nForce 400" },␊ |
353 | ␉{ 0x10DE03D5,␉"GeForce 6100 nForce 420" },␊ |
354 | ␉{ 0x10DE03D6,␉"GeForce 7025 / nForce 630a" },␊ |
355 | ␉// 03E0 - 03EF␊ |
356 | ␉// 03F0 - 03FF␊ |
357 | ␉// 0400 - 040F␊ |
358 | ␉{ 0x10DE0400,␉"GeForce 8600 GTS" },␊ |
359 | ␉{ 0x10DE0401,␉"GeForce 8600 GT" },␊ |
360 | ␉{ 0x10DE0402,␉"GeForce 8600 GT" },␊ |
361 | ␉{ 0x10DE0403,␉"GeForce 8600 GS" },␊ |
362 | ␉{ 0x10DE0404,␉"GeForce 8400 GS" },␊ |
363 | ␉{ 0x10DE0405,␉"GeForce 9500M GS" },␊ |
364 | ␉{ 0x10DE0406,␉"GeForce 8300 GS" },␊ |
365 | ␉{ 0x10DE0407,␉"GeForce 8600M GT" },␊ |
366 | ␉{ 0x10DE0408,␉"GeForce 9650M GS" },␊ |
367 | ␉{ 0x10DE0409,␉"GeForce 8700M GT" },␊ |
368 | ␉{ 0x10DE040A,␉"Quadro FX 370" },␊ |
369 | ␉{ 0x10DE040B,␉"Quadro NVS 320M" },␊ |
370 | ␉{ 0x10DE040C,␉"Quadro FX 570M" },␊ |
371 | ␉{ 0x10DE040D,␉"Quadro FX 1600M" },␊ |
372 | ␉{ 0x10DE040E,␉"Quadro FX 570" },␊ |
373 | ␉{ 0x10DE040F,␉"Quadro FX 1700" },␊ |
374 | ␉// 0410 - 041F␊ |
375 | ␉{ 0x10DE0410,␉"GeForce GT 330" },␊ |
376 | ␉// 0420 - 042F␊ |
377 | ␉{ 0x10DE0420,␉"GeForce 8400 SE" },␊ |
378 | ␉{ 0x10DE0421,␉"GeForce 8500 GT" },␊ |
379 | ␉{ 0x10DE0422,␉"GeForce 8400 GS" },␊ |
380 | ␉{ 0x10DE0423,␉"GeForce 8300 GS" },␊ |
381 | ␉{ 0x10DE0424,␉"GeForce 8400 GS" },␊ |
382 | ␉{ 0x10DE0425,␉"GeForce 8600M GS" },␊ |
383 | ␉{ 0x10DE0426,␉"GeForce 8400M GT" },␊ |
384 | ␉{ 0x10DE0427,␉"GeForce 8400M GS" },␊ |
385 | ␉{ 0x10DE0428,␉"GeForce 8400M G" },␊ |
386 | ␉{ 0x10DE0429,␉"Quadro NVS 140M" },␊ |
387 | ␉{ 0x10DE042A,␉"Quadro NVS 130M" },␊ |
388 | ␉{ 0x10DE042B,␉"Quadro NVS 135M" },␊ |
389 | ␉{ 0x10DE042C,␉"GeForce 9400 GT" },␊ |
390 | ␉{ 0x10DE042D,␉"Quadro FX 360M" },␊ |
391 | ␉{ 0x10DE042E,␉"GeForce 9300M G" },␊ |
392 | ␉{ 0x10DE042F,␉"Quadro NVS 290" },␊ |
393 | ␉// 0430 - 043F␊ |
394 | ␉// 0440 - 044F␊ |
395 | ␉// 0450 - 045F␊ |
396 | ␉// 0460 - 046F␊ |
397 | ␉// 0470 - 047F␊ |
398 | ␉// 0480 - 048F␊ |
399 | ␉// 0490 - 049F␊ |
400 | ␉// 04A0 - 04AF␊ |
401 | ␉// 04B0 - 04BF␊ |
402 | ␉// 04C0 - 04CF␊ |
403 | ␉{ 0x10DE04C0,␉"NVIDIA G78" },␊ |
404 | ␉{ 0x10DE04C1,␉"NVIDIA G78" },␊ |
405 | ␉{ 0x10DE04C2,␉"NVIDIA G78" },␊ |
406 | ␉{ 0x10DE04C3,␉"NVIDIA G78" },␊ |
407 | ␉{ 0x10DE04C4,␉"NVIDIA G78" },␊ |
408 | ␉{ 0x10DE04C5,␉"NVIDIA G78" },␊ |
409 | ␉{ 0x10DE04C6,␉"NVIDIA G78" },␊ |
410 | ␉{ 0x10DE04C7,␉"NVIDIA G78" },␊ |
411 | ␉{ 0x10DE04C8,␉"NVIDIA G78" },␊ |
412 | ␉{ 0x10DE04C9,␉"NVIDIA G78" },␊ |
413 | ␉{ 0x10DE04CA,␉"NVIDIA G78" },␊ |
414 | ␉{ 0x10DE04CB,␉"NVIDIA G78" },␊ |
415 | ␉{ 0x10DE04CC,␉"NVIDIA G78" },␊ |
416 | ␉{ 0x10DE04CD,␉"NVIDIA G78" },␊ |
417 | ␉{ 0x10DE04CE,␉"NVIDIA G78" },␊ |
418 | ␉{ 0x10DE04CF,␉"NVIDIA G78" },␊ |
419 | ␉// 04D0 - 04DF␊ |
420 | ␉// 04E0 - 04EF␊ |
421 | ␉// 04F0 - 04FF␊ |
422 | ␉// 0500 - 050F␊ |
423 | ␉// 0510 - 051F␊ |
424 | ␉// 0520 - 052F␊ |
425 | ␉// 0530 - 053F␊ |
426 | ␉{ 0x10DE0530,␉"GeForce 7190M / nForce 650M" },␊ |
427 | ␉{ 0x10DE0531,␉"GeForce 7150M / nForce 630M" },␊ |
428 | ␉{ 0x10DE0533,␉"GeForce 7000M / nForce 610M" },␊ |
429 | ␉{ 0x10DE053A,␉"GeForce 7050 PV / nForce 630a" },␊ |
430 | ␉{ 0x10DE053B,␉"GeForce 7050 PV / nForce 630a" },␊ |
431 | ␉{ 0x10DE053E,␉"GeForce 7025 / nForce 630a" },␊ |
432 | ␉// 0540 - 054F␊ |
433 | ␉// 0550 - 055F␊ |
434 | ␉// 0560 - 056F␊ |
435 | ␉// 0570 - 057F␊ |
436 | ␉// 0580 - 058F␊ |
437 | ␉// 0590 - 059F␊ |
438 | ␉// 05A0 - 05AF␊ |
439 | ␉// 05B0 - 05BF␊ |
440 | ␉// 05C0 - 05CF␊ |
441 | ␉// 05D0 - 05DF␊ |
442 | ␉// 05E0 - 05EF␊ |
443 | ␉{ 0x10DE05E0,␉"GeForce GTX 295" },␊ |
444 | ␉{ 0x10DE05E1,␉"GeForce GTX 280" },␊ |
445 | ␉{ 0x10DE05E2,␉"GeForce GTX 260" },␊ |
446 | ␉{ 0x10DE05E3,␉"GeForce GTX 285" },␊ |
447 | ␉{ 0x10DE05E4,␉"NVIDIA GT200" },␊ |
448 | ␉{ 0x10DE05E5,␉"NVIDIA GT200" },␊ |
449 | ␉{ 0x10DE05E6,␉"GeForce GTX 275" },␊ |
450 | ␉{ 0x10DE05E7,␉"Tesla C1060" },␊ |
451 | ␉{ 0x10DE05E8,␉"NVIDIA GT200" },␊ |
452 | ␉{ 0x10DE05E9,␉"NVIDIA GT200" },␊ |
453 | ␉{ 0x10DE05EA,␉"GeForce GTX 260" },␊ |
454 | ␉{ 0x10DE05EB,␉"GeForce GTX 295" },␊ |
455 | ␉{ 0x10DE05EC,␉"NVIDIA GT200" },␊ |
456 | ␉{ 0x10DE05ED,␉"Quadroplex 2200 D2" },␊ |
457 | ␉{ 0x10DE05EE,␉"NVIDIA GT200" },␊ |
458 | ␉{ 0x10DE05EF,␉"NVIDIA GT200" },␊ |
459 | ␉// 05F0 - 05FF␊ |
460 | ␉{ 0x10DE05F0,␉"NVIDIA GT200" },␊ |
461 | ␉{ 0x10DE05F1,␉"NVIDIA GT200" },␊ |
462 | ␉{ 0x10DE05F2,␉"NVIDIA GT200" },␊ |
463 | ␉{ 0x10DE05F3,␉"NVIDIA GT200" },␊ |
464 | ␉{ 0x10DE05F4,␉"NVIDIA GT200" },␊ |
465 | ␉{ 0x10DE05F5,␉"NVIDIA GT200" },␊ |
466 | ␉{ 0x10DE05F6,␉"NVIDIA GT200" },␊ |
467 | ␉{ 0x10DE05F7,␉"NVIDIA GT200" },␊ |
468 | ␉{ 0x10DE05F8,␉"Quadroplex 2200 S4" },␊ |
469 | ␉{ 0x10DE05F9,␉"Quadro CX" },␊ |
470 | ␉{ 0x10DE05FA,␉"NVIDIA GT200" },␊ |
471 | ␉{ 0x10DE05FB,␉"NVIDIA GT200" },␊ |
472 | ␉{ 0x10DE05FC,␉"NVIDIA GT200" },␊ |
473 | ␉{ 0x10DE05FD,␉"Quadro FX 5800" },␊ |
474 | ␉{ 0x10DE05FE,␉"Quadro FX 4800" },␊ |
475 | ␉{ 0x10DE05FF,␉"Quadro FX 3800" },␊ |
476 | ␉// 0600 - 060F␊ |
477 | ␉{ 0x10DE0600,␉"GeForce 8800 GTS 512" },␊ |
478 | ␉{ 0x10DE0601,␉"GeForce 9800 GT" },␊ |
479 | ␉{ 0x10DE0602,␉"GeForce 8800 GT" },␊ |
480 | ␉{ 0x10DE0603,␉"GeForce GT 230" },␊ |
481 | ␉{ 0x10DE0604,␉"GeForce 9800 GX2" },␊ |
482 | ␉{ 0x10DE0605,␉"GeForce 9800 GT" },␊ |
483 | ␉{ 0x10DE0606,␉"GeForce 8800 GS" },␊ |
484 | ␉{ 0x10DE0607,␉"GeForce GTS 240" },␊ |
485 | ␉{ 0x10DE0608,␉"GeForce 9800M GTX" },␊ |
486 | ␉{ 0x10DE0609,␉"GeForce 8800M GTS" },␊ |
487 | ␉{ 0x10DE060A,␉"GeForce GTX 280M" },␊ |
488 | ␉{ 0x10DE060B,␉"GeForce 9800M GT" },␊ |
489 | ␉{ 0x10DE060C,␉"GeForce 8800M GTX" },␊ |
490 | ␉{ 0x10DE060D,␉"GeForce 8800 GS" },␊ |
491 | ␉{ 0x10DE060F,␉"GeForce GTX 285M" },␊ |
492 | ␉// 0610 - 061F␊ |
493 | ␉{ 0x10DE0610,␉"GeForce 9600 GSO" },␊ |
494 | ␉{ 0x10DE0611,␉"GeForce 8800 GT" },␊ |
495 | ␉{ 0x10DE0612,␉"GeForce 9800 GTX" },␊ |
496 | ␉{ 0x10DE0613,␉"GeForce 9800 GTX+" },␊ |
497 | ␉{ 0x10DE0614,␉"GeForce 9800 GT" },␊ |
498 | ␉{ 0x10DE0615,␉"GeForce GTS 250" },␊ |
499 | ␉{ 0x10DE0617,␉"GeForce 9800M GTX" },␊ |
500 | ␉/* START */␊ |
501 | ␉{ 0x10DE0618,␉"GeForce GTX 260M" },␊ |
502 | ␉// { 0x10DE0618,␉0x1025028E,␉"GeForce GTX 260M" },␊ |
503 | ␉// { 0x10DE0618,␉0x102802A1,␉"GeForce GTX 260M" },␊ |
504 | ␉// { 0x10DE0618,␉0x102802A2,␉"GeForce GTX 260M" },␊ |
505 | ␉// { 0x10DE0618,␉0x10431A52,␉"GeForce GTX 260M" },␊ |
506 | ␉// { 0x10DE0618,␉0x10432028,␉"GeForce GTX 260M" },␊ |
507 | ␉// { 0x10DE0618,␉0x1043202B,␉"Asus GTX 680" }, // Subsystem Id: 1043 202B Asus GTX 680␊ |
508 | ␉// { 0x10DE0618,␉0x10432033,␉"GeForce GTX 260M" },␊ |
509 | ␉// { 0x10DE0618,␉0x15580481,␉"GeForce GTX 260M" },␊ |
510 | ␉// { 0x10DE0618,␉0x15580577,␉"GeForce GTX 260M" },␊ |
511 | ␉// { 0x10DE0618,␉0x15580860,␉"GeForce GTX 260M" },␊ |
512 | ␉/* END */␊ |
513 | ␉{ 0x10DE0619,␉"Quadro FX 4700 X2" },␊ |
514 | ␉{ 0x10DE061A,␉"Quadro FX 3700" },␊ |
515 | ␉{ 0x10DE061B,␉"Quadro VX 200" },␊ |
516 | ␉{ 0x10DE061C,␉"Quadro FX 3600M" },␊ |
517 | ␉{ 0x10DE061D,␉"Quadro FX 2800M" },␊ |
518 | ␉{ 0x10DE061E,␉"Quadro FX 3700M" },␊ |
519 | ␉{ 0x10DE061F,␉"Quadro FX 3800M" },␊ |
520 | ␉// 0620 - 062F␊ |
521 | ␉{ 0x10DE0620,␉"NVIDIA G94" }, // GeForce 8100/8200/8300␊ |
522 | ␉{ 0x10DE0621,␉"GeForce GT 230" },␊ |
523 | ␉{ 0x10DE0622,␉"GeForce 9600 GT" },␊ |
524 | ␉{ 0x10DE0623,␉"GeForce 9600 GS" },␊ |
525 | ␉{ 0x10DE0624,␉"NVIDIA G94" },␊ |
526 | ␉{ 0x10DE0625,␉"GeForce 9600 GSO 512"},␊ |
527 | ␉{ 0x10DE0626,␉"GeForce GT 130" },␊ |
528 | ␉{ 0x10DE0627,␉"GeForce GT 140" },␊ |
529 | ␉{ 0x10DE0628,␉"GeForce 9800M GTS" },␊ |
530 | ␉{ 0x10DE0629,␉"NVIDIA G94" },␊ |
531 | ␉{ 0x10DE062A,␉"GeForce 9700M GTS" },␊ |
532 | ␉{ 0x10DE062B,␉"GeForce 9800M GS" },␊ |
533 | ␉{ 0x10DE062C,␉"GeForce 9800M GTS" },␊ |
534 | ␉{ 0x10DE062D,␉"GeForce 9600 GT" },␊ |
535 | ␉{ 0x10DE062E,␉"GeForce 9600 GT" },␊ |
536 | ␉{ 0x10DE062F,␉"GeForce 9800 S" },␊ |
537 | ␉// 0630 - 063F␊ |
538 | ␉{ 0x10DE0630,␉"NVIDIA G94" },␊ |
539 | ␉{ 0x10DE0631,␉"GeForce GTS 160M" },␊ |
540 | ␉{ 0x10DE0632,␉"GeForce GTS 150M" },␊ |
541 | ␉{ 0x10DE0633,␉"NVIDIA G94" },␊ |
542 | ␉{ 0x10DE0634,␉"NVIDIA G94" },␊ |
543 | ␉{ 0x10DE0635,␉"GeForce 9600 GSO" },␊ |
544 | ␉{ 0x10DE0636,␉"NVIDIA G94" },␊ |
545 | ␉{ 0x10DE0637,␉"GeForce 9600 GT" },␊ |
546 | ␉{ 0x10DE0638,␉"Quadro FX 1800" },␊ |
547 | ␉{ 0x10DE0639,␉"NVIDIA G94" },␊ |
548 | ␉{ 0x10DE063A,␉"Quadro FX 2700M" },␊ |
549 | ␉{ 0x10DE063B,␉"NVIDIA G94" },␊ |
550 | ␉{ 0x10DE063C,␉"NVIDIA G94" },␊ |
551 | ␉{ 0x10DE063D,␉"NVIDIA G94" },␊ |
552 | ␉{ 0x10DE063E,␉"NVIDIA G94" },␊ |
553 | ␉{ 0x10DE063F,␉"NVIDIA G94" },␊ |
554 | ␉// 0640 - 064F␊ |
555 | ␉{ 0x10DE0640,␉"GeForce 9500 GT" },␊ |
556 | ␉{ 0x10DE0641,␉"GeForce 9400 GT" },␊ |
557 | ␉{ 0x10DE0642,␉"GeForce 8400 GS" },␊ |
558 | ␉{ 0x10DE0643,␉"GeForce 9500 GT" },␊ |
559 | ␉{ 0x10DE0644,␉"GeForce 9500 GS" },␊ |
560 | ␉{ 0x10DE0645,␉"GeForce 9500 GS" },␊ |
561 | ␉{ 0x10DE0646,␉"GeForce GT 120" },␊ |
562 | ␉{ 0x10DE0647,␉"GeForce 9600M GT" },␊ |
563 | ␉{ 0x10DE0648,␉"GeForce 9600M GS" },␊ |
564 | ␉{ 0x10DE0649,␉"GeForce 9600M GT" },␊ |
565 | ␉{ 0x10DE064A,␉"GeForce 9700M GT" },␊ |
566 | ␉{ 0x10DE064B,␉"GeForce 9500M G" },␊ |
567 | ␉{ 0x10DE064C,␉"GeForce 9650M GT" },␊ |
568 | ␉// 0650 - 065F␊ |
569 | ␉{ 0x10DE0650,␉"NVIDIA G96-825" },␊ |
570 | ␉{ 0x10DE0651,␉"GeForce G 110M" },␊ |
571 | ␉{ 0x10DE0652,␉"GeForce GT 130M" },␊ |
572 | ␉{ 0x10DE0653,␉"GeForce GT 120M" },␊ |
573 | ␉{ 0x10DE0654,␉"GeForce GT 220M" },␊ |
574 | ␉{ 0x10DE0655,␉"GeForce GT 120" },␊ |
575 | ␉{ 0x10DE0656,␉"GeForce 9650 S" },␊ |
576 | ␉{ 0x10DE0657,␉"NVIDIA G96" },␊ |
577 | ␉{ 0x10DE0658,␉"Quadro FX 380" },␊ |
578 | ␉{ 0x10DE0659,␉"Quadro FX 580" },␊ |
579 | ␉{ 0x10DE065A,␉"Quadro FX 1700M" },␊ |
580 | ␉{ 0x10DE065B,␉"GeForce 9400 GT" },␊ |
581 | ␉{ 0x10DE065C,␉"Quadro FX 770M" },␊ |
582 | ␉{ 0x10DE065D,␉"NVIDIA G96" },␊ |
583 | ␉{ 0x10DE065E,␉"NVIDIA G96" },␊ |
584 | ␉{ 0x10DE065F,␉"GeForce G210" },␊ |
585 | ␉// 0660 - 066F␊ |
586 | ␉// 0670 - 067F␊ |
587 | ␉// 0680 - 068F␊ |
588 | ␉// 0690 - 069F␊ |
589 | ␉// 06A0 - 06AF␊ |
590 | ␉{ 0x10DE06A0,␉"NVIDIA GT214" },␊ |
591 | ␉// 06B0 - 06BF␊ |
592 | ␉{ 0x10DE06B0,␉"NVIDIA GT214" },␊ |
593 | ␉// 06C0 - 06CF␊ |
594 | ␉{ 0x10DE06C0,␉"GeForce GTX 480" },␊ |
595 | ␉{ 0x10DE06C3,␉"GeForce GTX D12U" },␊ |
596 | ␉{ 0x10DE06C4,␉"GeForce GTX 465" },␊ |
597 | ␉{ 0x10DE06CA,␉"GeForce GTX 480M" },␊ |
598 | ␉{ 0x10DE06CD,␉"GeForce GTX 470" },␊ |
599 | ␉// 06D0 - 06DF␊ |
600 | ␉/* START */␊ |
601 | ␉{ 0x10DE06D1,␉"Tesla C2050 / C2070" },␊ |
602 | ␉// { 0x10DE06D1,␉0x10DE0771,␉"Tesla C2050" },␊ |
603 | ␉// { 0x10DE06D1,␉0x10DE0772,␉"Tesla C2070" },␊ |
604 | ␉{ 0x10DE06D2,␉"Tesla M2070 / X2070" },␊ |
605 | ␉// { 0x10DE06D2,␉0x10DE0774,␉"Tesla M2070" },␊ |
606 | ␉// { 0x10DE06D2,␉0x10DE0830,␉"Tesla M2070" },␊ |
607 | ␉// { 0x10DE06D2,␉0x10DE0842,␉"Tesla M2070" },␊ |
608 | ␉// { 0x10DE06D2,␉0x10DE088F,␉"Tesla X2070" },␊ |
609 | ␉// { 0x10DE06D2,␉0x10DE0908,␉"Tesla M2070" },␊ |
610 | ␉/* END */␊ |
611 | ␉{ 0x10DE06D8,␉"Quadro 6000" },␊ |
612 | ␉{ 0x10DE06D9,␉"Quadro 5000" },␊ |
613 | ␉{ 0x10DE06DA,␉"Quadro 5000M" },␊ |
614 | ␉{ 0x10DE06DC,␉"Quadro 6000" },␊ |
615 | ␉{ 0x10DE06DD,␉"Quadro 4000" },␊ |
616 | ␉{ 0x10DE06DE,␉"Tesla M2050" },␉// TODO: sub-device id: 0x0846␊ |
617 | ␉{ 0x10DE06DE,␉"Tesla M2070" },␉// TODO: sub-device id: ?␉␊ |
618 | ␉{ 0x10DE06DF,␉"Tesla M2070-Q" },␊ |
619 | ␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊ |
620 | ␉// 06E0 - 06EF␊ |
621 | ␉{ 0x10DE06E0,␉"GeForce 9300 GE" },␊ |
622 | ␉{ 0x10DE06E1,␉"GeForce 9300 GS" },␊ |
623 | ␉{ 0x10DE06E2,␉"GeForce 8400" },␊ |
624 | ␉{ 0x10DE06E3,␉"GeForce 8400 SE" },␊ |
625 | ␉{ 0x10DE06E4,␉"GeForce 8400 GS" },␊ |
626 | ␉{ 0x10DE06E5,␉"GeForce 9300M GS" },␊ |
627 | ␉{ 0x10DE06E6,␉"GeForce G100" },␊ |
628 | ␉{ 0x10DE06E7,␉"GeForce 9300 SE" },␊ |
629 | ␉{ 0x10DE06E8,␉"GeForce 9200M GS" },␊ |
630 | ␉{ 0x10DE06E9,␉"GeForce 9300M GS" },␊ |
631 | ␉{ 0x10DE06EA,␉"Quadro NVS 150M" },␊ |
632 | ␉{ 0x10DE06EB,␉"Quadro NVS 160M" },␊ |
633 | ␉{ 0x10DE06EC,␉"GeForce G 105M" },␊ |
634 | ␉{ 0x10DE06ED,␉"NVIDIA G98" },␊ |
635 | ␉{ 0x10DE06EF,␉"GeForce G 103M" },␊ |
636 | ␉// 06F0 - 06FF␊ |
637 | ␉{ 0x10DE06F0,␉"NVIDIA G98" },␊ |
638 | ␉{ 0x10DE06F1,␉"GeForce G105M" },␊ |
639 | ␉{ 0x10DE06F2,␉"NVIDIA G98" },␊ |
640 | ␉{ 0x10DE06F3,␉"NVIDIA G98" },␊ |
641 | ␉{ 0x10DE06F4,␉"NVIDIA G98" },␊ |
642 | ␉{ 0x10DE06F5,␉"NVIDIA G98" },␊ |
643 | ␉{ 0x10DE06F6,␉"NVIDIA G98" },␊ |
644 | ␉{ 0x10DE06F7,␉"NVIDIA G98" },␊ |
645 | ␉{ 0x10DE06F8,␉"Quadro NVS 420" },␊ |
646 | ␉{ 0x10DE06F9,␉"Quadro FX 370 LP" },␊ |
647 | ␉{ 0x10DE06FA,␉"Quadro NVS 450" },␊ |
648 | ␉{ 0x10DE06FB,␉"Quadro FX 370M" },␊ |
649 | ␉{ 0x10DE06FC,␉"NVIDIA G98" },␊ |
650 | ␉{ 0x10DE06FD,␉"Quadro NVS 295" },␊ |
651 | ␉{ 0x10DE06FE,␉"NVIDIA G98" },␊ |
652 | ␉{ 0x10DE06FF,␉"HICx16 + Graphics" },␊ |
653 | ␉// 0700 - 070F␊ |
654 | ␉// 0710 - 071F␊ |
655 | ␉// 0720 - 072F␊ |
656 | ␉// 0730 - 073F␊ |
657 | ␉// 0740 - 074F␊ |
658 | ␉// 0750 - 075F␊ |
659 | ␉// 0760 - 076F␊ |
660 | ␉// 0770 - 077F␊ |
661 | ␉// 0780 - 078F␊ |
662 | ␉// 0790 - 079F␊ |
663 | ␉// 07A0 - 07AF␊ |
664 | ␉// 07B0 - 07BF␊ |
665 | ␉// 07C0 - 07CF␊ |
666 | ␉// 07D0 - 07DF␊ |
667 | ␉// 07E0 - 07EF␊ |
668 | ␉{ 0x10DE07E0,␉"GeForce 7150 / nForce 630i" },␊ |
669 | ␉{ 0x10DE07E1,␉"GeForce 7100 / nForce 630i" },␊ |
670 | ␉{ 0x10DE07E2,␉"GeForce 7050 / nForce 630i" },␊ |
671 | ␉{ 0x10DE07E3,␉"GeForce 7050 / nForce 610i" },␊ |
672 | ␉{ 0x10DE07E5,␉"GeForce 7050 / nForce 620i" },␊ |
673 | ␉// 07F0 - 07FF␊ |
674 | ␉// 0800 - 080F␊ |
675 | ␉// 0810 - 081F␊ |
676 | ␉// 0820 - 082F␊ |
677 | ␉// 0830 - 083F␊ |
678 | ␉// 0840 - 084F␊ |
679 | ␉{ 0x10DE0840,␉"GeForce 8200M" },␊ |
680 | ␉{ 0x10DE0844,␉"GeForce 9100M G" },␊ |
681 | ␉{ 0x10DE0845,␉"GeForce 8200M G" },␊ |
682 | ␉{ 0x10DE0846,␉"GeForce 9200" },␊ |
683 | ␉{ 0x10DE0847,␉"GeForce 9100" },␊ |
684 | ␉{ 0x10DE0848,␉"GeForce 8300" },␊ |
685 | ␉{ 0x10DE0849,␉"GeForce 8200" },␊ |
686 | ␉{ 0x10DE084A,␉"nForce 730a" },␊ |
687 | ␉{ 0x10DE084B,␉"GeForce 9200" },␊ |
688 | ␉{ 0x10DE084C,␉"nForce 980a/780a SLI" },␊ |
689 | ␉{ 0x10DE084D,␉"nForce 750a SLI" },␊ |
690 | ␉{ 0x10DE084F,␉"GeForce 8100 / nForce 720a" },␊ |
691 | ␉// 0850 - 085F␊ |
692 | ␉// 0860 - 086F␊ |
693 | ␉{ 0x10DE0860,␉"GeForce 9300" },␊ |
694 | ␉{ 0x10DE0861,␉"GeForce 9400" },␊ |
695 | ␉{ 0x10DE0862,␉"GeForce 9400M G" },␊ |
696 | ␉{ 0x10DE0863,␉"GeForce 9400M" },␊ |
697 | ␉{ 0x10DE0864,␉"GeForce 9300" },␊ |
698 | ␉{ 0x10DE0865,␉"GeForce 9300" },␊ |
699 | ␉{ 0x10DE0866,␉"GeForce 9400M G" },␊ |
700 | ␉{ 0x10DE0867,␉"GeForce 9400" },␊ |
701 | ␉{ 0x10DE0868,␉"nForce 760i SLI" },␊ |
702 | ␉{ 0x10DE0869,␉"GeForce 9400" },␊ |
703 | ␉{ 0x10DE086A,␉"GeForce 9400" },␊ |
704 | ␉{ 0x10DE086C,␉"GeForce 9300 / nForce 730i" },␊ |
705 | ␉{ 0x10DE086D,␉"GeForce 9200" },␊ |
706 | ␉{ 0x10DE086E,␉"GeForce 9100M G" },␊ |
707 | ␉{ 0x10DE086F,␉"GeForce 8200M G" },␊ |
708 | ␉// 0870 - 087F␊ |
709 | ␉{ 0x10DE0870,␉"GeForce 9400M" },␊ |
710 | ␉{ 0x10DE0871,␉"GeForce 9200" },␊ |
711 | ␉{ 0x10DE0872,␉"GeForce G102M" },␊ |
712 | ␉{ 0x10DE0873,␉"GeForce G102M" },␊ |
713 | ␉{ 0x10DE0874,␉"ION 9300M" },␉␊ |
714 | ␉{ 0x10DE0876,␉"ION 9400M" },␊ |
715 | ␉{ 0x10DE087A,␉"GeForce 9400" },␊ |
716 | ␉{ 0x10DE087D,␉"ION 9400M" },␊ |
717 | ␉{ 0x10DE087E,␉"ION LE" },␊ |
718 | ␉{ 0x10DE087F,␉"ION LE" },␊ |
719 | ␉// 0880 - 088F␊ |
720 | ␉// 0890 - 089F␊ |
721 | ␉// 08A0 - 08AF␊ |
722 | ␉{ 0x10DE08A0,␉"GeForce 320M" },␊ |
723 | ␉// { 0x10DE08A1,␉"NVIDIA MCP89-MZT" },␊ |
724 | ␉// { 0x10DE08A2,␉"NVIDIA MCP89-EPT" },␊ |
725 | ␉{ 0x10DE08A3,␉"GeForce 320M" },␊ |
726 | ␉{ 0x10DE08A4,␉"GeForce 320M" },␊ |
727 | ␉{ 0x10DE08A5,␉"GeForce 320M" },␊ |
728 | ␉// 08B0 - 08BF␊ |
729 | ␉// { 0x10DE08B0,␉"MCP83 MMD" },␊ |
730 | ␉{ 0x10DE08B1,␉"GeForce 300M" },␊ |
731 | ␉// { 0x10DE08B2,␉"NVIDIA MCP83-MJ" },␊ |
732 | ␉// { 0x10DE08B3,␉"NVIDIA MCP89 MM9" },␊ |
733 | ␉// 08C0 - 08CF␊ |
734 | ␉// 08D0 - 08DF␊ |
735 | ␉// 08E0 - 08EF␊ |
736 | ␉// 08F0 - 08FF␊ |
737 | ␉// 0900 - 090F␊ |
738 | ␉// 0910 - 091F␊ |
739 | ␉// 0920 - 092F␊ |
740 | ␉// 0930 - 093F␊ |
741 | ␉// 0940 - 094F␊ |
742 | ␉// 0950 - 095F␊ |
743 | ␉// 0960 - 096F␊ |
744 | ␉// 0970 - 097F␊ |
745 | ␉// 0980 - 098F␊ |
746 | ␉// 0990 - 099F␊ |
747 | ␉// 09A0 - 09AF␊ |
748 | ␉// 09B0 - 09BF␊ |
749 | ␉// 09C0 - 09CF␊ |
750 | ␉// 09D0 - 09DF␊ |
751 | ␉// 09E0 - 09EF␊ |
752 | ␉// 09F0 - 09FF␊ |
753 | ␉// 0A00 - 0A0F␊ |
754 | ␉// { 0x10DE0A00,␉"NVIDIA GT212" },␊ |
755 | ␉// 0A10 - 0A1F␊ |
756 | ␉// { 0x10DE0A10,␉"NVIDIA GT212" },␊ |
757 | ␉// 0A20 - 0A2F␊ |
758 | ␉{ 0x10DE0A20,␉"GeForce GT 220" },␊ |
759 | ␉// { 0x10DE0A21,␉"NVIDIA D10M2-20" },␊ |
760 | ␉{ 0x10DE0A22,␉"GeForce 315" },␊ |
761 | ␉{ 0x10DE0A23,␉"GeForce 210" },␊ |
762 | ␉{ 0x10DE0A26,␉"GeForce 405" },␊ |
763 | ␉{ 0x10DE0A27,␉"GeForce 405" },␊ |
764 | ␉{ 0x10DE0A28,␉"GeForce GT 230M" },␊ |
765 | ␉{ 0x10DE0A29,␉"GeForce GT 330M" },␊ |
766 | ␉{ 0x10DE0A2A,␉"GeForce GT 230M" },␊ |
767 | ␉{ 0x10DE0A2B,␉"GeForce GT 330M" },␊ |
768 | ␉{ 0x10DE0A2C,␉"NVS 5100M" },␊ |
769 | ␉{ 0x10DE0A2D,␉"GeForce GT 320M" },␉␊ |
770 | ␉// 0A30 - 0A3F␊ |
771 | ␉// { 0x10DE0A30,␉"NVIDIA GT216" },␊ |
772 | ␉{ 0x10DE0A32,␉"GeForce GT 415" },␊ |
773 | ␉{ 0x10DE0A34,␉"GeForce GT 240M" },␊ |
774 | ␉{ 0x10DE0A35,␉"GeForce GT 325M" },␊ |
775 | ␉{ 0x10DE0A38,␉"Quadro 400" },␊ |
776 | ␉{ 0x10DE0A3C,␉"Quadro FX 880M" },␊ |
777 | ␉// { 0x10DE0A3D,␉"NVIDIA N10P-ES" },␊ |
778 | ␉// { 0x10DE0A3F,␉"NVIDIA GT216-INT" },␊ |
779 | ␉// 0A40 - 0A4F␊ |
780 | ␉// 0A50 - 0A5F␊ |
781 | ␉// 0A60 - 0A6F␊ |
782 | ␉{ 0x10DE0A60,␉"GeForce G210" },␊ |
783 | ␉// { 0x10DE0A61,␉"NVIDIA NVS 2100" },␊ |
784 | ␉{ 0x10DE0A62,␉"GeForce 205" },␊ |
785 | ␉{ 0x10DE0A63,␉"GeForce 310" },␊ |
786 | ␉{ 0x10DE0A64,␉"ION" },␊ |
787 | ␉{ 0x10DE0A65,␉"GeForce 210" },␊ |
788 | ␉{ 0x10DE0A66,␉"GeForce 310" },␊ |
789 | ␉{ 0x10DE0A67,␉"GeForce 315" },␊ |
790 | ␉{ 0x10DE0A68,␉"GeForce G105M" },␊ |
791 | ␉{ 0x10DE0A69,␉"GeForce G105M" },␊ |
792 | ␉{ 0x10DE0A6A,␉"NVS 2100M" },␊ |
793 | ␉{ 0x10DE0A6C,␉"NVS 3100M" },␊ |
794 | ␉{ 0x10DE0A6E,␉"GeForce 305M" },␊ |
795 | ␉{ 0x10DE0A6F,␉"ION" },␉␊ |
796 | ␉// 0A70 - 0A7F␊ |
797 | ␉{ 0x10DE0A70,␉"GeForce 310M" },␊ |
798 | ␉{ 0x10DE0A71,␉"GeForce 305M" },␊ |
799 | ␉{ 0x10DE0A72,␉"GeForce 310M" },␊ |
800 | ␉{ 0x10DE0A73,␉"GeForce 305M" },␊ |
801 | ␉{ 0x10DE0A74,␉"GeForce G210M" },␊ |
802 | ␉{ 0x10DE0A75,␉"GeForce G310M" },␊ |
803 | ␉{ 0x10DE0A76,␉"ION" },␊ |
804 | ␉{ 0x10DE0A78,␉"Quadro FX 380 LP" },␊ |
805 | ␉// { 0x10DE0A79,␉"N12M-NS-S" },␊ |
806 | ␉{ 0x10DE0A7A,␉"GeForce 315M" },␊ |
807 | ␉{ 0x10DE0A7B,␉"GeForce 505" },␊ |
808 | ␉{ 0x10DE0A7C,␉"Quadro FX 380M" },␊ |
809 | ␉// { 0x10DE0A7D,␉"NVIDIA GT218-ES" },␊ |
810 | ␉// { 0x10DE0A7E,␉"NVIDIA GT218-INT-S" },␊ |
811 | ␉// { 0x10DE0A7F,␉"NVIDIA GT218-INT-B" },␊ |
812 | ␉// 0A80 - 0A8F␊ |
813 | ␉// 0A90 - 0A9F␊ |
814 | ␉// 0AA0 - 0AAF␊ |
815 | ␉// 0AB0 - 0ABF␊ |
816 | ␉// 0AC0 - 0ACF␊ |
817 | ␉// 0AD0 - 0ADF␊ |
818 | ␉// 0AE0 - 0AEF␊ |
819 | ␉// 0AF0 - 0AFF␊ |
820 | ␉// 0B00 - 0B0F␊ |
821 | ␉// 0B10 - 0B1F␊ |
822 | ␉// 0B20 - 0B2F␊ |
823 | ␉// 0B30 - 0B3F␊ |
824 | ␉// 0B40 - 0B4F␊ |
825 | ␉// 0B50 - 0B5F␊ |
826 | ␉// 0B60 - 0B6F␊ |
827 | ␉// 0B70 - 0B7F␊ |
828 | ␉// 0B80 - 0B8F␊ |
829 | ␉// 0B90 - 0B9F␊ |
830 | ␉// 0BA0 - 0BAF␊ |
831 | ␉// 0BB0 - 0BBF␊ |
832 | ␉// 0BC0 - 0BCF␊ |
833 | ␉// 0BD0 - 0BDF␊ |
834 | ␉// 0BE0 - 0BEF␊ |
835 | ␉// 0BF0 - 0BFF␊ |
836 | ␉// 0C00 - 0C0F␊ |
837 | ␉// 0C10 - 0C1F␊ |
838 | ␉// 0C20 - 0C2F␊ |
839 | ␉// 0C30 - 0C3F␊ |
840 | ␉// 0C40 - 0C4F␊ |
841 | ␉// 0C50 - 0C5F␊ |
842 | ␉// 0C60 - 0C6F␊ |
843 | ␉// 0C70 - 0C7F␊ |
844 | ␉// 0C80 - 0C8F␊ |
845 | ␉// 0C90 - 0C9F␊ |
846 | ␉// 0CA0 - 0CAF␊ |
847 | ␉{ 0x10DE0CA0,␉"GeForce GT 330 " },␊ |
848 | ␉{ 0x10DE0CA2,␉"GeForce GT 320" },␊ |
849 | ␉{ 0x10DE0CA3,␉"GeForce GT 240" },␊ |
850 | ␉{ 0x10DE0CA4,␉"GeForce GT 340" },␊ |
851 | ␉{ 0x10DE0CA5,␉"GeForce GT 220" },␊ |
852 | ␉{ 0x10DE0CA7,␉"GeForce GT 330" },␊ |
853 | ␉{ 0x10DE0CA8,␉"GeForce GTS 260M" },␊ |
854 | ␉{ 0x10DE0CA9,␉"GeForce GTS 250M" },␊ |
855 | ␉{ 0x10DE0CAC,␉"GeForce GT 220" },␊ |
856 | ␉// { 0x10DE0CAD,␉"NVIDIA N10E-ES" },␊ |
857 | ␉// { 0x10DE0CAE,␉"NVIDIA GT215-INT" },␊ |
858 | ␉{ 0x10DE0CAF,␉"GeForce GT 335M" },␊ |
859 | ␉// 0CB0 - 0CBF␉␊ |
860 | ␉{ 0x10DE0CB0,␉"GeForce GTS 350M" },␊ |
861 | ␉{ 0x10DE0CB1,␉"GeForce GTS 360M" },␊ |
862 | ␉{ 0x10DE0CBC,␉"Quadro FX 1800M" },␊ |
863 | ␉// 0CC0 - 0CCF␊ |
864 | ␉// 0CD0 - 0CDF␊ |
865 | ␉// 0CE0 - 0CEF␊ |
866 | ␉// 0CF0 - 0CFF␊ |
867 | ␉// 0D00 - 0D0F␊ |
868 | ␉// 0D10 - 0D1F␊ |
869 | ␉// 0D20 - 0D2F␊ |
870 | ␉// 0D30 - 0D3F␊ |
871 | ␉// 0D40 - 0D4F␊ |
872 | ␉// 0D50 - 0D5F␊ |
873 | ␉// 0D60 - 0D6F␊ |
874 | ␉// 0D70 - 0D7F␊ |
875 | ␉// 0D80 - 0D8F␊ |
876 | ␉// 0D90 - 0D9F␊ |
877 | ␉// 0DA0 - 0DAF␊ |
878 | ␉// 0DB0 - 0DBF␊ |
879 | ␉// 0DC0 - 0DCF␊ |
880 | ␉{ 0x10DE0DC0,␉"GeForce GT 440" },␊ |
881 | ␉// { 0x10DE0DC1,␉"D12-P1-35" },␊ |
882 | ␉// { 0x10DE0DC2,␉"D12-P1-35" },␊ |
883 | ␉{ 0x10DE0DC4,␉"GeForce GTS 450" },␊ |
884 | ␉{ 0x10DE0DC5,␉"GeForce GTS 450" },␊ |
885 | ␉{ 0x10DE0DC6,␉"GeForce GTS 450" },␊ |
886 | ␉// { 0x10DE0DCA,␉"GF10x" },␊ |
887 | ␉// { 0x10DE0DCC,␉"N12E-GS" },␊ |
888 | ␉{ 0x10DE0DCD,␉"GeForce GT 555M" },␊ |
889 | ␉{ 0x10DE0DCE,␉"GeForce GT 555M" },␊ |
890 | ␉// { 0x10DE0DCF,␉"N12P-GT-B" },␊ |
891 | ␉// 0DD0 - 0DDF␉␊ |
892 | ␉// { 0x10DE0DD0,␉"N11E-GT" },␊ |
893 | ␉{ 0x10DE0DD1,␉"GeForce GTX 460M" },␊ |
894 | ␉{ 0x10DE0DD2,␉"GeForce GT 445M" },␊ |
895 | ␉{ 0x10DE0DD3,␉"GeForce GT 435M" },␊ |
896 | ␉{ 0x10DE0DD6,␉"GeForce GT 550M" },␊ |
897 | ␉{ 0x10DE0DD8,␉"Quadro 2000" },␊ |
898 | ␉{ 0x10DE0DDA,␉"Quadro 2000M" },␊ |
899 | ␉// { 0x10DE0DDE,␉"GF106-ES" },␊ |
900 | ␉// { 0x10DE0DDF,␉"GF106-INT" },␊ |
901 | ␉// 0DE0 - 0DEF␊ |
902 | ␉{ 0x10DE0DE0,␉"GeForce GT 440" },␊ |
903 | ␉{ 0x10DE0DE1,␉"GeForce GT 430" },␊ |
904 | ␉{ 0x10DE0DE2,␉"GeForce GT 420" },␊ |
905 | ␉{ 0x10DE0DE4,␉"GeForce GT 520" },␊ |
906 | ␉{ 0x10DE0DE5,␉"GeForce GT 530" },␊ |
907 | ␉{ 0x10DE0DE8,␉"GeForce GT 620M" },␊ |
908 | ␉{ 0x10DE0DE9,␉"GeForce GT 630M" },␊ |
909 | ␉{ 0x10DE0DEA,␉"GeForce GT 610M" },␊ |
910 | ␉{ 0x10DE0DEB,␉"GeForce GT 555M" },␊ |
911 | ␉{ 0x10DE0DEC,␉"GeForce GT 525M" },␊ |
912 | ␉{ 0x10DE0DED,␉"GeForce GT 520M" },␊ |
913 | ␉{ 0x10DE0DEE,␉"GeForce GT 415M" },␊ |
914 | ␉// { 0x10DE0DEF,␉"N13P-NS1-A1" },␊ |
915 | ␉// 0DF0 - 0DFF␉␊ |
916 | ␉{ 0x10DE0DF0,␉"GeForce GT 425M" },␊ |
917 | ␉{ 0x10DE0DF1,␉"GeForce GT 420M" },␊ |
918 | ␉{ 0x10DE0DF2,␉"GeForce GT 435M" },␊ |
919 | ␉{ 0x10DE0DF3,␉"GeForce GT 420M" },␊ |
920 | ␉{ 0x10DE0DF4,␉"GeForce GT 540M" },␊ |
921 | ␉{ 0x10DE0DF5,␉"GeForce GT 525M" },␊ |
922 | ␉{ 0x10DE0DF6,␉"GeForce GT 550M" },␊ |
923 | ␉{ 0x10DE0DF7,␉"GeForce GT 520M" },␊ |
924 | ␉{ 0x10DE0DF8,␉"Quadro 600" },␊ |
925 | ␉{ 0x10DE0DF9,␉"Quadro 500M" },␊ |
926 | ␉{ 0x10DE0DFA,␉"Quadro 1000M" },␊ |
927 | ␉{ 0x10DE0DFC,␉"NVS 5200M" },␊ |
928 | ␉// { 0x10DE0DFE,␉"GF108 ES" },␊ |
929 | ␉// { 0x10DE0DFF,␉"GF108 INT" },␊ |
930 | ␉// 0E00 - 0E0F␊ |
931 | ␉// 0E10 - 0E1F␊ |
932 | ␉// 0E20 - 0E2F␊ |
933 | ␉{ 0x10DE0E21,␉"D12U-25" },␊ |
934 | ␉{ 0x10DE0E22,␉"GeForce GTX 460" },␊ |
935 | ␉{ 0x10DE0E23,␉"GeForce GTX 460 SE" },␊ |
936 | ␉{ 0x10DE0E24,␉"GeForce GTX 460" },␊ |
937 | ␉// { 0x10DE0E25,␉"D12U-50" },␊ |
938 | ␉{ 0x10DE0E28,␉"GeForce GTX 460" },␊ |
939 | ␉// 0E30 - 0E3F␊ |
940 | ␉{ 0x10DE0E30,␉"GeForce GTX 470M" },␊ |
941 | ␉{ 0x10DE0E31,␉"GeForce GTX 485M" },␊ |
942 | ␉// { 0x10DE0E32,␉"N12E-GT" },␊ |
943 | ␉{ 0x10DE0E38,␉"GF104GL" },␊ |
944 | ␉{ 0x10DE0E3A,␉"Quadro 3000M" },␊ |
945 | ␉{ 0x10DE0E3B,␉"Quadro 4000M" },␊ |
946 | ␉// { 0x10DE0E3E,␉"GF104-ES" },␊ |
947 | ␉// { 0x10DE0E3F,␉"GF104-INT" },␊ |
948 | ␉// 0E40 - 0E4F␊ |
949 | ␉// 0E50 - 0E5F␊ |
950 | ␉// 0E60 - 0E6F␊ |
951 | ␉// 0E70 - 0E7F␊ |
952 | ␉// 0E80 - 0E8F␊ |
953 | ␉// 0E90 - 0E9F␊ |
954 | ␉// 0EA0 - 0EAF␊ |
955 | ␉// 0EB0 - 0EBF␊ |
956 | ␉// 0EC0 - 0ECF␊ |
957 | ␉// 0ED0 - 0EDF␊ |
958 | ␉// 0EE0 - 0EEF␊ |
959 | ␉// 0EF0 - 0EFF␊ |
960 | ␉// 0F00 - 0F0F␊ |
961 | ␉// 0F10 - 0F1F␊ |
962 | ␉// 0F20 - 0F2F␊ |
963 | ␉// 0F30 - 0F3F␊ |
964 | ␉// 0F40 - 0F4F␊ |
965 | ␉// 0F50 - 0F5F␊ |
966 | ␉// 0F60 - 0F6F␊ |
967 | ␉// 0F70 - 0F7F␊ |
968 | ␉// 0F80 - 0F8F␊ |
969 | ␉// 0F90 - 0F9F␊ |
970 | ␉// 0FA0 - 0FAF␊ |
971 | ␉// 0FB0 - 0FBF␊ |
972 | ␉// 0FC0 - 0FCF␊ |
973 | ␉// 0FD0 - 0FDF␊ |
974 | ␉{ 0x10DE0FD1,␉"GeForce GT 650M" },␊ |
975 | ␉{ 0x10DE0FD2,␉"GeForce GT 640M" },␊ |
976 | ␉{ 0x10DE0FD4,␉"GeForce GTX 660M" },␊ |
977 | ␉// { 0x10DE0FDB,␉"GK107-ESP-A1" },␊ |
978 | ␉// 0FE0 - 0FEF␊ |
979 | ␉// 0FF0 - 0FFF␊ |
980 | ␉// 1000 - 100F␊ |
981 | ␉// 1010 - 101F␊ |
982 | ␉// 1020 - 102F␊ |
983 | ␉// 1030 - 103F␊ |
984 | ␉// 1040 - 104F␊ |
985 | ␉{ 0x10DE1040,␉"GeForce GT 520" },␊ |
986 | ␉// { 0x10DE1041,␉"D13M1-45" },␊ |
987 | ␉{ 0x10DE1042,␉"GeForce 510" },␊ |
988 | ␉{ 0x10DE1048,␉"GeForce 605" },␊ |
989 | ␉{ 0x10DE1049,␉"GeForce GT 620" },␊ |
990 | ␉// 1050 - 105F␊ |
991 | ␉{ 0x10DE1050,␉"GeForce GT 520M" },␊ |
992 | ␉{ 0x10DE1051,␉"GeForce GT 520MX" },␊ |
993 | ␉{ 0x10DE1052,␉"GeForce GT 520M" },␊ |
994 | ␉{ 0x10DE1054,␉"GeForce GT 410M" },␊ |
995 | ␉{ 0x10DE1055,␉"GeForce 410M" },␊ |
996 | ␉{ 0x10DE1056,␉"Quadro NVS 4200M" },␊ |
997 | ␉{ 0x10DE1057,␉"Quadro NVS 4200M" },␊ |
998 | ␉{ 0x10DE1058,␉"GeForce 610M" },␊ |
999 | ␉{ 0x10DE1059,␉"GeForce 610M" },␊ |
1000 | ␉{ 0x10DE105A,␉"GeForce 610M" },␊ |
1001 | ␉// 1060 - 106F␊ |
1002 | ␉// 1070 - 107F␊ |
1003 | ␉// { 0x10DE107D,␉"GF119" },␊ |
1004 | ␉// { 0x10DE107E,␉"GF119-INT" },␊ |
1005 | ␉// { 0x10DE107F,␉"GF119-ES" },␊ |
1006 | ␉// 1080 - 108F␊ |
1007 | ␉{ 0x10DE1080,␉"GeForce GTX 580" },␊ |
1008 | ␉{ 0x10DE1081,␉"GeForce GTX 570" },␊ |
1009 | ␉{ 0x10DE1082,␉"GeForce GTX 560 Ti" },␊ |
1010 | ␉{ 0x10DE1083,␉"D13U" },␊ |
1011 | ␉{ 0x10DE1084,␉"GeForce GTX 560" },␊ |
1012 | ␉{ 0x10DE1086,␉"GeForce GTX 570" },␊ |
1013 | ␉{ 0x10DE1087,␉"GeForce GTX 560 Ti-448" },␊ |
1014 | ␉{ 0x10DE1088,␉"GeForce GTX 590" },␊ |
1015 | ␉{ 0x10DE1089,␉"GeForce GTX 580" },␊ |
1016 | ␉{ 0x10DE108B,␉"GeForce GTX 590" },␊ |
1017 | ␉// { 0x10DE108C,␉"D13U" },␊ |
1018 | ␉{ 0x10DE108E,␉"Tesla C2090" },␊ |
1019 | ␉// 1090 - 109F␊ |
1020 | ␉{ 0x10DE1091,␉"Tesla M2090" },␊ |
1021 | ␉{ 0x10DE1094,␉"Tesla M2075 Dual-Slot Computing Processor Module" },␊ |
1022 | ␉{ 0x10DE1096,␉"Tesla C2075" },␊ |
1023 | ␉// { 0x10DE1098,␉"D13U" },␊ |
1024 | ␉{ 0x10DE109A,␉"Quadro 5010M" },␊ |
1025 | ␉{ 0x10DE109B,␉"Quadro 7000" },␊ |
1026 | ␉// 10A0 - 10AF␊ |
1027 | ␉// 10B0 - 10BF␊ |
1028 | ␉// 10C0 - 10CF␊ |
1029 | ␉{ 0x10DE10C0,␉"GeForce 9300 GS" },␊ |
1030 | ␉{ 0x10DE10C3,␉"GeForce 8400 GS" },␊ |
1031 | ␉{ 0x10DE10C4,␉"NVIDIA ION" },␊ |
1032 | ␉{ 0x10DE10C5,␉"GeForce 405" },␊ |
1033 | ␉// 10D0 - 10DF␊ |
1034 | ␉{ 0x10DE10D8,␉"NVS 300" },␊ |
1035 | ␉// 10E0 - 10EF␊ |
1036 | ␉// 10F0 - 10FF␊ |
1037 | ␉// 1100 - 110F␊ |
1038 | ␉// 1110 - 111F␊ |
1039 | ␉// 1120 - 112F␊ |
1040 | ␉// 1130 - 113F␊ |
1041 | ␉// 1140 - 114F␊ |
1042 | ␉// { 0x10DE1140,␉"GF117" },␊ |
1043 | ␉{ 0x10DE1141,␉"GeForce 610M" },␊ |
1044 | ␉{ 0x10DE1142,␉"GeForce 620M" },␊ |
1045 | ␉// { 0x10DE1143,␉"N13P-GV" },␊ |
1046 | ␉// { 0x10DE1144,␉"GF117" },␊ |
1047 | ␉// { 0x10DE1145,␉"GF117" },␊ |
1048 | ␉// { 0x10DE1146,␉"GF117" },␊ |
1049 | ␉// { 0x10DE1147,␉"GF117" },␊ |
1050 | ␉// { 0x10DE1149,␉"GF117-ES" },␊ |
1051 | ␉// { 0x10DE114A,␉"GF117-INT" },␊ |
1052 | ␉// { 0x10DE114B,␉"PCI-GEN3-B" },␊ |
1053 | ␉// 1150 - 115F␊ |
1054 | ␉// 1160 - 116F␊ |
1055 | ␉// 1170 - 117F␊ |
1056 | ␉// 1180 - 118F␊ |
1057 | ␉{ 0x10DE1180,␉"GeForce GTX 680" },␊ |
1058 | ␉{ 0x10DE1188,␉"GeForce GTX 690" }␊ |
1059 | ␉{ 0x10DE1189,␉"GeForce GTX 670" }␊ |
1060 | ␉// 1190 - 119F␊ |
1061 | ␉// 11A0 - 11AF␊ |
1062 | ␉// 11B0 - 11BF␊ |
1063 | ␉// 11C0 - 11CF␊ |
1064 | ␉// 11D0 - 11DF␊ |
1065 | ␉// 11E0 - 11EF␊ |
1066 | ␉// 11F0 - 11FF␊ |
1067 | ␉// 1200 - 120F␊ |
1068 | ␉{ 0x10DE1200,␉"GeForce GTX 560 Ti" },␊ |
1069 | ␉{ 0x10DE1201,␉"GeForce GTX 560" },␊ |
1070 | ␉{ 0x10DE1202,␉"GeForce GTX 560 Ti" },␊ |
1071 | ␉{ 0x10DE1203,␉"GeForce GTX 460 SE v2" },␊ |
1072 | ␉{ 0x10DE1205,␉"GeForce GTX 460 v2" },␊ |
1073 | ␉{ 0x10DE1206,␉"GeForce GTX 555" },␊ |
1074 | ␉{ 0x10DE1208,␉"GeForce GTX 560 SE" },␊ |
1075 | ␉{ 0x10DE1210,␉"GeForce GTX 570M" },␊ |
1076 | ␉{ 0x10DE1211,␉"GeForce GTX 580M" },␊ |
1077 | ␉{ 0x10DE1212,␉"GeForce GTX 675M" },␊ |
1078 | ␉{ 0x10DE1213,␉"GeForce GTX 670M" },␊ |
1079 | ␉{ 0x10DE1240,␉"GeForce GT 620M" },␊ |
1080 | ␉{ 0x10DE1241,␉"GeForce GT 545" },␊ |
1081 | ␉{ 0x10DE1243,␉"GeForce GT 545" },␊ |
1082 | ␉{ 0x10DE1244,␉"GeForce GTX 550 Ti" },␊ |
1083 | ␉{ 0x10DE1245,␉"GeForce GTS 450" },␊ |
1084 | ␉{ 0x10DE1246,␉"GeForce GTX 550M" },␊ |
1085 | ␉{ 0x10DE1247,␉"GeForce GT 635M" }, // Subsystem Id: 1043 212C Asus GeForce GT 635M␊ |
1086 | ␉{ 0x10DE1248,␉"GeForce GTX 555M" },␊ |
1087 | ␉{ 0x10DE124B,␉"GeForce GT 640" },␊ |
1088 | ␉{ 0x10DE124D,␉"GeForce GTX 555M" },␊ |
1089 | ␉// { 0x10DE1250,␉"GF116-INT" },␊ |
1090 | ␉{ 0x10DE1251,␉"GeForce GTX 560M" },␊ |
1091 | ␉// 1260 - 126F␊ |
1092 | ␉// 1270 - 127F␊ |
1093 | ␉// 1280 - 128F␊ |
1094 | ␉// 1290 - 129F␊ |
1095 | ␉// 12A0 - 12AF␊ |
1096 | ␉// 12B0 - 12BF␊ |
1097 | ␉// 12C0 - 12CF␊ |
1098 | ␉// 12D0 - 12DF␊ |
1099 | ␉// 12E0 - 12EF␊ |
1100 | ␉// 12F0 - 12FF␊ |
1101 | };␊ |
1102 | ␊ |
1103 | #define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))␊ |
1104 | #define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))␊ |
1105 | #define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))␊ |
1106 | #define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))␊ |
1107 | #define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))␊ |
1108 | ␊ |
1109 | static int patch_nvidia_rom(uint8_t *rom)␊ |
1110 | {␊ |
1111 | ␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊ |
1112 | ␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊ |
1113 | ␉␉return PATCH_ROM_FAILED;␊ |
1114 | ␉}␊ |
1115 | ␉␊ |
1116 | ␉uint16_t dcbptr = READ_LE_SHORT(rom, 0x36);␊ |
1117 | ␊ |
1118 | ␉if (!dcbptr) {␊ |
1119 | ␉␉printf("no dcb table found\n");␊ |
1120 | ␉␉return PATCH_ROM_FAILED;␊ |
1121 | ␉}␊ |
1122 | ␉else␊ |
1123 | ␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊ |
1124 | ␊ |
1125 | ␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊ |
1126 | ␉uint8_t dcbtable_version = dcbtable[0];␊ |
1127 | ␉uint8_t headerlength␉ = 0;␊ |
1128 | ␉uint8_t numentries␉␉ = 0;␊ |
1129 | ␉uint8_t recordlength␉ = 0;␊ |
1130 | ␉␊ |
1131 | ␉if (dcbtable_version >= 0x20)␊ |
1132 | ␉{␊ |
1133 | ␉␉uint32_t sig;␊ |
1134 | ␉␉␊ |
1135 | ␉␉if (dcbtable_version >= 0x30)␊ |
1136 | ␉␉{␊ |
1137 | ␉␉␉headerlength = dcbtable[1];␊ |
1138 | ␉␉␉numentries␉ = dcbtable[2];␊ |
1139 | ␉␉␉recordlength = dcbtable[3];␊ |
1140 | ␊ |
1141 | ␉␉␉sig = READ_LE_INT(dcbtable, 6);␊ |
1142 | ␉␉}␊ |
1143 | ␉␉else␊ |
1144 | ␉␉{␊ |
1145 | ␉␉␉sig = READ_LE_INT(dcbtable, 4);␊ |
1146 | ␉␉␉headerlength = 8;␊ |
1147 | ␉␉}␊ |
1148 | ␉␉␊ |
1149 | ␉␉if (sig != 0x4edcbdcb)␊ |
1150 | ␉␉{␊ |
1151 | ␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊ |
1152 | ␉␉␉return PATCH_ROM_FAILED;␊ |
1153 | ␉␉}␊ |
1154 | ␉}␊ |
1155 | ␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊ |
1156 | ␉{␊ |
1157 | ␉␉char sig[8] = { 0 };␊ |
1158 | ␉␉␊ |
1159 | ␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊ |
1160 | ␉␉recordlength = 10;␊ |
1161 | ␉␉␊ |
1162 | ␉␉if (strcmp(sig, "DEV_REC"))␊ |
1163 | ␉␉{␊ |
1164 | ␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊ |
1165 | ␉␉␉return PATCH_ROM_FAILED;␊ |
1166 | ␉␉}␊ |
1167 | ␉}␊ |
1168 | ␉else␊ |
1169 | ␉{␊ |
1170 | ␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊ |
1171 | ␉␉return PATCH_ROM_FAILED;␊ |
1172 | ␉}␊ |
1173 | ␉␊ |
1174 | ␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊ |
1175 | ␉␉numentries = MAX_NUM_DCB_ENTRIES;␊ |
1176 | ␉␊ |
1177 | ␉uint8_t num_outputs = 0, i = 0;␊ |
1178 | ␉␊ |
1179 | ␉struct dcbentry␊ |
1180 | ␉{␊ |
1181 | ␉␉uint8_t type;␊ |
1182 | ␉␉uint8_t index;␊ |
1183 | ␉␉uint8_t *heads;␊ |
1184 | ␉} entries[numentries];␊ |
1185 | ␉␊ |
1186 | ␉for (i = 0; i < numentries; i++)␊ |
1187 | ␉{␊ |
1188 | ␉␉uint32_t connection;␊ |
1189 | ␉␉connection = READ_LE_INT(dcbtable,headerlength + recordlength * i);␊ |
1190 | ␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊ |
1191 | ␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊ |
1192 | ␉␉␉continue;␊ |
1193 | ␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊ |
1194 | ␉␉␉continue;␊ |
1195 | ␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊ |
1196 | ␉␉␉continue;␊ |
1197 | ␉␉␊ |
1198 | ␉␉entries[num_outputs].type = connection & 0xf;␊ |
1199 | ␉␉entries[num_outputs].index = num_outputs;␊ |
1200 | ␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊ |
1201 | ␉}␊ |
1202 | ␉␊ |
1203 | ␉int has_lvds = false;␊ |
1204 | ␉uint8_t channel1 = 0, channel2 = 0;␊ |
1205 | ␉␊ |
1206 | ␉for (i = 0; i < num_outputs; i++)␊ |
1207 | ␉{␊ |
1208 | ␉␉if (entries[i].type == 3)␊ |
1209 | ␉␉{␊ |
1210 | ␉␉␉has_lvds = true;␊ |
1211 | ␉␉␉//printf("found LVDS\n");␊ |
1212 | ␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
1213 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1214 | ␉␉}␊ |
1215 | ␉}␊ |
1216 | ␉␊ |
1217 | ␉// if we have a LVDS output, we group the rest to the second channel␊ |
1218 | ␉if (has_lvds)␊ |
1219 | ␉{␊ |
1220 | ␉␉for (i = 0; i < num_outputs; i++)␊ |
1221 | ␉␉{␊ |
1222 | ␉␉␉if (entries[i].type == TYPE_GROUPED)␊ |
1223 | ␉␉␉␉continue;␊ |
1224 | ␉␉␉␊ |
1225 | ␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
1226 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1227 | ␉␉}␊ |
1228 | ␉}␊ |
1229 | ␉else␊ |
1230 | ␉{␊ |
1231 | ␉␉int x;␊ |
1232 | ␉␉// we loop twice as we need to generate two channels␊ |
1233 | ␉␉for (x = 0; x <= 1; x++)␊ |
1234 | ␉␉{␊ |
1235 | ␉␉␉for (i=0; i<num_outputs; i++)␊ |
1236 | ␉␉␉{␊ |
1237 | ␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊ |
1238 | ␉␉␉␉␉continue;␊ |
1239 | ␉␉␉␉// if type is TMDS, the prior output is ANALOG␊ |
1240 | ␉␉␉␉// we always group ANALOG and TMDS␊ |
1241 | ␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊ |
1242 | ␉␉␉␉if (i && entries[i].type == 0x2)␊ |
1243 | ␉␉␉␉{␊ |
1244 | ␉␉␉␉␉switch (x)␊ |
1245 | ␉␉␉␉␉{␊ |
1246 | ␉␉␉␉␉␉case 0:␊ |
1247 | ␉␉␉␉␉␉␉//printf("group channel 1\n");␊ |
1248 | ␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
1249 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1250 | ␉␉␉␉␉␉␉␊ |
1251 | ␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊ |
1252 | ␉␉␉␉␉␉␉{␊ |
1253 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊ |
1254 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
1255 | ␉␉␉␉␉␉␉}␊ |
1256 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
1257 | ␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊ |
1258 | ␉␉␉␉␉␉␉{␊ |
1259 | ␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊ |
1260 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊ |
1261 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
1262 | ␉␉␉␉␉␉␉}␊ |
1263 | ␉␉␉␉␉␉␉break;␊ |
1264 | ␉␉␉␉␉␉␊ |
1265 | ␉␉␉␉␉␉case 1:␊ |
1266 | ␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊ |
1267 | ␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
1268 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1269 | ␉␉␉␉␉␉␉␊ |
1270 | ␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊ |
1271 | ␉␉␉␉␉␉␉{␊ |
1272 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊ |
1273 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
1274 | ␉␉␉␉␉␉␉}␊ |
1275 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
1276 | ␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊ |
1277 | ␉␉␉␉␉␉␉{␊ |
1278 | ␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊ |
1279 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊ |
1280 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
1281 | ␉␉␉␉␉␉␉}␊ |
1282 | ␉␉␉␉␉␉␉break;␊ |
1283 | ␉␉␉␉␉}␊ |
1284 | ␉␉␉␉␉break;␊ |
1285 | ␉␉␉␉}␊ |
1286 | ␉␉␉}␊ |
1287 | ␉␉}␊ |
1288 | ␉}␊ |
1289 | ␉␊ |
1290 | ␉// if we have left ungrouped outputs merge them to the empty channel␊ |
1291 | ␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊ |
1292 | ␉togroup = &channel2;␊ |
1293 | ␉␊ |
1294 | ␉for (i = 0; i < num_outputs; i++)␊ |
1295 | ␉{␊ |
1296 | ␉␉if (entries[i].type != TYPE_GROUPED)␊ |
1297 | ␉␉{␊ |
1298 | ␉␉␉//printf("%d not grouped\n", i);␊ |
1299 | ␉␉␉if (togroup)␊ |
1300 | ␉␉␉{␊ |
1301 | ␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊ |
1302 | ␉␉␉}␊ |
1303 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1304 | ␉␉}␊ |
1305 | ␉}␊ |
1306 | ␉␊ |
1307 | ␉if (channel1 > channel2)␊ |
1308 | ␉{␊ |
1309 | ␉␉uint8_t buff = channel1;␊ |
1310 | ␉␉channel1 = channel2;␊ |
1311 | ␉␉channel2 = buff;␊ |
1312 | ␉}␊ |
1313 | ␉␊ |
1314 | ␉default_NVCAP[6] = channel1;␊ |
1315 | ␉default_NVCAP[8] = channel2;␊ |
1316 | ␉␊ |
1317 | ␉// patching HEADS␊ |
1318 | ␉for (i = 0; i < num_outputs; i++)␊ |
1319 | ␉{␊ |
1320 | ␉␉if (channel1 & (1 << i))␊ |
1321 | ␉␉{␊ |
1322 | ␉␉␉*entries[i].heads = 1;␊ |
1323 | ␉␉}␊ |
1324 | ␉␉else if(channel2 & (1 << i))␊ |
1325 | ␉␉{␊ |
1326 | ␉␉␉*entries[i].heads = 2;␊ |
1327 | ␉␉}␊ |
1328 | ␉}␊ |
1329 | ␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊ |
1330 | }␊ |
1331 | ␊ |
1332 | static char *get_nvidia_model(uint32_t id)␊ |
1333 | {␊ |
1334 | ␉int i;␊ |
1335 | ␉␊ |
1336 | ␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++)␊ |
1337 | ␉{␊ |
1338 | ␉␉if (NVKnownChipsets[i].device == id)␊ |
1339 | ␉␉{␊ |
1340 | ␉␉␉return NVKnownChipsets[i].name;␊ |
1341 | ␉␉}␊ |
1342 | ␉}␊ |
1343 | ␉return NVKnownChipsets[0].name;␊ |
1344 | }␊ |
1345 | ␊ |
1346 | static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊ |
1347 | {␊ |
1348 | ␉int fd;␊ |
1349 | ␉int size;␊ |
1350 | ␉␊ |
1351 | ␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊ |
1352 | ␉{␊ |
1353 | ␉␉return 0;␊ |
1354 | ␉}␊ |
1355 | ␉␊ |
1356 | ␉size = file_size(fd);␊ |
1357 | ␉␊ |
1358 | ␉if (size > bufsize)␊ |
1359 | ␉{␊ |
1360 | ␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊ |
1361 | ␉␉␉␉filename, bufsize);␊ |
1362 | ␉␉size = bufsize;␊ |
1363 | ␉}␊ |
1364 | ␉size = read(fd, (char *)buf, size);␊ |
1365 | ␉close(fd);␊ |
1366 | ␉␊ |
1367 | ␉return size > 0 ? size : 0;␊ |
1368 | }␊ |
1369 | ␊ |
1370 | static int devprop_add_nvidia_template(struct DevPropDevice *device)␊ |
1371 | {␊ |
1372 | ␉char tmp[16];␊ |
1373 | ␉␊ |
1374 | ␉if (!device)␊ |
1375 | ␉␉return 0;␊ |
1376 | ␉␊ |
1377 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊ |
1378 | ␉␉return 0;␊ |
1379 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊ |
1380 | ␉␉return 0;␊ |
1381 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊ |
1382 | ␉␉return 0;␊ |
1383 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊ |
1384 | ␉␉return 0;␊ |
1385 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊ |
1386 | ␉␉return 0;␊ |
1387 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊ |
1388 | ␉␉return 0;␊ |
1389 | ␉if (devices_number == 1)␊ |
1390 | ␉{␊ |
1391 | ␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊ |
1392 | ␉␉ return 0;␊ |
1393 | ␉}␊ |
1394 | ␉else␊ |
1395 | ␉{␊ |
1396 | ␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊ |
1397 | ␉␉ return 0;␊ |
1398 | ␉}␊ |
1399 | ␊ |
1400 | ␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊ |
1401 | ␉// len = sprintf(tmp, "Slot-%x", devices_number);␊ |
1402 | ␉sprintf(tmp, "Slot-%x",devices_number);␊ |
1403 | ␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊ |
1404 | ␉devices_number++;␊ |
1405 | ␉␊ |
1406 | ␉return 1;␊ |
1407 | }␊ |
1408 | ␊ |
1409 | int hex2bin(const char *hex, uint8_t *bin, int len)␊ |
1410 | {␊ |
1411 | ␉char␉*p;␊ |
1412 | ␉int␉␉i;␊ |
1413 | ␉char␉buf[3];␊ |
1414 | ␉␊ |
1415 | ␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊ |
1416 | ␉␉printf("[ERROR] bin2hex input error\n");␊ |
1417 | ␉␉return -1;␊ |
1418 | ␉}␊ |
1419 | ␉␊ |
1420 | ␉buf[2] = '\0';␊ |
1421 | ␉p = (char *) hex;␊ |
1422 | ␉␊ |
1423 | ␉for (i = 0; i < len; i++)␊ |
1424 | ␉{␊ |
1425 | ␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊ |
1426 | ␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊ |
1427 | ␉␉␉return -2;␊ |
1428 | ␉␉}␊ |
1429 | ␉␉buf[0] = *p++;␊ |
1430 | ␉␉buf[1] = *p++;␊ |
1431 | ␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊ |
1432 | ␉}␊ |
1433 | ␉return 0;␊ |
1434 | }␊ |
1435 | ␊ |
1436 | unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊ |
1437 | {␊ |
1438 | ␉unsigned long long vram_size = 0;␊ |
1439 | ␉␊ |
1440 | ␉if (nvCardType < NV_ARCH_50)␊ |
1441 | ␉{␊ |
1442 | ␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
1443 | ␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊ |
1444 | ␉}␊ |
1445 | ␉else if (nvCardType < NV_ARCH_C0)␊ |
1446 | ␉{␊ |
1447 | ␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
1448 | ␉␉vram_size |= (vram_size & 0xff) << 32;␊ |
1449 | ␉␉vram_size &= 0xffffffff00ll;␊ |
1450 | ␉}␊ |
1451 | ␉else // >= NV_ARCH_C0␊ |
1452 | ␉{␊ |
1453 | ␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊ |
1454 | ␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊ |
1455 | ␉}␊ |
1456 | ␉␊ |
1457 | ␉// Workaround for 9600M GT, GT 210/420/430/440/525M/540M & GTX 560M␊ |
1458 | ␉switch (nvda_dev->device_id)␊ |
1459 | ␉{␊ |
1460 | ␉␉case 0x0647: vram_size = 512*1024*1024; break;␉// 9600M GT 0647␊ |
1461 | ␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT 0649␊ |
1462 | ␉␉case 0x0A65: vram_size = 1024*1024*1024; break; // GT 210␊ |
1463 | ␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊ |
1464 | ␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊ |
1465 | ␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊ |
1466 | ␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M 0DEC␊ |
1467 | ␉␉case 0x0DF4: vram_size = 1024*1024*1024; break; // GT 540M␊ |
1468 | ␉␉case 0x0DF5: vram_size = 1024*1024*1024; break; // GT 525M 0DF5␊ |
1469 | ␉␉case 0x1251: vram_size = 1536*1024*1024; break; // GTX 560M␊ |
1470 | ␉␉default: break;␊ |
1471 | ␉}␊ |
1472 | ␉␊ |
1473 | ␉return vram_size;␊ |
1474 | }␊ |
1475 | ␊ |
1476 | bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊ |
1477 | {␊ |
1478 | ␉struct DevPropDevice␉*device;␊ |
1479 | ␉char␉␉␉␉␉*devicepath;␊ |
1480 | ␉option_rom_pci_header_t *rom_pci_header;␊ |
1481 | ␉volatile uint8_t␉␉*regs;␊ |
1482 | ␉uint8_t␉␉␉␉␉*rom;␊ |
1483 | ␉uint8_t␉␉␉␉␉*nvRom;␊ |
1484 | ␉uint8_t␉␉␉␉␉nvCardType;␊ |
1485 | ␉unsigned long long␉␉videoRam;␊ |
1486 | ␉uint32_t␉␉␉␉nvBiosOveride;␊ |
1487 | ␉uint32_t␉␉␉␉bar[7];␊ |
1488 | ␉uint32_t␉␉␉␉boot_display;␊ |
1489 | ␉int␉␉␉␉␉␉nvPatch;␊ |
1490 | ␉int␉␉␉␉␉␉len;␊ |
1491 | ␉char␉␉␉␉␉biosVersion[32];␊ |
1492 | ␉char␉␉␉␉␉nvFilename[32];␊ |
1493 | ␉char␉␉␉␉␉kNVCAP[12];␊ |
1494 | ␉char␉␉␉␉␉*model;␊ |
1495 | ␉const char␉␉␉␉*value;␊ |
1496 | ␉bool␉␉␉␉␉doit;␊ |
1497 | ␉␊ |
1498 | ␉devicepath = get_pci_dev_path(nvda_dev);␊ |
1499 | ␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊ |
1500 | ␉regs = (uint8_t *) (bar[0] & ~0x0f);␊ |
1501 | ␉␊ |
1502 | ␉// get card type␊ |
1503 | ␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊ |
1504 | ␉␊ |
1505 | ␉// Amount of VRAM in kilobytes␊ |
1506 | ␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊ |
1507 | ␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊ |
1508 | ␉␊ |
1509 | ␉verbose("%s %dMB NV%02x [%04x:%04x]-[%04x:%04x] :: %s device number: %d\n",␊ |
1510 | ␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊ |
1511 | ␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊ |
1512 | ␉␉␉nvda_dev->subsys_id.subsys.vendor_id, nvda_dev->subsys_id.subsys.device_id,␊ |
1513 | ␉␉␉devicepath, devices_number);␊ |
1514 | ␉␊ |
1515 | ␉rom = malloc(NVIDIA_ROM_SIZE);␊ |
1516 | ␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊ |
1517 | ␉␉␉(uint16_t)nvda_dev->device_id);␊ |
1518 | ␉␊ |
1519 | ␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊ |
1520 | ␉{␊ |
1521 | ␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊ |
1522 | ␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊ |
1523 | ␉␉␊ |
1524 | ␉␉if (nvBiosOveride > 0)␊ |
1525 | ␉␉{␊ |
1526 | ␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊ |
1527 | ␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊ |
1528 | ␉␉}␊ |
1529 | ␉␉else␊ |
1530 | ␉␉{␊ |
1531 | ␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊ |
1532 | ␉␉␉return false;␊ |
1533 | ␉␉}␊ |
1534 | ␉}␊ |
1535 | ␉else␊ |
1536 | ␉{␊ |
1537 | ␉␉// Otherwise read bios from card␊ |
1538 | ␉␉nvBiosOveride = 0;␊ |
1539 | ␉␉␊ |
1540 | ␉␉// TODO: we should really check for the signature before copying the rom, i think.␊ |
1541 | ␉␉␊ |
1542 | ␉␉// PRAMIN first␊ |
1543 | ␊ |
1544 | // PROM next␊ |
1545 | // Enable PROM access␊ |
1546 | (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊ |
1547 | ␊ |
1548 | nvRom = (uint8_t*)®s[NV_PROM_OFFSET];␊ |
1549 | bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
1550 | ␊ |
1551 | // disable PROM access␊ |
1552 | (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊ |
1553 | ␊ |
1554 | ␉␉// Valid Signature ?␊ |
1555 | ␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊ |
1556 | ␉␉{␊ |
1557 | // PRAMIN first␊ |
1558 | nvRom = (uint8_t*)®s[NV_PRAMIN_OFFSET];␊ |
1559 | bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
1560 | ␊ |
1561 | ␉␉␉// Valid Signature ?␊ |
1562 | ␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊ |
1563 | ␉␉␉{␊ |
1564 | ␉␉␉␉// 0xC0000 last␊ |
1565 | ␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊ |
1566 | ␉␉␉␉␊ |
1567 | ␉␉␉␉// Valid Signature ?␊ |
1568 | ␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊ |
1569 | ␉␉␉␉{␊ |
1570 | ␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊ |
1571 | ␉␉␉␉␉return false;␊ |
1572 | ␉␉␉␉}␊ |
1573 | ␉␉␉␉else␊ |
1574 | ␉␉␉␉{␊ |
1575 | ␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1576 | ␉␉␉␉}␊ |
1577 | ␉␉␉}␊ |
1578 | ␉␉␉else␊ |
1579 | ␉␉␉{␊ |
1580 | ␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1581 | ␉␉␉}␊ |
1582 | ␉␉}␊ |
1583 | ␉␉else␊ |
1584 | ␉␉{␊ |
1585 | ␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1586 | ␉␉}␊ |
1587 | ␉}␊ |
1588 | ␉␊ |
1589 | ␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊ |
1590 | ␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊ |
1591 | ␉␉//return false;␊ |
1592 | ␉}␊ |
1593 | ␉␊ |
1594 | ␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊ |
1595 | ␉␊ |
1596 | ␉// check for 'PCIR' sig␊ |
1597 | ␉if (rom_pci_header->signature == 0x50434952)␊ |
1598 | ␉{␊ |
1599 | ␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊ |
1600 | ␉␉{␊ |
1601 | ␉␉␉// Get Model from the OpROM␊ |
1602 | ␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊ |
1603 | ␉␉}␊ |
1604 | ␉␉else␊ |
1605 | ␉␉{␊ |
1606 | ␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊ |
1607 | ␉␉}␊ |
1608 | ␉}␊ |
1609 | ␉␊ |
1610 | ␉if (!string) {␊ |
1611 | ␉␉string = devprop_create_string();␊ |
1612 | ␉}␊ |
1613 | ␉device = devprop_add_device(string, devicepath);␊ |
1614 | ␉␊ |
1615 | ␉/* FIXME: for primary graphics card only */␊ |
1616 | ␉boot_display = 1;␊ |
1617 | ␉if (devices_number == 1)␊ |
1618 | ␉{␊ |
1619 | ␉ devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊ |
1620 | ␉}␊ |
1621 | ␉␊ |
1622 | ␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊ |
1623 | ␉␉uint8_t built_in = 0x01;␊ |
1624 | ␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊ |
1625 | ␉}␊ |
1626 | ␊ |
1627 | ␉// get bios version␊ |
1628 | ␉const int MAX_BIOS_VERSION_LENGTH = 32;␊ |
1629 | ␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊ |
1630 | ␉␊ |
1631 | ␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊ |
1632 | ␉␊ |
1633 | ␉int i, version_start;␊ |
1634 | ␉int crlf_count = 0;␊ |
1635 | ␉␊ |
1636 | ␉// only search the first 384 bytes␊ |
1637 | ␉for (i = 0; i < 0x180; i++)␊ |
1638 | ␉{␊ |
1639 | ␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊ |
1640 | ␉␉{␊ |
1641 | ␉␉␉crlf_count++;␊ |
1642 | ␉␉␉// second 0x0D0A was found, extract bios version␊ |
1643 | ␉␉␉if (crlf_count == 2)␊ |
1644 | ␉␉␉{␊ |
1645 | ␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊ |
1646 | ␉␉␉␉␊ |
1647 | ␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊ |
1648 | ␉␉␉␉{␊ |
1649 | ␉␉␉␉␉// find start␊ |
1650 | ␉␉␉␉␉if (rom[version_start] == 0x00)␊ |
1651 | ␉␉␉␉␉{␊ |
1652 | ␉␉␉␉␉␉version_start++;␊ |
1653 | ␉␉␉␉␉␉␊ |
1654 | ␉␉␉␉␉␉// strip "Version "␊ |
1655 | ␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊ |
1656 | ␉␉␉␉␉␉{␊ |
1657 | ␉␉␉␉␉␉␉version_start += 8;␊ |
1658 | ␉␉␉␉␉␉}␊ |
1659 | ␉␉␉␉␉␉␊ |
1660 | ␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊ |
1661 | ␉␉␉␉␉␉break;␊ |
1662 | ␉␉␉␉␉}␊ |
1663 | ␉␉␉␉}␊ |
1664 | ␉␉␉␉break;␊ |
1665 | ␉␉␉}␊ |
1666 | ␉␉}␊ |
1667 | ␉}␊ |
1668 | ␉␊ |
1669 | ␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊ |
1670 | ␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊ |
1671 | ␉␊ |
1672 | ␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊ |
1673 | ␉{␊ |
1674 | ␉␉uint8_t new_NVCAP[NVCAP_LEN];␊ |
1675 | ␉␉␊ |
1676 | ␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊ |
1677 | ␉␉{␊ |
1678 | ␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊ |
1679 | ␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊ |
1680 | ␉␉}␊ |
1681 | ␉}␊ |
1682 | ␉␊ |
1683 | ␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊ |
1684 | ␉{␊ |
1685 | ␉␉uint8_t new_dcfg0[DCFG0_LEN];␊ |
1686 | ␉␉␊ |
1687 | ␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊ |
1688 | ␉␉{␊ |
1689 | ␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊ |
1690 | ␉␉␉␊ |
1691 | ␉␉␉verbose("Using user supplied @0,display-cfg\n");␊ |
1692 | ␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊ |
1693 | ␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊ |
1694 | ␉␉}␊ |
1695 | ␉}␊ |
1696 | ␉␊ |
1697 | ␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊ |
1698 | ␉{␊ |
1699 | ␉␉uint8_t new_dcfg1[DCFG1_LEN];␊ |
1700 | ␉␉␊ |
1701 | ␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊ |
1702 | ␉␉{␊ |
1703 | ␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊ |
1704 | ␉␉␉␊ |
1705 | ␉␉␉verbose("Using user supplied @1,display-cfg\n");␊ |
1706 | ␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊ |
1707 | ␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊ |
1708 | ␉␉}␊ |
1709 | ␉}␊ |
1710 | ␉␊ |
1711 | #if DEBUG_NVCAP␊ |
1712 | ␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊ |
1713 | ␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊ |
1714 | ␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊ |
1715 | ␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊ |
1716 | ␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊ |
1717 | ␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊ |
1718 | #endif␊ |
1719 | ␉␊ |
1720 | ␉devprop_add_nvidia_template(device);␊ |
1721 | ␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊ |
1722 | ␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊ |
1723 | ␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊ |
1724 | ␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊ |
1725 | ␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊ |
1726 | //␉devprop_add_value(device, "@1,connector-type", connector_type_1, 4); // fixme␊ |
1727 | //␉devprop_add_value(device, "@0,display-cfg", display_cfg_0, 4);␊ |
1728 | //␉devprop_add_value(device, "@1,display-cfg", display_cfg_1, 4);␊ |
1729 | ␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊ |
1730 | ␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊ |
1731 | ␉␊ |
1732 | ␉//add HDMI Audio back to nvidia␊ |
1733 | ␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊ |
1734 | //␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊ |
1735 | //␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊ |
1736 | ␉//end Nvidia HDMI Audio␊ |
1737 | ␉␊ |
1738 | ␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊ |
1739 | ␉{␊ |
1740 | ␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊ |
1741 | ␉}␊ |
1742 | ␉␊ |
1743 | ␉stringdata = malloc(sizeof(uint8_t) * string->length);␊ |
1744 | ␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊ |
1745 | ␉stringlength = string->length;␊ |
1746 | ␉␊ |
1747 | ␉return true;␊ |
1748 | }␊ |
1749 | |