1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | #include "cpu.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "boot.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␉␉msglog(x)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
24 | */␊ |
25 | static uint64_t measure_tsc_frequency(void)␊ |
26 | {␊ |
27 | ␉uint64_t tscStart;␊ |
28 | ␉uint64_t tscEnd;␊ |
29 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
30 | ␉unsigned long pollCount;␊ |
31 | ␉uint64_t retval = 0;␊ |
32 | ␉int i;␊ |
33 | ␉␊ |
34 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
35 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
36 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
37 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
38 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
39 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
40 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
41 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
42 | ␉ */␊ |
43 | ␉for(i = 0; i < 10; ++i)␊ |
44 | ␉{␊ |
45 | ␉␉enable_PIT2();␊ |
46 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
47 | ␉␉tscStart = rdtsc64();␊ |
48 | ␉␉pollCount = poll_PIT2_gate();␊ |
49 | ␉␉tscEnd = rdtsc64();␊ |
50 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
51 | ␉␉if (pollCount <= 1)␊ |
52 | ␉␉␉continue;␊ |
53 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
54 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
55 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
56 | ␉␉ */␊ |
57 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
58 | ␉␉␉continue;␊ |
59 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
60 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
61 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
62 | ␉}␊ |
63 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
64 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
65 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
66 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
67 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
68 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
69 | ␉ */␊ |
70 | ␉␊ |
71 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
72 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
73 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
74 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
75 | ␉ */␊ |
76 | ␉if (tscDelta > (1ULL<<32))␊ |
77 | ␉␉retval = 0;␊ |
78 | ␉else␊ |
79 | ␉{␊ |
80 | ␉␉retval = tscDelta * 1000 / 30;␊ |
81 | ␉}␊ |
82 | ␉disable_PIT2();␊ |
83 | ␉return retval;␊ |
84 | }␊ |
85 | ␊ |
86 | /*␊ |
87 | * Original comment/code:␊ |
88 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
89 | *␊ |
90 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
91 | * (just a naming change, mperf --> aperf )␊ |
92 | */␊ |
93 | static uint64_t measure_aperf_frequency(void)␊ |
94 | {␊ |
95 | ␉uint64_t aperfStart;␊ |
96 | ␉uint64_t aperfEnd;␊ |
97 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
98 | ␉unsigned long pollCount;␊ |
99 | ␉uint64_t retval = 0;␊ |
100 | ␉int i;␊ |
101 | ␉␊ |
102 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
103 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
104 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
105 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
106 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
107 | ␉ * expire.␊ |
108 | ␉ */␊ |
109 | ␉for(i = 0; i < 10; ++i)␊ |
110 | ␉{␊ |
111 | ␉␉enable_PIT2();␊ |
112 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
113 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
114 | ␉␉pollCount = poll_PIT2_gate();␊ |
115 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
116 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
117 | ␉␉if (pollCount <= 1)␊ |
118 | ␉␉␉continue;␊ |
119 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
120 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
121 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
122 | ␉␉ */␊ |
123 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
124 | ␉␉␉continue;␊ |
125 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
126 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
127 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
128 | ␉}␊ |
129 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
130 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
131 | ␉ */␊ |
132 | ␉␊ |
133 | ␉if (aperfDelta > (1ULL<<32))␊ |
134 | ␉␉retval = 0;␊ |
135 | ␉else␊ |
136 | ␉{␊ |
137 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
138 | ␉}␊ |
139 | ␉disable_PIT2();␊ |
140 | ␉return retval;␊ |
141 | }␊ |
142 | ␊ |
143 | /*␊ |
144 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
145 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
146 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
147 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
148 | * - fsbFrequency = tscFrequency / multi␊ |
149 | * - cpuFrequency = fsbFrequency * multi␊ |
150 | */␊ |
151 | void scan_cpu(PlatformInfo_t *p)␊ |
152 | {␊ |
153 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊ |
154 | ␉uint64_t␉msr, flex_ratio;␊ |
155 | ␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊ |
156 | ␉const char␉*newratio;␊ |
157 | ␉int␉␉␉len, myfsb;␊ |
158 | ␉uint8_t␉␉bus_ratio_min;␊ |
159 | ␉uint32_t␉max_ratio, min_ratio;␊ |
160 | ␉␊ |
161 | ␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊ |
162 | ␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊ |
163 | ␉␊ |
164 | ␉/* get cpuid values */␊ |
165 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
166 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
167 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊ |
168 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊ |
169 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
170 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
171 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊ |
172 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
173 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
174 | ␉}␊ |
175 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊ |
176 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
177 | ␉}␊ |
178 | ␉␊ |
179 | #if DEBUG_CPU␊ |
180 | ␉{␊ |
181 | ␉␉int␉␉i;␊ |
182 | ␉␉printf("CPUID Raw Values:\n");␊ |
183 | ␉␉for (i=0; i<CPUID_MAX; i++) {␊ |
184 | ␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
185 | ␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
186 | ␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
187 | ␉␉}␊ |
188 | ␉}␊ |
189 | #endif␊ |
190 | ␉␊ |
191 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
192 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
193 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
194 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
195 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
196 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
197 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
198 | ␉␊ |
199 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
200 | ␉␊ |
201 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊ |
202 | ␉␉p->CPU.Family == 0x06 &&␊ |
203 | ␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊ |
204 | ␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
205 | ␉␉)␊ |
206 | ␉{␊ |
207 | ␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊ |
208 | ␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊ |
209 | ␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊ |
210 | ␉}␊ |
211 | ␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊ |
212 | ␉{␊ |
213 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
214 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
215 | ␉}␊ |
216 | ␉else␊ |
217 | ␉{␊ |
218 | ␉␉// Use previous method for Cores and Threads␊ |
219 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
220 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
221 | ␉}␊ |
222 | ␉␊ |
223 | ␉/* get brand string (if supported) */␊ |
224 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
225 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊ |
226 | ␉␉uint32_t␉reg[4];␊ |
227 | ␉␉char␉␉str[128], *s;␊ |
228 | ␉␉/*␊ |
229 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
230 | ␉␉ * be NULL terminated.␊ |
231 | ␉␉ */␊ |
232 | ␉␉do_cpuid(0x80000002, reg);␊ |
233 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
234 | ␉␉do_cpuid(0x80000003, reg);␊ |
235 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
236 | ␉␉do_cpuid(0x80000004, reg);␊ |
237 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
238 | ␉␉for (s = str; *s != '\0'; s++) {␊ |
239 | ␉␉␉if (*s != ' ') break;␊ |
240 | ␉␉}␊ |
241 | ␉␉␊ |
242 | ␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊ |
243 | ␉␉␊ |
244 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
245 | ␉␉␉/*␊ |
246 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
247 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
248 | ␉␉␉ */␊ |
249 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
250 | ␉␉}␊ |
251 | ␉}␊ |
252 | ␉␊ |
253 | ␉/* setup features */␊ |
254 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
255 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
256 | ␉}␊ |
257 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
258 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
259 | ␉}␊ |
260 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
261 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
262 | ␉}␊ |
263 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
264 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
265 | ␉}␊ |
266 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
267 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
268 | ␉}␊ |
269 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
270 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
271 | ␉}␊ |
272 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊ |
273 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
274 | ␉}␊ |
275 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
276 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
277 | ␉}␊ |
278 | ␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
279 | ␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊ |
280 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
281 | ␉}␊ |
282 | ␉␊ |
283 | ␉tscFrequency = measure_tsc_frequency();␊ |
284 | ␉fsbFrequency = 0;␊ |
285 | ␉cpuFrequency = 0;␊ |
286 | ␉␊ |
287 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊ |
288 | ␉␉int intelCPU = p->CPU.Model;␊ |
289 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊ |
290 | ␉␉␉/* Nehalem CPU model */␊ |
291 | ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM ||␊ |
292 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS ||␊ |
293 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES ||␊ |
294 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM ||␊ |
295 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE ||␊ |
296 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊ |
297 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊ |
298 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊ |
299 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN ||␊ |
300 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE)) {␊ |
301 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
302 | ␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
303 | ␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊ |
304 | ␉␉␉␉bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊ |
305 | ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
306 | ␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
307 | ␉␉␉␉if (bitfield(msr, 16, 16)) {␊ |
308 | ␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊ |
309 | ␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
310 | ␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
311 | ␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
312 | ␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
313 | ␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
314 | ␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
315 | ␉␉␉␉␉ is inadvertently set to 0.␊ |
316 | ␉␉␉␉␉ */␊ |
317 | ␉␉␉␉␉if (flex_ratio == 0) {␊ |
318 | ␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
319 | ␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
320 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
321 | ␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
322 | ␉␉␉␉␉} else {␊ |
323 | ␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊ |
324 | ␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
325 | ␉␉␉␉␉␉}␊ |
326 | ␉␉␉␉␉}␊ |
327 | ␉␉␉␉}␊ |
328 | ␉␉␉␉␊ |
329 | ␉␉␉␉if (bus_ratio_max) {␊ |
330 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
331 | ␉␉␉␉}␊ |
332 | ␉␉␉␉//valv: Turbo Ratio Limit␊ |
333 | ␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊ |
334 | ␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
335 | ␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
336 | ␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
337 | ␉␉␉␉} else {␊ |
338 | ␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
339 | ␉␉␉␉}␊ |
340 | ␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊ |
341 | ␉␉␉␉␉max_ratio = atoi(newratio);␊ |
342 | ␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
343 | ␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊ |
344 | ␉␉␉␉␉␊ |
345 | ␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
346 | ␉␉␉␉␉␊ |
347 | ␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
348 | ␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊ |
349 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
350 | ␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊ |
351 | ␉␉␉␉␉␉else maxdiv = 0;␊ |
352 | ␉␉␉␉␉} else {␊ |
353 | ␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
354 | ␉␉␉␉␉}␊ |
355 | ␉␉␉␉}␊ |
356 | ␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
357 | ␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
358 | ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
359 | ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
360 | ␉␉␉␉␊ |
361 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
362 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊ |
363 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
364 | ␉␉␉} else {␊ |
365 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
366 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
367 | ␉␉␉␉currcoef = bitfield(msr, 12, 8);␊ |
368 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
369 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
370 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
371 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
372 | ␉␉␉␉␊ |
373 | ␉␉␉␉// This will always be model >= 3␊ |
374 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
375 | ␉␉␉␉{␊ |
376 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
377 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
378 | ␉␉␉␉} else {␊ |
379 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
380 | ␉␉␉␉␉/* XXX */␊ |
381 | ␉␉␉␉␉maxcoef = currcoef;␊ |
382 | ␉␉␉␉}␊ |
383 | ␉␉␉␉␊ |
384 | ␉␉␉␉if (maxcoef) {␊ |
385 | ␉␉␉␉␉if (maxdiv) {␊ |
386 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
387 | ␉␉␉␉␉} else {␊ |
388 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
389 | ␉␉␉␉␉}␊ |
390 | ␉␉␉␉␉if (currdiv) {␊ |
391 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
392 | ␉␉␉␉␉} else {␊ |
393 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
394 | ␉␉␉␉␉}␊ |
395 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
396 | ␉␉␉␉}␊ |
397 | ␉␉␉}␊ |
398 | ␉␉}␊ |
399 | ␉␉/* Mobile CPU */␊ |
400 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊ |
401 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
402 | ␉␉}␊ |
403 | ␉}␊ |
404 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
405 | ␉{␊ |
406 | ␉␉switch(p->CPU.ExtFamily)␊ |
407 | ␉␉{␊ |
408 | ␉␉␉case 0x00: /* K8 */␊ |
409 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
410 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
411 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
412 | ␉␉␉␉break;␊ |
413 | ␉␉␉␉␊ |
414 | ␉␉␉case 0x01: /* K10 */␊ |
415 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
416 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
417 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
418 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
419 | ␉␉␉␉{␊ |
420 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
421 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
422 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
423 | ␉␉␉␉}␊ |
424 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
425 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
426 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
427 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
428 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
429 | ␉␉␉␉␊ |
430 | ␉␉␉␉break;␊ |
431 | ␉␉␉␉␊ |
432 | ␉␉␉case 0x05: /* K14 */␊ |
433 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
434 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
435 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
436 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
437 | ␉␉␉␉␊ |
438 | ␉␉␉␉break;␊ |
439 | ␉␉␉␉␊ |
440 | ␉␉␉case 0x02: /* K11 */␊ |
441 | ␉␉␉␉// not implimented␊ |
442 | ␉␉␉␉break;␊ |
443 | ␉␉}␊ |
444 | ␉␉␊ |
445 | ␉␉if (maxcoef)␊ |
446 | ␉␉{␊ |
447 | ␉␉␉if (currdiv)␊ |
448 | ␉␉␉{␊ |
449 | ␉␉␉␉if (!currcoef) currcoef = maxcoef;␊ |
450 | ␉␉␉␉if (!cpuFrequency)␊ |
451 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
452 | ␉␉␉␉else␊ |
453 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
454 | ␉␉␉␉␊ |
455 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
456 | ␉␉␉} else {␊ |
457 | ␉␉␉␉if (!cpuFrequency)␊ |
458 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
459 | ␉␉␉␉else ␊ |
460 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
461 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
462 | ␉␉␉}␊ |
463 | ␉␉}␊ |
464 | ␉␉else if (currcoef)␊ |
465 | ␉␉{␊ |
466 | ␉␉␉if (currdiv)␊ |
467 | ␉␉␉{␊ |
468 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
469 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
470 | ␉␉␉} else {␊ |
471 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
472 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
473 | ␉␉␉}␊ |
474 | ␉␉}␊ |
475 | ␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊ |
476 | ␉}␊ |
477 | ␉␊ |
478 | #if 0␊ |
479 | ␉if (!fsbFrequency) {␊ |
480 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
481 | ␉␉cpuFrequency = tscFrequency;␊ |
482 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
483 | ␉}␊ |
484 | #endif␊ |
485 | ␉␊ |
486 | ␉p->CPU.MaxCoef = maxcoef;␊ |
487 | ␉p->CPU.MaxDiv = maxdiv;␊ |
488 | ␉p->CPU.CurrCoef = currcoef;␊ |
489 | ␉p->CPU.CurrDiv = currdiv;␊ |
490 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
491 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
492 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
493 | ␉␊ |
494 | ␉// keep formatted with spaces instead of tabs␊ |
495 | ␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊ |
496 | DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊ |
497 | DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊ |
498 | DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊ |
499 | DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊ |
500 | DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
501 | DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
502 | DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
503 | DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
504 | DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
505 | #if DEBUG_CPU␊ |
506 | ␉pause();␊ |
507 | #endif␊ |
508 | }␊ |
509 | |